r300g: implement the texture barrier
[mesa.git] / src / gallium / drivers / r300 / r300_state.c
1 /*
2 * Copyright 2008 Corbin Simpson <MostAwesomeDude@gmail.com>
3 * Copyright 2009 Marek Olšák <maraeo@gmail.com>
4 *
5 * Permission is hereby granted, free of charge, to any person obtaining a
6 * copy of this software and associated documentation files (the "Software"),
7 * to deal in the Software without restriction, including without limitation
8 * on the rights to use, copy, modify, merge, publish, distribute, sub
9 * license, and/or sell copies of the Software, and to permit persons to whom
10 * the Software is furnished to do so, subject to the following conditions:
11 *
12 * The above copyright notice and this permission notice (including the next
13 * paragraph) shall be included in all copies or substantial portions of the
14 * Software.
15 *
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
19 * THE AUTHOR(S) AND/OR THEIR SUPPLIERS BE LIABLE FOR ANY CLAIM,
20 * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
21 * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
22 * USE OR OTHER DEALINGS IN THE SOFTWARE. */
23
24 #include "draw/draw_context.h"
25
26 #include "util/u_framebuffer.h"
27 #include "util/u_half.h"
28 #include "util/u_math.h"
29 #include "util/u_mm.h"
30 #include "util/u_memory.h"
31 #include "util/u_pack_color.h"
32 #include "util/u_transfer.h"
33
34 #include "tgsi/tgsi_parse.h"
35
36 #include "pipe/p_config.h"
37
38 #include "r300_cb.h"
39 #include "r300_context.h"
40 #include "r300_emit.h"
41 #include "r300_reg.h"
42 #include "r300_screen.h"
43 #include "r300_screen_buffer.h"
44 #include "r300_state_inlines.h"
45 #include "r300_fs.h"
46 #include "r300_texture.h"
47 #include "r300_vs.h"
48 #include "r300_winsys.h"
49
50 /* r300_state: Functions used to intialize state context by translating
51 * Gallium state objects into semi-native r300 state objects. */
52
53 #define UPDATE_STATE(cso, atom) \
54 if (cso != atom.state) { \
55 atom.state = cso; \
56 r300_mark_atom_dirty(r300, &(atom)); \
57 }
58
59 static boolean blend_discard_if_src_alpha_0(unsigned srcRGB, unsigned srcA,
60 unsigned dstRGB, unsigned dstA)
61 {
62 /* If the blend equation is ADD or REVERSE_SUBTRACT,
63 * SRC_ALPHA == 0, and the following state is set, the colorbuffer
64 * will not be changed.
65 * Notice that the dst factors are the src factors inverted. */
66 return (srcRGB == PIPE_BLENDFACTOR_SRC_ALPHA ||
67 srcRGB == PIPE_BLENDFACTOR_SRC_ALPHA_SATURATE ||
68 srcRGB == PIPE_BLENDFACTOR_ZERO) &&
69 (srcA == PIPE_BLENDFACTOR_SRC_COLOR ||
70 srcA == PIPE_BLENDFACTOR_SRC_ALPHA ||
71 srcA == PIPE_BLENDFACTOR_SRC_ALPHA_SATURATE ||
72 srcA == PIPE_BLENDFACTOR_ZERO) &&
73 (dstRGB == PIPE_BLENDFACTOR_INV_SRC_ALPHA ||
74 dstRGB == PIPE_BLENDFACTOR_ONE) &&
75 (dstA == PIPE_BLENDFACTOR_INV_SRC_COLOR ||
76 dstA == PIPE_BLENDFACTOR_INV_SRC_ALPHA ||
77 dstA == PIPE_BLENDFACTOR_ONE);
78 }
79
80 static boolean blend_discard_if_src_alpha_1(unsigned srcRGB, unsigned srcA,
81 unsigned dstRGB, unsigned dstA)
82 {
83 /* If the blend equation is ADD or REVERSE_SUBTRACT,
84 * SRC_ALPHA == 1, and the following state is set, the colorbuffer
85 * will not be changed.
86 * Notice that the dst factors are the src factors inverted. */
87 return (srcRGB == PIPE_BLENDFACTOR_INV_SRC_ALPHA ||
88 srcRGB == PIPE_BLENDFACTOR_ZERO) &&
89 (srcA == PIPE_BLENDFACTOR_INV_SRC_COLOR ||
90 srcA == PIPE_BLENDFACTOR_INV_SRC_ALPHA ||
91 srcA == PIPE_BLENDFACTOR_ZERO) &&
92 (dstRGB == PIPE_BLENDFACTOR_SRC_ALPHA ||
93 dstRGB == PIPE_BLENDFACTOR_ONE) &&
94 (dstA == PIPE_BLENDFACTOR_SRC_COLOR ||
95 dstA == PIPE_BLENDFACTOR_SRC_ALPHA ||
96 dstA == PIPE_BLENDFACTOR_ONE);
97 }
98
99 static boolean blend_discard_if_src_color_0(unsigned srcRGB, unsigned srcA,
100 unsigned dstRGB, unsigned dstA)
101 {
102 /* If the blend equation is ADD or REVERSE_SUBTRACT,
103 * SRC_COLOR == (0,0,0), and the following state is set, the colorbuffer
104 * will not be changed.
105 * Notice that the dst factors are the src factors inverted. */
106 return (srcRGB == PIPE_BLENDFACTOR_SRC_COLOR ||
107 srcRGB == PIPE_BLENDFACTOR_ZERO) &&
108 (srcA == PIPE_BLENDFACTOR_ZERO) &&
109 (dstRGB == PIPE_BLENDFACTOR_INV_SRC_COLOR ||
110 dstRGB == PIPE_BLENDFACTOR_ONE) &&
111 (dstA == PIPE_BLENDFACTOR_ONE);
112 }
113
114 static boolean blend_discard_if_src_color_1(unsigned srcRGB, unsigned srcA,
115 unsigned dstRGB, unsigned dstA)
116 {
117 /* If the blend equation is ADD or REVERSE_SUBTRACT,
118 * SRC_COLOR == (1,1,1), and the following state is set, the colorbuffer
119 * will not be changed.
120 * Notice that the dst factors are the src factors inverted. */
121 return (srcRGB == PIPE_BLENDFACTOR_INV_SRC_COLOR ||
122 srcRGB == PIPE_BLENDFACTOR_ZERO) &&
123 (srcA == PIPE_BLENDFACTOR_ZERO) &&
124 (dstRGB == PIPE_BLENDFACTOR_SRC_COLOR ||
125 dstRGB == PIPE_BLENDFACTOR_ONE) &&
126 (dstA == PIPE_BLENDFACTOR_ONE);
127 }
128
129 static boolean blend_discard_if_src_alpha_color_0(unsigned srcRGB, unsigned srcA,
130 unsigned dstRGB, unsigned dstA)
131 {
132 /* If the blend equation is ADD or REVERSE_SUBTRACT,
133 * SRC_ALPHA_COLOR == (0,0,0,0), and the following state is set,
134 * the colorbuffer will not be changed.
135 * Notice that the dst factors are the src factors inverted. */
136 return (srcRGB == PIPE_BLENDFACTOR_SRC_COLOR ||
137 srcRGB == PIPE_BLENDFACTOR_SRC_ALPHA ||
138 srcRGB == PIPE_BLENDFACTOR_SRC_ALPHA_SATURATE ||
139 srcRGB == PIPE_BLENDFACTOR_ZERO) &&
140 (srcA == PIPE_BLENDFACTOR_SRC_COLOR ||
141 srcA == PIPE_BLENDFACTOR_SRC_ALPHA ||
142 srcA == PIPE_BLENDFACTOR_SRC_ALPHA_SATURATE ||
143 srcA == PIPE_BLENDFACTOR_ZERO) &&
144 (dstRGB == PIPE_BLENDFACTOR_INV_SRC_COLOR ||
145 dstRGB == PIPE_BLENDFACTOR_INV_SRC_ALPHA ||
146 dstRGB == PIPE_BLENDFACTOR_ONE) &&
147 (dstA == PIPE_BLENDFACTOR_INV_SRC_COLOR ||
148 dstA == PIPE_BLENDFACTOR_INV_SRC_ALPHA ||
149 dstA == PIPE_BLENDFACTOR_ONE);
150 }
151
152 static boolean blend_discard_if_src_alpha_color_1(unsigned srcRGB, unsigned srcA,
153 unsigned dstRGB, unsigned dstA)
154 {
155 /* If the blend equation is ADD or REVERSE_SUBTRACT,
156 * SRC_ALPHA_COLOR == (1,1,1,1), and the following state is set,
157 * the colorbuffer will not be changed.
158 * Notice that the dst factors are the src factors inverted. */
159 return (srcRGB == PIPE_BLENDFACTOR_INV_SRC_COLOR ||
160 srcRGB == PIPE_BLENDFACTOR_INV_SRC_ALPHA ||
161 srcRGB == PIPE_BLENDFACTOR_ZERO) &&
162 (srcA == PIPE_BLENDFACTOR_INV_SRC_COLOR ||
163 srcA == PIPE_BLENDFACTOR_INV_SRC_ALPHA ||
164 srcA == PIPE_BLENDFACTOR_ZERO) &&
165 (dstRGB == PIPE_BLENDFACTOR_SRC_COLOR ||
166 dstRGB == PIPE_BLENDFACTOR_SRC_ALPHA ||
167 dstRGB == PIPE_BLENDFACTOR_ONE) &&
168 (dstA == PIPE_BLENDFACTOR_SRC_COLOR ||
169 dstA == PIPE_BLENDFACTOR_SRC_ALPHA ||
170 dstA == PIPE_BLENDFACTOR_ONE);
171 }
172
173 static unsigned bgra_cmask(unsigned mask)
174 {
175 /* Gallium uses RGBA color ordering while R300 expects BGRA. */
176
177 return ((mask & PIPE_MASK_R) << 2) |
178 ((mask & PIPE_MASK_B) >> 2) |
179 (mask & (PIPE_MASK_G | PIPE_MASK_A));
180 }
181
182 /* Create a new blend state based on the CSO blend state.
183 *
184 * This encompasses alpha blending, logic/raster ops, and blend dithering. */
185 static void* r300_create_blend_state(struct pipe_context* pipe,
186 const struct pipe_blend_state* state)
187 {
188 struct r300_screen* r300screen = r300_screen(pipe->screen);
189 struct r300_blend_state* blend = CALLOC_STRUCT(r300_blend_state);
190 uint32_t blend_control = 0; /* R300_RB3D_CBLEND: 0x4e04 */
191 uint32_t blend_control_noclamp = 0; /* R300_RB3D_CBLEND: 0x4e04 */
192 uint32_t alpha_blend_control = 0; /* R300_RB3D_ABLEND: 0x4e08 */
193 uint32_t alpha_blend_control_noclamp = 0; /* R300_RB3D_ABLEND: 0x4e08 */
194 uint32_t color_channel_mask = 0; /* R300_RB3D_COLOR_CHANNEL_MASK: 0x4e0c */
195 uint32_t rop = 0; /* R300_RB3D_ROPCNTL: 0x4e18 */
196 uint32_t dither = 0; /* R300_RB3D_DITHER_CTL: 0x4e50 */
197 CB_LOCALS;
198
199 blend->state = *state;
200
201 if (state->rt[0].blend_enable)
202 {
203 unsigned eqRGB = state->rt[0].rgb_func;
204 unsigned srcRGB = state->rt[0].rgb_src_factor;
205 unsigned dstRGB = state->rt[0].rgb_dst_factor;
206
207 unsigned eqA = state->rt[0].alpha_func;
208 unsigned srcA = state->rt[0].alpha_src_factor;
209 unsigned dstA = state->rt[0].alpha_dst_factor;
210
211 /* despite the name, ALPHA_BLEND_ENABLE has nothing to do with alpha,
212 * this is just the crappy D3D naming */
213 blend_control = blend_control_noclamp =
214 R300_ALPHA_BLEND_ENABLE |
215 ( r300_translate_blend_factor(srcRGB) << R300_SRC_BLEND_SHIFT) |
216 ( r300_translate_blend_factor(dstRGB) << R300_DST_BLEND_SHIFT);
217 blend_control |=
218 r300_translate_blend_function(eqRGB, TRUE);
219 blend_control_noclamp |=
220 r300_translate_blend_function(eqRGB, FALSE);
221
222 /* Optimization: some operations do not require the destination color.
223 *
224 * When SRC_ALPHA_SATURATE is used, colorbuffer reads must be enabled,
225 * otherwise blending gives incorrect results. It seems to be
226 * a hardware bug. */
227 if (eqRGB == PIPE_BLEND_MIN || eqA == PIPE_BLEND_MIN ||
228 eqRGB == PIPE_BLEND_MAX || eqA == PIPE_BLEND_MAX ||
229 dstRGB != PIPE_BLENDFACTOR_ZERO ||
230 dstA != PIPE_BLENDFACTOR_ZERO ||
231 srcRGB == PIPE_BLENDFACTOR_DST_COLOR ||
232 srcRGB == PIPE_BLENDFACTOR_DST_ALPHA ||
233 srcRGB == PIPE_BLENDFACTOR_INV_DST_COLOR ||
234 srcRGB == PIPE_BLENDFACTOR_INV_DST_ALPHA ||
235 srcA == PIPE_BLENDFACTOR_DST_COLOR ||
236 srcA == PIPE_BLENDFACTOR_DST_ALPHA ||
237 srcA == PIPE_BLENDFACTOR_INV_DST_COLOR ||
238 srcA == PIPE_BLENDFACTOR_INV_DST_ALPHA ||
239 srcRGB == PIPE_BLENDFACTOR_SRC_ALPHA_SATURATE) {
240 /* Enable reading from the colorbuffer. */
241 blend_control |= R300_READ_ENABLE;
242 blend_control_noclamp |= R300_READ_ENABLE;
243
244 if (r300screen->caps.is_r500) {
245 /* Optimization: Depending on incoming pixels, we can
246 * conditionally disable the reading in hardware... */
247 if (eqRGB != PIPE_BLEND_MIN && eqA != PIPE_BLEND_MIN &&
248 eqRGB != PIPE_BLEND_MAX && eqA != PIPE_BLEND_MAX) {
249 /* Disable reading if SRC_ALPHA == 0. */
250 if ((dstRGB == PIPE_BLENDFACTOR_SRC_ALPHA ||
251 dstRGB == PIPE_BLENDFACTOR_ZERO) &&
252 (dstA == PIPE_BLENDFACTOR_SRC_COLOR ||
253 dstA == PIPE_BLENDFACTOR_SRC_ALPHA ||
254 dstA == PIPE_BLENDFACTOR_ZERO)) {
255 blend_control |= R500_SRC_ALPHA_0_NO_READ;
256 }
257
258 /* Disable reading if SRC_ALPHA == 1. */
259 if ((dstRGB == PIPE_BLENDFACTOR_INV_SRC_ALPHA ||
260 dstRGB == PIPE_BLENDFACTOR_ZERO) &&
261 (dstA == PIPE_BLENDFACTOR_INV_SRC_COLOR ||
262 dstA == PIPE_BLENDFACTOR_INV_SRC_ALPHA ||
263 dstA == PIPE_BLENDFACTOR_ZERO)) {
264 blend_control |= R500_SRC_ALPHA_1_NO_READ;
265 }
266 }
267 }
268 }
269
270 /* Optimization: discard pixels which don't change the colorbuffer.
271 *
272 * The code below is non-trivial and some math is involved.
273 *
274 * Discarding pixels must be disabled when FP16 AA is enabled.
275 * This is a hardware bug. Also, this implementation wouldn't work
276 * with FP blending enabled and equation clamping disabled.
277 *
278 * Equations other than ADD are rarely used and therefore won't be
279 * optimized. */
280 if ((eqRGB == PIPE_BLEND_ADD || eqRGB == PIPE_BLEND_REVERSE_SUBTRACT) &&
281 (eqA == PIPE_BLEND_ADD || eqA == PIPE_BLEND_REVERSE_SUBTRACT)) {
282 /* ADD: X+Y
283 * REVERSE_SUBTRACT: Y-X
284 *
285 * The idea is:
286 * If X = src*srcFactor = 0 and Y = dst*dstFactor = 1,
287 * then CB will not be changed.
288 *
289 * Given the srcFactor and dstFactor variables, we can derive
290 * what src and dst should be equal to and discard appropriate
291 * pixels.
292 */
293 if (blend_discard_if_src_alpha_0(srcRGB, srcA, dstRGB, dstA)) {
294 blend_control |= R300_DISCARD_SRC_PIXELS_SRC_ALPHA_0;
295 } else if (blend_discard_if_src_alpha_1(srcRGB, srcA,
296 dstRGB, dstA)) {
297 blend_control |= R300_DISCARD_SRC_PIXELS_SRC_ALPHA_1;
298 } else if (blend_discard_if_src_color_0(srcRGB, srcA,
299 dstRGB, dstA)) {
300 blend_control |= R300_DISCARD_SRC_PIXELS_SRC_COLOR_0;
301 } else if (blend_discard_if_src_color_1(srcRGB, srcA,
302 dstRGB, dstA)) {
303 blend_control |= R300_DISCARD_SRC_PIXELS_SRC_COLOR_1;
304 } else if (blend_discard_if_src_alpha_color_0(srcRGB, srcA,
305 dstRGB, dstA)) {
306 blend_control |=
307 R300_DISCARD_SRC_PIXELS_SRC_ALPHA_COLOR_0;
308 } else if (blend_discard_if_src_alpha_color_1(srcRGB, srcA,
309 dstRGB, dstA)) {
310 blend_control |=
311 R300_DISCARD_SRC_PIXELS_SRC_ALPHA_COLOR_1;
312 }
313 }
314
315 /* separate alpha */
316 if (srcA != srcRGB || dstA != dstRGB || eqA != eqRGB) {
317 blend_control |= R300_SEPARATE_ALPHA_ENABLE;
318 blend_control_noclamp |= R300_SEPARATE_ALPHA_ENABLE;
319 alpha_blend_control = alpha_blend_control_noclamp =
320 (r300_translate_blend_factor(srcA) << R300_SRC_BLEND_SHIFT) |
321 (r300_translate_blend_factor(dstA) << R300_DST_BLEND_SHIFT);
322 alpha_blend_control |=
323 r300_translate_blend_function(eqA, TRUE);
324 alpha_blend_control_noclamp |=
325 r300_translate_blend_function(eqA, FALSE);
326 }
327 }
328
329 /* PIPE_LOGICOP_* don't need to be translated, fortunately. */
330 if (state->logicop_enable) {
331 rop = R300_RB3D_ROPCNTL_ROP_ENABLE |
332 (state->logicop_func) << R300_RB3D_ROPCNTL_ROP_SHIFT;
333 }
334
335 /* Color channel masks for all MRTs. */
336 color_channel_mask = bgra_cmask(state->rt[0].colormask);
337 if (r300screen->caps.is_r500 && state->independent_blend_enable) {
338 if (state->rt[1].blend_enable) {
339 color_channel_mask |= bgra_cmask(state->rt[1].colormask) << 4;
340 }
341 if (state->rt[2].blend_enable) {
342 color_channel_mask |= bgra_cmask(state->rt[2].colormask) << 8;
343 }
344 if (state->rt[3].blend_enable) {
345 color_channel_mask |= bgra_cmask(state->rt[3].colormask) << 12;
346 }
347 }
348
349 /* Neither fglrx nor classic r300 ever set this, regardless of dithering
350 * state. Since it's an optional implementation detail, we can leave it
351 * out and never dither.
352 *
353 * This could be revisited if we ever get quality or conformance hints.
354 *
355 if (state->dither) {
356 dither = R300_RB3D_DITHER_CTL_DITHER_MODE_LUT |
357 R300_RB3D_DITHER_CTL_ALPHA_DITHER_MODE_LUT;
358 }
359 */
360
361 /* Build a command buffer. */
362 BEGIN_CB(blend->cb_clamp, 8);
363 OUT_CB_REG(R300_RB3D_ROPCNTL, rop);
364 OUT_CB_REG_SEQ(R300_RB3D_CBLEND, 3);
365 OUT_CB(blend_control);
366 OUT_CB(alpha_blend_control);
367 OUT_CB(color_channel_mask);
368 OUT_CB_REG(R300_RB3D_DITHER_CTL, dither);
369 END_CB;
370
371 /* Build a command buffer. */
372 BEGIN_CB(blend->cb_noclamp, 8);
373 OUT_CB_REG(R300_RB3D_ROPCNTL, rop);
374 OUT_CB_REG_SEQ(R300_RB3D_CBLEND, 3);
375 OUT_CB(blend_control_noclamp);
376 OUT_CB(alpha_blend_control_noclamp);
377 OUT_CB(color_channel_mask);
378 OUT_CB_REG(R300_RB3D_DITHER_CTL, dither);
379 END_CB;
380
381 /* The same as above, but with no colorbuffer reads and writes. */
382 BEGIN_CB(blend->cb_no_readwrite, 8);
383 OUT_CB_REG(R300_RB3D_ROPCNTL, rop);
384 OUT_CB_REG_SEQ(R300_RB3D_CBLEND, 3);
385 OUT_CB(0);
386 OUT_CB(0);
387 OUT_CB(0);
388 OUT_CB_REG(R300_RB3D_DITHER_CTL, dither);
389 END_CB;
390
391 return (void*)blend;
392 }
393
394 /* Bind blend state. */
395 static void r300_bind_blend_state(struct pipe_context* pipe,
396 void* state)
397 {
398 struct r300_context* r300 = r300_context(pipe);
399
400 UPDATE_STATE(state, r300->blend_state);
401
402 if (r300->fs.state && r300_pick_fragment_shader(r300)) {
403 r300_mark_fs_code_dirty(r300);
404 }
405 }
406
407 /* Free blend state. */
408 static void r300_delete_blend_state(struct pipe_context* pipe,
409 void* state)
410 {
411 FREE(state);
412 }
413
414 /* Convert float to 10bit integer */
415 static unsigned float_to_fixed10(float f)
416 {
417 return CLAMP((unsigned)(f * 1023.9f), 0, 1023);
418 }
419
420 /* Set blend color.
421 * Setup both R300 and R500 registers, figure out later which one to write. */
422 static void r300_set_blend_color(struct pipe_context* pipe,
423 const struct pipe_blend_color* color)
424 {
425 struct r300_context* r300 = r300_context(pipe);
426 struct pipe_framebuffer_state *fb = r300->fb_state.state;
427 struct r300_blend_color_state *state =
428 (struct r300_blend_color_state*)r300->blend_color_state.state;
429 struct pipe_blend_color c;
430 enum pipe_format format = fb->nr_cbufs ? fb->cbufs[0]->format : 0;
431 CB_LOCALS;
432
433 state->state = *color; /* Save it, so that we can reuse it in set_fb_state */
434 c = *color;
435
436 /* The blend color is dependent on the colorbuffer format. */
437 if (fb->nr_cbufs) {
438 switch (format) {
439 case PIPE_FORMAT_R8_UNORM:
440 case PIPE_FORMAT_L8_UNORM:
441 case PIPE_FORMAT_I8_UNORM:
442 c.color[1] = c.color[0];
443 break;
444
445 case PIPE_FORMAT_A8_UNORM:
446 c.color[1] = c.color[3];
447 break;
448
449 case PIPE_FORMAT_R8G8_UNORM:
450 c.color[2] = c.color[1];
451 break;
452
453 case PIPE_FORMAT_L8A8_UNORM:
454 c.color[2] = c.color[3];
455 break;
456
457 default:;
458 }
459 }
460
461 if (r300->screen->caps.is_r500) {
462 BEGIN_CB(state->cb, 3);
463 OUT_CB_REG_SEQ(R500_RB3D_CONSTANT_COLOR_AR, 2);
464
465 switch (format) {
466 case PIPE_FORMAT_R16G16B16A16_FLOAT:
467 OUT_CB(util_float_to_half(c.color[2]) |
468 (util_float_to_half(c.color[3]) << 16));
469 OUT_CB(util_float_to_half(c.color[0]) |
470 (util_float_to_half(c.color[1]) << 16));
471 break;
472
473 default:
474 OUT_CB(float_to_fixed10(c.color[0]) |
475 (float_to_fixed10(c.color[3]) << 16));
476 OUT_CB(float_to_fixed10(c.color[2]) |
477 (float_to_fixed10(c.color[1]) << 16));
478 }
479
480 END_CB;
481 } else {
482 union util_color uc;
483 util_pack_color(c.color, PIPE_FORMAT_B8G8R8A8_UNORM, &uc);
484
485 BEGIN_CB(state->cb, 2);
486 OUT_CB_REG(R300_RB3D_BLEND_COLOR, uc.ui);
487 END_CB;
488 }
489
490 r300_mark_atom_dirty(r300, &r300->blend_color_state);
491 }
492
493 static void r300_set_clip_state(struct pipe_context* pipe,
494 const struct pipe_clip_state* state)
495 {
496 struct r300_context* r300 = r300_context(pipe);
497 struct r300_clip_state *clip =
498 (struct r300_clip_state*)r300->clip_state.state;
499 CB_LOCALS;
500
501 clip->clip = *state;
502
503 if (r300->screen->caps.has_tcl) {
504 r300->clip_state.size = 2 + !!state->nr * 3 + state->nr * 4;
505
506 BEGIN_CB(clip->cb, r300->clip_state.size);
507 if (state->nr) {
508 OUT_CB_REG(R300_VAP_PVS_VECTOR_INDX_REG,
509 (r300->screen->caps.is_r500 ?
510 R500_PVS_UCP_START : R300_PVS_UCP_START));
511 OUT_CB_ONE_REG(R300_VAP_PVS_UPLOAD_DATA, state->nr * 4);
512 OUT_CB_TABLE(state->ucp, state->nr * 4);
513 }
514 OUT_CB_REG(R300_VAP_CLIP_CNTL, ((1 << state->nr) - 1) |
515 R300_PS_UCP_MODE_CLIP_AS_TRIFAN);
516 END_CB;
517
518 r300_mark_atom_dirty(r300, &r300->clip_state);
519 } else {
520 draw_set_clip_state(r300->draw, state);
521 }
522 }
523
524 static void
525 r300_set_sample_mask(struct pipe_context *pipe,
526 unsigned sample_mask)
527 {
528 }
529
530
531 /* Create a new depth, stencil, and alpha state based on the CSO dsa state.
532 *
533 * This contains the depth buffer, stencil buffer, alpha test, and such.
534 * On the Radeon, depth and stencil buffer setup are intertwined, which is
535 * the reason for some of the strange-looking assignments across registers. */
536 static void*
537 r300_create_dsa_state(struct pipe_context* pipe,
538 const struct pipe_depth_stencil_alpha_state* state)
539 {
540 struct r300_capabilities *caps = &r300_screen(pipe->screen)->caps;
541 struct r300_dsa_state* dsa = CALLOC_STRUCT(r300_dsa_state);
542 CB_LOCALS;
543
544 dsa->dsa = *state;
545
546 /* Depth test setup. - separate write mask depth for decomp flush */
547 if (state->depth.writemask) {
548 dsa->z_buffer_control |= R300_Z_WRITE_ENABLE;
549 }
550
551 if (state->depth.enabled) {
552 dsa->z_buffer_control |= R300_Z_ENABLE;
553
554 dsa->z_stencil_control |=
555 (r300_translate_depth_stencil_function(state->depth.func) <<
556 R300_Z_FUNC_SHIFT);
557 }
558
559 /* Stencil buffer setup. */
560 if (state->stencil[0].enabled) {
561 dsa->z_buffer_control |= R300_STENCIL_ENABLE;
562 dsa->z_stencil_control |=
563 (r300_translate_depth_stencil_function(state->stencil[0].func) <<
564 R300_S_FRONT_FUNC_SHIFT) |
565 (r300_translate_stencil_op(state->stencil[0].fail_op) <<
566 R300_S_FRONT_SFAIL_OP_SHIFT) |
567 (r300_translate_stencil_op(state->stencil[0].zpass_op) <<
568 R300_S_FRONT_ZPASS_OP_SHIFT) |
569 (r300_translate_stencil_op(state->stencil[0].zfail_op) <<
570 R300_S_FRONT_ZFAIL_OP_SHIFT);
571
572 dsa->stencil_ref_mask =
573 (state->stencil[0].valuemask << R300_STENCILMASK_SHIFT) |
574 (state->stencil[0].writemask << R300_STENCILWRITEMASK_SHIFT);
575
576 if (state->stencil[1].enabled) {
577 dsa->two_sided = TRUE;
578
579 dsa->z_buffer_control |= R300_STENCIL_FRONT_BACK;
580 dsa->z_stencil_control |=
581 (r300_translate_depth_stencil_function(state->stencil[1].func) <<
582 R300_S_BACK_FUNC_SHIFT) |
583 (r300_translate_stencil_op(state->stencil[1].fail_op) <<
584 R300_S_BACK_SFAIL_OP_SHIFT) |
585 (r300_translate_stencil_op(state->stencil[1].zpass_op) <<
586 R300_S_BACK_ZPASS_OP_SHIFT) |
587 (r300_translate_stencil_op(state->stencil[1].zfail_op) <<
588 R300_S_BACK_ZFAIL_OP_SHIFT);
589
590 dsa->stencil_ref_bf =
591 (state->stencil[1].valuemask << R300_STENCILMASK_SHIFT) |
592 (state->stencil[1].writemask << R300_STENCILWRITEMASK_SHIFT);
593
594 if (caps->is_r500) {
595 dsa->z_buffer_control |= R500_STENCIL_REFMASK_FRONT_BACK;
596 } else {
597 dsa->two_sided_stencil_ref =
598 (state->stencil[0].valuemask != state->stencil[1].valuemask ||
599 state->stencil[0].writemask != state->stencil[1].writemask);
600 }
601 }
602 }
603
604 /* Alpha test setup. */
605 if (state->alpha.enabled) {
606 dsa->alpha_function =
607 r300_translate_alpha_function(state->alpha.func) |
608 R300_FG_ALPHA_FUNC_ENABLE;
609
610 dsa->alpha_function |= float_to_ubyte(state->alpha.ref_value);
611 dsa->alpha_value = util_float_to_half(state->alpha.ref_value);
612
613 if (caps->is_r500) {
614 dsa->alpha_function_fp16 = dsa->alpha_function |
615 R500_FG_ALPHA_FUNC_FP16_ENABLE;
616 dsa->alpha_function |= R500_FG_ALPHA_FUNC_8BIT;
617 }
618 }
619
620 BEGIN_CB(&dsa->cb_begin, 10);
621 OUT_CB_REG(R300_FG_ALPHA_FUNC, dsa->alpha_function);
622 OUT_CB_REG_SEQ(R300_ZB_CNTL, 3);
623 OUT_CB(dsa->z_buffer_control);
624 OUT_CB(dsa->z_stencil_control);
625 OUT_CB(dsa->stencil_ref_mask);
626 OUT_CB_REG(R500_ZB_STENCILREFMASK_BF, dsa->stencil_ref_bf);
627 OUT_CB_REG(R500_FG_ALPHA_VALUE, dsa->alpha_value);
628 END_CB;
629
630 BEGIN_CB(&dsa->cb_begin_fp16, 10);
631 OUT_CB_REG(R300_FG_ALPHA_FUNC, dsa->alpha_function_fp16);
632 OUT_CB_REG_SEQ(R300_ZB_CNTL, 3);
633 OUT_CB(dsa->z_buffer_control);
634 OUT_CB(dsa->z_stencil_control);
635 OUT_CB(dsa->stencil_ref_mask);
636 OUT_CB_REG(R500_ZB_STENCILREFMASK_BF, dsa->stencil_ref_bf);
637 OUT_CB_REG(R500_FG_ALPHA_VALUE, dsa->alpha_value);
638 END_CB;
639
640 BEGIN_CB(dsa->cb_zb_no_readwrite, 10);
641 OUT_CB_REG(R300_FG_ALPHA_FUNC, dsa->alpha_function);
642 OUT_CB_REG_SEQ(R300_ZB_CNTL, 3);
643 OUT_CB(0);
644 OUT_CB(0);
645 OUT_CB(0);
646 OUT_CB_REG(R500_ZB_STENCILREFMASK_BF, 0);
647 OUT_CB_REG(R500_FG_ALPHA_VALUE, dsa->alpha_value);
648 END_CB;
649
650 BEGIN_CB(dsa->cb_fp16_zb_no_readwrite, 10);
651 OUT_CB_REG(R300_FG_ALPHA_FUNC, dsa->alpha_function_fp16);
652 OUT_CB_REG_SEQ(R300_ZB_CNTL, 3);
653 OUT_CB(0);
654 OUT_CB(0);
655 OUT_CB(0);
656 OUT_CB_REG(R500_ZB_STENCILREFMASK_BF, 0);
657 OUT_CB_REG(R500_FG_ALPHA_VALUE, dsa->alpha_value);
658 END_CB;
659
660 return (void*)dsa;
661 }
662
663 static void r300_dsa_inject_stencilref(struct r300_context *r300)
664 {
665 struct r300_dsa_state *dsa =
666 (struct r300_dsa_state*)r300->dsa_state.state;
667
668 if (!dsa)
669 return;
670
671 dsa->stencil_ref_mask =
672 (dsa->stencil_ref_mask & ~R300_STENCILREF_MASK) |
673 r300->stencil_ref.ref_value[0];
674 dsa->stencil_ref_bf =
675 (dsa->stencil_ref_bf & ~R300_STENCILREF_MASK) |
676 r300->stencil_ref.ref_value[1];
677 }
678
679 /* Bind DSA state. */
680 static void r300_bind_dsa_state(struct pipe_context* pipe,
681 void* state)
682 {
683 struct r300_context* r300 = r300_context(pipe);
684
685 if (!state) {
686 return;
687 }
688
689 UPDATE_STATE(state, r300->dsa_state);
690
691 r300_mark_atom_dirty(r300, &r300->hyperz_state); /* Will be updated before the emission. */
692 r300_dsa_inject_stencilref(r300);
693 }
694
695 /* Free DSA state. */
696 static void r300_delete_dsa_state(struct pipe_context* pipe,
697 void* state)
698 {
699 FREE(state);
700 }
701
702 static void r300_set_stencil_ref(struct pipe_context* pipe,
703 const struct pipe_stencil_ref* sr)
704 {
705 struct r300_context* r300 = r300_context(pipe);
706
707 r300->stencil_ref = *sr;
708
709 r300_dsa_inject_stencilref(r300);
710 r300_mark_atom_dirty(r300, &r300->dsa_state);
711 }
712
713 static void r300_tex_set_tiling_flags(struct r300_context *r300,
714 struct r300_resource *tex,
715 unsigned level)
716 {
717 /* Check if the macrotile flag needs to be changed.
718 * Skip changing the flags otherwise. */
719 if (tex->tex.macrotile[tex->surface_level] !=
720 tex->tex.macrotile[level]) {
721 r300->rws->buffer_set_tiling(tex->buf, r300->cs,
722 tex->tex.microtile, tex->tex.macrotile[level],
723 tex->tex.stride_in_bytes[0]);
724
725 tex->surface_level = level;
726 }
727 }
728
729 /* This switcheroo is needed just because of goddamned MACRO_SWITCH. */
730 static void r300_fb_set_tiling_flags(struct r300_context *r300,
731 const struct pipe_framebuffer_state *state)
732 {
733 unsigned i;
734
735 /* Set tiling flags for new surfaces. */
736 for (i = 0; i < state->nr_cbufs; i++) {
737 r300_tex_set_tiling_flags(r300,
738 r300_resource(state->cbufs[i]->texture),
739 state->cbufs[i]->u.tex.level);
740 }
741 if (state->zsbuf) {
742 r300_tex_set_tiling_flags(r300,
743 r300_resource(state->zsbuf->texture),
744 state->zsbuf->u.tex.level);
745 }
746 }
747
748 static void r300_print_fb_surf_info(struct pipe_surface *surf, unsigned index,
749 const char *binding)
750 {
751 struct pipe_resource *tex = surf->texture;
752 struct r300_resource *rtex = r300_resource(tex);
753
754 fprintf(stderr,
755 "r300: %s[%i] Dim: %ix%i, Firstlayer: %i, "
756 "Lastlayer: %i, Level: %i, Format: %s\n"
757
758 "r300: TEX: Macro: %s, Micro: %s, Pitch: %i, "
759 "Dim: %ix%ix%i, LastLevel: %i, Format: %s\n",
760
761 binding, index, surf->width, surf->height,
762 surf->u.tex.first_layer, surf->u.tex.last_layer, surf->u.tex.level,
763 util_format_short_name(surf->format),
764
765 rtex->tex.macrotile[0] ? "YES" : " NO",
766 rtex->tex.microtile ? "YES" : " NO",
767 rtex->tex.stride_in_pixels[0],
768 tex->width0, tex->height0, tex->depth0,
769 tex->last_level, util_format_short_name(tex->format));
770 }
771
772 void r300_mark_fb_state_dirty(struct r300_context *r300,
773 enum r300_fb_state_change change)
774 {
775 struct pipe_framebuffer_state *state = r300->fb_state.state;
776 boolean can_hyperz = r300->rws->get_value(r300->rws, R300_CAN_HYPERZ);
777
778 r300_mark_atom_dirty(r300, &r300->gpu_flush);
779 r300_mark_atom_dirty(r300, &r300->fb_state);
780
781 /* What is marked as dirty depends on the enum r300_fb_state_change. */
782 if (change == R300_CHANGED_FB_STATE) {
783 r300_mark_atom_dirty(r300, &r300->aa_state);
784 r300_mark_atom_dirty(r300, &r300->dsa_state); /* for AlphaRef */
785 r300_set_blend_color(&r300->context, r300->blend_color_state.state);
786 }
787
788 if (change == R300_CHANGED_FB_STATE ||
789 change == R300_CHANGED_HYPERZ_FLAG) {
790 r300_mark_atom_dirty(r300, &r300->hyperz_state);
791 }
792
793 if (change == R300_CHANGED_FB_STATE ||
794 change == R300_CHANGED_MULTIWRITE) {
795 r300_mark_atom_dirty(r300, &r300->fb_state_pipelined);
796 }
797
798 /* Now compute the fb_state atom size. */
799 r300->fb_state.size = 2 + (8 * state->nr_cbufs);
800
801 if (r300->cbzb_clear)
802 r300->fb_state.size += 10;
803 else if (state->zsbuf) {
804 r300->fb_state.size += 10;
805 if (can_hyperz)
806 r300->fb_state.size += 8;
807 }
808
809 /* The size of the rest of atoms stays the same. */
810 }
811
812 static void
813 r300_set_framebuffer_state(struct pipe_context* pipe,
814 const struct pipe_framebuffer_state* state)
815 {
816 struct r300_context* r300 = r300_context(pipe);
817 struct r300_aa_state *aa = (struct r300_aa_state*)r300->aa_state.state;
818 struct pipe_framebuffer_state *old_state = r300->fb_state.state;
819 unsigned max_width, max_height, i;
820 uint32_t zbuffer_bpp = 0;
821
822 if (r300->screen->caps.is_r500) {
823 max_width = max_height = 4096;
824 } else if (r300->screen->caps.is_r400) {
825 max_width = max_height = 4021;
826 } else {
827 max_width = max_height = 2560;
828 }
829
830 if (state->width > max_width || state->height > max_height) {
831 fprintf(stderr, "r300: Implementation error: Render targets are too "
832 "big in %s, refusing to bind framebuffer state!\n", __FUNCTION__);
833 return;
834 }
835
836 if (old_state->zsbuf && r300->zmask_in_use && !r300->hyperz_locked) {
837 /* There is a zmask in use, what are we gonna do? */
838 if (state->zsbuf) {
839 if (!pipe_surface_equal(old_state->zsbuf, state->zsbuf)) {
840 /* Decompress the currently bound zbuffer before we bind another one. */
841 r300_decompress_zmask(r300);
842 r300->hiz_in_use = FALSE;
843 }
844 } else {
845 /* We don't bind another zbuffer, so lock the current one. */
846 r300->hyperz_locked = TRUE;
847 pipe_surface_reference(&r300->locked_zbuffer, old_state->zsbuf);
848 }
849 } else if (r300->hyperz_locked && r300->locked_zbuffer) {
850 /* We have a locked zbuffer now, what are we gonna do? */
851 if (state->zsbuf) {
852 if (!pipe_surface_equal(r300->locked_zbuffer, state->zsbuf)) {
853 /* We are binding some other zbuffer, so decompress the locked one,
854 * it gets unlocked automatically. */
855 r300_decompress_zmask_locked_unsafe(r300);
856 r300->hiz_in_use = FALSE;
857 } else {
858 /* We are binding the locked zbuffer again, so unlock it. */
859 r300->hyperz_locked = FALSE;
860 }
861 }
862 }
863
864 /* Need to reset clamping or colormask. */
865 r300_mark_atom_dirty(r300, &r300->blend_state);
866
867 /* If zsbuf is set from NULL to non-NULL or vice versa.. */
868 if (!!old_state->zsbuf != !!state->zsbuf) {
869 r300_mark_atom_dirty(r300, &r300->dsa_state);
870 }
871
872 /* The tiling flags are dependent on the surface miplevel, unfortunately. */
873 r300_fb_set_tiling_flags(r300, state);
874
875 util_copy_framebuffer_state(r300->fb_state.state, state);
876
877 if (!r300->hyperz_locked) {
878 pipe_surface_reference(&r300->locked_zbuffer, NULL);
879 }
880
881 r300_mark_fb_state_dirty(r300, R300_CHANGED_FB_STATE);
882
883 if (state->zsbuf) {
884 switch (util_format_get_blocksize(state->zsbuf->texture->format)) {
885 case 2:
886 zbuffer_bpp = 16;
887 break;
888 case 4:
889 zbuffer_bpp = 24;
890 break;
891 }
892
893 /* Polygon offset depends on the zbuffer bit depth. */
894 if (r300->zbuffer_bpp != zbuffer_bpp) {
895 r300->zbuffer_bpp = zbuffer_bpp;
896
897 if (r300->polygon_offset_enabled)
898 r300_mark_atom_dirty(r300, &r300->rs_state);
899 }
900 }
901
902 /* Set up AA config. */
903 if (state->nr_cbufs && state->cbufs[0]->texture->nr_samples > 1) {
904 aa->aa_config = R300_GB_AA_CONFIG_AA_ENABLE;
905
906 switch (state->cbufs[0]->texture->nr_samples) {
907 case 2:
908 aa->aa_config |= R300_GB_AA_CONFIG_NUM_AA_SUBSAMPLES_2;
909 break;
910 case 3:
911 aa->aa_config |= R300_GB_AA_CONFIG_NUM_AA_SUBSAMPLES_3;
912 break;
913 case 4:
914 aa->aa_config |= R300_GB_AA_CONFIG_NUM_AA_SUBSAMPLES_4;
915 break;
916 case 6:
917 aa->aa_config |= R300_GB_AA_CONFIG_NUM_AA_SUBSAMPLES_6;
918 break;
919 }
920 } else {
921 aa->aa_config = 0;
922 }
923
924 if (DBG_ON(r300, DBG_FB)) {
925 fprintf(stderr, "r300: set_framebuffer_state:\n");
926 for (i = 0; i < state->nr_cbufs; i++) {
927 r300_print_fb_surf_info(state->cbufs[i], i, "CB");
928 }
929 if (state->zsbuf) {
930 r300_print_fb_surf_info(state->zsbuf, 0, "ZB");
931 }
932 }
933 }
934
935 /* Create fragment shader state. */
936 static void* r300_create_fs_state(struct pipe_context* pipe,
937 const struct pipe_shader_state* shader)
938 {
939 struct r300_fragment_shader* fs = NULL;
940
941 fs = (struct r300_fragment_shader*)CALLOC_STRUCT(r300_fragment_shader);
942
943 /* Copy state directly into shader. */
944 fs->state = *shader;
945 fs->state.tokens = tgsi_dup_tokens(shader->tokens);
946
947 return (void*)fs;
948 }
949
950 void r300_mark_fs_code_dirty(struct r300_context *r300)
951 {
952 struct r300_fragment_shader* fs = r300_fs(r300);
953
954 r300_mark_atom_dirty(r300, &r300->fs);
955 r300_mark_atom_dirty(r300, &r300->fs_rc_constant_state);
956 r300_mark_atom_dirty(r300, &r300->fs_constants);
957 r300->fs.size = fs->shader->cb_code_size;
958
959 if (r300->screen->caps.is_r500) {
960 r300->fs_rc_constant_state.size = fs->shader->rc_state_count * 7;
961 r300->fs_constants.size = fs->shader->externals_count * 4 + 3;
962 } else {
963 r300->fs_rc_constant_state.size = fs->shader->rc_state_count * 5;
964 r300->fs_constants.size = fs->shader->externals_count * 4 + 1;
965 }
966
967 ((struct r300_constant_buffer*)r300->fs_constants.state)->remap_table =
968 fs->shader->code.constants_remap_table;
969 }
970
971 /* Bind fragment shader state. */
972 static void r300_bind_fs_state(struct pipe_context* pipe, void* shader)
973 {
974 struct r300_context* r300 = r300_context(pipe);
975 struct r300_fragment_shader* fs = (struct r300_fragment_shader*)shader;
976 struct pipe_framebuffer_state *fb = r300->fb_state.state;
977 boolean last_multi_write;
978
979 if (fs == NULL) {
980 r300->fs.state = NULL;
981 return;
982 }
983
984 last_multi_write = r300_fragment_shader_writes_all(r300_fs(r300));
985
986 r300->fs.state = fs;
987 r300_pick_fragment_shader(r300);
988 r300_mark_fs_code_dirty(r300);
989
990 if (fb->nr_cbufs > 1 &&
991 last_multi_write != r300_fragment_shader_writes_all(fs)) {
992 r300_mark_fb_state_dirty(r300, R300_CHANGED_MULTIWRITE);
993 }
994
995 r300_mark_atom_dirty(r300, &r300->rs_block_state); /* Will be updated before the emission. */
996 }
997
998 /* Delete fragment shader state. */
999 static void r300_delete_fs_state(struct pipe_context* pipe, void* shader)
1000 {
1001 struct r300_fragment_shader* fs = (struct r300_fragment_shader*)shader;
1002 struct r300_fragment_shader_code *tmp, *ptr = fs->first;
1003
1004 while (ptr) {
1005 tmp = ptr;
1006 ptr = ptr->next;
1007 rc_constants_destroy(&tmp->code.constants);
1008 FREE(tmp->cb_code);
1009 FREE(tmp);
1010 }
1011 FREE((void*)fs->state.tokens);
1012 FREE(shader);
1013 }
1014
1015 static void r300_set_polygon_stipple(struct pipe_context* pipe,
1016 const struct pipe_poly_stipple* state)
1017 {
1018 /* XXX no idea how to set this up, but not terribly important */
1019 }
1020
1021 /* Create a new rasterizer state based on the CSO rasterizer state.
1022 *
1023 * This is a very large chunk of state, and covers most of the graphics
1024 * backend (GB), geometry assembly (GA), and setup unit (SU) blocks.
1025 *
1026 * In a not entirely unironic sidenote, this state has nearly nothing to do
1027 * with the actual block on the Radeon called the rasterizer (RS). */
1028 static void* r300_create_rs_state(struct pipe_context* pipe,
1029 const struct pipe_rasterizer_state* state)
1030 {
1031 struct r300_rs_state* rs = CALLOC_STRUCT(r300_rs_state);
1032 float psiz;
1033 uint32_t vap_control_status; /* R300_VAP_CNTL_STATUS: 0x2140 */
1034 uint32_t point_size; /* R300_GA_POINT_SIZE: 0x421c */
1035 uint32_t point_minmax; /* R300_GA_POINT_MINMAX: 0x4230 */
1036 uint32_t line_control; /* R300_GA_LINE_CNTL: 0x4234 */
1037 uint32_t polygon_offset_enable; /* R300_SU_POLY_OFFSET_ENABLE: 0x42b4 */
1038 uint32_t cull_mode; /* R300_SU_CULL_MODE: 0x42b8 */
1039 uint32_t line_stipple_config; /* R300_GA_LINE_STIPPLE_CONFIG: 0x4328 */
1040 uint32_t line_stipple_value; /* R300_GA_LINE_STIPPLE_VALUE: 0x4260 */
1041 uint32_t polygon_mode; /* R300_GA_POLY_MODE: 0x4288 */
1042 uint32_t clip_rule; /* R300_SC_CLIP_RULE: 0x43D0 */
1043 uint32_t round_mode; /* R300_GA_ROUND_MODE: 0x428c */
1044
1045 /* Point sprites texture coordinates, 0: lower left, 1: upper right */
1046 float point_texcoord_left = 0; /* R300_GA_POINT_S0: 0x4200 */
1047 float point_texcoord_bottom = 0;/* R300_GA_POINT_T0: 0x4204 */
1048 float point_texcoord_right = 1; /* R300_GA_POINT_S1: 0x4208 */
1049 float point_texcoord_top = 0; /* R300_GA_POINT_T1: 0x420c */
1050 boolean vclamp = TRUE;
1051 CB_LOCALS;
1052
1053 /* Copy rasterizer state. */
1054 rs->rs = *state;
1055 rs->rs_draw = *state;
1056
1057 rs->rs.sprite_coord_enable = state->point_quad_rasterization *
1058 state->sprite_coord_enable;
1059
1060 /* Override some states for Draw. */
1061 rs->rs_draw.sprite_coord_enable = 0; /* We can do this in HW. */
1062
1063 #ifdef PIPE_ARCH_LITTLE_ENDIAN
1064 vap_control_status = R300_VC_NO_SWAP;
1065 #else
1066 vap_control_status = R300_VC_32BIT_SWAP;
1067 #endif
1068
1069 /* If no TCL engine is present, turn off the HW TCL. */
1070 if (!r300_screen(pipe->screen)->caps.has_tcl) {
1071 vap_control_status |= R300_VAP_TCL_BYPASS;
1072 }
1073
1074 /* Point size width and height. */
1075 point_size =
1076 pack_float_16_6x(state->point_size) |
1077 (pack_float_16_6x(state->point_size) << R300_POINTSIZE_X_SHIFT);
1078
1079 /* Point size clamping. */
1080 if (state->point_size_per_vertex) {
1081 /* Per-vertex point size.
1082 * Clamp to [0, max FB size] */
1083 psiz = pipe->screen->get_paramf(pipe->screen,
1084 PIPE_CAP_MAX_POINT_WIDTH);
1085 point_minmax =
1086 pack_float_16_6x(psiz) << R300_GA_POINT_MINMAX_MAX_SHIFT;
1087 } else {
1088 /* We cannot disable the point-size vertex output,
1089 * so clamp it. */
1090 psiz = state->point_size;
1091 point_minmax =
1092 (pack_float_16_6x(psiz) << R300_GA_POINT_MINMAX_MIN_SHIFT) |
1093 (pack_float_16_6x(psiz) << R300_GA_POINT_MINMAX_MAX_SHIFT);
1094 }
1095
1096 /* Line control. */
1097 line_control = pack_float_16_6x(state->line_width) |
1098 R300_GA_LINE_CNTL_END_TYPE_COMP;
1099
1100 /* Enable polygon mode */
1101 polygon_mode = 0;
1102 if (state->fill_front != PIPE_POLYGON_MODE_FILL ||
1103 state->fill_back != PIPE_POLYGON_MODE_FILL) {
1104 polygon_mode = R300_GA_POLY_MODE_DUAL;
1105 }
1106
1107 /* Front face */
1108 if (state->front_ccw)
1109 cull_mode = R300_FRONT_FACE_CCW;
1110 else
1111 cull_mode = R300_FRONT_FACE_CW;
1112
1113 /* Polygon offset */
1114 polygon_offset_enable = 0;
1115 if (util_get_offset(state, state->fill_front)) {
1116 polygon_offset_enable |= R300_FRONT_ENABLE;
1117 }
1118 if (util_get_offset(state, state->fill_back)) {
1119 polygon_offset_enable |= R300_BACK_ENABLE;
1120 }
1121
1122 rs->polygon_offset_enable = polygon_offset_enable != 0;
1123
1124 /* Polygon mode */
1125 if (polygon_mode) {
1126 polygon_mode |=
1127 r300_translate_polygon_mode_front(state->fill_front);
1128 polygon_mode |=
1129 r300_translate_polygon_mode_back(state->fill_back);
1130 }
1131
1132 if (state->cull_face & PIPE_FACE_FRONT) {
1133 cull_mode |= R300_CULL_FRONT;
1134 }
1135 if (state->cull_face & PIPE_FACE_BACK) {
1136 cull_mode |= R300_CULL_BACK;
1137 }
1138
1139 if (state->line_stipple_enable) {
1140 line_stipple_config =
1141 R300_GA_LINE_STIPPLE_CONFIG_LINE_RESET_LINE |
1142 (fui((float)state->line_stipple_factor) &
1143 R300_GA_LINE_STIPPLE_CONFIG_STIPPLE_SCALE_MASK);
1144 /* XXX this might need to be scaled up */
1145 line_stipple_value = state->line_stipple_pattern;
1146 } else {
1147 line_stipple_config = 0;
1148 line_stipple_value = 0;
1149 }
1150
1151 if (state->flatshade) {
1152 rs->color_control = R300_SHADE_MODEL_FLAT;
1153 } else {
1154 rs->color_control = R300_SHADE_MODEL_SMOOTH;
1155 }
1156
1157 clip_rule = state->scissor ? 0xAAAA : 0xFFFF;
1158
1159 /* Point sprites coord mode */
1160 if (rs->rs.sprite_coord_enable) {
1161 switch (state->sprite_coord_mode) {
1162 case PIPE_SPRITE_COORD_UPPER_LEFT:
1163 point_texcoord_top = 0.0f;
1164 point_texcoord_bottom = 1.0f;
1165 break;
1166 case PIPE_SPRITE_COORD_LOWER_LEFT:
1167 point_texcoord_top = 1.0f;
1168 point_texcoord_bottom = 0.0f;
1169 break;
1170 }
1171 }
1172
1173 /* Vertex color clamping. FP20 means no clamping. */
1174 round_mode =
1175 R300_GA_ROUND_MODE_GEOMETRY_ROUND_NEAREST |
1176 (!vclamp ? (R300_GA_ROUND_MODE_RGB_CLAMP_FP20 |
1177 R300_GA_ROUND_MODE_ALPHA_CLAMP_FP20) : 0);
1178
1179 /* Build the main command buffer. */
1180 BEGIN_CB(rs->cb_main, RS_STATE_MAIN_SIZE);
1181 OUT_CB_REG(R300_VAP_CNTL_STATUS, vap_control_status);
1182 OUT_CB_REG(R300_GA_POINT_SIZE, point_size);
1183 OUT_CB_REG_SEQ(R300_GA_POINT_MINMAX, 2);
1184 OUT_CB(point_minmax);
1185 OUT_CB(line_control);
1186 OUT_CB_REG_SEQ(R300_SU_POLY_OFFSET_ENABLE, 2);
1187 OUT_CB(polygon_offset_enable);
1188 rs->cull_mode_index = 9;
1189 OUT_CB(cull_mode);
1190 OUT_CB_REG(R300_GA_LINE_STIPPLE_CONFIG, line_stipple_config);
1191 OUT_CB_REG(R300_GA_LINE_STIPPLE_VALUE, line_stipple_value);
1192 OUT_CB_REG(R300_GA_POLY_MODE, polygon_mode);
1193 OUT_CB_REG(R300_GA_ROUND_MODE, round_mode);
1194 OUT_CB_REG(R300_SC_CLIP_RULE, clip_rule);
1195 OUT_CB_REG_SEQ(R300_GA_POINT_S0, 4);
1196 OUT_CB_32F(point_texcoord_left);
1197 OUT_CB_32F(point_texcoord_bottom);
1198 OUT_CB_32F(point_texcoord_right);
1199 OUT_CB_32F(point_texcoord_top);
1200 END_CB;
1201
1202 /* Build the two command buffers for polygon offset setup. */
1203 if (polygon_offset_enable) {
1204 float scale = state->offset_scale * 12;
1205 float offset = state->offset_units * 4;
1206
1207 BEGIN_CB(rs->cb_poly_offset_zb16, 5);
1208 OUT_CB_REG_SEQ(R300_SU_POLY_OFFSET_FRONT_SCALE, 4);
1209 OUT_CB_32F(scale);
1210 OUT_CB_32F(offset);
1211 OUT_CB_32F(scale);
1212 OUT_CB_32F(offset);
1213 END_CB;
1214
1215 offset = state->offset_units * 2;
1216
1217 BEGIN_CB(rs->cb_poly_offset_zb24, 5);
1218 OUT_CB_REG_SEQ(R300_SU_POLY_OFFSET_FRONT_SCALE, 4);
1219 OUT_CB_32F(scale);
1220 OUT_CB_32F(offset);
1221 OUT_CB_32F(scale);
1222 OUT_CB_32F(offset);
1223 END_CB;
1224 }
1225
1226 return (void*)rs;
1227 }
1228
1229 /* Bind rasterizer state. */
1230 static void r300_bind_rs_state(struct pipe_context* pipe, void* state)
1231 {
1232 struct r300_context* r300 = r300_context(pipe);
1233 struct r300_rs_state* rs = (struct r300_rs_state*)state;
1234 int last_sprite_coord_enable = r300->sprite_coord_enable;
1235 boolean last_two_sided_color = r300->two_sided_color;
1236
1237 if (r300->draw && rs) {
1238 draw_set_rasterizer_state(r300->draw, &rs->rs_draw, state);
1239 }
1240
1241 if (rs) {
1242 r300->polygon_offset_enabled = rs->polygon_offset_enable;
1243 r300->sprite_coord_enable = rs->rs.sprite_coord_enable;
1244 r300->two_sided_color = rs->rs.light_twoside;
1245 } else {
1246 r300->polygon_offset_enabled = FALSE;
1247 r300->sprite_coord_enable = 0;
1248 r300->two_sided_color = FALSE;
1249 }
1250
1251 UPDATE_STATE(state, r300->rs_state);
1252 r300->rs_state.size = RS_STATE_MAIN_SIZE + (r300->polygon_offset_enabled ? 5 : 0);
1253
1254 if (last_sprite_coord_enable != r300->sprite_coord_enable ||
1255 last_two_sided_color != r300->two_sided_color) {
1256 r300_mark_atom_dirty(r300, &r300->rs_block_state);
1257 }
1258 }
1259
1260 /* Free rasterizer state. */
1261 static void r300_delete_rs_state(struct pipe_context* pipe, void* state)
1262 {
1263 FREE(state);
1264 }
1265
1266 static void*
1267 r300_create_sampler_state(struct pipe_context* pipe,
1268 const struct pipe_sampler_state* state)
1269 {
1270 struct r300_context* r300 = r300_context(pipe);
1271 struct r300_sampler_state* sampler = CALLOC_STRUCT(r300_sampler_state);
1272 boolean is_r500 = r300->screen->caps.is_r500;
1273 int lod_bias;
1274
1275 sampler->state = *state;
1276
1277 /* r300 doesn't handle CLAMP and MIRROR_CLAMP correctly when either MAG
1278 * or MIN filter is NEAREST. Since texwrap produces same results
1279 * for CLAMP and CLAMP_TO_EDGE, we use them instead. */
1280 if (sampler->state.min_img_filter == PIPE_TEX_FILTER_NEAREST ||
1281 sampler->state.mag_img_filter == PIPE_TEX_FILTER_NEAREST) {
1282 /* Wrap S. */
1283 if (sampler->state.wrap_s == PIPE_TEX_WRAP_CLAMP)
1284 sampler->state.wrap_s = PIPE_TEX_WRAP_CLAMP_TO_EDGE;
1285 else if (sampler->state.wrap_s == PIPE_TEX_WRAP_MIRROR_CLAMP)
1286 sampler->state.wrap_s = PIPE_TEX_WRAP_MIRROR_CLAMP_TO_EDGE;
1287
1288 /* Wrap T. */
1289 if (sampler->state.wrap_t == PIPE_TEX_WRAP_CLAMP)
1290 sampler->state.wrap_t = PIPE_TEX_WRAP_CLAMP_TO_EDGE;
1291 else if (sampler->state.wrap_t == PIPE_TEX_WRAP_MIRROR_CLAMP)
1292 sampler->state.wrap_t = PIPE_TEX_WRAP_MIRROR_CLAMP_TO_EDGE;
1293
1294 /* Wrap R. */
1295 if (sampler->state.wrap_r == PIPE_TEX_WRAP_CLAMP)
1296 sampler->state.wrap_r = PIPE_TEX_WRAP_CLAMP_TO_EDGE;
1297 else if (sampler->state.wrap_r == PIPE_TEX_WRAP_MIRROR_CLAMP)
1298 sampler->state.wrap_r = PIPE_TEX_WRAP_MIRROR_CLAMP_TO_EDGE;
1299 }
1300
1301 sampler->filter0 |=
1302 (r300_translate_wrap(sampler->state.wrap_s) << R300_TX_WRAP_S_SHIFT) |
1303 (r300_translate_wrap(sampler->state.wrap_t) << R300_TX_WRAP_T_SHIFT) |
1304 (r300_translate_wrap(sampler->state.wrap_r) << R300_TX_WRAP_R_SHIFT);
1305
1306 sampler->filter0 |= r300_translate_tex_filters(state->min_img_filter,
1307 state->mag_img_filter,
1308 state->min_mip_filter,
1309 state->max_anisotropy > 0);
1310
1311 sampler->filter0 |= r300_anisotropy(state->max_anisotropy);
1312
1313 /* Unfortunately, r300-r500 don't support floating-point mipmap lods. */
1314 /* We must pass these to the merge function to clamp them properly. */
1315 sampler->min_lod = (unsigned)MAX2(state->min_lod, 0);
1316 sampler->max_lod = (unsigned)MAX2(ceilf(state->max_lod), 0);
1317
1318 lod_bias = CLAMP((int)(state->lod_bias * 32 + 1), -(1 << 9), (1 << 9) - 1);
1319
1320 sampler->filter1 |= (lod_bias << R300_LOD_BIAS_SHIFT) & R300_LOD_BIAS_MASK;
1321
1322 /* This is very high quality anisotropic filtering for R5xx.
1323 * It's good for benchmarking the performance of texturing but
1324 * in practice we don't want to slow down the driver because it's
1325 * a pretty good performance killer. Feel free to play with it. */
1326 if (DBG_ON(r300, DBG_ANISOHQ) && is_r500) {
1327 sampler->filter1 |= r500_anisotropy(state->max_anisotropy);
1328 }
1329
1330 /* R500-specific fixups and optimizations */
1331 if (r300->screen->caps.is_r500) {
1332 sampler->filter1 |= R500_BORDER_FIX;
1333 }
1334
1335 return (void*)sampler;
1336 }
1337
1338 static void r300_bind_sampler_states(struct pipe_context* pipe,
1339 unsigned count,
1340 void** states)
1341 {
1342 struct r300_context* r300 = r300_context(pipe);
1343 struct r300_textures_state* state =
1344 (struct r300_textures_state*)r300->textures_state.state;
1345 unsigned tex_units = r300->screen->caps.num_tex_units;
1346
1347 if (count > tex_units) {
1348 return;
1349 }
1350
1351 memcpy(state->sampler_states, states, sizeof(void*) * count);
1352 state->sampler_state_count = count;
1353
1354 r300_mark_atom_dirty(r300, &r300->textures_state);
1355 }
1356
1357 static void r300_lacks_vertex_textures(struct pipe_context* pipe,
1358 unsigned count,
1359 void** states)
1360 {
1361 }
1362
1363 static void r300_delete_sampler_state(struct pipe_context* pipe, void* state)
1364 {
1365 FREE(state);
1366 }
1367
1368 static uint32_t r300_assign_texture_cache_region(unsigned index, unsigned num)
1369 {
1370 /* This looks like a hack, but I believe it's suppose to work like
1371 * that. To illustrate how this works, let's assume you have 5 textures.
1372 * From docs, 5 and the successive numbers are:
1373 *
1374 * FOURTH_1 = 5
1375 * FOURTH_2 = 6
1376 * FOURTH_3 = 7
1377 * EIGHTH_0 = 8
1378 * EIGHTH_1 = 9
1379 *
1380 * First 3 textures will get 3/4 of size of the cache, divived evenly
1381 * between them. The last 1/4 of the cache must be divided between
1382 * the last 2 textures, each will therefore get 1/8 of the cache.
1383 * Why not just to use "5 + texture_index" ?
1384 *
1385 * This simple trick works for all "num" <= 16.
1386 */
1387 if (num <= 1)
1388 return R300_TX_CACHE(R300_TX_CACHE_WHOLE);
1389 else
1390 return R300_TX_CACHE(num + index);
1391 }
1392
1393 static void r300_set_fragment_sampler_views(struct pipe_context* pipe,
1394 unsigned count,
1395 struct pipe_sampler_view** views)
1396 {
1397 struct r300_context* r300 = r300_context(pipe);
1398 struct r300_textures_state* state =
1399 (struct r300_textures_state*)r300->textures_state.state;
1400 struct r300_resource *texture;
1401 unsigned i, real_num_views = 0, view_index = 0;
1402 unsigned tex_units = r300->screen->caps.num_tex_units;
1403 boolean dirty_tex = FALSE;
1404
1405 if (count > tex_units) {
1406 return;
1407 }
1408
1409 /* Calculate the real number of views. */
1410 for (i = 0; i < count; i++) {
1411 if (views[i])
1412 real_num_views++;
1413 }
1414
1415 for (i = 0; i < count; i++) {
1416 pipe_sampler_view_reference(
1417 (struct pipe_sampler_view**)&state->sampler_views[i],
1418 views[i]);
1419
1420 if (!views[i]) {
1421 continue;
1422 }
1423
1424 /* A new sampler view (= texture)... */
1425 dirty_tex = TRUE;
1426
1427 /* Set the texrect factor in the fragment shader.
1428 * Needed for RECT and NPOT fallback. */
1429 texture = r300_resource(views[i]->texture);
1430 if (texture->tex.is_npot) {
1431 r300_mark_atom_dirty(r300, &r300->fs_rc_constant_state);
1432 }
1433
1434 state->sampler_views[i]->texcache_region =
1435 r300_assign_texture_cache_region(view_index, real_num_views);
1436 view_index++;
1437 }
1438
1439 for (i = count; i < tex_units; i++) {
1440 if (state->sampler_views[i]) {
1441 pipe_sampler_view_reference(
1442 (struct pipe_sampler_view**)&state->sampler_views[i],
1443 NULL);
1444 }
1445 }
1446
1447 state->sampler_view_count = count;
1448
1449 r300_mark_atom_dirty(r300, &r300->textures_state);
1450
1451 if (dirty_tex) {
1452 r300_mark_atom_dirty(r300, &r300->texture_cache_inval);
1453 }
1454 }
1455
1456 static struct pipe_sampler_view *
1457 r300_create_sampler_view(struct pipe_context *pipe,
1458 struct pipe_resource *texture,
1459 const struct pipe_sampler_view *templ)
1460 {
1461 struct r300_sampler_view *view = CALLOC_STRUCT(r300_sampler_view);
1462 struct r300_resource *tex = r300_resource(texture);
1463 boolean is_r500 = r300_screen(pipe->screen)->caps.is_r500;
1464 boolean dxtc_swizzle = r300_screen(pipe->screen)->caps.dxtc_swizzle;
1465
1466 if (view) {
1467 view->base = *templ;
1468 view->base.reference.count = 1;
1469 view->base.context = pipe;
1470 view->base.texture = NULL;
1471 pipe_resource_reference(&view->base.texture, texture);
1472
1473 view->swizzle[0] = templ->swizzle_r;
1474 view->swizzle[1] = templ->swizzle_g;
1475 view->swizzle[2] = templ->swizzle_b;
1476 view->swizzle[3] = templ->swizzle_a;
1477
1478 view->format = tex->tx_format;
1479 view->format.format1 |= r300_translate_texformat(templ->format,
1480 view->swizzle,
1481 is_r500,
1482 dxtc_swizzle);
1483 if (is_r500) {
1484 view->format.format2 |= r500_tx_format_msb_bit(templ->format);
1485 }
1486 }
1487
1488 return (struct pipe_sampler_view*)view;
1489 }
1490
1491 static void
1492 r300_sampler_view_destroy(struct pipe_context *pipe,
1493 struct pipe_sampler_view *view)
1494 {
1495 pipe_resource_reference(&view->texture, NULL);
1496 FREE(view);
1497 }
1498
1499 static void r300_set_scissor_state(struct pipe_context* pipe,
1500 const struct pipe_scissor_state* state)
1501 {
1502 struct r300_context* r300 = r300_context(pipe);
1503
1504 memcpy(r300->scissor_state.state, state,
1505 sizeof(struct pipe_scissor_state));
1506
1507 r300_mark_atom_dirty(r300, &r300->scissor_state);
1508 }
1509
1510 static void r300_set_viewport_state(struct pipe_context* pipe,
1511 const struct pipe_viewport_state* state)
1512 {
1513 struct r300_context* r300 = r300_context(pipe);
1514 struct r300_viewport_state* viewport =
1515 (struct r300_viewport_state*)r300->viewport_state.state;
1516
1517 r300->viewport = *state;
1518
1519 if (r300->draw) {
1520 draw_set_viewport_state(r300->draw, state);
1521 viewport->vte_control = R300_VTX_XY_FMT | R300_VTX_Z_FMT;
1522 return;
1523 }
1524
1525 /* Do the transform in HW. */
1526 viewport->vte_control = R300_VTX_W0_FMT;
1527
1528 if (state->scale[0] != 1.0f) {
1529 viewport->xscale = state->scale[0];
1530 viewport->vte_control |= R300_VPORT_X_SCALE_ENA;
1531 }
1532 if (state->scale[1] != 1.0f) {
1533 viewport->yscale = state->scale[1];
1534 viewport->vte_control |= R300_VPORT_Y_SCALE_ENA;
1535 }
1536 if (state->scale[2] != 1.0f) {
1537 viewport->zscale = state->scale[2];
1538 viewport->vte_control |= R300_VPORT_Z_SCALE_ENA;
1539 }
1540 if (state->translate[0] != 0.0f) {
1541 viewport->xoffset = state->translate[0];
1542 viewport->vte_control |= R300_VPORT_X_OFFSET_ENA;
1543 }
1544 if (state->translate[1] != 0.0f) {
1545 viewport->yoffset = state->translate[1];
1546 viewport->vte_control |= R300_VPORT_Y_OFFSET_ENA;
1547 }
1548 if (state->translate[2] != 0.0f) {
1549 viewport->zoffset = state->translate[2];
1550 viewport->vte_control |= R300_VPORT_Z_OFFSET_ENA;
1551 }
1552
1553 r300_mark_atom_dirty(r300, &r300->viewport_state);
1554 if (r300->fs.state && r300_fs(r300)->shader->inputs.wpos != ATTR_UNUSED) {
1555 r300_mark_atom_dirty(r300, &r300->fs_rc_constant_state);
1556 }
1557 }
1558
1559 static void r300_set_vertex_buffers(struct pipe_context* pipe,
1560 unsigned count,
1561 const struct pipe_vertex_buffer* buffers)
1562 {
1563 struct r300_context* r300 = r300_context(pipe);
1564 unsigned i;
1565 struct pipe_vertex_buffer dummy_vb = {0};
1566
1567 /* There must be at least one vertex buffer set, otherwise it locks up. */
1568 if (!count) {
1569 dummy_vb.buffer = r300->dummy_vb;
1570 buffers = &dummy_vb;
1571 count = 1;
1572 }
1573
1574 u_vbuf_mgr_set_vertex_buffers(r300->vbuf_mgr, count, buffers);
1575
1576 if (r300->screen->caps.has_tcl) {
1577 /* HW TCL. */
1578 for (i = 0; i < count; i++) {
1579 if (buffers[i].buffer &&
1580 !r300_resource(buffers[i].buffer)->b.user_ptr) {
1581 }
1582 }
1583 r300->vertex_arrays_dirty = TRUE;
1584 } else {
1585 /* SW TCL. */
1586 draw_set_vertex_buffers(r300->draw, count, buffers);
1587 }
1588 }
1589
1590 static void r300_set_index_buffer(struct pipe_context* pipe,
1591 const struct pipe_index_buffer *ib)
1592 {
1593 struct r300_context* r300 = r300_context(pipe);
1594
1595 if (ib && ib->buffer) {
1596 assert(ib->offset % ib->index_size == 0);
1597
1598 pipe_resource_reference(&r300->index_buffer.buffer, ib->buffer);
1599 memcpy(&r300->index_buffer, ib, sizeof(r300->index_buffer));
1600 r300->index_buffer.offset /= r300->index_buffer.index_size;
1601 }
1602 else {
1603 pipe_resource_reference(&r300->index_buffer.buffer, NULL);
1604 memset(&r300->index_buffer, 0, sizeof(r300->index_buffer));
1605 }
1606
1607 if (!r300->screen->caps.has_tcl) {
1608 draw_set_index_buffer(r300->draw, ib);
1609 }
1610 }
1611
1612 /* Initialize the PSC tables. */
1613 static void r300_vertex_psc(struct r300_vertex_element_state *velems)
1614 {
1615 struct r300_vertex_stream_state *vstream = &velems->vertex_stream;
1616 uint16_t type, swizzle;
1617 enum pipe_format format;
1618 unsigned i;
1619
1620 /* Vertex shaders have no semantics on their inputs,
1621 * so PSC should just route stuff based on the vertex elements,
1622 * and not on attrib information. */
1623 for (i = 0; i < velems->count; i++) {
1624 format = velems->velem[i].src_format;
1625
1626 type = r300_translate_vertex_data_type(format);
1627 if (type == R300_INVALID_FORMAT) {
1628 fprintf(stderr, "r300: Bad vertex format %s.\n",
1629 util_format_short_name(format));
1630 assert(0);
1631 abort();
1632 }
1633
1634 type |= i << R300_DST_VEC_LOC_SHIFT;
1635 swizzle = r300_translate_vertex_data_swizzle(format);
1636
1637 if (i & 1) {
1638 vstream->vap_prog_stream_cntl[i >> 1] |= type << 16;
1639 vstream->vap_prog_stream_cntl_ext[i >> 1] |= swizzle << 16;
1640 } else {
1641 vstream->vap_prog_stream_cntl[i >> 1] |= type;
1642 vstream->vap_prog_stream_cntl_ext[i >> 1] |= swizzle;
1643 }
1644 }
1645
1646 /* Set the last vector in the PSC. */
1647 if (i) {
1648 i -= 1;
1649 }
1650 vstream->vap_prog_stream_cntl[i >> 1] |=
1651 (R300_LAST_VEC << (i & 1 ? 16 : 0));
1652
1653 vstream->count = (i >> 1) + 1;
1654 }
1655
1656 static void* r300_create_vertex_elements_state(struct pipe_context* pipe,
1657 unsigned count,
1658 const struct pipe_vertex_element* attribs)
1659 {
1660 struct r300_context *r300 = r300_context(pipe);
1661 struct r300_vertex_element_state *velems;
1662 unsigned i;
1663 struct pipe_vertex_element dummy_attrib = {0};
1664
1665 /* R300 Programmable Stream Control (PSC) doesn't support 0 vertex elements. */
1666 if (!count) {
1667 dummy_attrib.src_format = PIPE_FORMAT_R8G8B8A8_UNORM;
1668 attribs = &dummy_attrib;
1669 count = 1;
1670 } else if (count > 16) {
1671 fprintf(stderr, "r300: More than 16 vertex elements are not supported,"
1672 " requested %i, using 16.\n", count);
1673 count = 16;
1674 }
1675
1676 velems = CALLOC_STRUCT(r300_vertex_element_state);
1677 if (!velems)
1678 return NULL;
1679
1680 velems->count = count;
1681 velems->vmgr_elements =
1682 u_vbuf_mgr_create_vertex_elements(r300->vbuf_mgr, count, attribs,
1683 velems->velem);
1684
1685 if (r300_screen(pipe->screen)->caps.has_tcl) {
1686 /* Setup PSC.
1687 * The unused components will be replaced by (..., 0, 1). */
1688 r300_vertex_psc(velems);
1689
1690 for (i = 0; i < count; i++) {
1691 velems->format_size[i] =
1692 align(util_format_get_blocksize(velems->velem[i].src_format), 4);
1693 velems->vertex_size_dwords += velems->format_size[i] / 4;
1694 }
1695 }
1696
1697 return velems;
1698 }
1699
1700 static void r300_bind_vertex_elements_state(struct pipe_context *pipe,
1701 void *state)
1702 {
1703 struct r300_context *r300 = r300_context(pipe);
1704 struct r300_vertex_element_state *velems = state;
1705
1706 if (velems == NULL) {
1707 return;
1708 }
1709
1710 r300->velems = velems;
1711
1712 u_vbuf_mgr_bind_vertex_elements(r300->vbuf_mgr, state, velems->vmgr_elements);
1713
1714 if (r300->draw) {
1715 draw_set_vertex_elements(r300->draw, velems->count, velems->velem);
1716 return;
1717 }
1718
1719 UPDATE_STATE(&velems->vertex_stream, r300->vertex_stream_state);
1720 r300->vertex_stream_state.size = (1 + velems->vertex_stream.count) * 2;
1721 r300->vertex_arrays_dirty = TRUE;
1722 }
1723
1724 static void r300_delete_vertex_elements_state(struct pipe_context *pipe, void *state)
1725 {
1726 struct r300_context *r300 = r300_context(pipe);
1727 struct r300_vertex_element_state *velems = state;
1728
1729 u_vbuf_mgr_destroy_vertex_elements(r300->vbuf_mgr, velems->vmgr_elements);
1730 FREE(state);
1731 }
1732
1733 static void* r300_create_vs_state(struct pipe_context* pipe,
1734 const struct pipe_shader_state* shader)
1735 {
1736 struct r300_context* r300 = r300_context(pipe);
1737 struct r300_vertex_shader* vs = CALLOC_STRUCT(r300_vertex_shader);
1738
1739 /* Copy state directly into shader. */
1740 vs->state = *shader;
1741 vs->state.tokens = tgsi_dup_tokens(shader->tokens);
1742
1743 if (r300->screen->caps.has_tcl) {
1744 r300_init_vs_outputs(vs);
1745 r300_translate_vertex_shader(r300, vs);
1746 } else {
1747 r300_draw_init_vertex_shader(r300->draw, vs);
1748 }
1749
1750 return vs;
1751 }
1752
1753 static void r300_bind_vs_state(struct pipe_context* pipe, void* shader)
1754 {
1755 struct r300_context* r300 = r300_context(pipe);
1756 struct r300_vertex_shader* vs = (struct r300_vertex_shader*)shader;
1757
1758 if (vs == NULL) {
1759 r300->vs_state.state = NULL;
1760 return;
1761 }
1762 if (vs == r300->vs_state.state) {
1763 return;
1764 }
1765 r300->vs_state.state = vs;
1766
1767 /* The majority of the RS block bits is dependent on the vertex shader. */
1768 r300_mark_atom_dirty(r300, &r300->rs_block_state); /* Will be updated before the emission. */
1769
1770 if (r300->screen->caps.has_tcl) {
1771 unsigned fc_op_dwords = r300->screen->caps.is_r500 ? 3 : 2;
1772 r300_mark_atom_dirty(r300, &r300->vs_state);
1773 r300->vs_state.size =
1774 vs->code.length + 9 +
1775 (vs->code.num_fc_ops ? vs->code.num_fc_ops * fc_op_dwords + 4 : 0);
1776
1777 r300_mark_atom_dirty(r300, &r300->vs_constants);
1778 r300->vs_constants.size =
1779 2 +
1780 (vs->externals_count ? vs->externals_count * 4 + 3 : 0) +
1781 (vs->immediates_count ? vs->immediates_count * 4 + 3 : 0);
1782
1783 ((struct r300_constant_buffer*)r300->vs_constants.state)->remap_table =
1784 vs->code.constants_remap_table;
1785
1786 r300_mark_atom_dirty(r300, &r300->pvs_flush);
1787 } else {
1788 draw_bind_vertex_shader(r300->draw,
1789 (struct draw_vertex_shader*)vs->draw_vs);
1790 }
1791 }
1792
1793 static void r300_delete_vs_state(struct pipe_context* pipe, void* shader)
1794 {
1795 struct r300_context* r300 = r300_context(pipe);
1796 struct r300_vertex_shader* vs = (struct r300_vertex_shader*)shader;
1797
1798 if (r300->screen->caps.has_tcl) {
1799 rc_constants_destroy(&vs->code.constants);
1800 if (vs->code.constants_remap_table)
1801 FREE(vs->code.constants_remap_table);
1802 } else {
1803 draw_delete_vertex_shader(r300->draw,
1804 (struct draw_vertex_shader*)vs->draw_vs);
1805 }
1806
1807 FREE((void*)vs->state.tokens);
1808 FREE(shader);
1809 }
1810
1811 static void r300_set_constant_buffer(struct pipe_context *pipe,
1812 uint shader, uint index,
1813 struct pipe_resource *buf)
1814 {
1815 struct r300_context* r300 = r300_context(pipe);
1816 struct r300_constant_buffer *cbuf;
1817 struct r300_resource *rbuf = r300_resource(buf);
1818 uint32_t *mapped;
1819
1820 switch (shader) {
1821 case PIPE_SHADER_VERTEX:
1822 cbuf = (struct r300_constant_buffer*)r300->vs_constants.state;
1823 break;
1824 case PIPE_SHADER_FRAGMENT:
1825 cbuf = (struct r300_constant_buffer*)r300->fs_constants.state;
1826 break;
1827 default:
1828 return;
1829 }
1830
1831 if (buf == NULL || buf->width0 == 0)
1832 return;
1833
1834 if (rbuf->b.user_ptr)
1835 mapped = (uint32_t*)rbuf->b.user_ptr;
1836 else if (rbuf->constant_buffer)
1837 mapped = (uint32_t*)rbuf->constant_buffer;
1838 else
1839 return;
1840
1841 if (shader == PIPE_SHADER_FRAGMENT ||
1842 (shader == PIPE_SHADER_VERTEX && r300->screen->caps.has_tcl)) {
1843 cbuf->ptr = mapped;
1844 }
1845
1846 if (shader == PIPE_SHADER_VERTEX) {
1847 if (r300->screen->caps.has_tcl) {
1848 struct r300_vertex_shader *vs =
1849 (struct r300_vertex_shader*)r300->vs_state.state;
1850
1851 if (!vs) {
1852 cbuf->buffer_base = 0;
1853 return;
1854 }
1855
1856 cbuf->buffer_base = r300->vs_const_base;
1857 r300->vs_const_base += vs->code.constants.Count;
1858 if (r300->vs_const_base > R500_MAX_PVS_CONST_VECS) {
1859 r300->vs_const_base = vs->code.constants.Count;
1860 cbuf->buffer_base = 0;
1861 r300_mark_atom_dirty(r300, &r300->pvs_flush);
1862 }
1863 r300_mark_atom_dirty(r300, &r300->vs_constants);
1864 } else if (r300->draw) {
1865 draw_set_mapped_constant_buffer(r300->draw, PIPE_SHADER_VERTEX,
1866 0, mapped, buf->width0);
1867 }
1868 } else if (shader == PIPE_SHADER_FRAGMENT) {
1869 r300_mark_atom_dirty(r300, &r300->fs_constants);
1870 }
1871 }
1872
1873 static void r300_texture_barrier(struct pipe_context *pipe)
1874 {
1875 struct r300_context *r300 = r300_context(pipe);
1876
1877 r300_mark_atom_dirty(r300, &r300->gpu_flush);
1878 r300_mark_atom_dirty(r300, &r300->texture_cache_inval);
1879 }
1880
1881 void r300_init_state_functions(struct r300_context* r300)
1882 {
1883 r300->context.create_blend_state = r300_create_blend_state;
1884 r300->context.bind_blend_state = r300_bind_blend_state;
1885 r300->context.delete_blend_state = r300_delete_blend_state;
1886
1887 r300->context.set_blend_color = r300_set_blend_color;
1888
1889 r300->context.set_clip_state = r300_set_clip_state;
1890 r300->context.set_sample_mask = r300_set_sample_mask;
1891
1892 r300->context.set_constant_buffer = r300_set_constant_buffer;
1893
1894 r300->context.create_depth_stencil_alpha_state = r300_create_dsa_state;
1895 r300->context.bind_depth_stencil_alpha_state = r300_bind_dsa_state;
1896 r300->context.delete_depth_stencil_alpha_state = r300_delete_dsa_state;
1897
1898 r300->context.set_stencil_ref = r300_set_stencil_ref;
1899
1900 r300->context.set_framebuffer_state = r300_set_framebuffer_state;
1901
1902 r300->context.create_fs_state = r300_create_fs_state;
1903 r300->context.bind_fs_state = r300_bind_fs_state;
1904 r300->context.delete_fs_state = r300_delete_fs_state;
1905
1906 r300->context.set_polygon_stipple = r300_set_polygon_stipple;
1907
1908 r300->context.create_rasterizer_state = r300_create_rs_state;
1909 r300->context.bind_rasterizer_state = r300_bind_rs_state;
1910 r300->context.delete_rasterizer_state = r300_delete_rs_state;
1911
1912 r300->context.create_sampler_state = r300_create_sampler_state;
1913 r300->context.bind_fragment_sampler_states = r300_bind_sampler_states;
1914 r300->context.bind_vertex_sampler_states = r300_lacks_vertex_textures;
1915 r300->context.delete_sampler_state = r300_delete_sampler_state;
1916
1917 r300->context.set_fragment_sampler_views = r300_set_fragment_sampler_views;
1918 r300->context.create_sampler_view = r300_create_sampler_view;
1919 r300->context.sampler_view_destroy = r300_sampler_view_destroy;
1920
1921 r300->context.set_scissor_state = r300_set_scissor_state;
1922
1923 r300->context.set_viewport_state = r300_set_viewport_state;
1924
1925 r300->context.set_vertex_buffers = r300_set_vertex_buffers;
1926 r300->context.set_index_buffer = r300_set_index_buffer;
1927 r300->context.redefine_user_buffer = u_default_redefine_user_buffer;
1928
1929 r300->context.create_vertex_elements_state = r300_create_vertex_elements_state;
1930 r300->context.bind_vertex_elements_state = r300_bind_vertex_elements_state;
1931 r300->context.delete_vertex_elements_state = r300_delete_vertex_elements_state;
1932
1933 r300->context.create_vs_state = r300_create_vs_state;
1934 r300->context.bind_vs_state = r300_bind_vs_state;
1935 r300->context.delete_vs_state = r300_delete_vs_state;
1936
1937 r300->context.texture_barrier = r300_texture_barrier;
1938 }