r300g: split constant buffer and shader emittion
[mesa.git] / src / gallium / drivers / r300 / r300_state.c
1 /*
2 * Copyright 2008 Corbin Simpson <MostAwesomeDude@gmail.com>
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * on the rights to use, copy, modify, merge, publish, distribute, sub
8 * license, and/or sell copies of the Software, and to permit persons to whom
9 * the Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
13 * Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHOR(S) AND/OR THEIR SUPPLIERS BE LIABLE FOR ANY CLAIM,
19 * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
20 * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
21 * USE OR OTHER DEALINGS IN THE SOFTWARE. */
22
23 #include "draw/draw_context.h"
24
25 #include "util/u_math.h"
26 #include "util/u_memory.h"
27 #include "util/u_pack_color.h"
28
29 #include "tgsi/tgsi_parse.h"
30
31 #include "pipe/p_config.h"
32 #include "pipe/internal/p_winsys_screen.h"
33
34 #include "r300_context.h"
35 #include "r300_reg.h"
36 #include "r300_screen.h"
37 #include "r300_state_inlines.h"
38 #include "r300_fs.h"
39 #include "r300_vs.h"
40
41 /* r300_state: Functions used to intialize state context by translating
42 * Gallium state objects into semi-native r300 state objects. */
43
44 /* Create a new blend state based on the CSO blend state.
45 *
46 * This encompasses alpha blending, logic/raster ops, and blend dithering. */
47 static void* r300_create_blend_state(struct pipe_context* pipe,
48 const struct pipe_blend_state* state)
49 {
50 struct r300_blend_state* blend = CALLOC_STRUCT(r300_blend_state);
51
52 if (state->blend_enable)
53 {
54 unsigned eqRGB = state->rgb_func;
55 unsigned srcRGB = state->rgb_src_factor;
56 unsigned dstRGB = state->rgb_dst_factor;
57
58 unsigned eqA = state->alpha_func;
59 unsigned srcA = state->alpha_src_factor;
60 unsigned dstA = state->alpha_dst_factor;
61
62 /* despite the name, ALPHA_BLEND_ENABLE has nothing to do with alpha,
63 * this is just the crappy D3D naming */
64 blend->blend_control = R300_ALPHA_BLEND_ENABLE |
65 r300_translate_blend_function(eqRGB) |
66 ( r300_translate_blend_factor(srcRGB) << R300_SRC_BLEND_SHIFT) |
67 ( r300_translate_blend_factor(dstRGB) << R300_DST_BLEND_SHIFT);
68
69 /* optimization: some operations do not require the destination color */
70 if (eqRGB == PIPE_BLEND_MIN || eqA == PIPE_BLEND_MIN ||
71 eqRGB == PIPE_BLEND_MAX || eqA == PIPE_BLEND_MAX ||
72 dstRGB != PIPE_BLENDFACTOR_ZERO ||
73 dstA != PIPE_BLENDFACTOR_ZERO ||
74 srcRGB == PIPE_BLENDFACTOR_DST_COLOR ||
75 srcRGB == PIPE_BLENDFACTOR_DST_ALPHA ||
76 srcRGB == PIPE_BLENDFACTOR_INV_DST_COLOR ||
77 srcRGB == PIPE_BLENDFACTOR_INV_DST_ALPHA ||
78 srcA == PIPE_BLENDFACTOR_DST_COLOR ||
79 srcA == PIPE_BLENDFACTOR_DST_ALPHA ||
80 srcA == PIPE_BLENDFACTOR_INV_DST_COLOR ||
81 srcA == PIPE_BLENDFACTOR_INV_DST_ALPHA)
82 blend->blend_control |= R300_READ_ENABLE;
83
84 /* XXX implement the optimization with DISCARD_SRC_PIXELS*/
85 /* XXX implement the optimization with SRC_ALPHA_?_NO_READ */
86
87 /* separate alpha */
88 if (srcA != srcRGB || dstA != dstRGB || eqA != eqRGB) {
89 blend->blend_control |= R300_SEPARATE_ALPHA_ENABLE;
90 blend->alpha_blend_control =
91 r300_translate_blend_function(eqA) |
92 (r300_translate_blend_factor(srcA) << R300_SRC_BLEND_SHIFT) |
93 (r300_translate_blend_factor(dstA) << R300_DST_BLEND_SHIFT);
94 }
95 }
96
97 /* PIPE_LOGICOP_* don't need to be translated, fortunately. */
98 if (state->logicop_enable) {
99 blend->rop = R300_RB3D_ROPCNTL_ROP_ENABLE |
100 (state->logicop_func) << R300_RB3D_ROPCNTL_ROP_SHIFT;
101 }
102
103 if (state->dither) {
104 blend->dither = R300_RB3D_DITHER_CTL_DITHER_MODE_LUT |
105 R300_RB3D_DITHER_CTL_ALPHA_DITHER_MODE_LUT;
106 }
107
108 return (void*)blend;
109 }
110
111 /* Bind blend state. */
112 static void r300_bind_blend_state(struct pipe_context* pipe,
113 void* state)
114 {
115 struct r300_context* r300 = r300_context(pipe);
116
117 r300->blend_state = (struct r300_blend_state*)state;
118 r300->dirty_state |= R300_NEW_BLEND;
119 }
120
121 /* Free blend state. */
122 static void r300_delete_blend_state(struct pipe_context* pipe,
123 void* state)
124 {
125 FREE(state);
126 }
127
128 /* Convert float to 10bit integer */
129 static unsigned float_to_fixed10(float f)
130 {
131 return CLAMP((unsigned)(f * 1023.9f), 0, 1023);
132 }
133
134 /* Set blend color.
135 * Setup both R300 and R500 registers, figure out later which one to write. */
136 static void r300_set_blend_color(struct pipe_context* pipe,
137 const struct pipe_blend_color* color)
138 {
139 struct r300_context* r300 = r300_context(pipe);
140
141 util_pack_color(color->color, PIPE_FORMAT_A8R8G8B8_UNORM,
142 &r300->blend_color_state->blend_color);
143
144 /* XXX if FP16 blending is enabled, we should use the FP16 format */
145 r300->blend_color_state->blend_color_red_alpha =
146 float_to_fixed10(color->color[0]) |
147 (float_to_fixed10(color->color[3]) << 16);
148 r300->blend_color_state->blend_color_green_blue =
149 float_to_fixed10(color->color[2]) |
150 (float_to_fixed10(color->color[1]) << 16);
151
152 r300->dirty_state |= R300_NEW_BLEND_COLOR;
153 }
154
155 static void r300_set_clip_state(struct pipe_context* pipe,
156 const struct pipe_clip_state* state)
157 {
158 struct r300_context* r300 = r300_context(pipe);
159
160 if (r300_screen(pipe->screen)->caps->has_tcl) {
161 r300->clip_state = *state;
162 r300->dirty_state |= R300_NEW_CLIP;
163 } else {
164 draw_flush(r300->draw);
165 draw_set_clip_state(r300->draw, state);
166 }
167 }
168
169 /* Create a new depth, stencil, and alpha state based on the CSO dsa state.
170 *
171 * This contains the depth buffer, stencil buffer, alpha test, and such.
172 * On the Radeon, depth and stencil buffer setup are intertwined, which is
173 * the reason for some of the strange-looking assignments across registers. */
174 static void*
175 r300_create_dsa_state(struct pipe_context* pipe,
176 const struct pipe_depth_stencil_alpha_state* state)
177 {
178 struct r300_capabilities *caps =
179 r300_screen(r300_context(pipe)->context.screen)->caps;
180 struct r300_dsa_state* dsa = CALLOC_STRUCT(r300_dsa_state);
181
182 /* Depth test setup. */
183 if (state->depth.enabled) {
184 dsa->z_buffer_control |= R300_Z_ENABLE;
185
186 if (state->depth.writemask) {
187 dsa->z_buffer_control |= R300_Z_WRITE_ENABLE;
188 }
189
190 dsa->z_stencil_control |=
191 (r300_translate_depth_stencil_function(state->depth.func) <<
192 R300_Z_FUNC_SHIFT);
193 }
194
195 /* Stencil buffer setup. */
196 if (state->stencil[0].enabled) {
197 dsa->z_buffer_control |= R300_STENCIL_ENABLE;
198 dsa->z_stencil_control |=
199 (r300_translate_depth_stencil_function(state->stencil[0].func) <<
200 R300_S_FRONT_FUNC_SHIFT) |
201 (r300_translate_stencil_op(state->stencil[0].fail_op) <<
202 R300_S_FRONT_SFAIL_OP_SHIFT) |
203 (r300_translate_stencil_op(state->stencil[0].zpass_op) <<
204 R300_S_FRONT_ZPASS_OP_SHIFT) |
205 (r300_translate_stencil_op(state->stencil[0].zfail_op) <<
206 R300_S_FRONT_ZFAIL_OP_SHIFT);
207
208 dsa->stencil_ref_mask = (state->stencil[0].ref_value) |
209 (state->stencil[0].valuemask << R300_STENCILMASK_SHIFT) |
210 (state->stencil[0].writemask << R300_STENCILWRITEMASK_SHIFT);
211
212 if (state->stencil[1].enabled) {
213 dsa->z_buffer_control |= R300_STENCIL_FRONT_BACK;
214 dsa->z_stencil_control |=
215 (r300_translate_depth_stencil_function(state->stencil[1].func) <<
216 R300_S_BACK_FUNC_SHIFT) |
217 (r300_translate_stencil_op(state->stencil[1].fail_op) <<
218 R300_S_BACK_SFAIL_OP_SHIFT) |
219 (r300_translate_stencil_op(state->stencil[1].zpass_op) <<
220 R300_S_BACK_ZPASS_OP_SHIFT) |
221 (r300_translate_stencil_op(state->stencil[1].zfail_op) <<
222 R300_S_BACK_ZFAIL_OP_SHIFT);
223
224 /* XXX it seems r3xx doesn't support STENCILREFMASK_BF */
225 if (caps->is_r500)
226 {
227 dsa->z_buffer_control |= R500_STENCIL_REFMASK_FRONT_BACK;
228 dsa->stencil_ref_bf = (state->stencil[1].ref_value) |
229 (state->stencil[1].valuemask <<
230 R300_STENCILMASK_SHIFT) |
231 (state->stencil[1].writemask <<
232 R300_STENCILWRITEMASK_SHIFT);
233 }
234 }
235 }
236
237 /* Alpha test setup. */
238 if (state->alpha.enabled) {
239 dsa->alpha_function =
240 r300_translate_alpha_function(state->alpha.func) |
241 R300_FG_ALPHA_FUNC_ENABLE;
242
243 /* XXX figure out why emitting 10bit alpha ref causes CS to dump */
244 /* always use 8bit alpha ref */
245 dsa->alpha_function |= float_to_ubyte(state->alpha.ref_value);
246
247 if (caps->is_r500)
248 dsa->alpha_function |= R500_FG_ALPHA_FUNC_8BIT;
249 }
250
251 return (void*)dsa;
252 }
253
254 /* Bind DSA state. */
255 static void r300_bind_dsa_state(struct pipe_context* pipe,
256 void* state)
257 {
258 struct r300_context* r300 = r300_context(pipe);
259
260 r300->dsa_state = (struct r300_dsa_state*)state;
261 r300->dirty_state |= R300_NEW_DSA;
262 }
263
264 /* Free DSA state. */
265 static void r300_delete_dsa_state(struct pipe_context* pipe,
266 void* state)
267 {
268 FREE(state);
269 }
270
271 static void r300_set_edgeflags(struct pipe_context* pipe,
272 const unsigned* bitfield)
273 {
274 /* XXX you know it's bad when i915 has this blank too */
275 /* XXX and even worse, I have no idea WTF the bitfield is */
276 }
277
278 static void
279 r300_set_framebuffer_state(struct pipe_context* pipe,
280 const struct pipe_framebuffer_state* state)
281 {
282 struct r300_context* r300 = r300_context(pipe);
283
284 draw_flush(r300->draw);
285
286 r300->framebuffer_state = *state;
287
288 r300->dirty_state |= R300_NEW_FRAMEBUFFERS;
289 }
290
291 /* Create fragment shader state. */
292 static void* r300_create_fs_state(struct pipe_context* pipe,
293 const struct pipe_shader_state* shader)
294 {
295 struct r300_fragment_shader* fs = NULL;
296
297 fs = (struct r300_fragment_shader*)CALLOC_STRUCT(r300_fragment_shader);
298
299 /* Copy state directly into shader. */
300 fs->state = *shader;
301 fs->state.tokens = tgsi_dup_tokens(shader->tokens);
302
303 tgsi_scan_shader(shader->tokens, &fs->info);
304
305 return (void*)fs;
306 }
307
308 /* Bind fragment shader state. */
309 static void r300_bind_fs_state(struct pipe_context* pipe, void* shader)
310 {
311 struct r300_context* r300 = r300_context(pipe);
312 struct r300_fragment_shader* fs = (struct r300_fragment_shader*)shader;
313
314 if (fs == NULL) {
315 r300->fs = NULL;
316 return;
317 } else if (!fs->translated) {
318 r300_translate_fragment_shader(r300, fs);
319 }
320
321 r300->fs = fs;
322
323 r300->dirty_state |= R300_NEW_FRAGMENT_SHADER | R300_NEW_FRAGMENT_SHADER_CONSTANTS;
324 }
325
326 /* Delete fragment shader state. */
327 static void r300_delete_fs_state(struct pipe_context* pipe, void* shader)
328 {
329 struct r300_fragment_shader* fs = (struct r300_fragment_shader*)shader;
330 rc_constants_destroy(&fs->code.constants);
331 FREE((void*)fs->state.tokens);
332 FREE(shader);
333 }
334
335 static void r300_set_polygon_stipple(struct pipe_context* pipe,
336 const struct pipe_poly_stipple* state)
337 {
338 /* XXX no idea how to set this up, but not terribly important */
339 }
340
341 /* Create a new rasterizer state based on the CSO rasterizer state.
342 *
343 * This is a very large chunk of state, and covers most of the graphics
344 * backend (GB), geometry assembly (GA), and setup unit (SU) blocks.
345 *
346 * In a not entirely unironic sidenote, this state has nearly nothing to do
347 * with the actual block on the Radeon called the rasterizer (RS). */
348 static void* r300_create_rs_state(struct pipe_context* pipe,
349 const struct pipe_rasterizer_state* state)
350 {
351 struct r300_rs_state* rs = CALLOC_STRUCT(r300_rs_state);
352
353 /* Copy rasterizer state for Draw. */
354 rs->rs = *state;
355
356 rs->enable_vte = !state->bypass_vs_clip_and_viewport;
357
358 #ifdef PIPE_ARCH_LITTLE_ENDIAN
359 rs->vap_control_status = R300_VC_NO_SWAP;
360 #else
361 rs->vap_control_status = R300_VC_32BIT_SWAP;
362 #endif
363
364 /* If bypassing TCL, or if no TCL engine is present, turn off the HW TCL.
365 * Else, enable HW TCL and force Draw's TCL off. */
366 if (state->bypass_vs_clip_and_viewport ||
367 !r300_screen(pipe->screen)->caps->has_tcl) {
368 rs->vap_control_status |= R300_VAP_TCL_BYPASS;
369 } else {
370 rs->rs.bypass_vs_clip_and_viewport = TRUE;
371 }
372
373 rs->point_size = pack_float_16_6x(state->point_size) |
374 (pack_float_16_6x(state->point_size) << R300_POINTSIZE_X_SHIFT);
375
376 rs->point_minmax =
377 ((int)(state->point_size_min * 6.0) <<
378 R300_GA_POINT_MINMAX_MIN_SHIFT) |
379 ((int)(state->point_size_max * 6.0) <<
380 R300_GA_POINT_MINMAX_MAX_SHIFT);
381
382 rs->line_control = pack_float_16_6x(state->line_width) |
383 R300_GA_LINE_CNTL_END_TYPE_COMP;
384
385 /* Radeons don't think in "CW/CCW", they think in "front/back". */
386 if (state->front_winding == PIPE_WINDING_CW) {
387 rs->cull_mode = R300_FRONT_FACE_CW;
388
389 if (state->offset_cw) {
390 rs->polygon_offset_enable |= R300_FRONT_ENABLE;
391 }
392 if (state->offset_ccw) {
393 rs->polygon_offset_enable |= R300_BACK_ENABLE;
394 }
395 } else {
396 rs->cull_mode = R300_FRONT_FACE_CCW;
397
398 if (state->offset_ccw) {
399 rs->polygon_offset_enable |= R300_FRONT_ENABLE;
400 }
401 if (state->offset_cw) {
402 rs->polygon_offset_enable |= R300_BACK_ENABLE;
403 }
404 }
405 if (state->front_winding & state->cull_mode) {
406 rs->cull_mode |= R300_CULL_FRONT;
407 }
408 if (~(state->front_winding) & state->cull_mode) {
409 rs->cull_mode |= R300_CULL_BACK;
410 }
411
412 if (rs->polygon_offset_enable) {
413 rs->depth_offset_front = rs->depth_offset_back =
414 fui(state->offset_units);
415 rs->depth_scale_front = rs->depth_scale_back =
416 fui(state->offset_scale);
417 }
418
419 if (state->line_stipple_enable) {
420 rs->line_stipple_config =
421 R300_GA_LINE_STIPPLE_CONFIG_LINE_RESET_LINE |
422 (fui((float)state->line_stipple_factor) &
423 R300_GA_LINE_STIPPLE_CONFIG_STIPPLE_SCALE_MASK);
424 /* XXX this might need to be scaled up */
425 rs->line_stipple_value = state->line_stipple_pattern;
426 }
427
428 if (state->flatshade) {
429 rs->color_control = R300_SHADE_MODEL_FLAT;
430 } else {
431 rs->color_control = R300_SHADE_MODEL_SMOOTH;
432 }
433
434 if (!state->flatshade_first) {
435 rs->color_control |= R300_GA_COLOR_CONTROL_PROVOKING_VERTEX_LAST;
436 }
437
438 return (void*)rs;
439 }
440
441 /* Bind rasterizer state. */
442 static void r300_bind_rs_state(struct pipe_context* pipe, void* state)
443 {
444 struct r300_context* r300 = r300_context(pipe);
445 struct r300_rs_state* rs = (struct r300_rs_state*)state;
446
447 draw_flush(r300->draw);
448 draw_set_rasterizer_state(r300->draw, &rs->rs);
449
450 r300->rs_state = rs;
451 r300->dirty_state |= R300_NEW_RASTERIZER;
452 r300->dirty_state |= R300_NEW_RS_BLOCK;
453 r300->dirty_state |= R300_NEW_SCISSOR;
454 r300->dirty_state |= R300_NEW_VIEWPORT;
455 }
456
457 /* Free rasterizer state. */
458 static void r300_delete_rs_state(struct pipe_context* pipe, void* state)
459 {
460 FREE(state);
461 }
462
463 static void*
464 r300_create_sampler_state(struct pipe_context* pipe,
465 const struct pipe_sampler_state* state)
466 {
467 struct r300_context* r300 = r300_context(pipe);
468 struct r300_sampler_state* sampler = CALLOC_STRUCT(r300_sampler_state);
469 int lod_bias;
470
471 sampler->filter0 |=
472 (r300_translate_wrap(state->wrap_s) << R300_TX_WRAP_S_SHIFT) |
473 (r300_translate_wrap(state->wrap_t) << R300_TX_WRAP_T_SHIFT) |
474 (r300_translate_wrap(state->wrap_r) << R300_TX_WRAP_R_SHIFT);
475
476 sampler->filter0 |= r300_translate_tex_filters(state->min_img_filter,
477 state->mag_img_filter,
478 state->min_mip_filter);
479
480 lod_bias = CLAMP((int)(state->lod_bias * 32), -(1 << 9), (1 << 9) - 1);
481
482 sampler->filter1 |= lod_bias << R300_LOD_BIAS_SHIFT;
483
484 sampler->filter1 |= r300_anisotropy(state->max_anisotropy);
485
486 util_pack_color(state->border_color, PIPE_FORMAT_A8R8G8B8_UNORM,
487 &sampler->border_color);
488
489 /* R500-specific fixups and optimizations */
490 if (r300_screen(r300->context.screen)->caps->is_r500) {
491 sampler->filter1 |= R500_BORDER_FIX;
492 }
493
494 return (void*)sampler;
495 }
496
497 static void r300_bind_sampler_states(struct pipe_context* pipe,
498 unsigned count,
499 void** states)
500 {
501 struct r300_context* r300 = r300_context(pipe);
502 int i;
503
504 if (count > 8) {
505 return;
506 }
507
508 for (i = 0; i < count; i++) {
509 if (r300->sampler_states[i] != states[i]) {
510 r300->sampler_states[i] = (struct r300_sampler_state*)states[i];
511 r300->dirty_state |= (R300_NEW_SAMPLER << i);
512 }
513 }
514
515 r300->sampler_count = count;
516 }
517
518 static void r300_delete_sampler_state(struct pipe_context* pipe, void* state)
519 {
520 FREE(state);
521 }
522
523 static void r300_set_sampler_textures(struct pipe_context* pipe,
524 unsigned count,
525 struct pipe_texture** texture)
526 {
527 struct r300_context* r300 = r300_context(pipe);
528 int i;
529
530 /* XXX magic num */
531 if (count > 8) {
532 return;
533 }
534
535 for (i = 0; i < count; i++) {
536 if (r300->textures[i] != (struct r300_texture*)texture[i]) {
537 pipe_texture_reference((struct pipe_texture**)&r300->textures[i],
538 texture[i]);
539 r300->dirty_state |= (R300_NEW_TEXTURE << i);
540 }
541 }
542
543 for (i = count; i < 8; i++) {
544 if (r300->textures[i]) {
545 pipe_texture_reference((struct pipe_texture**)&r300->textures[i],
546 NULL);
547 r300->dirty_state |= (R300_NEW_TEXTURE << i);
548 }
549 }
550
551 r300->texture_count = count;
552 }
553
554 static void r300_set_scissor_state(struct pipe_context* pipe,
555 const struct pipe_scissor_state* state)
556 {
557 struct r300_context* r300 = r300_context(pipe);
558
559 if (r300_screen(r300->context.screen)->caps->is_r500) {
560 r300->scissor_state->scissor_top_left =
561 (state->minx << R300_SCISSORS_X_SHIFT) |
562 (state->miny << R300_SCISSORS_Y_SHIFT);
563 r300->scissor_state->scissor_bottom_right =
564 ((state->maxx - 1) << R300_SCISSORS_X_SHIFT) |
565 ((state->maxy - 1) << R300_SCISSORS_Y_SHIFT);
566 } else {
567 /* Offset of 1440 in non-R500 chipsets. */
568 r300->scissor_state->scissor_top_left =
569 ((state->minx + 1440) << R300_SCISSORS_X_SHIFT) |
570 ((state->miny + 1440) << R300_SCISSORS_Y_SHIFT);
571 r300->scissor_state->scissor_bottom_right =
572 (((state->maxx - 1) + 1440) << R300_SCISSORS_X_SHIFT) |
573 (((state->maxy - 1) + 1440) << R300_SCISSORS_Y_SHIFT);
574 }
575
576 r300->dirty_state |= R300_NEW_SCISSOR;
577 }
578
579 static void r300_set_viewport_state(struct pipe_context* pipe,
580 const struct pipe_viewport_state* state)
581 {
582 struct r300_context* r300 = r300_context(pipe);
583
584 /* Do the transform in HW. */
585 r300->viewport_state->vte_control = R300_VTX_W0_FMT;
586
587 if (state->scale[0] != 1.0f) {
588 r300->viewport_state->xscale = state->scale[0];
589 r300->viewport_state->vte_control |= R300_VPORT_X_SCALE_ENA;
590 }
591 if (state->scale[1] != 1.0f) {
592 r300->viewport_state->yscale = state->scale[1];
593 r300->viewport_state->vte_control |= R300_VPORT_Y_SCALE_ENA;
594 }
595 if (state->scale[2] != 1.0f) {
596 r300->viewport_state->zscale = state->scale[2];
597 r300->viewport_state->vte_control |= R300_VPORT_Z_SCALE_ENA;
598 }
599 if (state->translate[0] != 0.0f) {
600 r300->viewport_state->xoffset = state->translate[0];
601 r300->viewport_state->vte_control |= R300_VPORT_X_OFFSET_ENA;
602 }
603 if (state->translate[1] != 0.0f) {
604 r300->viewport_state->yoffset = state->translate[1];
605 r300->viewport_state->vte_control |= R300_VPORT_Y_OFFSET_ENA;
606 }
607 if (state->translate[2] != 0.0f) {
608 r300->viewport_state->zoffset = state->translate[2];
609 r300->viewport_state->vte_control |= R300_VPORT_Z_OFFSET_ENA;
610 }
611
612 r300->dirty_state |= R300_NEW_VIEWPORT;
613 }
614
615 static void r300_set_vertex_buffers(struct pipe_context* pipe,
616 unsigned count,
617 const struct pipe_vertex_buffer* buffers)
618 {
619 struct r300_context* r300 = r300_context(pipe);
620
621 memcpy(r300->vertex_buffers, buffers,
622 sizeof(struct pipe_vertex_buffer) * count);
623
624 r300->vertex_buffer_count = count;
625
626 draw_flush(r300->draw);
627 draw_set_vertex_buffers(r300->draw, count, buffers);
628 }
629
630 static void r300_set_vertex_elements(struct pipe_context* pipe,
631 unsigned count,
632 const struct pipe_vertex_element* elements)
633 {
634 struct r300_context* r300 = r300_context(pipe);
635
636 draw_flush(r300->draw);
637 draw_set_vertex_elements(r300->draw, count, elements);
638 }
639
640 static void* r300_create_vs_state(struct pipe_context* pipe,
641 const struct pipe_shader_state* shader)
642 {
643 struct r300_context* r300 = r300_context(pipe);
644
645 if (r300_screen(pipe->screen)->caps->has_tcl) {
646 struct r300_vertex_shader* vs = CALLOC_STRUCT(r300_vertex_shader);
647 /* Copy state directly into shader. */
648 vs->state = *shader;
649 vs->state.tokens = tgsi_dup_tokens(shader->tokens);
650
651 tgsi_scan_shader(shader->tokens, &vs->info);
652
653 /* Appease Draw. */
654 vs->draw = draw_create_vertex_shader(r300->draw, shader);
655
656 return (void*)vs;
657 } else {
658 return draw_create_vertex_shader(r300->draw, shader);
659 }
660 }
661
662 static void r300_bind_vs_state(struct pipe_context* pipe, void* shader)
663 {
664 struct r300_context* r300 = r300_context(pipe);
665
666 draw_flush(r300->draw);
667
668 if (r300_screen(pipe->screen)->caps->has_tcl) {
669 struct r300_vertex_shader* vs = (struct r300_vertex_shader*)shader;
670
671 if (vs == NULL) {
672 r300->vs = NULL;
673 return;
674 } else if (!vs->translated) {
675 r300_translate_vertex_shader(r300, vs);
676 }
677
678 draw_bind_vertex_shader(r300->draw, vs->draw);
679 r300->vs = vs;
680 r300->dirty_state |= R300_NEW_VERTEX_SHADER | R300_NEW_VERTEX_SHADER_CONSTANTS;
681 } else {
682 draw_bind_vertex_shader(r300->draw,
683 (struct draw_vertex_shader*)shader);
684 }
685 }
686
687 static void r300_delete_vs_state(struct pipe_context* pipe, void* shader)
688 {
689 struct r300_context* r300 = r300_context(pipe);
690
691 if (r300_screen(pipe->screen)->caps->has_tcl) {
692 struct r300_vertex_shader* vs = (struct r300_vertex_shader*)shader;
693
694 rc_constants_destroy(&vs->code.constants);
695 draw_delete_vertex_shader(r300->draw, vs->draw);
696 FREE((void*)vs->state.tokens);
697 FREE(shader);
698 } else {
699 draw_delete_vertex_shader(r300->draw,
700 (struct draw_vertex_shader*)shader);
701 }
702 }
703
704 static void r300_set_constant_buffer(struct pipe_context *pipe,
705 uint shader, uint index,
706 const struct pipe_constant_buffer *buf)
707 {
708 struct r300_context* r300 = r300_context(pipe);
709 void *mapped;
710
711 if (buf == NULL || buf->buffer->size == 0 ||
712 (mapped = pipe_buffer_map(pipe->screen, buf->buffer, PIPE_BUFFER_USAGE_CPU_READ)) == NULL)
713 {
714 r300->shader_constants[shader].count = 0;
715 return;
716 }
717
718 assert((buf->buffer->size % 4 * sizeof(float)) == 0);
719 memcpy(r300->shader_constants[shader].constants, mapped, buf->buffer->size);
720 r300->shader_constants[shader].count = buf->buffer->size / (4 * sizeof(float));
721 pipe_buffer_unmap(pipe->screen, buf->buffer);
722
723 if (shader == PIPE_SHADER_VERTEX)
724 r300->dirty_state |= R300_NEW_VERTEX_SHADER_CONSTANTS;
725 else if (shader == PIPE_SHADER_FRAGMENT)
726 r300->dirty_state |= R300_NEW_FRAGMENT_SHADER_CONSTANTS;
727 }
728
729 void r300_init_state_functions(struct r300_context* r300)
730 {
731 r300->context.create_blend_state = r300_create_blend_state;
732 r300->context.bind_blend_state = r300_bind_blend_state;
733 r300->context.delete_blend_state = r300_delete_blend_state;
734
735 r300->context.set_blend_color = r300_set_blend_color;
736
737 r300->context.set_clip_state = r300_set_clip_state;
738
739 r300->context.set_constant_buffer = r300_set_constant_buffer;
740
741 r300->context.create_depth_stencil_alpha_state = r300_create_dsa_state;
742 r300->context.bind_depth_stencil_alpha_state = r300_bind_dsa_state;
743 r300->context.delete_depth_stencil_alpha_state = r300_delete_dsa_state;
744
745 r300->context.set_edgeflags = r300_set_edgeflags;
746
747 r300->context.set_framebuffer_state = r300_set_framebuffer_state;
748
749 r300->context.create_fs_state = r300_create_fs_state;
750 r300->context.bind_fs_state = r300_bind_fs_state;
751 r300->context.delete_fs_state = r300_delete_fs_state;
752
753 r300->context.set_polygon_stipple = r300_set_polygon_stipple;
754
755 r300->context.create_rasterizer_state = r300_create_rs_state;
756 r300->context.bind_rasterizer_state = r300_bind_rs_state;
757 r300->context.delete_rasterizer_state = r300_delete_rs_state;
758
759 r300->context.create_sampler_state = r300_create_sampler_state;
760 r300->context.bind_sampler_states = r300_bind_sampler_states;
761 r300->context.delete_sampler_state = r300_delete_sampler_state;
762
763 r300->context.set_sampler_textures = r300_set_sampler_textures;
764
765 r300->context.set_scissor_state = r300_set_scissor_state;
766
767 r300->context.set_viewport_state = r300_set_viewport_state;
768
769 r300->context.set_vertex_buffers = r300_set_vertex_buffers;
770 r300->context.set_vertex_elements = r300_set_vertex_elements;
771
772 r300->context.create_vs_state = r300_create_vs_state;
773 r300->context.bind_vs_state = r300_bind_vs_state;
774 r300->context.delete_vs_state = r300_delete_vs_state;
775 }