r300g: take advantage of KEEP_TILING_FLAGS flush flag
[mesa.git] / src / gallium / drivers / r300 / r300_state.c
1 /*
2 * Copyright 2008 Corbin Simpson <MostAwesomeDude@gmail.com>
3 * Copyright 2009 Marek Olšák <maraeo@gmail.com>
4 *
5 * Permission is hereby granted, free of charge, to any person obtaining a
6 * copy of this software and associated documentation files (the "Software"),
7 * to deal in the Software without restriction, including without limitation
8 * on the rights to use, copy, modify, merge, publish, distribute, sub
9 * license, and/or sell copies of the Software, and to permit persons to whom
10 * the Software is furnished to do so, subject to the following conditions:
11 *
12 * The above copyright notice and this permission notice (including the next
13 * paragraph) shall be included in all copies or substantial portions of the
14 * Software.
15 *
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
19 * THE AUTHOR(S) AND/OR THEIR SUPPLIERS BE LIABLE FOR ANY CLAIM,
20 * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
21 * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
22 * USE OR OTHER DEALINGS IN THE SOFTWARE. */
23
24 #include "draw/draw_context.h"
25
26 #include "util/u_framebuffer.h"
27 #include "util/u_half.h"
28 #include "util/u_math.h"
29 #include "util/u_mm.h"
30 #include "util/u_memory.h"
31 #include "util/u_pack_color.h"
32 #include "util/u_transfer.h"
33
34 #include "tgsi/tgsi_parse.h"
35
36 #include "pipe/p_config.h"
37
38 #include "r300_cb.h"
39 #include "r300_context.h"
40 #include "r300_emit.h"
41 #include "r300_reg.h"
42 #include "r300_screen.h"
43 #include "r300_screen_buffer.h"
44 #include "r300_state_inlines.h"
45 #include "r300_fs.h"
46 #include "r300_texture.h"
47 #include "r300_vs.h"
48
49 /* r300_state: Functions used to intialize state context by translating
50 * Gallium state objects into semi-native r300 state objects. */
51
52 #define UPDATE_STATE(cso, atom) \
53 if (cso != atom.state) { \
54 atom.state = cso; \
55 r300_mark_atom_dirty(r300, &(atom)); \
56 }
57
58 static boolean blend_discard_if_src_alpha_0(unsigned srcRGB, unsigned srcA,
59 unsigned dstRGB, unsigned dstA)
60 {
61 /* If the blend equation is ADD or REVERSE_SUBTRACT,
62 * SRC_ALPHA == 0, and the following state is set, the colorbuffer
63 * will not be changed.
64 * Notice that the dst factors are the src factors inverted. */
65 return (srcRGB == PIPE_BLENDFACTOR_SRC_ALPHA ||
66 srcRGB == PIPE_BLENDFACTOR_SRC_ALPHA_SATURATE ||
67 srcRGB == PIPE_BLENDFACTOR_ZERO) &&
68 (srcA == PIPE_BLENDFACTOR_SRC_COLOR ||
69 srcA == PIPE_BLENDFACTOR_SRC_ALPHA ||
70 srcA == PIPE_BLENDFACTOR_SRC_ALPHA_SATURATE ||
71 srcA == PIPE_BLENDFACTOR_ZERO) &&
72 (dstRGB == PIPE_BLENDFACTOR_INV_SRC_ALPHA ||
73 dstRGB == PIPE_BLENDFACTOR_ONE) &&
74 (dstA == PIPE_BLENDFACTOR_INV_SRC_COLOR ||
75 dstA == PIPE_BLENDFACTOR_INV_SRC_ALPHA ||
76 dstA == PIPE_BLENDFACTOR_ONE);
77 }
78
79 static boolean blend_discard_if_src_alpha_1(unsigned srcRGB, unsigned srcA,
80 unsigned dstRGB, unsigned dstA)
81 {
82 /* If the blend equation is ADD or REVERSE_SUBTRACT,
83 * SRC_ALPHA == 1, and the following state is set, the colorbuffer
84 * will not be changed.
85 * Notice that the dst factors are the src factors inverted. */
86 return (srcRGB == PIPE_BLENDFACTOR_INV_SRC_ALPHA ||
87 srcRGB == PIPE_BLENDFACTOR_ZERO) &&
88 (srcA == PIPE_BLENDFACTOR_INV_SRC_COLOR ||
89 srcA == PIPE_BLENDFACTOR_INV_SRC_ALPHA ||
90 srcA == PIPE_BLENDFACTOR_ZERO) &&
91 (dstRGB == PIPE_BLENDFACTOR_SRC_ALPHA ||
92 dstRGB == PIPE_BLENDFACTOR_ONE) &&
93 (dstA == PIPE_BLENDFACTOR_SRC_COLOR ||
94 dstA == PIPE_BLENDFACTOR_SRC_ALPHA ||
95 dstA == PIPE_BLENDFACTOR_ONE);
96 }
97
98 static boolean blend_discard_if_src_color_0(unsigned srcRGB, unsigned srcA,
99 unsigned dstRGB, unsigned dstA)
100 {
101 /* If the blend equation is ADD or REVERSE_SUBTRACT,
102 * SRC_COLOR == (0,0,0), and the following state is set, the colorbuffer
103 * will not be changed.
104 * Notice that the dst factors are the src factors inverted. */
105 return (srcRGB == PIPE_BLENDFACTOR_SRC_COLOR ||
106 srcRGB == PIPE_BLENDFACTOR_ZERO) &&
107 (srcA == PIPE_BLENDFACTOR_ZERO) &&
108 (dstRGB == PIPE_BLENDFACTOR_INV_SRC_COLOR ||
109 dstRGB == PIPE_BLENDFACTOR_ONE) &&
110 (dstA == PIPE_BLENDFACTOR_ONE);
111 }
112
113 static boolean blend_discard_if_src_color_1(unsigned srcRGB, unsigned srcA,
114 unsigned dstRGB, unsigned dstA)
115 {
116 /* If the blend equation is ADD or REVERSE_SUBTRACT,
117 * SRC_COLOR == (1,1,1), and the following state is set, the colorbuffer
118 * will not be changed.
119 * Notice that the dst factors are the src factors inverted. */
120 return (srcRGB == PIPE_BLENDFACTOR_INV_SRC_COLOR ||
121 srcRGB == PIPE_BLENDFACTOR_ZERO) &&
122 (srcA == PIPE_BLENDFACTOR_ZERO) &&
123 (dstRGB == PIPE_BLENDFACTOR_SRC_COLOR ||
124 dstRGB == PIPE_BLENDFACTOR_ONE) &&
125 (dstA == PIPE_BLENDFACTOR_ONE);
126 }
127
128 static boolean blend_discard_if_src_alpha_color_0(unsigned srcRGB, unsigned srcA,
129 unsigned dstRGB, unsigned dstA)
130 {
131 /* If the blend equation is ADD or REVERSE_SUBTRACT,
132 * SRC_ALPHA_COLOR == (0,0,0,0), and the following state is set,
133 * the colorbuffer will not be changed.
134 * Notice that the dst factors are the src factors inverted. */
135 return (srcRGB == PIPE_BLENDFACTOR_SRC_COLOR ||
136 srcRGB == PIPE_BLENDFACTOR_SRC_ALPHA ||
137 srcRGB == PIPE_BLENDFACTOR_SRC_ALPHA_SATURATE ||
138 srcRGB == PIPE_BLENDFACTOR_ZERO) &&
139 (srcA == PIPE_BLENDFACTOR_SRC_COLOR ||
140 srcA == PIPE_BLENDFACTOR_SRC_ALPHA ||
141 srcA == PIPE_BLENDFACTOR_SRC_ALPHA_SATURATE ||
142 srcA == PIPE_BLENDFACTOR_ZERO) &&
143 (dstRGB == PIPE_BLENDFACTOR_INV_SRC_COLOR ||
144 dstRGB == PIPE_BLENDFACTOR_INV_SRC_ALPHA ||
145 dstRGB == PIPE_BLENDFACTOR_ONE) &&
146 (dstA == PIPE_BLENDFACTOR_INV_SRC_COLOR ||
147 dstA == PIPE_BLENDFACTOR_INV_SRC_ALPHA ||
148 dstA == PIPE_BLENDFACTOR_ONE);
149 }
150
151 static boolean blend_discard_if_src_alpha_color_1(unsigned srcRGB, unsigned srcA,
152 unsigned dstRGB, unsigned dstA)
153 {
154 /* If the blend equation is ADD or REVERSE_SUBTRACT,
155 * SRC_ALPHA_COLOR == (1,1,1,1), and the following state is set,
156 * the colorbuffer will not be changed.
157 * Notice that the dst factors are the src factors inverted. */
158 return (srcRGB == PIPE_BLENDFACTOR_INV_SRC_COLOR ||
159 srcRGB == PIPE_BLENDFACTOR_INV_SRC_ALPHA ||
160 srcRGB == PIPE_BLENDFACTOR_ZERO) &&
161 (srcA == PIPE_BLENDFACTOR_INV_SRC_COLOR ||
162 srcA == PIPE_BLENDFACTOR_INV_SRC_ALPHA ||
163 srcA == PIPE_BLENDFACTOR_ZERO) &&
164 (dstRGB == PIPE_BLENDFACTOR_SRC_COLOR ||
165 dstRGB == PIPE_BLENDFACTOR_SRC_ALPHA ||
166 dstRGB == PIPE_BLENDFACTOR_ONE) &&
167 (dstA == PIPE_BLENDFACTOR_SRC_COLOR ||
168 dstA == PIPE_BLENDFACTOR_SRC_ALPHA ||
169 dstA == PIPE_BLENDFACTOR_ONE);
170 }
171
172 static unsigned bgra_cmask(unsigned mask)
173 {
174 /* Gallium uses RGBA color ordering while R300 expects BGRA. */
175
176 return ((mask & PIPE_MASK_R) << 2) |
177 ((mask & PIPE_MASK_B) >> 2) |
178 (mask & (PIPE_MASK_G | PIPE_MASK_A));
179 }
180
181 /* Create a new blend state based on the CSO blend state.
182 *
183 * This encompasses alpha blending, logic/raster ops, and blend dithering. */
184 static void* r300_create_blend_state(struct pipe_context* pipe,
185 const struct pipe_blend_state* state)
186 {
187 struct r300_screen* r300screen = r300_screen(pipe->screen);
188 struct r300_blend_state* blend = CALLOC_STRUCT(r300_blend_state);
189 uint32_t blend_control = 0; /* R300_RB3D_CBLEND: 0x4e04 */
190 uint32_t blend_control_noclamp = 0; /* R300_RB3D_CBLEND: 0x4e04 */
191 uint32_t alpha_blend_control = 0; /* R300_RB3D_ABLEND: 0x4e08 */
192 uint32_t alpha_blend_control_noclamp = 0; /* R300_RB3D_ABLEND: 0x4e08 */
193 uint32_t color_channel_mask = 0; /* R300_RB3D_COLOR_CHANNEL_MASK: 0x4e0c */
194 uint32_t rop = 0; /* R300_RB3D_ROPCNTL: 0x4e18 */
195 uint32_t dither = 0; /* R300_RB3D_DITHER_CTL: 0x4e50 */
196 CB_LOCALS;
197
198 blend->state = *state;
199
200 if (state->rt[0].blend_enable)
201 {
202 unsigned eqRGB = state->rt[0].rgb_func;
203 unsigned srcRGB = state->rt[0].rgb_src_factor;
204 unsigned dstRGB = state->rt[0].rgb_dst_factor;
205
206 unsigned eqA = state->rt[0].alpha_func;
207 unsigned srcA = state->rt[0].alpha_src_factor;
208 unsigned dstA = state->rt[0].alpha_dst_factor;
209
210 /* despite the name, ALPHA_BLEND_ENABLE has nothing to do with alpha,
211 * this is just the crappy D3D naming */
212 blend_control = blend_control_noclamp =
213 R300_ALPHA_BLEND_ENABLE |
214 ( r300_translate_blend_factor(srcRGB) << R300_SRC_BLEND_SHIFT) |
215 ( r300_translate_blend_factor(dstRGB) << R300_DST_BLEND_SHIFT);
216 blend_control |=
217 r300_translate_blend_function(eqRGB, TRUE);
218 blend_control_noclamp |=
219 r300_translate_blend_function(eqRGB, FALSE);
220
221 /* Optimization: some operations do not require the destination color.
222 *
223 * When SRC_ALPHA_SATURATE is used, colorbuffer reads must be enabled,
224 * otherwise blending gives incorrect results. It seems to be
225 * a hardware bug. */
226 if (eqRGB == PIPE_BLEND_MIN || eqA == PIPE_BLEND_MIN ||
227 eqRGB == PIPE_BLEND_MAX || eqA == PIPE_BLEND_MAX ||
228 dstRGB != PIPE_BLENDFACTOR_ZERO ||
229 dstA != PIPE_BLENDFACTOR_ZERO ||
230 srcRGB == PIPE_BLENDFACTOR_DST_COLOR ||
231 srcRGB == PIPE_BLENDFACTOR_DST_ALPHA ||
232 srcRGB == PIPE_BLENDFACTOR_INV_DST_COLOR ||
233 srcRGB == PIPE_BLENDFACTOR_INV_DST_ALPHA ||
234 srcA == PIPE_BLENDFACTOR_DST_COLOR ||
235 srcA == PIPE_BLENDFACTOR_DST_ALPHA ||
236 srcA == PIPE_BLENDFACTOR_INV_DST_COLOR ||
237 srcA == PIPE_BLENDFACTOR_INV_DST_ALPHA ||
238 srcRGB == PIPE_BLENDFACTOR_SRC_ALPHA_SATURATE) {
239 /* Enable reading from the colorbuffer. */
240 blend_control |= R300_READ_ENABLE;
241 blend_control_noclamp |= R300_READ_ENABLE;
242
243 if (r300screen->caps.is_r500) {
244 /* Optimization: Depending on incoming pixels, we can
245 * conditionally disable the reading in hardware... */
246 if (eqRGB != PIPE_BLEND_MIN && eqA != PIPE_BLEND_MIN &&
247 eqRGB != PIPE_BLEND_MAX && eqA != PIPE_BLEND_MAX) {
248 /* Disable reading if SRC_ALPHA == 0. */
249 if ((dstRGB == PIPE_BLENDFACTOR_SRC_ALPHA ||
250 dstRGB == PIPE_BLENDFACTOR_ZERO) &&
251 (dstA == PIPE_BLENDFACTOR_SRC_COLOR ||
252 dstA == PIPE_BLENDFACTOR_SRC_ALPHA ||
253 dstA == PIPE_BLENDFACTOR_ZERO)) {
254 blend_control |= R500_SRC_ALPHA_0_NO_READ;
255 }
256
257 /* Disable reading if SRC_ALPHA == 1. */
258 if ((dstRGB == PIPE_BLENDFACTOR_INV_SRC_ALPHA ||
259 dstRGB == PIPE_BLENDFACTOR_ZERO) &&
260 (dstA == PIPE_BLENDFACTOR_INV_SRC_COLOR ||
261 dstA == PIPE_BLENDFACTOR_INV_SRC_ALPHA ||
262 dstA == PIPE_BLENDFACTOR_ZERO)) {
263 blend_control |= R500_SRC_ALPHA_1_NO_READ;
264 }
265 }
266 }
267 }
268
269 /* Optimization: discard pixels which don't change the colorbuffer.
270 *
271 * The code below is non-trivial and some math is involved.
272 *
273 * Discarding pixels must be disabled when FP16 AA is enabled.
274 * This is a hardware bug. Also, this implementation wouldn't work
275 * with FP blending enabled and equation clamping disabled.
276 *
277 * Equations other than ADD are rarely used and therefore won't be
278 * optimized. */
279 if ((eqRGB == PIPE_BLEND_ADD || eqRGB == PIPE_BLEND_REVERSE_SUBTRACT) &&
280 (eqA == PIPE_BLEND_ADD || eqA == PIPE_BLEND_REVERSE_SUBTRACT)) {
281 /* ADD: X+Y
282 * REVERSE_SUBTRACT: Y-X
283 *
284 * The idea is:
285 * If X = src*srcFactor = 0 and Y = dst*dstFactor = 1,
286 * then CB will not be changed.
287 *
288 * Given the srcFactor and dstFactor variables, we can derive
289 * what src and dst should be equal to and discard appropriate
290 * pixels.
291 */
292 if (blend_discard_if_src_alpha_0(srcRGB, srcA, dstRGB, dstA)) {
293 blend_control |= R300_DISCARD_SRC_PIXELS_SRC_ALPHA_0;
294 } else if (blend_discard_if_src_alpha_1(srcRGB, srcA,
295 dstRGB, dstA)) {
296 blend_control |= R300_DISCARD_SRC_PIXELS_SRC_ALPHA_1;
297 } else if (blend_discard_if_src_color_0(srcRGB, srcA,
298 dstRGB, dstA)) {
299 blend_control |= R300_DISCARD_SRC_PIXELS_SRC_COLOR_0;
300 } else if (blend_discard_if_src_color_1(srcRGB, srcA,
301 dstRGB, dstA)) {
302 blend_control |= R300_DISCARD_SRC_PIXELS_SRC_COLOR_1;
303 } else if (blend_discard_if_src_alpha_color_0(srcRGB, srcA,
304 dstRGB, dstA)) {
305 blend_control |=
306 R300_DISCARD_SRC_PIXELS_SRC_ALPHA_COLOR_0;
307 } else if (blend_discard_if_src_alpha_color_1(srcRGB, srcA,
308 dstRGB, dstA)) {
309 blend_control |=
310 R300_DISCARD_SRC_PIXELS_SRC_ALPHA_COLOR_1;
311 }
312 }
313
314 /* separate alpha */
315 if (srcA != srcRGB || dstA != dstRGB || eqA != eqRGB) {
316 blend_control |= R300_SEPARATE_ALPHA_ENABLE;
317 blend_control_noclamp |= R300_SEPARATE_ALPHA_ENABLE;
318 alpha_blend_control = alpha_blend_control_noclamp =
319 (r300_translate_blend_factor(srcA) << R300_SRC_BLEND_SHIFT) |
320 (r300_translate_blend_factor(dstA) << R300_DST_BLEND_SHIFT);
321 alpha_blend_control |=
322 r300_translate_blend_function(eqA, TRUE);
323 alpha_blend_control_noclamp |=
324 r300_translate_blend_function(eqA, FALSE);
325 }
326 }
327
328 /* PIPE_LOGICOP_* don't need to be translated, fortunately. */
329 if (state->logicop_enable) {
330 rop = R300_RB3D_ROPCNTL_ROP_ENABLE |
331 (state->logicop_func) << R300_RB3D_ROPCNTL_ROP_SHIFT;
332 }
333
334 /* Color channel masks for all MRTs. */
335 color_channel_mask = bgra_cmask(state->rt[0].colormask);
336 if (r300screen->caps.is_r500 && state->independent_blend_enable) {
337 if (state->rt[1].blend_enable) {
338 color_channel_mask |= bgra_cmask(state->rt[1].colormask) << 4;
339 }
340 if (state->rt[2].blend_enable) {
341 color_channel_mask |= bgra_cmask(state->rt[2].colormask) << 8;
342 }
343 if (state->rt[3].blend_enable) {
344 color_channel_mask |= bgra_cmask(state->rt[3].colormask) << 12;
345 }
346 }
347
348 /* Neither fglrx nor classic r300 ever set this, regardless of dithering
349 * state. Since it's an optional implementation detail, we can leave it
350 * out and never dither.
351 *
352 * This could be revisited if we ever get quality or conformance hints.
353 *
354 if (state->dither) {
355 dither = R300_RB3D_DITHER_CTL_DITHER_MODE_LUT |
356 R300_RB3D_DITHER_CTL_ALPHA_DITHER_MODE_LUT;
357 }
358 */
359
360 /* Build a command buffer. */
361 BEGIN_CB(blend->cb_clamp, 8);
362 OUT_CB_REG(R300_RB3D_ROPCNTL, rop);
363 OUT_CB_REG_SEQ(R300_RB3D_CBLEND, 3);
364 OUT_CB(blend_control);
365 OUT_CB(alpha_blend_control);
366 OUT_CB(color_channel_mask);
367 OUT_CB_REG(R300_RB3D_DITHER_CTL, dither);
368 END_CB;
369
370 /* Build a command buffer. */
371 BEGIN_CB(blend->cb_noclamp, 8);
372 OUT_CB_REG(R300_RB3D_ROPCNTL, rop);
373 OUT_CB_REG_SEQ(R300_RB3D_CBLEND, 3);
374 OUT_CB(blend_control_noclamp);
375 OUT_CB(alpha_blend_control_noclamp);
376 OUT_CB(color_channel_mask);
377 OUT_CB_REG(R300_RB3D_DITHER_CTL, dither);
378 END_CB;
379
380 /* The same as above, but with no colorbuffer reads and writes. */
381 BEGIN_CB(blend->cb_no_readwrite, 8);
382 OUT_CB_REG(R300_RB3D_ROPCNTL, rop);
383 OUT_CB_REG_SEQ(R300_RB3D_CBLEND, 3);
384 OUT_CB(0);
385 OUT_CB(0);
386 OUT_CB(0);
387 OUT_CB_REG(R300_RB3D_DITHER_CTL, dither);
388 END_CB;
389
390 return (void*)blend;
391 }
392
393 /* Bind blend state. */
394 static void r300_bind_blend_state(struct pipe_context* pipe,
395 void* state)
396 {
397 struct r300_context* r300 = r300_context(pipe);
398
399 UPDATE_STATE(state, r300->blend_state);
400 }
401
402 /* Free blend state. */
403 static void r300_delete_blend_state(struct pipe_context* pipe,
404 void* state)
405 {
406 FREE(state);
407 }
408
409 /* Convert float to 10bit integer */
410 static unsigned float_to_fixed10(float f)
411 {
412 return CLAMP((unsigned)(f * 1023.9f), 0, 1023);
413 }
414
415 /* Set blend color.
416 * Setup both R300 and R500 registers, figure out later which one to write. */
417 static void r300_set_blend_color(struct pipe_context* pipe,
418 const struct pipe_blend_color* color)
419 {
420 struct r300_context* r300 = r300_context(pipe);
421 struct pipe_framebuffer_state *fb = r300->fb_state.state;
422 struct r300_blend_color_state *state =
423 (struct r300_blend_color_state*)r300->blend_color_state.state;
424 struct pipe_blend_color c;
425 enum pipe_format format = fb->nr_cbufs ? fb->cbufs[0]->format : 0;
426 CB_LOCALS;
427
428 state->state = *color; /* Save it, so that we can reuse it in set_fb_state */
429 c = *color;
430
431 /* The blend color is dependent on the colorbuffer format. */
432 if (fb->nr_cbufs) {
433 switch (format) {
434 case PIPE_FORMAT_R8_UNORM:
435 case PIPE_FORMAT_L8_UNORM:
436 case PIPE_FORMAT_I8_UNORM:
437 c.color[1] = c.color[0];
438 break;
439
440 case PIPE_FORMAT_A8_UNORM:
441 c.color[1] = c.color[3];
442 break;
443
444 case PIPE_FORMAT_R8G8_UNORM:
445 c.color[2] = c.color[1];
446 break;
447
448 case PIPE_FORMAT_L8A8_UNORM:
449 c.color[2] = c.color[3];
450 break;
451
452 default:;
453 }
454 }
455
456 if (r300->screen->caps.is_r500) {
457 BEGIN_CB(state->cb, 3);
458 OUT_CB_REG_SEQ(R500_RB3D_CONSTANT_COLOR_AR, 2);
459
460 switch (format) {
461 case PIPE_FORMAT_R16G16B16A16_FLOAT:
462 OUT_CB(util_float_to_half(c.color[2]) |
463 (util_float_to_half(c.color[3]) << 16));
464 OUT_CB(util_float_to_half(c.color[0]) |
465 (util_float_to_half(c.color[1]) << 16));
466 break;
467
468 default:
469 OUT_CB(float_to_fixed10(c.color[0]) |
470 (float_to_fixed10(c.color[3]) << 16));
471 OUT_CB(float_to_fixed10(c.color[2]) |
472 (float_to_fixed10(c.color[1]) << 16));
473 }
474
475 END_CB;
476 } else {
477 union util_color uc;
478 util_pack_color(c.color, PIPE_FORMAT_B8G8R8A8_UNORM, &uc);
479
480 BEGIN_CB(state->cb, 2);
481 OUT_CB_REG(R300_RB3D_BLEND_COLOR, uc.ui);
482 END_CB;
483 }
484
485 r300_mark_atom_dirty(r300, &r300->blend_color_state);
486 }
487
488 static void r300_set_clip_state(struct pipe_context* pipe,
489 const struct pipe_clip_state* state)
490 {
491 struct r300_context* r300 = r300_context(pipe);
492 struct r300_clip_state *clip =
493 (struct r300_clip_state*)r300->clip_state.state;
494 CB_LOCALS;
495
496 clip->clip = *state;
497
498 if (r300->screen->caps.has_tcl) {
499 r300->clip_state.size = 2 + !!state->nr * 3 + state->nr * 4;
500
501 BEGIN_CB(clip->cb, r300->clip_state.size);
502 if (state->nr) {
503 OUT_CB_REG(R300_VAP_PVS_VECTOR_INDX_REG,
504 (r300->screen->caps.is_r500 ?
505 R500_PVS_UCP_START : R300_PVS_UCP_START));
506 OUT_CB_ONE_REG(R300_VAP_PVS_UPLOAD_DATA, state->nr * 4);
507 OUT_CB_TABLE(state->ucp, state->nr * 4);
508 }
509 OUT_CB_REG(R300_VAP_CLIP_CNTL, ((1 << state->nr) - 1) |
510 R300_PS_UCP_MODE_CLIP_AS_TRIFAN);
511 END_CB;
512
513 r300_mark_atom_dirty(r300, &r300->clip_state);
514 } else {
515 draw_set_clip_state(r300->draw, state);
516 }
517 }
518
519 static void
520 r300_set_sample_mask(struct pipe_context *pipe,
521 unsigned sample_mask)
522 {
523 }
524
525
526 /* Create a new depth, stencil, and alpha state based on the CSO dsa state.
527 *
528 * This contains the depth buffer, stencil buffer, alpha test, and such.
529 * On the Radeon, depth and stencil buffer setup are intertwined, which is
530 * the reason for some of the strange-looking assignments across registers. */
531 static void*
532 r300_create_dsa_state(struct pipe_context* pipe,
533 const struct pipe_depth_stencil_alpha_state* state)
534 {
535 struct r300_capabilities *caps = &r300_screen(pipe->screen)->caps;
536 struct r300_dsa_state* dsa = CALLOC_STRUCT(r300_dsa_state);
537 CB_LOCALS;
538
539 dsa->dsa = *state;
540
541 /* Depth test setup. - separate write mask depth for decomp flush */
542 if (state->depth.writemask) {
543 dsa->z_buffer_control |= R300_Z_WRITE_ENABLE;
544 }
545
546 if (state->depth.enabled) {
547 dsa->z_buffer_control |= R300_Z_ENABLE;
548
549 dsa->z_stencil_control |=
550 (r300_translate_depth_stencil_function(state->depth.func) <<
551 R300_Z_FUNC_SHIFT);
552 } else {
553 /* We must enable depth test, otherwise occlusion queries won't work. */
554 dsa->z_buffer_control |= R300_Z_ENABLE;
555 dsa->z_stencil_control |= R300_ZS_ALWAYS;
556 }
557
558 /* Stencil buffer setup. */
559 if (state->stencil[0].enabled) {
560 dsa->z_buffer_control |= R300_STENCIL_ENABLE;
561 dsa->z_stencil_control |=
562 (r300_translate_depth_stencil_function(state->stencil[0].func) <<
563 R300_S_FRONT_FUNC_SHIFT) |
564 (r300_translate_stencil_op(state->stencil[0].fail_op) <<
565 R300_S_FRONT_SFAIL_OP_SHIFT) |
566 (r300_translate_stencil_op(state->stencil[0].zpass_op) <<
567 R300_S_FRONT_ZPASS_OP_SHIFT) |
568 (r300_translate_stencil_op(state->stencil[0].zfail_op) <<
569 R300_S_FRONT_ZFAIL_OP_SHIFT);
570
571 dsa->stencil_ref_mask =
572 (state->stencil[0].valuemask << R300_STENCILMASK_SHIFT) |
573 (state->stencil[0].writemask << R300_STENCILWRITEMASK_SHIFT);
574
575 if (state->stencil[1].enabled) {
576 dsa->two_sided = TRUE;
577
578 dsa->z_buffer_control |= R300_STENCIL_FRONT_BACK;
579 dsa->z_stencil_control |=
580 (r300_translate_depth_stencil_function(state->stencil[1].func) <<
581 R300_S_BACK_FUNC_SHIFT) |
582 (r300_translate_stencil_op(state->stencil[1].fail_op) <<
583 R300_S_BACK_SFAIL_OP_SHIFT) |
584 (r300_translate_stencil_op(state->stencil[1].zpass_op) <<
585 R300_S_BACK_ZPASS_OP_SHIFT) |
586 (r300_translate_stencil_op(state->stencil[1].zfail_op) <<
587 R300_S_BACK_ZFAIL_OP_SHIFT);
588
589 dsa->stencil_ref_bf =
590 (state->stencil[1].valuemask << R300_STENCILMASK_SHIFT) |
591 (state->stencil[1].writemask << R300_STENCILWRITEMASK_SHIFT);
592
593 if (caps->is_r500) {
594 dsa->z_buffer_control |= R500_STENCIL_REFMASK_FRONT_BACK;
595 } else {
596 dsa->two_sided_stencil_ref =
597 (state->stencil[0].valuemask != state->stencil[1].valuemask ||
598 state->stencil[0].writemask != state->stencil[1].writemask);
599 }
600 }
601 }
602
603 /* Alpha test setup. */
604 if (state->alpha.enabled) {
605 dsa->alpha_function =
606 r300_translate_alpha_function(state->alpha.func) |
607 R300_FG_ALPHA_FUNC_ENABLE;
608
609 dsa->alpha_function |= float_to_ubyte(state->alpha.ref_value);
610 dsa->alpha_value = util_float_to_half(state->alpha.ref_value);
611
612 if (caps->is_r500) {
613 dsa->alpha_function_fp16 = dsa->alpha_function |
614 R500_FG_ALPHA_FUNC_FP16_ENABLE;
615 dsa->alpha_function |= R500_FG_ALPHA_FUNC_8BIT;
616 }
617 }
618
619 BEGIN_CB(&dsa->cb_begin, 10);
620 OUT_CB_REG(R300_FG_ALPHA_FUNC, dsa->alpha_function);
621 OUT_CB_REG_SEQ(R300_ZB_CNTL, 3);
622 OUT_CB(dsa->z_buffer_control);
623 OUT_CB(dsa->z_stencil_control);
624 OUT_CB(dsa->stencil_ref_mask);
625 OUT_CB_REG(R500_ZB_STENCILREFMASK_BF, dsa->stencil_ref_bf);
626 OUT_CB_REG(R500_FG_ALPHA_VALUE, dsa->alpha_value);
627 END_CB;
628
629 BEGIN_CB(&dsa->cb_begin_fp16, 10);
630 OUT_CB_REG(R300_FG_ALPHA_FUNC, dsa->alpha_function_fp16);
631 OUT_CB_REG_SEQ(R300_ZB_CNTL, 3);
632 OUT_CB(dsa->z_buffer_control);
633 OUT_CB(dsa->z_stencil_control);
634 OUT_CB(dsa->stencil_ref_mask);
635 OUT_CB_REG(R500_ZB_STENCILREFMASK_BF, dsa->stencil_ref_bf);
636 OUT_CB_REG(R500_FG_ALPHA_VALUE, dsa->alpha_value);
637 END_CB;
638
639 /* We must enable depth test, otherwise occlusion queries won't work.
640 * We setup a dummy zbuffer to silent the CS checker, see emit_fb_state. */
641 BEGIN_CB(dsa->cb_zb_no_readwrite, 10);
642 OUT_CB_REG(R300_FG_ALPHA_FUNC, dsa->alpha_function);
643 OUT_CB_REG_SEQ(R300_ZB_CNTL, 3);
644 OUT_CB(R300_Z_ENABLE);
645 OUT_CB(R300_ZS_ALWAYS);
646 OUT_CB(0);
647 OUT_CB_REG(R500_ZB_STENCILREFMASK_BF, 0);
648 OUT_CB_REG(R500_FG_ALPHA_VALUE, dsa->alpha_value);
649 END_CB;
650
651 BEGIN_CB(dsa->cb_fp16_zb_no_readwrite, 10);
652 OUT_CB_REG(R300_FG_ALPHA_FUNC, dsa->alpha_function_fp16);
653 OUT_CB_REG_SEQ(R300_ZB_CNTL, 3);
654 OUT_CB(R300_Z_ENABLE);
655 OUT_CB(R300_ZS_ALWAYS);
656 OUT_CB(0);
657 OUT_CB_REG(R500_ZB_STENCILREFMASK_BF, 0);
658 OUT_CB_REG(R500_FG_ALPHA_VALUE, dsa->alpha_value);
659 END_CB;
660
661 return (void*)dsa;
662 }
663
664 static void r300_dsa_inject_stencilref(struct r300_context *r300)
665 {
666 struct r300_dsa_state *dsa =
667 (struct r300_dsa_state*)r300->dsa_state.state;
668
669 if (!dsa)
670 return;
671
672 dsa->stencil_ref_mask =
673 (dsa->stencil_ref_mask & ~R300_STENCILREF_MASK) |
674 r300->stencil_ref.ref_value[0];
675 dsa->stencil_ref_bf =
676 (dsa->stencil_ref_bf & ~R300_STENCILREF_MASK) |
677 r300->stencil_ref.ref_value[1];
678 }
679
680 /* Bind DSA state. */
681 static void r300_bind_dsa_state(struct pipe_context* pipe,
682 void* state)
683 {
684 struct r300_context* r300 = r300_context(pipe);
685
686 if (!state) {
687 return;
688 }
689
690 UPDATE_STATE(state, r300->dsa_state);
691
692 r300_mark_atom_dirty(r300, &r300->hyperz_state); /* Will be updated before the emission. */
693 r300_dsa_inject_stencilref(r300);
694 }
695
696 /* Free DSA state. */
697 static void r300_delete_dsa_state(struct pipe_context* pipe,
698 void* state)
699 {
700 FREE(state);
701 }
702
703 static void r300_set_stencil_ref(struct pipe_context* pipe,
704 const struct pipe_stencil_ref* sr)
705 {
706 struct r300_context* r300 = r300_context(pipe);
707
708 r300->stencil_ref = *sr;
709
710 r300_dsa_inject_stencilref(r300);
711 r300_mark_atom_dirty(r300, &r300->dsa_state);
712 }
713
714 static void r300_tex_set_tiling_flags(struct r300_context *r300,
715 struct r300_resource *tex,
716 unsigned level)
717 {
718 /* Check if the macrotile flag needs to be changed.
719 * Skip changing the flags otherwise. */
720 if (tex->tex.macrotile[tex->surface_level] !=
721 tex->tex.macrotile[level]) {
722 r300->rws->buffer_set_tiling(tex->buf, r300->cs,
723 tex->tex.microtile, tex->tex.macrotile[level],
724 tex->tex.stride_in_bytes[0]);
725
726 tex->surface_level = level;
727 }
728 }
729
730 /* This switcheroo is needed just because of goddamned MACRO_SWITCH. */
731 static void r300_fb_set_tiling_flags(struct r300_context *r300,
732 const struct pipe_framebuffer_state *state)
733 {
734 unsigned i;
735
736 /* Set tiling flags for new surfaces. */
737 for (i = 0; i < state->nr_cbufs; i++) {
738 r300_tex_set_tiling_flags(r300,
739 r300_resource(state->cbufs[i]->texture),
740 state->cbufs[i]->u.tex.level);
741 }
742 if (state->zsbuf) {
743 r300_tex_set_tiling_flags(r300,
744 r300_resource(state->zsbuf->texture),
745 state->zsbuf->u.tex.level);
746 }
747 }
748
749 static void r300_print_fb_surf_info(struct pipe_surface *surf, unsigned index,
750 const char *binding)
751 {
752 struct pipe_resource *tex = surf->texture;
753 struct r300_resource *rtex = r300_resource(tex);
754
755 fprintf(stderr,
756 "r300: %s[%i] Dim: %ix%i, Firstlayer: %i, "
757 "Lastlayer: %i, Level: %i, Format: %s\n"
758
759 "r300: TEX: Macro: %s, Micro: %s, Pitch: %i, "
760 "Dim: %ix%ix%i, LastLevel: %i, Format: %s\n",
761
762 binding, index, surf->width, surf->height,
763 surf->u.tex.first_layer, surf->u.tex.last_layer, surf->u.tex.level,
764 util_format_short_name(surf->format),
765
766 rtex->tex.macrotile[0] ? "YES" : " NO",
767 rtex->tex.microtile ? "YES" : " NO",
768 rtex->tex.stride_in_pixels[0],
769 tex->width0, tex->height0, tex->depth0,
770 tex->last_level, util_format_short_name(tex->format));
771 }
772
773 void r300_mark_fb_state_dirty(struct r300_context *r300,
774 enum r300_fb_state_change change)
775 {
776 struct pipe_framebuffer_state *state = r300->fb_state.state;
777
778 r300_mark_atom_dirty(r300, &r300->gpu_flush);
779 r300_mark_atom_dirty(r300, &r300->fb_state);
780
781 /* What is marked as dirty depends on the enum r300_fb_state_change. */
782 if (change == R300_CHANGED_FB_STATE) {
783 r300_mark_atom_dirty(r300, &r300->aa_state);
784 r300_mark_atom_dirty(r300, &r300->dsa_state); /* for AlphaRef */
785 r300_set_blend_color(&r300->context, r300->blend_color_state.state);
786 }
787
788 if (change == R300_CHANGED_FB_STATE ||
789 change == R300_CHANGED_HYPERZ_FLAG) {
790 r300_mark_atom_dirty(r300, &r300->hyperz_state);
791 }
792
793 if (change == R300_CHANGED_FB_STATE ||
794 change == R300_CHANGED_MULTIWRITE) {
795 r300_mark_atom_dirty(r300, &r300->fb_state_pipelined);
796 }
797
798 /* Now compute the fb_state atom size. */
799 r300->fb_state.size = 2 + (8 * state->nr_cbufs);
800
801 if (r300->cbzb_clear) {
802 r300->fb_state.size += 10;
803 } else if (state->zsbuf) {
804 r300->fb_state.size += 10;
805 if (r300->hyperz_enabled)
806 r300->fb_state.size += 8;
807 } else if (state->nr_cbufs) {
808 r300->fb_state.size += 10;
809 }
810
811 /* The size of the rest of atoms stays the same. */
812 }
813
814 static void
815 r300_set_framebuffer_state(struct pipe_context* pipe,
816 const struct pipe_framebuffer_state* state)
817 {
818 struct r300_context* r300 = r300_context(pipe);
819 struct r300_aa_state *aa = (struct r300_aa_state*)r300->aa_state.state;
820 struct pipe_framebuffer_state *old_state = r300->fb_state.state;
821 unsigned max_width, max_height, i;
822 uint32_t zbuffer_bpp = 0;
823 boolean unlock_zbuffer = FALSE;
824
825 if (r300->screen->caps.is_r500) {
826 max_width = max_height = 4096;
827 } else if (r300->screen->caps.is_r400) {
828 max_width = max_height = 4021;
829 } else {
830 max_width = max_height = 2560;
831 }
832
833 if (state->width > max_width || state->height > max_height) {
834 fprintf(stderr, "r300: Implementation error: Render targets are too "
835 "big in %s, refusing to bind framebuffer state!\n", __FUNCTION__);
836 return;
837 }
838
839 if (old_state->zsbuf && r300->zmask_in_use && !r300->locked_zbuffer) {
840 /* There is a zmask in use, what are we gonna do? */
841 if (state->zsbuf) {
842 if (!pipe_surface_equal(old_state->zsbuf, state->zsbuf)) {
843 /* Decompress the currently bound zbuffer before we bind another one. */
844 r300_decompress_zmask(r300);
845 r300->hiz_in_use = FALSE;
846 }
847 } else {
848 /* We don't bind another zbuffer, so lock the current one. */
849 pipe_surface_reference(&r300->locked_zbuffer, old_state->zsbuf);
850 }
851 } else if (r300->locked_zbuffer) {
852 /* We have a locked zbuffer now, what are we gonna do? */
853 if (state->zsbuf) {
854 if (!pipe_surface_equal(r300->locked_zbuffer, state->zsbuf)) {
855 /* We are binding some other zbuffer, so decompress the locked one,
856 * it gets unlocked automatically. */
857 r300_decompress_zmask_locked_unsafe(r300);
858 r300->hiz_in_use = FALSE;
859 } else {
860 /* We are binding the locked zbuffer again, so unlock it. */
861 unlock_zbuffer = TRUE;
862 }
863 }
864 }
865 assert(state->zsbuf || (r300->locked_zbuffer && !unlock_zbuffer) || !r300->zmask_in_use);
866
867 /* Need to reset clamping or colormask. */
868 r300_mark_atom_dirty(r300, &r300->blend_state);
869
870 /* If zsbuf is set from NULL to non-NULL or vice versa.. */
871 if (!!old_state->zsbuf != !!state->zsbuf) {
872 r300_mark_atom_dirty(r300, &r300->dsa_state);
873 }
874
875 if (r300->screen->info.drm_minor < 12) {
876 /* The tiling flags are dependent on the surface miplevel, unfortunately.
877 * This workarounds a bad design decision in old kernels which were
878 * rewriting tile fields in registers. */
879 r300_fb_set_tiling_flags(r300, state);
880 }
881
882 util_copy_framebuffer_state(r300->fb_state.state, state);
883
884 if (unlock_zbuffer) {
885 pipe_surface_reference(&r300->locked_zbuffer, NULL);
886 }
887
888 r300_mark_fb_state_dirty(r300, R300_CHANGED_FB_STATE);
889
890 if (state->zsbuf) {
891 switch (util_format_get_blocksize(state->zsbuf->texture->format)) {
892 case 2:
893 zbuffer_bpp = 16;
894 break;
895 case 4:
896 zbuffer_bpp = 24;
897 break;
898 }
899
900 /* Polygon offset depends on the zbuffer bit depth. */
901 if (r300->zbuffer_bpp != zbuffer_bpp) {
902 r300->zbuffer_bpp = zbuffer_bpp;
903
904 if (r300->polygon_offset_enabled)
905 r300_mark_atom_dirty(r300, &r300->rs_state);
906 }
907 }
908
909 /* Set up AA config. */
910 if (state->nr_cbufs && state->cbufs[0]->texture->nr_samples > 1) {
911 aa->aa_config = R300_GB_AA_CONFIG_AA_ENABLE;
912
913 switch (state->cbufs[0]->texture->nr_samples) {
914 case 2:
915 aa->aa_config |= R300_GB_AA_CONFIG_NUM_AA_SUBSAMPLES_2;
916 break;
917 case 3:
918 aa->aa_config |= R300_GB_AA_CONFIG_NUM_AA_SUBSAMPLES_3;
919 break;
920 case 4:
921 aa->aa_config |= R300_GB_AA_CONFIG_NUM_AA_SUBSAMPLES_4;
922 break;
923 case 6:
924 aa->aa_config |= R300_GB_AA_CONFIG_NUM_AA_SUBSAMPLES_6;
925 break;
926 }
927 } else {
928 aa->aa_config = 0;
929 }
930
931 if (DBG_ON(r300, DBG_FB)) {
932 fprintf(stderr, "r300: set_framebuffer_state:\n");
933 for (i = 0; i < state->nr_cbufs; i++) {
934 r300_print_fb_surf_info(state->cbufs[i], i, "CB");
935 }
936 if (state->zsbuf) {
937 r300_print_fb_surf_info(state->zsbuf, 0, "ZB");
938 }
939 }
940 }
941
942 /* Create fragment shader state. */
943 static void* r300_create_fs_state(struct pipe_context* pipe,
944 const struct pipe_shader_state* shader)
945 {
946 struct r300_fragment_shader* fs = NULL;
947
948 fs = (struct r300_fragment_shader*)CALLOC_STRUCT(r300_fragment_shader);
949
950 /* Copy state directly into shader. */
951 fs->state = *shader;
952 fs->state.tokens = tgsi_dup_tokens(shader->tokens);
953
954 return (void*)fs;
955 }
956
957 void r300_mark_fs_code_dirty(struct r300_context *r300)
958 {
959 struct r300_fragment_shader* fs = r300_fs(r300);
960
961 r300_mark_atom_dirty(r300, &r300->fs);
962 r300_mark_atom_dirty(r300, &r300->fs_rc_constant_state);
963 r300_mark_atom_dirty(r300, &r300->fs_constants);
964 r300->fs.size = fs->shader->cb_code_size;
965
966 if (r300->screen->caps.is_r500) {
967 r300->fs_rc_constant_state.size = fs->shader->rc_state_count * 7;
968 r300->fs_constants.size = fs->shader->externals_count * 4 + 3;
969 } else {
970 r300->fs_rc_constant_state.size = fs->shader->rc_state_count * 5;
971 r300->fs_constants.size = fs->shader->externals_count * 4 + 1;
972 }
973
974 ((struct r300_constant_buffer*)r300->fs_constants.state)->remap_table =
975 fs->shader->code.constants_remap_table;
976 }
977
978 /* Bind fragment shader state. */
979 static void r300_bind_fs_state(struct pipe_context* pipe, void* shader)
980 {
981 struct r300_context* r300 = r300_context(pipe);
982 struct r300_fragment_shader* fs = (struct r300_fragment_shader*)shader;
983
984 if (fs == NULL) {
985 r300->fs.state = NULL;
986 return;
987 }
988
989 r300->fs.state = fs;
990 r300->fs_status = FRAGMENT_SHADER_DIRTY;
991
992 r300_mark_atom_dirty(r300, &r300->rs_block_state); /* Will be updated before the emission. */
993 }
994
995 /* Delete fragment shader state. */
996 static void r300_delete_fs_state(struct pipe_context* pipe, void* shader)
997 {
998 struct r300_fragment_shader* fs = (struct r300_fragment_shader*)shader;
999 struct r300_fragment_shader_code *tmp, *ptr = fs->first;
1000
1001 while (ptr) {
1002 tmp = ptr;
1003 ptr = ptr->next;
1004 rc_constants_destroy(&tmp->code.constants);
1005 FREE(tmp->cb_code);
1006 FREE(tmp);
1007 }
1008 FREE((void*)fs->state.tokens);
1009 FREE(shader);
1010 }
1011
1012 static void r300_set_polygon_stipple(struct pipe_context* pipe,
1013 const struct pipe_poly_stipple* state)
1014 {
1015 /* XXX no idea how to set this up, but not terribly important */
1016 }
1017
1018 /* Create a new rasterizer state based on the CSO rasterizer state.
1019 *
1020 * This is a very large chunk of state, and covers most of the graphics
1021 * backend (GB), geometry assembly (GA), and setup unit (SU) blocks.
1022 *
1023 * In a not entirely unironic sidenote, this state has nearly nothing to do
1024 * with the actual block on the Radeon called the rasterizer (RS). */
1025 static void* r300_create_rs_state(struct pipe_context* pipe,
1026 const struct pipe_rasterizer_state* state)
1027 {
1028 struct r300_rs_state* rs = CALLOC_STRUCT(r300_rs_state);
1029 float psiz;
1030 uint32_t vap_control_status; /* R300_VAP_CNTL_STATUS: 0x2140 */
1031 uint32_t point_size; /* R300_GA_POINT_SIZE: 0x421c */
1032 uint32_t point_minmax; /* R300_GA_POINT_MINMAX: 0x4230 */
1033 uint32_t line_control; /* R300_GA_LINE_CNTL: 0x4234 */
1034 uint32_t polygon_offset_enable; /* R300_SU_POLY_OFFSET_ENABLE: 0x42b4 */
1035 uint32_t cull_mode; /* R300_SU_CULL_MODE: 0x42b8 */
1036 uint32_t line_stipple_config; /* R300_GA_LINE_STIPPLE_CONFIG: 0x4328 */
1037 uint32_t line_stipple_value; /* R300_GA_LINE_STIPPLE_VALUE: 0x4260 */
1038 uint32_t polygon_mode; /* R300_GA_POLY_MODE: 0x4288 */
1039 uint32_t clip_rule; /* R300_SC_CLIP_RULE: 0x43D0 */
1040 uint32_t round_mode; /* R300_GA_ROUND_MODE: 0x428c */
1041
1042 /* Point sprites texture coordinates, 0: lower left, 1: upper right */
1043 float point_texcoord_left = 0; /* R300_GA_POINT_S0: 0x4200 */
1044 float point_texcoord_bottom = 0;/* R300_GA_POINT_T0: 0x4204 */
1045 float point_texcoord_right = 1; /* R300_GA_POINT_S1: 0x4208 */
1046 float point_texcoord_top = 0; /* R300_GA_POINT_T1: 0x420c */
1047 boolean vclamp = state->clamp_vertex_color;
1048 CB_LOCALS;
1049
1050 /* Copy rasterizer state. */
1051 rs->rs = *state;
1052 rs->rs_draw = *state;
1053
1054 rs->rs.sprite_coord_enable = state->point_quad_rasterization *
1055 state->sprite_coord_enable;
1056
1057 /* Override some states for Draw. */
1058 rs->rs_draw.sprite_coord_enable = 0; /* We can do this in HW. */
1059
1060 #ifdef PIPE_ARCH_LITTLE_ENDIAN
1061 vap_control_status = R300_VC_NO_SWAP;
1062 #else
1063 vap_control_status = R300_VC_32BIT_SWAP;
1064 #endif
1065
1066 /* If no TCL engine is present, turn off the HW TCL. */
1067 if (!r300_screen(pipe->screen)->caps.has_tcl) {
1068 vap_control_status |= R300_VAP_TCL_BYPASS;
1069 }
1070
1071 /* Point size width and height. */
1072 point_size =
1073 pack_float_16_6x(state->point_size) |
1074 (pack_float_16_6x(state->point_size) << R300_POINTSIZE_X_SHIFT);
1075
1076 /* Point size clamping. */
1077 if (state->point_size_per_vertex) {
1078 /* Per-vertex point size.
1079 * Clamp to [0, max FB size] */
1080 psiz = pipe->screen->get_paramf(pipe->screen,
1081 PIPE_CAPF_MAX_POINT_WIDTH);
1082 point_minmax =
1083 pack_float_16_6x(psiz) << R300_GA_POINT_MINMAX_MAX_SHIFT;
1084 } else {
1085 /* We cannot disable the point-size vertex output,
1086 * so clamp it. */
1087 psiz = state->point_size;
1088 point_minmax =
1089 (pack_float_16_6x(psiz) << R300_GA_POINT_MINMAX_MIN_SHIFT) |
1090 (pack_float_16_6x(psiz) << R300_GA_POINT_MINMAX_MAX_SHIFT);
1091 }
1092
1093 /* Line control. */
1094 line_control = pack_float_16_6x(state->line_width) |
1095 R300_GA_LINE_CNTL_END_TYPE_COMP;
1096
1097 /* Enable polygon mode */
1098 polygon_mode = 0;
1099 if (state->fill_front != PIPE_POLYGON_MODE_FILL ||
1100 state->fill_back != PIPE_POLYGON_MODE_FILL) {
1101 polygon_mode = R300_GA_POLY_MODE_DUAL;
1102 }
1103
1104 /* Front face */
1105 if (state->front_ccw)
1106 cull_mode = R300_FRONT_FACE_CCW;
1107 else
1108 cull_mode = R300_FRONT_FACE_CW;
1109
1110 /* Polygon offset */
1111 polygon_offset_enable = 0;
1112 if (util_get_offset(state, state->fill_front)) {
1113 polygon_offset_enable |= R300_FRONT_ENABLE;
1114 }
1115 if (util_get_offset(state, state->fill_back)) {
1116 polygon_offset_enable |= R300_BACK_ENABLE;
1117 }
1118
1119 rs->polygon_offset_enable = polygon_offset_enable != 0;
1120
1121 /* Polygon mode */
1122 if (polygon_mode) {
1123 polygon_mode |=
1124 r300_translate_polygon_mode_front(state->fill_front);
1125 polygon_mode |=
1126 r300_translate_polygon_mode_back(state->fill_back);
1127 }
1128
1129 if (state->cull_face & PIPE_FACE_FRONT) {
1130 cull_mode |= R300_CULL_FRONT;
1131 }
1132 if (state->cull_face & PIPE_FACE_BACK) {
1133 cull_mode |= R300_CULL_BACK;
1134 }
1135
1136 if (state->line_stipple_enable) {
1137 line_stipple_config =
1138 R300_GA_LINE_STIPPLE_CONFIG_LINE_RESET_LINE |
1139 (fui((float)state->line_stipple_factor) &
1140 R300_GA_LINE_STIPPLE_CONFIG_STIPPLE_SCALE_MASK);
1141 /* XXX this might need to be scaled up */
1142 line_stipple_value = state->line_stipple_pattern;
1143 } else {
1144 line_stipple_config = 0;
1145 line_stipple_value = 0;
1146 }
1147
1148 if (state->flatshade) {
1149 rs->color_control = R300_SHADE_MODEL_FLAT;
1150 } else {
1151 rs->color_control = R300_SHADE_MODEL_SMOOTH;
1152 }
1153
1154 clip_rule = state->scissor ? 0xAAAA : 0xFFFF;
1155
1156 /* Point sprites coord mode */
1157 if (rs->rs.sprite_coord_enable) {
1158 switch (state->sprite_coord_mode) {
1159 case PIPE_SPRITE_COORD_UPPER_LEFT:
1160 point_texcoord_top = 0.0f;
1161 point_texcoord_bottom = 1.0f;
1162 break;
1163 case PIPE_SPRITE_COORD_LOWER_LEFT:
1164 point_texcoord_top = 1.0f;
1165 point_texcoord_bottom = 0.0f;
1166 break;
1167 }
1168 }
1169
1170 /* Vertex color clamping. FP20 means no clamping. */
1171 round_mode =
1172 R300_GA_ROUND_MODE_GEOMETRY_ROUND_NEAREST |
1173 (!vclamp ? (R300_GA_ROUND_MODE_RGB_CLAMP_FP20 |
1174 R300_GA_ROUND_MODE_ALPHA_CLAMP_FP20) : 0);
1175
1176 /* Build the main command buffer. */
1177 BEGIN_CB(rs->cb_main, RS_STATE_MAIN_SIZE);
1178 OUT_CB_REG(R300_VAP_CNTL_STATUS, vap_control_status);
1179 OUT_CB_REG(R300_GA_POINT_SIZE, point_size);
1180 OUT_CB_REG_SEQ(R300_GA_POINT_MINMAX, 2);
1181 OUT_CB(point_minmax);
1182 OUT_CB(line_control);
1183 OUT_CB_REG_SEQ(R300_SU_POLY_OFFSET_ENABLE, 2);
1184 OUT_CB(polygon_offset_enable);
1185 rs->cull_mode_index = 9;
1186 OUT_CB(cull_mode);
1187 OUT_CB_REG(R300_GA_LINE_STIPPLE_CONFIG, line_stipple_config);
1188 OUT_CB_REG(R300_GA_LINE_STIPPLE_VALUE, line_stipple_value);
1189 OUT_CB_REG(R300_GA_POLY_MODE, polygon_mode);
1190 OUT_CB_REG(R300_GA_ROUND_MODE, round_mode);
1191 OUT_CB_REG(R300_SC_CLIP_RULE, clip_rule);
1192 OUT_CB_REG_SEQ(R300_GA_POINT_S0, 4);
1193 OUT_CB_32F(point_texcoord_left);
1194 OUT_CB_32F(point_texcoord_bottom);
1195 OUT_CB_32F(point_texcoord_right);
1196 OUT_CB_32F(point_texcoord_top);
1197 END_CB;
1198
1199 /* Build the two command buffers for polygon offset setup. */
1200 if (polygon_offset_enable) {
1201 float scale = state->offset_scale * 12;
1202 float offset = state->offset_units * 4;
1203
1204 BEGIN_CB(rs->cb_poly_offset_zb16, 5);
1205 OUT_CB_REG_SEQ(R300_SU_POLY_OFFSET_FRONT_SCALE, 4);
1206 OUT_CB_32F(scale);
1207 OUT_CB_32F(offset);
1208 OUT_CB_32F(scale);
1209 OUT_CB_32F(offset);
1210 END_CB;
1211
1212 offset = state->offset_units * 2;
1213
1214 BEGIN_CB(rs->cb_poly_offset_zb24, 5);
1215 OUT_CB_REG_SEQ(R300_SU_POLY_OFFSET_FRONT_SCALE, 4);
1216 OUT_CB_32F(scale);
1217 OUT_CB_32F(offset);
1218 OUT_CB_32F(scale);
1219 OUT_CB_32F(offset);
1220 END_CB;
1221 }
1222
1223 return (void*)rs;
1224 }
1225
1226 /* Bind rasterizer state. */
1227 static void r300_bind_rs_state(struct pipe_context* pipe, void* state)
1228 {
1229 struct r300_context* r300 = r300_context(pipe);
1230 struct r300_rs_state* rs = (struct r300_rs_state*)state;
1231 int last_sprite_coord_enable = r300->sprite_coord_enable;
1232 boolean last_two_sided_color = r300->two_sided_color;
1233 boolean last_frag_clamp = r300->frag_clamp;
1234
1235 if (r300->draw && rs) {
1236 draw_set_rasterizer_state(r300->draw, &rs->rs_draw, state);
1237 }
1238
1239 if (rs) {
1240 r300->polygon_offset_enabled = rs->polygon_offset_enable;
1241 r300->sprite_coord_enable = rs->rs.sprite_coord_enable;
1242 r300->two_sided_color = rs->rs.light_twoside;
1243 r300->frag_clamp = rs->rs.clamp_fragment_color;
1244 } else {
1245 r300->polygon_offset_enabled = FALSE;
1246 r300->sprite_coord_enable = 0;
1247 r300->two_sided_color = FALSE;
1248 r300->frag_clamp = FALSE;
1249 }
1250
1251 UPDATE_STATE(state, r300->rs_state);
1252 r300->rs_state.size = RS_STATE_MAIN_SIZE + (r300->polygon_offset_enabled ? 5 : 0);
1253
1254 if (last_sprite_coord_enable != r300->sprite_coord_enable ||
1255 last_two_sided_color != r300->two_sided_color) {
1256 r300_mark_atom_dirty(r300, &r300->rs_block_state);
1257 }
1258
1259 if (last_frag_clamp != r300->frag_clamp &&
1260 r300->fs_status == FRAGMENT_SHADER_VALID) {
1261 r300->fs_status = FRAGMENT_SHADER_MAYBE_DIRTY;
1262 }
1263 }
1264
1265 /* Free rasterizer state. */
1266 static void r300_delete_rs_state(struct pipe_context* pipe, void* state)
1267 {
1268 FREE(state);
1269 }
1270
1271 static void*
1272 r300_create_sampler_state(struct pipe_context* pipe,
1273 const struct pipe_sampler_state* state)
1274 {
1275 struct r300_context* r300 = r300_context(pipe);
1276 struct r300_sampler_state* sampler = CALLOC_STRUCT(r300_sampler_state);
1277 boolean is_r500 = r300->screen->caps.is_r500;
1278 int lod_bias;
1279
1280 sampler->state = *state;
1281
1282 /* r300 doesn't handle CLAMP and MIRROR_CLAMP correctly when either MAG
1283 * or MIN filter is NEAREST. Since texwrap produces same results
1284 * for CLAMP and CLAMP_TO_EDGE, we use them instead. */
1285 if (sampler->state.min_img_filter == PIPE_TEX_FILTER_NEAREST ||
1286 sampler->state.mag_img_filter == PIPE_TEX_FILTER_NEAREST) {
1287 /* Wrap S. */
1288 if (sampler->state.wrap_s == PIPE_TEX_WRAP_CLAMP)
1289 sampler->state.wrap_s = PIPE_TEX_WRAP_CLAMP_TO_EDGE;
1290 else if (sampler->state.wrap_s == PIPE_TEX_WRAP_MIRROR_CLAMP)
1291 sampler->state.wrap_s = PIPE_TEX_WRAP_MIRROR_CLAMP_TO_EDGE;
1292
1293 /* Wrap T. */
1294 if (sampler->state.wrap_t == PIPE_TEX_WRAP_CLAMP)
1295 sampler->state.wrap_t = PIPE_TEX_WRAP_CLAMP_TO_EDGE;
1296 else if (sampler->state.wrap_t == PIPE_TEX_WRAP_MIRROR_CLAMP)
1297 sampler->state.wrap_t = PIPE_TEX_WRAP_MIRROR_CLAMP_TO_EDGE;
1298
1299 /* Wrap R. */
1300 if (sampler->state.wrap_r == PIPE_TEX_WRAP_CLAMP)
1301 sampler->state.wrap_r = PIPE_TEX_WRAP_CLAMP_TO_EDGE;
1302 else if (sampler->state.wrap_r == PIPE_TEX_WRAP_MIRROR_CLAMP)
1303 sampler->state.wrap_r = PIPE_TEX_WRAP_MIRROR_CLAMP_TO_EDGE;
1304 }
1305
1306 sampler->filter0 |=
1307 (r300_translate_wrap(sampler->state.wrap_s) << R300_TX_WRAP_S_SHIFT) |
1308 (r300_translate_wrap(sampler->state.wrap_t) << R300_TX_WRAP_T_SHIFT) |
1309 (r300_translate_wrap(sampler->state.wrap_r) << R300_TX_WRAP_R_SHIFT);
1310
1311 sampler->filter0 |= r300_translate_tex_filters(state->min_img_filter,
1312 state->mag_img_filter,
1313 state->min_mip_filter,
1314 state->max_anisotropy > 1);
1315
1316 sampler->filter0 |= r300_anisotropy(state->max_anisotropy);
1317
1318 /* Unfortunately, r300-r500 don't support floating-point mipmap lods. */
1319 /* We must pass these to the merge function to clamp them properly. */
1320 sampler->min_lod = (unsigned)MAX2(state->min_lod, 0);
1321 sampler->max_lod = (unsigned)MAX2(ceilf(state->max_lod), 0);
1322
1323 lod_bias = CLAMP((int)(state->lod_bias * 32 + 1), -(1 << 9), (1 << 9) - 1);
1324
1325 sampler->filter1 |= (lod_bias << R300_LOD_BIAS_SHIFT) & R300_LOD_BIAS_MASK;
1326
1327 /* This is very high quality anisotropic filtering for R5xx.
1328 * It's good for benchmarking the performance of texturing but
1329 * in practice we don't want to slow down the driver because it's
1330 * a pretty good performance killer. Feel free to play with it. */
1331 if (DBG_ON(r300, DBG_ANISOHQ) && is_r500) {
1332 sampler->filter1 |= r500_anisotropy(state->max_anisotropy);
1333 }
1334
1335 /* R500-specific fixups and optimizations */
1336 if (r300->screen->caps.is_r500) {
1337 sampler->filter1 |= R500_BORDER_FIX;
1338 }
1339
1340 return (void*)sampler;
1341 }
1342
1343 static void r300_bind_sampler_states(struct pipe_context* pipe,
1344 unsigned count,
1345 void** states)
1346 {
1347 struct r300_context* r300 = r300_context(pipe);
1348 struct r300_textures_state* state =
1349 (struct r300_textures_state*)r300->textures_state.state;
1350 unsigned tex_units = r300->screen->caps.num_tex_units;
1351
1352 if (count > tex_units) {
1353 return;
1354 }
1355
1356 memcpy(state->sampler_states, states, sizeof(void*) * count);
1357 state->sampler_state_count = count;
1358
1359 r300_mark_atom_dirty(r300, &r300->textures_state);
1360 }
1361
1362 static void r300_lacks_vertex_textures(struct pipe_context* pipe,
1363 unsigned count,
1364 void** states)
1365 {
1366 }
1367
1368 static void r300_delete_sampler_state(struct pipe_context* pipe, void* state)
1369 {
1370 FREE(state);
1371 }
1372
1373 static uint32_t r300_assign_texture_cache_region(unsigned index, unsigned num)
1374 {
1375 /* This looks like a hack, but I believe it's suppose to work like
1376 * that. To illustrate how this works, let's assume you have 5 textures.
1377 * From docs, 5 and the successive numbers are:
1378 *
1379 * FOURTH_1 = 5
1380 * FOURTH_2 = 6
1381 * FOURTH_3 = 7
1382 * EIGHTH_0 = 8
1383 * EIGHTH_1 = 9
1384 *
1385 * First 3 textures will get 3/4 of size of the cache, divived evenly
1386 * between them. The last 1/4 of the cache must be divided between
1387 * the last 2 textures, each will therefore get 1/8 of the cache.
1388 * Why not just to use "5 + texture_index" ?
1389 *
1390 * This simple trick works for all "num" <= 16.
1391 */
1392 if (num <= 1)
1393 return R300_TX_CACHE(R300_TX_CACHE_WHOLE);
1394 else
1395 return R300_TX_CACHE(num + index);
1396 }
1397
1398 static void r300_set_fragment_sampler_views(struct pipe_context* pipe,
1399 unsigned count,
1400 struct pipe_sampler_view** views)
1401 {
1402 struct r300_context* r300 = r300_context(pipe);
1403 struct r300_textures_state* state =
1404 (struct r300_textures_state*)r300->textures_state.state;
1405 struct r300_resource *texture;
1406 unsigned i, real_num_views = 0, view_index = 0;
1407 unsigned tex_units = r300->screen->caps.num_tex_units;
1408 boolean dirty_tex = FALSE;
1409
1410 if (count > tex_units) {
1411 return;
1412 }
1413
1414 /* Calculate the real number of views. */
1415 for (i = 0; i < count; i++) {
1416 if (views[i])
1417 real_num_views++;
1418 }
1419
1420 for (i = 0; i < count; i++) {
1421 pipe_sampler_view_reference(
1422 (struct pipe_sampler_view**)&state->sampler_views[i],
1423 views[i]);
1424
1425 if (!views[i]) {
1426 continue;
1427 }
1428
1429 /* A new sampler view (= texture)... */
1430 dirty_tex = TRUE;
1431
1432 /* Set the texrect factor in the fragment shader.
1433 * Needed for RECT and NPOT fallback. */
1434 texture = r300_resource(views[i]->texture);
1435 if (texture->tex.is_npot) {
1436 r300_mark_atom_dirty(r300, &r300->fs_rc_constant_state);
1437 }
1438
1439 state->sampler_views[i]->texcache_region =
1440 r300_assign_texture_cache_region(view_index, real_num_views);
1441 view_index++;
1442 }
1443
1444 for (i = count; i < tex_units; i++) {
1445 if (state->sampler_views[i]) {
1446 pipe_sampler_view_reference(
1447 (struct pipe_sampler_view**)&state->sampler_views[i],
1448 NULL);
1449 }
1450 }
1451
1452 state->sampler_view_count = count;
1453
1454 r300_mark_atom_dirty(r300, &r300->textures_state);
1455
1456 if (dirty_tex) {
1457 r300_mark_atom_dirty(r300, &r300->texture_cache_inval);
1458 }
1459 }
1460
1461 static struct pipe_sampler_view *
1462 r300_create_sampler_view(struct pipe_context *pipe,
1463 struct pipe_resource *texture,
1464 const struct pipe_sampler_view *templ)
1465 {
1466 struct r300_sampler_view *view = CALLOC_STRUCT(r300_sampler_view);
1467 struct r300_resource *tex = r300_resource(texture);
1468 boolean is_r500 = r300_screen(pipe->screen)->caps.is_r500;
1469 boolean dxtc_swizzle = r300_screen(pipe->screen)->caps.dxtc_swizzle;
1470
1471 if (view) {
1472 unsigned hwformat;
1473
1474 view->base = *templ;
1475 view->base.reference.count = 1;
1476 view->base.context = pipe;
1477 view->base.texture = NULL;
1478 pipe_resource_reference(&view->base.texture, texture);
1479
1480 view->swizzle[0] = templ->swizzle_r;
1481 view->swizzle[1] = templ->swizzle_g;
1482 view->swizzle[2] = templ->swizzle_b;
1483 view->swizzle[3] = templ->swizzle_a;
1484
1485 hwformat = r300_translate_texformat(templ->format,
1486 view->swizzle,
1487 is_r500,
1488 dxtc_swizzle);
1489
1490 if (hwformat == ~0) {
1491 fprintf(stderr, "r300: Ooops. Got unsupported format %s in %s.\n",
1492 util_format_short_name(templ->format), __func__);
1493 }
1494 assert(hwformat != ~0);
1495
1496 view->format = tex->tx_format;
1497 view->format.format1 |= hwformat;
1498 if (is_r500) {
1499 view->format.format2 |= r500_tx_format_msb_bit(templ->format);
1500 }
1501 }
1502
1503 return (struct pipe_sampler_view*)view;
1504 }
1505
1506 static void
1507 r300_sampler_view_destroy(struct pipe_context *pipe,
1508 struct pipe_sampler_view *view)
1509 {
1510 pipe_resource_reference(&view->texture, NULL);
1511 FREE(view);
1512 }
1513
1514 static void r300_set_scissor_state(struct pipe_context* pipe,
1515 const struct pipe_scissor_state* state)
1516 {
1517 struct r300_context* r300 = r300_context(pipe);
1518
1519 memcpy(r300->scissor_state.state, state,
1520 sizeof(struct pipe_scissor_state));
1521
1522 r300_mark_atom_dirty(r300, &r300->scissor_state);
1523 }
1524
1525 static void r300_set_viewport_state(struct pipe_context* pipe,
1526 const struct pipe_viewport_state* state)
1527 {
1528 struct r300_context* r300 = r300_context(pipe);
1529 struct r300_viewport_state* viewport =
1530 (struct r300_viewport_state*)r300->viewport_state.state;
1531
1532 r300->viewport = *state;
1533
1534 if (r300->draw) {
1535 draw_set_viewport_state(r300->draw, state);
1536 viewport->vte_control = R300_VTX_XY_FMT | R300_VTX_Z_FMT;
1537 return;
1538 }
1539
1540 /* Do the transform in HW. */
1541 viewport->vte_control = R300_VTX_W0_FMT;
1542
1543 if (state->scale[0] != 1.0f) {
1544 viewport->xscale = state->scale[0];
1545 viewport->vte_control |= R300_VPORT_X_SCALE_ENA;
1546 }
1547 if (state->scale[1] != 1.0f) {
1548 viewport->yscale = state->scale[1];
1549 viewport->vte_control |= R300_VPORT_Y_SCALE_ENA;
1550 }
1551 if (state->scale[2] != 1.0f) {
1552 viewport->zscale = state->scale[2];
1553 viewport->vte_control |= R300_VPORT_Z_SCALE_ENA;
1554 }
1555 if (state->translate[0] != 0.0f) {
1556 viewport->xoffset = state->translate[0];
1557 viewport->vte_control |= R300_VPORT_X_OFFSET_ENA;
1558 }
1559 if (state->translate[1] != 0.0f) {
1560 viewport->yoffset = state->translate[1];
1561 viewport->vte_control |= R300_VPORT_Y_OFFSET_ENA;
1562 }
1563 if (state->translate[2] != 0.0f) {
1564 viewport->zoffset = state->translate[2];
1565 viewport->vte_control |= R300_VPORT_Z_OFFSET_ENA;
1566 }
1567
1568 r300_mark_atom_dirty(r300, &r300->viewport_state);
1569 if (r300->fs.state && r300_fs(r300)->shader &&
1570 r300_fs(r300)->shader->inputs.wpos != ATTR_UNUSED) {
1571 r300_mark_atom_dirty(r300, &r300->fs_rc_constant_state);
1572 }
1573 }
1574
1575 static void r300_set_vertex_buffers(struct pipe_context* pipe,
1576 unsigned count,
1577 const struct pipe_vertex_buffer* buffers)
1578 {
1579 struct r300_context* r300 = r300_context(pipe);
1580 unsigned i;
1581 struct pipe_vertex_buffer dummy_vb = {0};
1582
1583 /* There must be at least one vertex buffer set, otherwise it locks up. */
1584 if (!count) {
1585 dummy_vb.buffer = r300->dummy_vb;
1586 buffers = &dummy_vb;
1587 count = 1;
1588 }
1589
1590 u_vbuf_set_vertex_buffers(r300->vbuf_mgr, count, buffers);
1591
1592 if (r300->screen->caps.has_tcl) {
1593 /* HW TCL. */
1594 for (i = 0; i < count; i++) {
1595 if (buffers[i].buffer &&
1596 !r300_resource(buffers[i].buffer)->b.user_ptr) {
1597 }
1598 }
1599 r300->vertex_arrays_dirty = TRUE;
1600 } else {
1601 /* SW TCL. */
1602 draw_set_vertex_buffers(r300->draw, count, buffers);
1603 }
1604 }
1605
1606 static void r300_set_index_buffer(struct pipe_context* pipe,
1607 const struct pipe_index_buffer *ib)
1608 {
1609 struct r300_context* r300 = r300_context(pipe);
1610
1611 u_vbuf_set_index_buffer(r300->vbuf_mgr, ib);
1612
1613 if (!r300->screen->caps.has_tcl) {
1614 draw_set_index_buffer(r300->draw, ib);
1615 }
1616 }
1617
1618 /* Initialize the PSC tables. */
1619 static void r300_vertex_psc(struct r300_vertex_element_state *velems)
1620 {
1621 struct r300_vertex_stream_state *vstream = &velems->vertex_stream;
1622 uint16_t type, swizzle;
1623 enum pipe_format format;
1624 unsigned i;
1625
1626 /* Vertex shaders have no semantics on their inputs,
1627 * so PSC should just route stuff based on the vertex elements,
1628 * and not on attrib information. */
1629 for (i = 0; i < velems->count; i++) {
1630 format = velems->velem[i].src_format;
1631
1632 type = r300_translate_vertex_data_type(format);
1633 if (type == R300_INVALID_FORMAT) {
1634 fprintf(stderr, "r300: Bad vertex format %s.\n",
1635 util_format_short_name(format));
1636 assert(0);
1637 abort();
1638 }
1639
1640 type |= i << R300_DST_VEC_LOC_SHIFT;
1641 swizzle = r300_translate_vertex_data_swizzle(format);
1642
1643 if (i & 1) {
1644 vstream->vap_prog_stream_cntl[i >> 1] |= type << 16;
1645 vstream->vap_prog_stream_cntl_ext[i >> 1] |= swizzle << 16;
1646 } else {
1647 vstream->vap_prog_stream_cntl[i >> 1] |= type;
1648 vstream->vap_prog_stream_cntl_ext[i >> 1] |= swizzle;
1649 }
1650 }
1651
1652 /* Set the last vector in the PSC. */
1653 if (i) {
1654 i -= 1;
1655 }
1656 vstream->vap_prog_stream_cntl[i >> 1] |=
1657 (R300_LAST_VEC << (i & 1 ? 16 : 0));
1658
1659 vstream->count = (i >> 1) + 1;
1660 }
1661
1662 static void* r300_create_vertex_elements_state(struct pipe_context* pipe,
1663 unsigned count,
1664 const struct pipe_vertex_element* attribs)
1665 {
1666 struct r300_context *r300 = r300_context(pipe);
1667 struct r300_vertex_element_state *velems;
1668 unsigned i;
1669 struct pipe_vertex_element dummy_attrib = {0};
1670
1671 /* R300 Programmable Stream Control (PSC) doesn't support 0 vertex elements. */
1672 if (!count) {
1673 dummy_attrib.src_format = PIPE_FORMAT_R8G8B8A8_UNORM;
1674 attribs = &dummy_attrib;
1675 count = 1;
1676 } else if (count > 16) {
1677 fprintf(stderr, "r300: More than 16 vertex elements are not supported,"
1678 " requested %i, using 16.\n", count);
1679 count = 16;
1680 }
1681
1682 velems = CALLOC_STRUCT(r300_vertex_element_state);
1683 if (!velems)
1684 return NULL;
1685
1686 velems->count = count;
1687 velems->vmgr_elements =
1688 u_vbuf_create_vertex_elements(r300->vbuf_mgr, count, attribs,
1689 velems->velem);
1690
1691 if (r300_screen(pipe->screen)->caps.has_tcl) {
1692 /* Setup PSC.
1693 * The unused components will be replaced by (..., 0, 1). */
1694 r300_vertex_psc(velems);
1695
1696 for (i = 0; i < count; i++) {
1697 velems->format_size[i] =
1698 align(util_format_get_blocksize(velems->velem[i].src_format), 4);
1699 velems->vertex_size_dwords += velems->format_size[i] / 4;
1700 }
1701 }
1702
1703 return velems;
1704 }
1705
1706 static void r300_bind_vertex_elements_state(struct pipe_context *pipe,
1707 void *state)
1708 {
1709 struct r300_context *r300 = r300_context(pipe);
1710 struct r300_vertex_element_state *velems = state;
1711
1712 if (velems == NULL) {
1713 return;
1714 }
1715
1716 r300->velems = velems;
1717
1718 u_vbuf_bind_vertex_elements(r300->vbuf_mgr, state, velems->vmgr_elements);
1719
1720 if (r300->draw) {
1721 draw_set_vertex_elements(r300->draw, velems->count, velems->velem);
1722 return;
1723 }
1724
1725 UPDATE_STATE(&velems->vertex_stream, r300->vertex_stream_state);
1726 r300->vertex_stream_state.size = (1 + velems->vertex_stream.count) * 2;
1727 r300->vertex_arrays_dirty = TRUE;
1728 }
1729
1730 static void r300_delete_vertex_elements_state(struct pipe_context *pipe, void *state)
1731 {
1732 struct r300_context *r300 = r300_context(pipe);
1733 struct r300_vertex_element_state *velems = state;
1734
1735 u_vbuf_destroy_vertex_elements(r300->vbuf_mgr, velems->vmgr_elements);
1736 FREE(state);
1737 }
1738
1739 static void* r300_create_vs_state(struct pipe_context* pipe,
1740 const struct pipe_shader_state* shader)
1741 {
1742 struct r300_context* r300 = r300_context(pipe);
1743 struct r300_vertex_shader* vs = CALLOC_STRUCT(r300_vertex_shader);
1744
1745 /* Copy state directly into shader. */
1746 vs->state = *shader;
1747 vs->state.tokens = tgsi_dup_tokens(shader->tokens);
1748
1749 if (r300->screen->caps.has_tcl) {
1750 r300_init_vs_outputs(vs);
1751 r300_translate_vertex_shader(r300, vs);
1752 } else {
1753 r300_draw_init_vertex_shader(r300->draw, vs);
1754 }
1755
1756 return vs;
1757 }
1758
1759 static void r300_bind_vs_state(struct pipe_context* pipe, void* shader)
1760 {
1761 struct r300_context* r300 = r300_context(pipe);
1762 struct r300_vertex_shader* vs = (struct r300_vertex_shader*)shader;
1763
1764 if (vs == NULL) {
1765 r300->vs_state.state = NULL;
1766 return;
1767 }
1768 if (vs == r300->vs_state.state) {
1769 return;
1770 }
1771 r300->vs_state.state = vs;
1772
1773 /* The majority of the RS block bits is dependent on the vertex shader. */
1774 r300_mark_atom_dirty(r300, &r300->rs_block_state); /* Will be updated before the emission. */
1775
1776 if (r300->screen->caps.has_tcl) {
1777 unsigned fc_op_dwords = r300->screen->caps.is_r500 ? 3 : 2;
1778 r300_mark_atom_dirty(r300, &r300->vs_state);
1779 r300->vs_state.size =
1780 vs->code.length + 9 +
1781 (vs->code.num_fc_ops ? vs->code.num_fc_ops * fc_op_dwords + 4 : 0);
1782
1783 r300_mark_atom_dirty(r300, &r300->vs_constants);
1784 r300->vs_constants.size =
1785 2 +
1786 (vs->externals_count ? vs->externals_count * 4 + 3 : 0) +
1787 (vs->immediates_count ? vs->immediates_count * 4 + 3 : 0);
1788
1789 ((struct r300_constant_buffer*)r300->vs_constants.state)->remap_table =
1790 vs->code.constants_remap_table;
1791
1792 r300_mark_atom_dirty(r300, &r300->pvs_flush);
1793 } else {
1794 draw_bind_vertex_shader(r300->draw,
1795 (struct draw_vertex_shader*)vs->draw_vs);
1796 }
1797 }
1798
1799 static void r300_delete_vs_state(struct pipe_context* pipe, void* shader)
1800 {
1801 struct r300_context* r300 = r300_context(pipe);
1802 struct r300_vertex_shader* vs = (struct r300_vertex_shader*)shader;
1803
1804 if (r300->screen->caps.has_tcl) {
1805 rc_constants_destroy(&vs->code.constants);
1806 if (vs->code.constants_remap_table)
1807 FREE(vs->code.constants_remap_table);
1808 } else {
1809 draw_delete_vertex_shader(r300->draw,
1810 (struct draw_vertex_shader*)vs->draw_vs);
1811 }
1812
1813 FREE((void*)vs->state.tokens);
1814 FREE(shader);
1815 }
1816
1817 static void r300_set_constant_buffer(struct pipe_context *pipe,
1818 uint shader, uint index,
1819 struct pipe_resource *buf)
1820 {
1821 struct r300_context* r300 = r300_context(pipe);
1822 struct r300_constant_buffer *cbuf;
1823 struct r300_resource *rbuf = r300_resource(buf);
1824 uint32_t *mapped;
1825
1826 switch (shader) {
1827 case PIPE_SHADER_VERTEX:
1828 cbuf = (struct r300_constant_buffer*)r300->vs_constants.state;
1829 break;
1830 case PIPE_SHADER_FRAGMENT:
1831 cbuf = (struct r300_constant_buffer*)r300->fs_constants.state;
1832 break;
1833 default:
1834 return;
1835 }
1836
1837 if (buf == NULL || buf->width0 == 0)
1838 return;
1839
1840 if (rbuf->b.user_ptr)
1841 mapped = (uint32_t*)rbuf->b.user_ptr;
1842 else if (rbuf->constant_buffer)
1843 mapped = (uint32_t*)rbuf->constant_buffer;
1844 else
1845 return;
1846
1847 if (shader == PIPE_SHADER_FRAGMENT ||
1848 (shader == PIPE_SHADER_VERTEX && r300->screen->caps.has_tcl)) {
1849 cbuf->ptr = mapped;
1850 }
1851
1852 if (shader == PIPE_SHADER_VERTEX) {
1853 if (r300->screen->caps.has_tcl) {
1854 struct r300_vertex_shader *vs =
1855 (struct r300_vertex_shader*)r300->vs_state.state;
1856
1857 if (!vs) {
1858 cbuf->buffer_base = 0;
1859 return;
1860 }
1861
1862 cbuf->buffer_base = r300->vs_const_base;
1863 r300->vs_const_base += vs->code.constants.Count;
1864 if (r300->vs_const_base > R500_MAX_PVS_CONST_VECS) {
1865 r300->vs_const_base = vs->code.constants.Count;
1866 cbuf->buffer_base = 0;
1867 r300_mark_atom_dirty(r300, &r300->pvs_flush);
1868 }
1869 r300_mark_atom_dirty(r300, &r300->vs_constants);
1870 } else if (r300->draw) {
1871 draw_set_mapped_constant_buffer(r300->draw, PIPE_SHADER_VERTEX,
1872 0, mapped, buf->width0);
1873 }
1874 } else if (shader == PIPE_SHADER_FRAGMENT) {
1875 r300_mark_atom_dirty(r300, &r300->fs_constants);
1876 }
1877 }
1878
1879 static void r300_texture_barrier(struct pipe_context *pipe)
1880 {
1881 struct r300_context *r300 = r300_context(pipe);
1882
1883 r300_mark_atom_dirty(r300, &r300->gpu_flush);
1884 r300_mark_atom_dirty(r300, &r300->texture_cache_inval);
1885 }
1886
1887 void r300_init_state_functions(struct r300_context* r300)
1888 {
1889 r300->context.create_blend_state = r300_create_blend_state;
1890 r300->context.bind_blend_state = r300_bind_blend_state;
1891 r300->context.delete_blend_state = r300_delete_blend_state;
1892
1893 r300->context.set_blend_color = r300_set_blend_color;
1894
1895 r300->context.set_clip_state = r300_set_clip_state;
1896 r300->context.set_sample_mask = r300_set_sample_mask;
1897
1898 r300->context.set_constant_buffer = r300_set_constant_buffer;
1899
1900 r300->context.create_depth_stencil_alpha_state = r300_create_dsa_state;
1901 r300->context.bind_depth_stencil_alpha_state = r300_bind_dsa_state;
1902 r300->context.delete_depth_stencil_alpha_state = r300_delete_dsa_state;
1903
1904 r300->context.set_stencil_ref = r300_set_stencil_ref;
1905
1906 r300->context.set_framebuffer_state = r300_set_framebuffer_state;
1907
1908 r300->context.create_fs_state = r300_create_fs_state;
1909 r300->context.bind_fs_state = r300_bind_fs_state;
1910 r300->context.delete_fs_state = r300_delete_fs_state;
1911
1912 r300->context.set_polygon_stipple = r300_set_polygon_stipple;
1913
1914 r300->context.create_rasterizer_state = r300_create_rs_state;
1915 r300->context.bind_rasterizer_state = r300_bind_rs_state;
1916 r300->context.delete_rasterizer_state = r300_delete_rs_state;
1917
1918 r300->context.create_sampler_state = r300_create_sampler_state;
1919 r300->context.bind_fragment_sampler_states = r300_bind_sampler_states;
1920 r300->context.bind_vertex_sampler_states = r300_lacks_vertex_textures;
1921 r300->context.delete_sampler_state = r300_delete_sampler_state;
1922
1923 r300->context.set_fragment_sampler_views = r300_set_fragment_sampler_views;
1924 r300->context.create_sampler_view = r300_create_sampler_view;
1925 r300->context.sampler_view_destroy = r300_sampler_view_destroy;
1926
1927 r300->context.set_scissor_state = r300_set_scissor_state;
1928
1929 r300->context.set_viewport_state = r300_set_viewport_state;
1930
1931 r300->context.set_vertex_buffers = r300_set_vertex_buffers;
1932 r300->context.set_index_buffer = r300_set_index_buffer;
1933 r300->context.redefine_user_buffer = u_default_redefine_user_buffer;
1934
1935 r300->context.create_vertex_elements_state = r300_create_vertex_elements_state;
1936 r300->context.bind_vertex_elements_state = r300_bind_vertex_elements_state;
1937 r300->context.delete_vertex_elements_state = r300_delete_vertex_elements_state;
1938
1939 r300->context.create_vs_state = r300_create_vs_state;
1940 r300->context.bind_vs_state = r300_bind_vs_state;
1941 r300->context.delete_vs_state = r300_delete_vs_state;
1942
1943 r300->context.texture_barrier = r300_texture_barrier;
1944 }