r300g: try to use color varyings for texcoords if max texcoord limit is exceeded
[mesa.git] / src / gallium / drivers / r300 / r300_state.c
1 /*
2 * Copyright 2008 Corbin Simpson <MostAwesomeDude@gmail.com>
3 * Copyright 2009 Marek Olšák <maraeo@gmail.com>
4 *
5 * Permission is hereby granted, free of charge, to any person obtaining a
6 * copy of this software and associated documentation files (the "Software"),
7 * to deal in the Software without restriction, including without limitation
8 * on the rights to use, copy, modify, merge, publish, distribute, sub
9 * license, and/or sell copies of the Software, and to permit persons to whom
10 * the Software is furnished to do so, subject to the following conditions:
11 *
12 * The above copyright notice and this permission notice (including the next
13 * paragraph) shall be included in all copies or substantial portions of the
14 * Software.
15 *
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
19 * THE AUTHOR(S) AND/OR THEIR SUPPLIERS BE LIABLE FOR ANY CLAIM,
20 * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
21 * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
22 * USE OR OTHER DEALINGS IN THE SOFTWARE. */
23
24 #include "draw/draw_context.h"
25
26 #include "util/u_framebuffer.h"
27 #include "util/u_half.h"
28 #include "util/u_helpers.h"
29 #include "util/u_math.h"
30 #include "util/u_mm.h"
31 #include "util/u_memory.h"
32 #include "util/u_pack_color.h"
33 #include "util/u_transfer.h"
34
35 #include "tgsi/tgsi_parse.h"
36
37 #include "pipe/p_config.h"
38
39 #include "r300_cb.h"
40 #include "r300_context.h"
41 #include "r300_emit.h"
42 #include "r300_reg.h"
43 #include "r300_screen.h"
44 #include "r300_screen_buffer.h"
45 #include "r300_state_inlines.h"
46 #include "r300_fs.h"
47 #include "r300_texture.h"
48 #include "r300_vs.h"
49
50 /* r300_state: Functions used to intialize state context by translating
51 * Gallium state objects into semi-native r300 state objects. */
52
53 #define UPDATE_STATE(cso, atom) \
54 if (cso != atom.state) { \
55 atom.state = cso; \
56 r300_mark_atom_dirty(r300, &(atom)); \
57 }
58
59 static boolean blend_discard_if_src_alpha_0(unsigned srcRGB, unsigned srcA,
60 unsigned dstRGB, unsigned dstA)
61 {
62 /* If the blend equation is ADD or REVERSE_SUBTRACT,
63 * SRC_ALPHA == 0, and the following state is set, the colorbuffer
64 * will not be changed.
65 * Notice that the dst factors are the src factors inverted. */
66 return (srcRGB == PIPE_BLENDFACTOR_SRC_ALPHA ||
67 srcRGB == PIPE_BLENDFACTOR_SRC_ALPHA_SATURATE ||
68 srcRGB == PIPE_BLENDFACTOR_ZERO) &&
69 (srcA == PIPE_BLENDFACTOR_SRC_COLOR ||
70 srcA == PIPE_BLENDFACTOR_SRC_ALPHA ||
71 srcA == PIPE_BLENDFACTOR_SRC_ALPHA_SATURATE ||
72 srcA == PIPE_BLENDFACTOR_ZERO) &&
73 (dstRGB == PIPE_BLENDFACTOR_INV_SRC_ALPHA ||
74 dstRGB == PIPE_BLENDFACTOR_ONE) &&
75 (dstA == PIPE_BLENDFACTOR_INV_SRC_COLOR ||
76 dstA == PIPE_BLENDFACTOR_INV_SRC_ALPHA ||
77 dstA == PIPE_BLENDFACTOR_ONE);
78 }
79
80 static boolean blend_discard_if_src_alpha_1(unsigned srcRGB, unsigned srcA,
81 unsigned dstRGB, unsigned dstA)
82 {
83 /* If the blend equation is ADD or REVERSE_SUBTRACT,
84 * SRC_ALPHA == 1, and the following state is set, the colorbuffer
85 * will not be changed.
86 * Notice that the dst factors are the src factors inverted. */
87 return (srcRGB == PIPE_BLENDFACTOR_INV_SRC_ALPHA ||
88 srcRGB == PIPE_BLENDFACTOR_ZERO) &&
89 (srcA == PIPE_BLENDFACTOR_INV_SRC_COLOR ||
90 srcA == PIPE_BLENDFACTOR_INV_SRC_ALPHA ||
91 srcA == PIPE_BLENDFACTOR_ZERO) &&
92 (dstRGB == PIPE_BLENDFACTOR_SRC_ALPHA ||
93 dstRGB == PIPE_BLENDFACTOR_ONE) &&
94 (dstA == PIPE_BLENDFACTOR_SRC_COLOR ||
95 dstA == PIPE_BLENDFACTOR_SRC_ALPHA ||
96 dstA == PIPE_BLENDFACTOR_ONE);
97 }
98
99 static boolean blend_discard_if_src_color_0(unsigned srcRGB, unsigned srcA,
100 unsigned dstRGB, unsigned dstA)
101 {
102 /* If the blend equation is ADD or REVERSE_SUBTRACT,
103 * SRC_COLOR == (0,0,0), and the following state is set, the colorbuffer
104 * will not be changed.
105 * Notice that the dst factors are the src factors inverted. */
106 return (srcRGB == PIPE_BLENDFACTOR_SRC_COLOR ||
107 srcRGB == PIPE_BLENDFACTOR_ZERO) &&
108 (srcA == PIPE_BLENDFACTOR_ZERO) &&
109 (dstRGB == PIPE_BLENDFACTOR_INV_SRC_COLOR ||
110 dstRGB == PIPE_BLENDFACTOR_ONE) &&
111 (dstA == PIPE_BLENDFACTOR_ONE);
112 }
113
114 static boolean blend_discard_if_src_color_1(unsigned srcRGB, unsigned srcA,
115 unsigned dstRGB, unsigned dstA)
116 {
117 /* If the blend equation is ADD or REVERSE_SUBTRACT,
118 * SRC_COLOR == (1,1,1), and the following state is set, the colorbuffer
119 * will not be changed.
120 * Notice that the dst factors are the src factors inverted. */
121 return (srcRGB == PIPE_BLENDFACTOR_INV_SRC_COLOR ||
122 srcRGB == PIPE_BLENDFACTOR_ZERO) &&
123 (srcA == PIPE_BLENDFACTOR_ZERO) &&
124 (dstRGB == PIPE_BLENDFACTOR_SRC_COLOR ||
125 dstRGB == PIPE_BLENDFACTOR_ONE) &&
126 (dstA == PIPE_BLENDFACTOR_ONE);
127 }
128
129 static boolean blend_discard_if_src_alpha_color_0(unsigned srcRGB, unsigned srcA,
130 unsigned dstRGB, unsigned dstA)
131 {
132 /* If the blend equation is ADD or REVERSE_SUBTRACT,
133 * SRC_ALPHA_COLOR == (0,0,0,0), and the following state is set,
134 * the colorbuffer will not be changed.
135 * Notice that the dst factors are the src factors inverted. */
136 return (srcRGB == PIPE_BLENDFACTOR_SRC_COLOR ||
137 srcRGB == PIPE_BLENDFACTOR_SRC_ALPHA ||
138 srcRGB == PIPE_BLENDFACTOR_SRC_ALPHA_SATURATE ||
139 srcRGB == PIPE_BLENDFACTOR_ZERO) &&
140 (srcA == PIPE_BLENDFACTOR_SRC_COLOR ||
141 srcA == PIPE_BLENDFACTOR_SRC_ALPHA ||
142 srcA == PIPE_BLENDFACTOR_SRC_ALPHA_SATURATE ||
143 srcA == PIPE_BLENDFACTOR_ZERO) &&
144 (dstRGB == PIPE_BLENDFACTOR_INV_SRC_COLOR ||
145 dstRGB == PIPE_BLENDFACTOR_INV_SRC_ALPHA ||
146 dstRGB == PIPE_BLENDFACTOR_ONE) &&
147 (dstA == PIPE_BLENDFACTOR_INV_SRC_COLOR ||
148 dstA == PIPE_BLENDFACTOR_INV_SRC_ALPHA ||
149 dstA == PIPE_BLENDFACTOR_ONE);
150 }
151
152 static boolean blend_discard_if_src_alpha_color_1(unsigned srcRGB, unsigned srcA,
153 unsigned dstRGB, unsigned dstA)
154 {
155 /* If the blend equation is ADD or REVERSE_SUBTRACT,
156 * SRC_ALPHA_COLOR == (1,1,1,1), and the following state is set,
157 * the colorbuffer will not be changed.
158 * Notice that the dst factors are the src factors inverted. */
159 return (srcRGB == PIPE_BLENDFACTOR_INV_SRC_COLOR ||
160 srcRGB == PIPE_BLENDFACTOR_INV_SRC_ALPHA ||
161 srcRGB == PIPE_BLENDFACTOR_ZERO) &&
162 (srcA == PIPE_BLENDFACTOR_INV_SRC_COLOR ||
163 srcA == PIPE_BLENDFACTOR_INV_SRC_ALPHA ||
164 srcA == PIPE_BLENDFACTOR_ZERO) &&
165 (dstRGB == PIPE_BLENDFACTOR_SRC_COLOR ||
166 dstRGB == PIPE_BLENDFACTOR_SRC_ALPHA ||
167 dstRGB == PIPE_BLENDFACTOR_ONE) &&
168 (dstA == PIPE_BLENDFACTOR_SRC_COLOR ||
169 dstA == PIPE_BLENDFACTOR_SRC_ALPHA ||
170 dstA == PIPE_BLENDFACTOR_ONE);
171 }
172
173 static unsigned blend_discard_conditionally(unsigned eqRGB, unsigned eqA,
174 unsigned dstRGB, unsigned dstA,
175 unsigned srcRGB, unsigned srcA)
176 {
177 unsigned blend_control = 0;
178
179 /* Optimization: discard pixels which don't change the colorbuffer.
180 *
181 * The code below is non-trivial and some math is involved.
182 *
183 * Discarding pixels must be disabled when FP16 AA is enabled.
184 * This is a hardware bug. Also, this implementation wouldn't work
185 * with FP blending enabled and equation clamping disabled.
186 *
187 * Equations other than ADD are rarely used and therefore won't be
188 * optimized. */
189 if ((eqRGB == PIPE_BLEND_ADD || eqRGB == PIPE_BLEND_REVERSE_SUBTRACT) &&
190 (eqA == PIPE_BLEND_ADD || eqA == PIPE_BLEND_REVERSE_SUBTRACT)) {
191 /* ADD: X+Y
192 * REVERSE_SUBTRACT: Y-X
193 *
194 * The idea is:
195 * If X = src*srcFactor = 0 and Y = dst*dstFactor = 1,
196 * then CB will not be changed.
197 *
198 * Given the srcFactor and dstFactor variables, we can derive
199 * what src and dst should be equal to and discard appropriate
200 * pixels.
201 */
202 if (blend_discard_if_src_alpha_0(srcRGB, srcA, dstRGB, dstA)) {
203 blend_control |= R300_DISCARD_SRC_PIXELS_SRC_ALPHA_0;
204 } else if (blend_discard_if_src_alpha_1(srcRGB, srcA,
205 dstRGB, dstA)) {
206 blend_control |= R300_DISCARD_SRC_PIXELS_SRC_ALPHA_1;
207 } else if (blend_discard_if_src_color_0(srcRGB, srcA,
208 dstRGB, dstA)) {
209 blend_control |= R300_DISCARD_SRC_PIXELS_SRC_COLOR_0;
210 } else if (blend_discard_if_src_color_1(srcRGB, srcA,
211 dstRGB, dstA)) {
212 blend_control |= R300_DISCARD_SRC_PIXELS_SRC_COLOR_1;
213 } else if (blend_discard_if_src_alpha_color_0(srcRGB, srcA,
214 dstRGB, dstA)) {
215 blend_control |=
216 R300_DISCARD_SRC_PIXELS_SRC_ALPHA_COLOR_0;
217 } else if (blend_discard_if_src_alpha_color_1(srcRGB, srcA,
218 dstRGB, dstA)) {
219 blend_control |=
220 R300_DISCARD_SRC_PIXELS_SRC_ALPHA_COLOR_1;
221 }
222 }
223 return blend_control;
224 }
225
226 /* The hardware colormask is clunky a must be swizzled depending on the format.
227 * This was figured out by trial-and-error. */
228 static unsigned bgra_cmask(unsigned mask)
229 {
230 return ((mask & PIPE_MASK_R) << 2) |
231 ((mask & PIPE_MASK_B) >> 2) |
232 (mask & (PIPE_MASK_G | PIPE_MASK_A));
233 }
234
235 static unsigned rgba_cmask(unsigned mask)
236 {
237 return mask & PIPE_MASK_RGBA;
238 }
239
240 static unsigned rrrr_cmask(unsigned mask)
241 {
242 return (mask & PIPE_MASK_R) |
243 ((mask & PIPE_MASK_R) << 1) |
244 ((mask & PIPE_MASK_R) << 2) |
245 ((mask & PIPE_MASK_R) << 3);
246 }
247
248 static unsigned aaaa_cmask(unsigned mask)
249 {
250 return ((mask & PIPE_MASK_A) >> 3) |
251 ((mask & PIPE_MASK_A) >> 2) |
252 ((mask & PIPE_MASK_A) >> 1) |
253 (mask & PIPE_MASK_A);
254 }
255
256 static unsigned grrg_cmask(unsigned mask)
257 {
258 return ((mask & PIPE_MASK_R) << 1) |
259 ((mask & PIPE_MASK_R) << 2) |
260 ((mask & PIPE_MASK_G) >> 1) |
261 ((mask & PIPE_MASK_G) << 2);
262 }
263
264 static unsigned arra_cmask(unsigned mask)
265 {
266 return ((mask & PIPE_MASK_R) << 1) |
267 ((mask & PIPE_MASK_R) << 2) |
268 ((mask & PIPE_MASK_A) >> 3) |
269 (mask & PIPE_MASK_A);
270 }
271
272 static unsigned blend_read_enable(unsigned eqRGB, unsigned eqA,
273 unsigned dstRGB, unsigned dstA,
274 unsigned srcRGB, unsigned srcA,
275 boolean src_alpha_optz)
276 {
277 unsigned blend_control = 0;
278
279 /* Optimization: some operations do not require the destination color.
280 *
281 * When SRC_ALPHA_SATURATE is used, colorbuffer reads must be enabled,
282 * otherwise blending gives incorrect results. It seems to be
283 * a hardware bug. */
284 if (eqRGB == PIPE_BLEND_MIN || eqA == PIPE_BLEND_MIN ||
285 eqRGB == PIPE_BLEND_MAX || eqA == PIPE_BLEND_MAX ||
286 dstRGB != PIPE_BLENDFACTOR_ZERO ||
287 dstA != PIPE_BLENDFACTOR_ZERO ||
288 srcRGB == PIPE_BLENDFACTOR_DST_COLOR ||
289 srcRGB == PIPE_BLENDFACTOR_DST_ALPHA ||
290 srcRGB == PIPE_BLENDFACTOR_INV_DST_COLOR ||
291 srcRGB == PIPE_BLENDFACTOR_INV_DST_ALPHA ||
292 srcA == PIPE_BLENDFACTOR_DST_COLOR ||
293 srcA == PIPE_BLENDFACTOR_DST_ALPHA ||
294 srcA == PIPE_BLENDFACTOR_INV_DST_COLOR ||
295 srcA == PIPE_BLENDFACTOR_INV_DST_ALPHA ||
296 srcRGB == PIPE_BLENDFACTOR_SRC_ALPHA_SATURATE) {
297 /* Enable reading from the colorbuffer. */
298 blend_control |= R300_READ_ENABLE;
299
300 if (src_alpha_optz) {
301 /* Optimization: Depending on incoming pixels, we can
302 * conditionally disable the reading in hardware... */
303 if (eqRGB != PIPE_BLEND_MIN && eqA != PIPE_BLEND_MIN &&
304 eqRGB != PIPE_BLEND_MAX && eqA != PIPE_BLEND_MAX) {
305 /* Disable reading if SRC_ALPHA == 0. */
306 if ((dstRGB == PIPE_BLENDFACTOR_SRC_ALPHA ||
307 dstRGB == PIPE_BLENDFACTOR_ZERO) &&
308 (dstA == PIPE_BLENDFACTOR_SRC_COLOR ||
309 dstA == PIPE_BLENDFACTOR_SRC_ALPHA ||
310 dstA == PIPE_BLENDFACTOR_ZERO) &&
311 (srcRGB != PIPE_BLENDFACTOR_DST_COLOR &&
312 srcRGB != PIPE_BLENDFACTOR_DST_ALPHA &&
313 srcRGB != PIPE_BLENDFACTOR_INV_DST_COLOR &&
314 srcRGB != PIPE_BLENDFACTOR_INV_DST_ALPHA)) {
315 blend_control |= R500_SRC_ALPHA_0_NO_READ;
316 }
317
318 /* Disable reading if SRC_ALPHA == 1. */
319 if ((dstRGB == PIPE_BLENDFACTOR_INV_SRC_ALPHA ||
320 dstRGB == PIPE_BLENDFACTOR_ZERO) &&
321 (dstA == PIPE_BLENDFACTOR_INV_SRC_COLOR ||
322 dstA == PIPE_BLENDFACTOR_INV_SRC_ALPHA ||
323 dstA == PIPE_BLENDFACTOR_ZERO) &&
324 (srcRGB != PIPE_BLENDFACTOR_DST_COLOR &&
325 srcRGB != PIPE_BLENDFACTOR_DST_ALPHA &&
326 srcRGB != PIPE_BLENDFACTOR_INV_DST_COLOR &&
327 srcRGB != PIPE_BLENDFACTOR_INV_DST_ALPHA)) {
328 blend_control |= R500_SRC_ALPHA_1_NO_READ;
329 }
330 }
331 }
332 }
333 return blend_control;
334 }
335
336 /* Create a new blend state based on the CSO blend state.
337 *
338 * This encompasses alpha blending, logic/raster ops, and blend dithering. */
339 static void* r300_create_blend_state(struct pipe_context* pipe,
340 const struct pipe_blend_state* state)
341 {
342 struct r300_screen* r300screen = r300_screen(pipe->screen);
343 struct r300_blend_state* blend = CALLOC_STRUCT(r300_blend_state);
344 uint32_t blend_control = 0; /* R300_RB3D_CBLEND: 0x4e04 */
345 uint32_t blend_control_noclamp = 0; /* R300_RB3D_CBLEND: 0x4e04 */
346 uint32_t blend_control_noalpha = 0; /* R300_RB3D_CBLEND: 0x4e04 */
347 uint32_t alpha_blend_control = 0; /* R300_RB3D_ABLEND: 0x4e08 */
348 uint32_t alpha_blend_control_noclamp = 0; /* R300_RB3D_ABLEND: 0x4e08 */
349 uint32_t alpha_blend_control_noalpha = 0; /* R300_RB3D_ABLEND: 0x4e08 */
350 uint32_t rop = 0; /* R300_RB3D_ROPCNTL: 0x4e18 */
351 uint32_t dither = 0; /* R300_RB3D_DITHER_CTL: 0x4e50 */
352 int i;
353
354 const unsigned eqRGB = state->rt[0].rgb_func;
355 const unsigned srcRGB = state->rt[0].rgb_src_factor;
356 const unsigned dstRGB = state->rt[0].rgb_dst_factor;
357
358 const unsigned eqA = state->rt[0].alpha_func;
359 const unsigned srcA = state->rt[0].alpha_src_factor;
360 const unsigned dstA = state->rt[0].alpha_dst_factor;
361
362 unsigned srcRGBX = srcRGB;
363 unsigned dstRGBX = dstRGB;
364 CB_LOCALS;
365
366 blend->state = *state;
367
368 /* force DST_ALPHA to ONE where we can */
369 switch (srcRGBX) {
370 case PIPE_BLENDFACTOR_DST_ALPHA:
371 srcRGBX = PIPE_BLENDFACTOR_ONE;
372 break;
373 case PIPE_BLENDFACTOR_INV_DST_ALPHA:
374 srcRGBX = PIPE_BLENDFACTOR_ZERO;
375 break;
376 }
377
378 switch (dstRGBX) {
379 case PIPE_BLENDFACTOR_DST_ALPHA:
380 dstRGBX = PIPE_BLENDFACTOR_ONE;
381 break;
382 case PIPE_BLENDFACTOR_INV_DST_ALPHA:
383 dstRGBX = PIPE_BLENDFACTOR_ZERO;
384 break;
385 }
386
387 /* Get blending register values. */
388 if (state->rt[0].blend_enable) {
389 unsigned blend_eq;
390
391 /* despite the name, ALPHA_BLEND_ENABLE has nothing to do with alpha,
392 * this is just the crappy D3D naming */
393 blend_control = blend_control_noclamp =
394 R300_ALPHA_BLEND_ENABLE |
395 ( r300_translate_blend_factor(srcRGB) << R300_SRC_BLEND_SHIFT) |
396 ( r300_translate_blend_factor(dstRGB) << R300_DST_BLEND_SHIFT);
397
398 blend_control_noalpha =
399 R300_ALPHA_BLEND_ENABLE |
400 ( r300_translate_blend_factor(srcRGBX) << R300_SRC_BLEND_SHIFT) |
401 ( r300_translate_blend_factor(dstRGBX) << R300_DST_BLEND_SHIFT);
402
403 blend_eq = r300_translate_blend_function(eqRGB, TRUE);
404 blend_control |= blend_eq;
405 blend_control_noalpha |= blend_eq;
406 blend_control_noclamp |= r300_translate_blend_function(eqRGB, FALSE);
407
408 /* Optimization: some operations do not require the destination color. */
409 blend_control |= blend_read_enable(eqRGB, eqA, dstRGB, dstA,
410 srcRGB, srcA, r300screen->caps.is_r500);
411 blend_control_noclamp |= blend_read_enable(eqRGB, eqA, dstRGB, dstA,
412 srcRGB, srcA, FALSE);
413 blend_control_noalpha |= blend_read_enable(eqRGB, eqA, dstRGBX, dstA,
414 srcRGBX, srcA, r300screen->caps.is_r500);
415
416 /* Optimization: discard pixels which don't change the colorbuffer.
417 * It cannot be used with FP16 AA. */
418 blend_control |= blend_discard_conditionally(eqRGB, eqA, dstRGB, dstA,
419 srcRGB, srcA);
420 blend_control_noalpha |= blend_discard_conditionally(eqRGB, eqA, dstRGBX, dstA,
421 srcRGBX, srcA);
422
423 /* separate alpha */
424 if (srcA != srcRGB || dstA != dstRGB || eqA != eqRGB) {
425 blend_control |= R300_SEPARATE_ALPHA_ENABLE;
426 blend_control_noclamp |= R300_SEPARATE_ALPHA_ENABLE;
427
428 alpha_blend_control = alpha_blend_control_noclamp =
429 (r300_translate_blend_factor(srcA) << R300_SRC_BLEND_SHIFT) |
430 (r300_translate_blend_factor(dstA) << R300_DST_BLEND_SHIFT);
431 alpha_blend_control |= r300_translate_blend_function(eqA, TRUE);
432 alpha_blend_control_noclamp |= r300_translate_blend_function(eqA, FALSE);
433 }
434 if (srcA != srcRGBX || dstA != dstRGBX || eqA != eqRGB) {
435 blend_control_noalpha |= R300_SEPARATE_ALPHA_ENABLE;
436
437 alpha_blend_control_noalpha =
438 (r300_translate_blend_factor(srcA) << R300_SRC_BLEND_SHIFT) |
439 (r300_translate_blend_factor(dstA) << R300_DST_BLEND_SHIFT) |
440 r300_translate_blend_function(eqA, TRUE);
441 }
442 }
443
444 /* PIPE_LOGICOP_* don't need to be translated, fortunately. */
445 if (state->logicop_enable) {
446 rop = R300_RB3D_ROPCNTL_ROP_ENABLE |
447 (state->logicop_func) << R300_RB3D_ROPCNTL_ROP_SHIFT;
448 }
449
450 /* Neither fglrx nor classic r300 ever set this, regardless of dithering
451 * state. Since it's an optional implementation detail, we can leave it
452 * out and never dither.
453 *
454 * This could be revisited if we ever get quality or conformance hints.
455 *
456 if (state->dither) {
457 dither = R300_RB3D_DITHER_CTL_DITHER_MODE_LUT |
458 R300_RB3D_DITHER_CTL_ALPHA_DITHER_MODE_LUT;
459 }
460 */
461
462 /* Build a command buffer. */
463 {
464 unsigned (*func[COLORMASK_NUM_SWIZZLES])(unsigned) = {
465 bgra_cmask,
466 rgba_cmask,
467 rrrr_cmask,
468 aaaa_cmask,
469 grrg_cmask,
470 arra_cmask,
471 bgra_cmask,
472 rgba_cmask
473 };
474
475 for (i = 0; i < COLORMASK_NUM_SWIZZLES; i++) {
476 boolean has_alpha = i != COLORMASK_RGBX && i != COLORMASK_BGRX;
477
478 BEGIN_CB(blend->cb_clamp[i], 8);
479 OUT_CB_REG(R300_RB3D_ROPCNTL, rop);
480 OUT_CB_REG_SEQ(R300_RB3D_CBLEND, 3);
481 OUT_CB(has_alpha ? blend_control : blend_control_noalpha);
482 OUT_CB(has_alpha ? alpha_blend_control : alpha_blend_control_noalpha);
483 OUT_CB(func[i](state->rt[0].colormask));
484 OUT_CB_REG(R300_RB3D_DITHER_CTL, dither);
485 END_CB;
486 }
487 }
488
489 /* Build a command buffer (for FP16). */
490 BEGIN_CB(blend->cb_noclamp, 8);
491 OUT_CB_REG(R300_RB3D_ROPCNTL, rop);
492 OUT_CB_REG_SEQ(R300_RB3D_CBLEND, 3);
493 OUT_CB(blend_control_noclamp);
494 OUT_CB(alpha_blend_control_noclamp);
495 OUT_CB(rgba_cmask(state->rt[0].colormask));
496 OUT_CB_REG(R300_RB3D_DITHER_CTL, dither);
497 END_CB;
498
499 /* The same as above, but with no colorbuffer reads and writes. */
500 BEGIN_CB(blend->cb_no_readwrite, 8);
501 OUT_CB_REG(R300_RB3D_ROPCNTL, rop);
502 OUT_CB_REG_SEQ(R300_RB3D_CBLEND, 3);
503 OUT_CB(0);
504 OUT_CB(0);
505 OUT_CB(0);
506 OUT_CB_REG(R300_RB3D_DITHER_CTL, dither);
507 END_CB;
508
509 return (void*)blend;
510 }
511
512 /* Bind blend state. */
513 static void r300_bind_blend_state(struct pipe_context* pipe,
514 void* state)
515 {
516 struct r300_context* r300 = r300_context(pipe);
517 struct r300_blend_state *blend = (struct r300_blend_state*)state;
518 boolean last_alpha_to_one = r300->alpha_to_one;
519 boolean last_alpha_to_coverage = r300->alpha_to_coverage;
520
521 UPDATE_STATE(state, r300->blend_state);
522
523 if (!blend)
524 return;
525
526 r300->alpha_to_one = blend->state.alpha_to_one;
527 r300->alpha_to_coverage = blend->state.alpha_to_coverage;
528
529 if (r300->alpha_to_one != last_alpha_to_one && r300->msaa_enable &&
530 r300->fs_status == FRAGMENT_SHADER_VALID) {
531 r300->fs_status = FRAGMENT_SHADER_MAYBE_DIRTY;
532 }
533
534 if (r300->alpha_to_coverage != last_alpha_to_coverage &&
535 r300->msaa_enable) {
536 r300_mark_atom_dirty(r300, &r300->dsa_state);
537 }
538 }
539
540 /* Free blend state. */
541 static void r300_delete_blend_state(struct pipe_context* pipe,
542 void* state)
543 {
544 FREE(state);
545 }
546
547 /* Convert float to 10bit integer */
548 static unsigned float_to_fixed10(float f)
549 {
550 return CLAMP((unsigned)(f * 1023.9f), 0, 1023);
551 }
552
553 /* Set blend color.
554 * Setup both R300 and R500 registers, figure out later which one to write. */
555 static void r300_set_blend_color(struct pipe_context* pipe,
556 const struct pipe_blend_color* color)
557 {
558 struct r300_context* r300 = r300_context(pipe);
559 struct pipe_framebuffer_state *fb = r300->fb_state.state;
560 struct r300_blend_color_state *state =
561 (struct r300_blend_color_state*)r300->blend_color_state.state;
562 struct pipe_blend_color c;
563 enum pipe_format format = fb->nr_cbufs ? fb->cbufs[0]->format : 0;
564 float tmp;
565 CB_LOCALS;
566
567 state->state = *color; /* Save it, so that we can reuse it in set_fb_state */
568 c = *color;
569
570 /* The blend color is dependent on the colorbuffer format. */
571 if (fb->nr_cbufs) {
572 switch (format) {
573 case PIPE_FORMAT_R8_UNORM:
574 case PIPE_FORMAT_L8_UNORM:
575 case PIPE_FORMAT_I8_UNORM:
576 c.color[1] = c.color[0];
577 break;
578
579 case PIPE_FORMAT_A8_UNORM:
580 c.color[1] = c.color[3];
581 break;
582
583 case PIPE_FORMAT_R8G8_UNORM:
584 c.color[2] = c.color[1];
585 break;
586
587 case PIPE_FORMAT_L8A8_UNORM:
588 c.color[2] = c.color[3];
589 break;
590
591 case PIPE_FORMAT_R8G8B8A8_UNORM:
592 case PIPE_FORMAT_R8G8B8X8_UNORM:
593 tmp = c.color[0];
594 c.color[0] = c.color[2];
595 c.color[2] = tmp;
596 break;
597
598 default:;
599 }
600 }
601
602 if (r300->screen->caps.is_r500) {
603 BEGIN_CB(state->cb, 3);
604 OUT_CB_REG_SEQ(R500_RB3D_CONSTANT_COLOR_AR, 2);
605
606 switch (format) {
607 case PIPE_FORMAT_R16G16B16A16_FLOAT:
608 OUT_CB(util_float_to_half(c.color[2]) |
609 (util_float_to_half(c.color[3]) << 16));
610 OUT_CB(util_float_to_half(c.color[0]) |
611 (util_float_to_half(c.color[1]) << 16));
612 break;
613
614 default:
615 OUT_CB(float_to_fixed10(c.color[0]) |
616 (float_to_fixed10(c.color[3]) << 16));
617 OUT_CB(float_to_fixed10(c.color[2]) |
618 (float_to_fixed10(c.color[1]) << 16));
619 }
620
621 END_CB;
622 } else {
623 union util_color uc;
624 util_pack_color(c.color, PIPE_FORMAT_B8G8R8A8_UNORM, &uc);
625
626 BEGIN_CB(state->cb, 2);
627 OUT_CB_REG(R300_RB3D_BLEND_COLOR, uc.ui);
628 END_CB;
629 }
630
631 r300_mark_atom_dirty(r300, &r300->blend_color_state);
632 }
633
634 static void r300_set_clip_state(struct pipe_context* pipe,
635 const struct pipe_clip_state* state)
636 {
637 struct r300_context* r300 = r300_context(pipe);
638 struct r300_clip_state *clip =
639 (struct r300_clip_state*)r300->clip_state.state;
640 CB_LOCALS;
641
642 if (r300->screen->caps.has_tcl) {
643 BEGIN_CB(clip->cb, r300->clip_state.size);
644 OUT_CB_REG(R300_VAP_PVS_VECTOR_INDX_REG,
645 (r300->screen->caps.is_r500 ?
646 R500_PVS_UCP_START : R300_PVS_UCP_START));
647 OUT_CB_ONE_REG(R300_VAP_PVS_UPLOAD_DATA, 6 * 4);
648 OUT_CB_TABLE(state->ucp, 6 * 4);
649 END_CB;
650
651 r300_mark_atom_dirty(r300, &r300->clip_state);
652 } else {
653 draw_set_clip_state(r300->draw, state);
654 }
655 }
656
657 /* Create a new depth, stencil, and alpha state based on the CSO dsa state.
658 *
659 * This contains the depth buffer, stencil buffer, alpha test, and such.
660 * On the Radeon, depth and stencil buffer setup are intertwined, which is
661 * the reason for some of the strange-looking assignments across registers. */
662 static void* r300_create_dsa_state(struct pipe_context* pipe,
663 const struct pipe_depth_stencil_alpha_state* state)
664 {
665 boolean is_r500 = r300_screen(pipe->screen)->caps.is_r500;
666 struct r300_dsa_state* dsa = CALLOC_STRUCT(r300_dsa_state);
667 CB_LOCALS;
668 uint32_t alpha_value_fp16 = 0;
669 uint32_t z_buffer_control = 0;
670 uint32_t z_stencil_control = 0;
671 uint32_t stencil_ref_mask = 0;
672 uint32_t stencil_ref_bf = 0;
673
674 dsa->dsa = *state;
675
676 /* Depth test setup. - separate write mask depth for decomp flush */
677 if (state->depth.writemask) {
678 z_buffer_control |= R300_Z_WRITE_ENABLE;
679 }
680
681 if (state->depth.enabled) {
682 z_buffer_control |= R300_Z_ENABLE;
683
684 z_stencil_control |=
685 (r300_translate_depth_stencil_function(state->depth.func) <<
686 R300_Z_FUNC_SHIFT);
687 }
688
689 /* Stencil buffer setup. */
690 if (state->stencil[0].enabled) {
691 z_buffer_control |= R300_STENCIL_ENABLE;
692 z_stencil_control |=
693 (r300_translate_depth_stencil_function(state->stencil[0].func) <<
694 R300_S_FRONT_FUNC_SHIFT) |
695 (r300_translate_stencil_op(state->stencil[0].fail_op) <<
696 R300_S_FRONT_SFAIL_OP_SHIFT) |
697 (r300_translate_stencil_op(state->stencil[0].zpass_op) <<
698 R300_S_FRONT_ZPASS_OP_SHIFT) |
699 (r300_translate_stencil_op(state->stencil[0].zfail_op) <<
700 R300_S_FRONT_ZFAIL_OP_SHIFT);
701
702 stencil_ref_mask =
703 (state->stencil[0].valuemask << R300_STENCILMASK_SHIFT) |
704 (state->stencil[0].writemask << R300_STENCILWRITEMASK_SHIFT);
705
706 if (state->stencil[1].enabled) {
707 dsa->two_sided = TRUE;
708
709 z_buffer_control |= R300_STENCIL_FRONT_BACK;
710 z_stencil_control |=
711 (r300_translate_depth_stencil_function(state->stencil[1].func) <<
712 R300_S_BACK_FUNC_SHIFT) |
713 (r300_translate_stencil_op(state->stencil[1].fail_op) <<
714 R300_S_BACK_SFAIL_OP_SHIFT) |
715 (r300_translate_stencil_op(state->stencil[1].zpass_op) <<
716 R300_S_BACK_ZPASS_OP_SHIFT) |
717 (r300_translate_stencil_op(state->stencil[1].zfail_op) <<
718 R300_S_BACK_ZFAIL_OP_SHIFT);
719
720 stencil_ref_bf =
721 (state->stencil[1].valuemask << R300_STENCILMASK_SHIFT) |
722 (state->stencil[1].writemask << R300_STENCILWRITEMASK_SHIFT);
723
724 if (is_r500) {
725 z_buffer_control |= R500_STENCIL_REFMASK_FRONT_BACK;
726 } else {
727 dsa->two_sided_stencil_ref =
728 (state->stencil[0].valuemask != state->stencil[1].valuemask ||
729 state->stencil[0].writemask != state->stencil[1].writemask);
730 }
731 }
732 }
733
734 /* Alpha test setup. */
735 if (state->alpha.enabled) {
736 dsa->alpha_function =
737 r300_translate_alpha_function(state->alpha.func) |
738 R300_FG_ALPHA_FUNC_ENABLE;
739
740 dsa->alpha_function |= float_to_ubyte(state->alpha.ref_value);
741 alpha_value_fp16 = util_float_to_half(state->alpha.ref_value);
742 }
743
744 BEGIN_CB(&dsa->cb_begin, 8);
745 OUT_CB_REG_SEQ(R300_ZB_CNTL, 3);
746 OUT_CB(z_buffer_control);
747 OUT_CB(z_stencil_control);
748 OUT_CB(stencil_ref_mask);
749 OUT_CB_REG(R500_ZB_STENCILREFMASK_BF, stencil_ref_bf);
750 OUT_CB_REG(R500_FG_ALPHA_VALUE, alpha_value_fp16);
751 END_CB;
752
753 BEGIN_CB(dsa->cb_zb_no_readwrite, 8);
754 OUT_CB_REG_SEQ(R300_ZB_CNTL, 3);
755 OUT_CB(0);
756 OUT_CB(0);
757 OUT_CB(0);
758 OUT_CB_REG(R500_ZB_STENCILREFMASK_BF, 0);
759 OUT_CB_REG(R500_FG_ALPHA_VALUE, alpha_value_fp16);
760 END_CB;
761
762 return (void*)dsa;
763 }
764
765 static void r300_dsa_inject_stencilref(struct r300_context *r300)
766 {
767 struct r300_dsa_state *dsa =
768 (struct r300_dsa_state*)r300->dsa_state.state;
769
770 if (!dsa)
771 return;
772
773 dsa->stencil_ref_mask =
774 (dsa->stencil_ref_mask & ~R300_STENCILREF_MASK) |
775 r300->stencil_ref.ref_value[0];
776 dsa->stencil_ref_bf =
777 (dsa->stencil_ref_bf & ~R300_STENCILREF_MASK) |
778 r300->stencil_ref.ref_value[1];
779 }
780
781 /* Bind DSA state. */
782 static void r300_bind_dsa_state(struct pipe_context* pipe,
783 void* state)
784 {
785 struct r300_context* r300 = r300_context(pipe);
786
787 if (!state) {
788 return;
789 }
790
791 UPDATE_STATE(state, r300->dsa_state);
792
793 r300_mark_atom_dirty(r300, &r300->hyperz_state); /* Will be updated before the emission. */
794 r300_dsa_inject_stencilref(r300);
795 }
796
797 /* Free DSA state. */
798 static void r300_delete_dsa_state(struct pipe_context* pipe,
799 void* state)
800 {
801 FREE(state);
802 }
803
804 static void r300_set_stencil_ref(struct pipe_context* pipe,
805 const struct pipe_stencil_ref* sr)
806 {
807 struct r300_context* r300 = r300_context(pipe);
808
809 r300->stencil_ref = *sr;
810
811 r300_dsa_inject_stencilref(r300);
812 r300_mark_atom_dirty(r300, &r300->dsa_state);
813 }
814
815 static void r300_tex_set_tiling_flags(struct r300_context *r300,
816 struct r300_resource *tex,
817 unsigned level)
818 {
819 /* Check if the macrotile flag needs to be changed.
820 * Skip changing the flags otherwise. */
821 if (tex->tex.macrotile[tex->surface_level] !=
822 tex->tex.macrotile[level]) {
823 r300->rws->buffer_set_tiling(tex->buf, r300->cs,
824 tex->tex.microtile, tex->tex.macrotile[level],
825 0, 0, 0, 0, 0,
826 tex->tex.stride_in_bytes[0]);
827
828 tex->surface_level = level;
829 }
830 }
831
832 /* This switcheroo is needed just because of goddamned MACRO_SWITCH. */
833 static void r300_fb_set_tiling_flags(struct r300_context *r300,
834 const struct pipe_framebuffer_state *state)
835 {
836 unsigned i;
837
838 /* Set tiling flags for new surfaces. */
839 for (i = 0; i < state->nr_cbufs; i++) {
840 r300_tex_set_tiling_flags(r300,
841 r300_resource(state->cbufs[i]->texture),
842 state->cbufs[i]->u.tex.level);
843 }
844 if (state->zsbuf) {
845 r300_tex_set_tiling_flags(r300,
846 r300_resource(state->zsbuf->texture),
847 state->zsbuf->u.tex.level);
848 }
849 }
850
851 static void r300_print_fb_surf_info(struct pipe_surface *surf, unsigned index,
852 const char *binding)
853 {
854 struct pipe_resource *tex = surf->texture;
855 struct r300_resource *rtex = r300_resource(tex);
856
857 fprintf(stderr,
858 "r300: %s[%i] Dim: %ix%i, Firstlayer: %i, "
859 "Lastlayer: %i, Level: %i, Format: %s\n"
860
861 "r300: TEX: Macro: %s, Micro: %s, "
862 "Dim: %ix%ix%i, LastLevel: %i, Format: %s\n",
863
864 binding, index, surf->width, surf->height,
865 surf->u.tex.first_layer, surf->u.tex.last_layer, surf->u.tex.level,
866 util_format_short_name(surf->format),
867
868 rtex->tex.macrotile[0] ? "YES" : " NO",
869 rtex->tex.microtile ? "YES" : " NO",
870 tex->width0, tex->height0, tex->depth0,
871 tex->last_level, util_format_short_name(surf->format));
872 }
873
874 void r300_mark_fb_state_dirty(struct r300_context *r300,
875 enum r300_fb_state_change change)
876 {
877 struct pipe_framebuffer_state *state = r300->fb_state.state;
878
879 r300_mark_atom_dirty(r300, &r300->gpu_flush);
880 r300_mark_atom_dirty(r300, &r300->fb_state);
881
882 /* What is marked as dirty depends on the enum r300_fb_state_change. */
883 if (change == R300_CHANGED_FB_STATE) {
884 r300_mark_atom_dirty(r300, &r300->aa_state);
885 r300_mark_atom_dirty(r300, &r300->dsa_state); /* for AlphaRef */
886 r300_set_blend_color(&r300->context, r300->blend_color_state.state);
887 }
888
889 if (change == R300_CHANGED_FB_STATE ||
890 change == R300_CHANGED_HYPERZ_FLAG) {
891 r300_mark_atom_dirty(r300, &r300->hyperz_state);
892 }
893
894 if (change == R300_CHANGED_FB_STATE ||
895 change == R300_CHANGED_MULTIWRITE) {
896 r300_mark_atom_dirty(r300, &r300->fb_state_pipelined);
897 }
898
899 /* Now compute the fb_state atom size. */
900 r300->fb_state.size = 2 + (8 * state->nr_cbufs);
901
902 if (r300->cbzb_clear)
903 r300->fb_state.size += 10;
904 else if (state->zsbuf) {
905 r300->fb_state.size += 10;
906 if (r300->hyperz_enabled)
907 r300->fb_state.size += 8;
908 }
909
910 if (r300->cmask_in_use) {
911 r300->fb_state.size += 6;
912 if (r300->screen->caps.is_r500 && r300->screen->info.drm_minor >= 29) {
913 r300->fb_state.size += 3;
914 }
915 }
916
917 /* The size of the rest of atoms stays the same. */
918 }
919
920 static unsigned r300_get_num_samples(struct r300_context *r300)
921 {
922 struct pipe_framebuffer_state* fb =
923 (struct pipe_framebuffer_state*)r300->fb_state.state;
924 unsigned i, num_samples;
925
926 if (!fb->nr_cbufs && !fb->zsbuf)
927 return 1;
928
929 num_samples = 6;
930
931 for (i = 0; i < fb->nr_cbufs; i++)
932 num_samples = MIN2(num_samples, fb->cbufs[i]->texture->nr_samples);
933
934 if (fb->zsbuf)
935 num_samples = MIN2(num_samples, fb->zsbuf->texture->nr_samples);
936
937 if (!num_samples)
938 num_samples = 1;
939
940 return num_samples;
941 }
942
943 static void
944 r300_set_framebuffer_state(struct pipe_context* pipe,
945 const struct pipe_framebuffer_state* state)
946 {
947 struct r300_context* r300 = r300_context(pipe);
948 struct r300_aa_state *aa = (struct r300_aa_state*)r300->aa_state.state;
949 struct pipe_framebuffer_state *old_state = r300->fb_state.state;
950 unsigned max_width, max_height, i;
951 uint32_t zbuffer_bpp = 0;
952 boolean unlock_zbuffer = FALSE;
953
954 if (r300->screen->caps.is_r500) {
955 max_width = max_height = 4096;
956 } else if (r300->screen->caps.is_r400) {
957 max_width = max_height = 4021;
958 } else {
959 max_width = max_height = 2560;
960 }
961
962 if (state->width > max_width || state->height > max_height) {
963 fprintf(stderr, "r300: Implementation error: Render targets are too "
964 "big in %s, refusing to bind framebuffer state!\n", __FUNCTION__);
965 return;
966 }
967
968 if (old_state->zsbuf && r300->zmask_in_use && !r300->locked_zbuffer) {
969 /* There is a zmask in use, what are we gonna do? */
970 if (state->zsbuf) {
971 if (!pipe_surface_equal(old_state->zsbuf, state->zsbuf)) {
972 /* Decompress the currently bound zbuffer before we bind another one. */
973 r300_decompress_zmask(r300);
974 r300->hiz_in_use = FALSE;
975 }
976 } else {
977 /* We don't bind another zbuffer, so lock the current one. */
978 pipe_surface_reference(&r300->locked_zbuffer, old_state->zsbuf);
979 }
980 } else if (r300->locked_zbuffer) {
981 /* We have a locked zbuffer now, what are we gonna do? */
982 if (state->zsbuf) {
983 if (!pipe_surface_equal(r300->locked_zbuffer, state->zsbuf)) {
984 /* We are binding some other zbuffer, so decompress the locked one,
985 * it gets unlocked automatically. */
986 r300_decompress_zmask_locked_unsafe(r300);
987 r300->hiz_in_use = FALSE;
988 } else {
989 /* We are binding the locked zbuffer again, so unlock it. */
990 unlock_zbuffer = TRUE;
991 }
992 }
993 }
994 assert(state->zsbuf || (r300->locked_zbuffer && !unlock_zbuffer) || !r300->zmask_in_use);
995
996 /* Set whether CMASK can be used. */
997 r300->cmask_in_use =
998 state->nr_cbufs == 1 &&
999 r300->screen->cmask_resource == state->cbufs[0]->texture;
1000
1001 /* Need to reset clamping or colormask. */
1002 r300_mark_atom_dirty(r300, &r300->blend_state);
1003
1004 /* Re-swizzle the blend color. */
1005 r300_set_blend_color(pipe, &((struct r300_blend_color_state*)r300->blend_color_state.state)->state);
1006
1007 /* If zsbuf is set from NULL to non-NULL or vice versa.. */
1008 if (!!old_state->zsbuf != !!state->zsbuf) {
1009 r300_mark_atom_dirty(r300, &r300->dsa_state);
1010 }
1011
1012 if (r300->screen->info.drm_minor < 12) {
1013 /* The tiling flags are dependent on the surface miplevel, unfortunately.
1014 * This workarounds a bad design decision in old kernels which were
1015 * rewriting tile fields in registers. */
1016 r300_fb_set_tiling_flags(r300, state);
1017 }
1018
1019 util_copy_framebuffer_state(r300->fb_state.state, state);
1020
1021 if (unlock_zbuffer) {
1022 pipe_surface_reference(&r300->locked_zbuffer, NULL);
1023 }
1024
1025 r300_mark_fb_state_dirty(r300, R300_CHANGED_FB_STATE);
1026
1027 if (state->zsbuf) {
1028 switch (util_format_get_blocksize(state->zsbuf->format)) {
1029 case 2:
1030 zbuffer_bpp = 16;
1031 break;
1032 case 4:
1033 zbuffer_bpp = 24;
1034 break;
1035 }
1036
1037 /* Polygon offset depends on the zbuffer bit depth. */
1038 if (r300->zbuffer_bpp != zbuffer_bpp) {
1039 r300->zbuffer_bpp = zbuffer_bpp;
1040
1041 if (r300->polygon_offset_enabled)
1042 r300_mark_atom_dirty(r300, &r300->rs_state);
1043 }
1044 }
1045
1046 r300->num_samples = r300_get_num_samples(r300);
1047
1048 /* Set up AA config. */
1049 if (r300->num_samples > 1) {
1050 switch (r300->num_samples) {
1051 case 2:
1052 aa->aa_config = R300_GB_AA_CONFIG_AA_ENABLE |
1053 R300_GB_AA_CONFIG_NUM_AA_SUBSAMPLES_2;
1054 break;
1055 case 4:
1056 aa->aa_config = R300_GB_AA_CONFIG_AA_ENABLE |
1057 R300_GB_AA_CONFIG_NUM_AA_SUBSAMPLES_4;
1058 break;
1059 case 6:
1060 aa->aa_config = R300_GB_AA_CONFIG_AA_ENABLE |
1061 R300_GB_AA_CONFIG_NUM_AA_SUBSAMPLES_6;
1062 break;
1063 }
1064 } else {
1065 aa->aa_config = 0;
1066 }
1067
1068 if (DBG_ON(r300, DBG_FB)) {
1069 fprintf(stderr, "r300: set_framebuffer_state:\n");
1070 for (i = 0; i < state->nr_cbufs; i++) {
1071 r300_print_fb_surf_info(state->cbufs[i], i, "CB");
1072 }
1073 if (state->zsbuf) {
1074 r300_print_fb_surf_info(state->zsbuf, 0, "ZB");
1075 }
1076 }
1077 }
1078
1079 /* Create fragment shader state. */
1080 static void* r300_create_fs_state(struct pipe_context* pipe,
1081 const struct pipe_shader_state* shader)
1082 {
1083 struct r300_fragment_shader* fs = NULL;
1084
1085 fs = (struct r300_fragment_shader*)CALLOC_STRUCT(r300_fragment_shader);
1086
1087 /* Copy state directly into shader. */
1088 fs->state = *shader;
1089 fs->state.tokens = tgsi_dup_tokens(shader->tokens);
1090
1091 return (void*)fs;
1092 }
1093
1094 void r300_mark_fs_code_dirty(struct r300_context *r300)
1095 {
1096 struct r300_fragment_shader* fs = r300_fs(r300);
1097
1098 r300_mark_atom_dirty(r300, &r300->fs);
1099 r300_mark_atom_dirty(r300, &r300->fs_rc_constant_state);
1100 r300_mark_atom_dirty(r300, &r300->fs_constants);
1101 r300->fs.size = fs->shader->cb_code_size;
1102
1103 if (r300->screen->caps.is_r500) {
1104 r300->fs_rc_constant_state.size = fs->shader->rc_state_count * 7;
1105 r300->fs_constants.size = fs->shader->externals_count * 4 + 3;
1106 } else {
1107 r300->fs_rc_constant_state.size = fs->shader->rc_state_count * 5;
1108 r300->fs_constants.size = fs->shader->externals_count * 4 + 1;
1109 }
1110
1111 ((struct r300_constant_buffer*)r300->fs_constants.state)->remap_table =
1112 fs->shader->code.constants_remap_table;
1113 }
1114
1115 /* Bind fragment shader state. */
1116 static void r300_bind_fs_state(struct pipe_context* pipe, void* shader)
1117 {
1118 struct r300_context* r300 = r300_context(pipe);
1119 struct r300_fragment_shader* fs = (struct r300_fragment_shader*)shader;
1120
1121 if (fs == NULL) {
1122 r300->fs.state = NULL;
1123 return;
1124 }
1125
1126 r300->fs.state = fs;
1127 r300->fs_status = FRAGMENT_SHADER_DIRTY;
1128
1129 r300_mark_atom_dirty(r300, &r300->rs_block_state); /* Will be updated before the emission. */
1130 }
1131
1132 /* Delete fragment shader state. */
1133 static void r300_delete_fs_state(struct pipe_context* pipe, void* shader)
1134 {
1135 struct r300_fragment_shader* fs = (struct r300_fragment_shader*)shader;
1136 struct r300_fragment_shader_code *tmp, *ptr = fs->first;
1137
1138 while (ptr) {
1139 tmp = ptr;
1140 ptr = ptr->next;
1141 rc_constants_destroy(&tmp->code.constants);
1142 FREE(tmp->cb_code);
1143 FREE(tmp);
1144 }
1145 FREE((void*)fs->state.tokens);
1146 FREE(shader);
1147 }
1148
1149 static void r300_set_polygon_stipple(struct pipe_context* pipe,
1150 const struct pipe_poly_stipple* state)
1151 {
1152 /* XXX no idea how to set this up, but not terribly important */
1153 }
1154
1155 /* Create a new rasterizer state based on the CSO rasterizer state.
1156 *
1157 * This is a very large chunk of state, and covers most of the graphics
1158 * backend (GB), geometry assembly (GA), and setup unit (SU) blocks.
1159 *
1160 * In a not entirely unironic sidenote, this state has nearly nothing to do
1161 * with the actual block on the Radeon called the rasterizer (RS). */
1162 static void* r300_create_rs_state(struct pipe_context* pipe,
1163 const struct pipe_rasterizer_state* state)
1164 {
1165 struct r300_rs_state* rs = CALLOC_STRUCT(r300_rs_state);
1166 uint32_t vap_control_status; /* R300_VAP_CNTL_STATUS: 0x2140 */
1167 uint32_t vap_clip_cntl; /* R300_VAP_CLIP_CNTL: 0x221C */
1168 uint32_t point_size; /* R300_GA_POINT_SIZE: 0x421c */
1169 uint32_t point_minmax; /* R300_GA_POINT_MINMAX: 0x4230 */
1170 uint32_t line_control; /* R300_GA_LINE_CNTL: 0x4234 */
1171 uint32_t polygon_offset_enable; /* R300_SU_POLY_OFFSET_ENABLE: 0x42b4 */
1172 uint32_t cull_mode; /* R300_SU_CULL_MODE: 0x42b8 */
1173 uint32_t line_stipple_config; /* R300_GA_LINE_STIPPLE_CONFIG: 0x4328 */
1174 uint32_t line_stipple_value; /* R300_GA_LINE_STIPPLE_VALUE: 0x4260 */
1175 uint32_t polygon_mode; /* R300_GA_POLY_MODE: 0x4288 */
1176 uint32_t clip_rule; /* R300_SC_CLIP_RULE: 0x43D0 */
1177 uint32_t round_mode; /* R300_GA_ROUND_MODE: 0x428c */
1178
1179 /* Point sprites texture coordinates, 0: lower left, 1: upper right */
1180 float point_texcoord_left = 0; /* R300_GA_POINT_S0: 0x4200 */
1181 float point_texcoord_bottom = 0;/* R300_GA_POINT_T0: 0x4204 */
1182 float point_texcoord_right = 1; /* R300_GA_POINT_S1: 0x4208 */
1183 float point_texcoord_top = 0; /* R300_GA_POINT_T1: 0x420c */
1184 boolean vclamp = !r300_context(pipe)->screen->caps.is_r500;
1185 CB_LOCALS;
1186
1187 /* Copy rasterizer state. */
1188 rs->rs = *state;
1189 rs->rs_draw = *state;
1190
1191 rs->rs.sprite_coord_enable = state->point_quad_rasterization *
1192 state->sprite_coord_enable;
1193
1194 /* Override some states for Draw. */
1195 rs->rs_draw.sprite_coord_enable = 0; /* We can do this in HW. */
1196 rs->rs_draw.offset_point = 0;
1197 rs->rs_draw.offset_line = 0;
1198 rs->rs_draw.offset_tri = 0;
1199 rs->rs_draw.offset_clamp = 0;
1200
1201 #ifdef PIPE_ARCH_LITTLE_ENDIAN
1202 vap_control_status = R300_VC_NO_SWAP;
1203 #else
1204 vap_control_status = R300_VC_32BIT_SWAP;
1205 #endif
1206
1207 /* If no TCL engine is present, turn off the HW TCL. */
1208 if (!r300_screen(pipe->screen)->caps.has_tcl) {
1209 vap_control_status |= R300_VAP_TCL_BYPASS;
1210 }
1211
1212 /* Point size width and height. */
1213 point_size =
1214 pack_float_16_6x(state->point_size) |
1215 (pack_float_16_6x(state->point_size) << R300_POINTSIZE_X_SHIFT);
1216
1217 /* Point size clamping. */
1218 if (state->point_size_per_vertex) {
1219 /* Per-vertex point size.
1220 * Clamp to [0, max FB size] */
1221 float min_psiz = util_get_min_point_size(state);
1222 float max_psiz = pipe->screen->get_paramf(pipe->screen,
1223 PIPE_CAPF_MAX_POINT_WIDTH);
1224 point_minmax =
1225 (pack_float_16_6x(min_psiz) << R300_GA_POINT_MINMAX_MIN_SHIFT) |
1226 (pack_float_16_6x(max_psiz) << R300_GA_POINT_MINMAX_MAX_SHIFT);
1227 } else {
1228 /* We cannot disable the point-size vertex output,
1229 * so clamp it. */
1230 float psiz = state->point_size;
1231 point_minmax =
1232 (pack_float_16_6x(psiz) << R300_GA_POINT_MINMAX_MIN_SHIFT) |
1233 (pack_float_16_6x(psiz) << R300_GA_POINT_MINMAX_MAX_SHIFT);
1234 }
1235
1236 /* Line control. */
1237 line_control = pack_float_16_6x(state->line_width) |
1238 R300_GA_LINE_CNTL_END_TYPE_COMP;
1239
1240 /* Enable polygon mode */
1241 polygon_mode = 0;
1242 if (state->fill_front != PIPE_POLYGON_MODE_FILL ||
1243 state->fill_back != PIPE_POLYGON_MODE_FILL) {
1244 polygon_mode = R300_GA_POLY_MODE_DUAL;
1245 }
1246
1247 /* Front face */
1248 if (state->front_ccw)
1249 cull_mode = R300_FRONT_FACE_CCW;
1250 else
1251 cull_mode = R300_FRONT_FACE_CW;
1252
1253 /* Polygon offset */
1254 polygon_offset_enable = 0;
1255 if (util_get_offset(state, state->fill_front)) {
1256 polygon_offset_enable |= R300_FRONT_ENABLE;
1257 }
1258 if (util_get_offset(state, state->fill_back)) {
1259 polygon_offset_enable |= R300_BACK_ENABLE;
1260 }
1261
1262 rs->polygon_offset_enable = polygon_offset_enable != 0;
1263
1264 /* Polygon mode */
1265 if (polygon_mode) {
1266 polygon_mode |=
1267 r300_translate_polygon_mode_front(state->fill_front);
1268 polygon_mode |=
1269 r300_translate_polygon_mode_back(state->fill_back);
1270 }
1271
1272 if (state->cull_face & PIPE_FACE_FRONT) {
1273 cull_mode |= R300_CULL_FRONT;
1274 }
1275 if (state->cull_face & PIPE_FACE_BACK) {
1276 cull_mode |= R300_CULL_BACK;
1277 }
1278
1279 if (state->line_stipple_enable) {
1280 line_stipple_config =
1281 R300_GA_LINE_STIPPLE_CONFIG_LINE_RESET_LINE |
1282 (fui((float)state->line_stipple_factor) &
1283 R300_GA_LINE_STIPPLE_CONFIG_STIPPLE_SCALE_MASK);
1284 /* XXX this might need to be scaled up */
1285 line_stipple_value = state->line_stipple_pattern;
1286 } else {
1287 line_stipple_config = 0;
1288 line_stipple_value = 0;
1289 }
1290
1291 if (state->flatshade) {
1292 rs->color_control = R300_SHADE_MODEL_FLAT;
1293 } else {
1294 rs->color_control = R300_SHADE_MODEL_SMOOTH;
1295 }
1296
1297 clip_rule = state->scissor ? 0xAAAA : 0xFFFF;
1298
1299 /* Point sprites coord mode */
1300 if (rs->rs.sprite_coord_enable) {
1301 switch (state->sprite_coord_mode) {
1302 case PIPE_SPRITE_COORD_UPPER_LEFT:
1303 point_texcoord_top = 0.0f;
1304 point_texcoord_bottom = 1.0f;
1305 break;
1306 case PIPE_SPRITE_COORD_LOWER_LEFT:
1307 point_texcoord_top = 1.0f;
1308 point_texcoord_bottom = 0.0f;
1309 break;
1310 }
1311 }
1312
1313 if (r300_screen(pipe->screen)->caps.has_tcl) {
1314 vap_clip_cntl = (state->clip_plane_enable & 63) |
1315 R300_PS_UCP_MODE_CLIP_AS_TRIFAN |
1316 (state->depth_clip ? 0 : R300_CLIP_DISABLE);
1317 } else {
1318 vap_clip_cntl = R300_CLIP_DISABLE;
1319 }
1320
1321 /* Vertex color clamping. FP20 means no clamping. */
1322 round_mode =
1323 R300_GA_ROUND_MODE_GEOMETRY_ROUND_NEAREST |
1324 (!vclamp ? (R300_GA_ROUND_MODE_RGB_CLAMP_FP20 |
1325 R300_GA_ROUND_MODE_ALPHA_CLAMP_FP20) : 0);
1326
1327 /* Build the main command buffer. */
1328 BEGIN_CB(rs->cb_main, RS_STATE_MAIN_SIZE);
1329 OUT_CB_REG(R300_VAP_CNTL_STATUS, vap_control_status);
1330 OUT_CB_REG(R300_VAP_CLIP_CNTL, vap_clip_cntl);
1331 OUT_CB_REG(R300_GA_POINT_SIZE, point_size);
1332 OUT_CB_REG_SEQ(R300_GA_POINT_MINMAX, 2);
1333 OUT_CB(point_minmax);
1334 OUT_CB(line_control);
1335 OUT_CB_REG_SEQ(R300_SU_POLY_OFFSET_ENABLE, 2);
1336 OUT_CB(polygon_offset_enable);
1337 rs->cull_mode_index = 11;
1338 OUT_CB(cull_mode);
1339 OUT_CB_REG(R300_GA_LINE_STIPPLE_CONFIG, line_stipple_config);
1340 OUT_CB_REG(R300_GA_LINE_STIPPLE_VALUE, line_stipple_value);
1341 OUT_CB_REG(R300_GA_POLY_MODE, polygon_mode);
1342 OUT_CB_REG(R300_GA_ROUND_MODE, round_mode);
1343 OUT_CB_REG(R300_SC_CLIP_RULE, clip_rule);
1344 OUT_CB_REG_SEQ(R300_GA_POINT_S0, 4);
1345 OUT_CB_32F(point_texcoord_left);
1346 OUT_CB_32F(point_texcoord_bottom);
1347 OUT_CB_32F(point_texcoord_right);
1348 OUT_CB_32F(point_texcoord_top);
1349 END_CB;
1350
1351 /* Build the two command buffers for polygon offset setup. */
1352 if (polygon_offset_enable) {
1353 float scale = state->offset_scale * 12;
1354 float offset = state->offset_units * 4;
1355
1356 BEGIN_CB(rs->cb_poly_offset_zb16, 5);
1357 OUT_CB_REG_SEQ(R300_SU_POLY_OFFSET_FRONT_SCALE, 4);
1358 OUT_CB_32F(scale);
1359 OUT_CB_32F(offset);
1360 OUT_CB_32F(scale);
1361 OUT_CB_32F(offset);
1362 END_CB;
1363
1364 offset = state->offset_units * 2;
1365
1366 BEGIN_CB(rs->cb_poly_offset_zb24, 5);
1367 OUT_CB_REG_SEQ(R300_SU_POLY_OFFSET_FRONT_SCALE, 4);
1368 OUT_CB_32F(scale);
1369 OUT_CB_32F(offset);
1370 OUT_CB_32F(scale);
1371 OUT_CB_32F(offset);
1372 END_CB;
1373 }
1374
1375 return (void*)rs;
1376 }
1377
1378 /* Bind rasterizer state. */
1379 static void r300_bind_rs_state(struct pipe_context* pipe, void* state)
1380 {
1381 struct r300_context* r300 = r300_context(pipe);
1382 struct r300_rs_state* rs = (struct r300_rs_state*)state;
1383 int last_sprite_coord_enable = r300->sprite_coord_enable;
1384 boolean last_two_sided_color = r300->two_sided_color;
1385 boolean last_msaa_enable = r300->msaa_enable;
1386 boolean last_flatshade = r300->flatshade;
1387
1388 if (r300->draw && rs) {
1389 draw_set_rasterizer_state(r300->draw, &rs->rs_draw, state);
1390 }
1391
1392 if (rs) {
1393 r300->polygon_offset_enabled = rs->polygon_offset_enable;
1394 r300->sprite_coord_enable = rs->rs.sprite_coord_enable;
1395 r300->two_sided_color = rs->rs.light_twoside;
1396 r300->msaa_enable = rs->rs.multisample;
1397 r300->flatshade = rs->rs.flatshade;
1398 } else {
1399 r300->polygon_offset_enabled = FALSE;
1400 r300->sprite_coord_enable = 0;
1401 r300->two_sided_color = FALSE;
1402 r300->msaa_enable = FALSE;
1403 r300->flatshade = FALSE;
1404 }
1405
1406 UPDATE_STATE(state, r300->rs_state);
1407 r300->rs_state.size = RS_STATE_MAIN_SIZE + (r300->polygon_offset_enabled ? 5 : 0);
1408
1409 if (last_sprite_coord_enable != r300->sprite_coord_enable ||
1410 last_two_sided_color != r300->two_sided_color ||
1411 last_flatshade != r300->flatshade) {
1412 r300_mark_atom_dirty(r300, &r300->rs_block_state);
1413 }
1414
1415 if (last_msaa_enable != r300->msaa_enable) {
1416 if (r300->alpha_to_coverage) {
1417 r300_mark_atom_dirty(r300, &r300->dsa_state);
1418 }
1419
1420 if (r300->alpha_to_one &&
1421 r300->fs_status == FRAGMENT_SHADER_VALID) {
1422 r300->fs_status = FRAGMENT_SHADER_MAYBE_DIRTY;
1423 }
1424 }
1425 }
1426
1427 /* Free rasterizer state. */
1428 static void r300_delete_rs_state(struct pipe_context* pipe, void* state)
1429 {
1430 FREE(state);
1431 }
1432
1433 static void*
1434 r300_create_sampler_state(struct pipe_context* pipe,
1435 const struct pipe_sampler_state* state)
1436 {
1437 struct r300_context* r300 = r300_context(pipe);
1438 struct r300_sampler_state* sampler = CALLOC_STRUCT(r300_sampler_state);
1439 boolean is_r500 = r300->screen->caps.is_r500;
1440 int lod_bias;
1441
1442 sampler->state = *state;
1443
1444 /* r300 doesn't handle CLAMP and MIRROR_CLAMP correctly when either MAG
1445 * or MIN filter is NEAREST. Since texwrap produces same results
1446 * for CLAMP and CLAMP_TO_EDGE, we use them instead. */
1447 if (sampler->state.min_img_filter == PIPE_TEX_FILTER_NEAREST ||
1448 sampler->state.mag_img_filter == PIPE_TEX_FILTER_NEAREST) {
1449 /* Wrap S. */
1450 if (sampler->state.wrap_s == PIPE_TEX_WRAP_CLAMP)
1451 sampler->state.wrap_s = PIPE_TEX_WRAP_CLAMP_TO_EDGE;
1452 else if (sampler->state.wrap_s == PIPE_TEX_WRAP_MIRROR_CLAMP)
1453 sampler->state.wrap_s = PIPE_TEX_WRAP_MIRROR_CLAMP_TO_EDGE;
1454
1455 /* Wrap T. */
1456 if (sampler->state.wrap_t == PIPE_TEX_WRAP_CLAMP)
1457 sampler->state.wrap_t = PIPE_TEX_WRAP_CLAMP_TO_EDGE;
1458 else if (sampler->state.wrap_t == PIPE_TEX_WRAP_MIRROR_CLAMP)
1459 sampler->state.wrap_t = PIPE_TEX_WRAP_MIRROR_CLAMP_TO_EDGE;
1460
1461 /* Wrap R. */
1462 if (sampler->state.wrap_r == PIPE_TEX_WRAP_CLAMP)
1463 sampler->state.wrap_r = PIPE_TEX_WRAP_CLAMP_TO_EDGE;
1464 else if (sampler->state.wrap_r == PIPE_TEX_WRAP_MIRROR_CLAMP)
1465 sampler->state.wrap_r = PIPE_TEX_WRAP_MIRROR_CLAMP_TO_EDGE;
1466 }
1467
1468 sampler->filter0 |=
1469 (r300_translate_wrap(sampler->state.wrap_s) << R300_TX_WRAP_S_SHIFT) |
1470 (r300_translate_wrap(sampler->state.wrap_t) << R300_TX_WRAP_T_SHIFT) |
1471 (r300_translate_wrap(sampler->state.wrap_r) << R300_TX_WRAP_R_SHIFT);
1472
1473 sampler->filter0 |= r300_translate_tex_filters(state->min_img_filter,
1474 state->mag_img_filter,
1475 state->min_mip_filter,
1476 state->max_anisotropy > 1);
1477
1478 sampler->filter0 |= r300_anisotropy(state->max_anisotropy);
1479
1480 /* Unfortunately, r300-r500 don't support floating-point mipmap lods. */
1481 /* We must pass these to the merge function to clamp them properly. */
1482 sampler->min_lod = (unsigned)MAX2(state->min_lod, 0);
1483 sampler->max_lod = (unsigned)MAX2(ceilf(state->max_lod), 0);
1484
1485 lod_bias = CLAMP((int)(state->lod_bias * 32 + 1), -(1 << 9), (1 << 9) - 1);
1486
1487 sampler->filter1 |= (lod_bias << R300_LOD_BIAS_SHIFT) & R300_LOD_BIAS_MASK;
1488
1489 /* This is very high quality anisotropic filtering for R5xx.
1490 * It's good for benchmarking the performance of texturing but
1491 * in practice we don't want to slow down the driver because it's
1492 * a pretty good performance killer. Feel free to play with it. */
1493 if (DBG_ON(r300, DBG_ANISOHQ) && is_r500) {
1494 sampler->filter1 |= r500_anisotropy(state->max_anisotropy);
1495 }
1496
1497 /* R500-specific fixups and optimizations */
1498 if (r300->screen->caps.is_r500) {
1499 sampler->filter1 |= R500_BORDER_FIX;
1500 }
1501
1502 return (void*)sampler;
1503 }
1504
1505 static void r300_bind_sampler_states(struct pipe_context* pipe,
1506 unsigned count,
1507 void** states)
1508 {
1509 struct r300_context* r300 = r300_context(pipe);
1510 struct r300_textures_state* state =
1511 (struct r300_textures_state*)r300->textures_state.state;
1512 unsigned tex_units = r300->screen->caps.num_tex_units;
1513
1514 if (count > tex_units) {
1515 return;
1516 }
1517
1518 memcpy(state->sampler_states, states, sizeof(void*) * count);
1519 state->sampler_state_count = count;
1520
1521 r300_mark_atom_dirty(r300, &r300->textures_state);
1522 }
1523
1524 static void r300_lacks_vertex_textures(struct pipe_context* pipe,
1525 unsigned count,
1526 void** states)
1527 {
1528 }
1529
1530 static void r300_delete_sampler_state(struct pipe_context* pipe, void* state)
1531 {
1532 FREE(state);
1533 }
1534
1535 static uint32_t r300_assign_texture_cache_region(unsigned index, unsigned num)
1536 {
1537 /* This looks like a hack, but I believe it's suppose to work like
1538 * that. To illustrate how this works, let's assume you have 5 textures.
1539 * From docs, 5 and the successive numbers are:
1540 *
1541 * FOURTH_1 = 5
1542 * FOURTH_2 = 6
1543 * FOURTH_3 = 7
1544 * EIGHTH_0 = 8
1545 * EIGHTH_1 = 9
1546 *
1547 * First 3 textures will get 3/4 of size of the cache, divived evenly
1548 * between them. The last 1/4 of the cache must be divided between
1549 * the last 2 textures, each will therefore get 1/8 of the cache.
1550 * Why not just to use "5 + texture_index" ?
1551 *
1552 * This simple trick works for all "num" <= 16.
1553 */
1554 if (num <= 1)
1555 return R300_TX_CACHE(R300_TX_CACHE_WHOLE);
1556 else
1557 return R300_TX_CACHE(num + index);
1558 }
1559
1560 static void r300_set_fragment_sampler_views(struct pipe_context* pipe,
1561 unsigned count,
1562 struct pipe_sampler_view** views)
1563 {
1564 struct r300_context* r300 = r300_context(pipe);
1565 struct r300_textures_state* state =
1566 (struct r300_textures_state*)r300->textures_state.state;
1567 struct r300_resource *texture;
1568 unsigned i, real_num_views = 0, view_index = 0;
1569 unsigned tex_units = r300->screen->caps.num_tex_units;
1570 boolean dirty_tex = FALSE;
1571
1572 if (count > tex_units) {
1573 return;
1574 }
1575
1576 /* Calculate the real number of views. */
1577 for (i = 0; i < count; i++) {
1578 if (views[i])
1579 real_num_views++;
1580 }
1581
1582 for (i = 0; i < count; i++) {
1583 pipe_sampler_view_reference(
1584 (struct pipe_sampler_view**)&state->sampler_views[i],
1585 views[i]);
1586
1587 if (!views[i]) {
1588 continue;
1589 }
1590
1591 /* A new sampler view (= texture)... */
1592 dirty_tex = TRUE;
1593
1594 /* Set the texrect factor in the fragment shader.
1595 * Needed for RECT and NPOT fallback. */
1596 texture = r300_resource(views[i]->texture);
1597 if (texture->tex.is_npot) {
1598 r300_mark_atom_dirty(r300, &r300->fs_rc_constant_state);
1599 }
1600
1601 state->sampler_views[i]->texcache_region =
1602 r300_assign_texture_cache_region(view_index, real_num_views);
1603 view_index++;
1604 }
1605
1606 for (i = count; i < tex_units; i++) {
1607 if (state->sampler_views[i]) {
1608 pipe_sampler_view_reference(
1609 (struct pipe_sampler_view**)&state->sampler_views[i],
1610 NULL);
1611 }
1612 }
1613
1614 state->sampler_view_count = count;
1615
1616 r300_mark_atom_dirty(r300, &r300->textures_state);
1617
1618 if (dirty_tex) {
1619 r300_mark_atom_dirty(r300, &r300->texture_cache_inval);
1620 }
1621 }
1622
1623 struct pipe_sampler_view *
1624 r300_create_sampler_view_custom(struct pipe_context *pipe,
1625 struct pipe_resource *texture,
1626 const struct pipe_sampler_view *templ,
1627 unsigned width0_override,
1628 unsigned height0_override)
1629 {
1630 struct r300_sampler_view *view = CALLOC_STRUCT(r300_sampler_view);
1631 struct r300_resource *tex = r300_resource(texture);
1632 boolean is_r500 = r300_screen(pipe->screen)->caps.is_r500;
1633 boolean dxtc_swizzle = r300_screen(pipe->screen)->caps.dxtc_swizzle;
1634
1635 if (view) {
1636 unsigned hwformat;
1637
1638 view->base = *templ;
1639 view->base.reference.count = 1;
1640 view->base.context = pipe;
1641 view->base.texture = NULL;
1642 pipe_resource_reference(&view->base.texture, texture);
1643
1644 view->width0_override = width0_override;
1645 view->height0_override = height0_override;
1646 view->swizzle[0] = templ->swizzle_r;
1647 view->swizzle[1] = templ->swizzle_g;
1648 view->swizzle[2] = templ->swizzle_b;
1649 view->swizzle[3] = templ->swizzle_a;
1650
1651 hwformat = r300_translate_texformat(templ->format,
1652 view->swizzle,
1653 is_r500,
1654 dxtc_swizzle);
1655
1656 if (hwformat == ~0) {
1657 fprintf(stderr, "r300: Ooops. Got unsupported format %s in %s.\n",
1658 util_format_short_name(templ->format), __func__);
1659 }
1660 assert(hwformat != ~0);
1661
1662 r300_texture_setup_format_state(r300_screen(pipe->screen), tex,
1663 templ->format, 0,
1664 width0_override, height0_override,
1665 &view->format);
1666 view->format.format1 |= hwformat;
1667 if (is_r500) {
1668 view->format.format2 |= r500_tx_format_msb_bit(templ->format);
1669 }
1670 }
1671
1672 return (struct pipe_sampler_view*)view;
1673 }
1674
1675 static struct pipe_sampler_view *
1676 r300_create_sampler_view(struct pipe_context *pipe,
1677 struct pipe_resource *texture,
1678 const struct pipe_sampler_view *templ)
1679 {
1680 return r300_create_sampler_view_custom(pipe, texture, templ,
1681 r300_resource(texture)->tex.width0,
1682 r300_resource(texture)->tex.height0);
1683 }
1684
1685
1686 static void
1687 r300_sampler_view_destroy(struct pipe_context *pipe,
1688 struct pipe_sampler_view *view)
1689 {
1690 pipe_resource_reference(&view->texture, NULL);
1691 FREE(view);
1692 }
1693
1694 static void r300_set_sample_mask(struct pipe_context *pipe,
1695 unsigned mask)
1696 {
1697 struct r300_context* r300 = r300_context(pipe);
1698
1699 *((unsigned*)r300->sample_mask.state) = mask;
1700
1701 r300_mark_atom_dirty(r300, &r300->sample_mask);
1702 }
1703
1704 static void r300_set_scissor_state(struct pipe_context* pipe,
1705 const struct pipe_scissor_state* state)
1706 {
1707 struct r300_context* r300 = r300_context(pipe);
1708
1709 memcpy(r300->scissor_state.state, state,
1710 sizeof(struct pipe_scissor_state));
1711
1712 r300_mark_atom_dirty(r300, &r300->scissor_state);
1713 }
1714
1715 static void r300_set_viewport_state(struct pipe_context* pipe,
1716 const struct pipe_viewport_state* state)
1717 {
1718 struct r300_context* r300 = r300_context(pipe);
1719 struct r300_viewport_state* viewport =
1720 (struct r300_viewport_state*)r300->viewport_state.state;
1721
1722 r300->viewport = *state;
1723
1724 if (r300->draw) {
1725 draw_set_viewport_state(r300->draw, state);
1726 viewport->vte_control = R300_VTX_XY_FMT | R300_VTX_Z_FMT;
1727 return;
1728 }
1729
1730 /* Do the transform in HW. */
1731 viewport->vte_control = R300_VTX_W0_FMT;
1732
1733 if (state->scale[0] != 1.0f) {
1734 viewport->xscale = state->scale[0];
1735 viewport->vte_control |= R300_VPORT_X_SCALE_ENA;
1736 }
1737 if (state->scale[1] != 1.0f) {
1738 viewport->yscale = state->scale[1];
1739 viewport->vte_control |= R300_VPORT_Y_SCALE_ENA;
1740 }
1741 if (state->scale[2] != 1.0f) {
1742 viewport->zscale = state->scale[2];
1743 viewport->vte_control |= R300_VPORT_Z_SCALE_ENA;
1744 }
1745 if (state->translate[0] != 0.0f) {
1746 viewport->xoffset = state->translate[0];
1747 viewport->vte_control |= R300_VPORT_X_OFFSET_ENA;
1748 }
1749 if (state->translate[1] != 0.0f) {
1750 viewport->yoffset = state->translate[1];
1751 viewport->vte_control |= R300_VPORT_Y_OFFSET_ENA;
1752 }
1753 if (state->translate[2] != 0.0f) {
1754 viewport->zoffset = state->translate[2];
1755 viewport->vte_control |= R300_VPORT_Z_OFFSET_ENA;
1756 }
1757
1758 r300_mark_atom_dirty(r300, &r300->viewport_state);
1759 if (r300->fs.state && r300_fs(r300)->shader &&
1760 r300_fs(r300)->shader->inputs.wpos != ATTR_UNUSED) {
1761 r300_mark_atom_dirty(r300, &r300->fs_rc_constant_state);
1762 }
1763 }
1764
1765 static void r300_set_vertex_buffers_hwtcl(struct pipe_context* pipe,
1766 unsigned start_slot, unsigned count,
1767 const struct pipe_vertex_buffer* buffers)
1768 {
1769 struct r300_context* r300 = r300_context(pipe);
1770
1771 util_set_vertex_buffers_count(r300->vertex_buffer,
1772 &r300->nr_vertex_buffers,
1773 buffers, start_slot, count);
1774
1775 /* There must be at least one vertex buffer set, otherwise it locks up. */
1776 if (!r300->nr_vertex_buffers) {
1777 util_set_vertex_buffers_count(r300->vertex_buffer,
1778 &r300->nr_vertex_buffers,
1779 &r300->dummy_vb, 0, 1);
1780 }
1781
1782 r300->vertex_arrays_dirty = TRUE;
1783 }
1784
1785 static void r300_set_vertex_buffers_swtcl(struct pipe_context* pipe,
1786 unsigned start_slot, unsigned count,
1787 const struct pipe_vertex_buffer* buffers)
1788 {
1789 struct r300_context* r300 = r300_context(pipe);
1790 unsigned i;
1791
1792 util_set_vertex_buffers_count(r300->vertex_buffer,
1793 &r300->nr_vertex_buffers,
1794 buffers, start_slot, count);
1795 draw_set_vertex_buffers(r300->draw, start_slot, count, buffers);
1796
1797 if (!buffers)
1798 return;
1799
1800 for (i = 0; i < count; i++) {
1801 if (buffers[i].user_buffer) {
1802 draw_set_mapped_vertex_buffer(r300->draw, start_slot + i,
1803 buffers[i].user_buffer);
1804 } else if (buffers[i].buffer) {
1805 draw_set_mapped_vertex_buffer(r300->draw, start_slot + i,
1806 r300_resource(buffers[i].buffer)->malloced_buffer);
1807 }
1808 }
1809 }
1810
1811 static void r300_set_index_buffer_hwtcl(struct pipe_context* pipe,
1812 const struct pipe_index_buffer *ib)
1813 {
1814 struct r300_context* r300 = r300_context(pipe);
1815
1816 if (ib) {
1817 pipe_resource_reference(&r300->index_buffer.buffer, ib->buffer);
1818 memcpy(&r300->index_buffer, ib, sizeof(*ib));
1819 } else {
1820 pipe_resource_reference(&r300->index_buffer.buffer, NULL);
1821 }
1822 }
1823
1824 static void r300_set_index_buffer_swtcl(struct pipe_context* pipe,
1825 const struct pipe_index_buffer *ib)
1826 {
1827 struct r300_context* r300 = r300_context(pipe);
1828
1829 if (ib) {
1830 const void *buf = NULL;
1831 if (ib->user_buffer) {
1832 buf = ib->user_buffer;
1833 } else if (ib->buffer) {
1834 buf = r300_resource(ib->buffer)->malloced_buffer;
1835 }
1836 draw_set_indexes(r300->draw,
1837 (const ubyte *) buf + ib->offset,
1838 ib->index_size);
1839 }
1840 }
1841
1842 /* Initialize the PSC tables. */
1843 static void r300_vertex_psc(struct r300_vertex_element_state *velems)
1844 {
1845 struct r300_vertex_stream_state *vstream = &velems->vertex_stream;
1846 uint16_t type, swizzle;
1847 enum pipe_format format;
1848 unsigned i;
1849
1850 /* Vertex shaders have no semantics on their inputs,
1851 * so PSC should just route stuff based on the vertex elements,
1852 * and not on attrib information. */
1853 for (i = 0; i < velems->count; i++) {
1854 format = velems->velem[i].src_format;
1855
1856 type = r300_translate_vertex_data_type(format);
1857 if (type == R300_INVALID_FORMAT) {
1858 fprintf(stderr, "r300: Bad vertex format %s.\n",
1859 util_format_short_name(format));
1860 assert(0);
1861 abort();
1862 }
1863
1864 type |= i << R300_DST_VEC_LOC_SHIFT;
1865 swizzle = r300_translate_vertex_data_swizzle(format);
1866
1867 if (i & 1) {
1868 vstream->vap_prog_stream_cntl[i >> 1] |= type << 16;
1869 vstream->vap_prog_stream_cntl_ext[i >> 1] |= swizzle << 16;
1870 } else {
1871 vstream->vap_prog_stream_cntl[i >> 1] |= type;
1872 vstream->vap_prog_stream_cntl_ext[i >> 1] |= swizzle;
1873 }
1874 }
1875
1876 /* Set the last vector in the PSC. */
1877 if (i) {
1878 i -= 1;
1879 }
1880 vstream->vap_prog_stream_cntl[i >> 1] |=
1881 (R300_LAST_VEC << (i & 1 ? 16 : 0));
1882
1883 vstream->count = (i >> 1) + 1;
1884 }
1885
1886 static void* r300_create_vertex_elements_state(struct pipe_context* pipe,
1887 unsigned count,
1888 const struct pipe_vertex_element* attribs)
1889 {
1890 struct r300_vertex_element_state *velems;
1891 unsigned i;
1892 struct pipe_vertex_element dummy_attrib = {0};
1893
1894 /* R300 Programmable Stream Control (PSC) doesn't support 0 vertex elements. */
1895 if (!count) {
1896 dummy_attrib.src_format = PIPE_FORMAT_R8G8B8A8_UNORM;
1897 attribs = &dummy_attrib;
1898 count = 1;
1899 } else if (count > 16) {
1900 fprintf(stderr, "r300: More than 16 vertex elements are not supported,"
1901 " requested %i, using 16.\n", count);
1902 count = 16;
1903 }
1904
1905 velems = CALLOC_STRUCT(r300_vertex_element_state);
1906 if (!velems)
1907 return NULL;
1908
1909 velems->count = count;
1910 memcpy(velems->velem, attribs, sizeof(struct pipe_vertex_element) * count);
1911
1912 if (r300_screen(pipe->screen)->caps.has_tcl) {
1913 /* Setup PSC.
1914 * The unused components will be replaced by (..., 0, 1). */
1915 r300_vertex_psc(velems);
1916
1917 for (i = 0; i < count; i++) {
1918 velems->format_size[i] =
1919 align(util_format_get_blocksize(velems->velem[i].src_format), 4);
1920 velems->vertex_size_dwords += velems->format_size[i] / 4;
1921 }
1922 }
1923
1924 return velems;
1925 }
1926
1927 static void r300_bind_vertex_elements_state(struct pipe_context *pipe,
1928 void *state)
1929 {
1930 struct r300_context *r300 = r300_context(pipe);
1931 struct r300_vertex_element_state *velems = state;
1932
1933 if (velems == NULL) {
1934 return;
1935 }
1936
1937 r300->velems = velems;
1938
1939 if (r300->draw) {
1940 draw_set_vertex_elements(r300->draw, velems->count, velems->velem);
1941 return;
1942 }
1943
1944 UPDATE_STATE(&velems->vertex_stream, r300->vertex_stream_state);
1945 r300->vertex_stream_state.size = (1 + velems->vertex_stream.count) * 2;
1946 r300->vertex_arrays_dirty = TRUE;
1947 }
1948
1949 static void r300_delete_vertex_elements_state(struct pipe_context *pipe, void *state)
1950 {
1951 FREE(state);
1952 }
1953
1954 static void* r300_create_vs_state(struct pipe_context* pipe,
1955 const struct pipe_shader_state* shader)
1956 {
1957 struct r300_context* r300 = r300_context(pipe);
1958 struct r300_vertex_shader* vs = CALLOC_STRUCT(r300_vertex_shader);
1959
1960 /* Copy state directly into shader. */
1961 vs->state = *shader;
1962 vs->state.tokens = tgsi_dup_tokens(shader->tokens);
1963
1964 if (r300->screen->caps.has_tcl) {
1965 r300_init_vs_outputs(r300, vs);
1966 r300_translate_vertex_shader(r300, vs);
1967 } else {
1968 r300_draw_init_vertex_shader(r300, vs);
1969 }
1970
1971 return vs;
1972 }
1973
1974 static void r300_bind_vs_state(struct pipe_context* pipe, void* shader)
1975 {
1976 struct r300_context* r300 = r300_context(pipe);
1977 struct r300_vertex_shader* vs = (struct r300_vertex_shader*)shader;
1978
1979 if (vs == NULL) {
1980 r300->vs_state.state = NULL;
1981 return;
1982 }
1983 if (vs == r300->vs_state.state) {
1984 return;
1985 }
1986 r300->vs_state.state = vs;
1987
1988 /* The majority of the RS block bits is dependent on the vertex shader. */
1989 r300_mark_atom_dirty(r300, &r300->rs_block_state); /* Will be updated before the emission. */
1990
1991 if (r300->screen->caps.has_tcl) {
1992 unsigned fc_op_dwords = r300->screen->caps.is_r500 ? 3 : 2;
1993 r300_mark_atom_dirty(r300, &r300->vs_state);
1994 r300->vs_state.size = vs->code.length + 9 +
1995 (R300_VS_MAX_FC_OPS * fc_op_dwords + 4);
1996
1997 r300_mark_atom_dirty(r300, &r300->vs_constants);
1998 r300->vs_constants.size =
1999 2 +
2000 (vs->externals_count ? vs->externals_count * 4 + 3 : 0) +
2001 (vs->immediates_count ? vs->immediates_count * 4 + 3 : 0);
2002
2003 ((struct r300_constant_buffer*)r300->vs_constants.state)->remap_table =
2004 vs->code.constants_remap_table;
2005
2006 r300_mark_atom_dirty(r300, &r300->pvs_flush);
2007 } else {
2008 draw_bind_vertex_shader(r300->draw,
2009 (struct draw_vertex_shader*)vs->draw_vs);
2010 }
2011 }
2012
2013 static void r300_delete_vs_state(struct pipe_context* pipe, void* shader)
2014 {
2015 struct r300_context* r300 = r300_context(pipe);
2016 struct r300_vertex_shader* vs = (struct r300_vertex_shader*)shader;
2017
2018 if (r300->screen->caps.has_tcl) {
2019 rc_constants_destroy(&vs->code.constants);
2020 FREE(vs->code.constants_remap_table);
2021 } else {
2022 draw_delete_vertex_shader(r300->draw,
2023 (struct draw_vertex_shader*)vs->draw_vs);
2024 }
2025
2026 FREE((void*)vs->state.tokens);
2027 FREE(shader);
2028 }
2029
2030 static void r300_set_constant_buffer(struct pipe_context *pipe,
2031 uint shader, uint index,
2032 struct pipe_constant_buffer *cb)
2033 {
2034 struct r300_context* r300 = r300_context(pipe);
2035 struct r300_constant_buffer *cbuf;
2036 uint32_t *mapped;
2037
2038 if (!cb)
2039 return;
2040
2041 switch (shader) {
2042 case PIPE_SHADER_VERTEX:
2043 cbuf = (struct r300_constant_buffer*)r300->vs_constants.state;
2044 break;
2045 case PIPE_SHADER_FRAGMENT:
2046 cbuf = (struct r300_constant_buffer*)r300->fs_constants.state;
2047 break;
2048 default:
2049 return;
2050 }
2051
2052
2053 if (cb->user_buffer)
2054 mapped = (uint32_t*)cb->user_buffer;
2055 else {
2056 struct r300_resource *rbuf = r300_resource(cb->buffer);
2057
2058 if (rbuf && rbuf->malloced_buffer)
2059 mapped = (uint32_t*)rbuf->malloced_buffer;
2060 else
2061 return;
2062 }
2063
2064 if (shader == PIPE_SHADER_FRAGMENT ||
2065 (shader == PIPE_SHADER_VERTEX && r300->screen->caps.has_tcl)) {
2066 cbuf->ptr = mapped;
2067 }
2068
2069 if (shader == PIPE_SHADER_VERTEX) {
2070 if (r300->screen->caps.has_tcl) {
2071 struct r300_vertex_shader *vs =
2072 (struct r300_vertex_shader*)r300->vs_state.state;
2073
2074 if (!vs) {
2075 cbuf->buffer_base = 0;
2076 return;
2077 }
2078
2079 cbuf->buffer_base = r300->vs_const_base;
2080 r300->vs_const_base += vs->code.constants.Count;
2081 if (r300->vs_const_base > R500_MAX_PVS_CONST_VECS) {
2082 r300->vs_const_base = vs->code.constants.Count;
2083 cbuf->buffer_base = 0;
2084 r300_mark_atom_dirty(r300, &r300->pvs_flush);
2085 }
2086 r300_mark_atom_dirty(r300, &r300->vs_constants);
2087 } else if (r300->draw) {
2088 draw_set_mapped_constant_buffer(r300->draw, PIPE_SHADER_VERTEX,
2089 0, mapped, cb->buffer_size);
2090 }
2091 } else if (shader == PIPE_SHADER_FRAGMENT) {
2092 r300_mark_atom_dirty(r300, &r300->fs_constants);
2093 }
2094 }
2095
2096 static void r300_texture_barrier(struct pipe_context *pipe)
2097 {
2098 struct r300_context *r300 = r300_context(pipe);
2099
2100 r300_mark_atom_dirty(r300, &r300->gpu_flush);
2101 r300_mark_atom_dirty(r300, &r300->texture_cache_inval);
2102 }
2103
2104 void r300_init_state_functions(struct r300_context* r300)
2105 {
2106 r300->context.create_blend_state = r300_create_blend_state;
2107 r300->context.bind_blend_state = r300_bind_blend_state;
2108 r300->context.delete_blend_state = r300_delete_blend_state;
2109
2110 r300->context.set_blend_color = r300_set_blend_color;
2111
2112 r300->context.set_clip_state = r300_set_clip_state;
2113 r300->context.set_sample_mask = r300_set_sample_mask;
2114
2115 r300->context.set_constant_buffer = r300_set_constant_buffer;
2116
2117 r300->context.create_depth_stencil_alpha_state = r300_create_dsa_state;
2118 r300->context.bind_depth_stencil_alpha_state = r300_bind_dsa_state;
2119 r300->context.delete_depth_stencil_alpha_state = r300_delete_dsa_state;
2120
2121 r300->context.set_stencil_ref = r300_set_stencil_ref;
2122
2123 r300->context.set_framebuffer_state = r300_set_framebuffer_state;
2124
2125 r300->context.create_fs_state = r300_create_fs_state;
2126 r300->context.bind_fs_state = r300_bind_fs_state;
2127 r300->context.delete_fs_state = r300_delete_fs_state;
2128
2129 r300->context.set_polygon_stipple = r300_set_polygon_stipple;
2130
2131 r300->context.create_rasterizer_state = r300_create_rs_state;
2132 r300->context.bind_rasterizer_state = r300_bind_rs_state;
2133 r300->context.delete_rasterizer_state = r300_delete_rs_state;
2134
2135 r300->context.create_sampler_state = r300_create_sampler_state;
2136 r300->context.bind_fragment_sampler_states = r300_bind_sampler_states;
2137 r300->context.bind_vertex_sampler_states = r300_lacks_vertex_textures;
2138 r300->context.delete_sampler_state = r300_delete_sampler_state;
2139
2140 r300->context.set_fragment_sampler_views = r300_set_fragment_sampler_views;
2141 r300->context.create_sampler_view = r300_create_sampler_view;
2142 r300->context.sampler_view_destroy = r300_sampler_view_destroy;
2143
2144 r300->context.set_scissor_state = r300_set_scissor_state;
2145
2146 r300->context.set_viewport_state = r300_set_viewport_state;
2147
2148 if (r300->screen->caps.has_tcl) {
2149 r300->context.set_vertex_buffers = r300_set_vertex_buffers_hwtcl;
2150 r300->context.set_index_buffer = r300_set_index_buffer_hwtcl;
2151 } else {
2152 r300->context.set_vertex_buffers = r300_set_vertex_buffers_swtcl;
2153 r300->context.set_index_buffer = r300_set_index_buffer_swtcl;
2154 }
2155
2156 r300->context.create_vertex_elements_state = r300_create_vertex_elements_state;
2157 r300->context.bind_vertex_elements_state = r300_bind_vertex_elements_state;
2158 r300->context.delete_vertex_elements_state = r300_delete_vertex_elements_state;
2159
2160 r300->context.create_vs_state = r300_create_vs_state;
2161 r300->context.bind_vs_state = r300_bind_vs_state;
2162 r300->context.delete_vs_state = r300_delete_vs_state;
2163
2164 r300->context.texture_barrier = r300_texture_barrier;
2165 }