r300g: fix routing of vertex streams if TCL is bypassed
[mesa.git] / src / gallium / drivers / r300 / r300_state.c
1 /*
2 * Copyright 2008 Corbin Simpson <MostAwesomeDude@gmail.com>
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * on the rights to use, copy, modify, merge, publish, distribute, sub
8 * license, and/or sell copies of the Software, and to permit persons to whom
9 * the Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
13 * Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHOR(S) AND/OR THEIR SUPPLIERS BE LIABLE FOR ANY CLAIM,
19 * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
20 * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
21 * USE OR OTHER DEALINGS IN THE SOFTWARE. */
22
23 #include "draw/draw_context.h"
24
25 #include "util/u_math.h"
26 #include "util/u_memory.h"
27 #include "util/u_pack_color.h"
28
29 #include "tgsi/tgsi_parse.h"
30
31 #include "pipe/p_config.h"
32 #include "pipe/internal/p_winsys_screen.h"
33
34 #include "r300_context.h"
35 #include "r300_reg.h"
36 #include "r300_screen.h"
37 #include "r300_state_inlines.h"
38 #include "r300_fs.h"
39 #include "r300_vs.h"
40
41 /* r300_state: Functions used to intialize state context by translating
42 * Gallium state objects into semi-native r300 state objects. */
43
44 /* Create a new blend state based on the CSO blend state.
45 *
46 * This encompasses alpha blending, logic/raster ops, and blend dithering. */
47 static void* r300_create_blend_state(struct pipe_context* pipe,
48 const struct pipe_blend_state* state)
49 {
50 struct r300_blend_state* blend = CALLOC_STRUCT(r300_blend_state);
51
52 if (state->blend_enable)
53 {
54 unsigned eqRGB = state->rgb_func;
55 unsigned srcRGB = state->rgb_src_factor;
56 unsigned dstRGB = state->rgb_dst_factor;
57
58 unsigned eqA = state->alpha_func;
59 unsigned srcA = state->alpha_src_factor;
60 unsigned dstA = state->alpha_dst_factor;
61
62 /* despite the name, ALPHA_BLEND_ENABLE has nothing to do with alpha,
63 * this is just the crappy D3D naming */
64 blend->blend_control = R300_ALPHA_BLEND_ENABLE |
65 r300_translate_blend_function(eqRGB) |
66 ( r300_translate_blend_factor(srcRGB) << R300_SRC_BLEND_SHIFT) |
67 ( r300_translate_blend_factor(dstRGB) << R300_DST_BLEND_SHIFT);
68
69 /* optimization: some operations do not require the destination color */
70 if (eqRGB == PIPE_BLEND_MIN || eqA == PIPE_BLEND_MIN ||
71 eqRGB == PIPE_BLEND_MAX || eqA == PIPE_BLEND_MAX ||
72 dstRGB != PIPE_BLENDFACTOR_ZERO ||
73 dstA != PIPE_BLENDFACTOR_ZERO ||
74 srcRGB == PIPE_BLENDFACTOR_DST_COLOR ||
75 srcRGB == PIPE_BLENDFACTOR_DST_ALPHA ||
76 srcRGB == PIPE_BLENDFACTOR_INV_DST_COLOR ||
77 srcRGB == PIPE_BLENDFACTOR_INV_DST_ALPHA ||
78 srcA == PIPE_BLENDFACTOR_DST_COLOR ||
79 srcA == PIPE_BLENDFACTOR_DST_ALPHA ||
80 srcA == PIPE_BLENDFACTOR_INV_DST_COLOR ||
81 srcA == PIPE_BLENDFACTOR_INV_DST_ALPHA)
82 blend->blend_control |= R300_READ_ENABLE;
83
84 /* XXX implement the optimization with DISCARD_SRC_PIXELS*/
85 /* XXX implement the optimization with SRC_ALPHA_?_NO_READ */
86
87 /* separate alpha */
88 if (srcA != srcRGB || dstA != dstRGB || eqA != eqRGB) {
89 blend->blend_control |= R300_SEPARATE_ALPHA_ENABLE;
90 blend->alpha_blend_control =
91 r300_translate_blend_function(eqA) |
92 (r300_translate_blend_factor(srcA) << R300_SRC_BLEND_SHIFT) |
93 (r300_translate_blend_factor(dstA) << R300_DST_BLEND_SHIFT);
94 }
95 }
96
97 /* PIPE_LOGICOP_* don't need to be translated, fortunately. */
98 if (state->logicop_enable) {
99 blend->rop = R300_RB3D_ROPCNTL_ROP_ENABLE |
100 (state->logicop_func) << R300_RB3D_ROPCNTL_ROP_SHIFT;
101 }
102
103 /* Color Channel Mask */
104 if (state->colormask & PIPE_MASK_R) {
105 blend->color_channel_mask |= RB3D_COLOR_CHANNEL_MASK_RED_MASK0;
106 }
107 if (state->colormask & PIPE_MASK_G) {
108 blend->color_channel_mask |= RB3D_COLOR_CHANNEL_MASK_GREEN_MASK0;
109 }
110 if (state->colormask & PIPE_MASK_B) {
111 blend->color_channel_mask |= RB3D_COLOR_CHANNEL_MASK_BLUE_MASK0;
112 }
113 if (state->colormask & PIPE_MASK_A) {
114 blend->color_channel_mask |= RB3D_COLOR_CHANNEL_MASK_ALPHA_MASK0;
115 }
116
117 if (state->dither) {
118 blend->dither = R300_RB3D_DITHER_CTL_DITHER_MODE_LUT |
119 R300_RB3D_DITHER_CTL_ALPHA_DITHER_MODE_LUT;
120 }
121
122 return (void*)blend;
123 }
124
125 /* Bind blend state. */
126 static void r300_bind_blend_state(struct pipe_context* pipe,
127 void* state)
128 {
129 struct r300_context* r300 = r300_context(pipe);
130
131 r300->blend_state = (struct r300_blend_state*)state;
132 r300->dirty_state |= R300_NEW_BLEND;
133 }
134
135 /* Free blend state. */
136 static void r300_delete_blend_state(struct pipe_context* pipe,
137 void* state)
138 {
139 FREE(state);
140 }
141
142 /* Convert float to 10bit integer */
143 static unsigned float_to_fixed10(float f)
144 {
145 return CLAMP((unsigned)(f * 1023.9f), 0, 1023);
146 }
147
148 /* Set blend color.
149 * Setup both R300 and R500 registers, figure out later which one to write. */
150 static void r300_set_blend_color(struct pipe_context* pipe,
151 const struct pipe_blend_color* color)
152 {
153 struct r300_context* r300 = r300_context(pipe);
154 union util_color uc;
155
156 util_pack_color(color->color, PIPE_FORMAT_A8R8G8B8_UNORM, &uc);
157 r300->blend_color_state->blend_color = uc.ui;
158
159 /* XXX if FP16 blending is enabled, we should use the FP16 format */
160 r300->blend_color_state->blend_color_red_alpha =
161 float_to_fixed10(color->color[0]) |
162 (float_to_fixed10(color->color[3]) << 16);
163 r300->blend_color_state->blend_color_green_blue =
164 float_to_fixed10(color->color[2]) |
165 (float_to_fixed10(color->color[1]) << 16);
166
167 r300->dirty_state |= R300_NEW_BLEND_COLOR;
168 }
169
170 static void r300_set_clip_state(struct pipe_context* pipe,
171 const struct pipe_clip_state* state)
172 {
173 struct r300_context* r300 = r300_context(pipe);
174
175 if (r300_screen(pipe->screen)->caps->has_tcl) {
176 r300->clip_state = *state;
177 r300->dirty_state |= R300_NEW_CLIP;
178 } else {
179 draw_flush(r300->draw);
180 draw_set_clip_state(r300->draw, state);
181 }
182 }
183
184 /* Create a new depth, stencil, and alpha state based on the CSO dsa state.
185 *
186 * This contains the depth buffer, stencil buffer, alpha test, and such.
187 * On the Radeon, depth and stencil buffer setup are intertwined, which is
188 * the reason for some of the strange-looking assignments across registers. */
189 static void*
190 r300_create_dsa_state(struct pipe_context* pipe,
191 const struct pipe_depth_stencil_alpha_state* state)
192 {
193 struct r300_capabilities *caps =
194 r300_screen(r300_context(pipe)->context.screen)->caps;
195 struct r300_dsa_state* dsa = CALLOC_STRUCT(r300_dsa_state);
196
197 /* Depth test setup. */
198 if (state->depth.enabled) {
199 dsa->z_buffer_control |= R300_Z_ENABLE;
200
201 if (state->depth.writemask) {
202 dsa->z_buffer_control |= R300_Z_WRITE_ENABLE;
203 }
204
205 dsa->z_stencil_control |=
206 (r300_translate_depth_stencil_function(state->depth.func) <<
207 R300_Z_FUNC_SHIFT);
208 }
209
210 /* Stencil buffer setup. */
211 if (state->stencil[0].enabled) {
212 dsa->z_buffer_control |= R300_STENCIL_ENABLE;
213 dsa->z_stencil_control |=
214 (r300_translate_depth_stencil_function(state->stencil[0].func) <<
215 R300_S_FRONT_FUNC_SHIFT) |
216 (r300_translate_stencil_op(state->stencil[0].fail_op) <<
217 R300_S_FRONT_SFAIL_OP_SHIFT) |
218 (r300_translate_stencil_op(state->stencil[0].zpass_op) <<
219 R300_S_FRONT_ZPASS_OP_SHIFT) |
220 (r300_translate_stencil_op(state->stencil[0].zfail_op) <<
221 R300_S_FRONT_ZFAIL_OP_SHIFT);
222
223 dsa->stencil_ref_mask = (state->stencil[0].ref_value) |
224 (state->stencil[0].valuemask << R300_STENCILMASK_SHIFT) |
225 (state->stencil[0].writemask << R300_STENCILWRITEMASK_SHIFT);
226
227 if (state->stencil[1].enabled) {
228 dsa->z_buffer_control |= R300_STENCIL_FRONT_BACK;
229 dsa->z_stencil_control |=
230 (r300_translate_depth_stencil_function(state->stencil[1].func) <<
231 R300_S_BACK_FUNC_SHIFT) |
232 (r300_translate_stencil_op(state->stencil[1].fail_op) <<
233 R300_S_BACK_SFAIL_OP_SHIFT) |
234 (r300_translate_stencil_op(state->stencil[1].zpass_op) <<
235 R300_S_BACK_ZPASS_OP_SHIFT) |
236 (r300_translate_stencil_op(state->stencil[1].zfail_op) <<
237 R300_S_BACK_ZFAIL_OP_SHIFT);
238
239 /* XXX it seems r3xx doesn't support STENCILREFMASK_BF */
240 if (caps->is_r500)
241 {
242 dsa->z_buffer_control |= R500_STENCIL_REFMASK_FRONT_BACK;
243 dsa->stencil_ref_bf = (state->stencil[1].ref_value) |
244 (state->stencil[1].valuemask <<
245 R300_STENCILMASK_SHIFT) |
246 (state->stencil[1].writemask <<
247 R300_STENCILWRITEMASK_SHIFT);
248 }
249 }
250 }
251
252 /* Alpha test setup. */
253 if (state->alpha.enabled) {
254 dsa->alpha_function =
255 r300_translate_alpha_function(state->alpha.func) |
256 R300_FG_ALPHA_FUNC_ENABLE;
257
258 /* XXX figure out why emitting 10bit alpha ref causes CS to dump */
259 /* always use 8bit alpha ref */
260 dsa->alpha_function |= float_to_ubyte(state->alpha.ref_value);
261
262 if (caps->is_r500)
263 dsa->alpha_function |= R500_FG_ALPHA_FUNC_8BIT;
264 }
265
266 return (void*)dsa;
267 }
268
269 /* Bind DSA state. */
270 static void r300_bind_dsa_state(struct pipe_context* pipe,
271 void* state)
272 {
273 struct r300_context* r300 = r300_context(pipe);
274
275 r300->dsa_state = (struct r300_dsa_state*)state;
276 r300->dirty_state |= R300_NEW_DSA;
277 }
278
279 /* Free DSA state. */
280 static void r300_delete_dsa_state(struct pipe_context* pipe,
281 void* state)
282 {
283 FREE(state);
284 }
285
286 static void r300_set_edgeflags(struct pipe_context* pipe,
287 const unsigned* bitfield)
288 {
289 /* XXX you know it's bad when i915 has this blank too */
290 /* XXX and even worse, I have no idea WTF the bitfield is */
291 }
292
293 static void r300_set_scissor_regs(const struct pipe_scissor_state* state,
294 struct r300_scissor_regs *scissor,
295 boolean is_r500)
296 {
297 if (is_r500) {
298 scissor->top_left =
299 (state->minx << R300_SCISSORS_X_SHIFT) |
300 (state->miny << R300_SCISSORS_Y_SHIFT);
301 scissor->bottom_right =
302 ((state->maxx - 1) << R300_SCISSORS_X_SHIFT) |
303 ((state->maxy - 1) << R300_SCISSORS_Y_SHIFT);
304 } else {
305 /* Offset of 1440 in non-R500 chipsets. */
306 scissor->top_left =
307 ((state->minx + 1440) << R300_SCISSORS_X_SHIFT) |
308 ((state->miny + 1440) << R300_SCISSORS_Y_SHIFT);
309 scissor->bottom_right =
310 (((state->maxx - 1) + 1440) << R300_SCISSORS_X_SHIFT) |
311 (((state->maxy - 1) + 1440) << R300_SCISSORS_Y_SHIFT);
312 }
313
314 scissor->empty_area = state->minx >= state->maxx ||
315 state->miny >= state->maxy;
316 }
317
318 static void
319 r300_set_framebuffer_state(struct pipe_context* pipe,
320 const struct pipe_framebuffer_state* state)
321 {
322 struct r300_context* r300 = r300_context(pipe);
323 struct pipe_scissor_state scissor;
324
325 if (r300->draw) {
326 draw_flush(r300->draw);
327 }
328
329 r300->framebuffer_state = *state;
330
331 scissor.minx = scissor.miny = 0;
332 scissor.maxx = state->width;
333 scissor.maxy = state->height;
334 r300_set_scissor_regs(&scissor, &r300->scissor_state->framebuffer,
335 r300_screen(r300->context.screen)->caps->is_r500);
336
337 /* Don't rely on the order of states being set for the first time. */
338 if (!r300->rs_state || !r300->rs_state->rs.scissor) {
339 r300->dirty_state |= R300_NEW_SCISSOR;
340 }
341 r300->dirty_state |= R300_NEW_FRAMEBUFFERS;
342 }
343
344 /* Create fragment shader state. */
345 static void* r300_create_fs_state(struct pipe_context* pipe,
346 const struct pipe_shader_state* shader)
347 {
348 struct r300_fragment_shader* fs = NULL;
349
350 fs = (struct r300_fragment_shader*)CALLOC_STRUCT(r300_fragment_shader);
351
352 /* Copy state directly into shader. */
353 fs->state = *shader;
354 fs->state.tokens = tgsi_dup_tokens(shader->tokens);
355
356 tgsi_scan_shader(shader->tokens, &fs->info);
357
358 return (void*)fs;
359 }
360
361 /* Bind fragment shader state. */
362 static void r300_bind_fs_state(struct pipe_context* pipe, void* shader)
363 {
364 struct r300_context* r300 = r300_context(pipe);
365 struct r300_fragment_shader* fs = (struct r300_fragment_shader*)shader;
366
367 if (fs == NULL) {
368 r300->fs = NULL;
369 return;
370 } else if (!fs->translated) {
371 r300_translate_fragment_shader(r300, fs);
372 }
373
374 r300->fs = fs;
375
376 r300->dirty_state |= R300_NEW_FRAGMENT_SHADER | R300_NEW_FRAGMENT_SHADER_CONSTANTS;
377 }
378
379 /* Delete fragment shader state. */
380 static void r300_delete_fs_state(struct pipe_context* pipe, void* shader)
381 {
382 struct r300_fragment_shader* fs = (struct r300_fragment_shader*)shader;
383 rc_constants_destroy(&fs->code.constants);
384 FREE((void*)fs->state.tokens);
385 FREE(shader);
386 }
387
388 static void r300_set_polygon_stipple(struct pipe_context* pipe,
389 const struct pipe_poly_stipple* state)
390 {
391 /* XXX no idea how to set this up, but not terribly important */
392 }
393
394 /* Create a new rasterizer state based on the CSO rasterizer state.
395 *
396 * This is a very large chunk of state, and covers most of the graphics
397 * backend (GB), geometry assembly (GA), and setup unit (SU) blocks.
398 *
399 * In a not entirely unironic sidenote, this state has nearly nothing to do
400 * with the actual block on the Radeon called the rasterizer (RS). */
401 static void* r300_create_rs_state(struct pipe_context* pipe,
402 const struct pipe_rasterizer_state* state)
403 {
404 struct r300_rs_state* rs = CALLOC_STRUCT(r300_rs_state);
405
406 /* Copy rasterizer state for Draw. */
407 rs->rs = *state;
408
409 rs->enable_vte = !state->bypass_vs_clip_and_viewport;
410
411 #ifdef PIPE_ARCH_LITTLE_ENDIAN
412 rs->vap_control_status = R300_VC_NO_SWAP;
413 #else
414 rs->vap_control_status = R300_VC_32BIT_SWAP;
415 #endif
416
417 /* If bypassing TCL, or if no TCL engine is present, turn off the HW TCL.
418 * Else, enable HW TCL and force Draw's TCL off. */
419 if (state->bypass_vs_clip_and_viewport ||
420 !r300_screen(pipe->screen)->caps->has_tcl) {
421 rs->vap_control_status |= R300_VAP_TCL_BYPASS;
422 }
423
424 rs->point_size = pack_float_16_6x(state->point_size) |
425 (pack_float_16_6x(state->point_size) << R300_POINTSIZE_X_SHIFT);
426
427 rs->point_minmax =
428 ((int)(state->point_size_min * 6.0) <<
429 R300_GA_POINT_MINMAX_MIN_SHIFT) |
430 ((int)(state->point_size_max * 6.0) <<
431 R300_GA_POINT_MINMAX_MAX_SHIFT);
432
433 rs->line_control = pack_float_16_6x(state->line_width) |
434 R300_GA_LINE_CNTL_END_TYPE_COMP;
435
436 /* XXX I think there is something wrong with the polygon mode,
437 * XXX re-test when r300g is in a better shape */
438
439 /* Enable polygon mode */
440 if (state->fill_cw != PIPE_POLYGON_MODE_FILL ||
441 state->fill_ccw != PIPE_POLYGON_MODE_FILL) {
442 rs->polygon_mode = R300_GA_POLY_MODE_DUAL;
443 }
444
445 /* Radeons don't think in "CW/CCW", they think in "front/back". */
446 if (state->front_winding == PIPE_WINDING_CW) {
447 rs->cull_mode = R300_FRONT_FACE_CW;
448
449 /* Polygon offset */
450 if (state->offset_cw) {
451 rs->polygon_offset_enable |= R300_FRONT_ENABLE;
452 }
453 if (state->offset_ccw) {
454 rs->polygon_offset_enable |= R300_BACK_ENABLE;
455 }
456
457 /* Polygon mode */
458 if (rs->polygon_mode) {
459 rs->polygon_mode |=
460 r300_translate_polygon_mode_front(state->fill_cw);
461 rs->polygon_mode |=
462 r300_translate_polygon_mode_back(state->fill_ccw);
463 }
464 } else {
465 rs->cull_mode = R300_FRONT_FACE_CCW;
466
467 /* Polygon offset */
468 if (state->offset_ccw) {
469 rs->polygon_offset_enable |= R300_FRONT_ENABLE;
470 }
471 if (state->offset_cw) {
472 rs->polygon_offset_enable |= R300_BACK_ENABLE;
473 }
474
475 /* Polygon mode */
476 if (rs->polygon_mode) {
477 rs->polygon_mode |=
478 r300_translate_polygon_mode_front(state->fill_ccw);
479 rs->polygon_mode |=
480 r300_translate_polygon_mode_back(state->fill_cw);
481 }
482 }
483 if (state->front_winding & state->cull_mode) {
484 rs->cull_mode |= R300_CULL_FRONT;
485 }
486 if (~(state->front_winding) & state->cull_mode) {
487 rs->cull_mode |= R300_CULL_BACK;
488 }
489
490 if (rs->polygon_offset_enable) {
491 rs->depth_offset_front = rs->depth_offset_back =
492 fui(state->offset_units);
493 rs->depth_scale_front = rs->depth_scale_back =
494 fui(state->offset_scale);
495 }
496
497 if (state->line_stipple_enable) {
498 rs->line_stipple_config =
499 R300_GA_LINE_STIPPLE_CONFIG_LINE_RESET_LINE |
500 (fui((float)state->line_stipple_factor) &
501 R300_GA_LINE_STIPPLE_CONFIG_STIPPLE_SCALE_MASK);
502 /* XXX this might need to be scaled up */
503 rs->line_stipple_value = state->line_stipple_pattern;
504 }
505
506 if (state->flatshade) {
507 rs->color_control = R300_SHADE_MODEL_FLAT;
508 } else {
509 rs->color_control = R300_SHADE_MODEL_SMOOTH;
510 }
511
512 if (!state->flatshade_first) {
513 rs->color_control |= R300_GA_COLOR_CONTROL_PROVOKING_VERTEX_LAST;
514 }
515
516 return (void*)rs;
517 }
518
519 /* Bind rasterizer state. */
520 static void r300_bind_rs_state(struct pipe_context* pipe, void* state)
521 {
522 struct r300_context* r300 = r300_context(pipe);
523 struct r300_rs_state* rs = (struct r300_rs_state*)state;
524
525 if (r300->draw) {
526 draw_flush(r300->draw);
527 draw_set_rasterizer_state(r300->draw, &rs->rs);
528 }
529
530 r300->rs_state = rs;
531 /* XXX Clean these up when we move to atom emits */
532 r300->dirty_state |= R300_NEW_RASTERIZER;
533 r300->dirty_state |= R300_NEW_RS_BLOCK;
534 r300->dirty_state |= R300_NEW_SCISSOR;
535 r300->dirty_state |= R300_NEW_VIEWPORT;
536 }
537
538 /* Free rasterizer state. */
539 static void r300_delete_rs_state(struct pipe_context* pipe, void* state)
540 {
541 FREE(state);
542 }
543
544 static void*
545 r300_create_sampler_state(struct pipe_context* pipe,
546 const struct pipe_sampler_state* state)
547 {
548 struct r300_context* r300 = r300_context(pipe);
549 struct r300_sampler_state* sampler = CALLOC_STRUCT(r300_sampler_state);
550 int lod_bias;
551 union util_color uc;
552
553 sampler->filter0 |=
554 (r300_translate_wrap(state->wrap_s) << R300_TX_WRAP_S_SHIFT) |
555 (r300_translate_wrap(state->wrap_t) << R300_TX_WRAP_T_SHIFT) |
556 (r300_translate_wrap(state->wrap_r) << R300_TX_WRAP_R_SHIFT);
557
558 sampler->filter0 |= r300_translate_tex_filters(state->min_img_filter,
559 state->mag_img_filter,
560 state->min_mip_filter);
561
562 /* Unfortunately, r300-r500 don't support floating-point mipmap lods. */
563 /* We must pass these to the emit function to clamp them properly. */
564 sampler->min_lod = MAX2((unsigned)state->min_lod, 0);
565 sampler->max_lod = MAX2((unsigned)ceilf(state->max_lod), 0);
566
567 lod_bias = CLAMP((int)(state->lod_bias * 32), -(1 << 9), (1 << 9) - 1);
568
569 sampler->filter1 |= lod_bias << R300_LOD_BIAS_SHIFT;
570
571 sampler->filter1 |= r300_anisotropy(state->max_anisotropy);
572
573 util_pack_color(state->border_color, PIPE_FORMAT_A8R8G8B8_UNORM, &uc);
574 sampler->border_color = uc.ui;
575
576 /* R500-specific fixups and optimizations */
577 if (r300_screen(r300->context.screen)->caps->is_r500) {
578 sampler->filter1 |= R500_BORDER_FIX;
579 }
580
581 return (void*)sampler;
582 }
583
584 static void r300_bind_sampler_states(struct pipe_context* pipe,
585 unsigned count,
586 void** states)
587 {
588 struct r300_context* r300 = r300_context(pipe);
589 int i;
590
591 if (count > 8) {
592 return;
593 }
594
595 for (i = 0; i < count; i++) {
596 if (r300->sampler_states[i] != states[i]) {
597 r300->sampler_states[i] = (struct r300_sampler_state*)states[i];
598 r300->dirty_state |= (R300_NEW_SAMPLER << i);
599 }
600 }
601
602 r300->sampler_count = count;
603 }
604
605 static void r300_lacks_vertex_textures(struct pipe_context* pipe,
606 unsigned count,
607 void** states)
608 {
609 }
610
611 static void r300_delete_sampler_state(struct pipe_context* pipe, void* state)
612 {
613 FREE(state);
614 }
615
616 static void r300_set_sampler_textures(struct pipe_context* pipe,
617 unsigned count,
618 struct pipe_texture** texture)
619 {
620 struct r300_context* r300 = r300_context(pipe);
621 boolean is_r500 = r300_screen(r300->context.screen)->caps->is_r500;
622 int i;
623
624 /* XXX magic num */
625 if (count > 8) {
626 return;
627 }
628
629 r300->context.flush(&r300->context, 0, NULL);
630
631 for (i = 0; i < count; i++) {
632 if (r300->textures[i] != (struct r300_texture*)texture[i]) {
633 pipe_texture_reference((struct pipe_texture**)&r300->textures[i],
634 texture[i]);
635 r300->dirty_state |= (R300_NEW_TEXTURE << i);
636
637 /* R300-specific - set the texrect factor in a fragment shader */
638 if (!is_r500 && r300->textures[i]->is_npot) {
639 /* XXX It would be nice to re-emit just 1 constant,
640 * XXX not all of them */
641 r300->dirty_state |= R300_NEW_FRAGMENT_SHADER_CONSTANTS;
642 }
643 }
644 }
645
646 for (i = count; i < 8; i++) {
647 if (r300->textures[i]) {
648 pipe_texture_reference((struct pipe_texture**)&r300->textures[i],
649 NULL);
650 r300->dirty_state |= (R300_NEW_TEXTURE << i);
651 }
652 }
653
654 r300->texture_count = count;
655 }
656
657 static void r300_set_scissor_state(struct pipe_context* pipe,
658 const struct pipe_scissor_state* state)
659 {
660 struct r300_context* r300 = r300_context(pipe);
661
662 r300_set_scissor_regs(state, &r300->scissor_state->scissor,
663 r300_screen(r300->context.screen)->caps->is_r500);
664
665 /* Don't rely on the order of states being set for the first time. */
666 if (!r300->rs_state || r300->rs_state->rs.scissor) {
667 r300->dirty_state |= R300_NEW_SCISSOR;
668 }
669 }
670
671 static void r300_set_viewport_state(struct pipe_context* pipe,
672 const struct pipe_viewport_state* state)
673 {
674 struct r300_context* r300 = r300_context(pipe);
675
676 /* Do the transform in HW. */
677 r300->viewport_state->vte_control = R300_VTX_W0_FMT;
678
679 if (state->scale[0] != 1.0f) {
680 r300->viewport_state->xscale = state->scale[0];
681 r300->viewport_state->vte_control |= R300_VPORT_X_SCALE_ENA;
682 }
683 if (state->scale[1] != 1.0f) {
684 r300->viewport_state->yscale = state->scale[1];
685 r300->viewport_state->vte_control |= R300_VPORT_Y_SCALE_ENA;
686 }
687 if (state->scale[2] != 1.0f) {
688 r300->viewport_state->zscale = state->scale[2];
689 r300->viewport_state->vte_control |= R300_VPORT_Z_SCALE_ENA;
690 }
691 if (state->translate[0] != 0.0f) {
692 r300->viewport_state->xoffset = state->translate[0];
693 r300->viewport_state->vte_control |= R300_VPORT_X_OFFSET_ENA;
694 }
695 if (state->translate[1] != 0.0f) {
696 r300->viewport_state->yoffset = state->translate[1];
697 r300->viewport_state->vte_control |= R300_VPORT_Y_OFFSET_ENA;
698 }
699 if (state->translate[2] != 0.0f) {
700 r300->viewport_state->zoffset = state->translate[2];
701 r300->viewport_state->vte_control |= R300_VPORT_Z_OFFSET_ENA;
702 }
703
704 r300->dirty_state |= R300_NEW_VIEWPORT;
705 }
706
707 static void r300_set_vertex_buffers(struct pipe_context* pipe,
708 unsigned count,
709 const struct pipe_vertex_buffer* buffers)
710 {
711 struct r300_context* r300 = r300_context(pipe);
712
713 memcpy(r300->vertex_buffer, buffers,
714 sizeof(struct pipe_vertex_buffer) * count);
715 r300->vertex_buffer_count = count;
716
717 if (r300->draw) {
718 draw_flush(r300->draw);
719 draw_set_vertex_buffers(r300->draw, count, buffers);
720 }
721
722 r300->dirty_state |= R300_NEW_VERTEX_FORMAT;
723 }
724
725 static void r300_set_vertex_elements(struct pipe_context* pipe,
726 unsigned count,
727 const struct pipe_vertex_element* elements)
728 {
729 struct r300_context* r300 = r300_context(pipe);
730
731 memcpy(r300->vertex_element,
732 elements,
733 sizeof(struct pipe_vertex_element) * count);
734 r300->vertex_element_count = count;
735
736 if (r300->draw) {
737 draw_flush(r300->draw);
738 draw_set_vertex_elements(r300->draw, count, elements);
739 }
740 }
741
742 static void* r300_create_vs_state(struct pipe_context* pipe,
743 const struct pipe_shader_state* shader)
744 {
745 struct r300_context* r300 = r300_context(pipe);
746
747 if (r300_screen(pipe->screen)->caps->has_tcl) {
748 struct r300_vertex_shader* vs = CALLOC_STRUCT(r300_vertex_shader);
749 /* Copy state directly into shader. */
750 vs->state = *shader;
751 vs->state.tokens = tgsi_dup_tokens(shader->tokens);
752
753 tgsi_scan_shader(shader->tokens, &vs->info);
754
755 return (void*)vs;
756 } else {
757 return draw_create_vertex_shader(r300->draw, shader);
758 }
759 }
760
761 static void r300_bind_vs_state(struct pipe_context* pipe, void* shader)
762 {
763 struct r300_context* r300 = r300_context(pipe);
764
765 if (r300_screen(pipe->screen)->caps->has_tcl) {
766 struct r300_vertex_shader* vs = (struct r300_vertex_shader*)shader;
767
768 if (vs == NULL) {
769 r300->vs = NULL;
770 return;
771 } else if (!vs->translated) {
772 r300_translate_vertex_shader(r300, vs);
773 }
774
775 r300->vs = vs;
776 r300->dirty_state |= R300_NEW_VERTEX_SHADER | R300_NEW_VERTEX_SHADER_CONSTANTS;
777 } else {
778 draw_flush(r300->draw);
779 draw_bind_vertex_shader(r300->draw,
780 (struct draw_vertex_shader*)shader);
781 }
782 }
783
784 static void r300_delete_vs_state(struct pipe_context* pipe, void* shader)
785 {
786 struct r300_context* r300 = r300_context(pipe);
787
788 if (r300_screen(pipe->screen)->caps->has_tcl) {
789 struct r300_vertex_shader* vs = (struct r300_vertex_shader*)shader;
790
791 rc_constants_destroy(&vs->code.constants);
792 FREE((void*)vs->state.tokens);
793 FREE(shader);
794 } else {
795 draw_delete_vertex_shader(r300->draw,
796 (struct draw_vertex_shader*)shader);
797 }
798 }
799
800 static void r300_set_constant_buffer(struct pipe_context *pipe,
801 uint shader, uint index,
802 const struct pipe_constant_buffer *buf)
803 {
804 struct r300_context* r300 = r300_context(pipe);
805 void *mapped;
806
807 if (buf == NULL || buf->buffer->size == 0 ||
808 (mapped = pipe_buffer_map(pipe->screen, buf->buffer, PIPE_BUFFER_USAGE_CPU_READ)) == NULL)
809 {
810 r300->shader_constants[shader].count = 0;
811 return;
812 }
813
814 assert((buf->buffer->size % 4 * sizeof(float)) == 0);
815 memcpy(r300->shader_constants[shader].constants, mapped, buf->buffer->size);
816 r300->shader_constants[shader].count = buf->buffer->size / (4 * sizeof(float));
817 pipe_buffer_unmap(pipe->screen, buf->buffer);
818
819 if (shader == PIPE_SHADER_VERTEX)
820 r300->dirty_state |= R300_NEW_VERTEX_SHADER_CONSTANTS;
821 else if (shader == PIPE_SHADER_FRAGMENT)
822 r300->dirty_state |= R300_NEW_FRAGMENT_SHADER_CONSTANTS;
823 }
824
825 void r300_init_state_functions(struct r300_context* r300)
826 {
827 r300->context.create_blend_state = r300_create_blend_state;
828 r300->context.bind_blend_state = r300_bind_blend_state;
829 r300->context.delete_blend_state = r300_delete_blend_state;
830
831 r300->context.set_blend_color = r300_set_blend_color;
832
833 r300->context.set_clip_state = r300_set_clip_state;
834
835 r300->context.set_constant_buffer = r300_set_constant_buffer;
836
837 r300->context.create_depth_stencil_alpha_state = r300_create_dsa_state;
838 r300->context.bind_depth_stencil_alpha_state = r300_bind_dsa_state;
839 r300->context.delete_depth_stencil_alpha_state = r300_delete_dsa_state;
840
841 r300->context.set_edgeflags = r300_set_edgeflags;
842
843 r300->context.set_framebuffer_state = r300_set_framebuffer_state;
844
845 r300->context.create_fs_state = r300_create_fs_state;
846 r300->context.bind_fs_state = r300_bind_fs_state;
847 r300->context.delete_fs_state = r300_delete_fs_state;
848
849 r300->context.set_polygon_stipple = r300_set_polygon_stipple;
850
851 r300->context.create_rasterizer_state = r300_create_rs_state;
852 r300->context.bind_rasterizer_state = r300_bind_rs_state;
853 r300->context.delete_rasterizer_state = r300_delete_rs_state;
854
855 r300->context.create_sampler_state = r300_create_sampler_state;
856 r300->context.bind_fragment_sampler_states = r300_bind_sampler_states;
857 r300->context.bind_vertex_sampler_states = r300_lacks_vertex_textures;
858 r300->context.delete_sampler_state = r300_delete_sampler_state;
859
860 r300->context.set_fragment_sampler_textures = r300_set_sampler_textures;
861
862 r300->context.set_scissor_state = r300_set_scissor_state;
863
864 r300->context.set_viewport_state = r300_set_viewport_state;
865
866 r300->context.set_vertex_buffers = r300_set_vertex_buffers;
867 r300->context.set_vertex_elements = r300_set_vertex_elements;
868
869 r300->context.create_vs_state = r300_create_vs_state;
870 r300->context.bind_vs_state = r300_bind_vs_state;
871 r300->context.delete_vs_state = r300_delete_vs_state;
872 }