Merge remote branch 'origin/nvc0'
[mesa.git] / src / gallium / drivers / r300 / r300_state.c
1 /*
2 * Copyright 2008 Corbin Simpson <MostAwesomeDude@gmail.com>
3 * Copyright 2009 Marek Olšák <maraeo@gmail.com>
4 *
5 * Permission is hereby granted, free of charge, to any person obtaining a
6 * copy of this software and associated documentation files (the "Software"),
7 * to deal in the Software without restriction, including without limitation
8 * on the rights to use, copy, modify, merge, publish, distribute, sub
9 * license, and/or sell copies of the Software, and to permit persons to whom
10 * the Software is furnished to do so, subject to the following conditions:
11 *
12 * The above copyright notice and this permission notice (including the next
13 * paragraph) shall be included in all copies or substantial portions of the
14 * Software.
15 *
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
19 * THE AUTHOR(S) AND/OR THEIR SUPPLIERS BE LIABLE FOR ANY CLAIM,
20 * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
21 * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
22 * USE OR OTHER DEALINGS IN THE SOFTWARE. */
23
24 #include "draw/draw_context.h"
25
26 #include "util/u_framebuffer.h"
27 #include "util/u_math.h"
28 #include "util/u_mm.h"
29 #include "util/u_memory.h"
30 #include "util/u_pack_color.h"
31 #include "util/u_transfer.h"
32
33 #include "tgsi/tgsi_parse.h"
34
35 #include "pipe/p_config.h"
36
37 #include "r300_cb.h"
38 #include "r300_context.h"
39 #include "r300_emit.h"
40 #include "r300_reg.h"
41 #include "r300_screen.h"
42 #include "r300_screen_buffer.h"
43 #include "r300_state_inlines.h"
44 #include "r300_fs.h"
45 #include "r300_texture.h"
46 #include "r300_vs.h"
47 #include "r300_winsys.h"
48
49 /* r300_state: Functions used to intialize state context by translating
50 * Gallium state objects into semi-native r300 state objects. */
51
52 #define UPDATE_STATE(cso, atom) \
53 if (cso != atom.state) { \
54 atom.state = cso; \
55 r300_mark_atom_dirty(r300, &(atom)); \
56 }
57
58 static boolean blend_discard_if_src_alpha_0(unsigned srcRGB, unsigned srcA,
59 unsigned dstRGB, unsigned dstA)
60 {
61 /* If the blend equation is ADD or REVERSE_SUBTRACT,
62 * SRC_ALPHA == 0, and the following state is set, the colorbuffer
63 * will not be changed.
64 * Notice that the dst factors are the src factors inverted. */
65 return (srcRGB == PIPE_BLENDFACTOR_SRC_ALPHA ||
66 srcRGB == PIPE_BLENDFACTOR_SRC_ALPHA_SATURATE ||
67 srcRGB == PIPE_BLENDFACTOR_ZERO) &&
68 (srcA == PIPE_BLENDFACTOR_SRC_COLOR ||
69 srcA == PIPE_BLENDFACTOR_SRC_ALPHA ||
70 srcA == PIPE_BLENDFACTOR_SRC_ALPHA_SATURATE ||
71 srcA == PIPE_BLENDFACTOR_ZERO) &&
72 (dstRGB == PIPE_BLENDFACTOR_INV_SRC_ALPHA ||
73 dstRGB == PIPE_BLENDFACTOR_ONE) &&
74 (dstA == PIPE_BLENDFACTOR_INV_SRC_COLOR ||
75 dstA == PIPE_BLENDFACTOR_INV_SRC_ALPHA ||
76 dstA == PIPE_BLENDFACTOR_ONE);
77 }
78
79 static boolean blend_discard_if_src_alpha_1(unsigned srcRGB, unsigned srcA,
80 unsigned dstRGB, unsigned dstA)
81 {
82 /* If the blend equation is ADD or REVERSE_SUBTRACT,
83 * SRC_ALPHA == 1, and the following state is set, the colorbuffer
84 * will not be changed.
85 * Notice that the dst factors are the src factors inverted. */
86 return (srcRGB == PIPE_BLENDFACTOR_INV_SRC_ALPHA ||
87 srcRGB == PIPE_BLENDFACTOR_ZERO) &&
88 (srcA == PIPE_BLENDFACTOR_INV_SRC_COLOR ||
89 srcA == PIPE_BLENDFACTOR_INV_SRC_ALPHA ||
90 srcA == PIPE_BLENDFACTOR_ZERO) &&
91 (dstRGB == PIPE_BLENDFACTOR_SRC_ALPHA ||
92 dstRGB == PIPE_BLENDFACTOR_ONE) &&
93 (dstA == PIPE_BLENDFACTOR_SRC_COLOR ||
94 dstA == PIPE_BLENDFACTOR_SRC_ALPHA ||
95 dstA == PIPE_BLENDFACTOR_ONE);
96 }
97
98 static boolean blend_discard_if_src_color_0(unsigned srcRGB, unsigned srcA,
99 unsigned dstRGB, unsigned dstA)
100 {
101 /* If the blend equation is ADD or REVERSE_SUBTRACT,
102 * SRC_COLOR == (0,0,0), and the following state is set, the colorbuffer
103 * will not be changed.
104 * Notice that the dst factors are the src factors inverted. */
105 return (srcRGB == PIPE_BLENDFACTOR_SRC_COLOR ||
106 srcRGB == PIPE_BLENDFACTOR_ZERO) &&
107 (srcA == PIPE_BLENDFACTOR_ZERO) &&
108 (dstRGB == PIPE_BLENDFACTOR_INV_SRC_COLOR ||
109 dstRGB == PIPE_BLENDFACTOR_ONE) &&
110 (dstA == PIPE_BLENDFACTOR_ONE);
111 }
112
113 static boolean blend_discard_if_src_color_1(unsigned srcRGB, unsigned srcA,
114 unsigned dstRGB, unsigned dstA)
115 {
116 /* If the blend equation is ADD or REVERSE_SUBTRACT,
117 * SRC_COLOR == (1,1,1), and the following state is set, the colorbuffer
118 * will not be changed.
119 * Notice that the dst factors are the src factors inverted. */
120 return (srcRGB == PIPE_BLENDFACTOR_INV_SRC_COLOR ||
121 srcRGB == PIPE_BLENDFACTOR_ZERO) &&
122 (srcA == PIPE_BLENDFACTOR_ZERO) &&
123 (dstRGB == PIPE_BLENDFACTOR_SRC_COLOR ||
124 dstRGB == PIPE_BLENDFACTOR_ONE) &&
125 (dstA == PIPE_BLENDFACTOR_ONE);
126 }
127
128 static boolean blend_discard_if_src_alpha_color_0(unsigned srcRGB, unsigned srcA,
129 unsigned dstRGB, unsigned dstA)
130 {
131 /* If the blend equation is ADD or REVERSE_SUBTRACT,
132 * SRC_ALPHA_COLOR == (0,0,0,0), and the following state is set,
133 * the colorbuffer will not be changed.
134 * Notice that the dst factors are the src factors inverted. */
135 return (srcRGB == PIPE_BLENDFACTOR_SRC_COLOR ||
136 srcRGB == PIPE_BLENDFACTOR_SRC_ALPHA ||
137 srcRGB == PIPE_BLENDFACTOR_SRC_ALPHA_SATURATE ||
138 srcRGB == PIPE_BLENDFACTOR_ZERO) &&
139 (srcA == PIPE_BLENDFACTOR_SRC_COLOR ||
140 srcA == PIPE_BLENDFACTOR_SRC_ALPHA ||
141 srcA == PIPE_BLENDFACTOR_SRC_ALPHA_SATURATE ||
142 srcA == PIPE_BLENDFACTOR_ZERO) &&
143 (dstRGB == PIPE_BLENDFACTOR_INV_SRC_COLOR ||
144 dstRGB == PIPE_BLENDFACTOR_INV_SRC_ALPHA ||
145 dstRGB == PIPE_BLENDFACTOR_ONE) &&
146 (dstA == PIPE_BLENDFACTOR_INV_SRC_COLOR ||
147 dstA == PIPE_BLENDFACTOR_INV_SRC_ALPHA ||
148 dstA == PIPE_BLENDFACTOR_ONE);
149 }
150
151 static boolean blend_discard_if_src_alpha_color_1(unsigned srcRGB, unsigned srcA,
152 unsigned dstRGB, unsigned dstA)
153 {
154 /* If the blend equation is ADD or REVERSE_SUBTRACT,
155 * SRC_ALPHA_COLOR == (1,1,1,1), and the following state is set,
156 * the colorbuffer will not be changed.
157 * Notice that the dst factors are the src factors inverted. */
158 return (srcRGB == PIPE_BLENDFACTOR_INV_SRC_COLOR ||
159 srcRGB == PIPE_BLENDFACTOR_INV_SRC_ALPHA ||
160 srcRGB == PIPE_BLENDFACTOR_ZERO) &&
161 (srcA == PIPE_BLENDFACTOR_INV_SRC_COLOR ||
162 srcA == PIPE_BLENDFACTOR_INV_SRC_ALPHA ||
163 srcA == PIPE_BLENDFACTOR_ZERO) &&
164 (dstRGB == PIPE_BLENDFACTOR_SRC_COLOR ||
165 dstRGB == PIPE_BLENDFACTOR_SRC_ALPHA ||
166 dstRGB == PIPE_BLENDFACTOR_ONE) &&
167 (dstA == PIPE_BLENDFACTOR_SRC_COLOR ||
168 dstA == PIPE_BLENDFACTOR_SRC_ALPHA ||
169 dstA == PIPE_BLENDFACTOR_ONE);
170 }
171
172 static unsigned bgra_cmask(unsigned mask)
173 {
174 /* Gallium uses RGBA color ordering while R300 expects BGRA. */
175
176 return ((mask & PIPE_MASK_R) << 2) |
177 ((mask & PIPE_MASK_B) >> 2) |
178 (mask & (PIPE_MASK_G | PIPE_MASK_A));
179 }
180
181 /* Create a new blend state based on the CSO blend state.
182 *
183 * This encompasses alpha blending, logic/raster ops, and blend dithering. */
184 static void* r300_create_blend_state(struct pipe_context* pipe,
185 const struct pipe_blend_state* state)
186 {
187 struct r300_screen* r300screen = r300_screen(pipe->screen);
188 struct r300_blend_state* blend = CALLOC_STRUCT(r300_blend_state);
189 uint32_t blend_control = 0; /* R300_RB3D_CBLEND: 0x4e04 */
190 uint32_t alpha_blend_control = 0; /* R300_RB3D_ABLEND: 0x4e08 */
191 uint32_t color_channel_mask = 0; /* R300_RB3D_COLOR_CHANNEL_MASK: 0x4e0c */
192 uint32_t rop = 0; /* R300_RB3D_ROPCNTL: 0x4e18 */
193 uint32_t dither = 0; /* R300_RB3D_DITHER_CTL: 0x4e50 */
194 CB_LOCALS;
195
196 if (state->rt[0].blend_enable)
197 {
198 unsigned eqRGB = state->rt[0].rgb_func;
199 unsigned srcRGB = state->rt[0].rgb_src_factor;
200 unsigned dstRGB = state->rt[0].rgb_dst_factor;
201
202 unsigned eqA = state->rt[0].alpha_func;
203 unsigned srcA = state->rt[0].alpha_src_factor;
204 unsigned dstA = state->rt[0].alpha_dst_factor;
205
206 /* despite the name, ALPHA_BLEND_ENABLE has nothing to do with alpha,
207 * this is just the crappy D3D naming */
208 blend_control = R300_ALPHA_BLEND_ENABLE |
209 r300_translate_blend_function(eqRGB) |
210 ( r300_translate_blend_factor(srcRGB) << R300_SRC_BLEND_SHIFT) |
211 ( r300_translate_blend_factor(dstRGB) << R300_DST_BLEND_SHIFT);
212
213 /* Optimization: some operations do not require the destination color.
214 *
215 * When SRC_ALPHA_SATURATE is used, colorbuffer reads must be enabled,
216 * otherwise blending gives incorrect results. It seems to be
217 * a hardware bug. */
218 if (eqRGB == PIPE_BLEND_MIN || eqA == PIPE_BLEND_MIN ||
219 eqRGB == PIPE_BLEND_MAX || eqA == PIPE_BLEND_MAX ||
220 dstRGB != PIPE_BLENDFACTOR_ZERO ||
221 dstA != PIPE_BLENDFACTOR_ZERO ||
222 srcRGB == PIPE_BLENDFACTOR_DST_COLOR ||
223 srcRGB == PIPE_BLENDFACTOR_DST_ALPHA ||
224 srcRGB == PIPE_BLENDFACTOR_INV_DST_COLOR ||
225 srcRGB == PIPE_BLENDFACTOR_INV_DST_ALPHA ||
226 srcA == PIPE_BLENDFACTOR_DST_COLOR ||
227 srcA == PIPE_BLENDFACTOR_DST_ALPHA ||
228 srcA == PIPE_BLENDFACTOR_INV_DST_COLOR ||
229 srcA == PIPE_BLENDFACTOR_INV_DST_ALPHA ||
230 srcRGB == PIPE_BLENDFACTOR_SRC_ALPHA_SATURATE) {
231 /* Enable reading from the colorbuffer. */
232 blend_control |= R300_READ_ENABLE;
233
234 if (r300screen->caps.is_r500) {
235 /* Optimization: Depending on incoming pixels, we can
236 * conditionally disable the reading in hardware... */
237 if (eqRGB != PIPE_BLEND_MIN && eqA != PIPE_BLEND_MIN &&
238 eqRGB != PIPE_BLEND_MAX && eqA != PIPE_BLEND_MAX) {
239 /* Disable reading if SRC_ALPHA == 0. */
240 if ((dstRGB == PIPE_BLENDFACTOR_SRC_ALPHA ||
241 dstRGB == PIPE_BLENDFACTOR_ZERO) &&
242 (dstA == PIPE_BLENDFACTOR_SRC_COLOR ||
243 dstA == PIPE_BLENDFACTOR_SRC_ALPHA ||
244 dstA == PIPE_BLENDFACTOR_ZERO)) {
245 blend_control |= R500_SRC_ALPHA_0_NO_READ;
246 }
247
248 /* Disable reading if SRC_ALPHA == 1. */
249 if ((dstRGB == PIPE_BLENDFACTOR_INV_SRC_ALPHA ||
250 dstRGB == PIPE_BLENDFACTOR_ZERO) &&
251 (dstA == PIPE_BLENDFACTOR_INV_SRC_COLOR ||
252 dstA == PIPE_BLENDFACTOR_INV_SRC_ALPHA ||
253 dstA == PIPE_BLENDFACTOR_ZERO)) {
254 blend_control |= R500_SRC_ALPHA_1_NO_READ;
255 }
256 }
257 }
258 }
259
260 /* Optimization: discard pixels which don't change the colorbuffer.
261 *
262 * The code below is non-trivial and some math is involved.
263 *
264 * Discarding pixels must be disabled when FP16 AA is enabled.
265 * This is a hardware bug. Also, this implementation wouldn't work
266 * with FP blending enabled and equation clamping disabled.
267 *
268 * Equations other than ADD are rarely used and therefore won't be
269 * optimized. */
270 if ((eqRGB == PIPE_BLEND_ADD || eqRGB == PIPE_BLEND_REVERSE_SUBTRACT) &&
271 (eqA == PIPE_BLEND_ADD || eqA == PIPE_BLEND_REVERSE_SUBTRACT)) {
272 /* ADD: X+Y
273 * REVERSE_SUBTRACT: Y-X
274 *
275 * The idea is:
276 * If X = src*srcFactor = 0 and Y = dst*dstFactor = 1,
277 * then CB will not be changed.
278 *
279 * Given the srcFactor and dstFactor variables, we can derive
280 * what src and dst should be equal to and discard appropriate
281 * pixels.
282 */
283 if (blend_discard_if_src_alpha_0(srcRGB, srcA, dstRGB, dstA)) {
284 blend_control |= R300_DISCARD_SRC_PIXELS_SRC_ALPHA_0;
285 } else if (blend_discard_if_src_alpha_1(srcRGB, srcA,
286 dstRGB, dstA)) {
287 blend_control |= R300_DISCARD_SRC_PIXELS_SRC_ALPHA_1;
288 } else if (blend_discard_if_src_color_0(srcRGB, srcA,
289 dstRGB, dstA)) {
290 blend_control |= R300_DISCARD_SRC_PIXELS_SRC_COLOR_0;
291 } else if (blend_discard_if_src_color_1(srcRGB, srcA,
292 dstRGB, dstA)) {
293 blend_control |= R300_DISCARD_SRC_PIXELS_SRC_COLOR_1;
294 } else if (blend_discard_if_src_alpha_color_0(srcRGB, srcA,
295 dstRGB, dstA)) {
296 blend_control |=
297 R300_DISCARD_SRC_PIXELS_SRC_ALPHA_COLOR_0;
298 } else if (blend_discard_if_src_alpha_color_1(srcRGB, srcA,
299 dstRGB, dstA)) {
300 blend_control |=
301 R300_DISCARD_SRC_PIXELS_SRC_ALPHA_COLOR_1;
302 }
303 }
304
305 /* separate alpha */
306 if (srcA != srcRGB || dstA != dstRGB || eqA != eqRGB) {
307 blend_control |= R300_SEPARATE_ALPHA_ENABLE;
308 alpha_blend_control =
309 r300_translate_blend_function(eqA) |
310 (r300_translate_blend_factor(srcA) << R300_SRC_BLEND_SHIFT) |
311 (r300_translate_blend_factor(dstA) << R300_DST_BLEND_SHIFT);
312 }
313 }
314
315 /* PIPE_LOGICOP_* don't need to be translated, fortunately. */
316 if (state->logicop_enable) {
317 rop = R300_RB3D_ROPCNTL_ROP_ENABLE |
318 (state->logicop_func) << R300_RB3D_ROPCNTL_ROP_SHIFT;
319 }
320
321 /* Color channel masks for all MRTs. */
322 color_channel_mask = bgra_cmask(state->rt[0].colormask);
323 if (r300screen->caps.is_r500 && state->independent_blend_enable) {
324 if (state->rt[1].blend_enable) {
325 color_channel_mask |= bgra_cmask(state->rt[1].colormask) << 4;
326 }
327 if (state->rt[2].blend_enable) {
328 color_channel_mask |= bgra_cmask(state->rt[2].colormask) << 8;
329 }
330 if (state->rt[3].blend_enable) {
331 color_channel_mask |= bgra_cmask(state->rt[3].colormask) << 12;
332 }
333 }
334
335 /* Neither fglrx nor classic r300 ever set this, regardless of dithering
336 * state. Since it's an optional implementation detail, we can leave it
337 * out and never dither.
338 *
339 * This could be revisited if we ever get quality or conformance hints.
340 *
341 if (state->dither) {
342 dither = R300_RB3D_DITHER_CTL_DITHER_MODE_LUT |
343 R300_RB3D_DITHER_CTL_ALPHA_DITHER_MODE_LUT;
344 }
345 */
346
347 /* Build a command buffer. */
348 BEGIN_CB(blend->cb, 8);
349 OUT_CB_REG(R300_RB3D_ROPCNTL, rop);
350 OUT_CB_REG_SEQ(R300_RB3D_CBLEND, 3);
351 OUT_CB(blend_control);
352 OUT_CB(alpha_blend_control);
353 OUT_CB(color_channel_mask);
354 OUT_CB_REG(R300_RB3D_DITHER_CTL, dither);
355 END_CB;
356
357 /* The same as above, but with no colorbuffer reads and writes. */
358 BEGIN_CB(blend->cb_no_readwrite, 8);
359 OUT_CB_REG(R300_RB3D_ROPCNTL, rop);
360 OUT_CB_REG_SEQ(R300_RB3D_CBLEND, 3);
361 OUT_CB(0);
362 OUT_CB(0);
363 OUT_CB(0);
364 OUT_CB_REG(R300_RB3D_DITHER_CTL, dither);
365 END_CB;
366
367 return (void*)blend;
368 }
369
370 /* Bind blend state. */
371 static void r300_bind_blend_state(struct pipe_context* pipe,
372 void* state)
373 {
374 struct r300_context* r300 = r300_context(pipe);
375
376 UPDATE_STATE(state, r300->blend_state);
377 }
378
379 /* Free blend state. */
380 static void r300_delete_blend_state(struct pipe_context* pipe,
381 void* state)
382 {
383 FREE(state);
384 }
385
386 /* Convert float to 10bit integer */
387 static unsigned float_to_fixed10(float f)
388 {
389 return CLAMP((unsigned)(f * 1023.9f), 0, 1023);
390 }
391
392 /* Set blend color.
393 * Setup both R300 and R500 registers, figure out later which one to write. */
394 static void r300_set_blend_color(struct pipe_context* pipe,
395 const struct pipe_blend_color* color)
396 {
397 struct r300_context* r300 = r300_context(pipe);
398 struct r300_blend_color_state* state =
399 (struct r300_blend_color_state*)r300->blend_color_state.state;
400 CB_LOCALS;
401
402 if (r300->screen->caps.is_r500) {
403 /* XXX if FP16 blending is enabled, we should use the FP16 format */
404 BEGIN_CB(state->cb, 3);
405 OUT_CB_REG_SEQ(R500_RB3D_CONSTANT_COLOR_AR, 2);
406 OUT_CB(float_to_fixed10(color->color[0]) |
407 (float_to_fixed10(color->color[3]) << 16));
408 OUT_CB(float_to_fixed10(color->color[2]) |
409 (float_to_fixed10(color->color[1]) << 16));
410 END_CB;
411 } else {
412 union util_color uc;
413 util_pack_color(color->color, PIPE_FORMAT_B8G8R8A8_UNORM, &uc);
414
415 BEGIN_CB(state->cb, 2);
416 OUT_CB_REG(R300_RB3D_BLEND_COLOR, uc.ui);
417 END_CB;
418 }
419
420 r300_mark_atom_dirty(r300, &r300->blend_color_state);
421 }
422
423 static void r300_set_clip_state(struct pipe_context* pipe,
424 const struct pipe_clip_state* state)
425 {
426 struct r300_context* r300 = r300_context(pipe);
427 struct r300_clip_state *clip =
428 (struct r300_clip_state*)r300->clip_state.state;
429 CB_LOCALS;
430
431 clip->clip = *state;
432
433 if (r300->screen->caps.has_tcl) {
434 r300->clip_state.size = 2 + !!state->nr * 3 + state->nr * 4;
435
436 BEGIN_CB(clip->cb, r300->clip_state.size);
437 if (state->nr) {
438 OUT_CB_REG(R300_VAP_PVS_VECTOR_INDX_REG,
439 (r300->screen->caps.is_r500 ?
440 R500_PVS_UCP_START : R300_PVS_UCP_START));
441 OUT_CB_ONE_REG(R300_VAP_PVS_UPLOAD_DATA, state->nr * 4);
442 OUT_CB_TABLE(state->ucp, state->nr * 4);
443 }
444 OUT_CB_REG(R300_VAP_CLIP_CNTL, ((1 << state->nr) - 1) |
445 R300_PS_UCP_MODE_CLIP_AS_TRIFAN);
446 END_CB;
447
448 r300_mark_atom_dirty(r300, &r300->clip_state);
449 } else {
450 draw_set_clip_state(r300->draw, state);
451 }
452 }
453
454 static void
455 r300_set_sample_mask(struct pipe_context *pipe,
456 unsigned sample_mask)
457 {
458 }
459
460
461 /* Create a new depth, stencil, and alpha state based on the CSO dsa state.
462 *
463 * This contains the depth buffer, stencil buffer, alpha test, and such.
464 * On the Radeon, depth and stencil buffer setup are intertwined, which is
465 * the reason for some of the strange-looking assignments across registers. */
466 static void*
467 r300_create_dsa_state(struct pipe_context* pipe,
468 const struct pipe_depth_stencil_alpha_state* state)
469 {
470 struct r300_capabilities *caps = &r300_screen(pipe->screen)->caps;
471 struct r300_dsa_state* dsa = CALLOC_STRUCT(r300_dsa_state);
472 CB_LOCALS;
473
474 dsa->dsa = *state;
475
476 /* Depth test setup. - separate write mask depth for decomp flush */
477 if (state->depth.writemask) {
478 dsa->z_buffer_control |= R300_Z_WRITE_ENABLE;
479 }
480
481 if (state->depth.enabled) {
482 dsa->z_buffer_control |= R300_Z_ENABLE;
483
484 dsa->z_stencil_control |=
485 (r300_translate_depth_stencil_function(state->depth.func) <<
486 R300_Z_FUNC_SHIFT);
487 }
488
489 /* Stencil buffer setup. */
490 if (state->stencil[0].enabled) {
491 dsa->z_buffer_control |= R300_STENCIL_ENABLE;
492 dsa->z_stencil_control |=
493 (r300_translate_depth_stencil_function(state->stencil[0].func) <<
494 R300_S_FRONT_FUNC_SHIFT) |
495 (r300_translate_stencil_op(state->stencil[0].fail_op) <<
496 R300_S_FRONT_SFAIL_OP_SHIFT) |
497 (r300_translate_stencil_op(state->stencil[0].zpass_op) <<
498 R300_S_FRONT_ZPASS_OP_SHIFT) |
499 (r300_translate_stencil_op(state->stencil[0].zfail_op) <<
500 R300_S_FRONT_ZFAIL_OP_SHIFT);
501
502 dsa->stencil_ref_mask =
503 (state->stencil[0].valuemask << R300_STENCILMASK_SHIFT) |
504 (state->stencil[0].writemask << R300_STENCILWRITEMASK_SHIFT);
505
506 if (state->stencil[1].enabled) {
507 dsa->two_sided = TRUE;
508
509 dsa->z_buffer_control |= R300_STENCIL_FRONT_BACK;
510 dsa->z_stencil_control |=
511 (r300_translate_depth_stencil_function(state->stencil[1].func) <<
512 R300_S_BACK_FUNC_SHIFT) |
513 (r300_translate_stencil_op(state->stencil[1].fail_op) <<
514 R300_S_BACK_SFAIL_OP_SHIFT) |
515 (r300_translate_stencil_op(state->stencil[1].zpass_op) <<
516 R300_S_BACK_ZPASS_OP_SHIFT) |
517 (r300_translate_stencil_op(state->stencil[1].zfail_op) <<
518 R300_S_BACK_ZFAIL_OP_SHIFT);
519
520 dsa->stencil_ref_bf =
521 (state->stencil[1].valuemask << R300_STENCILMASK_SHIFT) |
522 (state->stencil[1].writemask << R300_STENCILWRITEMASK_SHIFT);
523
524 if (caps->is_r500) {
525 dsa->z_buffer_control |= R500_STENCIL_REFMASK_FRONT_BACK;
526 } else {
527 dsa->two_sided_stencil_ref =
528 (state->stencil[0].valuemask != state->stencil[1].valuemask ||
529 state->stencil[0].writemask != state->stencil[1].writemask);
530 }
531 }
532 }
533
534 /* Alpha test setup. */
535 if (state->alpha.enabled) {
536 dsa->alpha_function =
537 r300_translate_alpha_function(state->alpha.func) |
538 R300_FG_ALPHA_FUNC_ENABLE;
539
540 /* We could use 10bit alpha ref but who needs that? */
541 dsa->alpha_function |= float_to_ubyte(state->alpha.ref_value);
542
543 if (caps->is_r500)
544 dsa->alpha_function |= R500_FG_ALPHA_FUNC_8BIT;
545 }
546
547 BEGIN_CB(&dsa->cb_begin, 8);
548 OUT_CB_REG(R300_FG_ALPHA_FUNC, dsa->alpha_function);
549 OUT_CB_REG_SEQ(R300_ZB_CNTL, 3);
550 OUT_CB(dsa->z_buffer_control);
551 OUT_CB(dsa->z_stencil_control);
552 OUT_CB(dsa->stencil_ref_mask);
553 OUT_CB_REG(R500_ZB_STENCILREFMASK_BF, dsa->stencil_ref_bf);
554 END_CB;
555
556 BEGIN_CB(dsa->cb_no_readwrite, 8);
557 OUT_CB_REG(R300_FG_ALPHA_FUNC, dsa->alpha_function);
558 OUT_CB_REG_SEQ(R300_ZB_CNTL, 3);
559 OUT_CB(0);
560 OUT_CB(0);
561 OUT_CB(0);
562 OUT_CB_REG(R500_ZB_STENCILREFMASK_BF, 0);
563 END_CB;
564
565 return (void*)dsa;
566 }
567
568 static void r300_dsa_inject_stencilref(struct r300_context *r300)
569 {
570 struct r300_dsa_state *dsa =
571 (struct r300_dsa_state*)r300->dsa_state.state;
572
573 if (!dsa)
574 return;
575
576 dsa->stencil_ref_mask =
577 (dsa->stencil_ref_mask & ~R300_STENCILREF_MASK) |
578 r300->stencil_ref.ref_value[0];
579 dsa->stencil_ref_bf =
580 (dsa->stencil_ref_bf & ~R300_STENCILREF_MASK) |
581 r300->stencil_ref.ref_value[1];
582 }
583
584 /* Bind DSA state. */
585 static void r300_bind_dsa_state(struct pipe_context* pipe,
586 void* state)
587 {
588 struct r300_context* r300 = r300_context(pipe);
589
590 if (!state) {
591 return;
592 }
593
594 UPDATE_STATE(state, r300->dsa_state);
595
596 r300_mark_atom_dirty(r300, &r300->hyperz_state); /* Will be updated before the emission. */
597 r300_dsa_inject_stencilref(r300);
598 }
599
600 /* Free DSA state. */
601 static void r300_delete_dsa_state(struct pipe_context* pipe,
602 void* state)
603 {
604 FREE(state);
605 }
606
607 static void r300_set_stencil_ref(struct pipe_context* pipe,
608 const struct pipe_stencil_ref* sr)
609 {
610 struct r300_context* r300 = r300_context(pipe);
611
612 r300->stencil_ref = *sr;
613
614 r300_dsa_inject_stencilref(r300);
615 r300_mark_atom_dirty(r300, &r300->dsa_state);
616 }
617
618 static void r300_tex_set_tiling_flags(struct r300_context *r300,
619 struct r300_resource *tex,
620 unsigned level)
621 {
622 /* Check if the macrotile flag needs to be changed.
623 * Skip changing the flags otherwise. */
624 if (tex->tex.macrotile[tex->surface_level] !=
625 tex->tex.macrotile[level]) {
626 r300->rws->buffer_set_tiling(tex->buf, r300->cs,
627 tex->tex.microtile, tex->tex.macrotile[level],
628 tex->tex.stride_in_bytes[0]);
629
630 tex->surface_level = level;
631 }
632 }
633
634 /* This switcheroo is needed just because of goddamned MACRO_SWITCH. */
635 static void r300_fb_set_tiling_flags(struct r300_context *r300,
636 const struct pipe_framebuffer_state *state)
637 {
638 unsigned i;
639
640 /* Set tiling flags for new surfaces. */
641 for (i = 0; i < state->nr_cbufs; i++) {
642 r300_tex_set_tiling_flags(r300,
643 r300_resource(state->cbufs[i]->texture),
644 state->cbufs[i]->u.tex.level);
645 }
646 if (state->zsbuf) {
647 r300_tex_set_tiling_flags(r300,
648 r300_resource(state->zsbuf->texture),
649 state->zsbuf->u.tex.level);
650 }
651 }
652
653 static void r300_print_fb_surf_info(struct pipe_surface *surf, unsigned index,
654 const char *binding)
655 {
656 struct pipe_resource *tex = surf->texture;
657 struct r300_resource *rtex = r300_resource(tex);
658
659 fprintf(stderr,
660 "r300: %s[%i] Dim: %ix%i, Firstlayer: %i, "
661 "Lastlayer: %i, Level: %i, Format: %s\n"
662
663 "r300: TEX: Macro: %s, Micro: %s, Pitch: %i, "
664 "Dim: %ix%ix%i, LastLevel: %i, Format: %s\n",
665
666 binding, index, surf->width, surf->height,
667 surf->u.tex.first_layer, surf->u.tex.last_layer, surf->u.tex.level,
668 util_format_short_name(surf->format),
669
670 rtex->tex.macrotile[0] ? "YES" : " NO",
671 rtex->tex.microtile ? "YES" : " NO",
672 rtex->tex.stride_in_pixels[0],
673 tex->width0, tex->height0, tex->depth0,
674 tex->last_level, util_format_short_name(tex->format));
675 }
676
677 void r300_mark_fb_state_dirty(struct r300_context *r300,
678 enum r300_fb_state_change change)
679 {
680 struct pipe_framebuffer_state *state = r300->fb_state.state;
681 boolean can_hyperz = r300->rws->get_value(r300->rws, R300_CAN_HYPERZ);
682
683 r300_mark_atom_dirty(r300, &r300->gpu_flush);
684 r300_mark_atom_dirty(r300, &r300->fb_state);
685
686 /* What is marked as dirty depends on the enum r300_fb_state_change. */
687 if (change == R300_CHANGED_FB_STATE) {
688 r300_mark_atom_dirty(r300, &r300->aa_state);
689 }
690
691 if (change == R300_CHANGED_FB_STATE ||
692 change == R300_CHANGED_HYPERZ_FLAG) {
693 r300_mark_atom_dirty(r300, &r300->hyperz_state);
694 }
695
696 if (change == R300_CHANGED_FB_STATE ||
697 change == R300_CHANGED_MULTIWRITE) {
698 r300_mark_atom_dirty(r300, &r300->fb_state_pipelined);
699 }
700
701 /* Now compute the fb_state atom size. */
702 r300->fb_state.size = 2 + (8 * state->nr_cbufs);
703
704 if (r300->cbzb_clear)
705 r300->fb_state.size += 10;
706 else if (state->zsbuf) {
707 r300->fb_state.size += 10;
708 if (can_hyperz)
709 r300->fb_state.size += 8;
710 }
711
712 /* The size of the rest of atoms stays the same. */
713 }
714
715 static void
716 r300_set_framebuffer_state(struct pipe_context* pipe,
717 const struct pipe_framebuffer_state* state)
718 {
719 struct r300_context* r300 = r300_context(pipe);
720 struct r300_aa_state *aa = (struct r300_aa_state*)r300->aa_state.state;
721 struct pipe_framebuffer_state *old_state = r300->fb_state.state;
722 unsigned max_width, max_height, i;
723 uint32_t zbuffer_bpp = 0;
724
725 if (r300->screen->caps.is_r500) {
726 max_width = max_height = 4096;
727 } else if (r300->screen->caps.is_r400) {
728 max_width = max_height = 4021;
729 } else {
730 max_width = max_height = 2560;
731 }
732
733 if (state->width > max_width || state->height > max_height) {
734 fprintf(stderr, "r300: Implementation error: Render targets are too "
735 "big in %s, refusing to bind framebuffer state!\n", __FUNCTION__);
736 return;
737 }
738
739 if (old_state->zsbuf && r300->zmask_in_use && !r300->hyperz_locked) {
740 /* There is a zmask in use, what are we gonna do? */
741 if (state->zsbuf) {
742 if (!pipe_surface_equal(old_state->zsbuf, state->zsbuf)) {
743 /* Decompress the currently bound zbuffer before we bind another one. */
744 r300_decompress_zmask(r300);
745 r300->hiz_in_use = FALSE;
746 }
747 } else {
748 /* We don't bind another zbuffer, so lock the current one. */
749 r300->hyperz_locked = TRUE;
750 pipe_surface_reference(&r300->locked_zbuffer, old_state->zsbuf);
751 }
752 } else if (r300->hyperz_locked && r300->locked_zbuffer) {
753 /* We have a locked zbuffer now, what are we gonna do? */
754 if (state->zsbuf) {
755 if (!pipe_surface_equal(r300->locked_zbuffer, state->zsbuf)) {
756 /* We are binding some other zbuffer, so decompress the locked one,
757 * it gets unlocked automatically. */
758 r300_decompress_zmask_locked_unsafe(r300);
759 r300->hiz_in_use = FALSE;
760 } else {
761 /* We are binding the locked zbuffer again, so unlock it. */
762 r300->hyperz_locked = FALSE;
763 }
764 }
765 }
766
767 /* If nr_cbufs is changed from zero to non-zero or vice versa... */
768 if (!!old_state->nr_cbufs != !!state->nr_cbufs) {
769 r300_mark_atom_dirty(r300, &r300->blend_state);
770 }
771 /* If zsbuf is set from NULL to non-NULL or vice versa.. */
772 if (!!old_state->zsbuf != !!state->zsbuf) {
773 r300_mark_atom_dirty(r300, &r300->dsa_state);
774 }
775
776 /* The tiling flags are dependent on the surface miplevel, unfortunately. */
777 r300_fb_set_tiling_flags(r300, state);
778
779 util_copy_framebuffer_state(r300->fb_state.state, state);
780
781 if (!r300->hyperz_locked) {
782 pipe_surface_reference(&r300->locked_zbuffer, NULL);
783 }
784
785 r300_mark_fb_state_dirty(r300, R300_CHANGED_FB_STATE);
786
787 if (state->zsbuf) {
788 switch (util_format_get_blocksize(state->zsbuf->texture->format)) {
789 case 2:
790 zbuffer_bpp = 16;
791 break;
792 case 4:
793 zbuffer_bpp = 24;
794 break;
795 }
796
797 /* Polygon offset depends on the zbuffer bit depth. */
798 if (r300->zbuffer_bpp != zbuffer_bpp) {
799 r300->zbuffer_bpp = zbuffer_bpp;
800
801 if (r300->polygon_offset_enabled)
802 r300_mark_atom_dirty(r300, &r300->rs_state);
803 }
804 }
805
806 /* Set up AA config. */
807 if (state->nr_cbufs && state->cbufs[0]->texture->nr_samples > 1) {
808 aa->aa_config = R300_GB_AA_CONFIG_AA_ENABLE;
809
810 switch (state->cbufs[0]->texture->nr_samples) {
811 case 2:
812 aa->aa_config |= R300_GB_AA_CONFIG_NUM_AA_SUBSAMPLES_2;
813 break;
814 case 3:
815 aa->aa_config |= R300_GB_AA_CONFIG_NUM_AA_SUBSAMPLES_3;
816 break;
817 case 4:
818 aa->aa_config |= R300_GB_AA_CONFIG_NUM_AA_SUBSAMPLES_4;
819 break;
820 case 6:
821 aa->aa_config |= R300_GB_AA_CONFIG_NUM_AA_SUBSAMPLES_6;
822 break;
823 }
824 } else {
825 aa->aa_config = 0;
826 }
827
828 if (DBG_ON(r300, DBG_FB)) {
829 fprintf(stderr, "r300: set_framebuffer_state:\n");
830 for (i = 0; i < state->nr_cbufs; i++) {
831 r300_print_fb_surf_info(state->cbufs[i], i, "CB");
832 }
833 if (state->zsbuf) {
834 r300_print_fb_surf_info(state->zsbuf, 0, "ZB");
835 }
836 }
837 }
838
839 /* Create fragment shader state. */
840 static void* r300_create_fs_state(struct pipe_context* pipe,
841 const struct pipe_shader_state* shader)
842 {
843 struct r300_fragment_shader* fs = NULL;
844
845 fs = (struct r300_fragment_shader*)CALLOC_STRUCT(r300_fragment_shader);
846
847 /* Copy state directly into shader. */
848 fs->state = *shader;
849 fs->state.tokens = tgsi_dup_tokens(shader->tokens);
850
851 return (void*)fs;
852 }
853
854 void r300_mark_fs_code_dirty(struct r300_context *r300)
855 {
856 struct r300_fragment_shader* fs = r300_fs(r300);
857
858 r300_mark_atom_dirty(r300, &r300->fs);
859 r300_mark_atom_dirty(r300, &r300->fs_rc_constant_state);
860 r300_mark_atom_dirty(r300, &r300->fs_constants);
861 r300->fs.size = fs->shader->cb_code_size;
862
863 if (r300->screen->caps.is_r500) {
864 r300->fs_rc_constant_state.size = fs->shader->rc_state_count * 7;
865 r300->fs_constants.size = fs->shader->externals_count * 4 + 3;
866 } else {
867 r300->fs_rc_constant_state.size = fs->shader->rc_state_count * 5;
868 r300->fs_constants.size = fs->shader->externals_count * 4 + 1;
869 }
870
871 ((struct r300_constant_buffer*)r300->fs_constants.state)->remap_table =
872 fs->shader->code.constants_remap_table;
873 }
874
875 /* Bind fragment shader state. */
876 static void r300_bind_fs_state(struct pipe_context* pipe, void* shader)
877 {
878 struct r300_context* r300 = r300_context(pipe);
879 struct r300_fragment_shader* fs = (struct r300_fragment_shader*)shader;
880 struct pipe_framebuffer_state *fb = r300->fb_state.state;
881 boolean last_multi_write;
882
883 if (fs == NULL) {
884 r300->fs.state = NULL;
885 return;
886 }
887
888 last_multi_write = r300_fragment_shader_writes_all(r300_fs(r300));
889
890 r300->fs.state = fs;
891 r300_pick_fragment_shader(r300);
892 r300_mark_fs_code_dirty(r300);
893
894 if (fb->nr_cbufs > 1 &&
895 last_multi_write != r300_fragment_shader_writes_all(fs)) {
896 r300_mark_fb_state_dirty(r300, R300_CHANGED_MULTIWRITE);
897 }
898
899 r300_mark_atom_dirty(r300, &r300->rs_block_state); /* Will be updated before the emission. */
900 }
901
902 /* Delete fragment shader state. */
903 static void r300_delete_fs_state(struct pipe_context* pipe, void* shader)
904 {
905 struct r300_fragment_shader* fs = (struct r300_fragment_shader*)shader;
906 struct r300_fragment_shader_code *tmp, *ptr = fs->first;
907
908 while (ptr) {
909 tmp = ptr;
910 ptr = ptr->next;
911 rc_constants_destroy(&tmp->code.constants);
912 FREE(tmp->cb_code);
913 FREE(tmp);
914 }
915 FREE((void*)fs->state.tokens);
916 FREE(shader);
917 }
918
919 static void r300_set_polygon_stipple(struct pipe_context* pipe,
920 const struct pipe_poly_stipple* state)
921 {
922 /* XXX no idea how to set this up, but not terribly important */
923 }
924
925 /* Create a new rasterizer state based on the CSO rasterizer state.
926 *
927 * This is a very large chunk of state, and covers most of the graphics
928 * backend (GB), geometry assembly (GA), and setup unit (SU) blocks.
929 *
930 * In a not entirely unironic sidenote, this state has nearly nothing to do
931 * with the actual block on the Radeon called the rasterizer (RS). */
932 static void* r300_create_rs_state(struct pipe_context* pipe,
933 const struct pipe_rasterizer_state* state)
934 {
935 struct r300_rs_state* rs = CALLOC_STRUCT(r300_rs_state);
936 float psiz;
937 uint32_t vap_control_status; /* R300_VAP_CNTL_STATUS: 0x2140 */
938 uint32_t point_size; /* R300_GA_POINT_SIZE: 0x421c */
939 uint32_t point_minmax; /* R300_GA_POINT_MINMAX: 0x4230 */
940 uint32_t line_control; /* R300_GA_LINE_CNTL: 0x4234 */
941 uint32_t polygon_offset_enable; /* R300_SU_POLY_OFFSET_ENABLE: 0x42b4 */
942 uint32_t cull_mode; /* R300_SU_CULL_MODE: 0x42b8 */
943 uint32_t line_stipple_config; /* R300_GA_LINE_STIPPLE_CONFIG: 0x4328 */
944 uint32_t line_stipple_value; /* R300_GA_LINE_STIPPLE_VALUE: 0x4260 */
945 uint32_t polygon_mode; /* R300_GA_POLY_MODE: 0x4288 */
946 uint32_t clip_rule; /* R300_SC_CLIP_RULE: 0x43D0 */
947
948 /* Point sprites texture coordinates, 0: lower left, 1: upper right */
949 float point_texcoord_left = 0; /* R300_GA_POINT_S0: 0x4200 */
950 float point_texcoord_bottom = 0;/* R300_GA_POINT_T0: 0x4204 */
951 float point_texcoord_right = 1; /* R300_GA_POINT_S1: 0x4208 */
952 float point_texcoord_top = 0; /* R300_GA_POINT_T1: 0x420c */
953 CB_LOCALS;
954
955 /* Copy rasterizer state. */
956 rs->rs = *state;
957 rs->rs_draw = *state;
958
959 rs->rs.sprite_coord_enable = state->point_quad_rasterization *
960 state->sprite_coord_enable;
961
962 /* Override some states for Draw. */
963 rs->rs_draw.sprite_coord_enable = 0; /* We can do this in HW. */
964
965 #ifdef PIPE_ARCH_LITTLE_ENDIAN
966 vap_control_status = R300_VC_NO_SWAP;
967 #else
968 vap_control_status = R300_VC_32BIT_SWAP;
969 #endif
970
971 /* If no TCL engine is present, turn off the HW TCL. */
972 if (!r300_screen(pipe->screen)->caps.has_tcl) {
973 vap_control_status |= R300_VAP_TCL_BYPASS;
974 }
975
976 /* Point size width and height. */
977 point_size =
978 pack_float_16_6x(state->point_size) |
979 (pack_float_16_6x(state->point_size) << R300_POINTSIZE_X_SHIFT);
980
981 /* Point size clamping. */
982 if (state->point_size_per_vertex) {
983 /* Per-vertex point size.
984 * Clamp to [0, max FB size] */
985 psiz = pipe->screen->get_paramf(pipe->screen,
986 PIPE_CAP_MAX_POINT_WIDTH);
987 point_minmax =
988 pack_float_16_6x(psiz) << R300_GA_POINT_MINMAX_MAX_SHIFT;
989 } else {
990 /* We cannot disable the point-size vertex output,
991 * so clamp it. */
992 psiz = state->point_size;
993 point_minmax =
994 (pack_float_16_6x(psiz) << R300_GA_POINT_MINMAX_MIN_SHIFT) |
995 (pack_float_16_6x(psiz) << R300_GA_POINT_MINMAX_MAX_SHIFT);
996 }
997
998 /* Line control. */
999 line_control = pack_float_16_6x(state->line_width) |
1000 R300_GA_LINE_CNTL_END_TYPE_COMP;
1001
1002 /* Enable polygon mode */
1003 polygon_mode = 0;
1004 if (state->fill_front != PIPE_POLYGON_MODE_FILL ||
1005 state->fill_back != PIPE_POLYGON_MODE_FILL) {
1006 polygon_mode = R300_GA_POLY_MODE_DUAL;
1007 }
1008
1009 /* Front face */
1010 if (state->front_ccw)
1011 cull_mode = R300_FRONT_FACE_CCW;
1012 else
1013 cull_mode = R300_FRONT_FACE_CW;
1014
1015 /* Polygon offset */
1016 polygon_offset_enable = 0;
1017 if (util_get_offset(state, state->fill_front)) {
1018 polygon_offset_enable |= R300_FRONT_ENABLE;
1019 }
1020 if (util_get_offset(state, state->fill_back)) {
1021 polygon_offset_enable |= R300_BACK_ENABLE;
1022 }
1023
1024 rs->polygon_offset_enable = polygon_offset_enable != 0;
1025
1026 /* Polygon mode */
1027 if (polygon_mode) {
1028 polygon_mode |=
1029 r300_translate_polygon_mode_front(state->fill_front);
1030 polygon_mode |=
1031 r300_translate_polygon_mode_back(state->fill_back);
1032 }
1033
1034 if (state->cull_face & PIPE_FACE_FRONT) {
1035 cull_mode |= R300_CULL_FRONT;
1036 }
1037 if (state->cull_face & PIPE_FACE_BACK) {
1038 cull_mode |= R300_CULL_BACK;
1039 }
1040
1041 if (state->line_stipple_enable) {
1042 line_stipple_config =
1043 R300_GA_LINE_STIPPLE_CONFIG_LINE_RESET_LINE |
1044 (fui((float)state->line_stipple_factor) &
1045 R300_GA_LINE_STIPPLE_CONFIG_STIPPLE_SCALE_MASK);
1046 /* XXX this might need to be scaled up */
1047 line_stipple_value = state->line_stipple_pattern;
1048 } else {
1049 line_stipple_config = 0;
1050 line_stipple_value = 0;
1051 }
1052
1053 if (state->flatshade) {
1054 rs->color_control = R300_SHADE_MODEL_FLAT;
1055 } else {
1056 rs->color_control = R300_SHADE_MODEL_SMOOTH;
1057 }
1058
1059 clip_rule = state->scissor ? 0xAAAA : 0xFFFF;
1060
1061 /* Point sprites coord mode */
1062 if (rs->rs.sprite_coord_enable) {
1063 switch (state->sprite_coord_mode) {
1064 case PIPE_SPRITE_COORD_UPPER_LEFT:
1065 point_texcoord_top = 0.0f;
1066 point_texcoord_bottom = 1.0f;
1067 break;
1068 case PIPE_SPRITE_COORD_LOWER_LEFT:
1069 point_texcoord_top = 1.0f;
1070 point_texcoord_bottom = 0.0f;
1071 break;
1072 }
1073 }
1074
1075 /* Build the main command buffer. */
1076 BEGIN_CB(rs->cb_main, RS_STATE_MAIN_SIZE);
1077 OUT_CB_REG(R300_VAP_CNTL_STATUS, vap_control_status);
1078 OUT_CB_REG(R300_GA_POINT_SIZE, point_size);
1079 OUT_CB_REG_SEQ(R300_GA_POINT_MINMAX, 2);
1080 OUT_CB(point_minmax);
1081 OUT_CB(line_control);
1082 OUT_CB_REG_SEQ(R300_SU_POLY_OFFSET_ENABLE, 2);
1083 OUT_CB(polygon_offset_enable);
1084 rs->cull_mode_index = 9;
1085 OUT_CB(cull_mode);
1086 OUT_CB_REG(R300_GA_LINE_STIPPLE_CONFIG, line_stipple_config);
1087 OUT_CB_REG(R300_GA_LINE_STIPPLE_VALUE, line_stipple_value);
1088 OUT_CB_REG(R300_GA_POLY_MODE, polygon_mode);
1089 OUT_CB_REG(R300_SC_CLIP_RULE, clip_rule);
1090 OUT_CB_REG_SEQ(R300_GA_POINT_S0, 4);
1091 OUT_CB_32F(point_texcoord_left);
1092 OUT_CB_32F(point_texcoord_bottom);
1093 OUT_CB_32F(point_texcoord_right);
1094 OUT_CB_32F(point_texcoord_top);
1095 END_CB;
1096
1097 /* Build the two command buffers for polygon offset setup. */
1098 if (polygon_offset_enable) {
1099 float scale = state->offset_scale * 12;
1100 float offset = state->offset_units * 4;
1101
1102 BEGIN_CB(rs->cb_poly_offset_zb16, 5);
1103 OUT_CB_REG_SEQ(R300_SU_POLY_OFFSET_FRONT_SCALE, 4);
1104 OUT_CB_32F(scale);
1105 OUT_CB_32F(offset);
1106 OUT_CB_32F(scale);
1107 OUT_CB_32F(offset);
1108 END_CB;
1109
1110 offset = state->offset_units * 2;
1111
1112 BEGIN_CB(rs->cb_poly_offset_zb24, 5);
1113 OUT_CB_REG_SEQ(R300_SU_POLY_OFFSET_FRONT_SCALE, 4);
1114 OUT_CB_32F(scale);
1115 OUT_CB_32F(offset);
1116 OUT_CB_32F(scale);
1117 OUT_CB_32F(offset);
1118 END_CB;
1119 }
1120
1121 return (void*)rs;
1122 }
1123
1124 /* Bind rasterizer state. */
1125 static void r300_bind_rs_state(struct pipe_context* pipe, void* state)
1126 {
1127 struct r300_context* r300 = r300_context(pipe);
1128 struct r300_rs_state* rs = (struct r300_rs_state*)state;
1129 int last_sprite_coord_enable = r300->sprite_coord_enable;
1130 boolean last_two_sided_color = r300->two_sided_color;
1131
1132 if (r300->draw && rs) {
1133 draw_set_rasterizer_state(r300->draw, &rs->rs_draw, state);
1134 }
1135
1136 if (rs) {
1137 r300->polygon_offset_enabled = rs->polygon_offset_enable;
1138 r300->sprite_coord_enable = rs->rs.sprite_coord_enable;
1139 r300->two_sided_color = rs->rs.light_twoside;
1140 } else {
1141 r300->polygon_offset_enabled = FALSE;
1142 r300->sprite_coord_enable = 0;
1143 r300->two_sided_color = FALSE;
1144 }
1145
1146 UPDATE_STATE(state, r300->rs_state);
1147 r300->rs_state.size = RS_STATE_MAIN_SIZE + (r300->polygon_offset_enabled ? 5 : 0);
1148
1149 if (last_sprite_coord_enable != r300->sprite_coord_enable ||
1150 last_two_sided_color != r300->two_sided_color) {
1151 r300_mark_atom_dirty(r300, &r300->rs_block_state);
1152 }
1153 }
1154
1155 /* Free rasterizer state. */
1156 static void r300_delete_rs_state(struct pipe_context* pipe, void* state)
1157 {
1158 FREE(state);
1159 }
1160
1161 static void*
1162 r300_create_sampler_state(struct pipe_context* pipe,
1163 const struct pipe_sampler_state* state)
1164 {
1165 struct r300_context* r300 = r300_context(pipe);
1166 struct r300_sampler_state* sampler = CALLOC_STRUCT(r300_sampler_state);
1167 boolean is_r500 = r300->screen->caps.is_r500;
1168 int lod_bias;
1169
1170 sampler->state = *state;
1171
1172 /* r300 doesn't handle CLAMP and MIRROR_CLAMP correctly when either MAG
1173 * or MIN filter is NEAREST. Since texwrap produces same results
1174 * for CLAMP and CLAMP_TO_EDGE, we use them instead. */
1175 if (sampler->state.min_img_filter == PIPE_TEX_FILTER_NEAREST ||
1176 sampler->state.mag_img_filter == PIPE_TEX_FILTER_NEAREST) {
1177 /* Wrap S. */
1178 if (sampler->state.wrap_s == PIPE_TEX_WRAP_CLAMP)
1179 sampler->state.wrap_s = PIPE_TEX_WRAP_CLAMP_TO_EDGE;
1180 else if (sampler->state.wrap_s == PIPE_TEX_WRAP_MIRROR_CLAMP)
1181 sampler->state.wrap_s = PIPE_TEX_WRAP_MIRROR_CLAMP_TO_EDGE;
1182
1183 /* Wrap T. */
1184 if (sampler->state.wrap_t == PIPE_TEX_WRAP_CLAMP)
1185 sampler->state.wrap_t = PIPE_TEX_WRAP_CLAMP_TO_EDGE;
1186 else if (sampler->state.wrap_t == PIPE_TEX_WRAP_MIRROR_CLAMP)
1187 sampler->state.wrap_t = PIPE_TEX_WRAP_MIRROR_CLAMP_TO_EDGE;
1188
1189 /* Wrap R. */
1190 if (sampler->state.wrap_r == PIPE_TEX_WRAP_CLAMP)
1191 sampler->state.wrap_r = PIPE_TEX_WRAP_CLAMP_TO_EDGE;
1192 else if (sampler->state.wrap_r == PIPE_TEX_WRAP_MIRROR_CLAMP)
1193 sampler->state.wrap_r = PIPE_TEX_WRAP_MIRROR_CLAMP_TO_EDGE;
1194 }
1195
1196 sampler->filter0 |=
1197 (r300_translate_wrap(sampler->state.wrap_s) << R300_TX_WRAP_S_SHIFT) |
1198 (r300_translate_wrap(sampler->state.wrap_t) << R300_TX_WRAP_T_SHIFT) |
1199 (r300_translate_wrap(sampler->state.wrap_r) << R300_TX_WRAP_R_SHIFT);
1200
1201 sampler->filter0 |= r300_translate_tex_filters(state->min_img_filter,
1202 state->mag_img_filter,
1203 state->min_mip_filter,
1204 state->max_anisotropy > 0);
1205
1206 sampler->filter0 |= r300_anisotropy(state->max_anisotropy);
1207
1208 /* Unfortunately, r300-r500 don't support floating-point mipmap lods. */
1209 /* We must pass these to the merge function to clamp them properly. */
1210 sampler->min_lod = (unsigned)MAX2(state->min_lod, 0);
1211 sampler->max_lod = (unsigned)MAX2(ceilf(state->max_lod), 0);
1212
1213 lod_bias = CLAMP((int)(state->lod_bias * 32 + 1), -(1 << 9), (1 << 9) - 1);
1214
1215 sampler->filter1 |= (lod_bias << R300_LOD_BIAS_SHIFT) & R300_LOD_BIAS_MASK;
1216
1217 /* This is very high quality anisotropic filtering for R5xx.
1218 * It's good for benchmarking the performance of texturing but
1219 * in practice we don't want to slow down the driver because it's
1220 * a pretty good performance killer. Feel free to play with it. */
1221 if (DBG_ON(r300, DBG_ANISOHQ) && is_r500) {
1222 sampler->filter1 |= r500_anisotropy(state->max_anisotropy);
1223 }
1224
1225 /* R500-specific fixups and optimizations */
1226 if (r300->screen->caps.is_r500) {
1227 sampler->filter1 |= R500_BORDER_FIX;
1228 }
1229
1230 return (void*)sampler;
1231 }
1232
1233 static void r300_bind_sampler_states(struct pipe_context* pipe,
1234 unsigned count,
1235 void** states)
1236 {
1237 struct r300_context* r300 = r300_context(pipe);
1238 struct r300_textures_state* state =
1239 (struct r300_textures_state*)r300->textures_state.state;
1240 unsigned tex_units = r300->screen->caps.num_tex_units;
1241
1242 if (count > tex_units) {
1243 return;
1244 }
1245
1246 memcpy(state->sampler_states, states, sizeof(void*) * count);
1247 state->sampler_state_count = count;
1248
1249 r300_mark_atom_dirty(r300, &r300->textures_state);
1250 }
1251
1252 static void r300_lacks_vertex_textures(struct pipe_context* pipe,
1253 unsigned count,
1254 void** states)
1255 {
1256 }
1257
1258 static void r300_delete_sampler_state(struct pipe_context* pipe, void* state)
1259 {
1260 FREE(state);
1261 }
1262
1263 static uint32_t r300_assign_texture_cache_region(unsigned index, unsigned num)
1264 {
1265 /* This looks like a hack, but I believe it's suppose to work like
1266 * that. To illustrate how this works, let's assume you have 5 textures.
1267 * From docs, 5 and the successive numbers are:
1268 *
1269 * FOURTH_1 = 5
1270 * FOURTH_2 = 6
1271 * FOURTH_3 = 7
1272 * EIGHTH_0 = 8
1273 * EIGHTH_1 = 9
1274 *
1275 * First 3 textures will get 3/4 of size of the cache, divived evenly
1276 * between them. The last 1/4 of the cache must be divided between
1277 * the last 2 textures, each will therefore get 1/8 of the cache.
1278 * Why not just to use "5 + texture_index" ?
1279 *
1280 * This simple trick works for all "num" <= 16.
1281 */
1282 if (num <= 1)
1283 return R300_TX_CACHE(R300_TX_CACHE_WHOLE);
1284 else
1285 return R300_TX_CACHE(num + index);
1286 }
1287
1288 static void r300_set_fragment_sampler_views(struct pipe_context* pipe,
1289 unsigned count,
1290 struct pipe_sampler_view** views)
1291 {
1292 struct r300_context* r300 = r300_context(pipe);
1293 struct r300_textures_state* state =
1294 (struct r300_textures_state*)r300->textures_state.state;
1295 struct r300_resource *texture;
1296 unsigned i, real_num_views = 0, view_index = 0;
1297 unsigned tex_units = r300->screen->caps.num_tex_units;
1298 boolean dirty_tex = FALSE;
1299
1300 if (count > tex_units) {
1301 return;
1302 }
1303
1304 /* Calculate the real number of views. */
1305 for (i = 0; i < count; i++) {
1306 if (views[i])
1307 real_num_views++;
1308 }
1309
1310 for (i = 0; i < count; i++) {
1311 pipe_sampler_view_reference(
1312 (struct pipe_sampler_view**)&state->sampler_views[i],
1313 views[i]);
1314
1315 if (!views[i]) {
1316 continue;
1317 }
1318
1319 /* A new sampler view (= texture)... */
1320 dirty_tex = TRUE;
1321
1322 /* Set the texrect factor in the fragment shader.
1323 * Needed for RECT and NPOT fallback. */
1324 texture = r300_resource(views[i]->texture);
1325 if (texture->tex.is_npot) {
1326 r300_mark_atom_dirty(r300, &r300->fs_rc_constant_state);
1327 }
1328
1329 state->sampler_views[i]->texcache_region =
1330 r300_assign_texture_cache_region(view_index, real_num_views);
1331 view_index++;
1332 }
1333
1334 for (i = count; i < tex_units; i++) {
1335 if (state->sampler_views[i]) {
1336 pipe_sampler_view_reference(
1337 (struct pipe_sampler_view**)&state->sampler_views[i],
1338 NULL);
1339 }
1340 }
1341
1342 state->sampler_view_count = count;
1343
1344 r300_mark_atom_dirty(r300, &r300->textures_state);
1345
1346 if (dirty_tex) {
1347 r300_mark_atom_dirty(r300, &r300->texture_cache_inval);
1348 }
1349 }
1350
1351 static struct pipe_sampler_view *
1352 r300_create_sampler_view(struct pipe_context *pipe,
1353 struct pipe_resource *texture,
1354 const struct pipe_sampler_view *templ)
1355 {
1356 struct r300_sampler_view *view = CALLOC_STRUCT(r300_sampler_view);
1357 struct r300_resource *tex = r300_resource(texture);
1358 boolean is_r500 = r300_screen(pipe->screen)->caps.is_r500;
1359 boolean dxtc_swizzle = r300_screen(pipe->screen)->caps.dxtc_swizzle;
1360
1361 if (view) {
1362 view->base = *templ;
1363 view->base.reference.count = 1;
1364 view->base.context = pipe;
1365 view->base.texture = NULL;
1366 pipe_resource_reference(&view->base.texture, texture);
1367
1368 view->swizzle[0] = templ->swizzle_r;
1369 view->swizzle[1] = templ->swizzle_g;
1370 view->swizzle[2] = templ->swizzle_b;
1371 view->swizzle[3] = templ->swizzle_a;
1372
1373 view->format = tex->tx_format;
1374 view->format.format1 |= r300_translate_texformat(templ->format,
1375 view->swizzle,
1376 is_r500,
1377 dxtc_swizzle);
1378 if (is_r500) {
1379 view->format.format2 |= r500_tx_format_msb_bit(templ->format);
1380 }
1381 }
1382
1383 return (struct pipe_sampler_view*)view;
1384 }
1385
1386 static void
1387 r300_sampler_view_destroy(struct pipe_context *pipe,
1388 struct pipe_sampler_view *view)
1389 {
1390 pipe_resource_reference(&view->texture, NULL);
1391 FREE(view);
1392 }
1393
1394 static void r300_set_scissor_state(struct pipe_context* pipe,
1395 const struct pipe_scissor_state* state)
1396 {
1397 struct r300_context* r300 = r300_context(pipe);
1398
1399 memcpy(r300->scissor_state.state, state,
1400 sizeof(struct pipe_scissor_state));
1401
1402 r300_mark_atom_dirty(r300, &r300->scissor_state);
1403 }
1404
1405 static void r300_set_viewport_state(struct pipe_context* pipe,
1406 const struct pipe_viewport_state* state)
1407 {
1408 struct r300_context* r300 = r300_context(pipe);
1409 struct r300_viewport_state* viewport =
1410 (struct r300_viewport_state*)r300->viewport_state.state;
1411
1412 r300->viewport = *state;
1413
1414 if (r300->draw) {
1415 draw_set_viewport_state(r300->draw, state);
1416 viewport->vte_control = R300_VTX_XY_FMT | R300_VTX_Z_FMT;
1417 return;
1418 }
1419
1420 /* Do the transform in HW. */
1421 viewport->vte_control = R300_VTX_W0_FMT;
1422
1423 if (state->scale[0] != 1.0f) {
1424 viewport->xscale = state->scale[0];
1425 viewport->vte_control |= R300_VPORT_X_SCALE_ENA;
1426 }
1427 if (state->scale[1] != 1.0f) {
1428 viewport->yscale = state->scale[1];
1429 viewport->vte_control |= R300_VPORT_Y_SCALE_ENA;
1430 }
1431 if (state->scale[2] != 1.0f) {
1432 viewport->zscale = state->scale[2];
1433 viewport->vte_control |= R300_VPORT_Z_SCALE_ENA;
1434 }
1435 if (state->translate[0] != 0.0f) {
1436 viewport->xoffset = state->translate[0];
1437 viewport->vte_control |= R300_VPORT_X_OFFSET_ENA;
1438 }
1439 if (state->translate[1] != 0.0f) {
1440 viewport->yoffset = state->translate[1];
1441 viewport->vte_control |= R300_VPORT_Y_OFFSET_ENA;
1442 }
1443 if (state->translate[2] != 0.0f) {
1444 viewport->zoffset = state->translate[2];
1445 viewport->vte_control |= R300_VPORT_Z_OFFSET_ENA;
1446 }
1447
1448 r300_mark_atom_dirty(r300, &r300->viewport_state);
1449 if (r300->fs.state && r300_fs(r300)->shader->inputs.wpos != ATTR_UNUSED) {
1450 r300_mark_atom_dirty(r300, &r300->fs_rc_constant_state);
1451 }
1452 }
1453
1454 static void r300_set_vertex_buffers(struct pipe_context* pipe,
1455 unsigned count,
1456 const struct pipe_vertex_buffer* buffers)
1457 {
1458 struct r300_context* r300 = r300_context(pipe);
1459 unsigned i;
1460 struct pipe_vertex_buffer dummy_vb = {0};
1461
1462 /* There must be at least one vertex buffer set, otherwise it locks up. */
1463 if (!count) {
1464 dummy_vb.buffer = r300->dummy_vb;
1465 buffers = &dummy_vb;
1466 count = 1;
1467 }
1468
1469 u_vbuf_mgr_set_vertex_buffers(r300->vbuf_mgr, count, buffers);
1470
1471 if (r300->screen->caps.has_tcl) {
1472 /* HW TCL. */
1473 for (i = 0; i < count; i++) {
1474 if (buffers[i].buffer &&
1475 !r300_resource(buffers[i].buffer)->b.user_ptr) {
1476 }
1477 }
1478 r300->vertex_arrays_dirty = TRUE;
1479 } else {
1480 /* SW TCL. */
1481 draw_set_vertex_buffers(r300->draw, count, buffers);
1482 }
1483 }
1484
1485 static void r300_set_index_buffer(struct pipe_context* pipe,
1486 const struct pipe_index_buffer *ib)
1487 {
1488 struct r300_context* r300 = r300_context(pipe);
1489
1490 if (ib && ib->buffer) {
1491 assert(ib->offset % ib->index_size == 0);
1492
1493 pipe_resource_reference(&r300->index_buffer.buffer, ib->buffer);
1494 memcpy(&r300->index_buffer, ib, sizeof(r300->index_buffer));
1495 r300->index_buffer.offset /= r300->index_buffer.index_size;
1496 }
1497 else {
1498 pipe_resource_reference(&r300->index_buffer.buffer, NULL);
1499 memset(&r300->index_buffer, 0, sizeof(r300->index_buffer));
1500 }
1501
1502 if (!r300->screen->caps.has_tcl) {
1503 draw_set_index_buffer(r300->draw, ib);
1504 }
1505 }
1506
1507 /* Initialize the PSC tables. */
1508 static void r300_vertex_psc(struct r300_vertex_element_state *velems)
1509 {
1510 struct r300_vertex_stream_state *vstream = &velems->vertex_stream;
1511 uint16_t type, swizzle;
1512 enum pipe_format format;
1513 unsigned i;
1514
1515 if (velems->count > 16) {
1516 fprintf(stderr, "r300: More than 16 vertex elements are not supported,"
1517 " requested %i, using 16.\n", velems->count);
1518 velems->count = 16;
1519 }
1520
1521 /* Vertex shaders have no semantics on their inputs,
1522 * so PSC should just route stuff based on the vertex elements,
1523 * and not on attrib information. */
1524 for (i = 0; i < velems->count; i++) {
1525 format = velems->velem[i].src_format;
1526
1527 type = r300_translate_vertex_data_type(format);
1528 if (type == R300_INVALID_FORMAT) {
1529 fprintf(stderr, "r300: Bad vertex format %s.\n",
1530 util_format_short_name(format));
1531 assert(0);
1532 abort();
1533 }
1534
1535 type |= i << R300_DST_VEC_LOC_SHIFT;
1536 swizzle = r300_translate_vertex_data_swizzle(format);
1537
1538 if (i & 1) {
1539 vstream->vap_prog_stream_cntl[i >> 1] |= type << 16;
1540 vstream->vap_prog_stream_cntl_ext[i >> 1] |= swizzle << 16;
1541 } else {
1542 vstream->vap_prog_stream_cntl[i >> 1] |= type;
1543 vstream->vap_prog_stream_cntl_ext[i >> 1] |= swizzle;
1544 }
1545 }
1546
1547 /* Set the last vector in the PSC. */
1548 if (i) {
1549 i -= 1;
1550 }
1551 vstream->vap_prog_stream_cntl[i >> 1] |=
1552 (R300_LAST_VEC << (i & 1 ? 16 : 0));
1553
1554 vstream->count = (i >> 1) + 1;
1555 }
1556
1557 static void* r300_create_vertex_elements_state(struct pipe_context* pipe,
1558 unsigned count,
1559 const struct pipe_vertex_element* attribs)
1560 {
1561 struct r300_context *r300 = r300_context(pipe);
1562 struct r300_vertex_element_state *velems;
1563 unsigned i;
1564 struct pipe_vertex_element dummy_attrib = {0};
1565
1566 /* R300 Programmable Stream Control (PSC) doesn't support 0 vertex elements. */
1567 if (!count) {
1568 dummy_attrib.src_format = PIPE_FORMAT_R8G8B8A8_UNORM;
1569 attribs = &dummy_attrib;
1570 count = 1;
1571 }
1572
1573 assert(count <= PIPE_MAX_ATTRIBS);
1574 velems = CALLOC_STRUCT(r300_vertex_element_state);
1575 if (!velems)
1576 return NULL;
1577
1578 velems->count = count;
1579 velems->vmgr_elements =
1580 u_vbuf_mgr_create_vertex_elements(r300->vbuf_mgr, count, attribs,
1581 velems->velem);
1582
1583 if (r300_screen(pipe->screen)->caps.has_tcl) {
1584 /* Setup PSC.
1585 * The unused components will be replaced by (..., 0, 1). */
1586 r300_vertex_psc(velems);
1587
1588 for (i = 0; i < count; i++) {
1589 velems->format_size[i] =
1590 align(util_format_get_blocksize(velems->velem[i].src_format), 4);
1591 velems->vertex_size_dwords += velems->format_size[i] / 4;
1592 }
1593 }
1594
1595 return velems;
1596 }
1597
1598 static void r300_bind_vertex_elements_state(struct pipe_context *pipe,
1599 void *state)
1600 {
1601 struct r300_context *r300 = r300_context(pipe);
1602 struct r300_vertex_element_state *velems = state;
1603
1604 if (velems == NULL) {
1605 return;
1606 }
1607
1608 r300->velems = velems;
1609
1610 u_vbuf_mgr_bind_vertex_elements(r300->vbuf_mgr, state, velems->vmgr_elements);
1611
1612 if (r300->draw) {
1613 draw_set_vertex_elements(r300->draw, velems->count, velems->velem);
1614 return;
1615 }
1616
1617 UPDATE_STATE(&velems->vertex_stream, r300->vertex_stream_state);
1618 r300->vertex_stream_state.size = (1 + velems->vertex_stream.count) * 2;
1619 r300->vertex_arrays_dirty = TRUE;
1620 }
1621
1622 static void r300_delete_vertex_elements_state(struct pipe_context *pipe, void *state)
1623 {
1624 struct r300_context *r300 = r300_context(pipe);
1625 struct r300_vertex_element_state *velems = state;
1626
1627 u_vbuf_mgr_destroy_vertex_elements(r300->vbuf_mgr, velems->vmgr_elements);
1628 FREE(state);
1629 }
1630
1631 static void* r300_create_vs_state(struct pipe_context* pipe,
1632 const struct pipe_shader_state* shader)
1633 {
1634 struct r300_context* r300 = r300_context(pipe);
1635 struct r300_vertex_shader* vs = CALLOC_STRUCT(r300_vertex_shader);
1636
1637 /* Copy state directly into shader. */
1638 vs->state = *shader;
1639 vs->state.tokens = tgsi_dup_tokens(shader->tokens);
1640
1641 if (r300->screen->caps.has_tcl) {
1642 r300_init_vs_outputs(vs);
1643 r300_translate_vertex_shader(r300, vs);
1644 } else {
1645 r300_draw_init_vertex_shader(r300->draw, vs);
1646 }
1647
1648 return vs;
1649 }
1650
1651 static void r300_bind_vs_state(struct pipe_context* pipe, void* shader)
1652 {
1653 struct r300_context* r300 = r300_context(pipe);
1654 struct r300_vertex_shader* vs = (struct r300_vertex_shader*)shader;
1655
1656 if (vs == NULL) {
1657 r300->vs_state.state = NULL;
1658 return;
1659 }
1660 if (vs == r300->vs_state.state) {
1661 return;
1662 }
1663 r300->vs_state.state = vs;
1664
1665 /* The majority of the RS block bits is dependent on the vertex shader. */
1666 r300_mark_atom_dirty(r300, &r300->rs_block_state); /* Will be updated before the emission. */
1667
1668 if (r300->screen->caps.has_tcl) {
1669 unsigned fc_op_dwords = r300->screen->caps.is_r500 ? 3 : 2;
1670 r300_mark_atom_dirty(r300, &r300->vs_state);
1671 r300->vs_state.size =
1672 vs->code.length + 9 +
1673 (vs->code.num_fc_ops ? vs->code.num_fc_ops * fc_op_dwords + 4 : 0);
1674
1675 r300_mark_atom_dirty(r300, &r300->vs_constants);
1676 r300->vs_constants.size =
1677 2 +
1678 (vs->externals_count ? vs->externals_count * 4 + 3 : 0) +
1679 (vs->immediates_count ? vs->immediates_count * 4 + 3 : 0);
1680
1681 ((struct r300_constant_buffer*)r300->vs_constants.state)->remap_table =
1682 vs->code.constants_remap_table;
1683
1684 r300_mark_atom_dirty(r300, &r300->pvs_flush);
1685 } else {
1686 draw_bind_vertex_shader(r300->draw,
1687 (struct draw_vertex_shader*)vs->draw_vs);
1688 }
1689 }
1690
1691 static void r300_delete_vs_state(struct pipe_context* pipe, void* shader)
1692 {
1693 struct r300_context* r300 = r300_context(pipe);
1694 struct r300_vertex_shader* vs = (struct r300_vertex_shader*)shader;
1695
1696 if (r300->screen->caps.has_tcl) {
1697 rc_constants_destroy(&vs->code.constants);
1698 if (vs->code.constants_remap_table)
1699 FREE(vs->code.constants_remap_table);
1700 } else {
1701 draw_delete_vertex_shader(r300->draw,
1702 (struct draw_vertex_shader*)vs->draw_vs);
1703 }
1704
1705 FREE((void*)vs->state.tokens);
1706 FREE(shader);
1707 }
1708
1709 static void r300_set_constant_buffer(struct pipe_context *pipe,
1710 uint shader, uint index,
1711 struct pipe_resource *buf)
1712 {
1713 struct r300_context* r300 = r300_context(pipe);
1714 struct r300_constant_buffer *cbuf;
1715 struct r300_resource *rbuf = r300_resource(buf);
1716 uint32_t *mapped;
1717
1718 switch (shader) {
1719 case PIPE_SHADER_VERTEX:
1720 cbuf = (struct r300_constant_buffer*)r300->vs_constants.state;
1721 break;
1722 case PIPE_SHADER_FRAGMENT:
1723 cbuf = (struct r300_constant_buffer*)r300->fs_constants.state;
1724 break;
1725 default:
1726 return;
1727 }
1728
1729 if (buf == NULL || buf->width0 == 0)
1730 return;
1731
1732 if (rbuf->b.user_ptr)
1733 mapped = (uint32_t*)rbuf->b.user_ptr;
1734 else if (rbuf->constant_buffer)
1735 mapped = (uint32_t*)rbuf->constant_buffer;
1736 else
1737 return;
1738
1739 if (shader == PIPE_SHADER_FRAGMENT ||
1740 (shader == PIPE_SHADER_VERTEX && r300->screen->caps.has_tcl)) {
1741 cbuf->ptr = mapped;
1742 }
1743
1744 if (shader == PIPE_SHADER_VERTEX) {
1745 if (r300->screen->caps.has_tcl) {
1746 struct r300_vertex_shader *vs =
1747 (struct r300_vertex_shader*)r300->vs_state.state;
1748
1749 if (!vs) {
1750 cbuf->buffer_base = 0;
1751 return;
1752 }
1753
1754 cbuf->buffer_base = r300->vs_const_base;
1755 r300->vs_const_base += vs->code.constants.Count;
1756 if (r300->vs_const_base > R500_MAX_PVS_CONST_VECS) {
1757 r300->vs_const_base = vs->code.constants.Count;
1758 cbuf->buffer_base = 0;
1759 r300_mark_atom_dirty(r300, &r300->pvs_flush);
1760 }
1761 r300_mark_atom_dirty(r300, &r300->vs_constants);
1762 } else if (r300->draw) {
1763 draw_set_mapped_constant_buffer(r300->draw, PIPE_SHADER_VERTEX,
1764 0, mapped, buf->width0);
1765 }
1766 } else if (shader == PIPE_SHADER_FRAGMENT) {
1767 r300_mark_atom_dirty(r300, &r300->fs_constants);
1768 }
1769 }
1770
1771 void r300_init_state_functions(struct r300_context* r300)
1772 {
1773 r300->context.create_blend_state = r300_create_blend_state;
1774 r300->context.bind_blend_state = r300_bind_blend_state;
1775 r300->context.delete_blend_state = r300_delete_blend_state;
1776
1777 r300->context.set_blend_color = r300_set_blend_color;
1778
1779 r300->context.set_clip_state = r300_set_clip_state;
1780 r300->context.set_sample_mask = r300_set_sample_mask;
1781
1782 r300->context.set_constant_buffer = r300_set_constant_buffer;
1783
1784 r300->context.create_depth_stencil_alpha_state = r300_create_dsa_state;
1785 r300->context.bind_depth_stencil_alpha_state = r300_bind_dsa_state;
1786 r300->context.delete_depth_stencil_alpha_state = r300_delete_dsa_state;
1787
1788 r300->context.set_stencil_ref = r300_set_stencil_ref;
1789
1790 r300->context.set_framebuffer_state = r300_set_framebuffer_state;
1791
1792 r300->context.create_fs_state = r300_create_fs_state;
1793 r300->context.bind_fs_state = r300_bind_fs_state;
1794 r300->context.delete_fs_state = r300_delete_fs_state;
1795
1796 r300->context.set_polygon_stipple = r300_set_polygon_stipple;
1797
1798 r300->context.create_rasterizer_state = r300_create_rs_state;
1799 r300->context.bind_rasterizer_state = r300_bind_rs_state;
1800 r300->context.delete_rasterizer_state = r300_delete_rs_state;
1801
1802 r300->context.create_sampler_state = r300_create_sampler_state;
1803 r300->context.bind_fragment_sampler_states = r300_bind_sampler_states;
1804 r300->context.bind_vertex_sampler_states = r300_lacks_vertex_textures;
1805 r300->context.delete_sampler_state = r300_delete_sampler_state;
1806
1807 r300->context.set_fragment_sampler_views = r300_set_fragment_sampler_views;
1808 r300->context.create_sampler_view = r300_create_sampler_view;
1809 r300->context.sampler_view_destroy = r300_sampler_view_destroy;
1810
1811 r300->context.set_scissor_state = r300_set_scissor_state;
1812
1813 r300->context.set_viewport_state = r300_set_viewport_state;
1814
1815 r300->context.set_vertex_buffers = r300_set_vertex_buffers;
1816 r300->context.set_index_buffer = r300_set_index_buffer;
1817 r300->context.redefine_user_buffer = u_default_redefine_user_buffer;
1818
1819 r300->context.create_vertex_elements_state = r300_create_vertex_elements_state;
1820 r300->context.bind_vertex_elements_state = r300_bind_vertex_elements_state;
1821 r300->context.delete_vertex_elements_state = r300_delete_vertex_elements_state;
1822
1823 r300->context.create_vs_state = r300_create_vs_state;
1824 r300->context.bind_vs_state = r300_bind_vs_state;
1825 r300->context.delete_vs_state = r300_delete_vs_state;
1826 }