r300g: fix HiZ memory size computation and deciding when to use HiZ
[mesa.git] / src / gallium / drivers / r300 / r300_state.c
1 /*
2 * Copyright 2008 Corbin Simpson <MostAwesomeDude@gmail.com>
3 * Copyright 2009 Marek Olšák <maraeo@gmail.com>
4 *
5 * Permission is hereby granted, free of charge, to any person obtaining a
6 * copy of this software and associated documentation files (the "Software"),
7 * to deal in the Software without restriction, including without limitation
8 * on the rights to use, copy, modify, merge, publish, distribute, sub
9 * license, and/or sell copies of the Software, and to permit persons to whom
10 * the Software is furnished to do so, subject to the following conditions:
11 *
12 * The above copyright notice and this permission notice (including the next
13 * paragraph) shall be included in all copies or substantial portions of the
14 * Software.
15 *
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
19 * THE AUTHOR(S) AND/OR THEIR SUPPLIERS BE LIABLE FOR ANY CLAIM,
20 * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
21 * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
22 * USE OR OTHER DEALINGS IN THE SOFTWARE. */
23
24 #include "draw/draw_context.h"
25
26 #include "util/u_framebuffer.h"
27 #include "util/u_math.h"
28 #include "util/u_mm.h"
29 #include "util/u_memory.h"
30 #include "util/u_pack_color.h"
31 #include "util/u_transfer.h"
32
33 #include "tgsi/tgsi_parse.h"
34
35 #include "pipe/p_config.h"
36
37 #include "r300_cb.h"
38 #include "r300_context.h"
39 #include "r300_emit.h"
40 #include "r300_reg.h"
41 #include "r300_screen.h"
42 #include "r300_screen_buffer.h"
43 #include "r300_state_inlines.h"
44 #include "r300_fs.h"
45 #include "r300_texture.h"
46 #include "r300_vs.h"
47 #include "r300_winsys.h"
48
49 /* r300_state: Functions used to intialize state context by translating
50 * Gallium state objects into semi-native r300 state objects. */
51
52 #define UPDATE_STATE(cso, atom) \
53 if (cso != atom.state) { \
54 atom.state = cso; \
55 r300_mark_atom_dirty(r300, &(atom)); \
56 }
57
58 static boolean blend_discard_if_src_alpha_0(unsigned srcRGB, unsigned srcA,
59 unsigned dstRGB, unsigned dstA)
60 {
61 /* If the blend equation is ADD or REVERSE_SUBTRACT,
62 * SRC_ALPHA == 0, and the following state is set, the colorbuffer
63 * will not be changed.
64 * Notice that the dst factors are the src factors inverted. */
65 return (srcRGB == PIPE_BLENDFACTOR_SRC_ALPHA ||
66 srcRGB == PIPE_BLENDFACTOR_SRC_ALPHA_SATURATE ||
67 srcRGB == PIPE_BLENDFACTOR_ZERO) &&
68 (srcA == PIPE_BLENDFACTOR_SRC_COLOR ||
69 srcA == PIPE_BLENDFACTOR_SRC_ALPHA ||
70 srcA == PIPE_BLENDFACTOR_SRC_ALPHA_SATURATE ||
71 srcA == PIPE_BLENDFACTOR_ZERO) &&
72 (dstRGB == PIPE_BLENDFACTOR_INV_SRC_ALPHA ||
73 dstRGB == PIPE_BLENDFACTOR_ONE) &&
74 (dstA == PIPE_BLENDFACTOR_INV_SRC_COLOR ||
75 dstA == PIPE_BLENDFACTOR_INV_SRC_ALPHA ||
76 dstA == PIPE_BLENDFACTOR_ONE);
77 }
78
79 static boolean blend_discard_if_src_alpha_1(unsigned srcRGB, unsigned srcA,
80 unsigned dstRGB, unsigned dstA)
81 {
82 /* If the blend equation is ADD or REVERSE_SUBTRACT,
83 * SRC_ALPHA == 1, and the following state is set, the colorbuffer
84 * will not be changed.
85 * Notice that the dst factors are the src factors inverted. */
86 return (srcRGB == PIPE_BLENDFACTOR_INV_SRC_ALPHA ||
87 srcRGB == PIPE_BLENDFACTOR_ZERO) &&
88 (srcA == PIPE_BLENDFACTOR_INV_SRC_COLOR ||
89 srcA == PIPE_BLENDFACTOR_INV_SRC_ALPHA ||
90 srcA == PIPE_BLENDFACTOR_ZERO) &&
91 (dstRGB == PIPE_BLENDFACTOR_SRC_ALPHA ||
92 dstRGB == PIPE_BLENDFACTOR_ONE) &&
93 (dstA == PIPE_BLENDFACTOR_SRC_COLOR ||
94 dstA == PIPE_BLENDFACTOR_SRC_ALPHA ||
95 dstA == PIPE_BLENDFACTOR_ONE);
96 }
97
98 static boolean blend_discard_if_src_color_0(unsigned srcRGB, unsigned srcA,
99 unsigned dstRGB, unsigned dstA)
100 {
101 /* If the blend equation is ADD or REVERSE_SUBTRACT,
102 * SRC_COLOR == (0,0,0), and the following state is set, the colorbuffer
103 * will not be changed.
104 * Notice that the dst factors are the src factors inverted. */
105 return (srcRGB == PIPE_BLENDFACTOR_SRC_COLOR ||
106 srcRGB == PIPE_BLENDFACTOR_ZERO) &&
107 (srcA == PIPE_BLENDFACTOR_ZERO) &&
108 (dstRGB == PIPE_BLENDFACTOR_INV_SRC_COLOR ||
109 dstRGB == PIPE_BLENDFACTOR_ONE) &&
110 (dstA == PIPE_BLENDFACTOR_ONE);
111 }
112
113 static boolean blend_discard_if_src_color_1(unsigned srcRGB, unsigned srcA,
114 unsigned dstRGB, unsigned dstA)
115 {
116 /* If the blend equation is ADD or REVERSE_SUBTRACT,
117 * SRC_COLOR == (1,1,1), and the following state is set, the colorbuffer
118 * will not be changed.
119 * Notice that the dst factors are the src factors inverted. */
120 return (srcRGB == PIPE_BLENDFACTOR_INV_SRC_COLOR ||
121 srcRGB == PIPE_BLENDFACTOR_ZERO) &&
122 (srcA == PIPE_BLENDFACTOR_ZERO) &&
123 (dstRGB == PIPE_BLENDFACTOR_SRC_COLOR ||
124 dstRGB == PIPE_BLENDFACTOR_ONE) &&
125 (dstA == PIPE_BLENDFACTOR_ONE);
126 }
127
128 static boolean blend_discard_if_src_alpha_color_0(unsigned srcRGB, unsigned srcA,
129 unsigned dstRGB, unsigned dstA)
130 {
131 /* If the blend equation is ADD or REVERSE_SUBTRACT,
132 * SRC_ALPHA_COLOR == (0,0,0,0), and the following state is set,
133 * the colorbuffer will not be changed.
134 * Notice that the dst factors are the src factors inverted. */
135 return (srcRGB == PIPE_BLENDFACTOR_SRC_COLOR ||
136 srcRGB == PIPE_BLENDFACTOR_SRC_ALPHA ||
137 srcRGB == PIPE_BLENDFACTOR_SRC_ALPHA_SATURATE ||
138 srcRGB == PIPE_BLENDFACTOR_ZERO) &&
139 (srcA == PIPE_BLENDFACTOR_SRC_COLOR ||
140 srcA == PIPE_BLENDFACTOR_SRC_ALPHA ||
141 srcA == PIPE_BLENDFACTOR_SRC_ALPHA_SATURATE ||
142 srcA == PIPE_BLENDFACTOR_ZERO) &&
143 (dstRGB == PIPE_BLENDFACTOR_INV_SRC_COLOR ||
144 dstRGB == PIPE_BLENDFACTOR_INV_SRC_ALPHA ||
145 dstRGB == PIPE_BLENDFACTOR_ONE) &&
146 (dstA == PIPE_BLENDFACTOR_INV_SRC_COLOR ||
147 dstA == PIPE_BLENDFACTOR_INV_SRC_ALPHA ||
148 dstA == PIPE_BLENDFACTOR_ONE);
149 }
150
151 static boolean blend_discard_if_src_alpha_color_1(unsigned srcRGB, unsigned srcA,
152 unsigned dstRGB, unsigned dstA)
153 {
154 /* If the blend equation is ADD or REVERSE_SUBTRACT,
155 * SRC_ALPHA_COLOR == (1,1,1,1), and the following state is set,
156 * the colorbuffer will not be changed.
157 * Notice that the dst factors are the src factors inverted. */
158 return (srcRGB == PIPE_BLENDFACTOR_INV_SRC_COLOR ||
159 srcRGB == PIPE_BLENDFACTOR_INV_SRC_ALPHA ||
160 srcRGB == PIPE_BLENDFACTOR_ZERO) &&
161 (srcA == PIPE_BLENDFACTOR_INV_SRC_COLOR ||
162 srcA == PIPE_BLENDFACTOR_INV_SRC_ALPHA ||
163 srcA == PIPE_BLENDFACTOR_ZERO) &&
164 (dstRGB == PIPE_BLENDFACTOR_SRC_COLOR ||
165 dstRGB == PIPE_BLENDFACTOR_SRC_ALPHA ||
166 dstRGB == PIPE_BLENDFACTOR_ONE) &&
167 (dstA == PIPE_BLENDFACTOR_SRC_COLOR ||
168 dstA == PIPE_BLENDFACTOR_SRC_ALPHA ||
169 dstA == PIPE_BLENDFACTOR_ONE);
170 }
171
172 static unsigned bgra_cmask(unsigned mask)
173 {
174 /* Gallium uses RGBA color ordering while R300 expects BGRA. */
175
176 return ((mask & PIPE_MASK_R) << 2) |
177 ((mask & PIPE_MASK_B) >> 2) |
178 (mask & (PIPE_MASK_G | PIPE_MASK_A));
179 }
180
181 /* Create a new blend state based on the CSO blend state.
182 *
183 * This encompasses alpha blending, logic/raster ops, and blend dithering. */
184 static void* r300_create_blend_state(struct pipe_context* pipe,
185 const struct pipe_blend_state* state)
186 {
187 struct r300_screen* r300screen = r300_screen(pipe->screen);
188 struct r300_blend_state* blend = CALLOC_STRUCT(r300_blend_state);
189 uint32_t blend_control = 0; /* R300_RB3D_CBLEND: 0x4e04 */
190 uint32_t alpha_blend_control = 0; /* R300_RB3D_ABLEND: 0x4e08 */
191 uint32_t color_channel_mask = 0; /* R300_RB3D_COLOR_CHANNEL_MASK: 0x4e0c */
192 uint32_t rop = 0; /* R300_RB3D_ROPCNTL: 0x4e18 */
193 uint32_t dither = 0; /* R300_RB3D_DITHER_CTL: 0x4e50 */
194 CB_LOCALS;
195
196 if (state->rt[0].blend_enable)
197 {
198 unsigned eqRGB = state->rt[0].rgb_func;
199 unsigned srcRGB = state->rt[0].rgb_src_factor;
200 unsigned dstRGB = state->rt[0].rgb_dst_factor;
201
202 unsigned eqA = state->rt[0].alpha_func;
203 unsigned srcA = state->rt[0].alpha_src_factor;
204 unsigned dstA = state->rt[0].alpha_dst_factor;
205
206 /* despite the name, ALPHA_BLEND_ENABLE has nothing to do with alpha,
207 * this is just the crappy D3D naming */
208 blend_control = R300_ALPHA_BLEND_ENABLE |
209 r300_translate_blend_function(eqRGB) |
210 ( r300_translate_blend_factor(srcRGB) << R300_SRC_BLEND_SHIFT) |
211 ( r300_translate_blend_factor(dstRGB) << R300_DST_BLEND_SHIFT);
212
213 /* Optimization: some operations do not require the destination color.
214 *
215 * When SRC_ALPHA_SATURATE is used, colorbuffer reads must be enabled,
216 * otherwise blending gives incorrect results. It seems to be
217 * a hardware bug. */
218 if (eqRGB == PIPE_BLEND_MIN || eqA == PIPE_BLEND_MIN ||
219 eqRGB == PIPE_BLEND_MAX || eqA == PIPE_BLEND_MAX ||
220 dstRGB != PIPE_BLENDFACTOR_ZERO ||
221 dstA != PIPE_BLENDFACTOR_ZERO ||
222 srcRGB == PIPE_BLENDFACTOR_DST_COLOR ||
223 srcRGB == PIPE_BLENDFACTOR_DST_ALPHA ||
224 srcRGB == PIPE_BLENDFACTOR_INV_DST_COLOR ||
225 srcRGB == PIPE_BLENDFACTOR_INV_DST_ALPHA ||
226 srcA == PIPE_BLENDFACTOR_DST_COLOR ||
227 srcA == PIPE_BLENDFACTOR_DST_ALPHA ||
228 srcA == PIPE_BLENDFACTOR_INV_DST_COLOR ||
229 srcA == PIPE_BLENDFACTOR_INV_DST_ALPHA ||
230 srcRGB == PIPE_BLENDFACTOR_SRC_ALPHA_SATURATE) {
231 /* Enable reading from the colorbuffer. */
232 blend_control |= R300_READ_ENABLE;
233
234 if (r300screen->caps.is_r500) {
235 /* Optimization: Depending on incoming pixels, we can
236 * conditionally disable the reading in hardware... */
237 if (eqRGB != PIPE_BLEND_MIN && eqA != PIPE_BLEND_MIN &&
238 eqRGB != PIPE_BLEND_MAX && eqA != PIPE_BLEND_MAX) {
239 /* Disable reading if SRC_ALPHA == 0. */
240 if ((dstRGB == PIPE_BLENDFACTOR_SRC_ALPHA ||
241 dstRGB == PIPE_BLENDFACTOR_ZERO) &&
242 (dstA == PIPE_BLENDFACTOR_SRC_COLOR ||
243 dstA == PIPE_BLENDFACTOR_SRC_ALPHA ||
244 dstA == PIPE_BLENDFACTOR_ZERO)) {
245 blend_control |= R500_SRC_ALPHA_0_NO_READ;
246 }
247
248 /* Disable reading if SRC_ALPHA == 1. */
249 if ((dstRGB == PIPE_BLENDFACTOR_INV_SRC_ALPHA ||
250 dstRGB == PIPE_BLENDFACTOR_ZERO) &&
251 (dstA == PIPE_BLENDFACTOR_INV_SRC_COLOR ||
252 dstA == PIPE_BLENDFACTOR_INV_SRC_ALPHA ||
253 dstA == PIPE_BLENDFACTOR_ZERO)) {
254 blend_control |= R500_SRC_ALPHA_1_NO_READ;
255 }
256 }
257 }
258 }
259
260 /* Optimization: discard pixels which don't change the colorbuffer.
261 *
262 * The code below is non-trivial and some math is involved.
263 *
264 * Discarding pixels must be disabled when FP16 AA is enabled.
265 * This is a hardware bug. Also, this implementation wouldn't work
266 * with FP blending enabled and equation clamping disabled.
267 *
268 * Equations other than ADD are rarely used and therefore won't be
269 * optimized. */
270 if ((eqRGB == PIPE_BLEND_ADD || eqRGB == PIPE_BLEND_REVERSE_SUBTRACT) &&
271 (eqA == PIPE_BLEND_ADD || eqA == PIPE_BLEND_REVERSE_SUBTRACT)) {
272 /* ADD: X+Y
273 * REVERSE_SUBTRACT: Y-X
274 *
275 * The idea is:
276 * If X = src*srcFactor = 0 and Y = dst*dstFactor = 1,
277 * then CB will not be changed.
278 *
279 * Given the srcFactor and dstFactor variables, we can derive
280 * what src and dst should be equal to and discard appropriate
281 * pixels.
282 */
283 if (blend_discard_if_src_alpha_0(srcRGB, srcA, dstRGB, dstA)) {
284 blend_control |= R300_DISCARD_SRC_PIXELS_SRC_ALPHA_0;
285 } else if (blend_discard_if_src_alpha_1(srcRGB, srcA,
286 dstRGB, dstA)) {
287 blend_control |= R300_DISCARD_SRC_PIXELS_SRC_ALPHA_1;
288 } else if (blend_discard_if_src_color_0(srcRGB, srcA,
289 dstRGB, dstA)) {
290 blend_control |= R300_DISCARD_SRC_PIXELS_SRC_COLOR_0;
291 } else if (blend_discard_if_src_color_1(srcRGB, srcA,
292 dstRGB, dstA)) {
293 blend_control |= R300_DISCARD_SRC_PIXELS_SRC_COLOR_1;
294 } else if (blend_discard_if_src_alpha_color_0(srcRGB, srcA,
295 dstRGB, dstA)) {
296 blend_control |=
297 R300_DISCARD_SRC_PIXELS_SRC_ALPHA_COLOR_0;
298 } else if (blend_discard_if_src_alpha_color_1(srcRGB, srcA,
299 dstRGB, dstA)) {
300 blend_control |=
301 R300_DISCARD_SRC_PIXELS_SRC_ALPHA_COLOR_1;
302 }
303 }
304
305 /* separate alpha */
306 if (srcA != srcRGB || dstA != dstRGB || eqA != eqRGB) {
307 blend_control |= R300_SEPARATE_ALPHA_ENABLE;
308 alpha_blend_control =
309 r300_translate_blend_function(eqA) |
310 (r300_translate_blend_factor(srcA) << R300_SRC_BLEND_SHIFT) |
311 (r300_translate_blend_factor(dstA) << R300_DST_BLEND_SHIFT);
312 }
313 }
314
315 /* PIPE_LOGICOP_* don't need to be translated, fortunately. */
316 if (state->logicop_enable) {
317 rop = R300_RB3D_ROPCNTL_ROP_ENABLE |
318 (state->logicop_func) << R300_RB3D_ROPCNTL_ROP_SHIFT;
319 }
320
321 /* Color channel masks for all MRTs. */
322 color_channel_mask = bgra_cmask(state->rt[0].colormask);
323 if (r300screen->caps.is_r500 && state->independent_blend_enable) {
324 if (state->rt[1].blend_enable) {
325 color_channel_mask |= bgra_cmask(state->rt[1].colormask) << 4;
326 }
327 if (state->rt[2].blend_enable) {
328 color_channel_mask |= bgra_cmask(state->rt[2].colormask) << 8;
329 }
330 if (state->rt[3].blend_enable) {
331 color_channel_mask |= bgra_cmask(state->rt[3].colormask) << 12;
332 }
333 }
334
335 /* Neither fglrx nor classic r300 ever set this, regardless of dithering
336 * state. Since it's an optional implementation detail, we can leave it
337 * out and never dither.
338 *
339 * This could be revisited if we ever get quality or conformance hints.
340 *
341 if (state->dither) {
342 dither = R300_RB3D_DITHER_CTL_DITHER_MODE_LUT |
343 R300_RB3D_DITHER_CTL_ALPHA_DITHER_MODE_LUT;
344 }
345 */
346
347 /* Build a command buffer. */
348 BEGIN_CB(blend->cb, 8);
349 OUT_CB_REG(R300_RB3D_ROPCNTL, rop);
350 OUT_CB_REG_SEQ(R300_RB3D_CBLEND, 3);
351 OUT_CB(blend_control);
352 OUT_CB(alpha_blend_control);
353 OUT_CB(color_channel_mask);
354 OUT_CB_REG(R300_RB3D_DITHER_CTL, dither);
355 END_CB;
356
357 /* The same as above, but with no colorbuffer reads and writes. */
358 BEGIN_CB(blend->cb_no_readwrite, 8);
359 OUT_CB_REG(R300_RB3D_ROPCNTL, rop);
360 OUT_CB_REG_SEQ(R300_RB3D_CBLEND, 3);
361 OUT_CB(0);
362 OUT_CB(0);
363 OUT_CB(0);
364 OUT_CB_REG(R300_RB3D_DITHER_CTL, dither);
365 END_CB;
366
367 return (void*)blend;
368 }
369
370 /* Bind blend state. */
371 static void r300_bind_blend_state(struct pipe_context* pipe,
372 void* state)
373 {
374 struct r300_context* r300 = r300_context(pipe);
375
376 UPDATE_STATE(state, r300->blend_state);
377 }
378
379 /* Free blend state. */
380 static void r300_delete_blend_state(struct pipe_context* pipe,
381 void* state)
382 {
383 FREE(state);
384 }
385
386 /* Convert float to 10bit integer */
387 static unsigned float_to_fixed10(float f)
388 {
389 return CLAMP((unsigned)(f * 1023.9f), 0, 1023);
390 }
391
392 /* Set blend color.
393 * Setup both R300 and R500 registers, figure out later which one to write. */
394 static void r300_set_blend_color(struct pipe_context* pipe,
395 const struct pipe_blend_color* color)
396 {
397 struct r300_context* r300 = r300_context(pipe);
398 struct r300_blend_color_state* state =
399 (struct r300_blend_color_state*)r300->blend_color_state.state;
400 CB_LOCALS;
401
402 if (r300->screen->caps.is_r500) {
403 /* XXX if FP16 blending is enabled, we should use the FP16 format */
404 BEGIN_CB(state->cb, 3);
405 OUT_CB_REG_SEQ(R500_RB3D_CONSTANT_COLOR_AR, 2);
406 OUT_CB(float_to_fixed10(color->color[0]) |
407 (float_to_fixed10(color->color[3]) << 16));
408 OUT_CB(float_to_fixed10(color->color[2]) |
409 (float_to_fixed10(color->color[1]) << 16));
410 END_CB;
411 } else {
412 union util_color uc;
413 util_pack_color(color->color, PIPE_FORMAT_B8G8R8A8_UNORM, &uc);
414
415 BEGIN_CB(state->cb, 2);
416 OUT_CB_REG(R300_RB3D_BLEND_COLOR, uc.ui);
417 END_CB;
418 }
419
420 r300_mark_atom_dirty(r300, &r300->blend_color_state);
421 }
422
423 static void r300_set_clip_state(struct pipe_context* pipe,
424 const struct pipe_clip_state* state)
425 {
426 struct r300_context* r300 = r300_context(pipe);
427 struct r300_clip_state *clip =
428 (struct r300_clip_state*)r300->clip_state.state;
429 CB_LOCALS;
430
431 clip->clip = *state;
432
433 if (r300->screen->caps.has_tcl) {
434 r300->clip_state.size = 2 + !!state->nr * 3 + state->nr * 4;
435
436 BEGIN_CB(clip->cb, r300->clip_state.size);
437 if (state->nr) {
438 OUT_CB_REG(R300_VAP_PVS_VECTOR_INDX_REG,
439 (r300->screen->caps.is_r500 ?
440 R500_PVS_UCP_START : R300_PVS_UCP_START));
441 OUT_CB_ONE_REG(R300_VAP_PVS_UPLOAD_DATA, state->nr * 4);
442 OUT_CB_TABLE(state->ucp, state->nr * 4);
443 }
444 OUT_CB_REG(R300_VAP_CLIP_CNTL, ((1 << state->nr) - 1) |
445 R300_PS_UCP_MODE_CLIP_AS_TRIFAN);
446 END_CB;
447
448 r300_mark_atom_dirty(r300, &r300->clip_state);
449 } else {
450 draw_set_clip_state(r300->draw, state);
451 }
452 }
453
454 static void
455 r300_set_sample_mask(struct pipe_context *pipe,
456 unsigned sample_mask)
457 {
458 }
459
460
461 /* Create a new depth, stencil, and alpha state based on the CSO dsa state.
462 *
463 * This contains the depth buffer, stencil buffer, alpha test, and such.
464 * On the Radeon, depth and stencil buffer setup are intertwined, which is
465 * the reason for some of the strange-looking assignments across registers. */
466 static void*
467 r300_create_dsa_state(struct pipe_context* pipe,
468 const struct pipe_depth_stencil_alpha_state* state)
469 {
470 struct r300_capabilities *caps = &r300_screen(pipe->screen)->caps;
471 struct r300_dsa_state* dsa = CALLOC_STRUCT(r300_dsa_state);
472 CB_LOCALS;
473
474 dsa->dsa = *state;
475
476 /* Depth test setup. - separate write mask depth for decomp flush */
477 if (state->depth.writemask) {
478 dsa->z_buffer_control |= R300_Z_WRITE_ENABLE;
479 }
480
481 if (state->depth.enabled) {
482 dsa->z_buffer_control |= R300_Z_ENABLE;
483
484 dsa->z_stencil_control |=
485 (r300_translate_depth_stencil_function(state->depth.func) <<
486 R300_Z_FUNC_SHIFT);
487 }
488
489 /* Stencil buffer setup. */
490 if (state->stencil[0].enabled) {
491 dsa->z_buffer_control |= R300_STENCIL_ENABLE;
492 dsa->z_stencil_control |=
493 (r300_translate_depth_stencil_function(state->stencil[0].func) <<
494 R300_S_FRONT_FUNC_SHIFT) |
495 (r300_translate_stencil_op(state->stencil[0].fail_op) <<
496 R300_S_FRONT_SFAIL_OP_SHIFT) |
497 (r300_translate_stencil_op(state->stencil[0].zpass_op) <<
498 R300_S_FRONT_ZPASS_OP_SHIFT) |
499 (r300_translate_stencil_op(state->stencil[0].zfail_op) <<
500 R300_S_FRONT_ZFAIL_OP_SHIFT);
501
502 dsa->stencil_ref_mask =
503 (state->stencil[0].valuemask << R300_STENCILMASK_SHIFT) |
504 (state->stencil[0].writemask << R300_STENCILWRITEMASK_SHIFT);
505
506 if (state->stencil[1].enabled) {
507 dsa->two_sided = TRUE;
508
509 dsa->z_buffer_control |= R300_STENCIL_FRONT_BACK;
510 dsa->z_stencil_control |=
511 (r300_translate_depth_stencil_function(state->stencil[1].func) <<
512 R300_S_BACK_FUNC_SHIFT) |
513 (r300_translate_stencil_op(state->stencil[1].fail_op) <<
514 R300_S_BACK_SFAIL_OP_SHIFT) |
515 (r300_translate_stencil_op(state->stencil[1].zpass_op) <<
516 R300_S_BACK_ZPASS_OP_SHIFT) |
517 (r300_translate_stencil_op(state->stencil[1].zfail_op) <<
518 R300_S_BACK_ZFAIL_OP_SHIFT);
519
520 dsa->stencil_ref_bf =
521 (state->stencil[1].valuemask << R300_STENCILMASK_SHIFT) |
522 (state->stencil[1].writemask << R300_STENCILWRITEMASK_SHIFT);
523
524 if (caps->is_r500) {
525 dsa->z_buffer_control |= R500_STENCIL_REFMASK_FRONT_BACK;
526 } else {
527 dsa->two_sided_stencil_ref =
528 (state->stencil[0].valuemask != state->stencil[1].valuemask ||
529 state->stencil[0].writemask != state->stencil[1].writemask);
530 }
531 }
532 }
533
534 /* Alpha test setup. */
535 if (state->alpha.enabled) {
536 dsa->alpha_function =
537 r300_translate_alpha_function(state->alpha.func) |
538 R300_FG_ALPHA_FUNC_ENABLE;
539
540 /* We could use 10bit alpha ref but who needs that? */
541 dsa->alpha_function |= float_to_ubyte(state->alpha.ref_value);
542
543 if (caps->is_r500)
544 dsa->alpha_function |= R500_FG_ALPHA_FUNC_8BIT;
545 }
546
547 BEGIN_CB(&dsa->cb_begin, 8);
548 OUT_CB_REG(R300_FG_ALPHA_FUNC, dsa->alpha_function);
549 OUT_CB_REG_SEQ(R300_ZB_CNTL, 3);
550 OUT_CB(dsa->z_buffer_control);
551 OUT_CB(dsa->z_stencil_control);
552 OUT_CB(dsa->stencil_ref_mask);
553 OUT_CB_REG(R500_ZB_STENCILREFMASK_BF, dsa->stencil_ref_bf);
554 END_CB;
555
556 BEGIN_CB(dsa->cb_no_readwrite, 8);
557 OUT_CB_REG(R300_FG_ALPHA_FUNC, dsa->alpha_function);
558 OUT_CB_REG_SEQ(R300_ZB_CNTL, 3);
559 OUT_CB(0);
560 OUT_CB(0);
561 OUT_CB(0);
562 OUT_CB_REG(R500_ZB_STENCILREFMASK_BF, 0);
563 END_CB;
564
565 return (void*)dsa;
566 }
567
568 static void r300_dsa_inject_stencilref(struct r300_context *r300)
569 {
570 struct r300_dsa_state *dsa =
571 (struct r300_dsa_state*)r300->dsa_state.state;
572
573 if (!dsa)
574 return;
575
576 dsa->stencil_ref_mask =
577 (dsa->stencil_ref_mask & ~R300_STENCILREF_MASK) |
578 r300->stencil_ref.ref_value[0];
579 dsa->stencil_ref_bf =
580 (dsa->stencil_ref_bf & ~R300_STENCILREF_MASK) |
581 r300->stencil_ref.ref_value[1];
582 }
583
584 /* Bind DSA state. */
585 static void r300_bind_dsa_state(struct pipe_context* pipe,
586 void* state)
587 {
588 struct r300_context* r300 = r300_context(pipe);
589
590 if (!state) {
591 return;
592 }
593
594 UPDATE_STATE(state, r300->dsa_state);
595
596 r300_mark_atom_dirty(r300, &r300->hyperz_state); /* Will be updated before the emission. */
597 r300_dsa_inject_stencilref(r300);
598 }
599
600 /* Free DSA state. */
601 static void r300_delete_dsa_state(struct pipe_context* pipe,
602 void* state)
603 {
604 FREE(state);
605 }
606
607 static void r300_set_stencil_ref(struct pipe_context* pipe,
608 const struct pipe_stencil_ref* sr)
609 {
610 struct r300_context* r300 = r300_context(pipe);
611
612 r300->stencil_ref = *sr;
613
614 r300_dsa_inject_stencilref(r300);
615 r300_mark_atom_dirty(r300, &r300->dsa_state);
616 }
617
618 static void r300_tex_set_tiling_flags(struct r300_context *r300,
619 struct r300_resource *tex,
620 unsigned level)
621 {
622 /* Check if the macrotile flag needs to be changed.
623 * Skip changing the flags otherwise. */
624 if (tex->tex.macrotile[tex->surface_level] !=
625 tex->tex.macrotile[level]) {
626 r300->rws->buffer_set_tiling(tex->buf, r300->cs,
627 tex->tex.microtile, tex->tex.macrotile[level],
628 tex->tex.stride_in_bytes[0]);
629
630 tex->surface_level = level;
631 }
632 }
633
634 /* This switcheroo is needed just because of goddamned MACRO_SWITCH. */
635 static void r300_fb_set_tiling_flags(struct r300_context *r300,
636 const struct pipe_framebuffer_state *state)
637 {
638 unsigned i;
639
640 /* Set tiling flags for new surfaces. */
641 for (i = 0; i < state->nr_cbufs; i++) {
642 r300_tex_set_tiling_flags(r300,
643 r300_resource(state->cbufs[i]->texture),
644 state->cbufs[i]->u.tex.level);
645 }
646 if (state->zsbuf) {
647 r300_tex_set_tiling_flags(r300,
648 r300_resource(state->zsbuf->texture),
649 state->zsbuf->u.tex.level);
650 }
651 }
652
653 static void r300_print_fb_surf_info(struct pipe_surface *surf, unsigned index,
654 const char *binding)
655 {
656 struct pipe_resource *tex = surf->texture;
657 struct r300_resource *rtex = r300_resource(tex);
658
659 fprintf(stderr,
660 "r300: %s[%i] Dim: %ix%i, Firstlayer: %i, "
661 "Lastlayer: %i, Level: %i, Format: %s\n"
662
663 "r300: TEX: Macro: %s, Micro: %s, Pitch: %i, "
664 "Dim: %ix%ix%i, LastLevel: %i, Format: %s\n",
665
666 binding, index, surf->width, surf->height,
667 surf->u.tex.first_layer, surf->u.tex.last_layer, surf->u.tex.level,
668 util_format_short_name(surf->format),
669
670 rtex->tex.macrotile[0] ? "YES" : " NO",
671 rtex->tex.microtile ? "YES" : " NO",
672 rtex->tex.stride_in_pixels[0],
673 tex->width0, tex->height0, tex->depth0,
674 tex->last_level, util_format_short_name(tex->format));
675 }
676
677 void r300_mark_fb_state_dirty(struct r300_context *r300,
678 enum r300_fb_state_change change)
679 {
680 struct pipe_framebuffer_state *state = r300->fb_state.state;
681 boolean can_hyperz = r300->rws->get_value(r300->rws, R300_CAN_HYPERZ);
682
683 r300_mark_atom_dirty(r300, &r300->gpu_flush);
684 r300_mark_atom_dirty(r300, &r300->fb_state);
685
686 /* What is marked as dirty depends on the enum r300_fb_state_change. */
687 if (change == R300_CHANGED_FB_STATE) {
688 r300_mark_atom_dirty(r300, &r300->aa_state);
689 }
690
691 if (change == R300_CHANGED_FB_STATE ||
692 change == R300_CHANGED_HYPERZ_FLAG) {
693 r300_mark_atom_dirty(r300, &r300->hyperz_state);
694 }
695
696 if (change == R300_CHANGED_FB_STATE ||
697 change == R300_CHANGED_MULTIWRITE) {
698 r300_mark_atom_dirty(r300, &r300->fb_state_pipelined);
699 }
700
701 /* Now compute the fb_state atom size. */
702 r300->fb_state.size = 2 + (8 * state->nr_cbufs);
703
704 if (r300->cbzb_clear)
705 r300->fb_state.size += 10;
706 else if (state->zsbuf) {
707 r300->fb_state.size += 10;
708 if (can_hyperz)
709 r300->fb_state.size += 8;
710 }
711
712 /* The size of the rest of atoms stays the same. */
713 }
714
715 static void
716 r300_set_framebuffer_state(struct pipe_context* pipe,
717 const struct pipe_framebuffer_state* state)
718 {
719 struct r300_context* r300 = r300_context(pipe);
720 struct r300_aa_state *aa = (struct r300_aa_state*)r300->aa_state.state;
721 struct pipe_framebuffer_state *old_state = r300->fb_state.state;
722 unsigned max_width, max_height, i;
723 uint32_t zbuffer_bpp = 0;
724
725 if (r300->screen->caps.is_r500) {
726 max_width = max_height = 4096;
727 } else if (r300->screen->caps.is_r400) {
728 max_width = max_height = 4021;
729 } else {
730 max_width = max_height = 2560;
731 }
732
733 if (state->width > max_width || state->height > max_height) {
734 fprintf(stderr, "r300: Implementation error: Render targets are too "
735 "big in %s, refusing to bind framebuffer state!\n", __FUNCTION__);
736 return;
737 }
738
739 if (old_state->zsbuf && r300->zmask_in_use && !r300->hyperz_locked) {
740 /* There is a zmask in use, what are we gonna do? */
741 if (state->zsbuf) {
742 if (!pipe_surface_equal(old_state->zsbuf, state->zsbuf)) {
743 /* Decompress the currently bound zbuffer before we bind another one. */
744 r300_decompress_zmask(r300);
745 r300->hiz_in_use = FALSE;
746 }
747 } else {
748 /* We don't bind another zbuffer, so lock the current one. */
749 r300->hyperz_locked = TRUE;
750 pipe_surface_reference(&r300->locked_zbuffer, old_state->zsbuf);
751 }
752 } else if (r300->hyperz_locked && r300->locked_zbuffer) {
753 /* We have a locked zbuffer now, what are we gonna do? */
754 if (state->zsbuf) {
755 if (!pipe_surface_equal(r300->locked_zbuffer, state->zsbuf)) {
756 /* We are binding some other zbuffer, so decompress the locked one,
757 * it gets unlocked automatically. */
758 r300_decompress_zmask_locked_unsafe(r300);
759 r300->hiz_in_use = FALSE;
760 } else {
761 /* We are binding the locked zbuffer again, so unlock it. */
762 r300->hyperz_locked = FALSE;
763 }
764 }
765 }
766
767 /* If nr_cbufs is changed from zero to non-zero or vice versa... */
768 if (!!old_state->nr_cbufs != !!state->nr_cbufs) {
769 r300_mark_atom_dirty(r300, &r300->blend_state);
770 }
771 /* If zsbuf is set from NULL to non-NULL or vice versa.. */
772 if (!!old_state->zsbuf != !!state->zsbuf) {
773 r300_mark_atom_dirty(r300, &r300->dsa_state);
774 }
775
776 /* The tiling flags are dependent on the surface miplevel, unfortunately. */
777 r300_fb_set_tiling_flags(r300, state);
778
779 util_copy_framebuffer_state(r300->fb_state.state, state);
780
781 if (!r300->hyperz_locked) {
782 pipe_surface_reference(&r300->locked_zbuffer, NULL);
783 }
784
785 r300_mark_fb_state_dirty(r300, R300_CHANGED_FB_STATE);
786
787 if (state->zsbuf) {
788 switch (util_format_get_blocksize(state->zsbuf->texture->format)) {
789 case 2:
790 zbuffer_bpp = 16;
791 break;
792 case 4:
793 zbuffer_bpp = 24;
794 break;
795 }
796
797 /* Polygon offset depends on the zbuffer bit depth. */
798 if (r300->zbuffer_bpp != zbuffer_bpp) {
799 r300->zbuffer_bpp = zbuffer_bpp;
800
801 if (r300->polygon_offset_enabled)
802 r300_mark_atom_dirty(r300, &r300->rs_state);
803 }
804 }
805
806 /* Set up AA config. */
807 if (r300->rws->get_value(r300->rws, R300_VID_DRM_2_3_0)) {
808 if (state->nr_cbufs && state->cbufs[0]->texture->nr_samples > 1) {
809 aa->aa_config = R300_GB_AA_CONFIG_AA_ENABLE;
810
811 switch (state->cbufs[0]->texture->nr_samples) {
812 case 2:
813 aa->aa_config |= R300_GB_AA_CONFIG_NUM_AA_SUBSAMPLES_2;
814 break;
815 case 3:
816 aa->aa_config |= R300_GB_AA_CONFIG_NUM_AA_SUBSAMPLES_3;
817 break;
818 case 4:
819 aa->aa_config |= R300_GB_AA_CONFIG_NUM_AA_SUBSAMPLES_4;
820 break;
821 case 6:
822 aa->aa_config |= R300_GB_AA_CONFIG_NUM_AA_SUBSAMPLES_6;
823 break;
824 }
825 } else {
826 aa->aa_config = 0;
827 }
828 }
829
830 if (DBG_ON(r300, DBG_FB)) {
831 fprintf(stderr, "r300: set_framebuffer_state:\n");
832 for (i = 0; i < state->nr_cbufs; i++) {
833 r300_print_fb_surf_info(state->cbufs[i], i, "CB");
834 }
835 if (state->zsbuf) {
836 r300_print_fb_surf_info(state->zsbuf, 0, "ZB");
837 }
838 }
839 }
840
841 /* Create fragment shader state. */
842 static void* r300_create_fs_state(struct pipe_context* pipe,
843 const struct pipe_shader_state* shader)
844 {
845 struct r300_fragment_shader* fs = NULL;
846
847 fs = (struct r300_fragment_shader*)CALLOC_STRUCT(r300_fragment_shader);
848
849 /* Copy state directly into shader. */
850 fs->state = *shader;
851 fs->state.tokens = tgsi_dup_tokens(shader->tokens);
852
853 return (void*)fs;
854 }
855
856 void r300_mark_fs_code_dirty(struct r300_context *r300)
857 {
858 struct r300_fragment_shader* fs = r300_fs(r300);
859
860 r300_mark_atom_dirty(r300, &r300->fs);
861 r300_mark_atom_dirty(r300, &r300->fs_rc_constant_state);
862 r300_mark_atom_dirty(r300, &r300->fs_constants);
863 r300->fs.size = fs->shader->cb_code_size;
864
865 if (r300->screen->caps.is_r500) {
866 r300->fs_rc_constant_state.size = fs->shader->rc_state_count * 7;
867 r300->fs_constants.size = fs->shader->externals_count * 4 + 3;
868 } else {
869 r300->fs_rc_constant_state.size = fs->shader->rc_state_count * 5;
870 r300->fs_constants.size = fs->shader->externals_count * 4 + 1;
871 }
872
873 ((struct r300_constant_buffer*)r300->fs_constants.state)->remap_table =
874 fs->shader->code.constants_remap_table;
875 }
876
877 /* Bind fragment shader state. */
878 static void r300_bind_fs_state(struct pipe_context* pipe, void* shader)
879 {
880 struct r300_context* r300 = r300_context(pipe);
881 struct r300_fragment_shader* fs = (struct r300_fragment_shader*)shader;
882 struct pipe_framebuffer_state *fb = r300->fb_state.state;
883 boolean last_multi_write;
884
885 if (fs == NULL) {
886 r300->fs.state = NULL;
887 return;
888 }
889
890 last_multi_write = r300_fragment_shader_writes_all(r300_fs(r300));
891
892 r300->fs.state = fs;
893 r300_pick_fragment_shader(r300);
894 r300_mark_fs_code_dirty(r300);
895
896 if (fb->nr_cbufs > 1 &&
897 last_multi_write != r300_fragment_shader_writes_all(fs)) {
898 r300_mark_fb_state_dirty(r300, R300_CHANGED_MULTIWRITE);
899 }
900
901 r300_mark_atom_dirty(r300, &r300->rs_block_state); /* Will be updated before the emission. */
902 }
903
904 /* Delete fragment shader state. */
905 static void r300_delete_fs_state(struct pipe_context* pipe, void* shader)
906 {
907 struct r300_fragment_shader* fs = (struct r300_fragment_shader*)shader;
908 struct r300_fragment_shader_code *tmp, *ptr = fs->first;
909
910 while (ptr) {
911 tmp = ptr;
912 ptr = ptr->next;
913 rc_constants_destroy(&tmp->code.constants);
914 FREE(tmp->cb_code);
915 FREE(tmp);
916 }
917 FREE((void*)fs->state.tokens);
918 FREE(shader);
919 }
920
921 static void r300_set_polygon_stipple(struct pipe_context* pipe,
922 const struct pipe_poly_stipple* state)
923 {
924 /* XXX no idea how to set this up, but not terribly important */
925 }
926
927 /* Create a new rasterizer state based on the CSO rasterizer state.
928 *
929 * This is a very large chunk of state, and covers most of the graphics
930 * backend (GB), geometry assembly (GA), and setup unit (SU) blocks.
931 *
932 * In a not entirely unironic sidenote, this state has nearly nothing to do
933 * with the actual block on the Radeon called the rasterizer (RS). */
934 static void* r300_create_rs_state(struct pipe_context* pipe,
935 const struct pipe_rasterizer_state* state)
936 {
937 struct r300_rs_state* rs = CALLOC_STRUCT(r300_rs_state);
938 float psiz;
939 uint32_t vap_control_status; /* R300_VAP_CNTL_STATUS: 0x2140 */
940 uint32_t point_size; /* R300_GA_POINT_SIZE: 0x421c */
941 uint32_t point_minmax; /* R300_GA_POINT_MINMAX: 0x4230 */
942 uint32_t line_control; /* R300_GA_LINE_CNTL: 0x4234 */
943 uint32_t polygon_offset_enable; /* R300_SU_POLY_OFFSET_ENABLE: 0x42b4 */
944 uint32_t cull_mode; /* R300_SU_CULL_MODE: 0x42b8 */
945 uint32_t line_stipple_config; /* R300_GA_LINE_STIPPLE_CONFIG: 0x4328 */
946 uint32_t line_stipple_value; /* R300_GA_LINE_STIPPLE_VALUE: 0x4260 */
947 uint32_t polygon_mode; /* R300_GA_POLY_MODE: 0x4288 */
948 uint32_t clip_rule; /* R300_SC_CLIP_RULE: 0x43D0 */
949
950 /* Point sprites texture coordinates, 0: lower left, 1: upper right */
951 float point_texcoord_left = 0; /* R300_GA_POINT_S0: 0x4200 */
952 float point_texcoord_bottom = 0;/* R300_GA_POINT_T0: 0x4204 */
953 float point_texcoord_right = 1; /* R300_GA_POINT_S1: 0x4208 */
954 float point_texcoord_top = 0; /* R300_GA_POINT_T1: 0x420c */
955 CB_LOCALS;
956
957 /* Copy rasterizer state. */
958 rs->rs = *state;
959 rs->rs_draw = *state;
960
961 rs->rs.sprite_coord_enable = state->point_quad_rasterization *
962 state->sprite_coord_enable;
963
964 /* Override some states for Draw. */
965 rs->rs_draw.sprite_coord_enable = 0; /* We can do this in HW. */
966
967 #ifdef PIPE_ARCH_LITTLE_ENDIAN
968 vap_control_status = R300_VC_NO_SWAP;
969 #else
970 vap_control_status = R300_VC_32BIT_SWAP;
971 #endif
972
973 /* If no TCL engine is present, turn off the HW TCL. */
974 if (!r300_screen(pipe->screen)->caps.has_tcl) {
975 vap_control_status |= R300_VAP_TCL_BYPASS;
976 }
977
978 /* Point size width and height. */
979 point_size =
980 pack_float_16_6x(state->point_size) |
981 (pack_float_16_6x(state->point_size) << R300_POINTSIZE_X_SHIFT);
982
983 /* Point size clamping. */
984 if (state->point_size_per_vertex) {
985 /* Per-vertex point size.
986 * Clamp to [0, max FB size] */
987 psiz = pipe->screen->get_paramf(pipe->screen,
988 PIPE_CAP_MAX_POINT_WIDTH);
989 point_minmax =
990 pack_float_16_6x(psiz) << R300_GA_POINT_MINMAX_MAX_SHIFT;
991 } else {
992 /* We cannot disable the point-size vertex output,
993 * so clamp it. */
994 psiz = state->point_size;
995 point_minmax =
996 (pack_float_16_6x(psiz) << R300_GA_POINT_MINMAX_MIN_SHIFT) |
997 (pack_float_16_6x(psiz) << R300_GA_POINT_MINMAX_MAX_SHIFT);
998 }
999
1000 /* Line control. */
1001 line_control = pack_float_16_6x(state->line_width) |
1002 R300_GA_LINE_CNTL_END_TYPE_COMP;
1003
1004 /* Enable polygon mode */
1005 polygon_mode = 0;
1006 if (state->fill_front != PIPE_POLYGON_MODE_FILL ||
1007 state->fill_back != PIPE_POLYGON_MODE_FILL) {
1008 polygon_mode = R300_GA_POLY_MODE_DUAL;
1009 }
1010
1011 /* Front face */
1012 if (state->front_ccw)
1013 cull_mode = R300_FRONT_FACE_CCW;
1014 else
1015 cull_mode = R300_FRONT_FACE_CW;
1016
1017 /* Polygon offset */
1018 polygon_offset_enable = 0;
1019 if (util_get_offset(state, state->fill_front)) {
1020 polygon_offset_enable |= R300_FRONT_ENABLE;
1021 }
1022 if (util_get_offset(state, state->fill_back)) {
1023 polygon_offset_enable |= R300_BACK_ENABLE;
1024 }
1025
1026 rs->polygon_offset_enable = polygon_offset_enable != 0;
1027
1028 /* Polygon mode */
1029 if (polygon_mode) {
1030 polygon_mode |=
1031 r300_translate_polygon_mode_front(state->fill_front);
1032 polygon_mode |=
1033 r300_translate_polygon_mode_back(state->fill_back);
1034 }
1035
1036 if (state->cull_face & PIPE_FACE_FRONT) {
1037 cull_mode |= R300_CULL_FRONT;
1038 }
1039 if (state->cull_face & PIPE_FACE_BACK) {
1040 cull_mode |= R300_CULL_BACK;
1041 }
1042
1043 if (state->line_stipple_enable) {
1044 line_stipple_config =
1045 R300_GA_LINE_STIPPLE_CONFIG_LINE_RESET_LINE |
1046 (fui((float)state->line_stipple_factor) &
1047 R300_GA_LINE_STIPPLE_CONFIG_STIPPLE_SCALE_MASK);
1048 /* XXX this might need to be scaled up */
1049 line_stipple_value = state->line_stipple_pattern;
1050 } else {
1051 line_stipple_config = 0;
1052 line_stipple_value = 0;
1053 }
1054
1055 if (state->flatshade) {
1056 rs->color_control = R300_SHADE_MODEL_FLAT;
1057 } else {
1058 rs->color_control = R300_SHADE_MODEL_SMOOTH;
1059 }
1060
1061 clip_rule = state->scissor ? 0xAAAA : 0xFFFF;
1062
1063 /* Point sprites coord mode */
1064 if (rs->rs.sprite_coord_enable) {
1065 switch (state->sprite_coord_mode) {
1066 case PIPE_SPRITE_COORD_UPPER_LEFT:
1067 point_texcoord_top = 0.0f;
1068 point_texcoord_bottom = 1.0f;
1069 break;
1070 case PIPE_SPRITE_COORD_LOWER_LEFT:
1071 point_texcoord_top = 1.0f;
1072 point_texcoord_bottom = 0.0f;
1073 break;
1074 }
1075 }
1076
1077 /* Build the main command buffer. */
1078 BEGIN_CB(rs->cb_main, RS_STATE_MAIN_SIZE);
1079 OUT_CB_REG(R300_VAP_CNTL_STATUS, vap_control_status);
1080 OUT_CB_REG(R300_GA_POINT_SIZE, point_size);
1081 OUT_CB_REG_SEQ(R300_GA_POINT_MINMAX, 2);
1082 OUT_CB(point_minmax);
1083 OUT_CB(line_control);
1084 OUT_CB_REG_SEQ(R300_SU_POLY_OFFSET_ENABLE, 2);
1085 OUT_CB(polygon_offset_enable);
1086 rs->cull_mode_index = 9;
1087 OUT_CB(cull_mode);
1088 OUT_CB_REG(R300_GA_LINE_STIPPLE_CONFIG, line_stipple_config);
1089 OUT_CB_REG(R300_GA_LINE_STIPPLE_VALUE, line_stipple_value);
1090 OUT_CB_REG(R300_GA_POLY_MODE, polygon_mode);
1091 OUT_CB_REG(R300_SC_CLIP_RULE, clip_rule);
1092 OUT_CB_REG_SEQ(R300_GA_POINT_S0, 4);
1093 OUT_CB_32F(point_texcoord_left);
1094 OUT_CB_32F(point_texcoord_bottom);
1095 OUT_CB_32F(point_texcoord_right);
1096 OUT_CB_32F(point_texcoord_top);
1097 END_CB;
1098
1099 /* Build the two command buffers for polygon offset setup. */
1100 if (polygon_offset_enable) {
1101 float scale = state->offset_scale * 12;
1102 float offset = state->offset_units * 4;
1103
1104 BEGIN_CB(rs->cb_poly_offset_zb16, 5);
1105 OUT_CB_REG_SEQ(R300_SU_POLY_OFFSET_FRONT_SCALE, 4);
1106 OUT_CB_32F(scale);
1107 OUT_CB_32F(offset);
1108 OUT_CB_32F(scale);
1109 OUT_CB_32F(offset);
1110 END_CB;
1111
1112 offset = state->offset_units * 2;
1113
1114 BEGIN_CB(rs->cb_poly_offset_zb24, 5);
1115 OUT_CB_REG_SEQ(R300_SU_POLY_OFFSET_FRONT_SCALE, 4);
1116 OUT_CB_32F(scale);
1117 OUT_CB_32F(offset);
1118 OUT_CB_32F(scale);
1119 OUT_CB_32F(offset);
1120 END_CB;
1121 }
1122
1123 return (void*)rs;
1124 }
1125
1126 /* Bind rasterizer state. */
1127 static void r300_bind_rs_state(struct pipe_context* pipe, void* state)
1128 {
1129 struct r300_context* r300 = r300_context(pipe);
1130 struct r300_rs_state* rs = (struct r300_rs_state*)state;
1131 int last_sprite_coord_enable = r300->sprite_coord_enable;
1132 boolean last_two_sided_color = r300->two_sided_color;
1133
1134 if (r300->draw && rs) {
1135 draw_set_rasterizer_state(r300->draw, &rs->rs_draw, state);
1136 }
1137
1138 if (rs) {
1139 r300->polygon_offset_enabled = rs->polygon_offset_enable;
1140 r300->sprite_coord_enable = rs->rs.sprite_coord_enable;
1141 r300->two_sided_color = rs->rs.light_twoside;
1142 } else {
1143 r300->polygon_offset_enabled = FALSE;
1144 r300->sprite_coord_enable = 0;
1145 r300->two_sided_color = FALSE;
1146 }
1147
1148 UPDATE_STATE(state, r300->rs_state);
1149 r300->rs_state.size = RS_STATE_MAIN_SIZE + (r300->polygon_offset_enabled ? 5 : 0);
1150
1151 if (last_sprite_coord_enable != r300->sprite_coord_enable ||
1152 last_two_sided_color != r300->two_sided_color) {
1153 r300_mark_atom_dirty(r300, &r300->rs_block_state);
1154 }
1155 }
1156
1157 /* Free rasterizer state. */
1158 static void r300_delete_rs_state(struct pipe_context* pipe, void* state)
1159 {
1160 FREE(state);
1161 }
1162
1163 static void*
1164 r300_create_sampler_state(struct pipe_context* pipe,
1165 const struct pipe_sampler_state* state)
1166 {
1167 struct r300_context* r300 = r300_context(pipe);
1168 struct r300_sampler_state* sampler = CALLOC_STRUCT(r300_sampler_state);
1169 boolean is_r500 = r300->screen->caps.is_r500;
1170 int lod_bias;
1171
1172 sampler->state = *state;
1173
1174 /* r300 doesn't handle CLAMP and MIRROR_CLAMP correctly when either MAG
1175 * or MIN filter is NEAREST. Since texwrap produces same results
1176 * for CLAMP and CLAMP_TO_EDGE, we use them instead. */
1177 if (sampler->state.min_img_filter == PIPE_TEX_FILTER_NEAREST ||
1178 sampler->state.mag_img_filter == PIPE_TEX_FILTER_NEAREST) {
1179 /* Wrap S. */
1180 if (sampler->state.wrap_s == PIPE_TEX_WRAP_CLAMP)
1181 sampler->state.wrap_s = PIPE_TEX_WRAP_CLAMP_TO_EDGE;
1182 else if (sampler->state.wrap_s == PIPE_TEX_WRAP_MIRROR_CLAMP)
1183 sampler->state.wrap_s = PIPE_TEX_WRAP_MIRROR_CLAMP_TO_EDGE;
1184
1185 /* Wrap T. */
1186 if (sampler->state.wrap_t == PIPE_TEX_WRAP_CLAMP)
1187 sampler->state.wrap_t = PIPE_TEX_WRAP_CLAMP_TO_EDGE;
1188 else if (sampler->state.wrap_t == PIPE_TEX_WRAP_MIRROR_CLAMP)
1189 sampler->state.wrap_t = PIPE_TEX_WRAP_MIRROR_CLAMP_TO_EDGE;
1190
1191 /* Wrap R. */
1192 if (sampler->state.wrap_r == PIPE_TEX_WRAP_CLAMP)
1193 sampler->state.wrap_r = PIPE_TEX_WRAP_CLAMP_TO_EDGE;
1194 else if (sampler->state.wrap_r == PIPE_TEX_WRAP_MIRROR_CLAMP)
1195 sampler->state.wrap_r = PIPE_TEX_WRAP_MIRROR_CLAMP_TO_EDGE;
1196 }
1197
1198 sampler->filter0 |=
1199 (r300_translate_wrap(sampler->state.wrap_s) << R300_TX_WRAP_S_SHIFT) |
1200 (r300_translate_wrap(sampler->state.wrap_t) << R300_TX_WRAP_T_SHIFT) |
1201 (r300_translate_wrap(sampler->state.wrap_r) << R300_TX_WRAP_R_SHIFT);
1202
1203 sampler->filter0 |= r300_translate_tex_filters(state->min_img_filter,
1204 state->mag_img_filter,
1205 state->min_mip_filter,
1206 state->max_anisotropy > 0);
1207
1208 sampler->filter0 |= r300_anisotropy(state->max_anisotropy);
1209
1210 /* Unfortunately, r300-r500 don't support floating-point mipmap lods. */
1211 /* We must pass these to the merge function to clamp them properly. */
1212 sampler->min_lod = (unsigned)MAX2(state->min_lod, 0);
1213 sampler->max_lod = (unsigned)MAX2(ceilf(state->max_lod), 0);
1214
1215 lod_bias = CLAMP((int)(state->lod_bias * 32 + 1), -(1 << 9), (1 << 9) - 1);
1216
1217 sampler->filter1 |= (lod_bias << R300_LOD_BIAS_SHIFT) & R300_LOD_BIAS_MASK;
1218
1219 /* This is very high quality anisotropic filtering for R5xx.
1220 * It's good for benchmarking the performance of texturing but
1221 * in practice we don't want to slow down the driver because it's
1222 * a pretty good performance killer. Feel free to play with it. */
1223 if (DBG_ON(r300, DBG_ANISOHQ) && is_r500) {
1224 sampler->filter1 |= r500_anisotropy(state->max_anisotropy);
1225 }
1226
1227 /* R500-specific fixups and optimizations */
1228 if (r300->screen->caps.is_r500) {
1229 sampler->filter1 |= R500_BORDER_FIX;
1230 }
1231
1232 return (void*)sampler;
1233 }
1234
1235 static void r300_bind_sampler_states(struct pipe_context* pipe,
1236 unsigned count,
1237 void** states)
1238 {
1239 struct r300_context* r300 = r300_context(pipe);
1240 struct r300_textures_state* state =
1241 (struct r300_textures_state*)r300->textures_state.state;
1242 unsigned tex_units = r300->screen->caps.num_tex_units;
1243
1244 if (count > tex_units) {
1245 return;
1246 }
1247
1248 memcpy(state->sampler_states, states, sizeof(void*) * count);
1249 state->sampler_state_count = count;
1250
1251 r300_mark_atom_dirty(r300, &r300->textures_state);
1252 }
1253
1254 static void r300_lacks_vertex_textures(struct pipe_context* pipe,
1255 unsigned count,
1256 void** states)
1257 {
1258 }
1259
1260 static void r300_delete_sampler_state(struct pipe_context* pipe, void* state)
1261 {
1262 FREE(state);
1263 }
1264
1265 static uint32_t r300_assign_texture_cache_region(unsigned index, unsigned num)
1266 {
1267 /* This looks like a hack, but I believe it's suppose to work like
1268 * that. To illustrate how this works, let's assume you have 5 textures.
1269 * From docs, 5 and the successive numbers are:
1270 *
1271 * FOURTH_1 = 5
1272 * FOURTH_2 = 6
1273 * FOURTH_3 = 7
1274 * EIGHTH_0 = 8
1275 * EIGHTH_1 = 9
1276 *
1277 * First 3 textures will get 3/4 of size of the cache, divived evenly
1278 * between them. The last 1/4 of the cache must be divided between
1279 * the last 2 textures, each will therefore get 1/8 of the cache.
1280 * Why not just to use "5 + texture_index" ?
1281 *
1282 * This simple trick works for all "num" <= 16.
1283 */
1284 if (num <= 1)
1285 return R300_TX_CACHE(R300_TX_CACHE_WHOLE);
1286 else
1287 return R300_TX_CACHE(num + index);
1288 }
1289
1290 static void r300_set_fragment_sampler_views(struct pipe_context* pipe,
1291 unsigned count,
1292 struct pipe_sampler_view** views)
1293 {
1294 struct r300_context* r300 = r300_context(pipe);
1295 struct r300_textures_state* state =
1296 (struct r300_textures_state*)r300->textures_state.state;
1297 struct r300_resource *texture;
1298 unsigned i, real_num_views = 0, view_index = 0;
1299 unsigned tex_units = r300->screen->caps.num_tex_units;
1300 boolean dirty_tex = FALSE;
1301
1302 if (count > tex_units) {
1303 return;
1304 }
1305
1306 /* Calculate the real number of views. */
1307 for (i = 0; i < count; i++) {
1308 if (views[i])
1309 real_num_views++;
1310 }
1311
1312 for (i = 0; i < count; i++) {
1313 pipe_sampler_view_reference(
1314 (struct pipe_sampler_view**)&state->sampler_views[i],
1315 views[i]);
1316
1317 if (!views[i]) {
1318 continue;
1319 }
1320
1321 /* A new sampler view (= texture)... */
1322 dirty_tex = TRUE;
1323
1324 /* Set the texrect factor in the fragment shader.
1325 * Needed for RECT and NPOT fallback. */
1326 texture = r300_resource(views[i]->texture);
1327 if (texture->tex.is_npot) {
1328 r300_mark_atom_dirty(r300, &r300->fs_rc_constant_state);
1329 }
1330
1331 state->sampler_views[i]->texcache_region =
1332 r300_assign_texture_cache_region(view_index, real_num_views);
1333 view_index++;
1334 }
1335
1336 for (i = count; i < tex_units; i++) {
1337 if (state->sampler_views[i]) {
1338 pipe_sampler_view_reference(
1339 (struct pipe_sampler_view**)&state->sampler_views[i],
1340 NULL);
1341 }
1342 }
1343
1344 state->sampler_view_count = count;
1345
1346 r300_mark_atom_dirty(r300, &r300->textures_state);
1347
1348 if (dirty_tex) {
1349 r300_mark_atom_dirty(r300, &r300->texture_cache_inval);
1350 }
1351 }
1352
1353 static struct pipe_sampler_view *
1354 r300_create_sampler_view(struct pipe_context *pipe,
1355 struct pipe_resource *texture,
1356 const struct pipe_sampler_view *templ)
1357 {
1358 struct r300_sampler_view *view = CALLOC_STRUCT(r300_sampler_view);
1359 struct r300_resource *tex = r300_resource(texture);
1360 boolean is_r500 = r300_screen(pipe->screen)->caps.is_r500;
1361 boolean dxtc_swizzle = r300_screen(pipe->screen)->caps.dxtc_swizzle;
1362
1363 if (view) {
1364 view->base = *templ;
1365 view->base.reference.count = 1;
1366 view->base.context = pipe;
1367 view->base.texture = NULL;
1368 pipe_resource_reference(&view->base.texture, texture);
1369
1370 view->swizzle[0] = templ->swizzle_r;
1371 view->swizzle[1] = templ->swizzle_g;
1372 view->swizzle[2] = templ->swizzle_b;
1373 view->swizzle[3] = templ->swizzle_a;
1374
1375 view->format = tex->tx_format;
1376 view->format.format1 |= r300_translate_texformat(templ->format,
1377 view->swizzle,
1378 is_r500,
1379 dxtc_swizzle);
1380 if (is_r500) {
1381 view->format.format2 |= r500_tx_format_msb_bit(templ->format);
1382 }
1383 }
1384
1385 return (struct pipe_sampler_view*)view;
1386 }
1387
1388 static void
1389 r300_sampler_view_destroy(struct pipe_context *pipe,
1390 struct pipe_sampler_view *view)
1391 {
1392 pipe_resource_reference(&view->texture, NULL);
1393 FREE(view);
1394 }
1395
1396 static void r300_set_scissor_state(struct pipe_context* pipe,
1397 const struct pipe_scissor_state* state)
1398 {
1399 struct r300_context* r300 = r300_context(pipe);
1400
1401 memcpy(r300->scissor_state.state, state,
1402 sizeof(struct pipe_scissor_state));
1403
1404 r300_mark_atom_dirty(r300, &r300->scissor_state);
1405 }
1406
1407 static void r300_set_viewport_state(struct pipe_context* pipe,
1408 const struct pipe_viewport_state* state)
1409 {
1410 struct r300_context* r300 = r300_context(pipe);
1411 struct r300_viewport_state* viewport =
1412 (struct r300_viewport_state*)r300->viewport_state.state;
1413
1414 r300->viewport = *state;
1415
1416 if (r300->draw) {
1417 draw_set_viewport_state(r300->draw, state);
1418 viewport->vte_control = R300_VTX_XY_FMT | R300_VTX_Z_FMT;
1419 return;
1420 }
1421
1422 /* Do the transform in HW. */
1423 viewport->vte_control = R300_VTX_W0_FMT;
1424
1425 if (state->scale[0] != 1.0f) {
1426 viewport->xscale = state->scale[0];
1427 viewport->vte_control |= R300_VPORT_X_SCALE_ENA;
1428 }
1429 if (state->scale[1] != 1.0f) {
1430 viewport->yscale = state->scale[1];
1431 viewport->vte_control |= R300_VPORT_Y_SCALE_ENA;
1432 }
1433 if (state->scale[2] != 1.0f) {
1434 viewport->zscale = state->scale[2];
1435 viewport->vte_control |= R300_VPORT_Z_SCALE_ENA;
1436 }
1437 if (state->translate[0] != 0.0f) {
1438 viewport->xoffset = state->translate[0];
1439 viewport->vte_control |= R300_VPORT_X_OFFSET_ENA;
1440 }
1441 if (state->translate[1] != 0.0f) {
1442 viewport->yoffset = state->translate[1];
1443 viewport->vte_control |= R300_VPORT_Y_OFFSET_ENA;
1444 }
1445 if (state->translate[2] != 0.0f) {
1446 viewport->zoffset = state->translate[2];
1447 viewport->vte_control |= R300_VPORT_Z_OFFSET_ENA;
1448 }
1449
1450 r300_mark_atom_dirty(r300, &r300->viewport_state);
1451 if (r300->fs.state && r300_fs(r300)->shader->inputs.wpos != ATTR_UNUSED) {
1452 r300_mark_atom_dirty(r300, &r300->fs_rc_constant_state);
1453 }
1454 }
1455
1456 static void r300_set_vertex_buffers(struct pipe_context* pipe,
1457 unsigned count,
1458 const struct pipe_vertex_buffer* buffers)
1459 {
1460 struct r300_context* r300 = r300_context(pipe);
1461 unsigned i;
1462 struct pipe_vertex_buffer dummy_vb = {0};
1463
1464 /* There must be at least one vertex buffer set, otherwise it locks up. */
1465 if (!count) {
1466 dummy_vb.buffer = r300->dummy_vb;
1467 buffers = &dummy_vb;
1468 count = 1;
1469 }
1470
1471 u_vbuf_mgr_set_vertex_buffers(r300->vbuf_mgr, count, buffers);
1472
1473 if (r300->screen->caps.has_tcl) {
1474 /* HW TCL. */
1475 for (i = 0; i < count; i++) {
1476 if (buffers[i].buffer &&
1477 !r300_resource(buffers[i].buffer)->b.user_ptr) {
1478 }
1479 }
1480 r300->vertex_arrays_dirty = TRUE;
1481 } else {
1482 /* SW TCL. */
1483 draw_set_vertex_buffers(r300->draw, count, buffers);
1484 }
1485 }
1486
1487 static void r300_set_index_buffer(struct pipe_context* pipe,
1488 const struct pipe_index_buffer *ib)
1489 {
1490 struct r300_context* r300 = r300_context(pipe);
1491
1492 if (ib && ib->buffer) {
1493 assert(ib->offset % ib->index_size == 0);
1494
1495 pipe_resource_reference(&r300->index_buffer.buffer, ib->buffer);
1496 memcpy(&r300->index_buffer, ib, sizeof(r300->index_buffer));
1497 r300->index_buffer.offset /= r300->index_buffer.index_size;
1498 }
1499 else {
1500 pipe_resource_reference(&r300->index_buffer.buffer, NULL);
1501 memset(&r300->index_buffer, 0, sizeof(r300->index_buffer));
1502 }
1503
1504 if (!r300->screen->caps.has_tcl) {
1505 draw_set_index_buffer(r300->draw, ib);
1506 }
1507 }
1508
1509 /* Initialize the PSC tables. */
1510 static void r300_vertex_psc(struct r300_vertex_element_state *velems)
1511 {
1512 struct r300_vertex_stream_state *vstream = &velems->vertex_stream;
1513 uint16_t type, swizzle;
1514 enum pipe_format format;
1515 unsigned i;
1516
1517 if (velems->count > 16) {
1518 fprintf(stderr, "r300: More than 16 vertex elements are not supported,"
1519 " requested %i, using 16.\n", velems->count);
1520 velems->count = 16;
1521 }
1522
1523 /* Vertex shaders have no semantics on their inputs,
1524 * so PSC should just route stuff based on the vertex elements,
1525 * and not on attrib information. */
1526 for (i = 0; i < velems->count; i++) {
1527 format = velems->velem[i].src_format;
1528
1529 type = r300_translate_vertex_data_type(format);
1530 if (type == R300_INVALID_FORMAT) {
1531 fprintf(stderr, "r300: Bad vertex format %s.\n",
1532 util_format_short_name(format));
1533 assert(0);
1534 abort();
1535 }
1536
1537 type |= i << R300_DST_VEC_LOC_SHIFT;
1538 swizzle = r300_translate_vertex_data_swizzle(format);
1539
1540 if (i & 1) {
1541 vstream->vap_prog_stream_cntl[i >> 1] |= type << 16;
1542 vstream->vap_prog_stream_cntl_ext[i >> 1] |= swizzle << 16;
1543 } else {
1544 vstream->vap_prog_stream_cntl[i >> 1] |= type;
1545 vstream->vap_prog_stream_cntl_ext[i >> 1] |= swizzle;
1546 }
1547 }
1548
1549 /* Set the last vector in the PSC. */
1550 if (i) {
1551 i -= 1;
1552 }
1553 vstream->vap_prog_stream_cntl[i >> 1] |=
1554 (R300_LAST_VEC << (i & 1 ? 16 : 0));
1555
1556 vstream->count = (i >> 1) + 1;
1557 }
1558
1559 static void* r300_create_vertex_elements_state(struct pipe_context* pipe,
1560 unsigned count,
1561 const struct pipe_vertex_element* attribs)
1562 {
1563 struct r300_context *r300 = r300_context(pipe);
1564 struct r300_vertex_element_state *velems;
1565 unsigned i;
1566 struct pipe_vertex_element dummy_attrib = {0};
1567
1568 /* R300 Programmable Stream Control (PSC) doesn't support 0 vertex elements. */
1569 if (!count) {
1570 dummy_attrib.src_format = PIPE_FORMAT_R8G8B8A8_UNORM;
1571 attribs = &dummy_attrib;
1572 count = 1;
1573 }
1574
1575 assert(count <= PIPE_MAX_ATTRIBS);
1576 velems = CALLOC_STRUCT(r300_vertex_element_state);
1577 if (!velems)
1578 return NULL;
1579
1580 velems->count = count;
1581 velems->vmgr_elements =
1582 u_vbuf_mgr_create_vertex_elements(r300->vbuf_mgr, count, attribs,
1583 velems->velem);
1584
1585 if (r300_screen(pipe->screen)->caps.has_tcl) {
1586 /* Setup PSC.
1587 * The unused components will be replaced by (..., 0, 1). */
1588 r300_vertex_psc(velems);
1589
1590 for (i = 0; i < count; i++) {
1591 velems->format_size[i] =
1592 align(util_format_get_blocksize(velems->velem[i].src_format), 4);
1593 velems->vertex_size_dwords += velems->format_size[i] / 4;
1594 }
1595 }
1596
1597 return velems;
1598 }
1599
1600 static void r300_bind_vertex_elements_state(struct pipe_context *pipe,
1601 void *state)
1602 {
1603 struct r300_context *r300 = r300_context(pipe);
1604 struct r300_vertex_element_state *velems = state;
1605
1606 if (velems == NULL) {
1607 return;
1608 }
1609
1610 r300->velems = velems;
1611
1612 u_vbuf_mgr_bind_vertex_elements(r300->vbuf_mgr, state, velems->vmgr_elements);
1613
1614 if (r300->draw) {
1615 draw_set_vertex_elements(r300->draw, velems->count, velems->velem);
1616 return;
1617 }
1618
1619 UPDATE_STATE(&velems->vertex_stream, r300->vertex_stream_state);
1620 r300->vertex_stream_state.size = (1 + velems->vertex_stream.count) * 2;
1621 r300->vertex_arrays_dirty = TRUE;
1622 }
1623
1624 static void r300_delete_vertex_elements_state(struct pipe_context *pipe, void *state)
1625 {
1626 struct r300_context *r300 = r300_context(pipe);
1627 struct r300_vertex_element_state *velems = state;
1628
1629 u_vbuf_mgr_destroy_vertex_elements(r300->vbuf_mgr, velems->vmgr_elements);
1630 FREE(state);
1631 }
1632
1633 static void* r300_create_vs_state(struct pipe_context* pipe,
1634 const struct pipe_shader_state* shader)
1635 {
1636 struct r300_context* r300 = r300_context(pipe);
1637 struct r300_vertex_shader* vs = CALLOC_STRUCT(r300_vertex_shader);
1638
1639 /* Copy state directly into shader. */
1640 vs->state = *shader;
1641 vs->state.tokens = tgsi_dup_tokens(shader->tokens);
1642
1643 if (r300->screen->caps.has_tcl) {
1644 r300_init_vs_outputs(vs);
1645 r300_translate_vertex_shader(r300, vs);
1646 } else {
1647 r300_draw_init_vertex_shader(r300->draw, vs);
1648 }
1649
1650 return vs;
1651 }
1652
1653 static void r300_bind_vs_state(struct pipe_context* pipe, void* shader)
1654 {
1655 struct r300_context* r300 = r300_context(pipe);
1656 struct r300_vertex_shader* vs = (struct r300_vertex_shader*)shader;
1657
1658 if (vs == NULL) {
1659 r300->vs_state.state = NULL;
1660 return;
1661 }
1662 if (vs == r300->vs_state.state) {
1663 return;
1664 }
1665 r300->vs_state.state = vs;
1666
1667 /* The majority of the RS block bits is dependent on the vertex shader. */
1668 r300_mark_atom_dirty(r300, &r300->rs_block_state); /* Will be updated before the emission. */
1669
1670 if (r300->screen->caps.has_tcl) {
1671 unsigned fc_op_dwords = r300->screen->caps.is_r500 ? 3 : 2;
1672 r300_mark_atom_dirty(r300, &r300->vs_state);
1673 r300->vs_state.size =
1674 vs->code.length + 9 +
1675 (vs->code.num_fc_ops ? vs->code.num_fc_ops * fc_op_dwords + 4 : 0);
1676
1677 r300_mark_atom_dirty(r300, &r300->vs_constants);
1678 r300->vs_constants.size =
1679 2 +
1680 (vs->externals_count ? vs->externals_count * 4 + 3 : 0) +
1681 (vs->immediates_count ? vs->immediates_count * 4 + 3 : 0);
1682
1683 ((struct r300_constant_buffer*)r300->vs_constants.state)->remap_table =
1684 vs->code.constants_remap_table;
1685
1686 r300_mark_atom_dirty(r300, &r300->pvs_flush);
1687 } else {
1688 draw_bind_vertex_shader(r300->draw,
1689 (struct draw_vertex_shader*)vs->draw_vs);
1690 }
1691 }
1692
1693 static void r300_delete_vs_state(struct pipe_context* pipe, void* shader)
1694 {
1695 struct r300_context* r300 = r300_context(pipe);
1696 struct r300_vertex_shader* vs = (struct r300_vertex_shader*)shader;
1697
1698 if (r300->screen->caps.has_tcl) {
1699 rc_constants_destroy(&vs->code.constants);
1700 if (vs->code.constants_remap_table)
1701 FREE(vs->code.constants_remap_table);
1702 } else {
1703 draw_delete_vertex_shader(r300->draw,
1704 (struct draw_vertex_shader*)vs->draw_vs);
1705 }
1706
1707 FREE((void*)vs->state.tokens);
1708 FREE(shader);
1709 }
1710
1711 static void r300_set_constant_buffer(struct pipe_context *pipe,
1712 uint shader, uint index,
1713 struct pipe_resource *buf)
1714 {
1715 struct r300_context* r300 = r300_context(pipe);
1716 struct r300_constant_buffer *cbuf;
1717 struct r300_resource *rbuf = r300_resource(buf);
1718 uint32_t *mapped;
1719
1720 switch (shader) {
1721 case PIPE_SHADER_VERTEX:
1722 cbuf = (struct r300_constant_buffer*)r300->vs_constants.state;
1723 break;
1724 case PIPE_SHADER_FRAGMENT:
1725 cbuf = (struct r300_constant_buffer*)r300->fs_constants.state;
1726 break;
1727 default:
1728 return;
1729 }
1730
1731 if (buf == NULL || buf->width0 == 0)
1732 return;
1733
1734 if (rbuf->b.user_ptr)
1735 mapped = (uint32_t*)rbuf->b.user_ptr;
1736 else if (rbuf->constant_buffer)
1737 mapped = (uint32_t*)rbuf->constant_buffer;
1738 else
1739 return;
1740
1741 if (shader == PIPE_SHADER_FRAGMENT ||
1742 (shader == PIPE_SHADER_VERTEX && r300->screen->caps.has_tcl)) {
1743 cbuf->ptr = mapped;
1744 }
1745
1746 if (shader == PIPE_SHADER_VERTEX) {
1747 if (r300->screen->caps.has_tcl) {
1748 struct r300_vertex_shader *vs =
1749 (struct r300_vertex_shader*)r300->vs_state.state;
1750
1751 if (!vs) {
1752 cbuf->buffer_base = 0;
1753 return;
1754 }
1755
1756 cbuf->buffer_base = r300->vs_const_base;
1757 r300->vs_const_base += vs->code.constants.Count;
1758 if (r300->vs_const_base > R500_MAX_PVS_CONST_VECS) {
1759 r300->vs_const_base = vs->code.constants.Count;
1760 cbuf->buffer_base = 0;
1761 r300_mark_atom_dirty(r300, &r300->pvs_flush);
1762 }
1763 r300_mark_atom_dirty(r300, &r300->vs_constants);
1764 } else if (r300->draw) {
1765 draw_set_mapped_constant_buffer(r300->draw, PIPE_SHADER_VERTEX,
1766 0, mapped, buf->width0);
1767 }
1768 } else if (shader == PIPE_SHADER_FRAGMENT) {
1769 r300_mark_atom_dirty(r300, &r300->fs_constants);
1770 }
1771 }
1772
1773 void r300_init_state_functions(struct r300_context* r300)
1774 {
1775 r300->context.create_blend_state = r300_create_blend_state;
1776 r300->context.bind_blend_state = r300_bind_blend_state;
1777 r300->context.delete_blend_state = r300_delete_blend_state;
1778
1779 r300->context.set_blend_color = r300_set_blend_color;
1780
1781 r300->context.set_clip_state = r300_set_clip_state;
1782 r300->context.set_sample_mask = r300_set_sample_mask;
1783
1784 r300->context.set_constant_buffer = r300_set_constant_buffer;
1785
1786 r300->context.create_depth_stencil_alpha_state = r300_create_dsa_state;
1787 r300->context.bind_depth_stencil_alpha_state = r300_bind_dsa_state;
1788 r300->context.delete_depth_stencil_alpha_state = r300_delete_dsa_state;
1789
1790 r300->context.set_stencil_ref = r300_set_stencil_ref;
1791
1792 r300->context.set_framebuffer_state = r300_set_framebuffer_state;
1793
1794 r300->context.create_fs_state = r300_create_fs_state;
1795 r300->context.bind_fs_state = r300_bind_fs_state;
1796 r300->context.delete_fs_state = r300_delete_fs_state;
1797
1798 r300->context.set_polygon_stipple = r300_set_polygon_stipple;
1799
1800 r300->context.create_rasterizer_state = r300_create_rs_state;
1801 r300->context.bind_rasterizer_state = r300_bind_rs_state;
1802 r300->context.delete_rasterizer_state = r300_delete_rs_state;
1803
1804 r300->context.create_sampler_state = r300_create_sampler_state;
1805 r300->context.bind_fragment_sampler_states = r300_bind_sampler_states;
1806 r300->context.bind_vertex_sampler_states = r300_lacks_vertex_textures;
1807 r300->context.delete_sampler_state = r300_delete_sampler_state;
1808
1809 r300->context.set_fragment_sampler_views = r300_set_fragment_sampler_views;
1810 r300->context.create_sampler_view = r300_create_sampler_view;
1811 r300->context.sampler_view_destroy = r300_sampler_view_destroy;
1812
1813 r300->context.set_scissor_state = r300_set_scissor_state;
1814
1815 r300->context.set_viewport_state = r300_set_viewport_state;
1816
1817 r300->context.set_vertex_buffers = r300_set_vertex_buffers;
1818 r300->context.set_index_buffer = r300_set_index_buffer;
1819 r300->context.redefine_user_buffer = u_default_redefine_user_buffer;
1820
1821 r300->context.create_vertex_elements_state = r300_create_vertex_elements_state;
1822 r300->context.bind_vertex_elements_state = r300_bind_vertex_elements_state;
1823 r300->context.delete_vertex_elements_state = r300_delete_vertex_elements_state;
1824
1825 r300->context.create_vs_state = r300_create_vs_state;
1826 r300->context.bind_vs_state = r300_bind_vs_state;
1827 r300->context.delete_vs_state = r300_delete_vs_state;
1828 }