Merge remote branch 'origin/master' into pipe-video
[mesa.git] / src / gallium / drivers / r300 / r300_state.c
1 /*
2 * Copyright 2008 Corbin Simpson <MostAwesomeDude@gmail.com>
3 * Copyright 2009 Marek Olšák <maraeo@gmail.com>
4 *
5 * Permission is hereby granted, free of charge, to any person obtaining a
6 * copy of this software and associated documentation files (the "Software"),
7 * to deal in the Software without restriction, including without limitation
8 * on the rights to use, copy, modify, merge, publish, distribute, sub
9 * license, and/or sell copies of the Software, and to permit persons to whom
10 * the Software is furnished to do so, subject to the following conditions:
11 *
12 * The above copyright notice and this permission notice (including the next
13 * paragraph) shall be included in all copies or substantial portions of the
14 * Software.
15 *
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
19 * THE AUTHOR(S) AND/OR THEIR SUPPLIERS BE LIABLE FOR ANY CLAIM,
20 * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
21 * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
22 * USE OR OTHER DEALINGS IN THE SOFTWARE. */
23
24 #include "draw/draw_context.h"
25
26 #include "util/u_framebuffer.h"
27 #include "util/u_half.h"
28 #include "util/u_math.h"
29 #include "util/u_mm.h"
30 #include "util/u_memory.h"
31 #include "util/u_pack_color.h"
32 #include "util/u_transfer.h"
33
34 #include "tgsi/tgsi_parse.h"
35
36 #include "pipe/p_config.h"
37
38 #include "r300_cb.h"
39 #include "r300_context.h"
40 #include "r300_emit.h"
41 #include "r300_reg.h"
42 #include "r300_screen.h"
43 #include "r300_screen_buffer.h"
44 #include "r300_state_inlines.h"
45 #include "r300_fs.h"
46 #include "r300_texture.h"
47 #include "r300_vs.h"
48
49 /* r300_state: Functions used to intialize state context by translating
50 * Gallium state objects into semi-native r300 state objects. */
51
52 #define UPDATE_STATE(cso, atom) \
53 if (cso != atom.state) { \
54 atom.state = cso; \
55 r300_mark_atom_dirty(r300, &(atom)); \
56 }
57
58 static boolean blend_discard_if_src_alpha_0(unsigned srcRGB, unsigned srcA,
59 unsigned dstRGB, unsigned dstA)
60 {
61 /* If the blend equation is ADD or REVERSE_SUBTRACT,
62 * SRC_ALPHA == 0, and the following state is set, the colorbuffer
63 * will not be changed.
64 * Notice that the dst factors are the src factors inverted. */
65 return (srcRGB == PIPE_BLENDFACTOR_SRC_ALPHA ||
66 srcRGB == PIPE_BLENDFACTOR_SRC_ALPHA_SATURATE ||
67 srcRGB == PIPE_BLENDFACTOR_ZERO) &&
68 (srcA == PIPE_BLENDFACTOR_SRC_COLOR ||
69 srcA == PIPE_BLENDFACTOR_SRC_ALPHA ||
70 srcA == PIPE_BLENDFACTOR_SRC_ALPHA_SATURATE ||
71 srcA == PIPE_BLENDFACTOR_ZERO) &&
72 (dstRGB == PIPE_BLENDFACTOR_INV_SRC_ALPHA ||
73 dstRGB == PIPE_BLENDFACTOR_ONE) &&
74 (dstA == PIPE_BLENDFACTOR_INV_SRC_COLOR ||
75 dstA == PIPE_BLENDFACTOR_INV_SRC_ALPHA ||
76 dstA == PIPE_BLENDFACTOR_ONE);
77 }
78
79 static boolean blend_discard_if_src_alpha_1(unsigned srcRGB, unsigned srcA,
80 unsigned dstRGB, unsigned dstA)
81 {
82 /* If the blend equation is ADD or REVERSE_SUBTRACT,
83 * SRC_ALPHA == 1, and the following state is set, the colorbuffer
84 * will not be changed.
85 * Notice that the dst factors are the src factors inverted. */
86 return (srcRGB == PIPE_BLENDFACTOR_INV_SRC_ALPHA ||
87 srcRGB == PIPE_BLENDFACTOR_ZERO) &&
88 (srcA == PIPE_BLENDFACTOR_INV_SRC_COLOR ||
89 srcA == PIPE_BLENDFACTOR_INV_SRC_ALPHA ||
90 srcA == PIPE_BLENDFACTOR_ZERO) &&
91 (dstRGB == PIPE_BLENDFACTOR_SRC_ALPHA ||
92 dstRGB == PIPE_BLENDFACTOR_ONE) &&
93 (dstA == PIPE_BLENDFACTOR_SRC_COLOR ||
94 dstA == PIPE_BLENDFACTOR_SRC_ALPHA ||
95 dstA == PIPE_BLENDFACTOR_ONE);
96 }
97
98 static boolean blend_discard_if_src_color_0(unsigned srcRGB, unsigned srcA,
99 unsigned dstRGB, unsigned dstA)
100 {
101 /* If the blend equation is ADD or REVERSE_SUBTRACT,
102 * SRC_COLOR == (0,0,0), and the following state is set, the colorbuffer
103 * will not be changed.
104 * Notice that the dst factors are the src factors inverted. */
105 return (srcRGB == PIPE_BLENDFACTOR_SRC_COLOR ||
106 srcRGB == PIPE_BLENDFACTOR_ZERO) &&
107 (srcA == PIPE_BLENDFACTOR_ZERO) &&
108 (dstRGB == PIPE_BLENDFACTOR_INV_SRC_COLOR ||
109 dstRGB == PIPE_BLENDFACTOR_ONE) &&
110 (dstA == PIPE_BLENDFACTOR_ONE);
111 }
112
113 static boolean blend_discard_if_src_color_1(unsigned srcRGB, unsigned srcA,
114 unsigned dstRGB, unsigned dstA)
115 {
116 /* If the blend equation is ADD or REVERSE_SUBTRACT,
117 * SRC_COLOR == (1,1,1), and the following state is set, the colorbuffer
118 * will not be changed.
119 * Notice that the dst factors are the src factors inverted. */
120 return (srcRGB == PIPE_BLENDFACTOR_INV_SRC_COLOR ||
121 srcRGB == PIPE_BLENDFACTOR_ZERO) &&
122 (srcA == PIPE_BLENDFACTOR_ZERO) &&
123 (dstRGB == PIPE_BLENDFACTOR_SRC_COLOR ||
124 dstRGB == PIPE_BLENDFACTOR_ONE) &&
125 (dstA == PIPE_BLENDFACTOR_ONE);
126 }
127
128 static boolean blend_discard_if_src_alpha_color_0(unsigned srcRGB, unsigned srcA,
129 unsigned dstRGB, unsigned dstA)
130 {
131 /* If the blend equation is ADD or REVERSE_SUBTRACT,
132 * SRC_ALPHA_COLOR == (0,0,0,0), and the following state is set,
133 * the colorbuffer will not be changed.
134 * Notice that the dst factors are the src factors inverted. */
135 return (srcRGB == PIPE_BLENDFACTOR_SRC_COLOR ||
136 srcRGB == PIPE_BLENDFACTOR_SRC_ALPHA ||
137 srcRGB == PIPE_BLENDFACTOR_SRC_ALPHA_SATURATE ||
138 srcRGB == PIPE_BLENDFACTOR_ZERO) &&
139 (srcA == PIPE_BLENDFACTOR_SRC_COLOR ||
140 srcA == PIPE_BLENDFACTOR_SRC_ALPHA ||
141 srcA == PIPE_BLENDFACTOR_SRC_ALPHA_SATURATE ||
142 srcA == PIPE_BLENDFACTOR_ZERO) &&
143 (dstRGB == PIPE_BLENDFACTOR_INV_SRC_COLOR ||
144 dstRGB == PIPE_BLENDFACTOR_INV_SRC_ALPHA ||
145 dstRGB == PIPE_BLENDFACTOR_ONE) &&
146 (dstA == PIPE_BLENDFACTOR_INV_SRC_COLOR ||
147 dstA == PIPE_BLENDFACTOR_INV_SRC_ALPHA ||
148 dstA == PIPE_BLENDFACTOR_ONE);
149 }
150
151 static boolean blend_discard_if_src_alpha_color_1(unsigned srcRGB, unsigned srcA,
152 unsigned dstRGB, unsigned dstA)
153 {
154 /* If the blend equation is ADD or REVERSE_SUBTRACT,
155 * SRC_ALPHA_COLOR == (1,1,1,1), and the following state is set,
156 * the colorbuffer will not be changed.
157 * Notice that the dst factors are the src factors inverted. */
158 return (srcRGB == PIPE_BLENDFACTOR_INV_SRC_COLOR ||
159 srcRGB == PIPE_BLENDFACTOR_INV_SRC_ALPHA ||
160 srcRGB == PIPE_BLENDFACTOR_ZERO) &&
161 (srcA == PIPE_BLENDFACTOR_INV_SRC_COLOR ||
162 srcA == PIPE_BLENDFACTOR_INV_SRC_ALPHA ||
163 srcA == PIPE_BLENDFACTOR_ZERO) &&
164 (dstRGB == PIPE_BLENDFACTOR_SRC_COLOR ||
165 dstRGB == PIPE_BLENDFACTOR_SRC_ALPHA ||
166 dstRGB == PIPE_BLENDFACTOR_ONE) &&
167 (dstA == PIPE_BLENDFACTOR_SRC_COLOR ||
168 dstA == PIPE_BLENDFACTOR_SRC_ALPHA ||
169 dstA == PIPE_BLENDFACTOR_ONE);
170 }
171
172 static unsigned bgra_cmask(unsigned mask)
173 {
174 /* Gallium uses RGBA color ordering while R300 expects BGRA. */
175
176 return ((mask & PIPE_MASK_R) << 2) |
177 ((mask & PIPE_MASK_B) >> 2) |
178 (mask & (PIPE_MASK_G | PIPE_MASK_A));
179 }
180
181 /* Create a new blend state based on the CSO blend state.
182 *
183 * This encompasses alpha blending, logic/raster ops, and blend dithering. */
184 static void* r300_create_blend_state(struct pipe_context* pipe,
185 const struct pipe_blend_state* state)
186 {
187 struct r300_screen* r300screen = r300_screen(pipe->screen);
188 struct r300_blend_state* blend = CALLOC_STRUCT(r300_blend_state);
189 uint32_t blend_control = 0; /* R300_RB3D_CBLEND: 0x4e04 */
190 uint32_t blend_control_noclamp = 0; /* R300_RB3D_CBLEND: 0x4e04 */
191 uint32_t alpha_blend_control = 0; /* R300_RB3D_ABLEND: 0x4e08 */
192 uint32_t alpha_blend_control_noclamp = 0; /* R300_RB3D_ABLEND: 0x4e08 */
193 uint32_t color_channel_mask = 0; /* R300_RB3D_COLOR_CHANNEL_MASK: 0x4e0c */
194 uint32_t rop = 0; /* R300_RB3D_ROPCNTL: 0x4e18 */
195 uint32_t dither = 0; /* R300_RB3D_DITHER_CTL: 0x4e50 */
196 CB_LOCALS;
197
198 blend->state = *state;
199
200 if (state->rt[0].blend_enable)
201 {
202 unsigned eqRGB = state->rt[0].rgb_func;
203 unsigned srcRGB = state->rt[0].rgb_src_factor;
204 unsigned dstRGB = state->rt[0].rgb_dst_factor;
205
206 unsigned eqA = state->rt[0].alpha_func;
207 unsigned srcA = state->rt[0].alpha_src_factor;
208 unsigned dstA = state->rt[0].alpha_dst_factor;
209
210 /* despite the name, ALPHA_BLEND_ENABLE has nothing to do with alpha,
211 * this is just the crappy D3D naming */
212 blend_control = blend_control_noclamp =
213 R300_ALPHA_BLEND_ENABLE |
214 ( r300_translate_blend_factor(srcRGB) << R300_SRC_BLEND_SHIFT) |
215 ( r300_translate_blend_factor(dstRGB) << R300_DST_BLEND_SHIFT);
216 blend_control |=
217 r300_translate_blend_function(eqRGB, TRUE);
218 blend_control_noclamp |=
219 r300_translate_blend_function(eqRGB, FALSE);
220
221 /* Optimization: some operations do not require the destination color.
222 *
223 * When SRC_ALPHA_SATURATE is used, colorbuffer reads must be enabled,
224 * otherwise blending gives incorrect results. It seems to be
225 * a hardware bug. */
226 if (eqRGB == PIPE_BLEND_MIN || eqA == PIPE_BLEND_MIN ||
227 eqRGB == PIPE_BLEND_MAX || eqA == PIPE_BLEND_MAX ||
228 dstRGB != PIPE_BLENDFACTOR_ZERO ||
229 dstA != PIPE_BLENDFACTOR_ZERO ||
230 srcRGB == PIPE_BLENDFACTOR_DST_COLOR ||
231 srcRGB == PIPE_BLENDFACTOR_DST_ALPHA ||
232 srcRGB == PIPE_BLENDFACTOR_INV_DST_COLOR ||
233 srcRGB == PIPE_BLENDFACTOR_INV_DST_ALPHA ||
234 srcA == PIPE_BLENDFACTOR_DST_COLOR ||
235 srcA == PIPE_BLENDFACTOR_DST_ALPHA ||
236 srcA == PIPE_BLENDFACTOR_INV_DST_COLOR ||
237 srcA == PIPE_BLENDFACTOR_INV_DST_ALPHA ||
238 srcRGB == PIPE_BLENDFACTOR_SRC_ALPHA_SATURATE) {
239 /* Enable reading from the colorbuffer. */
240 blend_control |= R300_READ_ENABLE;
241 blend_control_noclamp |= R300_READ_ENABLE;
242
243 if (r300screen->caps.is_r500) {
244 /* Optimization: Depending on incoming pixels, we can
245 * conditionally disable the reading in hardware... */
246 if (eqRGB != PIPE_BLEND_MIN && eqA != PIPE_BLEND_MIN &&
247 eqRGB != PIPE_BLEND_MAX && eqA != PIPE_BLEND_MAX) {
248 /* Disable reading if SRC_ALPHA == 0. */
249 if ((dstRGB == PIPE_BLENDFACTOR_SRC_ALPHA ||
250 dstRGB == PIPE_BLENDFACTOR_ZERO) &&
251 (dstA == PIPE_BLENDFACTOR_SRC_COLOR ||
252 dstA == PIPE_BLENDFACTOR_SRC_ALPHA ||
253 dstA == PIPE_BLENDFACTOR_ZERO)) {
254 blend_control |= R500_SRC_ALPHA_0_NO_READ;
255 }
256
257 /* Disable reading if SRC_ALPHA == 1. */
258 if ((dstRGB == PIPE_BLENDFACTOR_INV_SRC_ALPHA ||
259 dstRGB == PIPE_BLENDFACTOR_ZERO) &&
260 (dstA == PIPE_BLENDFACTOR_INV_SRC_COLOR ||
261 dstA == PIPE_BLENDFACTOR_INV_SRC_ALPHA ||
262 dstA == PIPE_BLENDFACTOR_ZERO)) {
263 blend_control |= R500_SRC_ALPHA_1_NO_READ;
264 }
265 }
266 }
267 }
268
269 /* Optimization: discard pixels which don't change the colorbuffer.
270 *
271 * The code below is non-trivial and some math is involved.
272 *
273 * Discarding pixels must be disabled when FP16 AA is enabled.
274 * This is a hardware bug. Also, this implementation wouldn't work
275 * with FP blending enabled and equation clamping disabled.
276 *
277 * Equations other than ADD are rarely used and therefore won't be
278 * optimized. */
279 if ((eqRGB == PIPE_BLEND_ADD || eqRGB == PIPE_BLEND_REVERSE_SUBTRACT) &&
280 (eqA == PIPE_BLEND_ADD || eqA == PIPE_BLEND_REVERSE_SUBTRACT)) {
281 /* ADD: X+Y
282 * REVERSE_SUBTRACT: Y-X
283 *
284 * The idea is:
285 * If X = src*srcFactor = 0 and Y = dst*dstFactor = 1,
286 * then CB will not be changed.
287 *
288 * Given the srcFactor and dstFactor variables, we can derive
289 * what src and dst should be equal to and discard appropriate
290 * pixels.
291 */
292 if (blend_discard_if_src_alpha_0(srcRGB, srcA, dstRGB, dstA)) {
293 blend_control |= R300_DISCARD_SRC_PIXELS_SRC_ALPHA_0;
294 } else if (blend_discard_if_src_alpha_1(srcRGB, srcA,
295 dstRGB, dstA)) {
296 blend_control |= R300_DISCARD_SRC_PIXELS_SRC_ALPHA_1;
297 } else if (blend_discard_if_src_color_0(srcRGB, srcA,
298 dstRGB, dstA)) {
299 blend_control |= R300_DISCARD_SRC_PIXELS_SRC_COLOR_0;
300 } else if (blend_discard_if_src_color_1(srcRGB, srcA,
301 dstRGB, dstA)) {
302 blend_control |= R300_DISCARD_SRC_PIXELS_SRC_COLOR_1;
303 } else if (blend_discard_if_src_alpha_color_0(srcRGB, srcA,
304 dstRGB, dstA)) {
305 blend_control |=
306 R300_DISCARD_SRC_PIXELS_SRC_ALPHA_COLOR_0;
307 } else if (blend_discard_if_src_alpha_color_1(srcRGB, srcA,
308 dstRGB, dstA)) {
309 blend_control |=
310 R300_DISCARD_SRC_PIXELS_SRC_ALPHA_COLOR_1;
311 }
312 }
313
314 /* separate alpha */
315 if (srcA != srcRGB || dstA != dstRGB || eqA != eqRGB) {
316 blend_control |= R300_SEPARATE_ALPHA_ENABLE;
317 blend_control_noclamp |= R300_SEPARATE_ALPHA_ENABLE;
318 alpha_blend_control = alpha_blend_control_noclamp =
319 (r300_translate_blend_factor(srcA) << R300_SRC_BLEND_SHIFT) |
320 (r300_translate_blend_factor(dstA) << R300_DST_BLEND_SHIFT);
321 alpha_blend_control |=
322 r300_translate_blend_function(eqA, TRUE);
323 alpha_blend_control_noclamp |=
324 r300_translate_blend_function(eqA, FALSE);
325 }
326 }
327
328 /* PIPE_LOGICOP_* don't need to be translated, fortunately. */
329 if (state->logicop_enable) {
330 rop = R300_RB3D_ROPCNTL_ROP_ENABLE |
331 (state->logicop_func) << R300_RB3D_ROPCNTL_ROP_SHIFT;
332 }
333
334 /* Color channel masks for all MRTs. */
335 color_channel_mask = bgra_cmask(state->rt[0].colormask);
336 if (r300screen->caps.is_r500 && state->independent_blend_enable) {
337 if (state->rt[1].blend_enable) {
338 color_channel_mask |= bgra_cmask(state->rt[1].colormask) << 4;
339 }
340 if (state->rt[2].blend_enable) {
341 color_channel_mask |= bgra_cmask(state->rt[2].colormask) << 8;
342 }
343 if (state->rt[3].blend_enable) {
344 color_channel_mask |= bgra_cmask(state->rt[3].colormask) << 12;
345 }
346 }
347
348 /* Neither fglrx nor classic r300 ever set this, regardless of dithering
349 * state. Since it's an optional implementation detail, we can leave it
350 * out and never dither.
351 *
352 * This could be revisited if we ever get quality or conformance hints.
353 *
354 if (state->dither) {
355 dither = R300_RB3D_DITHER_CTL_DITHER_MODE_LUT |
356 R300_RB3D_DITHER_CTL_ALPHA_DITHER_MODE_LUT;
357 }
358 */
359
360 /* Build a command buffer. */
361 BEGIN_CB(blend->cb_clamp, 8);
362 OUT_CB_REG(R300_RB3D_ROPCNTL, rop);
363 OUT_CB_REG_SEQ(R300_RB3D_CBLEND, 3);
364 OUT_CB(blend_control);
365 OUT_CB(alpha_blend_control);
366 OUT_CB(color_channel_mask);
367 OUT_CB_REG(R300_RB3D_DITHER_CTL, dither);
368 END_CB;
369
370 /* Build a command buffer. */
371 BEGIN_CB(blend->cb_noclamp, 8);
372 OUT_CB_REG(R300_RB3D_ROPCNTL, rop);
373 OUT_CB_REG_SEQ(R300_RB3D_CBLEND, 3);
374 OUT_CB(blend_control_noclamp);
375 OUT_CB(alpha_blend_control_noclamp);
376 OUT_CB(color_channel_mask);
377 OUT_CB_REG(R300_RB3D_DITHER_CTL, dither);
378 END_CB;
379
380 /* The same as above, but with no colorbuffer reads and writes. */
381 BEGIN_CB(blend->cb_no_readwrite, 8);
382 OUT_CB_REG(R300_RB3D_ROPCNTL, rop);
383 OUT_CB_REG_SEQ(R300_RB3D_CBLEND, 3);
384 OUT_CB(0);
385 OUT_CB(0);
386 OUT_CB(0);
387 OUT_CB_REG(R300_RB3D_DITHER_CTL, dither);
388 END_CB;
389
390 return (void*)blend;
391 }
392
393 /* Bind blend state. */
394 static void r300_bind_blend_state(struct pipe_context* pipe,
395 void* state)
396 {
397 struct r300_context* r300 = r300_context(pipe);
398
399 UPDATE_STATE(state, r300->blend_state);
400 }
401
402 /* Free blend state. */
403 static void r300_delete_blend_state(struct pipe_context* pipe,
404 void* state)
405 {
406 FREE(state);
407 }
408
409 /* Convert float to 10bit integer */
410 static unsigned float_to_fixed10(float f)
411 {
412 return CLAMP((unsigned)(f * 1023.9f), 0, 1023);
413 }
414
415 /* Set blend color.
416 * Setup both R300 and R500 registers, figure out later which one to write. */
417 static void r300_set_blend_color(struct pipe_context* pipe,
418 const struct pipe_blend_color* color)
419 {
420 struct r300_context* r300 = r300_context(pipe);
421 struct pipe_framebuffer_state *fb = r300->fb_state.state;
422 struct r300_blend_color_state *state =
423 (struct r300_blend_color_state*)r300->blend_color_state.state;
424 struct pipe_blend_color c;
425 enum pipe_format format = fb->nr_cbufs ? fb->cbufs[0]->format : 0;
426 CB_LOCALS;
427
428 state->state = *color; /* Save it, so that we can reuse it in set_fb_state */
429 c = *color;
430
431 /* The blend color is dependent on the colorbuffer format. */
432 if (fb->nr_cbufs) {
433 switch (format) {
434 case PIPE_FORMAT_R8_UNORM:
435 case PIPE_FORMAT_L8_UNORM:
436 case PIPE_FORMAT_I8_UNORM:
437 c.color[1] = c.color[0];
438 break;
439
440 case PIPE_FORMAT_A8_UNORM:
441 c.color[1] = c.color[3];
442 break;
443
444 case PIPE_FORMAT_R8G8_UNORM:
445 c.color[2] = c.color[1];
446 break;
447
448 case PIPE_FORMAT_L8A8_UNORM:
449 c.color[2] = c.color[3];
450 break;
451
452 default:;
453 }
454 }
455
456 if (r300->screen->caps.is_r500) {
457 BEGIN_CB(state->cb, 3);
458 OUT_CB_REG_SEQ(R500_RB3D_CONSTANT_COLOR_AR, 2);
459
460 switch (format) {
461 case PIPE_FORMAT_R16G16B16A16_FLOAT:
462 OUT_CB(util_float_to_half(c.color[2]) |
463 (util_float_to_half(c.color[3]) << 16));
464 OUT_CB(util_float_to_half(c.color[0]) |
465 (util_float_to_half(c.color[1]) << 16));
466 break;
467
468 default:
469 OUT_CB(float_to_fixed10(c.color[0]) |
470 (float_to_fixed10(c.color[3]) << 16));
471 OUT_CB(float_to_fixed10(c.color[2]) |
472 (float_to_fixed10(c.color[1]) << 16));
473 }
474
475 END_CB;
476 } else {
477 union util_color uc;
478 util_pack_color(c.color, PIPE_FORMAT_B8G8R8A8_UNORM, &uc);
479
480 BEGIN_CB(state->cb, 2);
481 OUT_CB_REG(R300_RB3D_BLEND_COLOR, uc.ui);
482 END_CB;
483 }
484
485 r300_mark_atom_dirty(r300, &r300->blend_color_state);
486 }
487
488 static void r300_set_clip_state(struct pipe_context* pipe,
489 const struct pipe_clip_state* state)
490 {
491 struct r300_context* r300 = r300_context(pipe);
492 struct r300_clip_state *clip =
493 (struct r300_clip_state*)r300->clip_state.state;
494 CB_LOCALS;
495
496 clip->clip = *state;
497
498 if (r300->screen->caps.has_tcl) {
499 r300->clip_state.size = 2 + !!state->nr * 3 + state->nr * 4;
500
501 BEGIN_CB(clip->cb, r300->clip_state.size);
502 if (state->nr) {
503 OUT_CB_REG(R300_VAP_PVS_VECTOR_INDX_REG,
504 (r300->screen->caps.is_r500 ?
505 R500_PVS_UCP_START : R300_PVS_UCP_START));
506 OUT_CB_ONE_REG(R300_VAP_PVS_UPLOAD_DATA, state->nr * 4);
507 OUT_CB_TABLE(state->ucp, state->nr * 4);
508 }
509 OUT_CB_REG(R300_VAP_CLIP_CNTL, ((1 << state->nr) - 1) |
510 R300_PS_UCP_MODE_CLIP_AS_TRIFAN);
511 END_CB;
512
513 r300_mark_atom_dirty(r300, &r300->clip_state);
514 } else {
515 draw_set_clip_state(r300->draw, state);
516 }
517 }
518
519 static void
520 r300_set_sample_mask(struct pipe_context *pipe,
521 unsigned sample_mask)
522 {
523 }
524
525
526 /* Create a new depth, stencil, and alpha state based on the CSO dsa state.
527 *
528 * This contains the depth buffer, stencil buffer, alpha test, and such.
529 * On the Radeon, depth and stencil buffer setup are intertwined, which is
530 * the reason for some of the strange-looking assignments across registers. */
531 static void*
532 r300_create_dsa_state(struct pipe_context* pipe,
533 const struct pipe_depth_stencil_alpha_state* state)
534 {
535 struct r300_capabilities *caps = &r300_screen(pipe->screen)->caps;
536 struct r300_dsa_state* dsa = CALLOC_STRUCT(r300_dsa_state);
537 CB_LOCALS;
538
539 dsa->dsa = *state;
540
541 /* Depth test setup. - separate write mask depth for decomp flush */
542 if (state->depth.writemask) {
543 dsa->z_buffer_control |= R300_Z_WRITE_ENABLE;
544 }
545
546 if (state->depth.enabled) {
547 dsa->z_buffer_control |= R300_Z_ENABLE;
548
549 dsa->z_stencil_control |=
550 (r300_translate_depth_stencil_function(state->depth.func) <<
551 R300_Z_FUNC_SHIFT);
552 }
553
554 /* Stencil buffer setup. */
555 if (state->stencil[0].enabled) {
556 dsa->z_buffer_control |= R300_STENCIL_ENABLE;
557 dsa->z_stencil_control |=
558 (r300_translate_depth_stencil_function(state->stencil[0].func) <<
559 R300_S_FRONT_FUNC_SHIFT) |
560 (r300_translate_stencil_op(state->stencil[0].fail_op) <<
561 R300_S_FRONT_SFAIL_OP_SHIFT) |
562 (r300_translate_stencil_op(state->stencil[0].zpass_op) <<
563 R300_S_FRONT_ZPASS_OP_SHIFT) |
564 (r300_translate_stencil_op(state->stencil[0].zfail_op) <<
565 R300_S_FRONT_ZFAIL_OP_SHIFT);
566
567 dsa->stencil_ref_mask =
568 (state->stencil[0].valuemask << R300_STENCILMASK_SHIFT) |
569 (state->stencil[0].writemask << R300_STENCILWRITEMASK_SHIFT);
570
571 if (state->stencil[1].enabled) {
572 dsa->two_sided = TRUE;
573
574 dsa->z_buffer_control |= R300_STENCIL_FRONT_BACK;
575 dsa->z_stencil_control |=
576 (r300_translate_depth_stencil_function(state->stencil[1].func) <<
577 R300_S_BACK_FUNC_SHIFT) |
578 (r300_translate_stencil_op(state->stencil[1].fail_op) <<
579 R300_S_BACK_SFAIL_OP_SHIFT) |
580 (r300_translate_stencil_op(state->stencil[1].zpass_op) <<
581 R300_S_BACK_ZPASS_OP_SHIFT) |
582 (r300_translate_stencil_op(state->stencil[1].zfail_op) <<
583 R300_S_BACK_ZFAIL_OP_SHIFT);
584
585 dsa->stencil_ref_bf =
586 (state->stencil[1].valuemask << R300_STENCILMASK_SHIFT) |
587 (state->stencil[1].writemask << R300_STENCILWRITEMASK_SHIFT);
588
589 if (caps->is_r500) {
590 dsa->z_buffer_control |= R500_STENCIL_REFMASK_FRONT_BACK;
591 } else {
592 dsa->two_sided_stencil_ref =
593 (state->stencil[0].valuemask != state->stencil[1].valuemask ||
594 state->stencil[0].writemask != state->stencil[1].writemask);
595 }
596 }
597 }
598
599 /* Alpha test setup. */
600 if (state->alpha.enabled) {
601 dsa->alpha_function =
602 r300_translate_alpha_function(state->alpha.func) |
603 R300_FG_ALPHA_FUNC_ENABLE;
604
605 dsa->alpha_function |= float_to_ubyte(state->alpha.ref_value);
606 dsa->alpha_value = util_float_to_half(state->alpha.ref_value);
607
608 if (caps->is_r500) {
609 dsa->alpha_function_fp16 = dsa->alpha_function |
610 R500_FG_ALPHA_FUNC_FP16_ENABLE;
611 dsa->alpha_function |= R500_FG_ALPHA_FUNC_8BIT;
612 }
613 }
614
615 BEGIN_CB(&dsa->cb_begin, 10);
616 OUT_CB_REG(R300_FG_ALPHA_FUNC, dsa->alpha_function);
617 OUT_CB_REG_SEQ(R300_ZB_CNTL, 3);
618 OUT_CB(dsa->z_buffer_control);
619 OUT_CB(dsa->z_stencil_control);
620 OUT_CB(dsa->stencil_ref_mask);
621 OUT_CB_REG(R500_ZB_STENCILREFMASK_BF, dsa->stencil_ref_bf);
622 OUT_CB_REG(R500_FG_ALPHA_VALUE, dsa->alpha_value);
623 END_CB;
624
625 BEGIN_CB(&dsa->cb_begin_fp16, 10);
626 OUT_CB_REG(R300_FG_ALPHA_FUNC, dsa->alpha_function_fp16);
627 OUT_CB_REG_SEQ(R300_ZB_CNTL, 3);
628 OUT_CB(dsa->z_buffer_control);
629 OUT_CB(dsa->z_stencil_control);
630 OUT_CB(dsa->stencil_ref_mask);
631 OUT_CB_REG(R500_ZB_STENCILREFMASK_BF, dsa->stencil_ref_bf);
632 OUT_CB_REG(R500_FG_ALPHA_VALUE, dsa->alpha_value);
633 END_CB;
634
635 BEGIN_CB(dsa->cb_zb_no_readwrite, 10);
636 OUT_CB_REG(R300_FG_ALPHA_FUNC, dsa->alpha_function);
637 OUT_CB_REG_SEQ(R300_ZB_CNTL, 3);
638 OUT_CB(0);
639 OUT_CB(0);
640 OUT_CB(0);
641 OUT_CB_REG(R500_ZB_STENCILREFMASK_BF, 0);
642 OUT_CB_REG(R500_FG_ALPHA_VALUE, dsa->alpha_value);
643 END_CB;
644
645 BEGIN_CB(dsa->cb_fp16_zb_no_readwrite, 10);
646 OUT_CB_REG(R300_FG_ALPHA_FUNC, dsa->alpha_function_fp16);
647 OUT_CB_REG_SEQ(R300_ZB_CNTL, 3);
648 OUT_CB(0);
649 OUT_CB(0);
650 OUT_CB(0);
651 OUT_CB_REG(R500_ZB_STENCILREFMASK_BF, 0);
652 OUT_CB_REG(R500_FG_ALPHA_VALUE, dsa->alpha_value);
653 END_CB;
654
655 return (void*)dsa;
656 }
657
658 static void r300_dsa_inject_stencilref(struct r300_context *r300)
659 {
660 struct r300_dsa_state *dsa =
661 (struct r300_dsa_state*)r300->dsa_state.state;
662
663 if (!dsa)
664 return;
665
666 dsa->stencil_ref_mask =
667 (dsa->stencil_ref_mask & ~R300_STENCILREF_MASK) |
668 r300->stencil_ref.ref_value[0];
669 dsa->stencil_ref_bf =
670 (dsa->stencil_ref_bf & ~R300_STENCILREF_MASK) |
671 r300->stencil_ref.ref_value[1];
672 }
673
674 /* Bind DSA state. */
675 static void r300_bind_dsa_state(struct pipe_context* pipe,
676 void* state)
677 {
678 struct r300_context* r300 = r300_context(pipe);
679
680 if (!state) {
681 return;
682 }
683
684 UPDATE_STATE(state, r300->dsa_state);
685
686 r300_mark_atom_dirty(r300, &r300->hyperz_state); /* Will be updated before the emission. */
687 r300_dsa_inject_stencilref(r300);
688 }
689
690 /* Free DSA state. */
691 static void r300_delete_dsa_state(struct pipe_context* pipe,
692 void* state)
693 {
694 FREE(state);
695 }
696
697 static void r300_set_stencil_ref(struct pipe_context* pipe,
698 const struct pipe_stencil_ref* sr)
699 {
700 struct r300_context* r300 = r300_context(pipe);
701
702 r300->stencil_ref = *sr;
703
704 r300_dsa_inject_stencilref(r300);
705 r300_mark_atom_dirty(r300, &r300->dsa_state);
706 }
707
708 static void r300_tex_set_tiling_flags(struct r300_context *r300,
709 struct r300_resource *tex,
710 unsigned level)
711 {
712 /* Check if the macrotile flag needs to be changed.
713 * Skip changing the flags otherwise. */
714 if (tex->tex.macrotile[tex->surface_level] !=
715 tex->tex.macrotile[level]) {
716 r300->rws->buffer_set_tiling(tex->buf, r300->cs,
717 tex->tex.microtile, tex->tex.macrotile[level],
718 tex->tex.stride_in_bytes[0]);
719
720 tex->surface_level = level;
721 }
722 }
723
724 /* This switcheroo is needed just because of goddamned MACRO_SWITCH. */
725 static void r300_fb_set_tiling_flags(struct r300_context *r300,
726 const struct pipe_framebuffer_state *state)
727 {
728 unsigned i;
729
730 /* Set tiling flags for new surfaces. */
731 for (i = 0; i < state->nr_cbufs; i++) {
732 r300_tex_set_tiling_flags(r300,
733 r300_resource(state->cbufs[i]->texture),
734 state->cbufs[i]->u.tex.level);
735 }
736 if (state->zsbuf) {
737 r300_tex_set_tiling_flags(r300,
738 r300_resource(state->zsbuf->texture),
739 state->zsbuf->u.tex.level);
740 }
741 }
742
743 static void r300_print_fb_surf_info(struct pipe_surface *surf, unsigned index,
744 const char *binding)
745 {
746 struct pipe_resource *tex = surf->texture;
747 struct r300_resource *rtex = r300_resource(tex);
748
749 fprintf(stderr,
750 "r300: %s[%i] Dim: %ix%i, Firstlayer: %i, "
751 "Lastlayer: %i, Level: %i, Format: %s\n"
752
753 "r300: TEX: Macro: %s, Micro: %s, Pitch: %i, "
754 "Dim: %ix%ix%i, LastLevel: %i, Format: %s\n",
755
756 binding, index, surf->width, surf->height,
757 surf->u.tex.first_layer, surf->u.tex.last_layer, surf->u.tex.level,
758 util_format_short_name(surf->format),
759
760 rtex->tex.macrotile[0] ? "YES" : " NO",
761 rtex->tex.microtile ? "YES" : " NO",
762 rtex->tex.stride_in_pixels[0],
763 tex->width0, tex->height0, tex->depth0,
764 tex->last_level, util_format_short_name(tex->format));
765 }
766
767 void r300_mark_fb_state_dirty(struct r300_context *r300,
768 enum r300_fb_state_change change)
769 {
770 struct pipe_framebuffer_state *state = r300->fb_state.state;
771 boolean can_hyperz = r300->rws->get_value(r300->rws, RADEON_VID_CAN_HYPERZ);
772
773 r300_mark_atom_dirty(r300, &r300->gpu_flush);
774 r300_mark_atom_dirty(r300, &r300->fb_state);
775
776 /* What is marked as dirty depends on the enum r300_fb_state_change. */
777 if (change == R300_CHANGED_FB_STATE) {
778 r300_mark_atom_dirty(r300, &r300->aa_state);
779 r300_mark_atom_dirty(r300, &r300->dsa_state); /* for AlphaRef */
780 r300_set_blend_color(&r300->context, r300->blend_color_state.state);
781 }
782
783 if (change == R300_CHANGED_FB_STATE ||
784 change == R300_CHANGED_HYPERZ_FLAG) {
785 r300_mark_atom_dirty(r300, &r300->hyperz_state);
786 }
787
788 if (change == R300_CHANGED_FB_STATE ||
789 change == R300_CHANGED_MULTIWRITE) {
790 r300_mark_atom_dirty(r300, &r300->fb_state_pipelined);
791 }
792
793 /* Now compute the fb_state atom size. */
794 r300->fb_state.size = 2 + (8 * state->nr_cbufs);
795
796 if (r300->cbzb_clear)
797 r300->fb_state.size += 10;
798 else if (state->zsbuf) {
799 r300->fb_state.size += 10;
800 if (can_hyperz)
801 r300->fb_state.size += 8;
802 }
803
804 /* The size of the rest of atoms stays the same. */
805 }
806
807 static void
808 r300_set_framebuffer_state(struct pipe_context* pipe,
809 const struct pipe_framebuffer_state* state)
810 {
811 struct r300_context* r300 = r300_context(pipe);
812 struct r300_aa_state *aa = (struct r300_aa_state*)r300->aa_state.state;
813 struct pipe_framebuffer_state *old_state = r300->fb_state.state;
814 unsigned max_width, max_height, i;
815 uint32_t zbuffer_bpp = 0;
816
817 if (r300->screen->caps.is_r500) {
818 max_width = max_height = 4096;
819 } else if (r300->screen->caps.is_r400) {
820 max_width = max_height = 4021;
821 } else {
822 max_width = max_height = 2560;
823 }
824
825 if (state->width > max_width || state->height > max_height) {
826 fprintf(stderr, "r300: Implementation error: Render targets are too "
827 "big in %s, refusing to bind framebuffer state!\n", __FUNCTION__);
828 return;
829 }
830
831 if (old_state->zsbuf && r300->zmask_in_use && !r300->hyperz_locked) {
832 /* There is a zmask in use, what are we gonna do? */
833 if (state->zsbuf) {
834 if (!pipe_surface_equal(old_state->zsbuf, state->zsbuf)) {
835 /* Decompress the currently bound zbuffer before we bind another one. */
836 r300_decompress_zmask(r300);
837 r300->hiz_in_use = FALSE;
838 }
839 } else {
840 /* We don't bind another zbuffer, so lock the current one. */
841 r300->hyperz_locked = TRUE;
842 pipe_surface_reference(&r300->locked_zbuffer, old_state->zsbuf);
843 }
844 } else if (r300->hyperz_locked && r300->locked_zbuffer) {
845 /* We have a locked zbuffer now, what are we gonna do? */
846 if (state->zsbuf) {
847 if (!pipe_surface_equal(r300->locked_zbuffer, state->zsbuf)) {
848 /* We are binding some other zbuffer, so decompress the locked one,
849 * it gets unlocked automatically. */
850 r300_decompress_zmask_locked_unsafe(r300);
851 r300->hiz_in_use = FALSE;
852 } else {
853 /* We are binding the locked zbuffer again, so unlock it. */
854 r300->hyperz_locked = FALSE;
855 }
856 }
857 }
858 assert(state->zsbuf || r300->hyperz_locked || !r300->zmask_in_use);
859
860 /* Need to reset clamping or colormask. */
861 r300_mark_atom_dirty(r300, &r300->blend_state);
862
863 /* If zsbuf is set from NULL to non-NULL or vice versa.. */
864 if (!!old_state->zsbuf != !!state->zsbuf) {
865 r300_mark_atom_dirty(r300, &r300->dsa_state);
866 }
867
868 /* The tiling flags are dependent on the surface miplevel, unfortunately. */
869 r300_fb_set_tiling_flags(r300, state);
870
871 util_copy_framebuffer_state(r300->fb_state.state, state);
872
873 if (!r300->hyperz_locked) {
874 pipe_surface_reference(&r300->locked_zbuffer, NULL);
875 }
876
877 r300_mark_fb_state_dirty(r300, R300_CHANGED_FB_STATE);
878
879 if (state->zsbuf) {
880 switch (util_format_get_blocksize(state->zsbuf->texture->format)) {
881 case 2:
882 zbuffer_bpp = 16;
883 break;
884 case 4:
885 zbuffer_bpp = 24;
886 break;
887 }
888
889 /* Polygon offset depends on the zbuffer bit depth. */
890 if (r300->zbuffer_bpp != zbuffer_bpp) {
891 r300->zbuffer_bpp = zbuffer_bpp;
892
893 if (r300->polygon_offset_enabled)
894 r300_mark_atom_dirty(r300, &r300->rs_state);
895 }
896 }
897
898 /* Set up AA config. */
899 if (state->nr_cbufs && state->cbufs[0]->texture->nr_samples > 1) {
900 aa->aa_config = R300_GB_AA_CONFIG_AA_ENABLE;
901
902 switch (state->cbufs[0]->texture->nr_samples) {
903 case 2:
904 aa->aa_config |= R300_GB_AA_CONFIG_NUM_AA_SUBSAMPLES_2;
905 break;
906 case 3:
907 aa->aa_config |= R300_GB_AA_CONFIG_NUM_AA_SUBSAMPLES_3;
908 break;
909 case 4:
910 aa->aa_config |= R300_GB_AA_CONFIG_NUM_AA_SUBSAMPLES_4;
911 break;
912 case 6:
913 aa->aa_config |= R300_GB_AA_CONFIG_NUM_AA_SUBSAMPLES_6;
914 break;
915 }
916 } else {
917 aa->aa_config = 0;
918 }
919
920 if (DBG_ON(r300, DBG_FB)) {
921 fprintf(stderr, "r300: set_framebuffer_state:\n");
922 for (i = 0; i < state->nr_cbufs; i++) {
923 r300_print_fb_surf_info(state->cbufs[i], i, "CB");
924 }
925 if (state->zsbuf) {
926 r300_print_fb_surf_info(state->zsbuf, 0, "ZB");
927 }
928 }
929 }
930
931 /* Create fragment shader state. */
932 static void* r300_create_fs_state(struct pipe_context* pipe,
933 const struct pipe_shader_state* shader)
934 {
935 struct r300_fragment_shader* fs = NULL;
936
937 fs = (struct r300_fragment_shader*)CALLOC_STRUCT(r300_fragment_shader);
938
939 /* Copy state directly into shader. */
940 fs->state = *shader;
941 fs->state.tokens = tgsi_dup_tokens(shader->tokens);
942
943 return (void*)fs;
944 }
945
946 void r300_mark_fs_code_dirty(struct r300_context *r300)
947 {
948 struct r300_fragment_shader* fs = r300_fs(r300);
949
950 r300_mark_atom_dirty(r300, &r300->fs);
951 r300_mark_atom_dirty(r300, &r300->fs_rc_constant_state);
952 r300_mark_atom_dirty(r300, &r300->fs_constants);
953 r300->fs.size = fs->shader->cb_code_size;
954
955 if (r300->screen->caps.is_r500) {
956 r300->fs_rc_constant_state.size = fs->shader->rc_state_count * 7;
957 r300->fs_constants.size = fs->shader->externals_count * 4 + 3;
958 } else {
959 r300->fs_rc_constant_state.size = fs->shader->rc_state_count * 5;
960 r300->fs_constants.size = fs->shader->externals_count * 4 + 1;
961 }
962
963 ((struct r300_constant_buffer*)r300->fs_constants.state)->remap_table =
964 fs->shader->code.constants_remap_table;
965 }
966
967 /* Bind fragment shader state. */
968 static void r300_bind_fs_state(struct pipe_context* pipe, void* shader)
969 {
970 struct r300_context* r300 = r300_context(pipe);
971 struct r300_fragment_shader* fs = (struct r300_fragment_shader*)shader;
972
973 if (fs == NULL) {
974 r300->fs.state = NULL;
975 return;
976 }
977
978 r300->fs.state = fs;
979 r300->fs_status = FRAGMENT_SHADER_DIRTY;
980
981 r300_mark_atom_dirty(r300, &r300->rs_block_state); /* Will be updated before the emission. */
982 }
983
984 /* Delete fragment shader state. */
985 static void r300_delete_fs_state(struct pipe_context* pipe, void* shader)
986 {
987 struct r300_fragment_shader* fs = (struct r300_fragment_shader*)shader;
988 struct r300_fragment_shader_code *tmp, *ptr = fs->first;
989
990 while (ptr) {
991 tmp = ptr;
992 ptr = ptr->next;
993 rc_constants_destroy(&tmp->code.constants);
994 FREE(tmp->cb_code);
995 FREE(tmp);
996 }
997 FREE((void*)fs->state.tokens);
998 FREE(shader);
999 }
1000
1001 static void r300_set_polygon_stipple(struct pipe_context* pipe,
1002 const struct pipe_poly_stipple* state)
1003 {
1004 /* XXX no idea how to set this up, but not terribly important */
1005 }
1006
1007 /* Create a new rasterizer state based on the CSO rasterizer state.
1008 *
1009 * This is a very large chunk of state, and covers most of the graphics
1010 * backend (GB), geometry assembly (GA), and setup unit (SU) blocks.
1011 *
1012 * In a not entirely unironic sidenote, this state has nearly nothing to do
1013 * with the actual block on the Radeon called the rasterizer (RS). */
1014 static void* r300_create_rs_state(struct pipe_context* pipe,
1015 const struct pipe_rasterizer_state* state)
1016 {
1017 struct r300_rs_state* rs = CALLOC_STRUCT(r300_rs_state);
1018 float psiz;
1019 uint32_t vap_control_status; /* R300_VAP_CNTL_STATUS: 0x2140 */
1020 uint32_t point_size; /* R300_GA_POINT_SIZE: 0x421c */
1021 uint32_t point_minmax; /* R300_GA_POINT_MINMAX: 0x4230 */
1022 uint32_t line_control; /* R300_GA_LINE_CNTL: 0x4234 */
1023 uint32_t polygon_offset_enable; /* R300_SU_POLY_OFFSET_ENABLE: 0x42b4 */
1024 uint32_t cull_mode; /* R300_SU_CULL_MODE: 0x42b8 */
1025 uint32_t line_stipple_config; /* R300_GA_LINE_STIPPLE_CONFIG: 0x4328 */
1026 uint32_t line_stipple_value; /* R300_GA_LINE_STIPPLE_VALUE: 0x4260 */
1027 uint32_t polygon_mode; /* R300_GA_POLY_MODE: 0x4288 */
1028 uint32_t clip_rule; /* R300_SC_CLIP_RULE: 0x43D0 */
1029 uint32_t round_mode; /* R300_GA_ROUND_MODE: 0x428c */
1030
1031 /* Point sprites texture coordinates, 0: lower left, 1: upper right */
1032 float point_texcoord_left = 0; /* R300_GA_POINT_S0: 0x4200 */
1033 float point_texcoord_bottom = 0;/* R300_GA_POINT_T0: 0x4204 */
1034 float point_texcoord_right = 1; /* R300_GA_POINT_S1: 0x4208 */
1035 float point_texcoord_top = 0; /* R300_GA_POINT_T1: 0x420c */
1036 boolean vclamp = state->clamp_vertex_color;
1037 CB_LOCALS;
1038
1039 /* Copy rasterizer state. */
1040 rs->rs = *state;
1041 rs->rs_draw = *state;
1042
1043 rs->rs.sprite_coord_enable = state->point_quad_rasterization *
1044 state->sprite_coord_enable;
1045
1046 /* Override some states for Draw. */
1047 rs->rs_draw.sprite_coord_enable = 0; /* We can do this in HW. */
1048
1049 #ifdef PIPE_ARCH_LITTLE_ENDIAN
1050 vap_control_status = R300_VC_NO_SWAP;
1051 #else
1052 vap_control_status = R300_VC_32BIT_SWAP;
1053 #endif
1054
1055 /* If no TCL engine is present, turn off the HW TCL. */
1056 if (!r300_screen(pipe->screen)->caps.has_tcl) {
1057 vap_control_status |= R300_VAP_TCL_BYPASS;
1058 }
1059
1060 /* Point size width and height. */
1061 point_size =
1062 pack_float_16_6x(state->point_size) |
1063 (pack_float_16_6x(state->point_size) << R300_POINTSIZE_X_SHIFT);
1064
1065 /* Point size clamping. */
1066 if (state->point_size_per_vertex) {
1067 /* Per-vertex point size.
1068 * Clamp to [0, max FB size] */
1069 psiz = pipe->screen->get_paramf(pipe->screen,
1070 PIPE_CAP_MAX_POINT_WIDTH);
1071 point_minmax =
1072 pack_float_16_6x(psiz) << R300_GA_POINT_MINMAX_MAX_SHIFT;
1073 } else {
1074 /* We cannot disable the point-size vertex output,
1075 * so clamp it. */
1076 psiz = state->point_size;
1077 point_minmax =
1078 (pack_float_16_6x(psiz) << R300_GA_POINT_MINMAX_MIN_SHIFT) |
1079 (pack_float_16_6x(psiz) << R300_GA_POINT_MINMAX_MAX_SHIFT);
1080 }
1081
1082 /* Line control. */
1083 line_control = pack_float_16_6x(state->line_width) |
1084 R300_GA_LINE_CNTL_END_TYPE_COMP;
1085
1086 /* Enable polygon mode */
1087 polygon_mode = 0;
1088 if (state->fill_front != PIPE_POLYGON_MODE_FILL ||
1089 state->fill_back != PIPE_POLYGON_MODE_FILL) {
1090 polygon_mode = R300_GA_POLY_MODE_DUAL;
1091 }
1092
1093 /* Front face */
1094 if (state->front_ccw)
1095 cull_mode = R300_FRONT_FACE_CCW;
1096 else
1097 cull_mode = R300_FRONT_FACE_CW;
1098
1099 /* Polygon offset */
1100 polygon_offset_enable = 0;
1101 if (util_get_offset(state, state->fill_front)) {
1102 polygon_offset_enable |= R300_FRONT_ENABLE;
1103 }
1104 if (util_get_offset(state, state->fill_back)) {
1105 polygon_offset_enable |= R300_BACK_ENABLE;
1106 }
1107
1108 rs->polygon_offset_enable = polygon_offset_enable != 0;
1109
1110 /* Polygon mode */
1111 if (polygon_mode) {
1112 polygon_mode |=
1113 r300_translate_polygon_mode_front(state->fill_front);
1114 polygon_mode |=
1115 r300_translate_polygon_mode_back(state->fill_back);
1116 }
1117
1118 if (state->cull_face & PIPE_FACE_FRONT) {
1119 cull_mode |= R300_CULL_FRONT;
1120 }
1121 if (state->cull_face & PIPE_FACE_BACK) {
1122 cull_mode |= R300_CULL_BACK;
1123 }
1124
1125 if (state->line_stipple_enable) {
1126 line_stipple_config =
1127 R300_GA_LINE_STIPPLE_CONFIG_LINE_RESET_LINE |
1128 (fui((float)state->line_stipple_factor) &
1129 R300_GA_LINE_STIPPLE_CONFIG_STIPPLE_SCALE_MASK);
1130 /* XXX this might need to be scaled up */
1131 line_stipple_value = state->line_stipple_pattern;
1132 } else {
1133 line_stipple_config = 0;
1134 line_stipple_value = 0;
1135 }
1136
1137 if (state->flatshade) {
1138 rs->color_control = R300_SHADE_MODEL_FLAT;
1139 } else {
1140 rs->color_control = R300_SHADE_MODEL_SMOOTH;
1141 }
1142
1143 clip_rule = state->scissor ? 0xAAAA : 0xFFFF;
1144
1145 /* Point sprites coord mode */
1146 if (rs->rs.sprite_coord_enable) {
1147 switch (state->sprite_coord_mode) {
1148 case PIPE_SPRITE_COORD_UPPER_LEFT:
1149 point_texcoord_top = 0.0f;
1150 point_texcoord_bottom = 1.0f;
1151 break;
1152 case PIPE_SPRITE_COORD_LOWER_LEFT:
1153 point_texcoord_top = 1.0f;
1154 point_texcoord_bottom = 0.0f;
1155 break;
1156 }
1157 }
1158
1159 /* Vertex color clamping. FP20 means no clamping. */
1160 round_mode =
1161 R300_GA_ROUND_MODE_GEOMETRY_ROUND_NEAREST |
1162 (!vclamp ? (R300_GA_ROUND_MODE_RGB_CLAMP_FP20 |
1163 R300_GA_ROUND_MODE_ALPHA_CLAMP_FP20) : 0);
1164
1165 /* Build the main command buffer. */
1166 BEGIN_CB(rs->cb_main, RS_STATE_MAIN_SIZE);
1167 OUT_CB_REG(R300_VAP_CNTL_STATUS, vap_control_status);
1168 OUT_CB_REG(R300_GA_POINT_SIZE, point_size);
1169 OUT_CB_REG_SEQ(R300_GA_POINT_MINMAX, 2);
1170 OUT_CB(point_minmax);
1171 OUT_CB(line_control);
1172 OUT_CB_REG_SEQ(R300_SU_POLY_OFFSET_ENABLE, 2);
1173 OUT_CB(polygon_offset_enable);
1174 rs->cull_mode_index = 9;
1175 OUT_CB(cull_mode);
1176 OUT_CB_REG(R300_GA_LINE_STIPPLE_CONFIG, line_stipple_config);
1177 OUT_CB_REG(R300_GA_LINE_STIPPLE_VALUE, line_stipple_value);
1178 OUT_CB_REG(R300_GA_POLY_MODE, polygon_mode);
1179 OUT_CB_REG(R300_GA_ROUND_MODE, round_mode);
1180 OUT_CB_REG(R300_SC_CLIP_RULE, clip_rule);
1181 OUT_CB_REG_SEQ(R300_GA_POINT_S0, 4);
1182 OUT_CB_32F(point_texcoord_left);
1183 OUT_CB_32F(point_texcoord_bottom);
1184 OUT_CB_32F(point_texcoord_right);
1185 OUT_CB_32F(point_texcoord_top);
1186 END_CB;
1187
1188 /* Build the two command buffers for polygon offset setup. */
1189 if (polygon_offset_enable) {
1190 float scale = state->offset_scale * 12;
1191 float offset = state->offset_units * 4;
1192
1193 BEGIN_CB(rs->cb_poly_offset_zb16, 5);
1194 OUT_CB_REG_SEQ(R300_SU_POLY_OFFSET_FRONT_SCALE, 4);
1195 OUT_CB_32F(scale);
1196 OUT_CB_32F(offset);
1197 OUT_CB_32F(scale);
1198 OUT_CB_32F(offset);
1199 END_CB;
1200
1201 offset = state->offset_units * 2;
1202
1203 BEGIN_CB(rs->cb_poly_offset_zb24, 5);
1204 OUT_CB_REG_SEQ(R300_SU_POLY_OFFSET_FRONT_SCALE, 4);
1205 OUT_CB_32F(scale);
1206 OUT_CB_32F(offset);
1207 OUT_CB_32F(scale);
1208 OUT_CB_32F(offset);
1209 END_CB;
1210 }
1211
1212 return (void*)rs;
1213 }
1214
1215 /* Bind rasterizer state. */
1216 static void r300_bind_rs_state(struct pipe_context* pipe, void* state)
1217 {
1218 struct r300_context* r300 = r300_context(pipe);
1219 struct r300_rs_state* rs = (struct r300_rs_state*)state;
1220 int last_sprite_coord_enable = r300->sprite_coord_enable;
1221 boolean last_two_sided_color = r300->two_sided_color;
1222 boolean last_frag_clamp = r300->frag_clamp;
1223
1224 if (r300->draw && rs) {
1225 draw_set_rasterizer_state(r300->draw, &rs->rs_draw, state);
1226 }
1227
1228 if (rs) {
1229 r300->polygon_offset_enabled = rs->polygon_offset_enable;
1230 r300->sprite_coord_enable = rs->rs.sprite_coord_enable;
1231 r300->two_sided_color = rs->rs.light_twoside;
1232 r300->frag_clamp = rs->rs.clamp_fragment_color;
1233 } else {
1234 r300->polygon_offset_enabled = FALSE;
1235 r300->sprite_coord_enable = 0;
1236 r300->two_sided_color = FALSE;
1237 r300->frag_clamp = FALSE;
1238 }
1239
1240 UPDATE_STATE(state, r300->rs_state);
1241 r300->rs_state.size = RS_STATE_MAIN_SIZE + (r300->polygon_offset_enabled ? 5 : 0);
1242
1243 if (last_sprite_coord_enable != r300->sprite_coord_enable ||
1244 last_two_sided_color != r300->two_sided_color) {
1245 r300_mark_atom_dirty(r300, &r300->rs_block_state);
1246 }
1247
1248 if (last_frag_clamp != r300->frag_clamp &&
1249 r300->fs_status == FRAGMENT_SHADER_VALID) {
1250 r300->fs_status = FRAGMENT_SHADER_MAYBE_DIRTY;
1251 }
1252 }
1253
1254 /* Free rasterizer state. */
1255 static void r300_delete_rs_state(struct pipe_context* pipe, void* state)
1256 {
1257 FREE(state);
1258 }
1259
1260 static void*
1261 r300_create_sampler_state(struct pipe_context* pipe,
1262 const struct pipe_sampler_state* state)
1263 {
1264 struct r300_context* r300 = r300_context(pipe);
1265 struct r300_sampler_state* sampler = CALLOC_STRUCT(r300_sampler_state);
1266 boolean is_r500 = r300->screen->caps.is_r500;
1267 int lod_bias;
1268
1269 sampler->state = *state;
1270
1271 /* r300 doesn't handle CLAMP and MIRROR_CLAMP correctly when either MAG
1272 * or MIN filter is NEAREST. Since texwrap produces same results
1273 * for CLAMP and CLAMP_TO_EDGE, we use them instead. */
1274 if (sampler->state.min_img_filter == PIPE_TEX_FILTER_NEAREST ||
1275 sampler->state.mag_img_filter == PIPE_TEX_FILTER_NEAREST) {
1276 /* Wrap S. */
1277 if (sampler->state.wrap_s == PIPE_TEX_WRAP_CLAMP)
1278 sampler->state.wrap_s = PIPE_TEX_WRAP_CLAMP_TO_EDGE;
1279 else if (sampler->state.wrap_s == PIPE_TEX_WRAP_MIRROR_CLAMP)
1280 sampler->state.wrap_s = PIPE_TEX_WRAP_MIRROR_CLAMP_TO_EDGE;
1281
1282 /* Wrap T. */
1283 if (sampler->state.wrap_t == PIPE_TEX_WRAP_CLAMP)
1284 sampler->state.wrap_t = PIPE_TEX_WRAP_CLAMP_TO_EDGE;
1285 else if (sampler->state.wrap_t == PIPE_TEX_WRAP_MIRROR_CLAMP)
1286 sampler->state.wrap_t = PIPE_TEX_WRAP_MIRROR_CLAMP_TO_EDGE;
1287
1288 /* Wrap R. */
1289 if (sampler->state.wrap_r == PIPE_TEX_WRAP_CLAMP)
1290 sampler->state.wrap_r = PIPE_TEX_WRAP_CLAMP_TO_EDGE;
1291 else if (sampler->state.wrap_r == PIPE_TEX_WRAP_MIRROR_CLAMP)
1292 sampler->state.wrap_r = PIPE_TEX_WRAP_MIRROR_CLAMP_TO_EDGE;
1293 }
1294
1295 sampler->filter0 |=
1296 (r300_translate_wrap(sampler->state.wrap_s) << R300_TX_WRAP_S_SHIFT) |
1297 (r300_translate_wrap(sampler->state.wrap_t) << R300_TX_WRAP_T_SHIFT) |
1298 (r300_translate_wrap(sampler->state.wrap_r) << R300_TX_WRAP_R_SHIFT);
1299
1300 sampler->filter0 |= r300_translate_tex_filters(state->min_img_filter,
1301 state->mag_img_filter,
1302 state->min_mip_filter,
1303 state->max_anisotropy > 0);
1304
1305 sampler->filter0 |= r300_anisotropy(state->max_anisotropy);
1306
1307 /* Unfortunately, r300-r500 don't support floating-point mipmap lods. */
1308 /* We must pass these to the merge function to clamp them properly. */
1309 sampler->min_lod = (unsigned)MAX2(state->min_lod, 0);
1310 sampler->max_lod = (unsigned)MAX2(ceilf(state->max_lod), 0);
1311
1312 lod_bias = CLAMP((int)(state->lod_bias * 32 + 1), -(1 << 9), (1 << 9) - 1);
1313
1314 sampler->filter1 |= (lod_bias << R300_LOD_BIAS_SHIFT) & R300_LOD_BIAS_MASK;
1315
1316 /* This is very high quality anisotropic filtering for R5xx.
1317 * It's good for benchmarking the performance of texturing but
1318 * in practice we don't want to slow down the driver because it's
1319 * a pretty good performance killer. Feel free to play with it. */
1320 if (DBG_ON(r300, DBG_ANISOHQ) && is_r500) {
1321 sampler->filter1 |= r500_anisotropy(state->max_anisotropy);
1322 }
1323
1324 /* R500-specific fixups and optimizations */
1325 if (r300->screen->caps.is_r500) {
1326 sampler->filter1 |= R500_BORDER_FIX;
1327 }
1328
1329 return (void*)sampler;
1330 }
1331
1332 static void r300_bind_sampler_states(struct pipe_context* pipe,
1333 unsigned count,
1334 void** states)
1335 {
1336 struct r300_context* r300 = r300_context(pipe);
1337 struct r300_textures_state* state =
1338 (struct r300_textures_state*)r300->textures_state.state;
1339 unsigned tex_units = r300->screen->caps.num_tex_units;
1340
1341 if (count > tex_units) {
1342 return;
1343 }
1344
1345 memcpy(state->sampler_states, states, sizeof(void*) * count);
1346 state->sampler_state_count = count;
1347
1348 r300_mark_atom_dirty(r300, &r300->textures_state);
1349 }
1350
1351 static void r300_lacks_vertex_textures(struct pipe_context* pipe,
1352 unsigned count,
1353 void** states)
1354 {
1355 }
1356
1357 static void r300_delete_sampler_state(struct pipe_context* pipe, void* state)
1358 {
1359 FREE(state);
1360 }
1361
1362 static uint32_t r300_assign_texture_cache_region(unsigned index, unsigned num)
1363 {
1364 /* This looks like a hack, but I believe it's suppose to work like
1365 * that. To illustrate how this works, let's assume you have 5 textures.
1366 * From docs, 5 and the successive numbers are:
1367 *
1368 * FOURTH_1 = 5
1369 * FOURTH_2 = 6
1370 * FOURTH_3 = 7
1371 * EIGHTH_0 = 8
1372 * EIGHTH_1 = 9
1373 *
1374 * First 3 textures will get 3/4 of size of the cache, divived evenly
1375 * between them. The last 1/4 of the cache must be divided between
1376 * the last 2 textures, each will therefore get 1/8 of the cache.
1377 * Why not just to use "5 + texture_index" ?
1378 *
1379 * This simple trick works for all "num" <= 16.
1380 */
1381 if (num <= 1)
1382 return R300_TX_CACHE(R300_TX_CACHE_WHOLE);
1383 else
1384 return R300_TX_CACHE(num + index);
1385 }
1386
1387 static void r300_set_fragment_sampler_views(struct pipe_context* pipe,
1388 unsigned count,
1389 struct pipe_sampler_view** views)
1390 {
1391 struct r300_context* r300 = r300_context(pipe);
1392 struct r300_textures_state* state =
1393 (struct r300_textures_state*)r300->textures_state.state;
1394 struct r300_resource *texture;
1395 unsigned i, real_num_views = 0, view_index = 0;
1396 unsigned tex_units = r300->screen->caps.num_tex_units;
1397 boolean dirty_tex = FALSE;
1398
1399 if (count > tex_units) {
1400 return;
1401 }
1402
1403 /* Calculate the real number of views. */
1404 for (i = 0; i < count; i++) {
1405 if (views[i])
1406 real_num_views++;
1407 }
1408
1409 for (i = 0; i < count; i++) {
1410 pipe_sampler_view_reference(
1411 (struct pipe_sampler_view**)&state->sampler_views[i],
1412 views[i]);
1413
1414 if (!views[i]) {
1415 continue;
1416 }
1417
1418 /* A new sampler view (= texture)... */
1419 dirty_tex = TRUE;
1420
1421 /* Set the texrect factor in the fragment shader.
1422 * Needed for RECT and NPOT fallback. */
1423 texture = r300_resource(views[i]->texture);
1424 if (texture->tex.is_npot) {
1425 r300_mark_atom_dirty(r300, &r300->fs_rc_constant_state);
1426 }
1427
1428 state->sampler_views[i]->texcache_region =
1429 r300_assign_texture_cache_region(view_index, real_num_views);
1430 view_index++;
1431 }
1432
1433 for (i = count; i < tex_units; i++) {
1434 if (state->sampler_views[i]) {
1435 pipe_sampler_view_reference(
1436 (struct pipe_sampler_view**)&state->sampler_views[i],
1437 NULL);
1438 }
1439 }
1440
1441 state->sampler_view_count = count;
1442
1443 r300_mark_atom_dirty(r300, &r300->textures_state);
1444
1445 if (dirty_tex) {
1446 r300_mark_atom_dirty(r300, &r300->texture_cache_inval);
1447 }
1448 }
1449
1450 static struct pipe_sampler_view *
1451 r300_create_sampler_view(struct pipe_context *pipe,
1452 struct pipe_resource *texture,
1453 const struct pipe_sampler_view *templ)
1454 {
1455 struct r300_sampler_view *view = CALLOC_STRUCT(r300_sampler_view);
1456 struct r300_resource *tex = r300_resource(texture);
1457 boolean is_r500 = r300_screen(pipe->screen)->caps.is_r500;
1458 boolean dxtc_swizzle = r300_screen(pipe->screen)->caps.dxtc_swizzle;
1459
1460 if (view) {
1461 view->base = *templ;
1462 view->base.reference.count = 1;
1463 view->base.context = pipe;
1464 view->base.texture = NULL;
1465 pipe_resource_reference(&view->base.texture, texture);
1466
1467 view->swizzle[0] = templ->swizzle_r;
1468 view->swizzle[1] = templ->swizzle_g;
1469 view->swizzle[2] = templ->swizzle_b;
1470 view->swizzle[3] = templ->swizzle_a;
1471
1472 view->format = tex->tx_format;
1473 view->format.format1 |= r300_translate_texformat(templ->format,
1474 view->swizzle,
1475 is_r500,
1476 dxtc_swizzle);
1477 if (is_r500) {
1478 view->format.format2 |= r500_tx_format_msb_bit(templ->format);
1479 }
1480 }
1481
1482 return (struct pipe_sampler_view*)view;
1483 }
1484
1485 static void
1486 r300_sampler_view_destroy(struct pipe_context *pipe,
1487 struct pipe_sampler_view *view)
1488 {
1489 pipe_resource_reference(&view->texture, NULL);
1490 FREE(view);
1491 }
1492
1493 static void r300_set_scissor_state(struct pipe_context* pipe,
1494 const struct pipe_scissor_state* state)
1495 {
1496 struct r300_context* r300 = r300_context(pipe);
1497
1498 memcpy(r300->scissor_state.state, state,
1499 sizeof(struct pipe_scissor_state));
1500
1501 r300_mark_atom_dirty(r300, &r300->scissor_state);
1502 }
1503
1504 static void r300_set_viewport_state(struct pipe_context* pipe,
1505 const struct pipe_viewport_state* state)
1506 {
1507 struct r300_context* r300 = r300_context(pipe);
1508 struct r300_viewport_state* viewport =
1509 (struct r300_viewport_state*)r300->viewport_state.state;
1510
1511 r300->viewport = *state;
1512
1513 if (r300->draw) {
1514 draw_set_viewport_state(r300->draw, state);
1515 viewport->vte_control = R300_VTX_XY_FMT | R300_VTX_Z_FMT;
1516 return;
1517 }
1518
1519 /* Do the transform in HW. */
1520 viewport->vte_control = R300_VTX_W0_FMT;
1521
1522 if (state->scale[0] != 1.0f) {
1523 viewport->xscale = state->scale[0];
1524 viewport->vte_control |= R300_VPORT_X_SCALE_ENA;
1525 }
1526 if (state->scale[1] != 1.0f) {
1527 viewport->yscale = state->scale[1];
1528 viewport->vte_control |= R300_VPORT_Y_SCALE_ENA;
1529 }
1530 if (state->scale[2] != 1.0f) {
1531 viewport->zscale = state->scale[2];
1532 viewport->vte_control |= R300_VPORT_Z_SCALE_ENA;
1533 }
1534 if (state->translate[0] != 0.0f) {
1535 viewport->xoffset = state->translate[0];
1536 viewport->vte_control |= R300_VPORT_X_OFFSET_ENA;
1537 }
1538 if (state->translate[1] != 0.0f) {
1539 viewport->yoffset = state->translate[1];
1540 viewport->vte_control |= R300_VPORT_Y_OFFSET_ENA;
1541 }
1542 if (state->translate[2] != 0.0f) {
1543 viewport->zoffset = state->translate[2];
1544 viewport->vte_control |= R300_VPORT_Z_OFFSET_ENA;
1545 }
1546
1547 r300_mark_atom_dirty(r300, &r300->viewport_state);
1548 if (r300->fs.state && r300_fs(r300)->shader &&
1549 r300_fs(r300)->shader->inputs.wpos != ATTR_UNUSED) {
1550 r300_mark_atom_dirty(r300, &r300->fs_rc_constant_state);
1551 }
1552 }
1553
1554 static void r300_set_vertex_buffers(struct pipe_context* pipe,
1555 unsigned count,
1556 const struct pipe_vertex_buffer* buffers)
1557 {
1558 struct r300_context* r300 = r300_context(pipe);
1559 unsigned i;
1560 struct pipe_vertex_buffer dummy_vb = {0};
1561
1562 /* There must be at least one vertex buffer set, otherwise it locks up. */
1563 if (!count) {
1564 dummy_vb.buffer = r300->dummy_vb;
1565 buffers = &dummy_vb;
1566 count = 1;
1567 }
1568
1569 u_vbuf_mgr_set_vertex_buffers(r300->vbuf_mgr, count, buffers);
1570
1571 if (r300->screen->caps.has_tcl) {
1572 /* HW TCL. */
1573 for (i = 0; i < count; i++) {
1574 if (buffers[i].buffer &&
1575 !r300_resource(buffers[i].buffer)->b.user_ptr) {
1576 }
1577 }
1578 r300->vertex_arrays_dirty = TRUE;
1579 } else {
1580 /* SW TCL. */
1581 draw_set_vertex_buffers(r300->draw, count, buffers);
1582 }
1583 }
1584
1585 static void r300_set_index_buffer(struct pipe_context* pipe,
1586 const struct pipe_index_buffer *ib)
1587 {
1588 struct r300_context* r300 = r300_context(pipe);
1589
1590 if (ib && ib->buffer) {
1591 assert(ib->offset % ib->index_size == 0);
1592
1593 pipe_resource_reference(&r300->index_buffer.buffer, ib->buffer);
1594 memcpy(&r300->index_buffer, ib, sizeof(r300->index_buffer));
1595 r300->index_buffer.offset /= r300->index_buffer.index_size;
1596 }
1597 else {
1598 pipe_resource_reference(&r300->index_buffer.buffer, NULL);
1599 memset(&r300->index_buffer, 0, sizeof(r300->index_buffer));
1600 }
1601
1602 if (!r300->screen->caps.has_tcl) {
1603 draw_set_index_buffer(r300->draw, ib);
1604 }
1605 }
1606
1607 /* Initialize the PSC tables. */
1608 static void r300_vertex_psc(struct r300_vertex_element_state *velems)
1609 {
1610 struct r300_vertex_stream_state *vstream = &velems->vertex_stream;
1611 uint16_t type, swizzle;
1612 enum pipe_format format;
1613 unsigned i;
1614
1615 /* Vertex shaders have no semantics on their inputs,
1616 * so PSC should just route stuff based on the vertex elements,
1617 * and not on attrib information. */
1618 for (i = 0; i < velems->count; i++) {
1619 format = velems->velem[i].src_format;
1620
1621 type = r300_translate_vertex_data_type(format);
1622 if (type == R300_INVALID_FORMAT) {
1623 fprintf(stderr, "r300: Bad vertex format %s.\n",
1624 util_format_short_name(format));
1625 assert(0);
1626 abort();
1627 }
1628
1629 type |= i << R300_DST_VEC_LOC_SHIFT;
1630 swizzle = r300_translate_vertex_data_swizzle(format);
1631
1632 if (i & 1) {
1633 vstream->vap_prog_stream_cntl[i >> 1] |= type << 16;
1634 vstream->vap_prog_stream_cntl_ext[i >> 1] |= swizzle << 16;
1635 } else {
1636 vstream->vap_prog_stream_cntl[i >> 1] |= type;
1637 vstream->vap_prog_stream_cntl_ext[i >> 1] |= swizzle;
1638 }
1639 }
1640
1641 /* Set the last vector in the PSC. */
1642 if (i) {
1643 i -= 1;
1644 }
1645 vstream->vap_prog_stream_cntl[i >> 1] |=
1646 (R300_LAST_VEC << (i & 1 ? 16 : 0));
1647
1648 vstream->count = (i >> 1) + 1;
1649 }
1650
1651 static void* r300_create_vertex_elements_state(struct pipe_context* pipe,
1652 unsigned count,
1653 const struct pipe_vertex_element* attribs)
1654 {
1655 struct r300_context *r300 = r300_context(pipe);
1656 struct r300_vertex_element_state *velems;
1657 unsigned i;
1658 struct pipe_vertex_element dummy_attrib = {0};
1659
1660 /* R300 Programmable Stream Control (PSC) doesn't support 0 vertex elements. */
1661 if (!count) {
1662 dummy_attrib.src_format = PIPE_FORMAT_R8G8B8A8_UNORM;
1663 attribs = &dummy_attrib;
1664 count = 1;
1665 } else if (count > 16) {
1666 fprintf(stderr, "r300: More than 16 vertex elements are not supported,"
1667 " requested %i, using 16.\n", count);
1668 count = 16;
1669 }
1670
1671 velems = CALLOC_STRUCT(r300_vertex_element_state);
1672 if (!velems)
1673 return NULL;
1674
1675 velems->count = count;
1676 velems->vmgr_elements =
1677 u_vbuf_mgr_create_vertex_elements(r300->vbuf_mgr, count, attribs,
1678 velems->velem);
1679
1680 if (r300_screen(pipe->screen)->caps.has_tcl) {
1681 /* Setup PSC.
1682 * The unused components will be replaced by (..., 0, 1). */
1683 r300_vertex_psc(velems);
1684
1685 for (i = 0; i < count; i++) {
1686 velems->format_size[i] =
1687 align(util_format_get_blocksize(velems->velem[i].src_format), 4);
1688 velems->vertex_size_dwords += velems->format_size[i] / 4;
1689 }
1690 }
1691
1692 return velems;
1693 }
1694
1695 static void r300_bind_vertex_elements_state(struct pipe_context *pipe,
1696 void *state)
1697 {
1698 struct r300_context *r300 = r300_context(pipe);
1699 struct r300_vertex_element_state *velems = state;
1700
1701 if (velems == NULL) {
1702 return;
1703 }
1704
1705 r300->velems = velems;
1706
1707 u_vbuf_mgr_bind_vertex_elements(r300->vbuf_mgr, state, velems->vmgr_elements);
1708
1709 if (r300->draw) {
1710 draw_set_vertex_elements(r300->draw, velems->count, velems->velem);
1711 return;
1712 }
1713
1714 UPDATE_STATE(&velems->vertex_stream, r300->vertex_stream_state);
1715 r300->vertex_stream_state.size = (1 + velems->vertex_stream.count) * 2;
1716 r300->vertex_arrays_dirty = TRUE;
1717 }
1718
1719 static void r300_delete_vertex_elements_state(struct pipe_context *pipe, void *state)
1720 {
1721 struct r300_context *r300 = r300_context(pipe);
1722 struct r300_vertex_element_state *velems = state;
1723
1724 u_vbuf_mgr_destroy_vertex_elements(r300->vbuf_mgr, velems->vmgr_elements);
1725 FREE(state);
1726 }
1727
1728 static void* r300_create_vs_state(struct pipe_context* pipe,
1729 const struct pipe_shader_state* shader)
1730 {
1731 struct r300_context* r300 = r300_context(pipe);
1732 struct r300_vertex_shader* vs = CALLOC_STRUCT(r300_vertex_shader);
1733
1734 /* Copy state directly into shader. */
1735 vs->state = *shader;
1736 vs->state.tokens = tgsi_dup_tokens(shader->tokens);
1737
1738 if (r300->screen->caps.has_tcl) {
1739 r300_init_vs_outputs(vs);
1740 r300_translate_vertex_shader(r300, vs);
1741 } else {
1742 r300_draw_init_vertex_shader(r300->draw, vs);
1743 }
1744
1745 return vs;
1746 }
1747
1748 static void r300_bind_vs_state(struct pipe_context* pipe, void* shader)
1749 {
1750 struct r300_context* r300 = r300_context(pipe);
1751 struct r300_vertex_shader* vs = (struct r300_vertex_shader*)shader;
1752
1753 if (vs == NULL) {
1754 r300->vs_state.state = NULL;
1755 return;
1756 }
1757 if (vs == r300->vs_state.state) {
1758 return;
1759 }
1760 r300->vs_state.state = vs;
1761
1762 /* The majority of the RS block bits is dependent on the vertex shader. */
1763 r300_mark_atom_dirty(r300, &r300->rs_block_state); /* Will be updated before the emission. */
1764
1765 if (r300->screen->caps.has_tcl) {
1766 unsigned fc_op_dwords = r300->screen->caps.is_r500 ? 3 : 2;
1767 r300_mark_atom_dirty(r300, &r300->vs_state);
1768 r300->vs_state.size =
1769 vs->code.length + 9 +
1770 (vs->code.num_fc_ops ? vs->code.num_fc_ops * fc_op_dwords + 4 : 0);
1771
1772 r300_mark_atom_dirty(r300, &r300->vs_constants);
1773 r300->vs_constants.size =
1774 2 +
1775 (vs->externals_count ? vs->externals_count * 4 + 3 : 0) +
1776 (vs->immediates_count ? vs->immediates_count * 4 + 3 : 0);
1777
1778 ((struct r300_constant_buffer*)r300->vs_constants.state)->remap_table =
1779 vs->code.constants_remap_table;
1780
1781 r300_mark_atom_dirty(r300, &r300->pvs_flush);
1782 } else {
1783 draw_bind_vertex_shader(r300->draw,
1784 (struct draw_vertex_shader*)vs->draw_vs);
1785 }
1786 }
1787
1788 static void r300_delete_vs_state(struct pipe_context* pipe, void* shader)
1789 {
1790 struct r300_context* r300 = r300_context(pipe);
1791 struct r300_vertex_shader* vs = (struct r300_vertex_shader*)shader;
1792
1793 if (r300->screen->caps.has_tcl) {
1794 rc_constants_destroy(&vs->code.constants);
1795 if (vs->code.constants_remap_table)
1796 FREE(vs->code.constants_remap_table);
1797 } else {
1798 draw_delete_vertex_shader(r300->draw,
1799 (struct draw_vertex_shader*)vs->draw_vs);
1800 }
1801
1802 FREE((void*)vs->state.tokens);
1803 FREE(shader);
1804 }
1805
1806 static void r300_set_constant_buffer(struct pipe_context *pipe,
1807 uint shader, uint index,
1808 struct pipe_resource *buf)
1809 {
1810 struct r300_context* r300 = r300_context(pipe);
1811 struct r300_constant_buffer *cbuf;
1812 struct r300_resource *rbuf = r300_resource(buf);
1813 uint32_t *mapped;
1814
1815 switch (shader) {
1816 case PIPE_SHADER_VERTEX:
1817 cbuf = (struct r300_constant_buffer*)r300->vs_constants.state;
1818 break;
1819 case PIPE_SHADER_FRAGMENT:
1820 cbuf = (struct r300_constant_buffer*)r300->fs_constants.state;
1821 break;
1822 default:
1823 return;
1824 }
1825
1826 if (buf == NULL || buf->width0 == 0)
1827 return;
1828
1829 if (rbuf->b.user_ptr)
1830 mapped = (uint32_t*)rbuf->b.user_ptr;
1831 else if (rbuf->constant_buffer)
1832 mapped = (uint32_t*)rbuf->constant_buffer;
1833 else
1834 return;
1835
1836 if (shader == PIPE_SHADER_FRAGMENT ||
1837 (shader == PIPE_SHADER_VERTEX && r300->screen->caps.has_tcl)) {
1838 cbuf->ptr = mapped;
1839 }
1840
1841 if (shader == PIPE_SHADER_VERTEX) {
1842 if (r300->screen->caps.has_tcl) {
1843 struct r300_vertex_shader *vs =
1844 (struct r300_vertex_shader*)r300->vs_state.state;
1845
1846 if (!vs) {
1847 cbuf->buffer_base = 0;
1848 return;
1849 }
1850
1851 cbuf->buffer_base = r300->vs_const_base;
1852 r300->vs_const_base += vs->code.constants.Count;
1853 if (r300->vs_const_base > R500_MAX_PVS_CONST_VECS) {
1854 r300->vs_const_base = vs->code.constants.Count;
1855 cbuf->buffer_base = 0;
1856 r300_mark_atom_dirty(r300, &r300->pvs_flush);
1857 }
1858 r300_mark_atom_dirty(r300, &r300->vs_constants);
1859 } else if (r300->draw) {
1860 draw_set_mapped_constant_buffer(r300->draw, PIPE_SHADER_VERTEX,
1861 0, mapped, buf->width0);
1862 }
1863 } else if (shader == PIPE_SHADER_FRAGMENT) {
1864 r300_mark_atom_dirty(r300, &r300->fs_constants);
1865 }
1866 }
1867
1868 static void r300_texture_barrier(struct pipe_context *pipe)
1869 {
1870 struct r300_context *r300 = r300_context(pipe);
1871
1872 r300_mark_atom_dirty(r300, &r300->gpu_flush);
1873 r300_mark_atom_dirty(r300, &r300->texture_cache_inval);
1874 }
1875
1876 void r300_init_state_functions(struct r300_context* r300)
1877 {
1878 r300->context.create_blend_state = r300_create_blend_state;
1879 r300->context.bind_blend_state = r300_bind_blend_state;
1880 r300->context.delete_blend_state = r300_delete_blend_state;
1881
1882 r300->context.set_blend_color = r300_set_blend_color;
1883
1884 r300->context.set_clip_state = r300_set_clip_state;
1885 r300->context.set_sample_mask = r300_set_sample_mask;
1886
1887 r300->context.set_constant_buffer = r300_set_constant_buffer;
1888
1889 r300->context.create_depth_stencil_alpha_state = r300_create_dsa_state;
1890 r300->context.bind_depth_stencil_alpha_state = r300_bind_dsa_state;
1891 r300->context.delete_depth_stencil_alpha_state = r300_delete_dsa_state;
1892
1893 r300->context.set_stencil_ref = r300_set_stencil_ref;
1894
1895 r300->context.set_framebuffer_state = r300_set_framebuffer_state;
1896
1897 r300->context.create_fs_state = r300_create_fs_state;
1898 r300->context.bind_fs_state = r300_bind_fs_state;
1899 r300->context.delete_fs_state = r300_delete_fs_state;
1900
1901 r300->context.set_polygon_stipple = r300_set_polygon_stipple;
1902
1903 r300->context.create_rasterizer_state = r300_create_rs_state;
1904 r300->context.bind_rasterizer_state = r300_bind_rs_state;
1905 r300->context.delete_rasterizer_state = r300_delete_rs_state;
1906
1907 r300->context.create_sampler_state = r300_create_sampler_state;
1908 r300->context.bind_fragment_sampler_states = r300_bind_sampler_states;
1909 r300->context.bind_vertex_sampler_states = r300_lacks_vertex_textures;
1910 r300->context.delete_sampler_state = r300_delete_sampler_state;
1911
1912 r300->context.set_fragment_sampler_views = r300_set_fragment_sampler_views;
1913 r300->context.create_sampler_view = r300_create_sampler_view;
1914 r300->context.sampler_view_destroy = r300_sampler_view_destroy;
1915
1916 r300->context.set_scissor_state = r300_set_scissor_state;
1917
1918 r300->context.set_viewport_state = r300_set_viewport_state;
1919
1920 r300->context.set_vertex_buffers = r300_set_vertex_buffers;
1921 r300->context.set_index_buffer = r300_set_index_buffer;
1922 r300->context.redefine_user_buffer = u_default_redefine_user_buffer;
1923
1924 r300->context.create_vertex_elements_state = r300_create_vertex_elements_state;
1925 r300->context.bind_vertex_elements_state = r300_bind_vertex_elements_state;
1926 r300->context.delete_vertex_elements_state = r300_delete_vertex_elements_state;
1927
1928 r300->context.create_vs_state = r300_create_vs_state;
1929 r300->context.bind_vs_state = r300_bind_vs_state;
1930 r300->context.delete_vs_state = r300_delete_vs_state;
1931
1932 r300->context.texture_barrier = r300_texture_barrier;
1933 }