r300g: fix a race between CS and SET_TILING ioctls
[mesa.git] / src / gallium / drivers / r300 / r300_state.c
1 /*
2 * Copyright 2008 Corbin Simpson <MostAwesomeDude@gmail.com>
3 * Copyright 2009 Marek Olšák <maraeo@gmail.com>
4 *
5 * Permission is hereby granted, free of charge, to any person obtaining a
6 * copy of this software and associated documentation files (the "Software"),
7 * to deal in the Software without restriction, including without limitation
8 * on the rights to use, copy, modify, merge, publish, distribute, sub
9 * license, and/or sell copies of the Software, and to permit persons to whom
10 * the Software is furnished to do so, subject to the following conditions:
11 *
12 * The above copyright notice and this permission notice (including the next
13 * paragraph) shall be included in all copies or substantial portions of the
14 * Software.
15 *
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
19 * THE AUTHOR(S) AND/OR THEIR SUPPLIERS BE LIABLE FOR ANY CLAIM,
20 * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
21 * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
22 * USE OR OTHER DEALINGS IN THE SOFTWARE. */
23
24 #include "draw/draw_context.h"
25
26 #include "util/u_framebuffer.h"
27 #include "util/u_math.h"
28 #include "util/u_mm.h"
29 #include "util/u_memory.h"
30 #include "util/u_pack_color.h"
31 #include "util/u_transfer.h"
32
33 #include "tgsi/tgsi_parse.h"
34
35 #include "pipe/p_config.h"
36
37 #include "r300_cb.h"
38 #include "r300_context.h"
39 #include "r300_emit.h"
40 #include "r300_reg.h"
41 #include "r300_screen.h"
42 #include "r300_screen_buffer.h"
43 #include "r300_state_inlines.h"
44 #include "r300_fs.h"
45 #include "r300_texture.h"
46 #include "r300_vs.h"
47 #include "r300_winsys.h"
48 #include "r300_hyperz.h"
49
50 /* r300_state: Functions used to intialize state context by translating
51 * Gallium state objects into semi-native r300 state objects. */
52
53 #define UPDATE_STATE(cso, atom) \
54 if (cso != atom.state) { \
55 atom.state = cso; \
56 r300_mark_atom_dirty(r300, &(atom)); \
57 }
58
59 static boolean blend_discard_if_src_alpha_0(unsigned srcRGB, unsigned srcA,
60 unsigned dstRGB, unsigned dstA)
61 {
62 /* If the blend equation is ADD or REVERSE_SUBTRACT,
63 * SRC_ALPHA == 0, and the following state is set, the colorbuffer
64 * will not be changed.
65 * Notice that the dst factors are the src factors inverted. */
66 return (srcRGB == PIPE_BLENDFACTOR_SRC_ALPHA ||
67 srcRGB == PIPE_BLENDFACTOR_SRC_ALPHA_SATURATE ||
68 srcRGB == PIPE_BLENDFACTOR_ZERO) &&
69 (srcA == PIPE_BLENDFACTOR_SRC_COLOR ||
70 srcA == PIPE_BLENDFACTOR_SRC_ALPHA ||
71 srcA == PIPE_BLENDFACTOR_SRC_ALPHA_SATURATE ||
72 srcA == PIPE_BLENDFACTOR_ZERO) &&
73 (dstRGB == PIPE_BLENDFACTOR_INV_SRC_ALPHA ||
74 dstRGB == PIPE_BLENDFACTOR_ONE) &&
75 (dstA == PIPE_BLENDFACTOR_INV_SRC_COLOR ||
76 dstA == PIPE_BLENDFACTOR_INV_SRC_ALPHA ||
77 dstA == PIPE_BLENDFACTOR_ONE);
78 }
79
80 static boolean blend_discard_if_src_alpha_1(unsigned srcRGB, unsigned srcA,
81 unsigned dstRGB, unsigned dstA)
82 {
83 /* If the blend equation is ADD or REVERSE_SUBTRACT,
84 * SRC_ALPHA == 1, and the following state is set, the colorbuffer
85 * will not be changed.
86 * Notice that the dst factors are the src factors inverted. */
87 return (srcRGB == PIPE_BLENDFACTOR_INV_SRC_ALPHA ||
88 srcRGB == PIPE_BLENDFACTOR_ZERO) &&
89 (srcA == PIPE_BLENDFACTOR_INV_SRC_COLOR ||
90 srcA == PIPE_BLENDFACTOR_INV_SRC_ALPHA ||
91 srcA == PIPE_BLENDFACTOR_ZERO) &&
92 (dstRGB == PIPE_BLENDFACTOR_SRC_ALPHA ||
93 dstRGB == PIPE_BLENDFACTOR_ONE) &&
94 (dstA == PIPE_BLENDFACTOR_SRC_COLOR ||
95 dstA == PIPE_BLENDFACTOR_SRC_ALPHA ||
96 dstA == PIPE_BLENDFACTOR_ONE);
97 }
98
99 static boolean blend_discard_if_src_color_0(unsigned srcRGB, unsigned srcA,
100 unsigned dstRGB, unsigned dstA)
101 {
102 /* If the blend equation is ADD or REVERSE_SUBTRACT,
103 * SRC_COLOR == (0,0,0), and the following state is set, the colorbuffer
104 * will not be changed.
105 * Notice that the dst factors are the src factors inverted. */
106 return (srcRGB == PIPE_BLENDFACTOR_SRC_COLOR ||
107 srcRGB == PIPE_BLENDFACTOR_ZERO) &&
108 (srcA == PIPE_BLENDFACTOR_ZERO) &&
109 (dstRGB == PIPE_BLENDFACTOR_INV_SRC_COLOR ||
110 dstRGB == PIPE_BLENDFACTOR_ONE) &&
111 (dstA == PIPE_BLENDFACTOR_ONE);
112 }
113
114 static boolean blend_discard_if_src_color_1(unsigned srcRGB, unsigned srcA,
115 unsigned dstRGB, unsigned dstA)
116 {
117 /* If the blend equation is ADD or REVERSE_SUBTRACT,
118 * SRC_COLOR == (1,1,1), and the following state is set, the colorbuffer
119 * will not be changed.
120 * Notice that the dst factors are the src factors inverted. */
121 return (srcRGB == PIPE_BLENDFACTOR_INV_SRC_COLOR ||
122 srcRGB == PIPE_BLENDFACTOR_ZERO) &&
123 (srcA == PIPE_BLENDFACTOR_ZERO) &&
124 (dstRGB == PIPE_BLENDFACTOR_SRC_COLOR ||
125 dstRGB == PIPE_BLENDFACTOR_ONE) &&
126 (dstA == PIPE_BLENDFACTOR_ONE);
127 }
128
129 static boolean blend_discard_if_src_alpha_color_0(unsigned srcRGB, unsigned srcA,
130 unsigned dstRGB, unsigned dstA)
131 {
132 /* If the blend equation is ADD or REVERSE_SUBTRACT,
133 * SRC_ALPHA_COLOR == (0,0,0,0), and the following state is set,
134 * the colorbuffer will not be changed.
135 * Notice that the dst factors are the src factors inverted. */
136 return (srcRGB == PIPE_BLENDFACTOR_SRC_COLOR ||
137 srcRGB == PIPE_BLENDFACTOR_SRC_ALPHA ||
138 srcRGB == PIPE_BLENDFACTOR_SRC_ALPHA_SATURATE ||
139 srcRGB == PIPE_BLENDFACTOR_ZERO) &&
140 (srcA == PIPE_BLENDFACTOR_SRC_COLOR ||
141 srcA == PIPE_BLENDFACTOR_SRC_ALPHA ||
142 srcA == PIPE_BLENDFACTOR_SRC_ALPHA_SATURATE ||
143 srcA == PIPE_BLENDFACTOR_ZERO) &&
144 (dstRGB == PIPE_BLENDFACTOR_INV_SRC_COLOR ||
145 dstRGB == PIPE_BLENDFACTOR_INV_SRC_ALPHA ||
146 dstRGB == PIPE_BLENDFACTOR_ONE) &&
147 (dstA == PIPE_BLENDFACTOR_INV_SRC_COLOR ||
148 dstA == PIPE_BLENDFACTOR_INV_SRC_ALPHA ||
149 dstA == PIPE_BLENDFACTOR_ONE);
150 }
151
152 static boolean blend_discard_if_src_alpha_color_1(unsigned srcRGB, unsigned srcA,
153 unsigned dstRGB, unsigned dstA)
154 {
155 /* If the blend equation is ADD or REVERSE_SUBTRACT,
156 * SRC_ALPHA_COLOR == (1,1,1,1), and the following state is set,
157 * the colorbuffer will not be changed.
158 * Notice that the dst factors are the src factors inverted. */
159 return (srcRGB == PIPE_BLENDFACTOR_INV_SRC_COLOR ||
160 srcRGB == PIPE_BLENDFACTOR_INV_SRC_ALPHA ||
161 srcRGB == PIPE_BLENDFACTOR_ZERO) &&
162 (srcA == PIPE_BLENDFACTOR_INV_SRC_COLOR ||
163 srcA == PIPE_BLENDFACTOR_INV_SRC_ALPHA ||
164 srcA == PIPE_BLENDFACTOR_ZERO) &&
165 (dstRGB == PIPE_BLENDFACTOR_SRC_COLOR ||
166 dstRGB == PIPE_BLENDFACTOR_SRC_ALPHA ||
167 dstRGB == PIPE_BLENDFACTOR_ONE) &&
168 (dstA == PIPE_BLENDFACTOR_SRC_COLOR ||
169 dstA == PIPE_BLENDFACTOR_SRC_ALPHA ||
170 dstA == PIPE_BLENDFACTOR_ONE);
171 }
172
173 static unsigned bgra_cmask(unsigned mask)
174 {
175 /* Gallium uses RGBA color ordering while R300 expects BGRA. */
176
177 return ((mask & PIPE_MASK_R) << 2) |
178 ((mask & PIPE_MASK_B) >> 2) |
179 (mask & (PIPE_MASK_G | PIPE_MASK_A));
180 }
181
182 /* Create a new blend state based on the CSO blend state.
183 *
184 * This encompasses alpha blending, logic/raster ops, and blend dithering. */
185 static void* r300_create_blend_state(struct pipe_context* pipe,
186 const struct pipe_blend_state* state)
187 {
188 struct r300_screen* r300screen = r300_screen(pipe->screen);
189 struct r300_blend_state* blend = CALLOC_STRUCT(r300_blend_state);
190 uint32_t blend_control = 0; /* R300_RB3D_CBLEND: 0x4e04 */
191 uint32_t alpha_blend_control = 0; /* R300_RB3D_ABLEND: 0x4e08 */
192 uint32_t color_channel_mask = 0; /* R300_RB3D_COLOR_CHANNEL_MASK: 0x4e0c */
193 uint32_t rop = 0; /* R300_RB3D_ROPCNTL: 0x4e18 */
194 uint32_t dither = 0; /* R300_RB3D_DITHER_CTL: 0x4e50 */
195 CB_LOCALS;
196
197 if (state->rt[0].blend_enable)
198 {
199 unsigned eqRGB = state->rt[0].rgb_func;
200 unsigned srcRGB = state->rt[0].rgb_src_factor;
201 unsigned dstRGB = state->rt[0].rgb_dst_factor;
202
203 unsigned eqA = state->rt[0].alpha_func;
204 unsigned srcA = state->rt[0].alpha_src_factor;
205 unsigned dstA = state->rt[0].alpha_dst_factor;
206
207 /* despite the name, ALPHA_BLEND_ENABLE has nothing to do with alpha,
208 * this is just the crappy D3D naming */
209 blend_control = R300_ALPHA_BLEND_ENABLE |
210 r300_translate_blend_function(eqRGB) |
211 ( r300_translate_blend_factor(srcRGB) << R300_SRC_BLEND_SHIFT) |
212 ( r300_translate_blend_factor(dstRGB) << R300_DST_BLEND_SHIFT);
213
214 /* Optimization: some operations do not require the destination color.
215 *
216 * When SRC_ALPHA_SATURATE is used, colorbuffer reads must be enabled,
217 * otherwise blending gives incorrect results. It seems to be
218 * a hardware bug. */
219 if (eqRGB == PIPE_BLEND_MIN || eqA == PIPE_BLEND_MIN ||
220 eqRGB == PIPE_BLEND_MAX || eqA == PIPE_BLEND_MAX ||
221 dstRGB != PIPE_BLENDFACTOR_ZERO ||
222 dstA != PIPE_BLENDFACTOR_ZERO ||
223 srcRGB == PIPE_BLENDFACTOR_DST_COLOR ||
224 srcRGB == PIPE_BLENDFACTOR_DST_ALPHA ||
225 srcRGB == PIPE_BLENDFACTOR_INV_DST_COLOR ||
226 srcRGB == PIPE_BLENDFACTOR_INV_DST_ALPHA ||
227 srcA == PIPE_BLENDFACTOR_DST_COLOR ||
228 srcA == PIPE_BLENDFACTOR_DST_ALPHA ||
229 srcA == PIPE_BLENDFACTOR_INV_DST_COLOR ||
230 srcA == PIPE_BLENDFACTOR_INV_DST_ALPHA ||
231 srcRGB == PIPE_BLENDFACTOR_SRC_ALPHA_SATURATE) {
232 /* Enable reading from the colorbuffer. */
233 blend_control |= R300_READ_ENABLE;
234
235 if (r300screen->caps.is_r500) {
236 /* Optimization: Depending on incoming pixels, we can
237 * conditionally disable the reading in hardware... */
238 if (eqRGB != PIPE_BLEND_MIN && eqA != PIPE_BLEND_MIN &&
239 eqRGB != PIPE_BLEND_MAX && eqA != PIPE_BLEND_MAX) {
240 /* Disable reading if SRC_ALPHA == 0. */
241 if ((dstRGB == PIPE_BLENDFACTOR_SRC_ALPHA ||
242 dstRGB == PIPE_BLENDFACTOR_ZERO) &&
243 (dstA == PIPE_BLENDFACTOR_SRC_COLOR ||
244 dstA == PIPE_BLENDFACTOR_SRC_ALPHA ||
245 dstA == PIPE_BLENDFACTOR_ZERO)) {
246 blend_control |= R500_SRC_ALPHA_0_NO_READ;
247 }
248
249 /* Disable reading if SRC_ALPHA == 1. */
250 if ((dstRGB == PIPE_BLENDFACTOR_INV_SRC_ALPHA ||
251 dstRGB == PIPE_BLENDFACTOR_ZERO) &&
252 (dstA == PIPE_BLENDFACTOR_INV_SRC_COLOR ||
253 dstA == PIPE_BLENDFACTOR_INV_SRC_ALPHA ||
254 dstA == PIPE_BLENDFACTOR_ZERO)) {
255 blend_control |= R500_SRC_ALPHA_1_NO_READ;
256 }
257 }
258 }
259 }
260
261 /* Optimization: discard pixels which don't change the colorbuffer.
262 *
263 * The code below is non-trivial and some math is involved.
264 *
265 * Discarding pixels must be disabled when FP16 AA is enabled.
266 * This is a hardware bug. Also, this implementation wouldn't work
267 * with FP blending enabled and equation clamping disabled.
268 *
269 * Equations other than ADD are rarely used and therefore won't be
270 * optimized. */
271 if ((eqRGB == PIPE_BLEND_ADD || eqRGB == PIPE_BLEND_REVERSE_SUBTRACT) &&
272 (eqA == PIPE_BLEND_ADD || eqA == PIPE_BLEND_REVERSE_SUBTRACT)) {
273 /* ADD: X+Y
274 * REVERSE_SUBTRACT: Y-X
275 *
276 * The idea is:
277 * If X = src*srcFactor = 0 and Y = dst*dstFactor = 1,
278 * then CB will not be changed.
279 *
280 * Given the srcFactor and dstFactor variables, we can derive
281 * what src and dst should be equal to and discard appropriate
282 * pixels.
283 */
284 if (blend_discard_if_src_alpha_0(srcRGB, srcA, dstRGB, dstA)) {
285 blend_control |= R300_DISCARD_SRC_PIXELS_SRC_ALPHA_0;
286 } else if (blend_discard_if_src_alpha_1(srcRGB, srcA,
287 dstRGB, dstA)) {
288 blend_control |= R300_DISCARD_SRC_PIXELS_SRC_ALPHA_1;
289 } else if (blend_discard_if_src_color_0(srcRGB, srcA,
290 dstRGB, dstA)) {
291 blend_control |= R300_DISCARD_SRC_PIXELS_SRC_COLOR_0;
292 } else if (blend_discard_if_src_color_1(srcRGB, srcA,
293 dstRGB, dstA)) {
294 blend_control |= R300_DISCARD_SRC_PIXELS_SRC_COLOR_1;
295 } else if (blend_discard_if_src_alpha_color_0(srcRGB, srcA,
296 dstRGB, dstA)) {
297 blend_control |=
298 R300_DISCARD_SRC_PIXELS_SRC_ALPHA_COLOR_0;
299 } else if (blend_discard_if_src_alpha_color_1(srcRGB, srcA,
300 dstRGB, dstA)) {
301 blend_control |=
302 R300_DISCARD_SRC_PIXELS_SRC_ALPHA_COLOR_1;
303 }
304 }
305
306 /* separate alpha */
307 if (srcA != srcRGB || dstA != dstRGB || eqA != eqRGB) {
308 blend_control |= R300_SEPARATE_ALPHA_ENABLE;
309 alpha_blend_control =
310 r300_translate_blend_function(eqA) |
311 (r300_translate_blend_factor(srcA) << R300_SRC_BLEND_SHIFT) |
312 (r300_translate_blend_factor(dstA) << R300_DST_BLEND_SHIFT);
313 }
314 }
315
316 /* PIPE_LOGICOP_* don't need to be translated, fortunately. */
317 if (state->logicop_enable) {
318 rop = R300_RB3D_ROPCNTL_ROP_ENABLE |
319 (state->logicop_func) << R300_RB3D_ROPCNTL_ROP_SHIFT;
320 }
321
322 /* Color channel masks for all MRTs. */
323 color_channel_mask = bgra_cmask(state->rt[0].colormask);
324 if (r300screen->caps.is_r500 && state->independent_blend_enable) {
325 if (state->rt[1].blend_enable) {
326 color_channel_mask |= bgra_cmask(state->rt[1].colormask) << 4;
327 }
328 if (state->rt[2].blend_enable) {
329 color_channel_mask |= bgra_cmask(state->rt[2].colormask) << 8;
330 }
331 if (state->rt[3].blend_enable) {
332 color_channel_mask |= bgra_cmask(state->rt[3].colormask) << 12;
333 }
334 }
335
336 /* Neither fglrx nor classic r300 ever set this, regardless of dithering
337 * state. Since it's an optional implementation detail, we can leave it
338 * out and never dither.
339 *
340 * This could be revisited if we ever get quality or conformance hints.
341 *
342 if (state->dither) {
343 dither = R300_RB3D_DITHER_CTL_DITHER_MODE_LUT |
344 R300_RB3D_DITHER_CTL_ALPHA_DITHER_MODE_LUT;
345 }
346 */
347
348 /* Build a command buffer. */
349 BEGIN_CB(blend->cb, 8);
350 OUT_CB_REG(R300_RB3D_ROPCNTL, rop);
351 OUT_CB_REG_SEQ(R300_RB3D_CBLEND, 3);
352 OUT_CB(blend_control);
353 OUT_CB(alpha_blend_control);
354 OUT_CB(color_channel_mask);
355 OUT_CB_REG(R300_RB3D_DITHER_CTL, dither);
356 END_CB;
357
358 /* The same as above, but with no colorbuffer reads and writes. */
359 BEGIN_CB(blend->cb_no_readwrite, 8);
360 OUT_CB_REG(R300_RB3D_ROPCNTL, rop);
361 OUT_CB_REG_SEQ(R300_RB3D_CBLEND, 3);
362 OUT_CB(0);
363 OUT_CB(0);
364 OUT_CB(0);
365 OUT_CB_REG(R300_RB3D_DITHER_CTL, dither);
366 END_CB;
367
368 return (void*)blend;
369 }
370
371 /* Bind blend state. */
372 static void r300_bind_blend_state(struct pipe_context* pipe,
373 void* state)
374 {
375 struct r300_context* r300 = r300_context(pipe);
376
377 UPDATE_STATE(state, r300->blend_state);
378 }
379
380 /* Free blend state. */
381 static void r300_delete_blend_state(struct pipe_context* pipe,
382 void* state)
383 {
384 FREE(state);
385 }
386
387 /* Convert float to 10bit integer */
388 static unsigned float_to_fixed10(float f)
389 {
390 return CLAMP((unsigned)(f * 1023.9f), 0, 1023);
391 }
392
393 /* Set blend color.
394 * Setup both R300 and R500 registers, figure out later which one to write. */
395 static void r300_set_blend_color(struct pipe_context* pipe,
396 const struct pipe_blend_color* color)
397 {
398 struct r300_context* r300 = r300_context(pipe);
399 struct r300_blend_color_state* state =
400 (struct r300_blend_color_state*)r300->blend_color_state.state;
401 CB_LOCALS;
402
403 if (r300->screen->caps.is_r500) {
404 /* XXX if FP16 blending is enabled, we should use the FP16 format */
405 BEGIN_CB(state->cb, 3);
406 OUT_CB_REG_SEQ(R500_RB3D_CONSTANT_COLOR_AR, 2);
407 OUT_CB(float_to_fixed10(color->color[0]) |
408 (float_to_fixed10(color->color[3]) << 16));
409 OUT_CB(float_to_fixed10(color->color[2]) |
410 (float_to_fixed10(color->color[1]) << 16));
411 END_CB;
412 } else {
413 union util_color uc;
414 util_pack_color(color->color, PIPE_FORMAT_B8G8R8A8_UNORM, &uc);
415
416 BEGIN_CB(state->cb, 2);
417 OUT_CB_REG(R300_RB3D_BLEND_COLOR, uc.ui);
418 END_CB;
419 }
420
421 r300_mark_atom_dirty(r300, &r300->blend_color_state);
422 }
423
424 static void r300_set_clip_state(struct pipe_context* pipe,
425 const struct pipe_clip_state* state)
426 {
427 struct r300_context* r300 = r300_context(pipe);
428 struct r300_clip_state *clip =
429 (struct r300_clip_state*)r300->clip_state.state;
430 CB_LOCALS;
431
432 clip->clip = *state;
433
434 if (r300->screen->caps.has_tcl) {
435 r300->clip_state.size = 2 + !!state->nr * 3 + state->nr * 4;
436
437 BEGIN_CB(clip->cb, r300->clip_state.size);
438 if (state->nr) {
439 OUT_CB_REG(R300_VAP_PVS_VECTOR_INDX_REG,
440 (r300->screen->caps.is_r500 ?
441 R500_PVS_UCP_START : R300_PVS_UCP_START));
442 OUT_CB_ONE_REG(R300_VAP_PVS_UPLOAD_DATA, state->nr * 4);
443 OUT_CB_TABLE(state->ucp, state->nr * 4);
444 }
445 OUT_CB_REG(R300_VAP_CLIP_CNTL, ((1 << state->nr) - 1) |
446 R300_PS_UCP_MODE_CLIP_AS_TRIFAN);
447 END_CB;
448
449 r300_mark_atom_dirty(r300, &r300->clip_state);
450 } else {
451 draw_set_clip_state(r300->draw, state);
452 }
453 }
454
455 static void
456 r300_set_sample_mask(struct pipe_context *pipe,
457 unsigned sample_mask)
458 {
459 }
460
461
462 /* Create a new depth, stencil, and alpha state based on the CSO dsa state.
463 *
464 * This contains the depth buffer, stencil buffer, alpha test, and such.
465 * On the Radeon, depth and stencil buffer setup are intertwined, which is
466 * the reason for some of the strange-looking assignments across registers. */
467 static void*
468 r300_create_dsa_state(struct pipe_context* pipe,
469 const struct pipe_depth_stencil_alpha_state* state)
470 {
471 struct r300_capabilities *caps = &r300_screen(pipe->screen)->caps;
472 struct r300_dsa_state* dsa = CALLOC_STRUCT(r300_dsa_state);
473 CB_LOCALS;
474
475 dsa->dsa = *state;
476
477 /* Depth test setup. - separate write mask depth for decomp flush */
478 if (state->depth.writemask) {
479 dsa->z_buffer_control |= R300_Z_WRITE_ENABLE;
480 }
481
482 if (state->depth.enabled) {
483 dsa->z_buffer_control |= R300_Z_ENABLE;
484
485 dsa->z_stencil_control |=
486 (r300_translate_depth_stencil_function(state->depth.func) <<
487 R300_Z_FUNC_SHIFT);
488 }
489
490 /* Stencil buffer setup. */
491 if (state->stencil[0].enabled) {
492 dsa->z_buffer_control |= R300_STENCIL_ENABLE;
493 dsa->z_stencil_control |=
494 (r300_translate_depth_stencil_function(state->stencil[0].func) <<
495 R300_S_FRONT_FUNC_SHIFT) |
496 (r300_translate_stencil_op(state->stencil[0].fail_op) <<
497 R300_S_FRONT_SFAIL_OP_SHIFT) |
498 (r300_translate_stencil_op(state->stencil[0].zpass_op) <<
499 R300_S_FRONT_ZPASS_OP_SHIFT) |
500 (r300_translate_stencil_op(state->stencil[0].zfail_op) <<
501 R300_S_FRONT_ZFAIL_OP_SHIFT);
502
503 dsa->stencil_ref_mask =
504 (state->stencil[0].valuemask << R300_STENCILMASK_SHIFT) |
505 (state->stencil[0].writemask << R300_STENCILWRITEMASK_SHIFT);
506
507 if (state->stencil[1].enabled) {
508 dsa->two_sided = TRUE;
509
510 dsa->z_buffer_control |= R300_STENCIL_FRONT_BACK;
511 dsa->z_stencil_control |=
512 (r300_translate_depth_stencil_function(state->stencil[1].func) <<
513 R300_S_BACK_FUNC_SHIFT) |
514 (r300_translate_stencil_op(state->stencil[1].fail_op) <<
515 R300_S_BACK_SFAIL_OP_SHIFT) |
516 (r300_translate_stencil_op(state->stencil[1].zpass_op) <<
517 R300_S_BACK_ZPASS_OP_SHIFT) |
518 (r300_translate_stencil_op(state->stencil[1].zfail_op) <<
519 R300_S_BACK_ZFAIL_OP_SHIFT);
520
521 dsa->stencil_ref_bf =
522 (state->stencil[1].valuemask << R300_STENCILMASK_SHIFT) |
523 (state->stencil[1].writemask << R300_STENCILWRITEMASK_SHIFT);
524
525 if (caps->is_r500) {
526 dsa->z_buffer_control |= R500_STENCIL_REFMASK_FRONT_BACK;
527 } else {
528 dsa->two_sided_stencil_ref =
529 (state->stencil[0].valuemask != state->stencil[1].valuemask ||
530 state->stencil[0].writemask != state->stencil[1].writemask);
531 }
532 }
533 }
534
535 /* Alpha test setup. */
536 if (state->alpha.enabled) {
537 dsa->alpha_function =
538 r300_translate_alpha_function(state->alpha.func) |
539 R300_FG_ALPHA_FUNC_ENABLE;
540
541 /* We could use 10bit alpha ref but who needs that? */
542 dsa->alpha_function |= float_to_ubyte(state->alpha.ref_value);
543
544 if (caps->is_r500)
545 dsa->alpha_function |= R500_FG_ALPHA_FUNC_8BIT;
546 }
547
548 BEGIN_CB(&dsa->cb_begin, 8);
549 OUT_CB_REG(R300_FG_ALPHA_FUNC, dsa->alpha_function);
550 OUT_CB_REG_SEQ(R300_ZB_CNTL, 3);
551 OUT_CB(dsa->z_buffer_control);
552 OUT_CB(dsa->z_stencil_control);
553 OUT_CB(dsa->stencil_ref_mask);
554 OUT_CB_REG(R500_ZB_STENCILREFMASK_BF, dsa->stencil_ref_bf);
555 END_CB;
556
557 BEGIN_CB(dsa->cb_no_readwrite, 8);
558 OUT_CB_REG(R300_FG_ALPHA_FUNC, dsa->alpha_function);
559 OUT_CB_REG_SEQ(R300_ZB_CNTL, 3);
560 OUT_CB(0);
561 OUT_CB(0);
562 OUT_CB(0);
563 OUT_CB_REG(R500_ZB_STENCILREFMASK_BF, 0);
564 END_CB;
565
566 return (void*)dsa;
567 }
568
569 static void r300_dsa_inject_stencilref(struct r300_context *r300)
570 {
571 struct r300_dsa_state *dsa =
572 (struct r300_dsa_state*)r300->dsa_state.state;
573
574 if (!dsa)
575 return;
576
577 dsa->stencil_ref_mask =
578 (dsa->stencil_ref_mask & ~R300_STENCILREF_MASK) |
579 r300->stencil_ref.ref_value[0];
580 dsa->stencil_ref_bf =
581 (dsa->stencil_ref_bf & ~R300_STENCILREF_MASK) |
582 r300->stencil_ref.ref_value[1];
583 }
584
585 /* Bind DSA state. */
586 static void r300_bind_dsa_state(struct pipe_context* pipe,
587 void* state)
588 {
589 struct r300_context* r300 = r300_context(pipe);
590
591 if (!state) {
592 return;
593 }
594
595 UPDATE_STATE(state, r300->dsa_state);
596
597 r300_mark_atom_dirty(r300, &r300->hyperz_state); /* Will be updated before the emission. */
598 r300_dsa_inject_stencilref(r300);
599 }
600
601 /* Free DSA state. */
602 static void r300_delete_dsa_state(struct pipe_context* pipe,
603 void* state)
604 {
605 FREE(state);
606 }
607
608 static void r300_set_stencil_ref(struct pipe_context* pipe,
609 const struct pipe_stencil_ref* sr)
610 {
611 struct r300_context* r300 = r300_context(pipe);
612
613 r300->stencil_ref = *sr;
614
615 r300_dsa_inject_stencilref(r300);
616 r300_mark_atom_dirty(r300, &r300->dsa_state);
617 }
618
619 static void r300_tex_set_tiling_flags(struct r300_context *r300,
620 struct r300_resource *tex,
621 unsigned level)
622 {
623 /* Check if the macrotile flag needs to be changed.
624 * Skip changing the flags otherwise. */
625 if (tex->tex.macrotile[tex->surface_level] !=
626 tex->tex.macrotile[level]) {
627 r300->rws->buffer_set_tiling(tex->buf, r300->cs,
628 tex->tex.microtile, tex->tex.macrotile[level],
629 tex->tex.stride_in_bytes[0]);
630
631 tex->surface_level = level;
632 }
633 }
634
635 /* This switcheroo is needed just because of goddamned MACRO_SWITCH. */
636 static void r300_fb_set_tiling_flags(struct r300_context *r300,
637 const struct pipe_framebuffer_state *state)
638 {
639 unsigned i;
640
641 /* Set tiling flags for new surfaces. */
642 for (i = 0; i < state->nr_cbufs; i++) {
643 r300_tex_set_tiling_flags(r300,
644 r300_resource(state->cbufs[i]->texture),
645 state->cbufs[i]->u.tex.level);
646 }
647 if (state->zsbuf) {
648 r300_tex_set_tiling_flags(r300,
649 r300_resource(state->zsbuf->texture),
650 state->zsbuf->u.tex.level);
651 }
652 }
653
654 static void r300_print_fb_surf_info(struct pipe_surface *surf, unsigned index,
655 const char *binding)
656 {
657 struct pipe_resource *tex = surf->texture;
658 struct r300_resource *rtex = r300_resource(tex);
659
660 fprintf(stderr,
661 "r300: %s[%i] Dim: %ix%i, Firstlayer: %i, "
662 "Lastlayer: %i, Level: %i, Format: %s\n"
663
664 "r300: TEX: Macro: %s, Micro: %s, Pitch: %i, "
665 "Dim: %ix%ix%i, LastLevel: %i, Format: %s\n",
666
667 binding, index, surf->width, surf->height,
668 surf->u.tex.first_layer, surf->u.tex.last_layer, surf->u.tex.level,
669 util_format_short_name(surf->format),
670
671 rtex->tex.macrotile[0] ? "YES" : " NO",
672 rtex->tex.microtile ? "YES" : " NO",
673 rtex->tex.stride_in_pixels[0],
674 tex->width0, tex->height0, tex->depth0,
675 tex->last_level, util_format_short_name(tex->format));
676 }
677
678 void r300_mark_fb_state_dirty(struct r300_context *r300,
679 enum r300_fb_state_change change)
680 {
681 struct pipe_framebuffer_state *state = r300->fb_state.state;
682 boolean can_hyperz = r300->rws->get_value(r300->rws, R300_CAN_HYPERZ);
683
684 r300_mark_atom_dirty(r300, &r300->gpu_flush);
685 r300_mark_atom_dirty(r300, &r300->fb_state);
686
687 /* What is marked as dirty depends on the enum r300_fb_state_change. */
688 if (change == R300_CHANGED_FB_STATE) {
689 r300_mark_atom_dirty(r300, &r300->aa_state);
690 }
691
692 if (change == R300_CHANGED_FB_STATE ||
693 change == R300_CHANGED_HYPERZ_FLAG) {
694 r300_mark_atom_dirty(r300, &r300->hyperz_state);
695 }
696
697 if (change == R300_CHANGED_FB_STATE ||
698 change == R300_CHANGED_MULTIWRITE) {
699 r300_mark_atom_dirty(r300, &r300->fb_state_pipelined);
700 }
701
702 /* Now compute the fb_state atom size. */
703 r300->fb_state.size = 2 + (8 * state->nr_cbufs);
704
705 if (r300->cbzb_clear)
706 r300->fb_state.size += 10;
707 else if (state->zsbuf) {
708 r300->fb_state.size += 10;
709 if (can_hyperz)
710 r300->fb_state.size += r300->screen->caps.hiz_ram ? 8 : 4;
711 }
712
713 /* The size of the rest of atoms stays the same. */
714 }
715
716 static void
717 r300_set_framebuffer_state(struct pipe_context* pipe,
718 const struct pipe_framebuffer_state* state)
719 {
720 struct r300_context* r300 = r300_context(pipe);
721 struct r300_aa_state *aa = (struct r300_aa_state*)r300->aa_state.state;
722 struct pipe_framebuffer_state *old_state = r300->fb_state.state;
723 boolean can_hyperz = r300->rws->get_value(r300->rws, R300_CAN_HYPERZ);
724 unsigned max_width, max_height, i;
725 uint32_t zbuffer_bpp = 0;
726
727 if (r300->screen->caps.is_r500) {
728 max_width = max_height = 4096;
729 } else if (r300->screen->caps.is_r400) {
730 max_width = max_height = 4021;
731 } else {
732 max_width = max_height = 2560;
733 }
734
735 if (state->width > max_width || state->height > max_height) {
736 fprintf(stderr, "r300: Implementation error: Render targets are too "
737 "big in %s, refusing to bind framebuffer state!\n", __FUNCTION__);
738 return;
739 }
740
741 if (old_state->zsbuf && r300->zmask_in_use && !r300->zmask_locked) {
742 /* There is a zmask in use, what are we gonna do? */
743 if (state->zsbuf) {
744 if (!pipe_surface_equal(old_state->zsbuf, state->zsbuf)) {
745 /* Decompress the currently bound zbuffer before we bind another one. */
746 r300_decompress_zmask(r300);
747 }
748 } else {
749 /* We don't bind another zbuffer, so lock the current one. */
750 r300->zmask_locked = TRUE;
751 pipe_surface_reference(&r300->locked_zbuffer, old_state->zsbuf);
752 }
753 } else if (r300->zmask_locked && r300->locked_zbuffer) {
754 /* We have a locked zbuffer now, what are we gonna do? */
755 if (state->zsbuf) {
756 if (!pipe_surface_equal(r300->locked_zbuffer, state->zsbuf)) {
757 /* We are binding some other zbuffer, so decompress the locked one,
758 * it gets unlocked automatically. */
759 r300_decompress_zmask_locked_unsafe(r300);
760 } else {
761 /* We are binding the locked zbuffer again, so unlock it. */
762 r300->zmask_locked = FALSE;
763 }
764 }
765 }
766
767 /* If nr_cbufs is changed from zero to non-zero or vice versa... */
768 if (!!old_state->nr_cbufs != !!state->nr_cbufs) {
769 r300_mark_atom_dirty(r300, &r300->blend_state);
770 }
771 /* If zsbuf is set from NULL to non-NULL or vice versa.. */
772 if (!!old_state->zsbuf != !!state->zsbuf) {
773 r300_mark_atom_dirty(r300, &r300->dsa_state);
774 }
775
776 /* The tiling flags are dependent on the surface miplevel, unfortunately. */
777 r300_fb_set_tiling_flags(r300, state);
778
779 util_copy_framebuffer_state(r300->fb_state.state, state);
780
781 if (!r300->zmask_locked) {
782 pipe_surface_reference(&r300->locked_zbuffer, NULL);
783 }
784
785 r300_mark_fb_state_dirty(r300, R300_CHANGED_FB_STATE);
786 r300->validate_buffers = TRUE;
787
788 if (state->zsbuf) {
789 switch (util_format_get_blocksize(state->zsbuf->texture->format)) {
790 case 2:
791 zbuffer_bpp = 16;
792 break;
793 case 4:
794 zbuffer_bpp = 24;
795 break;
796 }
797
798 /* Setup Hyper-Z. */
799 if (can_hyperz) {
800 struct r300_surface *zs_surf = r300_surface(state->zsbuf);
801 struct r300_resource *tex = r300_resource(zs_surf->base.texture);
802 int level = zs_surf->base.u.tex.level;
803
804 /* work out whether we can support hiz on this buffer */
805 r300_hiz_alloc_block(r300, zs_surf);
806
807 DBG(r300, DBG_HYPERZ,
808 "hyper-z features: hiz: %d @ %08x\n", tex->hiz_mem[level] ? 1 : 0,
809 tex->hiz_mem[level] ? tex->hiz_mem[level]->ofs : 0xdeadbeef);
810 }
811
812 /* Polygon offset depends on the zbuffer bit depth. */
813 if (r300->zbuffer_bpp != zbuffer_bpp) {
814 r300->zbuffer_bpp = zbuffer_bpp;
815
816 if (r300->polygon_offset_enabled)
817 r300_mark_atom_dirty(r300, &r300->rs_state);
818 }
819 }
820
821 /* Set up AA config. */
822 if (r300->rws->get_value(r300->rws, R300_VID_DRM_2_3_0)) {
823 if (state->nr_cbufs && state->cbufs[0]->texture->nr_samples > 1) {
824 aa->aa_config = R300_GB_AA_CONFIG_AA_ENABLE;
825
826 switch (state->cbufs[0]->texture->nr_samples) {
827 case 2:
828 aa->aa_config |= R300_GB_AA_CONFIG_NUM_AA_SUBSAMPLES_2;
829 break;
830 case 3:
831 aa->aa_config |= R300_GB_AA_CONFIG_NUM_AA_SUBSAMPLES_3;
832 break;
833 case 4:
834 aa->aa_config |= R300_GB_AA_CONFIG_NUM_AA_SUBSAMPLES_4;
835 break;
836 case 6:
837 aa->aa_config |= R300_GB_AA_CONFIG_NUM_AA_SUBSAMPLES_6;
838 break;
839 }
840 } else {
841 aa->aa_config = 0;
842 }
843 }
844
845 if (DBG_ON(r300, DBG_FB)) {
846 fprintf(stderr, "r300: set_framebuffer_state:\n");
847 for (i = 0; i < state->nr_cbufs; i++) {
848 r300_print_fb_surf_info(state->cbufs[i], i, "CB");
849 }
850 if (state->zsbuf) {
851 r300_print_fb_surf_info(state->zsbuf, 0, "ZB");
852 }
853 }
854 }
855
856 /* Create fragment shader state. */
857 static void* r300_create_fs_state(struct pipe_context* pipe,
858 const struct pipe_shader_state* shader)
859 {
860 struct r300_fragment_shader* fs = NULL;
861
862 fs = (struct r300_fragment_shader*)CALLOC_STRUCT(r300_fragment_shader);
863
864 /* Copy state directly into shader. */
865 fs->state = *shader;
866 fs->state.tokens = tgsi_dup_tokens(shader->tokens);
867
868 return (void*)fs;
869 }
870
871 void r300_mark_fs_code_dirty(struct r300_context *r300)
872 {
873 struct r300_fragment_shader* fs = r300_fs(r300);
874
875 r300_mark_atom_dirty(r300, &r300->fs);
876 r300_mark_atom_dirty(r300, &r300->fs_rc_constant_state);
877 r300_mark_atom_dirty(r300, &r300->fs_constants);
878 r300->fs.size = fs->shader->cb_code_size;
879
880 if (r300->screen->caps.is_r500) {
881 r300->fs_rc_constant_state.size = fs->shader->rc_state_count * 7;
882 r300->fs_constants.size = fs->shader->externals_count * 4 + 3;
883 } else {
884 r300->fs_rc_constant_state.size = fs->shader->rc_state_count * 5;
885 r300->fs_constants.size = fs->shader->externals_count * 4 + 1;
886 }
887
888 ((struct r300_constant_buffer*)r300->fs_constants.state)->remap_table =
889 fs->shader->code.constants_remap_table;
890 }
891
892 /* Bind fragment shader state. */
893 static void r300_bind_fs_state(struct pipe_context* pipe, void* shader)
894 {
895 struct r300_context* r300 = r300_context(pipe);
896 struct r300_fragment_shader* fs = (struct r300_fragment_shader*)shader;
897 struct pipe_framebuffer_state *fb = r300->fb_state.state;
898 boolean last_multi_write;
899
900 if (fs == NULL) {
901 r300->fs.state = NULL;
902 return;
903 }
904
905 last_multi_write = r300_fragment_shader_writes_all(r300_fs(r300));
906
907 r300->fs.state = fs;
908 r300_pick_fragment_shader(r300);
909 r300_mark_fs_code_dirty(r300);
910
911 if (fb->nr_cbufs > 1 &&
912 last_multi_write != r300_fragment_shader_writes_all(fs)) {
913 r300_mark_fb_state_dirty(r300, R300_CHANGED_MULTIWRITE);
914 }
915
916 r300_mark_atom_dirty(r300, &r300->rs_block_state); /* Will be updated before the emission. */
917 }
918
919 /* Delete fragment shader state. */
920 static void r300_delete_fs_state(struct pipe_context* pipe, void* shader)
921 {
922 struct r300_fragment_shader* fs = (struct r300_fragment_shader*)shader;
923 struct r300_fragment_shader_code *tmp, *ptr = fs->first;
924
925 while (ptr) {
926 tmp = ptr;
927 ptr = ptr->next;
928 rc_constants_destroy(&tmp->code.constants);
929 FREE(tmp->cb_code);
930 FREE(tmp);
931 }
932 FREE((void*)fs->state.tokens);
933 FREE(shader);
934 }
935
936 static void r300_set_polygon_stipple(struct pipe_context* pipe,
937 const struct pipe_poly_stipple* state)
938 {
939 /* XXX no idea how to set this up, but not terribly important */
940 }
941
942 /* Create a new rasterizer state based on the CSO rasterizer state.
943 *
944 * This is a very large chunk of state, and covers most of the graphics
945 * backend (GB), geometry assembly (GA), and setup unit (SU) blocks.
946 *
947 * In a not entirely unironic sidenote, this state has nearly nothing to do
948 * with the actual block on the Radeon called the rasterizer (RS). */
949 static void* r300_create_rs_state(struct pipe_context* pipe,
950 const struct pipe_rasterizer_state* state)
951 {
952 struct r300_rs_state* rs = CALLOC_STRUCT(r300_rs_state);
953 float psiz;
954 uint32_t vap_control_status; /* R300_VAP_CNTL_STATUS: 0x2140 */
955 uint32_t point_size; /* R300_GA_POINT_SIZE: 0x421c */
956 uint32_t point_minmax; /* R300_GA_POINT_MINMAX: 0x4230 */
957 uint32_t line_control; /* R300_GA_LINE_CNTL: 0x4234 */
958 uint32_t polygon_offset_enable; /* R300_SU_POLY_OFFSET_ENABLE: 0x42b4 */
959 uint32_t cull_mode; /* R300_SU_CULL_MODE: 0x42b8 */
960 uint32_t line_stipple_config; /* R300_GA_LINE_STIPPLE_CONFIG: 0x4328 */
961 uint32_t line_stipple_value; /* R300_GA_LINE_STIPPLE_VALUE: 0x4260 */
962 uint32_t polygon_mode; /* R300_GA_POLY_MODE: 0x4288 */
963 uint32_t clip_rule; /* R300_SC_CLIP_RULE: 0x43D0 */
964
965 /* Point sprites texture coordinates, 0: lower left, 1: upper right */
966 float point_texcoord_left = 0; /* R300_GA_POINT_S0: 0x4200 */
967 float point_texcoord_bottom = 0;/* R300_GA_POINT_T0: 0x4204 */
968 float point_texcoord_right = 1; /* R300_GA_POINT_S1: 0x4208 */
969 float point_texcoord_top = 0; /* R300_GA_POINT_T1: 0x420c */
970 CB_LOCALS;
971
972 /* Copy rasterizer state. */
973 rs->rs = *state;
974 rs->rs_draw = *state;
975
976 rs->rs.sprite_coord_enable = state->point_quad_rasterization *
977 state->sprite_coord_enable;
978
979 /* Override some states for Draw. */
980 rs->rs_draw.sprite_coord_enable = 0; /* We can do this in HW. */
981
982 #ifdef PIPE_ARCH_LITTLE_ENDIAN
983 vap_control_status = R300_VC_NO_SWAP;
984 #else
985 vap_control_status = R300_VC_32BIT_SWAP;
986 #endif
987
988 /* If no TCL engine is present, turn off the HW TCL. */
989 if (!r300_screen(pipe->screen)->caps.has_tcl) {
990 vap_control_status |= R300_VAP_TCL_BYPASS;
991 }
992
993 /* Point size width and height. */
994 point_size =
995 pack_float_16_6x(state->point_size) |
996 (pack_float_16_6x(state->point_size) << R300_POINTSIZE_X_SHIFT);
997
998 /* Point size clamping. */
999 if (state->point_size_per_vertex) {
1000 /* Per-vertex point size.
1001 * Clamp to [0, max FB size] */
1002 psiz = pipe->screen->get_paramf(pipe->screen,
1003 PIPE_CAP_MAX_POINT_WIDTH);
1004 point_minmax =
1005 pack_float_16_6x(psiz) << R300_GA_POINT_MINMAX_MAX_SHIFT;
1006 } else {
1007 /* We cannot disable the point-size vertex output,
1008 * so clamp it. */
1009 psiz = state->point_size;
1010 point_minmax =
1011 (pack_float_16_6x(psiz) << R300_GA_POINT_MINMAX_MIN_SHIFT) |
1012 (pack_float_16_6x(psiz) << R300_GA_POINT_MINMAX_MAX_SHIFT);
1013 }
1014
1015 /* Line control. */
1016 line_control = pack_float_16_6x(state->line_width) |
1017 R300_GA_LINE_CNTL_END_TYPE_COMP;
1018
1019 /* Enable polygon mode */
1020 polygon_mode = 0;
1021 if (state->fill_front != PIPE_POLYGON_MODE_FILL ||
1022 state->fill_back != PIPE_POLYGON_MODE_FILL) {
1023 polygon_mode = R300_GA_POLY_MODE_DUAL;
1024 }
1025
1026 /* Front face */
1027 if (state->front_ccw)
1028 cull_mode = R300_FRONT_FACE_CCW;
1029 else
1030 cull_mode = R300_FRONT_FACE_CW;
1031
1032 /* Polygon offset */
1033 polygon_offset_enable = 0;
1034 if (util_get_offset(state, state->fill_front)) {
1035 polygon_offset_enable |= R300_FRONT_ENABLE;
1036 }
1037 if (util_get_offset(state, state->fill_back)) {
1038 polygon_offset_enable |= R300_BACK_ENABLE;
1039 }
1040
1041 rs->polygon_offset_enable = polygon_offset_enable != 0;
1042
1043 /* Polygon mode */
1044 if (polygon_mode) {
1045 polygon_mode |=
1046 r300_translate_polygon_mode_front(state->fill_front);
1047 polygon_mode |=
1048 r300_translate_polygon_mode_back(state->fill_back);
1049 }
1050
1051 if (state->cull_face & PIPE_FACE_FRONT) {
1052 cull_mode |= R300_CULL_FRONT;
1053 }
1054 if (state->cull_face & PIPE_FACE_BACK) {
1055 cull_mode |= R300_CULL_BACK;
1056 }
1057
1058 if (state->line_stipple_enable) {
1059 line_stipple_config =
1060 R300_GA_LINE_STIPPLE_CONFIG_LINE_RESET_LINE |
1061 (fui((float)state->line_stipple_factor) &
1062 R300_GA_LINE_STIPPLE_CONFIG_STIPPLE_SCALE_MASK);
1063 /* XXX this might need to be scaled up */
1064 line_stipple_value = state->line_stipple_pattern;
1065 } else {
1066 line_stipple_config = 0;
1067 line_stipple_value = 0;
1068 }
1069
1070 if (state->flatshade) {
1071 rs->color_control = R300_SHADE_MODEL_FLAT;
1072 } else {
1073 rs->color_control = R300_SHADE_MODEL_SMOOTH;
1074 }
1075
1076 clip_rule = state->scissor ? 0xAAAA : 0xFFFF;
1077
1078 /* Point sprites coord mode */
1079 if (rs->rs.sprite_coord_enable) {
1080 switch (state->sprite_coord_mode) {
1081 case PIPE_SPRITE_COORD_UPPER_LEFT:
1082 point_texcoord_top = 0.0f;
1083 point_texcoord_bottom = 1.0f;
1084 break;
1085 case PIPE_SPRITE_COORD_LOWER_LEFT:
1086 point_texcoord_top = 1.0f;
1087 point_texcoord_bottom = 0.0f;
1088 break;
1089 }
1090 }
1091
1092 /* Build the main command buffer. */
1093 BEGIN_CB(rs->cb_main, RS_STATE_MAIN_SIZE);
1094 OUT_CB_REG(R300_VAP_CNTL_STATUS, vap_control_status);
1095 OUT_CB_REG(R300_GA_POINT_SIZE, point_size);
1096 OUT_CB_REG_SEQ(R300_GA_POINT_MINMAX, 2);
1097 OUT_CB(point_minmax);
1098 OUT_CB(line_control);
1099 OUT_CB_REG_SEQ(R300_SU_POLY_OFFSET_ENABLE, 2);
1100 OUT_CB(polygon_offset_enable);
1101 rs->cull_mode_index = 9;
1102 OUT_CB(cull_mode);
1103 OUT_CB_REG(R300_GA_LINE_STIPPLE_CONFIG, line_stipple_config);
1104 OUT_CB_REG(R300_GA_LINE_STIPPLE_VALUE, line_stipple_value);
1105 OUT_CB_REG(R300_GA_POLY_MODE, polygon_mode);
1106 OUT_CB_REG(R300_SC_CLIP_RULE, clip_rule);
1107 OUT_CB_REG_SEQ(R300_GA_POINT_S0, 4);
1108 OUT_CB_32F(point_texcoord_left);
1109 OUT_CB_32F(point_texcoord_bottom);
1110 OUT_CB_32F(point_texcoord_right);
1111 OUT_CB_32F(point_texcoord_top);
1112 END_CB;
1113
1114 /* Build the two command buffers for polygon offset setup. */
1115 if (polygon_offset_enable) {
1116 float scale = state->offset_scale * 12;
1117 float offset = state->offset_units * 4;
1118
1119 BEGIN_CB(rs->cb_poly_offset_zb16, 5);
1120 OUT_CB_REG_SEQ(R300_SU_POLY_OFFSET_FRONT_SCALE, 4);
1121 OUT_CB_32F(scale);
1122 OUT_CB_32F(offset);
1123 OUT_CB_32F(scale);
1124 OUT_CB_32F(offset);
1125 END_CB;
1126
1127 offset = state->offset_units * 2;
1128
1129 BEGIN_CB(rs->cb_poly_offset_zb24, 5);
1130 OUT_CB_REG_SEQ(R300_SU_POLY_OFFSET_FRONT_SCALE, 4);
1131 OUT_CB_32F(scale);
1132 OUT_CB_32F(offset);
1133 OUT_CB_32F(scale);
1134 OUT_CB_32F(offset);
1135 END_CB;
1136 }
1137
1138 return (void*)rs;
1139 }
1140
1141 /* Bind rasterizer state. */
1142 static void r300_bind_rs_state(struct pipe_context* pipe, void* state)
1143 {
1144 struct r300_context* r300 = r300_context(pipe);
1145 struct r300_rs_state* rs = (struct r300_rs_state*)state;
1146 int last_sprite_coord_enable = r300->sprite_coord_enable;
1147 boolean last_two_sided_color = r300->two_sided_color;
1148
1149 if (r300->draw && rs) {
1150 draw_set_rasterizer_state(r300->draw, &rs->rs_draw, state);
1151 }
1152
1153 if (rs) {
1154 r300->polygon_offset_enabled = rs->polygon_offset_enable;
1155 r300->sprite_coord_enable = rs->rs.sprite_coord_enable;
1156 r300->two_sided_color = rs->rs.light_twoside;
1157 } else {
1158 r300->polygon_offset_enabled = FALSE;
1159 r300->sprite_coord_enable = 0;
1160 r300->two_sided_color = FALSE;
1161 }
1162
1163 UPDATE_STATE(state, r300->rs_state);
1164 r300->rs_state.size = RS_STATE_MAIN_SIZE + (r300->polygon_offset_enabled ? 5 : 0);
1165
1166 if (last_sprite_coord_enable != r300->sprite_coord_enable ||
1167 last_two_sided_color != r300->two_sided_color) {
1168 r300_mark_atom_dirty(r300, &r300->rs_block_state);
1169 }
1170 }
1171
1172 /* Free rasterizer state. */
1173 static void r300_delete_rs_state(struct pipe_context* pipe, void* state)
1174 {
1175 FREE(state);
1176 }
1177
1178 static void*
1179 r300_create_sampler_state(struct pipe_context* pipe,
1180 const struct pipe_sampler_state* state)
1181 {
1182 struct r300_context* r300 = r300_context(pipe);
1183 struct r300_sampler_state* sampler = CALLOC_STRUCT(r300_sampler_state);
1184 boolean is_r500 = r300->screen->caps.is_r500;
1185 int lod_bias;
1186
1187 sampler->state = *state;
1188
1189 /* r300 doesn't handle CLAMP and MIRROR_CLAMP correctly when either MAG
1190 * or MIN filter is NEAREST. Since texwrap produces same results
1191 * for CLAMP and CLAMP_TO_EDGE, we use them instead. */
1192 if (sampler->state.min_img_filter == PIPE_TEX_FILTER_NEAREST ||
1193 sampler->state.mag_img_filter == PIPE_TEX_FILTER_NEAREST) {
1194 /* Wrap S. */
1195 if (sampler->state.wrap_s == PIPE_TEX_WRAP_CLAMP)
1196 sampler->state.wrap_s = PIPE_TEX_WRAP_CLAMP_TO_EDGE;
1197 else if (sampler->state.wrap_s == PIPE_TEX_WRAP_MIRROR_CLAMP)
1198 sampler->state.wrap_s = PIPE_TEX_WRAP_MIRROR_CLAMP_TO_EDGE;
1199
1200 /* Wrap T. */
1201 if (sampler->state.wrap_t == PIPE_TEX_WRAP_CLAMP)
1202 sampler->state.wrap_t = PIPE_TEX_WRAP_CLAMP_TO_EDGE;
1203 else if (sampler->state.wrap_t == PIPE_TEX_WRAP_MIRROR_CLAMP)
1204 sampler->state.wrap_t = PIPE_TEX_WRAP_MIRROR_CLAMP_TO_EDGE;
1205
1206 /* Wrap R. */
1207 if (sampler->state.wrap_r == PIPE_TEX_WRAP_CLAMP)
1208 sampler->state.wrap_r = PIPE_TEX_WRAP_CLAMP_TO_EDGE;
1209 else if (sampler->state.wrap_r == PIPE_TEX_WRAP_MIRROR_CLAMP)
1210 sampler->state.wrap_r = PIPE_TEX_WRAP_MIRROR_CLAMP_TO_EDGE;
1211 }
1212
1213 sampler->filter0 |=
1214 (r300_translate_wrap(sampler->state.wrap_s) << R300_TX_WRAP_S_SHIFT) |
1215 (r300_translate_wrap(sampler->state.wrap_t) << R300_TX_WRAP_T_SHIFT) |
1216 (r300_translate_wrap(sampler->state.wrap_r) << R300_TX_WRAP_R_SHIFT);
1217
1218 sampler->filter0 |= r300_translate_tex_filters(state->min_img_filter,
1219 state->mag_img_filter,
1220 state->min_mip_filter,
1221 state->max_anisotropy > 0);
1222
1223 sampler->filter0 |= r300_anisotropy(state->max_anisotropy);
1224
1225 /* Unfortunately, r300-r500 don't support floating-point mipmap lods. */
1226 /* We must pass these to the merge function to clamp them properly. */
1227 sampler->min_lod = (unsigned)MAX2(state->min_lod, 0);
1228 sampler->max_lod = (unsigned)MAX2(ceilf(state->max_lod), 0);
1229
1230 lod_bias = CLAMP((int)(state->lod_bias * 32 + 1), -(1 << 9), (1 << 9) - 1);
1231
1232 sampler->filter1 |= (lod_bias << R300_LOD_BIAS_SHIFT) & R300_LOD_BIAS_MASK;
1233
1234 /* This is very high quality anisotropic filtering for R5xx.
1235 * It's good for benchmarking the performance of texturing but
1236 * in practice we don't want to slow down the driver because it's
1237 * a pretty good performance killer. Feel free to play with it. */
1238 if (DBG_ON(r300, DBG_ANISOHQ) && is_r500) {
1239 sampler->filter1 |= r500_anisotropy(state->max_anisotropy);
1240 }
1241
1242 /* R500-specific fixups and optimizations */
1243 if (r300->screen->caps.is_r500) {
1244 sampler->filter1 |= R500_BORDER_FIX;
1245 }
1246
1247 return (void*)sampler;
1248 }
1249
1250 static void r300_bind_sampler_states(struct pipe_context* pipe,
1251 unsigned count,
1252 void** states)
1253 {
1254 struct r300_context* r300 = r300_context(pipe);
1255 struct r300_textures_state* state =
1256 (struct r300_textures_state*)r300->textures_state.state;
1257 unsigned tex_units = r300->screen->caps.num_tex_units;
1258
1259 if (count > tex_units) {
1260 return;
1261 }
1262
1263 memcpy(state->sampler_states, states, sizeof(void*) * count);
1264 state->sampler_state_count = count;
1265
1266 r300_mark_atom_dirty(r300, &r300->textures_state);
1267 }
1268
1269 static void r300_lacks_vertex_textures(struct pipe_context* pipe,
1270 unsigned count,
1271 void** states)
1272 {
1273 }
1274
1275 static void r300_delete_sampler_state(struct pipe_context* pipe, void* state)
1276 {
1277 FREE(state);
1278 }
1279
1280 static uint32_t r300_assign_texture_cache_region(unsigned index, unsigned num)
1281 {
1282 /* This looks like a hack, but I believe it's suppose to work like
1283 * that. To illustrate how this works, let's assume you have 5 textures.
1284 * From docs, 5 and the successive numbers are:
1285 *
1286 * FOURTH_1 = 5
1287 * FOURTH_2 = 6
1288 * FOURTH_3 = 7
1289 * EIGHTH_0 = 8
1290 * EIGHTH_1 = 9
1291 *
1292 * First 3 textures will get 3/4 of size of the cache, divived evenly
1293 * between them. The last 1/4 of the cache must be divided between
1294 * the last 2 textures, each will therefore get 1/8 of the cache.
1295 * Why not just to use "5 + texture_index" ?
1296 *
1297 * This simple trick works for all "num" <= 16.
1298 */
1299 if (num <= 1)
1300 return R300_TX_CACHE(R300_TX_CACHE_WHOLE);
1301 else
1302 return R300_TX_CACHE(num + index);
1303 }
1304
1305 static void r300_set_fragment_sampler_views(struct pipe_context* pipe,
1306 unsigned count,
1307 struct pipe_sampler_view** views)
1308 {
1309 struct r300_context* r300 = r300_context(pipe);
1310 struct r300_textures_state* state =
1311 (struct r300_textures_state*)r300->textures_state.state;
1312 struct r300_resource *texture;
1313 unsigned i, real_num_views = 0, view_index = 0;
1314 unsigned tex_units = r300->screen->caps.num_tex_units;
1315 boolean dirty_tex = FALSE;
1316
1317 if (count > tex_units) {
1318 return;
1319 }
1320
1321 /* Calculate the real number of views. */
1322 for (i = 0; i < count; i++) {
1323 if (views[i])
1324 real_num_views++;
1325 }
1326
1327 for (i = 0; i < count; i++) {
1328 pipe_sampler_view_reference(
1329 (struct pipe_sampler_view**)&state->sampler_views[i],
1330 views[i]);
1331
1332 if (!views[i]) {
1333 continue;
1334 }
1335
1336 /* A new sampler view (= texture)... */
1337 dirty_tex = TRUE;
1338
1339 /* Set the texrect factor in the fragment shader.
1340 * Needed for RECT and NPOT fallback. */
1341 texture = r300_resource(views[i]->texture);
1342 if (texture->tex.is_npot) {
1343 r300_mark_atom_dirty(r300, &r300->fs_rc_constant_state);
1344 }
1345
1346 state->sampler_views[i]->texcache_region =
1347 r300_assign_texture_cache_region(view_index, real_num_views);
1348 view_index++;
1349 }
1350
1351 for (i = count; i < tex_units; i++) {
1352 if (state->sampler_views[i]) {
1353 pipe_sampler_view_reference(
1354 (struct pipe_sampler_view**)&state->sampler_views[i],
1355 NULL);
1356 }
1357 }
1358
1359 state->sampler_view_count = count;
1360
1361 r300_mark_atom_dirty(r300, &r300->textures_state);
1362 r300->validate_buffers = TRUE;
1363
1364 if (dirty_tex) {
1365 r300_mark_atom_dirty(r300, &r300->texture_cache_inval);
1366 }
1367 }
1368
1369 static struct pipe_sampler_view *
1370 r300_create_sampler_view(struct pipe_context *pipe,
1371 struct pipe_resource *texture,
1372 const struct pipe_sampler_view *templ)
1373 {
1374 struct r300_sampler_view *view = CALLOC_STRUCT(r300_sampler_view);
1375 struct r300_resource *tex = r300_resource(texture);
1376 boolean is_r500 = r300_screen(pipe->screen)->caps.is_r500;
1377 boolean dxtc_swizzle = r300_screen(pipe->screen)->caps.dxtc_swizzle;
1378
1379 if (view) {
1380 view->base = *templ;
1381 view->base.reference.count = 1;
1382 view->base.context = pipe;
1383 view->base.texture = NULL;
1384 pipe_resource_reference(&view->base.texture, texture);
1385
1386 view->swizzle[0] = templ->swizzle_r;
1387 view->swizzle[1] = templ->swizzle_g;
1388 view->swizzle[2] = templ->swizzle_b;
1389 view->swizzle[3] = templ->swizzle_a;
1390
1391 view->format = tex->tx_format;
1392 view->format.format1 |= r300_translate_texformat(templ->format,
1393 view->swizzle,
1394 is_r500,
1395 dxtc_swizzle);
1396 if (is_r500) {
1397 view->format.format2 |= r500_tx_format_msb_bit(templ->format);
1398 }
1399 }
1400
1401 return (struct pipe_sampler_view*)view;
1402 }
1403
1404 static void
1405 r300_sampler_view_destroy(struct pipe_context *pipe,
1406 struct pipe_sampler_view *view)
1407 {
1408 pipe_resource_reference(&view->texture, NULL);
1409 FREE(view);
1410 }
1411
1412 static void r300_set_scissor_state(struct pipe_context* pipe,
1413 const struct pipe_scissor_state* state)
1414 {
1415 struct r300_context* r300 = r300_context(pipe);
1416
1417 memcpy(r300->scissor_state.state, state,
1418 sizeof(struct pipe_scissor_state));
1419
1420 r300_mark_atom_dirty(r300, &r300->scissor_state);
1421 }
1422
1423 static void r300_set_viewport_state(struct pipe_context* pipe,
1424 const struct pipe_viewport_state* state)
1425 {
1426 struct r300_context* r300 = r300_context(pipe);
1427 struct r300_viewport_state* viewport =
1428 (struct r300_viewport_state*)r300->viewport_state.state;
1429
1430 r300->viewport = *state;
1431
1432 if (r300->draw) {
1433 draw_set_viewport_state(r300->draw, state);
1434 viewport->vte_control = R300_VTX_XY_FMT | R300_VTX_Z_FMT;
1435 return;
1436 }
1437
1438 /* Do the transform in HW. */
1439 viewport->vte_control = R300_VTX_W0_FMT;
1440
1441 if (state->scale[0] != 1.0f) {
1442 viewport->xscale = state->scale[0];
1443 viewport->vte_control |= R300_VPORT_X_SCALE_ENA;
1444 }
1445 if (state->scale[1] != 1.0f) {
1446 viewport->yscale = state->scale[1];
1447 viewport->vte_control |= R300_VPORT_Y_SCALE_ENA;
1448 }
1449 if (state->scale[2] != 1.0f) {
1450 viewport->zscale = state->scale[2];
1451 viewport->vte_control |= R300_VPORT_Z_SCALE_ENA;
1452 }
1453 if (state->translate[0] != 0.0f) {
1454 viewport->xoffset = state->translate[0];
1455 viewport->vte_control |= R300_VPORT_X_OFFSET_ENA;
1456 }
1457 if (state->translate[1] != 0.0f) {
1458 viewport->yoffset = state->translate[1];
1459 viewport->vte_control |= R300_VPORT_Y_OFFSET_ENA;
1460 }
1461 if (state->translate[2] != 0.0f) {
1462 viewport->zoffset = state->translate[2];
1463 viewport->vte_control |= R300_VPORT_Z_OFFSET_ENA;
1464 }
1465
1466 r300_mark_atom_dirty(r300, &r300->viewport_state);
1467 if (r300->fs.state && r300_fs(r300)->shader->inputs.wpos != ATTR_UNUSED) {
1468 r300_mark_atom_dirty(r300, &r300->fs_rc_constant_state);
1469 }
1470 }
1471
1472 static void r300_set_vertex_buffers(struct pipe_context* pipe,
1473 unsigned count,
1474 const struct pipe_vertex_buffer* buffers)
1475 {
1476 struct r300_context* r300 = r300_context(pipe);
1477 unsigned i;
1478 struct pipe_vertex_buffer dummy_vb = {0};
1479
1480 /* There must be at least one vertex buffer set, otherwise it locks up. */
1481 if (!count) {
1482 dummy_vb.buffer = r300->dummy_vb;
1483 buffers = &dummy_vb;
1484 count = 1;
1485 }
1486
1487 u_vbuf_mgr_set_vertex_buffers(r300->vbuf_mgr, count, buffers);
1488
1489 if (r300->screen->caps.has_tcl) {
1490 /* HW TCL. */
1491 for (i = 0; i < count; i++) {
1492 if (buffers[i].buffer &&
1493 !r300_resource(buffers[i].buffer)->b.user_ptr) {
1494 r300->validate_buffers = TRUE;
1495 }
1496 }
1497 r300->vertex_arrays_dirty = TRUE;
1498 } else {
1499 /* SW TCL. */
1500 draw_set_vertex_buffers(r300->draw, count, buffers);
1501 }
1502 }
1503
1504 static void r300_set_index_buffer(struct pipe_context* pipe,
1505 const struct pipe_index_buffer *ib)
1506 {
1507 struct r300_context* r300 = r300_context(pipe);
1508
1509 if (ib && ib->buffer) {
1510 assert(ib->offset % ib->index_size == 0);
1511
1512 pipe_resource_reference(&r300->index_buffer.buffer, ib->buffer);
1513 memcpy(&r300->index_buffer, ib, sizeof(r300->index_buffer));
1514 r300->index_buffer.offset /= r300->index_buffer.index_size;
1515
1516 if (r300->screen->caps.has_tcl &&
1517 !r300_resource(ib->buffer)->b.user_ptr) {
1518 r300->validate_buffers = TRUE;
1519 r300->upload_ib_validated = FALSE;
1520 }
1521 }
1522 else {
1523 pipe_resource_reference(&r300->index_buffer.buffer, NULL);
1524 memset(&r300->index_buffer, 0, sizeof(r300->index_buffer));
1525 }
1526
1527 if (!r300->screen->caps.has_tcl) {
1528 draw_set_index_buffer(r300->draw, ib);
1529 }
1530 }
1531
1532 /* Initialize the PSC tables. */
1533 static void r300_vertex_psc(struct r300_vertex_element_state *velems)
1534 {
1535 struct r300_vertex_stream_state *vstream = &velems->vertex_stream;
1536 uint16_t type, swizzle;
1537 enum pipe_format format;
1538 unsigned i;
1539
1540 if (velems->count > 16) {
1541 fprintf(stderr, "r300: More than 16 vertex elements are not supported,"
1542 " requested %i, using 16.\n", velems->count);
1543 velems->count = 16;
1544 }
1545
1546 /* Vertex shaders have no semantics on their inputs,
1547 * so PSC should just route stuff based on the vertex elements,
1548 * and not on attrib information. */
1549 for (i = 0; i < velems->count; i++) {
1550 format = velems->velem[i].src_format;
1551
1552 type = r300_translate_vertex_data_type(format);
1553 if (type == R300_INVALID_FORMAT) {
1554 fprintf(stderr, "r300: Bad vertex format %s.\n",
1555 util_format_short_name(format));
1556 assert(0);
1557 abort();
1558 }
1559
1560 type |= i << R300_DST_VEC_LOC_SHIFT;
1561 swizzle = r300_translate_vertex_data_swizzle(format);
1562
1563 if (i & 1) {
1564 vstream->vap_prog_stream_cntl[i >> 1] |= type << 16;
1565 vstream->vap_prog_stream_cntl_ext[i >> 1] |= swizzle << 16;
1566 } else {
1567 vstream->vap_prog_stream_cntl[i >> 1] |= type;
1568 vstream->vap_prog_stream_cntl_ext[i >> 1] |= swizzle;
1569 }
1570 }
1571
1572 /* Set the last vector in the PSC. */
1573 if (i) {
1574 i -= 1;
1575 }
1576 vstream->vap_prog_stream_cntl[i >> 1] |=
1577 (R300_LAST_VEC << (i & 1 ? 16 : 0));
1578
1579 vstream->count = (i >> 1) + 1;
1580 }
1581
1582 static void* r300_create_vertex_elements_state(struct pipe_context* pipe,
1583 unsigned count,
1584 const struct pipe_vertex_element* attribs)
1585 {
1586 struct r300_context *r300 = r300_context(pipe);
1587 struct r300_vertex_element_state *velems;
1588 unsigned i;
1589 struct pipe_vertex_element dummy_attrib = {0};
1590
1591 /* R300 Programmable Stream Control (PSC) doesn't support 0 vertex elements. */
1592 if (!count) {
1593 dummy_attrib.src_format = PIPE_FORMAT_R8G8B8A8_UNORM;
1594 attribs = &dummy_attrib;
1595 count = 1;
1596 }
1597
1598 assert(count <= PIPE_MAX_ATTRIBS);
1599 velems = CALLOC_STRUCT(r300_vertex_element_state);
1600 if (!velems)
1601 return NULL;
1602
1603 velems->count = count;
1604 velems->vmgr_elements =
1605 u_vbuf_mgr_create_vertex_elements(r300->vbuf_mgr, count, attribs,
1606 velems->velem);
1607
1608 if (r300_screen(pipe->screen)->caps.has_tcl) {
1609 /* Setup PSC.
1610 * The unused components will be replaced by (..., 0, 1). */
1611 r300_vertex_psc(velems);
1612
1613 for (i = 0; i < count; i++) {
1614 velems->format_size[i] =
1615 align(util_format_get_blocksize(velems->velem[i].src_format), 4);
1616 velems->vertex_size_dwords += velems->format_size[i] / 4;
1617 }
1618 }
1619
1620 return velems;
1621 }
1622
1623 static void r300_bind_vertex_elements_state(struct pipe_context *pipe,
1624 void *state)
1625 {
1626 struct r300_context *r300 = r300_context(pipe);
1627 struct r300_vertex_element_state *velems = state;
1628
1629 if (velems == NULL) {
1630 return;
1631 }
1632
1633 r300->velems = velems;
1634
1635 u_vbuf_mgr_bind_vertex_elements(r300->vbuf_mgr, state, velems->vmgr_elements);
1636
1637 if (r300->draw) {
1638 draw_set_vertex_elements(r300->draw, velems->count, velems->velem);
1639 return;
1640 }
1641
1642 UPDATE_STATE(&velems->vertex_stream, r300->vertex_stream_state);
1643 r300->vertex_stream_state.size = (1 + velems->vertex_stream.count) * 2;
1644 r300->vertex_arrays_dirty = TRUE;
1645 }
1646
1647 static void r300_delete_vertex_elements_state(struct pipe_context *pipe, void *state)
1648 {
1649 struct r300_context *r300 = r300_context(pipe);
1650 struct r300_vertex_element_state *velems = state;
1651
1652 u_vbuf_mgr_destroy_vertex_elements(r300->vbuf_mgr, velems->vmgr_elements);
1653 FREE(state);
1654 }
1655
1656 static void* r300_create_vs_state(struct pipe_context* pipe,
1657 const struct pipe_shader_state* shader)
1658 {
1659 struct r300_context* r300 = r300_context(pipe);
1660 struct r300_vertex_shader* vs = CALLOC_STRUCT(r300_vertex_shader);
1661
1662 /* Copy state directly into shader. */
1663 vs->state = *shader;
1664 vs->state.tokens = tgsi_dup_tokens(shader->tokens);
1665
1666 if (r300->screen->caps.has_tcl) {
1667 r300_init_vs_outputs(vs);
1668 r300_translate_vertex_shader(r300, vs);
1669 } else {
1670 r300_draw_init_vertex_shader(r300->draw, vs);
1671 }
1672
1673 return vs;
1674 }
1675
1676 static void r300_bind_vs_state(struct pipe_context* pipe, void* shader)
1677 {
1678 struct r300_context* r300 = r300_context(pipe);
1679 struct r300_vertex_shader* vs = (struct r300_vertex_shader*)shader;
1680
1681 if (vs == NULL) {
1682 r300->vs_state.state = NULL;
1683 return;
1684 }
1685 if (vs == r300->vs_state.state) {
1686 return;
1687 }
1688 r300->vs_state.state = vs;
1689
1690 /* The majority of the RS block bits is dependent on the vertex shader. */
1691 r300_mark_atom_dirty(r300, &r300->rs_block_state); /* Will be updated before the emission. */
1692
1693 if (r300->screen->caps.has_tcl) {
1694 unsigned fc_op_dwords = r300->screen->caps.is_r500 ? 3 : 2;
1695 r300_mark_atom_dirty(r300, &r300->vs_state);
1696 r300->vs_state.size =
1697 vs->code.length + 9 +
1698 (vs->code.num_fc_ops ? vs->code.num_fc_ops * fc_op_dwords + 4 : 0);
1699
1700 r300_mark_atom_dirty(r300, &r300->vs_constants);
1701 r300->vs_constants.size =
1702 2 +
1703 (vs->externals_count ? vs->externals_count * 4 + 3 : 0) +
1704 (vs->immediates_count ? vs->immediates_count * 4 + 3 : 0);
1705
1706 ((struct r300_constant_buffer*)r300->vs_constants.state)->remap_table =
1707 vs->code.constants_remap_table;
1708
1709 r300_mark_atom_dirty(r300, &r300->pvs_flush);
1710 } else {
1711 draw_bind_vertex_shader(r300->draw,
1712 (struct draw_vertex_shader*)vs->draw_vs);
1713 }
1714 }
1715
1716 static void r300_delete_vs_state(struct pipe_context* pipe, void* shader)
1717 {
1718 struct r300_context* r300 = r300_context(pipe);
1719 struct r300_vertex_shader* vs = (struct r300_vertex_shader*)shader;
1720
1721 if (r300->screen->caps.has_tcl) {
1722 rc_constants_destroy(&vs->code.constants);
1723 if (vs->code.constants_remap_table)
1724 FREE(vs->code.constants_remap_table);
1725 } else {
1726 draw_delete_vertex_shader(r300->draw,
1727 (struct draw_vertex_shader*)vs->draw_vs);
1728 }
1729
1730 FREE((void*)vs->state.tokens);
1731 FREE(shader);
1732 }
1733
1734 static void r300_set_constant_buffer(struct pipe_context *pipe,
1735 uint shader, uint index,
1736 struct pipe_resource *buf)
1737 {
1738 struct r300_context* r300 = r300_context(pipe);
1739 struct r300_constant_buffer *cbuf;
1740 struct r300_resource *rbuf = r300_resource(buf);
1741 uint32_t *mapped;
1742
1743 switch (shader) {
1744 case PIPE_SHADER_VERTEX:
1745 cbuf = (struct r300_constant_buffer*)r300->vs_constants.state;
1746 break;
1747 case PIPE_SHADER_FRAGMENT:
1748 cbuf = (struct r300_constant_buffer*)r300->fs_constants.state;
1749 break;
1750 default:
1751 return;
1752 }
1753
1754 if (buf == NULL || buf->width0 == 0)
1755 return;
1756
1757 if (rbuf->b.user_ptr)
1758 mapped = (uint32_t*)rbuf->b.user_ptr;
1759 else if (rbuf->constant_buffer)
1760 mapped = (uint32_t*)rbuf->constant_buffer;
1761 else
1762 return;
1763
1764 if (shader == PIPE_SHADER_FRAGMENT ||
1765 (shader == PIPE_SHADER_VERTEX && r300->screen->caps.has_tcl)) {
1766 cbuf->ptr = mapped;
1767 }
1768
1769 if (shader == PIPE_SHADER_VERTEX) {
1770 if (r300->screen->caps.has_tcl) {
1771 struct r300_vertex_shader *vs =
1772 (struct r300_vertex_shader*)r300->vs_state.state;
1773
1774 if (!vs) {
1775 cbuf->buffer_base = 0;
1776 return;
1777 }
1778
1779 cbuf->buffer_base = r300->vs_const_base;
1780 r300->vs_const_base += vs->code.constants.Count;
1781 if (r300->vs_const_base > R500_MAX_PVS_CONST_VECS) {
1782 r300->vs_const_base = vs->code.constants.Count;
1783 cbuf->buffer_base = 0;
1784 r300_mark_atom_dirty(r300, &r300->pvs_flush);
1785 }
1786 r300_mark_atom_dirty(r300, &r300->vs_constants);
1787 } else if (r300->draw) {
1788 draw_set_mapped_constant_buffer(r300->draw, PIPE_SHADER_VERTEX,
1789 0, mapped, buf->width0);
1790 }
1791 } else if (shader == PIPE_SHADER_FRAGMENT) {
1792 r300_mark_atom_dirty(r300, &r300->fs_constants);
1793 }
1794 }
1795
1796 void r300_init_state_functions(struct r300_context* r300)
1797 {
1798 r300->context.create_blend_state = r300_create_blend_state;
1799 r300->context.bind_blend_state = r300_bind_blend_state;
1800 r300->context.delete_blend_state = r300_delete_blend_state;
1801
1802 r300->context.set_blend_color = r300_set_blend_color;
1803
1804 r300->context.set_clip_state = r300_set_clip_state;
1805 r300->context.set_sample_mask = r300_set_sample_mask;
1806
1807 r300->context.set_constant_buffer = r300_set_constant_buffer;
1808
1809 r300->context.create_depth_stencil_alpha_state = r300_create_dsa_state;
1810 r300->context.bind_depth_stencil_alpha_state = r300_bind_dsa_state;
1811 r300->context.delete_depth_stencil_alpha_state = r300_delete_dsa_state;
1812
1813 r300->context.set_stencil_ref = r300_set_stencil_ref;
1814
1815 r300->context.set_framebuffer_state = r300_set_framebuffer_state;
1816
1817 r300->context.create_fs_state = r300_create_fs_state;
1818 r300->context.bind_fs_state = r300_bind_fs_state;
1819 r300->context.delete_fs_state = r300_delete_fs_state;
1820
1821 r300->context.set_polygon_stipple = r300_set_polygon_stipple;
1822
1823 r300->context.create_rasterizer_state = r300_create_rs_state;
1824 r300->context.bind_rasterizer_state = r300_bind_rs_state;
1825 r300->context.delete_rasterizer_state = r300_delete_rs_state;
1826
1827 r300->context.create_sampler_state = r300_create_sampler_state;
1828 r300->context.bind_fragment_sampler_states = r300_bind_sampler_states;
1829 r300->context.bind_vertex_sampler_states = r300_lacks_vertex_textures;
1830 r300->context.delete_sampler_state = r300_delete_sampler_state;
1831
1832 r300->context.set_fragment_sampler_views = r300_set_fragment_sampler_views;
1833 r300->context.create_sampler_view = r300_create_sampler_view;
1834 r300->context.sampler_view_destroy = r300_sampler_view_destroy;
1835
1836 r300->context.set_scissor_state = r300_set_scissor_state;
1837
1838 r300->context.set_viewport_state = r300_set_viewport_state;
1839
1840 r300->context.set_vertex_buffers = r300_set_vertex_buffers;
1841 r300->context.set_index_buffer = r300_set_index_buffer;
1842 r300->context.redefine_user_buffer = u_default_redefine_user_buffer;
1843
1844 r300->context.create_vertex_elements_state = r300_create_vertex_elements_state;
1845 r300->context.bind_vertex_elements_state = r300_bind_vertex_elements_state;
1846 r300->context.delete_vertex_elements_state = r300_delete_vertex_elements_state;
1847
1848 r300->context.create_vs_state = r300_create_vs_state;
1849 r300->context.bind_vs_state = r300_bind_vs_state;
1850 r300->context.delete_vs_state = r300_delete_vs_state;
1851 }