r300g: dynamically ask for and release Hyper-Z access
[mesa.git] / src / gallium / drivers / r300 / r300_state.c
1 /*
2 * Copyright 2008 Corbin Simpson <MostAwesomeDude@gmail.com>
3 * Copyright 2009 Marek Olšák <maraeo@gmail.com>
4 *
5 * Permission is hereby granted, free of charge, to any person obtaining a
6 * copy of this software and associated documentation files (the "Software"),
7 * to deal in the Software without restriction, including without limitation
8 * on the rights to use, copy, modify, merge, publish, distribute, sub
9 * license, and/or sell copies of the Software, and to permit persons to whom
10 * the Software is furnished to do so, subject to the following conditions:
11 *
12 * The above copyright notice and this permission notice (including the next
13 * paragraph) shall be included in all copies or substantial portions of the
14 * Software.
15 *
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
19 * THE AUTHOR(S) AND/OR THEIR SUPPLIERS BE LIABLE FOR ANY CLAIM,
20 * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
21 * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
22 * USE OR OTHER DEALINGS IN THE SOFTWARE. */
23
24 #include "draw/draw_context.h"
25
26 #include "util/u_framebuffer.h"
27 #include "util/u_half.h"
28 #include "util/u_math.h"
29 #include "util/u_mm.h"
30 #include "util/u_memory.h"
31 #include "util/u_pack_color.h"
32 #include "util/u_transfer.h"
33
34 #include "tgsi/tgsi_parse.h"
35
36 #include "pipe/p_config.h"
37
38 #include "r300_cb.h"
39 #include "r300_context.h"
40 #include "r300_emit.h"
41 #include "r300_reg.h"
42 #include "r300_screen.h"
43 #include "r300_screen_buffer.h"
44 #include "r300_state_inlines.h"
45 #include "r300_fs.h"
46 #include "r300_texture.h"
47 #include "r300_vs.h"
48
49 /* r300_state: Functions used to intialize state context by translating
50 * Gallium state objects into semi-native r300 state objects. */
51
52 #define UPDATE_STATE(cso, atom) \
53 if (cso != atom.state) { \
54 atom.state = cso; \
55 r300_mark_atom_dirty(r300, &(atom)); \
56 }
57
58 static boolean blend_discard_if_src_alpha_0(unsigned srcRGB, unsigned srcA,
59 unsigned dstRGB, unsigned dstA)
60 {
61 /* If the blend equation is ADD or REVERSE_SUBTRACT,
62 * SRC_ALPHA == 0, and the following state is set, the colorbuffer
63 * will not be changed.
64 * Notice that the dst factors are the src factors inverted. */
65 return (srcRGB == PIPE_BLENDFACTOR_SRC_ALPHA ||
66 srcRGB == PIPE_BLENDFACTOR_SRC_ALPHA_SATURATE ||
67 srcRGB == PIPE_BLENDFACTOR_ZERO) &&
68 (srcA == PIPE_BLENDFACTOR_SRC_COLOR ||
69 srcA == PIPE_BLENDFACTOR_SRC_ALPHA ||
70 srcA == PIPE_BLENDFACTOR_SRC_ALPHA_SATURATE ||
71 srcA == PIPE_BLENDFACTOR_ZERO) &&
72 (dstRGB == PIPE_BLENDFACTOR_INV_SRC_ALPHA ||
73 dstRGB == PIPE_BLENDFACTOR_ONE) &&
74 (dstA == PIPE_BLENDFACTOR_INV_SRC_COLOR ||
75 dstA == PIPE_BLENDFACTOR_INV_SRC_ALPHA ||
76 dstA == PIPE_BLENDFACTOR_ONE);
77 }
78
79 static boolean blend_discard_if_src_alpha_1(unsigned srcRGB, unsigned srcA,
80 unsigned dstRGB, unsigned dstA)
81 {
82 /* If the blend equation is ADD or REVERSE_SUBTRACT,
83 * SRC_ALPHA == 1, and the following state is set, the colorbuffer
84 * will not be changed.
85 * Notice that the dst factors are the src factors inverted. */
86 return (srcRGB == PIPE_BLENDFACTOR_INV_SRC_ALPHA ||
87 srcRGB == PIPE_BLENDFACTOR_ZERO) &&
88 (srcA == PIPE_BLENDFACTOR_INV_SRC_COLOR ||
89 srcA == PIPE_BLENDFACTOR_INV_SRC_ALPHA ||
90 srcA == PIPE_BLENDFACTOR_ZERO) &&
91 (dstRGB == PIPE_BLENDFACTOR_SRC_ALPHA ||
92 dstRGB == PIPE_BLENDFACTOR_ONE) &&
93 (dstA == PIPE_BLENDFACTOR_SRC_COLOR ||
94 dstA == PIPE_BLENDFACTOR_SRC_ALPHA ||
95 dstA == PIPE_BLENDFACTOR_ONE);
96 }
97
98 static boolean blend_discard_if_src_color_0(unsigned srcRGB, unsigned srcA,
99 unsigned dstRGB, unsigned dstA)
100 {
101 /* If the blend equation is ADD or REVERSE_SUBTRACT,
102 * SRC_COLOR == (0,0,0), and the following state is set, the colorbuffer
103 * will not be changed.
104 * Notice that the dst factors are the src factors inverted. */
105 return (srcRGB == PIPE_BLENDFACTOR_SRC_COLOR ||
106 srcRGB == PIPE_BLENDFACTOR_ZERO) &&
107 (srcA == PIPE_BLENDFACTOR_ZERO) &&
108 (dstRGB == PIPE_BLENDFACTOR_INV_SRC_COLOR ||
109 dstRGB == PIPE_BLENDFACTOR_ONE) &&
110 (dstA == PIPE_BLENDFACTOR_ONE);
111 }
112
113 static boolean blend_discard_if_src_color_1(unsigned srcRGB, unsigned srcA,
114 unsigned dstRGB, unsigned dstA)
115 {
116 /* If the blend equation is ADD or REVERSE_SUBTRACT,
117 * SRC_COLOR == (1,1,1), and the following state is set, the colorbuffer
118 * will not be changed.
119 * Notice that the dst factors are the src factors inverted. */
120 return (srcRGB == PIPE_BLENDFACTOR_INV_SRC_COLOR ||
121 srcRGB == PIPE_BLENDFACTOR_ZERO) &&
122 (srcA == PIPE_BLENDFACTOR_ZERO) &&
123 (dstRGB == PIPE_BLENDFACTOR_SRC_COLOR ||
124 dstRGB == PIPE_BLENDFACTOR_ONE) &&
125 (dstA == PIPE_BLENDFACTOR_ONE);
126 }
127
128 static boolean blend_discard_if_src_alpha_color_0(unsigned srcRGB, unsigned srcA,
129 unsigned dstRGB, unsigned dstA)
130 {
131 /* If the blend equation is ADD or REVERSE_SUBTRACT,
132 * SRC_ALPHA_COLOR == (0,0,0,0), and the following state is set,
133 * the colorbuffer will not be changed.
134 * Notice that the dst factors are the src factors inverted. */
135 return (srcRGB == PIPE_BLENDFACTOR_SRC_COLOR ||
136 srcRGB == PIPE_BLENDFACTOR_SRC_ALPHA ||
137 srcRGB == PIPE_BLENDFACTOR_SRC_ALPHA_SATURATE ||
138 srcRGB == PIPE_BLENDFACTOR_ZERO) &&
139 (srcA == PIPE_BLENDFACTOR_SRC_COLOR ||
140 srcA == PIPE_BLENDFACTOR_SRC_ALPHA ||
141 srcA == PIPE_BLENDFACTOR_SRC_ALPHA_SATURATE ||
142 srcA == PIPE_BLENDFACTOR_ZERO) &&
143 (dstRGB == PIPE_BLENDFACTOR_INV_SRC_COLOR ||
144 dstRGB == PIPE_BLENDFACTOR_INV_SRC_ALPHA ||
145 dstRGB == PIPE_BLENDFACTOR_ONE) &&
146 (dstA == PIPE_BLENDFACTOR_INV_SRC_COLOR ||
147 dstA == PIPE_BLENDFACTOR_INV_SRC_ALPHA ||
148 dstA == PIPE_BLENDFACTOR_ONE);
149 }
150
151 static boolean blend_discard_if_src_alpha_color_1(unsigned srcRGB, unsigned srcA,
152 unsigned dstRGB, unsigned dstA)
153 {
154 /* If the blend equation is ADD or REVERSE_SUBTRACT,
155 * SRC_ALPHA_COLOR == (1,1,1,1), and the following state is set,
156 * the colorbuffer will not be changed.
157 * Notice that the dst factors are the src factors inverted. */
158 return (srcRGB == PIPE_BLENDFACTOR_INV_SRC_COLOR ||
159 srcRGB == PIPE_BLENDFACTOR_INV_SRC_ALPHA ||
160 srcRGB == PIPE_BLENDFACTOR_ZERO) &&
161 (srcA == PIPE_BLENDFACTOR_INV_SRC_COLOR ||
162 srcA == PIPE_BLENDFACTOR_INV_SRC_ALPHA ||
163 srcA == PIPE_BLENDFACTOR_ZERO) &&
164 (dstRGB == PIPE_BLENDFACTOR_SRC_COLOR ||
165 dstRGB == PIPE_BLENDFACTOR_SRC_ALPHA ||
166 dstRGB == PIPE_BLENDFACTOR_ONE) &&
167 (dstA == PIPE_BLENDFACTOR_SRC_COLOR ||
168 dstA == PIPE_BLENDFACTOR_SRC_ALPHA ||
169 dstA == PIPE_BLENDFACTOR_ONE);
170 }
171
172 static unsigned bgra_cmask(unsigned mask)
173 {
174 /* Gallium uses RGBA color ordering while R300 expects BGRA. */
175
176 return ((mask & PIPE_MASK_R) << 2) |
177 ((mask & PIPE_MASK_B) >> 2) |
178 (mask & (PIPE_MASK_G | PIPE_MASK_A));
179 }
180
181 /* Create a new blend state based on the CSO blend state.
182 *
183 * This encompasses alpha blending, logic/raster ops, and blend dithering. */
184 static void* r300_create_blend_state(struct pipe_context* pipe,
185 const struct pipe_blend_state* state)
186 {
187 struct r300_screen* r300screen = r300_screen(pipe->screen);
188 struct r300_blend_state* blend = CALLOC_STRUCT(r300_blend_state);
189 uint32_t blend_control = 0; /* R300_RB3D_CBLEND: 0x4e04 */
190 uint32_t blend_control_noclamp = 0; /* R300_RB3D_CBLEND: 0x4e04 */
191 uint32_t alpha_blend_control = 0; /* R300_RB3D_ABLEND: 0x4e08 */
192 uint32_t alpha_blend_control_noclamp = 0; /* R300_RB3D_ABLEND: 0x4e08 */
193 uint32_t color_channel_mask = 0; /* R300_RB3D_COLOR_CHANNEL_MASK: 0x4e0c */
194 uint32_t rop = 0; /* R300_RB3D_ROPCNTL: 0x4e18 */
195 uint32_t dither = 0; /* R300_RB3D_DITHER_CTL: 0x4e50 */
196 CB_LOCALS;
197
198 blend->state = *state;
199
200 if (state->rt[0].blend_enable)
201 {
202 unsigned eqRGB = state->rt[0].rgb_func;
203 unsigned srcRGB = state->rt[0].rgb_src_factor;
204 unsigned dstRGB = state->rt[0].rgb_dst_factor;
205
206 unsigned eqA = state->rt[0].alpha_func;
207 unsigned srcA = state->rt[0].alpha_src_factor;
208 unsigned dstA = state->rt[0].alpha_dst_factor;
209
210 /* despite the name, ALPHA_BLEND_ENABLE has nothing to do with alpha,
211 * this is just the crappy D3D naming */
212 blend_control = blend_control_noclamp =
213 R300_ALPHA_BLEND_ENABLE |
214 ( r300_translate_blend_factor(srcRGB) << R300_SRC_BLEND_SHIFT) |
215 ( r300_translate_blend_factor(dstRGB) << R300_DST_BLEND_SHIFT);
216 blend_control |=
217 r300_translate_blend_function(eqRGB, TRUE);
218 blend_control_noclamp |=
219 r300_translate_blend_function(eqRGB, FALSE);
220
221 /* Optimization: some operations do not require the destination color.
222 *
223 * When SRC_ALPHA_SATURATE is used, colorbuffer reads must be enabled,
224 * otherwise blending gives incorrect results. It seems to be
225 * a hardware bug. */
226 if (eqRGB == PIPE_BLEND_MIN || eqA == PIPE_BLEND_MIN ||
227 eqRGB == PIPE_BLEND_MAX || eqA == PIPE_BLEND_MAX ||
228 dstRGB != PIPE_BLENDFACTOR_ZERO ||
229 dstA != PIPE_BLENDFACTOR_ZERO ||
230 srcRGB == PIPE_BLENDFACTOR_DST_COLOR ||
231 srcRGB == PIPE_BLENDFACTOR_DST_ALPHA ||
232 srcRGB == PIPE_BLENDFACTOR_INV_DST_COLOR ||
233 srcRGB == PIPE_BLENDFACTOR_INV_DST_ALPHA ||
234 srcA == PIPE_BLENDFACTOR_DST_COLOR ||
235 srcA == PIPE_BLENDFACTOR_DST_ALPHA ||
236 srcA == PIPE_BLENDFACTOR_INV_DST_COLOR ||
237 srcA == PIPE_BLENDFACTOR_INV_DST_ALPHA ||
238 srcRGB == PIPE_BLENDFACTOR_SRC_ALPHA_SATURATE) {
239 /* Enable reading from the colorbuffer. */
240 blend_control |= R300_READ_ENABLE;
241 blend_control_noclamp |= R300_READ_ENABLE;
242
243 if (r300screen->caps.is_r500) {
244 /* Optimization: Depending on incoming pixels, we can
245 * conditionally disable the reading in hardware... */
246 if (eqRGB != PIPE_BLEND_MIN && eqA != PIPE_BLEND_MIN &&
247 eqRGB != PIPE_BLEND_MAX && eqA != PIPE_BLEND_MAX) {
248 /* Disable reading if SRC_ALPHA == 0. */
249 if ((dstRGB == PIPE_BLENDFACTOR_SRC_ALPHA ||
250 dstRGB == PIPE_BLENDFACTOR_ZERO) &&
251 (dstA == PIPE_BLENDFACTOR_SRC_COLOR ||
252 dstA == PIPE_BLENDFACTOR_SRC_ALPHA ||
253 dstA == PIPE_BLENDFACTOR_ZERO)) {
254 blend_control |= R500_SRC_ALPHA_0_NO_READ;
255 }
256
257 /* Disable reading if SRC_ALPHA == 1. */
258 if ((dstRGB == PIPE_BLENDFACTOR_INV_SRC_ALPHA ||
259 dstRGB == PIPE_BLENDFACTOR_ZERO) &&
260 (dstA == PIPE_BLENDFACTOR_INV_SRC_COLOR ||
261 dstA == PIPE_BLENDFACTOR_INV_SRC_ALPHA ||
262 dstA == PIPE_BLENDFACTOR_ZERO)) {
263 blend_control |= R500_SRC_ALPHA_1_NO_READ;
264 }
265 }
266 }
267 }
268
269 /* Optimization: discard pixels which don't change the colorbuffer.
270 *
271 * The code below is non-trivial and some math is involved.
272 *
273 * Discarding pixels must be disabled when FP16 AA is enabled.
274 * This is a hardware bug. Also, this implementation wouldn't work
275 * with FP blending enabled and equation clamping disabled.
276 *
277 * Equations other than ADD are rarely used and therefore won't be
278 * optimized. */
279 if ((eqRGB == PIPE_BLEND_ADD || eqRGB == PIPE_BLEND_REVERSE_SUBTRACT) &&
280 (eqA == PIPE_BLEND_ADD || eqA == PIPE_BLEND_REVERSE_SUBTRACT)) {
281 /* ADD: X+Y
282 * REVERSE_SUBTRACT: Y-X
283 *
284 * The idea is:
285 * If X = src*srcFactor = 0 and Y = dst*dstFactor = 1,
286 * then CB will not be changed.
287 *
288 * Given the srcFactor and dstFactor variables, we can derive
289 * what src and dst should be equal to and discard appropriate
290 * pixels.
291 */
292 if (blend_discard_if_src_alpha_0(srcRGB, srcA, dstRGB, dstA)) {
293 blend_control |= R300_DISCARD_SRC_PIXELS_SRC_ALPHA_0;
294 } else if (blend_discard_if_src_alpha_1(srcRGB, srcA,
295 dstRGB, dstA)) {
296 blend_control |= R300_DISCARD_SRC_PIXELS_SRC_ALPHA_1;
297 } else if (blend_discard_if_src_color_0(srcRGB, srcA,
298 dstRGB, dstA)) {
299 blend_control |= R300_DISCARD_SRC_PIXELS_SRC_COLOR_0;
300 } else if (blend_discard_if_src_color_1(srcRGB, srcA,
301 dstRGB, dstA)) {
302 blend_control |= R300_DISCARD_SRC_PIXELS_SRC_COLOR_1;
303 } else if (blend_discard_if_src_alpha_color_0(srcRGB, srcA,
304 dstRGB, dstA)) {
305 blend_control |=
306 R300_DISCARD_SRC_PIXELS_SRC_ALPHA_COLOR_0;
307 } else if (blend_discard_if_src_alpha_color_1(srcRGB, srcA,
308 dstRGB, dstA)) {
309 blend_control |=
310 R300_DISCARD_SRC_PIXELS_SRC_ALPHA_COLOR_1;
311 }
312 }
313
314 /* separate alpha */
315 if (srcA != srcRGB || dstA != dstRGB || eqA != eqRGB) {
316 blend_control |= R300_SEPARATE_ALPHA_ENABLE;
317 blend_control_noclamp |= R300_SEPARATE_ALPHA_ENABLE;
318 alpha_blend_control = alpha_blend_control_noclamp =
319 (r300_translate_blend_factor(srcA) << R300_SRC_BLEND_SHIFT) |
320 (r300_translate_blend_factor(dstA) << R300_DST_BLEND_SHIFT);
321 alpha_blend_control |=
322 r300_translate_blend_function(eqA, TRUE);
323 alpha_blend_control_noclamp |=
324 r300_translate_blend_function(eqA, FALSE);
325 }
326 }
327
328 /* PIPE_LOGICOP_* don't need to be translated, fortunately. */
329 if (state->logicop_enable) {
330 rop = R300_RB3D_ROPCNTL_ROP_ENABLE |
331 (state->logicop_func) << R300_RB3D_ROPCNTL_ROP_SHIFT;
332 }
333
334 /* Color channel masks for all MRTs. */
335 color_channel_mask = bgra_cmask(state->rt[0].colormask);
336 if (r300screen->caps.is_r500 && state->independent_blend_enable) {
337 if (state->rt[1].blend_enable) {
338 color_channel_mask |= bgra_cmask(state->rt[1].colormask) << 4;
339 }
340 if (state->rt[2].blend_enable) {
341 color_channel_mask |= bgra_cmask(state->rt[2].colormask) << 8;
342 }
343 if (state->rt[3].blend_enable) {
344 color_channel_mask |= bgra_cmask(state->rt[3].colormask) << 12;
345 }
346 }
347
348 /* Neither fglrx nor classic r300 ever set this, regardless of dithering
349 * state. Since it's an optional implementation detail, we can leave it
350 * out and never dither.
351 *
352 * This could be revisited if we ever get quality or conformance hints.
353 *
354 if (state->dither) {
355 dither = R300_RB3D_DITHER_CTL_DITHER_MODE_LUT |
356 R300_RB3D_DITHER_CTL_ALPHA_DITHER_MODE_LUT;
357 }
358 */
359
360 /* Build a command buffer. */
361 BEGIN_CB(blend->cb_clamp, 8);
362 OUT_CB_REG(R300_RB3D_ROPCNTL, rop);
363 OUT_CB_REG_SEQ(R300_RB3D_CBLEND, 3);
364 OUT_CB(blend_control);
365 OUT_CB(alpha_blend_control);
366 OUT_CB(color_channel_mask);
367 OUT_CB_REG(R300_RB3D_DITHER_CTL, dither);
368 END_CB;
369
370 /* Build a command buffer. */
371 BEGIN_CB(blend->cb_noclamp, 8);
372 OUT_CB_REG(R300_RB3D_ROPCNTL, rop);
373 OUT_CB_REG_SEQ(R300_RB3D_CBLEND, 3);
374 OUT_CB(blend_control_noclamp);
375 OUT_CB(alpha_blend_control_noclamp);
376 OUT_CB(color_channel_mask);
377 OUT_CB_REG(R300_RB3D_DITHER_CTL, dither);
378 END_CB;
379
380 /* The same as above, but with no colorbuffer reads and writes. */
381 BEGIN_CB(blend->cb_no_readwrite, 8);
382 OUT_CB_REG(R300_RB3D_ROPCNTL, rop);
383 OUT_CB_REG_SEQ(R300_RB3D_CBLEND, 3);
384 OUT_CB(0);
385 OUT_CB(0);
386 OUT_CB(0);
387 OUT_CB_REG(R300_RB3D_DITHER_CTL, dither);
388 END_CB;
389
390 return (void*)blend;
391 }
392
393 /* Bind blend state. */
394 static void r300_bind_blend_state(struct pipe_context* pipe,
395 void* state)
396 {
397 struct r300_context* r300 = r300_context(pipe);
398
399 UPDATE_STATE(state, r300->blend_state);
400 }
401
402 /* Free blend state. */
403 static void r300_delete_blend_state(struct pipe_context* pipe,
404 void* state)
405 {
406 FREE(state);
407 }
408
409 /* Convert float to 10bit integer */
410 static unsigned float_to_fixed10(float f)
411 {
412 return CLAMP((unsigned)(f * 1023.9f), 0, 1023);
413 }
414
415 /* Set blend color.
416 * Setup both R300 and R500 registers, figure out later which one to write. */
417 static void r300_set_blend_color(struct pipe_context* pipe,
418 const struct pipe_blend_color* color)
419 {
420 struct r300_context* r300 = r300_context(pipe);
421 struct pipe_framebuffer_state *fb = r300->fb_state.state;
422 struct r300_blend_color_state *state =
423 (struct r300_blend_color_state*)r300->blend_color_state.state;
424 struct pipe_blend_color c;
425 enum pipe_format format = fb->nr_cbufs ? fb->cbufs[0]->format : 0;
426 CB_LOCALS;
427
428 state->state = *color; /* Save it, so that we can reuse it in set_fb_state */
429 c = *color;
430
431 /* The blend color is dependent on the colorbuffer format. */
432 if (fb->nr_cbufs) {
433 switch (format) {
434 case PIPE_FORMAT_R8_UNORM:
435 case PIPE_FORMAT_L8_UNORM:
436 case PIPE_FORMAT_I8_UNORM:
437 c.color[1] = c.color[0];
438 break;
439
440 case PIPE_FORMAT_A8_UNORM:
441 c.color[1] = c.color[3];
442 break;
443
444 case PIPE_FORMAT_R8G8_UNORM:
445 c.color[2] = c.color[1];
446 break;
447
448 case PIPE_FORMAT_L8A8_UNORM:
449 c.color[2] = c.color[3];
450 break;
451
452 default:;
453 }
454 }
455
456 if (r300->screen->caps.is_r500) {
457 BEGIN_CB(state->cb, 3);
458 OUT_CB_REG_SEQ(R500_RB3D_CONSTANT_COLOR_AR, 2);
459
460 switch (format) {
461 case PIPE_FORMAT_R16G16B16A16_FLOAT:
462 OUT_CB(util_float_to_half(c.color[2]) |
463 (util_float_to_half(c.color[3]) << 16));
464 OUT_CB(util_float_to_half(c.color[0]) |
465 (util_float_to_half(c.color[1]) << 16));
466 break;
467
468 default:
469 OUT_CB(float_to_fixed10(c.color[0]) |
470 (float_to_fixed10(c.color[3]) << 16));
471 OUT_CB(float_to_fixed10(c.color[2]) |
472 (float_to_fixed10(c.color[1]) << 16));
473 }
474
475 END_CB;
476 } else {
477 union util_color uc;
478 util_pack_color(c.color, PIPE_FORMAT_B8G8R8A8_UNORM, &uc);
479
480 BEGIN_CB(state->cb, 2);
481 OUT_CB_REG(R300_RB3D_BLEND_COLOR, uc.ui);
482 END_CB;
483 }
484
485 r300_mark_atom_dirty(r300, &r300->blend_color_state);
486 }
487
488 static void r300_set_clip_state(struct pipe_context* pipe,
489 const struct pipe_clip_state* state)
490 {
491 struct r300_context* r300 = r300_context(pipe);
492 struct r300_clip_state *clip =
493 (struct r300_clip_state*)r300->clip_state.state;
494 CB_LOCALS;
495
496 clip->clip = *state;
497
498 if (r300->screen->caps.has_tcl) {
499 r300->clip_state.size = 2 + !!state->nr * 3 + state->nr * 4;
500
501 BEGIN_CB(clip->cb, r300->clip_state.size);
502 if (state->nr) {
503 OUT_CB_REG(R300_VAP_PVS_VECTOR_INDX_REG,
504 (r300->screen->caps.is_r500 ?
505 R500_PVS_UCP_START : R300_PVS_UCP_START));
506 OUT_CB_ONE_REG(R300_VAP_PVS_UPLOAD_DATA, state->nr * 4);
507 OUT_CB_TABLE(state->ucp, state->nr * 4);
508 }
509 OUT_CB_REG(R300_VAP_CLIP_CNTL, ((1 << state->nr) - 1) |
510 R300_PS_UCP_MODE_CLIP_AS_TRIFAN);
511 END_CB;
512
513 r300_mark_atom_dirty(r300, &r300->clip_state);
514 } else {
515 draw_set_clip_state(r300->draw, state);
516 }
517 }
518
519 static void
520 r300_set_sample_mask(struct pipe_context *pipe,
521 unsigned sample_mask)
522 {
523 }
524
525
526 /* Create a new depth, stencil, and alpha state based on the CSO dsa state.
527 *
528 * This contains the depth buffer, stencil buffer, alpha test, and such.
529 * On the Radeon, depth and stencil buffer setup are intertwined, which is
530 * the reason for some of the strange-looking assignments across registers. */
531 static void*
532 r300_create_dsa_state(struct pipe_context* pipe,
533 const struct pipe_depth_stencil_alpha_state* state)
534 {
535 struct r300_capabilities *caps = &r300_screen(pipe->screen)->caps;
536 struct r300_dsa_state* dsa = CALLOC_STRUCT(r300_dsa_state);
537 CB_LOCALS;
538
539 dsa->dsa = *state;
540
541 /* Depth test setup. - separate write mask depth for decomp flush */
542 if (state->depth.writemask) {
543 dsa->z_buffer_control |= R300_Z_WRITE_ENABLE;
544 }
545
546 if (state->depth.enabled) {
547 dsa->z_buffer_control |= R300_Z_ENABLE;
548
549 dsa->z_stencil_control |=
550 (r300_translate_depth_stencil_function(state->depth.func) <<
551 R300_Z_FUNC_SHIFT);
552 }
553
554 /* Stencil buffer setup. */
555 if (state->stencil[0].enabled) {
556 dsa->z_buffer_control |= R300_STENCIL_ENABLE;
557 dsa->z_stencil_control |=
558 (r300_translate_depth_stencil_function(state->stencil[0].func) <<
559 R300_S_FRONT_FUNC_SHIFT) |
560 (r300_translate_stencil_op(state->stencil[0].fail_op) <<
561 R300_S_FRONT_SFAIL_OP_SHIFT) |
562 (r300_translate_stencil_op(state->stencil[0].zpass_op) <<
563 R300_S_FRONT_ZPASS_OP_SHIFT) |
564 (r300_translate_stencil_op(state->stencil[0].zfail_op) <<
565 R300_S_FRONT_ZFAIL_OP_SHIFT);
566
567 dsa->stencil_ref_mask =
568 (state->stencil[0].valuemask << R300_STENCILMASK_SHIFT) |
569 (state->stencil[0].writemask << R300_STENCILWRITEMASK_SHIFT);
570
571 if (state->stencil[1].enabled) {
572 dsa->two_sided = TRUE;
573
574 dsa->z_buffer_control |= R300_STENCIL_FRONT_BACK;
575 dsa->z_stencil_control |=
576 (r300_translate_depth_stencil_function(state->stencil[1].func) <<
577 R300_S_BACK_FUNC_SHIFT) |
578 (r300_translate_stencil_op(state->stencil[1].fail_op) <<
579 R300_S_BACK_SFAIL_OP_SHIFT) |
580 (r300_translate_stencil_op(state->stencil[1].zpass_op) <<
581 R300_S_BACK_ZPASS_OP_SHIFT) |
582 (r300_translate_stencil_op(state->stencil[1].zfail_op) <<
583 R300_S_BACK_ZFAIL_OP_SHIFT);
584
585 dsa->stencil_ref_bf =
586 (state->stencil[1].valuemask << R300_STENCILMASK_SHIFT) |
587 (state->stencil[1].writemask << R300_STENCILWRITEMASK_SHIFT);
588
589 if (caps->is_r500) {
590 dsa->z_buffer_control |= R500_STENCIL_REFMASK_FRONT_BACK;
591 } else {
592 dsa->two_sided_stencil_ref =
593 (state->stencil[0].valuemask != state->stencil[1].valuemask ||
594 state->stencil[0].writemask != state->stencil[1].writemask);
595 }
596 }
597 }
598
599 /* Alpha test setup. */
600 if (state->alpha.enabled) {
601 dsa->alpha_function =
602 r300_translate_alpha_function(state->alpha.func) |
603 R300_FG_ALPHA_FUNC_ENABLE;
604
605 dsa->alpha_function |= float_to_ubyte(state->alpha.ref_value);
606 dsa->alpha_value = util_float_to_half(state->alpha.ref_value);
607
608 if (caps->is_r500) {
609 dsa->alpha_function_fp16 = dsa->alpha_function |
610 R500_FG_ALPHA_FUNC_FP16_ENABLE;
611 dsa->alpha_function |= R500_FG_ALPHA_FUNC_8BIT;
612 }
613 }
614
615 BEGIN_CB(&dsa->cb_begin, 10);
616 OUT_CB_REG(R300_FG_ALPHA_FUNC, dsa->alpha_function);
617 OUT_CB_REG_SEQ(R300_ZB_CNTL, 3);
618 OUT_CB(dsa->z_buffer_control);
619 OUT_CB(dsa->z_stencil_control);
620 OUT_CB(dsa->stencil_ref_mask);
621 OUT_CB_REG(R500_ZB_STENCILREFMASK_BF, dsa->stencil_ref_bf);
622 OUT_CB_REG(R500_FG_ALPHA_VALUE, dsa->alpha_value);
623 END_CB;
624
625 BEGIN_CB(&dsa->cb_begin_fp16, 10);
626 OUT_CB_REG(R300_FG_ALPHA_FUNC, dsa->alpha_function_fp16);
627 OUT_CB_REG_SEQ(R300_ZB_CNTL, 3);
628 OUT_CB(dsa->z_buffer_control);
629 OUT_CB(dsa->z_stencil_control);
630 OUT_CB(dsa->stencil_ref_mask);
631 OUT_CB_REG(R500_ZB_STENCILREFMASK_BF, dsa->stencil_ref_bf);
632 OUT_CB_REG(R500_FG_ALPHA_VALUE, dsa->alpha_value);
633 END_CB;
634
635 BEGIN_CB(dsa->cb_zb_no_readwrite, 10);
636 OUT_CB_REG(R300_FG_ALPHA_FUNC, dsa->alpha_function);
637 OUT_CB_REG_SEQ(R300_ZB_CNTL, 3);
638 OUT_CB(0);
639 OUT_CB(0);
640 OUT_CB(0);
641 OUT_CB_REG(R500_ZB_STENCILREFMASK_BF, 0);
642 OUT_CB_REG(R500_FG_ALPHA_VALUE, dsa->alpha_value);
643 END_CB;
644
645 BEGIN_CB(dsa->cb_fp16_zb_no_readwrite, 10);
646 OUT_CB_REG(R300_FG_ALPHA_FUNC, dsa->alpha_function_fp16);
647 OUT_CB_REG_SEQ(R300_ZB_CNTL, 3);
648 OUT_CB(0);
649 OUT_CB(0);
650 OUT_CB(0);
651 OUT_CB_REG(R500_ZB_STENCILREFMASK_BF, 0);
652 OUT_CB_REG(R500_FG_ALPHA_VALUE, dsa->alpha_value);
653 END_CB;
654
655 return (void*)dsa;
656 }
657
658 static void r300_dsa_inject_stencilref(struct r300_context *r300)
659 {
660 struct r300_dsa_state *dsa =
661 (struct r300_dsa_state*)r300->dsa_state.state;
662
663 if (!dsa)
664 return;
665
666 dsa->stencil_ref_mask =
667 (dsa->stencil_ref_mask & ~R300_STENCILREF_MASK) |
668 r300->stencil_ref.ref_value[0];
669 dsa->stencil_ref_bf =
670 (dsa->stencil_ref_bf & ~R300_STENCILREF_MASK) |
671 r300->stencil_ref.ref_value[1];
672 }
673
674 /* Bind DSA state. */
675 static void r300_bind_dsa_state(struct pipe_context* pipe,
676 void* state)
677 {
678 struct r300_context* r300 = r300_context(pipe);
679
680 if (!state) {
681 return;
682 }
683
684 UPDATE_STATE(state, r300->dsa_state);
685
686 r300_mark_atom_dirty(r300, &r300->hyperz_state); /* Will be updated before the emission. */
687 r300_dsa_inject_stencilref(r300);
688 }
689
690 /* Free DSA state. */
691 static void r300_delete_dsa_state(struct pipe_context* pipe,
692 void* state)
693 {
694 FREE(state);
695 }
696
697 static void r300_set_stencil_ref(struct pipe_context* pipe,
698 const struct pipe_stencil_ref* sr)
699 {
700 struct r300_context* r300 = r300_context(pipe);
701
702 r300->stencil_ref = *sr;
703
704 r300_dsa_inject_stencilref(r300);
705 r300_mark_atom_dirty(r300, &r300->dsa_state);
706 }
707
708 static void r300_tex_set_tiling_flags(struct r300_context *r300,
709 struct r300_resource *tex,
710 unsigned level)
711 {
712 /* Check if the macrotile flag needs to be changed.
713 * Skip changing the flags otherwise. */
714 if (tex->tex.macrotile[tex->surface_level] !=
715 tex->tex.macrotile[level]) {
716 r300->rws->buffer_set_tiling(tex->buf, r300->cs,
717 tex->tex.microtile, tex->tex.macrotile[level],
718 tex->tex.stride_in_bytes[0]);
719
720 tex->surface_level = level;
721 }
722 }
723
724 /* This switcheroo is needed just because of goddamned MACRO_SWITCH. */
725 static void r300_fb_set_tiling_flags(struct r300_context *r300,
726 const struct pipe_framebuffer_state *state)
727 {
728 unsigned i;
729
730 /* Set tiling flags for new surfaces. */
731 for (i = 0; i < state->nr_cbufs; i++) {
732 r300_tex_set_tiling_flags(r300,
733 r300_resource(state->cbufs[i]->texture),
734 state->cbufs[i]->u.tex.level);
735 }
736 if (state->zsbuf) {
737 r300_tex_set_tiling_flags(r300,
738 r300_resource(state->zsbuf->texture),
739 state->zsbuf->u.tex.level);
740 }
741 }
742
743 static void r300_print_fb_surf_info(struct pipe_surface *surf, unsigned index,
744 const char *binding)
745 {
746 struct pipe_resource *tex = surf->texture;
747 struct r300_resource *rtex = r300_resource(tex);
748
749 fprintf(stderr,
750 "r300: %s[%i] Dim: %ix%i, Firstlayer: %i, "
751 "Lastlayer: %i, Level: %i, Format: %s\n"
752
753 "r300: TEX: Macro: %s, Micro: %s, Pitch: %i, "
754 "Dim: %ix%ix%i, LastLevel: %i, Format: %s\n",
755
756 binding, index, surf->width, surf->height,
757 surf->u.tex.first_layer, surf->u.tex.last_layer, surf->u.tex.level,
758 util_format_short_name(surf->format),
759
760 rtex->tex.macrotile[0] ? "YES" : " NO",
761 rtex->tex.microtile ? "YES" : " NO",
762 rtex->tex.stride_in_pixels[0],
763 tex->width0, tex->height0, tex->depth0,
764 tex->last_level, util_format_short_name(tex->format));
765 }
766
767 void r300_mark_fb_state_dirty(struct r300_context *r300,
768 enum r300_fb_state_change change)
769 {
770 struct pipe_framebuffer_state *state = r300->fb_state.state;
771
772 r300_mark_atom_dirty(r300, &r300->gpu_flush);
773 r300_mark_atom_dirty(r300, &r300->fb_state);
774
775 /* What is marked as dirty depends on the enum r300_fb_state_change. */
776 if (change == R300_CHANGED_FB_STATE) {
777 r300_mark_atom_dirty(r300, &r300->aa_state);
778 r300_mark_atom_dirty(r300, &r300->dsa_state); /* for AlphaRef */
779 r300_set_blend_color(&r300->context, r300->blend_color_state.state);
780 }
781
782 if (change == R300_CHANGED_FB_STATE ||
783 change == R300_CHANGED_HYPERZ_FLAG) {
784 r300_mark_atom_dirty(r300, &r300->hyperz_state);
785 }
786
787 if (change == R300_CHANGED_FB_STATE ||
788 change == R300_CHANGED_MULTIWRITE) {
789 r300_mark_atom_dirty(r300, &r300->fb_state_pipelined);
790 }
791
792 /* Now compute the fb_state atom size. */
793 r300->fb_state.size = 2 + (8 * state->nr_cbufs);
794
795 if (r300->cbzb_clear)
796 r300->fb_state.size += 10;
797 else if (state->zsbuf) {
798 r300->fb_state.size += 10;
799 if (r300->hyperz_enabled)
800 r300->fb_state.size += 8;
801 }
802
803 /* The size of the rest of atoms stays the same. */
804 }
805
806 static void
807 r300_set_framebuffer_state(struct pipe_context* pipe,
808 const struct pipe_framebuffer_state* state)
809 {
810 struct r300_context* r300 = r300_context(pipe);
811 struct r300_aa_state *aa = (struct r300_aa_state*)r300->aa_state.state;
812 struct pipe_framebuffer_state *old_state = r300->fb_state.state;
813 unsigned max_width, max_height, i;
814 uint32_t zbuffer_bpp = 0;
815 boolean unlock_zbuffer = FALSE;
816
817 if (r300->screen->caps.is_r500) {
818 max_width = max_height = 4096;
819 } else if (r300->screen->caps.is_r400) {
820 max_width = max_height = 4021;
821 } else {
822 max_width = max_height = 2560;
823 }
824
825 if (state->width > max_width || state->height > max_height) {
826 fprintf(stderr, "r300: Implementation error: Render targets are too "
827 "big in %s, refusing to bind framebuffer state!\n", __FUNCTION__);
828 return;
829 }
830
831 if (old_state->zsbuf && r300->zmask_in_use && !r300->locked_zbuffer) {
832 /* There is a zmask in use, what are we gonna do? */
833 if (state->zsbuf) {
834 if (!pipe_surface_equal(old_state->zsbuf, state->zsbuf)) {
835 /* Decompress the currently bound zbuffer before we bind another one. */
836 r300_decompress_zmask(r300);
837 r300->hiz_in_use = FALSE;
838 }
839 } else {
840 /* We don't bind another zbuffer, so lock the current one. */
841 pipe_surface_reference(&r300->locked_zbuffer, old_state->zsbuf);
842 }
843 } else if (r300->locked_zbuffer) {
844 /* We have a locked zbuffer now, what are we gonna do? */
845 if (state->zsbuf) {
846 if (!pipe_surface_equal(r300->locked_zbuffer, state->zsbuf)) {
847 /* We are binding some other zbuffer, so decompress the locked one,
848 * it gets unlocked automatically. */
849 r300_decompress_zmask_locked_unsafe(r300);
850 r300->hiz_in_use = FALSE;
851 } else {
852 /* We are binding the locked zbuffer again, so unlock it. */
853 unlock_zbuffer = TRUE;
854 }
855 }
856 }
857 assert(state->zsbuf || (r300->locked_zbuffer && !unlock_zbuffer) || !r300->zmask_in_use);
858
859 /* Need to reset clamping or colormask. */
860 r300_mark_atom_dirty(r300, &r300->blend_state);
861
862 /* If zsbuf is set from NULL to non-NULL or vice versa.. */
863 if (!!old_state->zsbuf != !!state->zsbuf) {
864 r300_mark_atom_dirty(r300, &r300->dsa_state);
865 }
866
867 /* The tiling flags are dependent on the surface miplevel, unfortunately. */
868 r300_fb_set_tiling_flags(r300, state);
869
870 util_copy_framebuffer_state(r300->fb_state.state, state);
871
872 if (unlock_zbuffer) {
873 pipe_surface_reference(&r300->locked_zbuffer, NULL);
874 }
875
876 r300_mark_fb_state_dirty(r300, R300_CHANGED_FB_STATE);
877
878 if (state->zsbuf) {
879 switch (util_format_get_blocksize(state->zsbuf->texture->format)) {
880 case 2:
881 zbuffer_bpp = 16;
882 break;
883 case 4:
884 zbuffer_bpp = 24;
885 break;
886 }
887
888 /* Polygon offset depends on the zbuffer bit depth. */
889 if (r300->zbuffer_bpp != zbuffer_bpp) {
890 r300->zbuffer_bpp = zbuffer_bpp;
891
892 if (r300->polygon_offset_enabled)
893 r300_mark_atom_dirty(r300, &r300->rs_state);
894 }
895 }
896
897 /* Set up AA config. */
898 if (state->nr_cbufs && state->cbufs[0]->texture->nr_samples > 1) {
899 aa->aa_config = R300_GB_AA_CONFIG_AA_ENABLE;
900
901 switch (state->cbufs[0]->texture->nr_samples) {
902 case 2:
903 aa->aa_config |= R300_GB_AA_CONFIG_NUM_AA_SUBSAMPLES_2;
904 break;
905 case 3:
906 aa->aa_config |= R300_GB_AA_CONFIG_NUM_AA_SUBSAMPLES_3;
907 break;
908 case 4:
909 aa->aa_config |= R300_GB_AA_CONFIG_NUM_AA_SUBSAMPLES_4;
910 break;
911 case 6:
912 aa->aa_config |= R300_GB_AA_CONFIG_NUM_AA_SUBSAMPLES_6;
913 break;
914 }
915 } else {
916 aa->aa_config = 0;
917 }
918
919 if (DBG_ON(r300, DBG_FB)) {
920 fprintf(stderr, "r300: set_framebuffer_state:\n");
921 for (i = 0; i < state->nr_cbufs; i++) {
922 r300_print_fb_surf_info(state->cbufs[i], i, "CB");
923 }
924 if (state->zsbuf) {
925 r300_print_fb_surf_info(state->zsbuf, 0, "ZB");
926 }
927 }
928 }
929
930 /* Create fragment shader state. */
931 static void* r300_create_fs_state(struct pipe_context* pipe,
932 const struct pipe_shader_state* shader)
933 {
934 struct r300_fragment_shader* fs = NULL;
935
936 fs = (struct r300_fragment_shader*)CALLOC_STRUCT(r300_fragment_shader);
937
938 /* Copy state directly into shader. */
939 fs->state = *shader;
940 fs->state.tokens = tgsi_dup_tokens(shader->tokens);
941
942 return (void*)fs;
943 }
944
945 void r300_mark_fs_code_dirty(struct r300_context *r300)
946 {
947 struct r300_fragment_shader* fs = r300_fs(r300);
948
949 r300_mark_atom_dirty(r300, &r300->fs);
950 r300_mark_atom_dirty(r300, &r300->fs_rc_constant_state);
951 r300_mark_atom_dirty(r300, &r300->fs_constants);
952 r300->fs.size = fs->shader->cb_code_size;
953
954 if (r300->screen->caps.is_r500) {
955 r300->fs_rc_constant_state.size = fs->shader->rc_state_count * 7;
956 r300->fs_constants.size = fs->shader->externals_count * 4 + 3;
957 } else {
958 r300->fs_rc_constant_state.size = fs->shader->rc_state_count * 5;
959 r300->fs_constants.size = fs->shader->externals_count * 4 + 1;
960 }
961
962 ((struct r300_constant_buffer*)r300->fs_constants.state)->remap_table =
963 fs->shader->code.constants_remap_table;
964 }
965
966 /* Bind fragment shader state. */
967 static void r300_bind_fs_state(struct pipe_context* pipe, void* shader)
968 {
969 struct r300_context* r300 = r300_context(pipe);
970 struct r300_fragment_shader* fs = (struct r300_fragment_shader*)shader;
971
972 if (fs == NULL) {
973 r300->fs.state = NULL;
974 return;
975 }
976
977 r300->fs.state = fs;
978 r300->fs_status = FRAGMENT_SHADER_DIRTY;
979
980 r300_mark_atom_dirty(r300, &r300->rs_block_state); /* Will be updated before the emission. */
981 }
982
983 /* Delete fragment shader state. */
984 static void r300_delete_fs_state(struct pipe_context* pipe, void* shader)
985 {
986 struct r300_fragment_shader* fs = (struct r300_fragment_shader*)shader;
987 struct r300_fragment_shader_code *tmp, *ptr = fs->first;
988
989 while (ptr) {
990 tmp = ptr;
991 ptr = ptr->next;
992 rc_constants_destroy(&tmp->code.constants);
993 FREE(tmp->cb_code);
994 FREE(tmp);
995 }
996 FREE((void*)fs->state.tokens);
997 FREE(shader);
998 }
999
1000 static void r300_set_polygon_stipple(struct pipe_context* pipe,
1001 const struct pipe_poly_stipple* state)
1002 {
1003 /* XXX no idea how to set this up, but not terribly important */
1004 }
1005
1006 /* Create a new rasterizer state based on the CSO rasterizer state.
1007 *
1008 * This is a very large chunk of state, and covers most of the graphics
1009 * backend (GB), geometry assembly (GA), and setup unit (SU) blocks.
1010 *
1011 * In a not entirely unironic sidenote, this state has nearly nothing to do
1012 * with the actual block on the Radeon called the rasterizer (RS). */
1013 static void* r300_create_rs_state(struct pipe_context* pipe,
1014 const struct pipe_rasterizer_state* state)
1015 {
1016 struct r300_rs_state* rs = CALLOC_STRUCT(r300_rs_state);
1017 float psiz;
1018 uint32_t vap_control_status; /* R300_VAP_CNTL_STATUS: 0x2140 */
1019 uint32_t point_size; /* R300_GA_POINT_SIZE: 0x421c */
1020 uint32_t point_minmax; /* R300_GA_POINT_MINMAX: 0x4230 */
1021 uint32_t line_control; /* R300_GA_LINE_CNTL: 0x4234 */
1022 uint32_t polygon_offset_enable; /* R300_SU_POLY_OFFSET_ENABLE: 0x42b4 */
1023 uint32_t cull_mode; /* R300_SU_CULL_MODE: 0x42b8 */
1024 uint32_t line_stipple_config; /* R300_GA_LINE_STIPPLE_CONFIG: 0x4328 */
1025 uint32_t line_stipple_value; /* R300_GA_LINE_STIPPLE_VALUE: 0x4260 */
1026 uint32_t polygon_mode; /* R300_GA_POLY_MODE: 0x4288 */
1027 uint32_t clip_rule; /* R300_SC_CLIP_RULE: 0x43D0 */
1028 uint32_t round_mode; /* R300_GA_ROUND_MODE: 0x428c */
1029
1030 /* Point sprites texture coordinates, 0: lower left, 1: upper right */
1031 float point_texcoord_left = 0; /* R300_GA_POINT_S0: 0x4200 */
1032 float point_texcoord_bottom = 0;/* R300_GA_POINT_T0: 0x4204 */
1033 float point_texcoord_right = 1; /* R300_GA_POINT_S1: 0x4208 */
1034 float point_texcoord_top = 0; /* R300_GA_POINT_T1: 0x420c */
1035 boolean vclamp = state->clamp_vertex_color;
1036 CB_LOCALS;
1037
1038 /* Copy rasterizer state. */
1039 rs->rs = *state;
1040 rs->rs_draw = *state;
1041
1042 rs->rs.sprite_coord_enable = state->point_quad_rasterization *
1043 state->sprite_coord_enable;
1044
1045 /* Override some states for Draw. */
1046 rs->rs_draw.sprite_coord_enable = 0; /* We can do this in HW. */
1047
1048 #ifdef PIPE_ARCH_LITTLE_ENDIAN
1049 vap_control_status = R300_VC_NO_SWAP;
1050 #else
1051 vap_control_status = R300_VC_32BIT_SWAP;
1052 #endif
1053
1054 /* If no TCL engine is present, turn off the HW TCL. */
1055 if (!r300_screen(pipe->screen)->caps.has_tcl) {
1056 vap_control_status |= R300_VAP_TCL_BYPASS;
1057 }
1058
1059 /* Point size width and height. */
1060 point_size =
1061 pack_float_16_6x(state->point_size) |
1062 (pack_float_16_6x(state->point_size) << R300_POINTSIZE_X_SHIFT);
1063
1064 /* Point size clamping. */
1065 if (state->point_size_per_vertex) {
1066 /* Per-vertex point size.
1067 * Clamp to [0, max FB size] */
1068 psiz = pipe->screen->get_paramf(pipe->screen,
1069 PIPE_CAP_MAX_POINT_WIDTH);
1070 point_minmax =
1071 pack_float_16_6x(psiz) << R300_GA_POINT_MINMAX_MAX_SHIFT;
1072 } else {
1073 /* We cannot disable the point-size vertex output,
1074 * so clamp it. */
1075 psiz = state->point_size;
1076 point_minmax =
1077 (pack_float_16_6x(psiz) << R300_GA_POINT_MINMAX_MIN_SHIFT) |
1078 (pack_float_16_6x(psiz) << R300_GA_POINT_MINMAX_MAX_SHIFT);
1079 }
1080
1081 /* Line control. */
1082 line_control = pack_float_16_6x(state->line_width) |
1083 R300_GA_LINE_CNTL_END_TYPE_COMP;
1084
1085 /* Enable polygon mode */
1086 polygon_mode = 0;
1087 if (state->fill_front != PIPE_POLYGON_MODE_FILL ||
1088 state->fill_back != PIPE_POLYGON_MODE_FILL) {
1089 polygon_mode = R300_GA_POLY_MODE_DUAL;
1090 }
1091
1092 /* Front face */
1093 if (state->front_ccw)
1094 cull_mode = R300_FRONT_FACE_CCW;
1095 else
1096 cull_mode = R300_FRONT_FACE_CW;
1097
1098 /* Polygon offset */
1099 polygon_offset_enable = 0;
1100 if (util_get_offset(state, state->fill_front)) {
1101 polygon_offset_enable |= R300_FRONT_ENABLE;
1102 }
1103 if (util_get_offset(state, state->fill_back)) {
1104 polygon_offset_enable |= R300_BACK_ENABLE;
1105 }
1106
1107 rs->polygon_offset_enable = polygon_offset_enable != 0;
1108
1109 /* Polygon mode */
1110 if (polygon_mode) {
1111 polygon_mode |=
1112 r300_translate_polygon_mode_front(state->fill_front);
1113 polygon_mode |=
1114 r300_translate_polygon_mode_back(state->fill_back);
1115 }
1116
1117 if (state->cull_face & PIPE_FACE_FRONT) {
1118 cull_mode |= R300_CULL_FRONT;
1119 }
1120 if (state->cull_face & PIPE_FACE_BACK) {
1121 cull_mode |= R300_CULL_BACK;
1122 }
1123
1124 if (state->line_stipple_enable) {
1125 line_stipple_config =
1126 R300_GA_LINE_STIPPLE_CONFIG_LINE_RESET_LINE |
1127 (fui((float)state->line_stipple_factor) &
1128 R300_GA_LINE_STIPPLE_CONFIG_STIPPLE_SCALE_MASK);
1129 /* XXX this might need to be scaled up */
1130 line_stipple_value = state->line_stipple_pattern;
1131 } else {
1132 line_stipple_config = 0;
1133 line_stipple_value = 0;
1134 }
1135
1136 if (state->flatshade) {
1137 rs->color_control = R300_SHADE_MODEL_FLAT;
1138 } else {
1139 rs->color_control = R300_SHADE_MODEL_SMOOTH;
1140 }
1141
1142 clip_rule = state->scissor ? 0xAAAA : 0xFFFF;
1143
1144 /* Point sprites coord mode */
1145 if (rs->rs.sprite_coord_enable) {
1146 switch (state->sprite_coord_mode) {
1147 case PIPE_SPRITE_COORD_UPPER_LEFT:
1148 point_texcoord_top = 0.0f;
1149 point_texcoord_bottom = 1.0f;
1150 break;
1151 case PIPE_SPRITE_COORD_LOWER_LEFT:
1152 point_texcoord_top = 1.0f;
1153 point_texcoord_bottom = 0.0f;
1154 break;
1155 }
1156 }
1157
1158 /* Vertex color clamping. FP20 means no clamping. */
1159 round_mode =
1160 R300_GA_ROUND_MODE_GEOMETRY_ROUND_NEAREST |
1161 (!vclamp ? (R300_GA_ROUND_MODE_RGB_CLAMP_FP20 |
1162 R300_GA_ROUND_MODE_ALPHA_CLAMP_FP20) : 0);
1163
1164 /* Build the main command buffer. */
1165 BEGIN_CB(rs->cb_main, RS_STATE_MAIN_SIZE);
1166 OUT_CB_REG(R300_VAP_CNTL_STATUS, vap_control_status);
1167 OUT_CB_REG(R300_GA_POINT_SIZE, point_size);
1168 OUT_CB_REG_SEQ(R300_GA_POINT_MINMAX, 2);
1169 OUT_CB(point_minmax);
1170 OUT_CB(line_control);
1171 OUT_CB_REG_SEQ(R300_SU_POLY_OFFSET_ENABLE, 2);
1172 OUT_CB(polygon_offset_enable);
1173 rs->cull_mode_index = 9;
1174 OUT_CB(cull_mode);
1175 OUT_CB_REG(R300_GA_LINE_STIPPLE_CONFIG, line_stipple_config);
1176 OUT_CB_REG(R300_GA_LINE_STIPPLE_VALUE, line_stipple_value);
1177 OUT_CB_REG(R300_GA_POLY_MODE, polygon_mode);
1178 OUT_CB_REG(R300_GA_ROUND_MODE, round_mode);
1179 OUT_CB_REG(R300_SC_CLIP_RULE, clip_rule);
1180 OUT_CB_REG_SEQ(R300_GA_POINT_S0, 4);
1181 OUT_CB_32F(point_texcoord_left);
1182 OUT_CB_32F(point_texcoord_bottom);
1183 OUT_CB_32F(point_texcoord_right);
1184 OUT_CB_32F(point_texcoord_top);
1185 END_CB;
1186
1187 /* Build the two command buffers for polygon offset setup. */
1188 if (polygon_offset_enable) {
1189 float scale = state->offset_scale * 12;
1190 float offset = state->offset_units * 4;
1191
1192 BEGIN_CB(rs->cb_poly_offset_zb16, 5);
1193 OUT_CB_REG_SEQ(R300_SU_POLY_OFFSET_FRONT_SCALE, 4);
1194 OUT_CB_32F(scale);
1195 OUT_CB_32F(offset);
1196 OUT_CB_32F(scale);
1197 OUT_CB_32F(offset);
1198 END_CB;
1199
1200 offset = state->offset_units * 2;
1201
1202 BEGIN_CB(rs->cb_poly_offset_zb24, 5);
1203 OUT_CB_REG_SEQ(R300_SU_POLY_OFFSET_FRONT_SCALE, 4);
1204 OUT_CB_32F(scale);
1205 OUT_CB_32F(offset);
1206 OUT_CB_32F(scale);
1207 OUT_CB_32F(offset);
1208 END_CB;
1209 }
1210
1211 return (void*)rs;
1212 }
1213
1214 /* Bind rasterizer state. */
1215 static void r300_bind_rs_state(struct pipe_context* pipe, void* state)
1216 {
1217 struct r300_context* r300 = r300_context(pipe);
1218 struct r300_rs_state* rs = (struct r300_rs_state*)state;
1219 int last_sprite_coord_enable = r300->sprite_coord_enable;
1220 boolean last_two_sided_color = r300->two_sided_color;
1221 boolean last_frag_clamp = r300->frag_clamp;
1222
1223 if (r300->draw && rs) {
1224 draw_set_rasterizer_state(r300->draw, &rs->rs_draw, state);
1225 }
1226
1227 if (rs) {
1228 r300->polygon_offset_enabled = rs->polygon_offset_enable;
1229 r300->sprite_coord_enable = rs->rs.sprite_coord_enable;
1230 r300->two_sided_color = rs->rs.light_twoside;
1231 r300->frag_clamp = rs->rs.clamp_fragment_color;
1232 } else {
1233 r300->polygon_offset_enabled = FALSE;
1234 r300->sprite_coord_enable = 0;
1235 r300->two_sided_color = FALSE;
1236 r300->frag_clamp = FALSE;
1237 }
1238
1239 UPDATE_STATE(state, r300->rs_state);
1240 r300->rs_state.size = RS_STATE_MAIN_SIZE + (r300->polygon_offset_enabled ? 5 : 0);
1241
1242 if (last_sprite_coord_enable != r300->sprite_coord_enable ||
1243 last_two_sided_color != r300->two_sided_color) {
1244 r300_mark_atom_dirty(r300, &r300->rs_block_state);
1245 }
1246
1247 if (last_frag_clamp != r300->frag_clamp &&
1248 r300->fs_status == FRAGMENT_SHADER_VALID) {
1249 r300->fs_status = FRAGMENT_SHADER_MAYBE_DIRTY;
1250 }
1251 }
1252
1253 /* Free rasterizer state. */
1254 static void r300_delete_rs_state(struct pipe_context* pipe, void* state)
1255 {
1256 FREE(state);
1257 }
1258
1259 static void*
1260 r300_create_sampler_state(struct pipe_context* pipe,
1261 const struct pipe_sampler_state* state)
1262 {
1263 struct r300_context* r300 = r300_context(pipe);
1264 struct r300_sampler_state* sampler = CALLOC_STRUCT(r300_sampler_state);
1265 boolean is_r500 = r300->screen->caps.is_r500;
1266 int lod_bias;
1267
1268 sampler->state = *state;
1269
1270 /* r300 doesn't handle CLAMP and MIRROR_CLAMP correctly when either MAG
1271 * or MIN filter is NEAREST. Since texwrap produces same results
1272 * for CLAMP and CLAMP_TO_EDGE, we use them instead. */
1273 if (sampler->state.min_img_filter == PIPE_TEX_FILTER_NEAREST ||
1274 sampler->state.mag_img_filter == PIPE_TEX_FILTER_NEAREST) {
1275 /* Wrap S. */
1276 if (sampler->state.wrap_s == PIPE_TEX_WRAP_CLAMP)
1277 sampler->state.wrap_s = PIPE_TEX_WRAP_CLAMP_TO_EDGE;
1278 else if (sampler->state.wrap_s == PIPE_TEX_WRAP_MIRROR_CLAMP)
1279 sampler->state.wrap_s = PIPE_TEX_WRAP_MIRROR_CLAMP_TO_EDGE;
1280
1281 /* Wrap T. */
1282 if (sampler->state.wrap_t == PIPE_TEX_WRAP_CLAMP)
1283 sampler->state.wrap_t = PIPE_TEX_WRAP_CLAMP_TO_EDGE;
1284 else if (sampler->state.wrap_t == PIPE_TEX_WRAP_MIRROR_CLAMP)
1285 sampler->state.wrap_t = PIPE_TEX_WRAP_MIRROR_CLAMP_TO_EDGE;
1286
1287 /* Wrap R. */
1288 if (sampler->state.wrap_r == PIPE_TEX_WRAP_CLAMP)
1289 sampler->state.wrap_r = PIPE_TEX_WRAP_CLAMP_TO_EDGE;
1290 else if (sampler->state.wrap_r == PIPE_TEX_WRAP_MIRROR_CLAMP)
1291 sampler->state.wrap_r = PIPE_TEX_WRAP_MIRROR_CLAMP_TO_EDGE;
1292 }
1293
1294 sampler->filter0 |=
1295 (r300_translate_wrap(sampler->state.wrap_s) << R300_TX_WRAP_S_SHIFT) |
1296 (r300_translate_wrap(sampler->state.wrap_t) << R300_TX_WRAP_T_SHIFT) |
1297 (r300_translate_wrap(sampler->state.wrap_r) << R300_TX_WRAP_R_SHIFT);
1298
1299 sampler->filter0 |= r300_translate_tex_filters(state->min_img_filter,
1300 state->mag_img_filter,
1301 state->min_mip_filter,
1302 state->max_anisotropy > 0);
1303
1304 sampler->filter0 |= r300_anisotropy(state->max_anisotropy);
1305
1306 /* Unfortunately, r300-r500 don't support floating-point mipmap lods. */
1307 /* We must pass these to the merge function to clamp them properly. */
1308 sampler->min_lod = (unsigned)MAX2(state->min_lod, 0);
1309 sampler->max_lod = (unsigned)MAX2(ceilf(state->max_lod), 0);
1310
1311 lod_bias = CLAMP((int)(state->lod_bias * 32 + 1), -(1 << 9), (1 << 9) - 1);
1312
1313 sampler->filter1 |= (lod_bias << R300_LOD_BIAS_SHIFT) & R300_LOD_BIAS_MASK;
1314
1315 /* This is very high quality anisotropic filtering for R5xx.
1316 * It's good for benchmarking the performance of texturing but
1317 * in practice we don't want to slow down the driver because it's
1318 * a pretty good performance killer. Feel free to play with it. */
1319 if (DBG_ON(r300, DBG_ANISOHQ) && is_r500) {
1320 sampler->filter1 |= r500_anisotropy(state->max_anisotropy);
1321 }
1322
1323 /* R500-specific fixups and optimizations */
1324 if (r300->screen->caps.is_r500) {
1325 sampler->filter1 |= R500_BORDER_FIX;
1326 }
1327
1328 return (void*)sampler;
1329 }
1330
1331 static void r300_bind_sampler_states(struct pipe_context* pipe,
1332 unsigned count,
1333 void** states)
1334 {
1335 struct r300_context* r300 = r300_context(pipe);
1336 struct r300_textures_state* state =
1337 (struct r300_textures_state*)r300->textures_state.state;
1338 unsigned tex_units = r300->screen->caps.num_tex_units;
1339
1340 if (count > tex_units) {
1341 return;
1342 }
1343
1344 memcpy(state->sampler_states, states, sizeof(void*) * count);
1345 state->sampler_state_count = count;
1346
1347 r300_mark_atom_dirty(r300, &r300->textures_state);
1348 }
1349
1350 static void r300_lacks_vertex_textures(struct pipe_context* pipe,
1351 unsigned count,
1352 void** states)
1353 {
1354 }
1355
1356 static void r300_delete_sampler_state(struct pipe_context* pipe, void* state)
1357 {
1358 FREE(state);
1359 }
1360
1361 static uint32_t r300_assign_texture_cache_region(unsigned index, unsigned num)
1362 {
1363 /* This looks like a hack, but I believe it's suppose to work like
1364 * that. To illustrate how this works, let's assume you have 5 textures.
1365 * From docs, 5 and the successive numbers are:
1366 *
1367 * FOURTH_1 = 5
1368 * FOURTH_2 = 6
1369 * FOURTH_3 = 7
1370 * EIGHTH_0 = 8
1371 * EIGHTH_1 = 9
1372 *
1373 * First 3 textures will get 3/4 of size of the cache, divived evenly
1374 * between them. The last 1/4 of the cache must be divided between
1375 * the last 2 textures, each will therefore get 1/8 of the cache.
1376 * Why not just to use "5 + texture_index" ?
1377 *
1378 * This simple trick works for all "num" <= 16.
1379 */
1380 if (num <= 1)
1381 return R300_TX_CACHE(R300_TX_CACHE_WHOLE);
1382 else
1383 return R300_TX_CACHE(num + index);
1384 }
1385
1386 static void r300_set_fragment_sampler_views(struct pipe_context* pipe,
1387 unsigned count,
1388 struct pipe_sampler_view** views)
1389 {
1390 struct r300_context* r300 = r300_context(pipe);
1391 struct r300_textures_state* state =
1392 (struct r300_textures_state*)r300->textures_state.state;
1393 struct r300_resource *texture;
1394 unsigned i, real_num_views = 0, view_index = 0;
1395 unsigned tex_units = r300->screen->caps.num_tex_units;
1396 boolean dirty_tex = FALSE;
1397
1398 if (count > tex_units) {
1399 return;
1400 }
1401
1402 /* Calculate the real number of views. */
1403 for (i = 0; i < count; i++) {
1404 if (views[i])
1405 real_num_views++;
1406 }
1407
1408 for (i = 0; i < count; i++) {
1409 pipe_sampler_view_reference(
1410 (struct pipe_sampler_view**)&state->sampler_views[i],
1411 views[i]);
1412
1413 if (!views[i]) {
1414 continue;
1415 }
1416
1417 /* A new sampler view (= texture)... */
1418 dirty_tex = TRUE;
1419
1420 /* Set the texrect factor in the fragment shader.
1421 * Needed for RECT and NPOT fallback. */
1422 texture = r300_resource(views[i]->texture);
1423 if (texture->tex.is_npot) {
1424 r300_mark_atom_dirty(r300, &r300->fs_rc_constant_state);
1425 }
1426
1427 state->sampler_views[i]->texcache_region =
1428 r300_assign_texture_cache_region(view_index, real_num_views);
1429 view_index++;
1430 }
1431
1432 for (i = count; i < tex_units; i++) {
1433 if (state->sampler_views[i]) {
1434 pipe_sampler_view_reference(
1435 (struct pipe_sampler_view**)&state->sampler_views[i],
1436 NULL);
1437 }
1438 }
1439
1440 state->sampler_view_count = count;
1441
1442 r300_mark_atom_dirty(r300, &r300->textures_state);
1443
1444 if (dirty_tex) {
1445 r300_mark_atom_dirty(r300, &r300->texture_cache_inval);
1446 }
1447 }
1448
1449 static struct pipe_sampler_view *
1450 r300_create_sampler_view(struct pipe_context *pipe,
1451 struct pipe_resource *texture,
1452 const struct pipe_sampler_view *templ)
1453 {
1454 struct r300_sampler_view *view = CALLOC_STRUCT(r300_sampler_view);
1455 struct r300_resource *tex = r300_resource(texture);
1456 boolean is_r500 = r300_screen(pipe->screen)->caps.is_r500;
1457 boolean dxtc_swizzle = r300_screen(pipe->screen)->caps.dxtc_swizzle;
1458
1459 if (view) {
1460 view->base = *templ;
1461 view->base.reference.count = 1;
1462 view->base.context = pipe;
1463 view->base.texture = NULL;
1464 pipe_resource_reference(&view->base.texture, texture);
1465
1466 view->swizzle[0] = templ->swizzle_r;
1467 view->swizzle[1] = templ->swizzle_g;
1468 view->swizzle[2] = templ->swizzle_b;
1469 view->swizzle[3] = templ->swizzle_a;
1470
1471 view->format = tex->tx_format;
1472 view->format.format1 |= r300_translate_texformat(templ->format,
1473 view->swizzle,
1474 is_r500,
1475 dxtc_swizzle);
1476 if (is_r500) {
1477 view->format.format2 |= r500_tx_format_msb_bit(templ->format);
1478 }
1479 }
1480
1481 return (struct pipe_sampler_view*)view;
1482 }
1483
1484 static void
1485 r300_sampler_view_destroy(struct pipe_context *pipe,
1486 struct pipe_sampler_view *view)
1487 {
1488 pipe_resource_reference(&view->texture, NULL);
1489 FREE(view);
1490 }
1491
1492 static void r300_set_scissor_state(struct pipe_context* pipe,
1493 const struct pipe_scissor_state* state)
1494 {
1495 struct r300_context* r300 = r300_context(pipe);
1496
1497 memcpy(r300->scissor_state.state, state,
1498 sizeof(struct pipe_scissor_state));
1499
1500 r300_mark_atom_dirty(r300, &r300->scissor_state);
1501 }
1502
1503 static void r300_set_viewport_state(struct pipe_context* pipe,
1504 const struct pipe_viewport_state* state)
1505 {
1506 struct r300_context* r300 = r300_context(pipe);
1507 struct r300_viewport_state* viewport =
1508 (struct r300_viewport_state*)r300->viewport_state.state;
1509
1510 r300->viewport = *state;
1511
1512 if (r300->draw) {
1513 draw_set_viewport_state(r300->draw, state);
1514 viewport->vte_control = R300_VTX_XY_FMT | R300_VTX_Z_FMT;
1515 return;
1516 }
1517
1518 /* Do the transform in HW. */
1519 viewport->vte_control = R300_VTX_W0_FMT;
1520
1521 if (state->scale[0] != 1.0f) {
1522 viewport->xscale = state->scale[0];
1523 viewport->vte_control |= R300_VPORT_X_SCALE_ENA;
1524 }
1525 if (state->scale[1] != 1.0f) {
1526 viewport->yscale = state->scale[1];
1527 viewport->vte_control |= R300_VPORT_Y_SCALE_ENA;
1528 }
1529 if (state->scale[2] != 1.0f) {
1530 viewport->zscale = state->scale[2];
1531 viewport->vte_control |= R300_VPORT_Z_SCALE_ENA;
1532 }
1533 if (state->translate[0] != 0.0f) {
1534 viewport->xoffset = state->translate[0];
1535 viewport->vte_control |= R300_VPORT_X_OFFSET_ENA;
1536 }
1537 if (state->translate[1] != 0.0f) {
1538 viewport->yoffset = state->translate[1];
1539 viewport->vte_control |= R300_VPORT_Y_OFFSET_ENA;
1540 }
1541 if (state->translate[2] != 0.0f) {
1542 viewport->zoffset = state->translate[2];
1543 viewport->vte_control |= R300_VPORT_Z_OFFSET_ENA;
1544 }
1545
1546 r300_mark_atom_dirty(r300, &r300->viewport_state);
1547 if (r300->fs.state && r300_fs(r300)->shader &&
1548 r300_fs(r300)->shader->inputs.wpos != ATTR_UNUSED) {
1549 r300_mark_atom_dirty(r300, &r300->fs_rc_constant_state);
1550 }
1551 }
1552
1553 static void r300_set_vertex_buffers(struct pipe_context* pipe,
1554 unsigned count,
1555 const struct pipe_vertex_buffer* buffers)
1556 {
1557 struct r300_context* r300 = r300_context(pipe);
1558 unsigned i;
1559 struct pipe_vertex_buffer dummy_vb = {0};
1560
1561 /* There must be at least one vertex buffer set, otherwise it locks up. */
1562 if (!count) {
1563 dummy_vb.buffer = r300->dummy_vb;
1564 buffers = &dummy_vb;
1565 count = 1;
1566 }
1567
1568 u_vbuf_mgr_set_vertex_buffers(r300->vbuf_mgr, count, buffers);
1569
1570 if (r300->screen->caps.has_tcl) {
1571 /* HW TCL. */
1572 for (i = 0; i < count; i++) {
1573 if (buffers[i].buffer &&
1574 !r300_resource(buffers[i].buffer)->b.user_ptr) {
1575 }
1576 }
1577 r300->vertex_arrays_dirty = TRUE;
1578 } else {
1579 /* SW TCL. */
1580 draw_set_vertex_buffers(r300->draw, count, buffers);
1581 }
1582 }
1583
1584 static void r300_set_index_buffer(struct pipe_context* pipe,
1585 const struct pipe_index_buffer *ib)
1586 {
1587 struct r300_context* r300 = r300_context(pipe);
1588
1589 if (ib && ib->buffer) {
1590 assert(ib->offset % ib->index_size == 0);
1591
1592 pipe_resource_reference(&r300->index_buffer.buffer, ib->buffer);
1593 memcpy(&r300->index_buffer, ib, sizeof(r300->index_buffer));
1594 r300->index_buffer.offset /= r300->index_buffer.index_size;
1595 }
1596 else {
1597 pipe_resource_reference(&r300->index_buffer.buffer, NULL);
1598 memset(&r300->index_buffer, 0, sizeof(r300->index_buffer));
1599 }
1600
1601 if (!r300->screen->caps.has_tcl) {
1602 draw_set_index_buffer(r300->draw, ib);
1603 }
1604 }
1605
1606 /* Initialize the PSC tables. */
1607 static void r300_vertex_psc(struct r300_vertex_element_state *velems)
1608 {
1609 struct r300_vertex_stream_state *vstream = &velems->vertex_stream;
1610 uint16_t type, swizzle;
1611 enum pipe_format format;
1612 unsigned i;
1613
1614 /* Vertex shaders have no semantics on their inputs,
1615 * so PSC should just route stuff based on the vertex elements,
1616 * and not on attrib information. */
1617 for (i = 0; i < velems->count; i++) {
1618 format = velems->velem[i].src_format;
1619
1620 type = r300_translate_vertex_data_type(format);
1621 if (type == R300_INVALID_FORMAT) {
1622 fprintf(stderr, "r300: Bad vertex format %s.\n",
1623 util_format_short_name(format));
1624 assert(0);
1625 abort();
1626 }
1627
1628 type |= i << R300_DST_VEC_LOC_SHIFT;
1629 swizzle = r300_translate_vertex_data_swizzle(format);
1630
1631 if (i & 1) {
1632 vstream->vap_prog_stream_cntl[i >> 1] |= type << 16;
1633 vstream->vap_prog_stream_cntl_ext[i >> 1] |= swizzle << 16;
1634 } else {
1635 vstream->vap_prog_stream_cntl[i >> 1] |= type;
1636 vstream->vap_prog_stream_cntl_ext[i >> 1] |= swizzle;
1637 }
1638 }
1639
1640 /* Set the last vector in the PSC. */
1641 if (i) {
1642 i -= 1;
1643 }
1644 vstream->vap_prog_stream_cntl[i >> 1] |=
1645 (R300_LAST_VEC << (i & 1 ? 16 : 0));
1646
1647 vstream->count = (i >> 1) + 1;
1648 }
1649
1650 static void* r300_create_vertex_elements_state(struct pipe_context* pipe,
1651 unsigned count,
1652 const struct pipe_vertex_element* attribs)
1653 {
1654 struct r300_context *r300 = r300_context(pipe);
1655 struct r300_vertex_element_state *velems;
1656 unsigned i;
1657 struct pipe_vertex_element dummy_attrib = {0};
1658
1659 /* R300 Programmable Stream Control (PSC) doesn't support 0 vertex elements. */
1660 if (!count) {
1661 dummy_attrib.src_format = PIPE_FORMAT_R8G8B8A8_UNORM;
1662 attribs = &dummy_attrib;
1663 count = 1;
1664 } else if (count > 16) {
1665 fprintf(stderr, "r300: More than 16 vertex elements are not supported,"
1666 " requested %i, using 16.\n", count);
1667 count = 16;
1668 }
1669
1670 velems = CALLOC_STRUCT(r300_vertex_element_state);
1671 if (!velems)
1672 return NULL;
1673
1674 velems->count = count;
1675 velems->vmgr_elements =
1676 u_vbuf_mgr_create_vertex_elements(r300->vbuf_mgr, count, attribs,
1677 velems->velem);
1678
1679 if (r300_screen(pipe->screen)->caps.has_tcl) {
1680 /* Setup PSC.
1681 * The unused components will be replaced by (..., 0, 1). */
1682 r300_vertex_psc(velems);
1683
1684 for (i = 0; i < count; i++) {
1685 velems->format_size[i] =
1686 align(util_format_get_blocksize(velems->velem[i].src_format), 4);
1687 velems->vertex_size_dwords += velems->format_size[i] / 4;
1688 }
1689 }
1690
1691 return velems;
1692 }
1693
1694 static void r300_bind_vertex_elements_state(struct pipe_context *pipe,
1695 void *state)
1696 {
1697 struct r300_context *r300 = r300_context(pipe);
1698 struct r300_vertex_element_state *velems = state;
1699
1700 if (velems == NULL) {
1701 return;
1702 }
1703
1704 r300->velems = velems;
1705
1706 u_vbuf_mgr_bind_vertex_elements(r300->vbuf_mgr, state, velems->vmgr_elements);
1707
1708 if (r300->draw) {
1709 draw_set_vertex_elements(r300->draw, velems->count, velems->velem);
1710 return;
1711 }
1712
1713 UPDATE_STATE(&velems->vertex_stream, r300->vertex_stream_state);
1714 r300->vertex_stream_state.size = (1 + velems->vertex_stream.count) * 2;
1715 r300->vertex_arrays_dirty = TRUE;
1716 }
1717
1718 static void r300_delete_vertex_elements_state(struct pipe_context *pipe, void *state)
1719 {
1720 struct r300_context *r300 = r300_context(pipe);
1721 struct r300_vertex_element_state *velems = state;
1722
1723 u_vbuf_mgr_destroy_vertex_elements(r300->vbuf_mgr, velems->vmgr_elements);
1724 FREE(state);
1725 }
1726
1727 static void* r300_create_vs_state(struct pipe_context* pipe,
1728 const struct pipe_shader_state* shader)
1729 {
1730 struct r300_context* r300 = r300_context(pipe);
1731 struct r300_vertex_shader* vs = CALLOC_STRUCT(r300_vertex_shader);
1732
1733 /* Copy state directly into shader. */
1734 vs->state = *shader;
1735 vs->state.tokens = tgsi_dup_tokens(shader->tokens);
1736
1737 if (r300->screen->caps.has_tcl) {
1738 r300_init_vs_outputs(vs);
1739 r300_translate_vertex_shader(r300, vs);
1740 } else {
1741 r300_draw_init_vertex_shader(r300->draw, vs);
1742 }
1743
1744 return vs;
1745 }
1746
1747 static void r300_bind_vs_state(struct pipe_context* pipe, void* shader)
1748 {
1749 struct r300_context* r300 = r300_context(pipe);
1750 struct r300_vertex_shader* vs = (struct r300_vertex_shader*)shader;
1751
1752 if (vs == NULL) {
1753 r300->vs_state.state = NULL;
1754 return;
1755 }
1756 if (vs == r300->vs_state.state) {
1757 return;
1758 }
1759 r300->vs_state.state = vs;
1760
1761 /* The majority of the RS block bits is dependent on the vertex shader. */
1762 r300_mark_atom_dirty(r300, &r300->rs_block_state); /* Will be updated before the emission. */
1763
1764 if (r300->screen->caps.has_tcl) {
1765 unsigned fc_op_dwords = r300->screen->caps.is_r500 ? 3 : 2;
1766 r300_mark_atom_dirty(r300, &r300->vs_state);
1767 r300->vs_state.size =
1768 vs->code.length + 9 +
1769 (vs->code.num_fc_ops ? vs->code.num_fc_ops * fc_op_dwords + 4 : 0);
1770
1771 r300_mark_atom_dirty(r300, &r300->vs_constants);
1772 r300->vs_constants.size =
1773 2 +
1774 (vs->externals_count ? vs->externals_count * 4 + 3 : 0) +
1775 (vs->immediates_count ? vs->immediates_count * 4 + 3 : 0);
1776
1777 ((struct r300_constant_buffer*)r300->vs_constants.state)->remap_table =
1778 vs->code.constants_remap_table;
1779
1780 r300_mark_atom_dirty(r300, &r300->pvs_flush);
1781 } else {
1782 draw_bind_vertex_shader(r300->draw,
1783 (struct draw_vertex_shader*)vs->draw_vs);
1784 }
1785 }
1786
1787 static void r300_delete_vs_state(struct pipe_context* pipe, void* shader)
1788 {
1789 struct r300_context* r300 = r300_context(pipe);
1790 struct r300_vertex_shader* vs = (struct r300_vertex_shader*)shader;
1791
1792 if (r300->screen->caps.has_tcl) {
1793 rc_constants_destroy(&vs->code.constants);
1794 if (vs->code.constants_remap_table)
1795 FREE(vs->code.constants_remap_table);
1796 } else {
1797 draw_delete_vertex_shader(r300->draw,
1798 (struct draw_vertex_shader*)vs->draw_vs);
1799 }
1800
1801 FREE((void*)vs->state.tokens);
1802 FREE(shader);
1803 }
1804
1805 static void r300_set_constant_buffer(struct pipe_context *pipe,
1806 uint shader, uint index,
1807 struct pipe_resource *buf)
1808 {
1809 struct r300_context* r300 = r300_context(pipe);
1810 struct r300_constant_buffer *cbuf;
1811 struct r300_resource *rbuf = r300_resource(buf);
1812 uint32_t *mapped;
1813
1814 switch (shader) {
1815 case PIPE_SHADER_VERTEX:
1816 cbuf = (struct r300_constant_buffer*)r300->vs_constants.state;
1817 break;
1818 case PIPE_SHADER_FRAGMENT:
1819 cbuf = (struct r300_constant_buffer*)r300->fs_constants.state;
1820 break;
1821 default:
1822 return;
1823 }
1824
1825 if (buf == NULL || buf->width0 == 0)
1826 return;
1827
1828 if (rbuf->b.user_ptr)
1829 mapped = (uint32_t*)rbuf->b.user_ptr;
1830 else if (rbuf->constant_buffer)
1831 mapped = (uint32_t*)rbuf->constant_buffer;
1832 else
1833 return;
1834
1835 if (shader == PIPE_SHADER_FRAGMENT ||
1836 (shader == PIPE_SHADER_VERTEX && r300->screen->caps.has_tcl)) {
1837 cbuf->ptr = mapped;
1838 }
1839
1840 if (shader == PIPE_SHADER_VERTEX) {
1841 if (r300->screen->caps.has_tcl) {
1842 struct r300_vertex_shader *vs =
1843 (struct r300_vertex_shader*)r300->vs_state.state;
1844
1845 if (!vs) {
1846 cbuf->buffer_base = 0;
1847 return;
1848 }
1849
1850 cbuf->buffer_base = r300->vs_const_base;
1851 r300->vs_const_base += vs->code.constants.Count;
1852 if (r300->vs_const_base > R500_MAX_PVS_CONST_VECS) {
1853 r300->vs_const_base = vs->code.constants.Count;
1854 cbuf->buffer_base = 0;
1855 r300_mark_atom_dirty(r300, &r300->pvs_flush);
1856 }
1857 r300_mark_atom_dirty(r300, &r300->vs_constants);
1858 } else if (r300->draw) {
1859 draw_set_mapped_constant_buffer(r300->draw, PIPE_SHADER_VERTEX,
1860 0, mapped, buf->width0);
1861 }
1862 } else if (shader == PIPE_SHADER_FRAGMENT) {
1863 r300_mark_atom_dirty(r300, &r300->fs_constants);
1864 }
1865 }
1866
1867 static void r300_texture_barrier(struct pipe_context *pipe)
1868 {
1869 struct r300_context *r300 = r300_context(pipe);
1870
1871 r300_mark_atom_dirty(r300, &r300->gpu_flush);
1872 r300_mark_atom_dirty(r300, &r300->texture_cache_inval);
1873 }
1874
1875 void r300_init_state_functions(struct r300_context* r300)
1876 {
1877 r300->context.create_blend_state = r300_create_blend_state;
1878 r300->context.bind_blend_state = r300_bind_blend_state;
1879 r300->context.delete_blend_state = r300_delete_blend_state;
1880
1881 r300->context.set_blend_color = r300_set_blend_color;
1882
1883 r300->context.set_clip_state = r300_set_clip_state;
1884 r300->context.set_sample_mask = r300_set_sample_mask;
1885
1886 r300->context.set_constant_buffer = r300_set_constant_buffer;
1887
1888 r300->context.create_depth_stencil_alpha_state = r300_create_dsa_state;
1889 r300->context.bind_depth_stencil_alpha_state = r300_bind_dsa_state;
1890 r300->context.delete_depth_stencil_alpha_state = r300_delete_dsa_state;
1891
1892 r300->context.set_stencil_ref = r300_set_stencil_ref;
1893
1894 r300->context.set_framebuffer_state = r300_set_framebuffer_state;
1895
1896 r300->context.create_fs_state = r300_create_fs_state;
1897 r300->context.bind_fs_state = r300_bind_fs_state;
1898 r300->context.delete_fs_state = r300_delete_fs_state;
1899
1900 r300->context.set_polygon_stipple = r300_set_polygon_stipple;
1901
1902 r300->context.create_rasterizer_state = r300_create_rs_state;
1903 r300->context.bind_rasterizer_state = r300_bind_rs_state;
1904 r300->context.delete_rasterizer_state = r300_delete_rs_state;
1905
1906 r300->context.create_sampler_state = r300_create_sampler_state;
1907 r300->context.bind_fragment_sampler_states = r300_bind_sampler_states;
1908 r300->context.bind_vertex_sampler_states = r300_lacks_vertex_textures;
1909 r300->context.delete_sampler_state = r300_delete_sampler_state;
1910
1911 r300->context.set_fragment_sampler_views = r300_set_fragment_sampler_views;
1912 r300->context.create_sampler_view = r300_create_sampler_view;
1913 r300->context.sampler_view_destroy = r300_sampler_view_destroy;
1914
1915 r300->context.set_scissor_state = r300_set_scissor_state;
1916
1917 r300->context.set_viewport_state = r300_set_viewport_state;
1918
1919 r300->context.set_vertex_buffers = r300_set_vertex_buffers;
1920 r300->context.set_index_buffer = r300_set_index_buffer;
1921 r300->context.redefine_user_buffer = u_default_redefine_user_buffer;
1922
1923 r300->context.create_vertex_elements_state = r300_create_vertex_elements_state;
1924 r300->context.bind_vertex_elements_state = r300_bind_vertex_elements_state;
1925 r300->context.delete_vertex_elements_state = r300_delete_vertex_elements_state;
1926
1927 r300->context.create_vs_state = r300_create_vs_state;
1928 r300->context.bind_vs_state = r300_bind_vs_state;
1929 r300->context.delete_vs_state = r300_delete_vs_state;
1930
1931 r300->context.texture_barrier = r300_texture_barrier;
1932 }