2 * Copyright 2008 Corbin Simpson <MostAwesomeDude@gmail.com>
3 * Copyright 2009 Marek Olšák <maraeo@gmail.com>
5 * Permission is hereby granted, free of charge, to any person obtaining a
6 * copy of this software and associated documentation files (the "Software"),
7 * to deal in the Software without restriction, including without limitation
8 * on the rights to use, copy, modify, merge, publish, distribute, sub
9 * license, and/or sell copies of the Software, and to permit persons to whom
10 * the Software is furnished to do so, subject to the following conditions:
12 * The above copyright notice and this permission notice (including the next
13 * paragraph) shall be included in all copies or substantial portions of the
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
19 * THE AUTHOR(S) AND/OR THEIR SUPPLIERS BE LIABLE FOR ANY CLAIM,
20 * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
21 * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
22 * USE OR OTHER DEALINGS IN THE SOFTWARE. */
24 #include "draw/draw_context.h"
26 #include "util/u_framebuffer.h"
27 #include "util/u_math.h"
28 #include "util/u_mm.h"
29 #include "util/u_memory.h"
30 #include "util/u_pack_color.h"
32 #include "tgsi/tgsi_parse.h"
34 #include "pipe/p_config.h"
37 #include "r300_context.h"
38 #include "r300_emit.h"
40 #include "r300_screen.h"
41 #include "r300_screen_buffer.h"
42 #include "r300_state_inlines.h"
44 #include "r300_texture.h"
46 #include "r300_winsys.h"
47 #include "r300_hyperz.h"
49 /* r300_state: Functions used to intialize state context by translating
50 * Gallium state objects into semi-native r300 state objects. */
52 #define UPDATE_STATE(cso, atom) \
53 if (cso != atom.state) { \
58 static boolean
blend_discard_if_src_alpha_0(unsigned srcRGB
, unsigned srcA
,
59 unsigned dstRGB
, unsigned dstA
)
61 /* If the blend equation is ADD or REVERSE_SUBTRACT,
62 * SRC_ALPHA == 0, and the following state is set, the colorbuffer
63 * will not be changed.
64 * Notice that the dst factors are the src factors inverted. */
65 return (srcRGB
== PIPE_BLENDFACTOR_SRC_ALPHA
||
66 srcRGB
== PIPE_BLENDFACTOR_SRC_ALPHA_SATURATE
||
67 srcRGB
== PIPE_BLENDFACTOR_ZERO
) &&
68 (srcA
== PIPE_BLENDFACTOR_SRC_COLOR
||
69 srcA
== PIPE_BLENDFACTOR_SRC_ALPHA
||
70 srcA
== PIPE_BLENDFACTOR_SRC_ALPHA_SATURATE
||
71 srcA
== PIPE_BLENDFACTOR_ZERO
) &&
72 (dstRGB
== PIPE_BLENDFACTOR_INV_SRC_ALPHA
||
73 dstRGB
== PIPE_BLENDFACTOR_ONE
) &&
74 (dstA
== PIPE_BLENDFACTOR_INV_SRC_COLOR
||
75 dstA
== PIPE_BLENDFACTOR_INV_SRC_ALPHA
||
76 dstA
== PIPE_BLENDFACTOR_ONE
);
79 static boolean
blend_discard_if_src_alpha_1(unsigned srcRGB
, unsigned srcA
,
80 unsigned dstRGB
, unsigned dstA
)
82 /* If the blend equation is ADD or REVERSE_SUBTRACT,
83 * SRC_ALPHA == 1, and the following state is set, the colorbuffer
84 * will not be changed.
85 * Notice that the dst factors are the src factors inverted. */
86 return (srcRGB
== PIPE_BLENDFACTOR_INV_SRC_ALPHA
||
87 srcRGB
== PIPE_BLENDFACTOR_ZERO
) &&
88 (srcA
== PIPE_BLENDFACTOR_INV_SRC_COLOR
||
89 srcA
== PIPE_BLENDFACTOR_INV_SRC_ALPHA
||
90 srcA
== PIPE_BLENDFACTOR_ZERO
) &&
91 (dstRGB
== PIPE_BLENDFACTOR_SRC_ALPHA
||
92 dstRGB
== PIPE_BLENDFACTOR_ONE
) &&
93 (dstA
== PIPE_BLENDFACTOR_SRC_COLOR
||
94 dstA
== PIPE_BLENDFACTOR_SRC_ALPHA
||
95 dstA
== PIPE_BLENDFACTOR_ONE
);
98 static boolean
blend_discard_if_src_color_0(unsigned srcRGB
, unsigned srcA
,
99 unsigned dstRGB
, unsigned dstA
)
101 /* If the blend equation is ADD or REVERSE_SUBTRACT,
102 * SRC_COLOR == (0,0,0), and the following state is set, the colorbuffer
103 * will not be changed.
104 * Notice that the dst factors are the src factors inverted. */
105 return (srcRGB
== PIPE_BLENDFACTOR_SRC_COLOR
||
106 srcRGB
== PIPE_BLENDFACTOR_ZERO
) &&
107 (srcA
== PIPE_BLENDFACTOR_ZERO
) &&
108 (dstRGB
== PIPE_BLENDFACTOR_INV_SRC_COLOR
||
109 dstRGB
== PIPE_BLENDFACTOR_ONE
) &&
110 (dstA
== PIPE_BLENDFACTOR_ONE
);
113 static boolean
blend_discard_if_src_color_1(unsigned srcRGB
, unsigned srcA
,
114 unsigned dstRGB
, unsigned dstA
)
116 /* If the blend equation is ADD or REVERSE_SUBTRACT,
117 * SRC_COLOR == (1,1,1), and the following state is set, the colorbuffer
118 * will not be changed.
119 * Notice that the dst factors are the src factors inverted. */
120 return (srcRGB
== PIPE_BLENDFACTOR_INV_SRC_COLOR
||
121 srcRGB
== PIPE_BLENDFACTOR_ZERO
) &&
122 (srcA
== PIPE_BLENDFACTOR_ZERO
) &&
123 (dstRGB
== PIPE_BLENDFACTOR_SRC_COLOR
||
124 dstRGB
== PIPE_BLENDFACTOR_ONE
) &&
125 (dstA
== PIPE_BLENDFACTOR_ONE
);
128 static boolean
blend_discard_if_src_alpha_color_0(unsigned srcRGB
, unsigned srcA
,
129 unsigned dstRGB
, unsigned dstA
)
131 /* If the blend equation is ADD or REVERSE_SUBTRACT,
132 * SRC_ALPHA_COLOR == (0,0,0,0), and the following state is set,
133 * the colorbuffer will not be changed.
134 * Notice that the dst factors are the src factors inverted. */
135 return (srcRGB
== PIPE_BLENDFACTOR_SRC_COLOR
||
136 srcRGB
== PIPE_BLENDFACTOR_SRC_ALPHA
||
137 srcRGB
== PIPE_BLENDFACTOR_SRC_ALPHA_SATURATE
||
138 srcRGB
== PIPE_BLENDFACTOR_ZERO
) &&
139 (srcA
== PIPE_BLENDFACTOR_SRC_COLOR
||
140 srcA
== PIPE_BLENDFACTOR_SRC_ALPHA
||
141 srcA
== PIPE_BLENDFACTOR_SRC_ALPHA_SATURATE
||
142 srcA
== PIPE_BLENDFACTOR_ZERO
) &&
143 (dstRGB
== PIPE_BLENDFACTOR_INV_SRC_COLOR
||
144 dstRGB
== PIPE_BLENDFACTOR_INV_SRC_ALPHA
||
145 dstRGB
== PIPE_BLENDFACTOR_ONE
) &&
146 (dstA
== PIPE_BLENDFACTOR_INV_SRC_COLOR
||
147 dstA
== PIPE_BLENDFACTOR_INV_SRC_ALPHA
||
148 dstA
== PIPE_BLENDFACTOR_ONE
);
151 static boolean
blend_discard_if_src_alpha_color_1(unsigned srcRGB
, unsigned srcA
,
152 unsigned dstRGB
, unsigned dstA
)
154 /* If the blend equation is ADD or REVERSE_SUBTRACT,
155 * SRC_ALPHA_COLOR == (1,1,1,1), and the following state is set,
156 * the colorbuffer will not be changed.
157 * Notice that the dst factors are the src factors inverted. */
158 return (srcRGB
== PIPE_BLENDFACTOR_INV_SRC_COLOR
||
159 srcRGB
== PIPE_BLENDFACTOR_INV_SRC_ALPHA
||
160 srcRGB
== PIPE_BLENDFACTOR_ZERO
) &&
161 (srcA
== PIPE_BLENDFACTOR_INV_SRC_COLOR
||
162 srcA
== PIPE_BLENDFACTOR_INV_SRC_ALPHA
||
163 srcA
== PIPE_BLENDFACTOR_ZERO
) &&
164 (dstRGB
== PIPE_BLENDFACTOR_SRC_COLOR
||
165 dstRGB
== PIPE_BLENDFACTOR_SRC_ALPHA
||
166 dstRGB
== PIPE_BLENDFACTOR_ONE
) &&
167 (dstA
== PIPE_BLENDFACTOR_SRC_COLOR
||
168 dstA
== PIPE_BLENDFACTOR_SRC_ALPHA
||
169 dstA
== PIPE_BLENDFACTOR_ONE
);
172 static unsigned bgra_cmask(unsigned mask
)
174 /* Gallium uses RGBA color ordering while R300 expects BGRA. */
176 return ((mask
& PIPE_MASK_R
) << 2) |
177 ((mask
& PIPE_MASK_B
) >> 2) |
178 (mask
& (PIPE_MASK_G
| PIPE_MASK_A
));
181 /* Create a new blend state based on the CSO blend state.
183 * This encompasses alpha blending, logic/raster ops, and blend dithering. */
184 static void* r300_create_blend_state(struct pipe_context
* pipe
,
185 const struct pipe_blend_state
* state
)
187 struct r300_screen
* r300screen
= r300_screen(pipe
->screen
);
188 struct r300_blend_state
* blend
= CALLOC_STRUCT(r300_blend_state
);
189 uint32_t blend_control
= 0; /* R300_RB3D_CBLEND: 0x4e04 */
190 uint32_t alpha_blend_control
= 0; /* R300_RB3D_ABLEND: 0x4e08 */
191 uint32_t color_channel_mask
= 0; /* R300_RB3D_COLOR_CHANNEL_MASK: 0x4e0c */
192 uint32_t rop
= 0; /* R300_RB3D_ROPCNTL: 0x4e18 */
193 uint32_t dither
= 0; /* R300_RB3D_DITHER_CTL: 0x4e50 */
196 if (state
->rt
[0].blend_enable
)
198 unsigned eqRGB
= state
->rt
[0].rgb_func
;
199 unsigned srcRGB
= state
->rt
[0].rgb_src_factor
;
200 unsigned dstRGB
= state
->rt
[0].rgb_dst_factor
;
202 unsigned eqA
= state
->rt
[0].alpha_func
;
203 unsigned srcA
= state
->rt
[0].alpha_src_factor
;
204 unsigned dstA
= state
->rt
[0].alpha_dst_factor
;
206 /* despite the name, ALPHA_BLEND_ENABLE has nothing to do with alpha,
207 * this is just the crappy D3D naming */
208 blend_control
= R300_ALPHA_BLEND_ENABLE
|
209 r300_translate_blend_function(eqRGB
) |
210 ( r300_translate_blend_factor(srcRGB
) << R300_SRC_BLEND_SHIFT
) |
211 ( r300_translate_blend_factor(dstRGB
) << R300_DST_BLEND_SHIFT
);
213 /* Optimization: some operations do not require the destination color.
215 * When SRC_ALPHA_SATURATE is used, colorbuffer reads must be enabled,
216 * otherwise blending gives incorrect results. It seems to be
218 if (eqRGB
== PIPE_BLEND_MIN
|| eqA
== PIPE_BLEND_MIN
||
219 eqRGB
== PIPE_BLEND_MAX
|| eqA
== PIPE_BLEND_MAX
||
220 dstRGB
!= PIPE_BLENDFACTOR_ZERO
||
221 dstA
!= PIPE_BLENDFACTOR_ZERO
||
222 srcRGB
== PIPE_BLENDFACTOR_DST_COLOR
||
223 srcRGB
== PIPE_BLENDFACTOR_DST_ALPHA
||
224 srcRGB
== PIPE_BLENDFACTOR_INV_DST_COLOR
||
225 srcRGB
== PIPE_BLENDFACTOR_INV_DST_ALPHA
||
226 srcA
== PIPE_BLENDFACTOR_DST_COLOR
||
227 srcA
== PIPE_BLENDFACTOR_DST_ALPHA
||
228 srcA
== PIPE_BLENDFACTOR_INV_DST_COLOR
||
229 srcA
== PIPE_BLENDFACTOR_INV_DST_ALPHA
||
230 srcRGB
== PIPE_BLENDFACTOR_SRC_ALPHA_SATURATE
) {
231 /* Enable reading from the colorbuffer. */
232 blend_control
|= R300_READ_ENABLE
;
234 if (r300screen
->caps
.is_r500
) {
235 /* Optimization: Depending on incoming pixels, we can
236 * conditionally disable the reading in hardware... */
237 if (eqRGB
!= PIPE_BLEND_MIN
&& eqA
!= PIPE_BLEND_MIN
&&
238 eqRGB
!= PIPE_BLEND_MAX
&& eqA
!= PIPE_BLEND_MAX
) {
239 /* Disable reading if SRC_ALPHA == 0. */
240 if ((dstRGB
== PIPE_BLENDFACTOR_SRC_ALPHA
||
241 dstRGB
== PIPE_BLENDFACTOR_ZERO
) &&
242 (dstA
== PIPE_BLENDFACTOR_SRC_COLOR
||
243 dstA
== PIPE_BLENDFACTOR_SRC_ALPHA
||
244 dstA
== PIPE_BLENDFACTOR_ZERO
)) {
245 blend_control
|= R500_SRC_ALPHA_0_NO_READ
;
248 /* Disable reading if SRC_ALPHA == 1. */
249 if ((dstRGB
== PIPE_BLENDFACTOR_INV_SRC_ALPHA
||
250 dstRGB
== PIPE_BLENDFACTOR_ZERO
) &&
251 (dstA
== PIPE_BLENDFACTOR_INV_SRC_COLOR
||
252 dstA
== PIPE_BLENDFACTOR_INV_SRC_ALPHA
||
253 dstA
== PIPE_BLENDFACTOR_ZERO
)) {
254 blend_control
|= R500_SRC_ALPHA_1_NO_READ
;
260 /* Optimization: discard pixels which don't change the colorbuffer.
262 * The code below is non-trivial and some math is involved.
264 * Discarding pixels must be disabled when FP16 AA is enabled.
265 * This is a hardware bug. Also, this implementation wouldn't work
266 * with FP blending enabled and equation clamping disabled.
268 * Equations other than ADD are rarely used and therefore won't be
270 if ((eqRGB
== PIPE_BLEND_ADD
|| eqRGB
== PIPE_BLEND_REVERSE_SUBTRACT
) &&
271 (eqA
== PIPE_BLEND_ADD
|| eqA
== PIPE_BLEND_REVERSE_SUBTRACT
)) {
273 * REVERSE_SUBTRACT: Y-X
276 * If X = src*srcFactor = 0 and Y = dst*dstFactor = 1,
277 * then CB will not be changed.
279 * Given the srcFactor and dstFactor variables, we can derive
280 * what src and dst should be equal to and discard appropriate
283 if (blend_discard_if_src_alpha_0(srcRGB
, srcA
, dstRGB
, dstA
)) {
284 blend_control
|= R300_DISCARD_SRC_PIXELS_SRC_ALPHA_0
;
285 } else if (blend_discard_if_src_alpha_1(srcRGB
, srcA
,
287 blend_control
|= R300_DISCARD_SRC_PIXELS_SRC_ALPHA_1
;
288 } else if (blend_discard_if_src_color_0(srcRGB
, srcA
,
290 blend_control
|= R300_DISCARD_SRC_PIXELS_SRC_COLOR_0
;
291 } else if (blend_discard_if_src_color_1(srcRGB
, srcA
,
293 blend_control
|= R300_DISCARD_SRC_PIXELS_SRC_COLOR_1
;
294 } else if (blend_discard_if_src_alpha_color_0(srcRGB
, srcA
,
297 R300_DISCARD_SRC_PIXELS_SRC_ALPHA_COLOR_0
;
298 } else if (blend_discard_if_src_alpha_color_1(srcRGB
, srcA
,
301 R300_DISCARD_SRC_PIXELS_SRC_ALPHA_COLOR_1
;
306 if (srcA
!= srcRGB
|| dstA
!= dstRGB
|| eqA
!= eqRGB
) {
307 blend_control
|= R300_SEPARATE_ALPHA_ENABLE
;
308 alpha_blend_control
=
309 r300_translate_blend_function(eqA
) |
310 (r300_translate_blend_factor(srcA
) << R300_SRC_BLEND_SHIFT
) |
311 (r300_translate_blend_factor(dstA
) << R300_DST_BLEND_SHIFT
);
315 /* PIPE_LOGICOP_* don't need to be translated, fortunately. */
316 if (state
->logicop_enable
) {
317 rop
= R300_RB3D_ROPCNTL_ROP_ENABLE
|
318 (state
->logicop_func
) << R300_RB3D_ROPCNTL_ROP_SHIFT
;
321 /* Color channel masks for all MRTs. */
322 color_channel_mask
= bgra_cmask(state
->rt
[0].colormask
);
323 if (r300screen
->caps
.is_r500
&& state
->independent_blend_enable
) {
324 if (state
->rt
[1].blend_enable
) {
325 color_channel_mask
|= bgra_cmask(state
->rt
[1].colormask
) << 4;
327 if (state
->rt
[2].blend_enable
) {
328 color_channel_mask
|= bgra_cmask(state
->rt
[2].colormask
) << 8;
330 if (state
->rt
[3].blend_enable
) {
331 color_channel_mask
|= bgra_cmask(state
->rt
[3].colormask
) << 12;
335 /* Neither fglrx nor classic r300 ever set this, regardless of dithering
336 * state. Since it's an optional implementation detail, we can leave it
337 * out and never dither.
339 * This could be revisited if we ever get quality or conformance hints.
342 dither = R300_RB3D_DITHER_CTL_DITHER_MODE_LUT |
343 R300_RB3D_DITHER_CTL_ALPHA_DITHER_MODE_LUT;
347 /* Build a command buffer. */
348 BEGIN_CB(blend
->cb
, 8);
349 OUT_CB_REG(R300_RB3D_ROPCNTL
, rop
);
350 OUT_CB_REG_SEQ(R300_RB3D_CBLEND
, 3);
351 OUT_CB(blend_control
);
352 OUT_CB(alpha_blend_control
);
353 OUT_CB(color_channel_mask
);
354 OUT_CB_REG(R300_RB3D_DITHER_CTL
, dither
);
357 /* The same as above, but with no colorbuffer reads and writes. */
358 BEGIN_CB(blend
->cb_no_readwrite
, 8);
359 OUT_CB_REG(R300_RB3D_ROPCNTL
, rop
);
360 OUT_CB_REG_SEQ(R300_RB3D_CBLEND
, 3);
364 OUT_CB_REG(R300_RB3D_DITHER_CTL
, dither
);
370 /* Bind blend state. */
371 static void r300_bind_blend_state(struct pipe_context
* pipe
,
374 struct r300_context
* r300
= r300_context(pipe
);
376 UPDATE_STATE(state
, r300
->blend_state
);
379 /* Free blend state. */
380 static void r300_delete_blend_state(struct pipe_context
* pipe
,
386 /* Convert float to 10bit integer */
387 static unsigned float_to_fixed10(float f
)
389 return CLAMP((unsigned)(f
* 1023.9f
), 0, 1023);
393 * Setup both R300 and R500 registers, figure out later which one to write. */
394 static void r300_set_blend_color(struct pipe_context
* pipe
,
395 const struct pipe_blend_color
* color
)
397 struct r300_context
* r300
= r300_context(pipe
);
398 struct r300_blend_color_state
* state
=
399 (struct r300_blend_color_state
*)r300
->blend_color_state
.state
;
402 if (r300
->screen
->caps
.is_r500
) {
403 /* XXX if FP16 blending is enabled, we should use the FP16 format */
404 BEGIN_CB(state
->cb
, 3);
405 OUT_CB_REG_SEQ(R500_RB3D_CONSTANT_COLOR_AR
, 2);
406 OUT_CB(float_to_fixed10(color
->color
[0]) |
407 (float_to_fixed10(color
->color
[3]) << 16));
408 OUT_CB(float_to_fixed10(color
->color
[2]) |
409 (float_to_fixed10(color
->color
[1]) << 16));
413 util_pack_color(color
->color
, PIPE_FORMAT_B8G8R8A8_UNORM
, &uc
);
415 BEGIN_CB(state
->cb
, 2);
416 OUT_CB_REG(R300_RB3D_BLEND_COLOR
, uc
.ui
);
420 r300
->blend_color_state
.dirty
= TRUE
;
423 static void r300_set_clip_state(struct pipe_context
* pipe
,
424 const struct pipe_clip_state
* state
)
426 struct r300_context
* r300
= r300_context(pipe
);
427 struct r300_clip_state
*clip
=
428 (struct r300_clip_state
*)r300
->clip_state
.state
;
433 if (r300
->screen
->caps
.has_tcl
) {
434 r300
->clip_state
.size
= 2 + !!state
->nr
* 3 + state
->nr
* 4;
436 BEGIN_CB(clip
->cb
, r300
->clip_state
.size
);
438 OUT_CB_REG(R300_VAP_PVS_VECTOR_INDX_REG
,
439 (r300
->screen
->caps
.is_r500
?
440 R500_PVS_UCP_START
: R300_PVS_UCP_START
));
441 OUT_CB_ONE_REG(R300_VAP_PVS_UPLOAD_DATA
, state
->nr
* 4);
442 OUT_CB_TABLE(state
->ucp
, state
->nr
* 4);
444 OUT_CB_REG(R300_VAP_CLIP_CNTL
, ((1 << state
->nr
) - 1) |
445 R300_PS_UCP_MODE_CLIP_AS_TRIFAN
|
446 (state
->depth_clamp
? R300_CLIP_DISABLE
: 0));
449 r300
->clip_state
.dirty
= TRUE
;
451 draw_set_clip_state(r300
->draw
, state
);
456 r300_set_sample_mask(struct pipe_context
*pipe
,
457 unsigned sample_mask
)
462 /* Create a new depth, stencil, and alpha state based on the CSO dsa state.
464 * This contains the depth buffer, stencil buffer, alpha test, and such.
465 * On the Radeon, depth and stencil buffer setup are intertwined, which is
466 * the reason for some of the strange-looking assignments across registers. */
468 r300_create_dsa_state(struct pipe_context
* pipe
,
469 const struct pipe_depth_stencil_alpha_state
* state
)
471 struct r300_capabilities
*caps
= &r300_screen(pipe
->screen
)->caps
;
472 struct r300_dsa_state
* dsa
= CALLOC_STRUCT(r300_dsa_state
);
477 /* Depth test setup. - separate write mask depth for decomp flush */
478 if (state
->depth
.writemask
) {
479 dsa
->z_buffer_control
|= R300_Z_WRITE_ENABLE
;
482 if (state
->depth
.enabled
) {
483 dsa
->z_buffer_control
|= R300_Z_ENABLE
;
485 dsa
->z_stencil_control
|=
486 (r300_translate_depth_stencil_function(state
->depth
.func
) <<
490 /* Stencil buffer setup. */
491 if (state
->stencil
[0].enabled
) {
492 dsa
->z_buffer_control
|= R300_STENCIL_ENABLE
;
493 dsa
->z_stencil_control
|=
494 (r300_translate_depth_stencil_function(state
->stencil
[0].func
) <<
495 R300_S_FRONT_FUNC_SHIFT
) |
496 (r300_translate_stencil_op(state
->stencil
[0].fail_op
) <<
497 R300_S_FRONT_SFAIL_OP_SHIFT
) |
498 (r300_translate_stencil_op(state
->stencil
[0].zpass_op
) <<
499 R300_S_FRONT_ZPASS_OP_SHIFT
) |
500 (r300_translate_stencil_op(state
->stencil
[0].zfail_op
) <<
501 R300_S_FRONT_ZFAIL_OP_SHIFT
);
503 dsa
->stencil_ref_mask
=
504 (state
->stencil
[0].valuemask
<< R300_STENCILMASK_SHIFT
) |
505 (state
->stencil
[0].writemask
<< R300_STENCILWRITEMASK_SHIFT
);
507 if (state
->stencil
[1].enabled
) {
508 dsa
->two_sided
= TRUE
;
510 dsa
->z_buffer_control
|= R300_STENCIL_FRONT_BACK
;
511 dsa
->z_stencil_control
|=
512 (r300_translate_depth_stencil_function(state
->stencil
[1].func
) <<
513 R300_S_BACK_FUNC_SHIFT
) |
514 (r300_translate_stencil_op(state
->stencil
[1].fail_op
) <<
515 R300_S_BACK_SFAIL_OP_SHIFT
) |
516 (r300_translate_stencil_op(state
->stencil
[1].zpass_op
) <<
517 R300_S_BACK_ZPASS_OP_SHIFT
) |
518 (r300_translate_stencil_op(state
->stencil
[1].zfail_op
) <<
519 R300_S_BACK_ZFAIL_OP_SHIFT
);
521 dsa
->stencil_ref_bf
=
522 (state
->stencil
[1].valuemask
<< R300_STENCILMASK_SHIFT
) |
523 (state
->stencil
[1].writemask
<< R300_STENCILWRITEMASK_SHIFT
);
526 dsa
->z_buffer_control
|= R500_STENCIL_REFMASK_FRONT_BACK
;
528 dsa
->two_sided_stencil_ref
=
529 (state
->stencil
[0].valuemask
!= state
->stencil
[1].valuemask
||
530 state
->stencil
[0].writemask
!= state
->stencil
[1].writemask
);
535 /* Alpha test setup. */
536 if (state
->alpha
.enabled
) {
537 dsa
->alpha_function
=
538 r300_translate_alpha_function(state
->alpha
.func
) |
539 R300_FG_ALPHA_FUNC_ENABLE
;
541 /* We could use 10bit alpha ref but who needs that? */
542 dsa
->alpha_function
|= float_to_ubyte(state
->alpha
.ref_value
);
545 dsa
->alpha_function
|= R500_FG_ALPHA_FUNC_8BIT
;
548 BEGIN_CB(&dsa
->cb_begin
, 8);
549 OUT_CB_REG(R300_FG_ALPHA_FUNC
, dsa
->alpha_function
);
550 OUT_CB_REG_SEQ(R300_ZB_CNTL
, 3);
551 OUT_CB(dsa
->z_buffer_control
);
552 OUT_CB(dsa
->z_stencil_control
);
553 OUT_CB(dsa
->stencil_ref_mask
);
554 OUT_CB_REG(R500_ZB_STENCILREFMASK_BF
, dsa
->stencil_ref_bf
);
557 BEGIN_CB(dsa
->cb_no_readwrite
, 8);
558 OUT_CB_REG(R300_FG_ALPHA_FUNC
, dsa
->alpha_function
);
559 OUT_CB_REG_SEQ(R300_ZB_CNTL
, 3);
563 OUT_CB_REG(R500_ZB_STENCILREFMASK_BF
, 0);
569 static void r300_dsa_inject_stencilref(struct r300_context
*r300
)
571 struct r300_dsa_state
*dsa
=
572 (struct r300_dsa_state
*)r300
->dsa_state
.state
;
577 dsa
->stencil_ref_mask
=
578 (dsa
->stencil_ref_mask
& ~R300_STENCILREF_MASK
) |
579 r300
->stencil_ref
.ref_value
[0];
580 dsa
->stencil_ref_bf
=
581 (dsa
->stencil_ref_bf
& ~R300_STENCILREF_MASK
) |
582 r300
->stencil_ref
.ref_value
[1];
585 /* Bind DSA state. */
586 static void r300_bind_dsa_state(struct pipe_context
* pipe
,
589 struct r300_context
* r300
= r300_context(pipe
);
595 UPDATE_STATE(state
, r300
->dsa_state
);
597 r300
->hyperz_state
.dirty
= TRUE
; /* Will be updated before the emission. */
598 r300_dsa_inject_stencilref(r300
);
601 /* Free DSA state. */
602 static void r300_delete_dsa_state(struct pipe_context
* pipe
,
608 static void r300_set_stencil_ref(struct pipe_context
* pipe
,
609 const struct pipe_stencil_ref
* sr
)
611 struct r300_context
* r300
= r300_context(pipe
);
613 r300
->stencil_ref
= *sr
;
615 r300_dsa_inject_stencilref(r300
);
616 r300
->dsa_state
.dirty
= TRUE
;
619 static void r300_tex_set_tiling_flags(struct r300_context
*r300
,
620 struct r300_texture
*tex
, unsigned level
)
622 /* Check if the macrotile flag needs to be changed.
623 * Skip changing the flags otherwise. */
624 if (tex
->desc
.macrotile
[tex
->surface_level
] !=
625 tex
->desc
.macrotile
[level
]) {
626 /* Tiling determines how DRM treats the buffer data.
627 * We must flush CS when changing it if the buffer is referenced. */
628 if (r300
->rws
->cs_is_buffer_referenced(r300
->cs
,
629 tex
->buffer
, R300_REF_CS
))
630 r300
->context
.flush(&r300
->context
, 0, NULL
);
632 r300
->rws
->buffer_set_tiling(r300
->rws
, tex
->buffer
,
633 tex
->desc
.microtile
, tex
->desc
.macrotile
[level
],
634 tex
->desc
.stride_in_bytes
[0]);
636 tex
->surface_level
= level
;
640 /* This switcheroo is needed just because of goddamned MACRO_SWITCH. */
641 static void r300_fb_set_tiling_flags(struct r300_context
*r300
,
642 const struct pipe_framebuffer_state
*state
)
646 /* Set tiling flags for new surfaces. */
647 for (i
= 0; i
< state
->nr_cbufs
; i
++) {
648 r300_tex_set_tiling_flags(r300
,
649 r300_texture(state
->cbufs
[i
]->texture
),
650 state
->cbufs
[i
]->level
);
653 r300_tex_set_tiling_flags(r300
,
654 r300_texture(state
->zsbuf
->texture
),
655 state
->zsbuf
->level
);
659 static void r300_print_fb_surf_info(struct pipe_surface
*surf
, unsigned index
,
662 struct pipe_resource
*tex
= surf
->texture
;
663 struct r300_texture
*rtex
= r300_texture(tex
);
666 "r300: %s[%i] Dim: %ix%i, Offset: %i, ZSlice: %i, "
667 "Face: %i, Level: %i, Format: %s\n"
669 "r300: TEX: Macro: %s, Micro: %s, Pitch: %i, "
670 "Dim: %ix%ix%i, LastLevel: %i, Format: %s\n",
672 binding
, index
, surf
->width
, surf
->height
, surf
->offset
,
673 surf
->zslice
, surf
->face
, surf
->level
,
674 util_format_short_name(surf
->format
),
676 rtex
->desc
.macrotile
[0] ? "YES" : " NO",
677 rtex
->desc
.microtile
? "YES" : " NO",
678 rtex
->desc
.stride_in_pixels
[0],
679 tex
->width0
, tex
->height0
, tex
->depth0
,
680 tex
->last_level
, util_format_short_name(tex
->format
));
683 void r300_mark_fb_state_dirty(struct r300_context
*r300
,
684 enum r300_fb_state_change change
)
686 struct pipe_framebuffer_state
*state
= r300
->fb_state
.state
;
687 boolean can_hyperz
= r300
->rws
->get_value(r300
->rws
, R300_CAN_HYPERZ
);
689 /* What is marked as dirty depends on the enum r300_fb_state_change. */
690 r300
->gpu_flush
.dirty
= TRUE
;
691 r300
->fb_state
.dirty
= TRUE
;
692 r300
->hyperz_state
.dirty
= TRUE
;
694 if (change
== R300_CHANGED_FB_STATE
) {
695 r300
->aa_state
.dirty
= TRUE
;
696 r300
->fb_state_pipelined
.dirty
= TRUE
;
699 /* Now compute the fb_state atom size. */
700 r300
->fb_state
.size
= 2 + (8 * state
->nr_cbufs
);
702 if (r300
->cbzb_clear
)
703 r300
->fb_state
.size
+= 10;
704 else if (state
->zsbuf
) {
705 r300
->fb_state
.size
+= 10;
707 r300
->fb_state
.size
+= r300
->screen
->caps
.hiz_ram
? 8 : 4;
710 /* The size of the rest of atoms stays the same. */
714 r300_set_framebuffer_state(struct pipe_context
* pipe
,
715 const struct pipe_framebuffer_state
* state
)
717 struct r300_context
* r300
= r300_context(pipe
);
718 struct r300_aa_state
*aa
= (struct r300_aa_state
*)r300
->aa_state
.state
;
719 struct pipe_framebuffer_state
*old_state
= r300
->fb_state
.state
;
720 boolean can_hyperz
= r300
->rws
->get_value(r300
->rws
, R300_CAN_HYPERZ
);
721 unsigned max_width
, max_height
, i
;
722 uint32_t zbuffer_bpp
= 0;
725 if (r300
->screen
->caps
.is_r500
) {
726 max_width
= max_height
= 4096;
727 } else if (r300
->screen
->caps
.is_r400
) {
728 max_width
= max_height
= 4021;
730 max_width
= max_height
= 2560;
733 if (state
->width
> max_width
|| state
->height
> max_height
) {
734 fprintf(stderr
, "r300: Implementation error: Render targets are too "
735 "big in %s, refusing to bind framebuffer state!\n", __FUNCTION__
);
739 /* If nr_cbufs is changed from zero to non-zero or vice versa... */
740 if (!!old_state
->nr_cbufs
!= !!state
->nr_cbufs
) {
741 r300
->blend_state
.dirty
= TRUE
;
743 /* If zsbuf is set from NULL to non-NULL or vice versa.. */
744 if (!!old_state
->zsbuf
!= !!state
->zsbuf
) {
745 r300
->dsa_state
.dirty
= TRUE
;
748 /* The tiling flags are dependent on the surface miplevel, unfortunately. */
749 r300_fb_set_tiling_flags(r300
, state
);
751 util_copy_framebuffer_state(r300
->fb_state
.state
, state
);
753 r300_mark_fb_state_dirty(r300
, R300_CHANGED_FB_STATE
);
755 r300
->z_compression
= false;
758 blocksize
= util_format_get_blocksize(state
->zsbuf
->texture
->format
);
768 struct r300_surface
*zs_surf
= r300_surface(state
->zsbuf
);
769 struct r300_texture
*tex
;
770 int compress
= r300
->screen
->caps
.is_rv350
? RV350_Z_COMPRESS_88
: R300_Z_COMPRESS_44
;
771 int level
= zs_surf
->base
.level
;
773 tex
= r300_texture(zs_surf
->base
.texture
);
775 /* work out whether we can support hiz on this buffer */
776 r300_hiz_alloc_block(r300
, zs_surf
);
778 /* work out whether we can support zmask features on this buffer */
779 r300_zmask_alloc_block(r300
, zs_surf
, compress
);
781 if (tex
->zmask_mem
[level
]) {
782 /* compression causes hangs on 16-bit */
783 if (zbuffer_bpp
== 24)
784 r300
->z_compression
= compress
;
786 DBG(r300
, DBG_HYPERZ
,
787 "hyper-z features: hiz: %d @ %08x z-compression: %d z-fastfill: %d @ %08x\n", tex
->hiz_mem
[level
] ? 1 : 0,
788 tex
->hiz_mem
[level
] ? tex
->hiz_mem
[level
]->ofs
: 0xdeadbeef,
789 r300
->z_compression
, tex
->zmask_mem
[level
] ? 1 : 0,
790 tex
->zmask_mem
[level
] ? tex
->zmask_mem
[level
]->ofs
: 0xdeadbeef);
793 /* Polygon offset depends on the zbuffer bit depth. */
794 if (r300
->zbuffer_bpp
!= zbuffer_bpp
) {
795 r300
->zbuffer_bpp
= zbuffer_bpp
;
797 if (r300
->polygon_offset_enabled
)
798 r300
->rs_state
.dirty
= TRUE
;
802 /* Set up AA config. */
803 if (r300
->rws
->get_value(r300
->rws
, R300_VID_DRM_2_3_0
)) {
804 if (state
->nr_cbufs
&& state
->cbufs
[0]->texture
->nr_samples
> 1) {
805 aa
->aa_config
= R300_GB_AA_CONFIG_AA_ENABLE
;
807 switch (state
->cbufs
[0]->texture
->nr_samples
) {
809 aa
->aa_config
|= R300_GB_AA_CONFIG_NUM_AA_SUBSAMPLES_2
;
812 aa
->aa_config
|= R300_GB_AA_CONFIG_NUM_AA_SUBSAMPLES_3
;
815 aa
->aa_config
|= R300_GB_AA_CONFIG_NUM_AA_SUBSAMPLES_4
;
818 aa
->aa_config
|= R300_GB_AA_CONFIG_NUM_AA_SUBSAMPLES_6
;
826 if (DBG_ON(r300
, DBG_FB
)) {
827 fprintf(stderr
, "r300: set_framebuffer_state:\n");
828 for (i
= 0; i
< state
->nr_cbufs
; i
++) {
829 r300_print_fb_surf_info(state
->cbufs
[i
], i
, "CB");
832 r300_print_fb_surf_info(state
->zsbuf
, 0, "ZB");
837 /* Create fragment shader state. */
838 static void* r300_create_fs_state(struct pipe_context
* pipe
,
839 const struct pipe_shader_state
* shader
)
841 struct r300_fragment_shader
* fs
= NULL
;
843 fs
= (struct r300_fragment_shader
*)CALLOC_STRUCT(r300_fragment_shader
);
845 /* Copy state directly into shader. */
847 fs
->state
.tokens
= tgsi_dup_tokens(shader
->tokens
);
852 void r300_mark_fs_code_dirty(struct r300_context
*r300
)
854 struct r300_fragment_shader
* fs
= r300_fs(r300
);
856 r300
->fs
.dirty
= TRUE
;
857 r300
->fs_rc_constant_state
.dirty
= TRUE
;
858 r300
->fs_constants
.dirty
= TRUE
;
859 r300
->fs
.size
= fs
->shader
->cb_code_size
;
861 if (r300
->screen
->caps
.is_r500
) {
862 r300
->fs_rc_constant_state
.size
= fs
->shader
->rc_state_count
* 7;
863 r300
->fs_constants
.size
= fs
->shader
->externals_count
* 4 + 3;
865 r300
->fs_rc_constant_state
.size
= fs
->shader
->rc_state_count
* 5;
866 r300
->fs_constants
.size
= fs
->shader
->externals_count
* 4 + 1;
869 ((struct r300_constant_buffer
*)r300
->fs_constants
.state
)->remap_table
=
870 fs
->shader
->code
.constants_remap_table
;
873 /* Bind fragment shader state. */
874 static void r300_bind_fs_state(struct pipe_context
* pipe
, void* shader
)
876 struct r300_context
* r300
= r300_context(pipe
);
877 struct r300_fragment_shader
* fs
= (struct r300_fragment_shader
*)shader
;
880 r300
->fs
.state
= NULL
;
885 r300_pick_fragment_shader(r300
);
886 r300_mark_fs_code_dirty(r300
);
888 r300
->rs_block_state
.dirty
= TRUE
; /* Will be updated before the emission. */
891 /* Delete fragment shader state. */
892 static void r300_delete_fs_state(struct pipe_context
* pipe
, void* shader
)
894 struct r300_fragment_shader
* fs
= (struct r300_fragment_shader
*)shader
;
895 struct r300_fragment_shader_code
*tmp
, *ptr
= fs
->first
;
900 rc_constants_destroy(&tmp
->code
.constants
);
904 FREE((void*)fs
->state
.tokens
);
908 static void r300_set_polygon_stipple(struct pipe_context
* pipe
,
909 const struct pipe_poly_stipple
* state
)
911 /* XXX no idea how to set this up, but not terribly important */
914 /* Create a new rasterizer state based on the CSO rasterizer state.
916 * This is a very large chunk of state, and covers most of the graphics
917 * backend (GB), geometry assembly (GA), and setup unit (SU) blocks.
919 * In a not entirely unironic sidenote, this state has nearly nothing to do
920 * with the actual block on the Radeon called the rasterizer (RS). */
921 static void* r300_create_rs_state(struct pipe_context
* pipe
,
922 const struct pipe_rasterizer_state
* state
)
924 struct r300_rs_state
* rs
= CALLOC_STRUCT(r300_rs_state
);
926 uint32_t vap_control_status
; /* R300_VAP_CNTL_STATUS: 0x2140 */
927 uint32_t point_size
; /* R300_GA_POINT_SIZE: 0x421c */
928 uint32_t point_minmax
; /* R300_GA_POINT_MINMAX: 0x4230 */
929 uint32_t line_control
; /* R300_GA_LINE_CNTL: 0x4234 */
930 uint32_t polygon_offset_enable
; /* R300_SU_POLY_OFFSET_ENABLE: 0x42b4 */
931 uint32_t cull_mode
; /* R300_SU_CULL_MODE: 0x42b8 */
932 uint32_t line_stipple_config
; /* R300_GA_LINE_STIPPLE_CONFIG: 0x4328 */
933 uint32_t line_stipple_value
; /* R300_GA_LINE_STIPPLE_VALUE: 0x4260 */
934 uint32_t polygon_mode
; /* R300_GA_POLY_MODE: 0x4288 */
935 uint32_t clip_rule
; /* R300_SC_CLIP_RULE: 0x43D0 */
937 /* Point sprites texture coordinates, 0: lower left, 1: upper right */
938 float point_texcoord_left
= 0; /* R300_GA_POINT_S0: 0x4200 */
939 float point_texcoord_bottom
= 0;/* R300_GA_POINT_T0: 0x4204 */
940 float point_texcoord_right
= 1; /* R300_GA_POINT_S1: 0x4208 */
941 float point_texcoord_top
= 0; /* R300_GA_POINT_T1: 0x420c */
944 /* Copy rasterizer state. */
946 rs
->rs_draw
= *state
;
948 rs
->rs
.sprite_coord_enable
= state
->point_quad_rasterization
*
949 state
->sprite_coord_enable
;
951 /* Override some states for Draw. */
952 rs
->rs_draw
.sprite_coord_enable
= 0; /* We can do this in HW. */
954 #ifdef PIPE_ARCH_LITTLE_ENDIAN
955 vap_control_status
= R300_VC_NO_SWAP
;
957 vap_control_status
= R300_VC_32BIT_SWAP
;
960 /* If no TCL engine is present, turn off the HW TCL. */
961 if (!r300_screen(pipe
->screen
)->caps
.has_tcl
) {
962 vap_control_status
|= R300_VAP_TCL_BYPASS
;
965 /* Point size width and height. */
967 pack_float_16_6x(state
->point_size
) |
968 (pack_float_16_6x(state
->point_size
) << R300_POINTSIZE_X_SHIFT
);
970 /* Point size clamping. */
971 if (state
->point_size_per_vertex
) {
972 /* Per-vertex point size.
973 * Clamp to [0, max FB size] */
974 psiz
= pipe
->screen
->get_paramf(pipe
->screen
,
975 PIPE_CAP_MAX_POINT_WIDTH
);
977 pack_float_16_6x(psiz
) << R300_GA_POINT_MINMAX_MAX_SHIFT
;
979 /* We cannot disable the point-size vertex output,
981 psiz
= state
->point_size
;
983 (pack_float_16_6x(psiz
) << R300_GA_POINT_MINMAX_MIN_SHIFT
) |
984 (pack_float_16_6x(psiz
) << R300_GA_POINT_MINMAX_MAX_SHIFT
);
988 line_control
= pack_float_16_6x(state
->line_width
) |
989 R300_GA_LINE_CNTL_END_TYPE_COMP
;
991 /* Enable polygon mode */
993 if (state
->fill_front
!= PIPE_POLYGON_MODE_FILL
||
994 state
->fill_back
!= PIPE_POLYGON_MODE_FILL
) {
995 polygon_mode
= R300_GA_POLY_MODE_DUAL
;
999 if (state
->front_ccw
)
1000 cull_mode
= R300_FRONT_FACE_CCW
;
1002 cull_mode
= R300_FRONT_FACE_CW
;
1004 /* Polygon offset */
1005 polygon_offset_enable
= 0;
1006 if (util_get_offset(state
, state
->fill_front
)) {
1007 polygon_offset_enable
|= R300_FRONT_ENABLE
;
1009 if (util_get_offset(state
, state
->fill_back
)) {
1010 polygon_offset_enable
|= R300_BACK_ENABLE
;
1013 rs
->polygon_offset_enable
= polygon_offset_enable
!= 0;
1018 r300_translate_polygon_mode_front(state
->fill_front
);
1020 r300_translate_polygon_mode_back(state
->fill_back
);
1023 if (state
->cull_face
& PIPE_FACE_FRONT
) {
1024 cull_mode
|= R300_CULL_FRONT
;
1026 if (state
->cull_face
& PIPE_FACE_BACK
) {
1027 cull_mode
|= R300_CULL_BACK
;
1030 if (state
->line_stipple_enable
) {
1031 line_stipple_config
=
1032 R300_GA_LINE_STIPPLE_CONFIG_LINE_RESET_LINE
|
1033 (fui((float)state
->line_stipple_factor
) &
1034 R300_GA_LINE_STIPPLE_CONFIG_STIPPLE_SCALE_MASK
);
1035 /* XXX this might need to be scaled up */
1036 line_stipple_value
= state
->line_stipple_pattern
;
1038 line_stipple_config
= 0;
1039 line_stipple_value
= 0;
1042 if (state
->flatshade
) {
1043 rs
->color_control
= R300_SHADE_MODEL_FLAT
;
1045 rs
->color_control
= R300_SHADE_MODEL_SMOOTH
;
1048 clip_rule
= state
->scissor
? 0xAAAA : 0xFFFF;
1050 /* Point sprites coord mode */
1051 if (rs
->rs
.sprite_coord_enable
) {
1052 switch (state
->sprite_coord_mode
) {
1053 case PIPE_SPRITE_COORD_UPPER_LEFT
:
1054 point_texcoord_top
= 0.0f
;
1055 point_texcoord_bottom
= 1.0f
;
1057 case PIPE_SPRITE_COORD_LOWER_LEFT
:
1058 point_texcoord_top
= 1.0f
;
1059 point_texcoord_bottom
= 0.0f
;
1064 /* Build the main command buffer. */
1065 BEGIN_CB(rs
->cb_main
, RS_STATE_MAIN_SIZE
);
1066 OUT_CB_REG(R300_VAP_CNTL_STATUS
, vap_control_status
);
1067 OUT_CB_REG(R300_GA_POINT_SIZE
, point_size
);
1068 OUT_CB_REG_SEQ(R300_GA_POINT_MINMAX
, 2);
1069 OUT_CB(point_minmax
);
1070 OUT_CB(line_control
);
1071 OUT_CB_REG_SEQ(R300_SU_POLY_OFFSET_ENABLE
, 2);
1072 OUT_CB(polygon_offset_enable
);
1073 rs
->cull_mode_index
= 9;
1075 OUT_CB_REG(R300_GA_LINE_STIPPLE_CONFIG
, line_stipple_config
);
1076 OUT_CB_REG(R300_GA_LINE_STIPPLE_VALUE
, line_stipple_value
);
1077 OUT_CB_REG(R300_GA_POLY_MODE
, polygon_mode
);
1078 OUT_CB_REG(R300_SC_CLIP_RULE
, clip_rule
);
1079 OUT_CB_REG_SEQ(R300_GA_POINT_S0
, 4);
1080 OUT_CB_32F(point_texcoord_left
);
1081 OUT_CB_32F(point_texcoord_bottom
);
1082 OUT_CB_32F(point_texcoord_right
);
1083 OUT_CB_32F(point_texcoord_top
);
1086 /* Build the two command buffers for polygon offset setup. */
1087 if (polygon_offset_enable
) {
1088 float scale
= state
->offset_scale
* 12;
1089 float offset
= state
->offset_units
* 4;
1091 BEGIN_CB(rs
->cb_poly_offset_zb16
, 5);
1092 OUT_CB_REG_SEQ(R300_SU_POLY_OFFSET_FRONT_SCALE
, 4);
1099 offset
= state
->offset_units
* 2;
1101 BEGIN_CB(rs
->cb_poly_offset_zb24
, 5);
1102 OUT_CB_REG_SEQ(R300_SU_POLY_OFFSET_FRONT_SCALE
, 4);
1113 /* Bind rasterizer state. */
1114 static void r300_bind_rs_state(struct pipe_context
* pipe
, void* state
)
1116 struct r300_context
* r300
= r300_context(pipe
);
1117 struct r300_rs_state
* rs
= (struct r300_rs_state
*)state
;
1118 int last_sprite_coord_enable
= r300
->sprite_coord_enable
;
1119 boolean last_two_sided_color
= r300
->two_sided_color
;
1121 if (r300
->draw
&& rs
) {
1122 draw_set_rasterizer_state(r300
->draw
, &rs
->rs_draw
, state
);
1126 r300
->polygon_offset_enabled
= rs
->polygon_offset_enable
;
1127 r300
->sprite_coord_enable
= rs
->rs
.sprite_coord_enable
;
1128 r300
->two_sided_color
= rs
->rs
.light_twoside
;
1130 r300
->polygon_offset_enabled
= FALSE
;
1131 r300
->sprite_coord_enable
= 0;
1132 r300
->two_sided_color
= FALSE
;
1135 UPDATE_STATE(state
, r300
->rs_state
);
1136 r300
->rs_state
.size
= RS_STATE_MAIN_SIZE
+ (r300
->polygon_offset_enabled
? 5 : 0);
1138 if (last_sprite_coord_enable
!= r300
->sprite_coord_enable
||
1139 last_two_sided_color
!= r300
->two_sided_color
) {
1140 r300
->rs_block_state
.dirty
= TRUE
;
1144 /* Free rasterizer state. */
1145 static void r300_delete_rs_state(struct pipe_context
* pipe
, void* state
)
1151 r300_create_sampler_state(struct pipe_context
* pipe
,
1152 const struct pipe_sampler_state
* state
)
1154 struct r300_context
* r300
= r300_context(pipe
);
1155 struct r300_sampler_state
* sampler
= CALLOC_STRUCT(r300_sampler_state
);
1156 boolean is_r500
= r300
->screen
->caps
.is_r500
;
1159 sampler
->state
= *state
;
1161 /* r300 doesn't handle CLAMP and MIRROR_CLAMP correctly when either MAG
1162 * or MIN filter is NEAREST. Since texwrap produces same results
1163 * for CLAMP and CLAMP_TO_EDGE, we use them instead. */
1164 if (sampler
->state
.min_img_filter
== PIPE_TEX_FILTER_NEAREST
||
1165 sampler
->state
.mag_img_filter
== PIPE_TEX_FILTER_NEAREST
) {
1167 if (sampler
->state
.wrap_s
== PIPE_TEX_WRAP_CLAMP
)
1168 sampler
->state
.wrap_s
= PIPE_TEX_WRAP_CLAMP_TO_EDGE
;
1169 else if (sampler
->state
.wrap_s
== PIPE_TEX_WRAP_MIRROR_CLAMP
)
1170 sampler
->state
.wrap_s
= PIPE_TEX_WRAP_MIRROR_CLAMP_TO_EDGE
;
1173 if (sampler
->state
.wrap_t
== PIPE_TEX_WRAP_CLAMP
)
1174 sampler
->state
.wrap_t
= PIPE_TEX_WRAP_CLAMP_TO_EDGE
;
1175 else if (sampler
->state
.wrap_t
== PIPE_TEX_WRAP_MIRROR_CLAMP
)
1176 sampler
->state
.wrap_t
= PIPE_TEX_WRAP_MIRROR_CLAMP_TO_EDGE
;
1179 if (sampler
->state
.wrap_r
== PIPE_TEX_WRAP_CLAMP
)
1180 sampler
->state
.wrap_r
= PIPE_TEX_WRAP_CLAMP_TO_EDGE
;
1181 else if (sampler
->state
.wrap_r
== PIPE_TEX_WRAP_MIRROR_CLAMP
)
1182 sampler
->state
.wrap_r
= PIPE_TEX_WRAP_MIRROR_CLAMP_TO_EDGE
;
1186 (r300_translate_wrap(sampler
->state
.wrap_s
) << R300_TX_WRAP_S_SHIFT
) |
1187 (r300_translate_wrap(sampler
->state
.wrap_t
) << R300_TX_WRAP_T_SHIFT
) |
1188 (r300_translate_wrap(sampler
->state
.wrap_r
) << R300_TX_WRAP_R_SHIFT
);
1190 sampler
->filter0
|= r300_translate_tex_filters(state
->min_img_filter
,
1191 state
->mag_img_filter
,
1192 state
->min_mip_filter
,
1193 state
->max_anisotropy
> 0);
1195 sampler
->filter0
|= r300_anisotropy(state
->max_anisotropy
);
1197 /* Unfortunately, r300-r500 don't support floating-point mipmap lods. */
1198 /* We must pass these to the merge function to clamp them properly. */
1199 sampler
->min_lod
= (unsigned)MAX2(state
->min_lod
, 0);
1200 sampler
->max_lod
= (unsigned)MAX2(ceilf(state
->max_lod
), 0);
1202 lod_bias
= CLAMP((int)(state
->lod_bias
* 32 + 1), -(1 << 9), (1 << 9) - 1);
1204 sampler
->filter1
|= (lod_bias
<< R300_LOD_BIAS_SHIFT
) & R300_LOD_BIAS_MASK
;
1206 /* This is very high quality anisotropic filtering for R5xx.
1207 * It's good for benchmarking the performance of texturing but
1208 * in practice we don't want to slow down the driver because it's
1209 * a pretty good performance killer. Feel free to play with it. */
1210 if (DBG_ON(r300
, DBG_ANISOHQ
) && is_r500
) {
1211 sampler
->filter1
|= r500_anisotropy(state
->max_anisotropy
);
1214 /* R500-specific fixups and optimizations */
1215 if (r300
->screen
->caps
.is_r500
) {
1216 sampler
->filter1
|= R500_BORDER_FIX
;
1219 return (void*)sampler
;
1222 static void r300_bind_sampler_states(struct pipe_context
* pipe
,
1226 struct r300_context
* r300
= r300_context(pipe
);
1227 struct r300_textures_state
* state
=
1228 (struct r300_textures_state
*)r300
->textures_state
.state
;
1229 unsigned tex_units
= r300
->screen
->caps
.num_tex_units
;
1231 if (count
> tex_units
) {
1235 memcpy(state
->sampler_states
, states
, sizeof(void*) * count
);
1236 state
->sampler_state_count
= count
;
1238 r300
->textures_state
.dirty
= TRUE
;
1241 static void r300_lacks_vertex_textures(struct pipe_context
* pipe
,
1247 static void r300_delete_sampler_state(struct pipe_context
* pipe
, void* state
)
1252 static uint32_t r300_assign_texture_cache_region(unsigned index
, unsigned num
)
1254 /* This looks like a hack, but I believe it's suppose to work like
1255 * that. To illustrate how this works, let's assume you have 5 textures.
1256 * From docs, 5 and the successive numbers are:
1264 * First 3 textures will get 3/4 of size of the cache, divived evenly
1265 * between them. The last 1/4 of the cache must be divided between
1266 * the last 2 textures, each will therefore get 1/8 of the cache.
1267 * Why not just to use "5 + texture_index" ?
1269 * This simple trick works for all "num" <= 16.
1272 return R300_TX_CACHE(R300_TX_CACHE_WHOLE
);
1274 return R300_TX_CACHE(num
+ index
);
1277 static void r300_set_fragment_sampler_views(struct pipe_context
* pipe
,
1279 struct pipe_sampler_view
** views
)
1281 struct r300_context
* r300
= r300_context(pipe
);
1282 struct r300_textures_state
* state
=
1283 (struct r300_textures_state
*)r300
->textures_state
.state
;
1284 struct r300_texture
*texture
;
1285 unsigned i
, real_num_views
= 0, view_index
= 0;
1286 unsigned tex_units
= r300
->screen
->caps
.num_tex_units
;
1287 boolean dirty_tex
= FALSE
;
1289 if (count
> tex_units
) {
1293 /* Calculate the real number of views. */
1294 for (i
= 0; i
< count
; i
++) {
1299 for (i
= 0; i
< count
; i
++) {
1300 if (&state
->sampler_views
[i
]->base
!= views
[i
]) {
1301 pipe_sampler_view_reference(
1302 (struct pipe_sampler_view
**)&state
->sampler_views
[i
],
1309 /* A new sampler view (= texture)... */
1312 /* Set the texrect factor in the fragment shader.
1313 * Needed for RECT and NPOT fallback. */
1314 texture
= r300_texture(views
[i
]->texture
);
1315 if (texture
->desc
.is_npot
) {
1316 r300
->fs_rc_constant_state
.dirty
= TRUE
;
1319 state
->sampler_views
[i
]->texcache_region
=
1320 r300_assign_texture_cache_region(view_index
, real_num_views
);
1325 for (i
= count
; i
< tex_units
; i
++) {
1326 if (state
->sampler_views
[i
]) {
1327 pipe_sampler_view_reference(
1328 (struct pipe_sampler_view
**)&state
->sampler_views
[i
],
1333 state
->sampler_view_count
= count
;
1335 r300
->textures_state
.dirty
= TRUE
;
1338 r300
->texture_cache_inval
.dirty
= TRUE
;
1342 static struct pipe_sampler_view
*
1343 r300_create_sampler_view(struct pipe_context
*pipe
,
1344 struct pipe_resource
*texture
,
1345 const struct pipe_sampler_view
*templ
)
1347 struct r300_sampler_view
*view
= CALLOC_STRUCT(r300_sampler_view
);
1348 struct r300_texture
*tex
= r300_texture(texture
);
1349 boolean is_r500
= r300_screen(pipe
->screen
)->caps
.is_r500
;
1352 view
->base
= *templ
;
1353 view
->base
.reference
.count
= 1;
1354 view
->base
.context
= pipe
;
1355 view
->base
.texture
= NULL
;
1356 pipe_resource_reference(&view
->base
.texture
, texture
);
1358 view
->swizzle
[0] = templ
->swizzle_r
;
1359 view
->swizzle
[1] = templ
->swizzle_g
;
1360 view
->swizzle
[2] = templ
->swizzle_b
;
1361 view
->swizzle
[3] = templ
->swizzle_a
;
1363 view
->format
= tex
->tx_format
;
1364 view
->format
.format1
|= r300_translate_texformat(templ
->format
,
1368 view
->format
.format2
|= r500_tx_format_msb_bit(templ
->format
);
1372 return (struct pipe_sampler_view
*)view
;
1376 r300_sampler_view_destroy(struct pipe_context
*pipe
,
1377 struct pipe_sampler_view
*view
)
1379 pipe_resource_reference(&view
->texture
, NULL
);
1383 static void r300_set_scissor_state(struct pipe_context
* pipe
,
1384 const struct pipe_scissor_state
* state
)
1386 struct r300_context
* r300
= r300_context(pipe
);
1388 memcpy(r300
->scissor_state
.state
, state
,
1389 sizeof(struct pipe_scissor_state
));
1391 r300
->scissor_state
.dirty
= TRUE
;
1394 static void r300_set_viewport_state(struct pipe_context
* pipe
,
1395 const struct pipe_viewport_state
* state
)
1397 struct r300_context
* r300
= r300_context(pipe
);
1398 struct r300_viewport_state
* viewport
=
1399 (struct r300_viewport_state
*)r300
->viewport_state
.state
;
1401 r300
->viewport
= *state
;
1404 draw_set_viewport_state(r300
->draw
, state
);
1405 viewport
->vte_control
= R300_VTX_XY_FMT
| R300_VTX_Z_FMT
;
1409 /* Do the transform in HW. */
1410 viewport
->vte_control
= R300_VTX_W0_FMT
;
1412 if (state
->scale
[0] != 1.0f
) {
1413 viewport
->xscale
= state
->scale
[0];
1414 viewport
->vte_control
|= R300_VPORT_X_SCALE_ENA
;
1416 if (state
->scale
[1] != 1.0f
) {
1417 viewport
->yscale
= state
->scale
[1];
1418 viewport
->vte_control
|= R300_VPORT_Y_SCALE_ENA
;
1420 if (state
->scale
[2] != 1.0f
) {
1421 viewport
->zscale
= state
->scale
[2];
1422 viewport
->vte_control
|= R300_VPORT_Z_SCALE_ENA
;
1424 if (state
->translate
[0] != 0.0f
) {
1425 viewport
->xoffset
= state
->translate
[0];
1426 viewport
->vte_control
|= R300_VPORT_X_OFFSET_ENA
;
1428 if (state
->translate
[1] != 0.0f
) {
1429 viewport
->yoffset
= state
->translate
[1];
1430 viewport
->vte_control
|= R300_VPORT_Y_OFFSET_ENA
;
1432 if (state
->translate
[2] != 0.0f
) {
1433 viewport
->zoffset
= state
->translate
[2];
1434 viewport
->vte_control
|= R300_VPORT_Z_OFFSET_ENA
;
1437 r300
->viewport_state
.dirty
= TRUE
;
1438 if (r300
->fs
.state
&& r300_fs(r300
)->shader
->inputs
.wpos
!= ATTR_UNUSED
) {
1439 r300
->fs_rc_constant_state
.dirty
= TRUE
;
1443 static void r300_set_vertex_buffers(struct pipe_context
* pipe
,
1445 const struct pipe_vertex_buffer
* buffers
)
1447 struct r300_context
* r300
= r300_context(pipe
);
1448 struct pipe_vertex_buffer
*vbo
;
1449 unsigned i
, max_index
= (1 << 24) - 1;
1450 boolean any_user_buffer
= FALSE
;
1451 struct pipe_vertex_buffer dummy_vb
= {0};
1453 /* There must be at least one vertex buffer set, otherwise it locks up. */
1455 dummy_vb
.buffer
= r300
->dummy_vb
;
1456 dummy_vb
.max_index
= r300
->dummy_vb
->width0
/ 4;
1457 buffers
= &dummy_vb
;
1461 if (count
== r300
->vertex_buffer_count
&&
1462 memcmp(r300
->vertex_buffer
, buffers
,
1463 sizeof(struct pipe_vertex_buffer
) * count
) == 0) {
1467 if (r300
->screen
->caps
.has_tcl
) {
1469 r300
->incompatible_vb_layout
= FALSE
;
1471 /* Check if the strides and offsets are aligned to the size of DWORD. */
1472 for (i
= 0; i
< count
; i
++) {
1473 if (buffers
[i
].buffer
) {
1474 if (buffers
[i
].stride
% 4 != 0 ||
1475 buffers
[i
].buffer_offset
% 4 != 0) {
1476 r300
->incompatible_vb_layout
= TRUE
;
1482 for (i
= 0; i
< count
; i
++) {
1483 /* Why, yes, I AM casting away constness. How did you know? */
1484 vbo
= (struct pipe_vertex_buffer
*)&buffers
[i
];
1486 /* Skip NULL buffers */
1487 if (!buffers
[i
].buffer
) {
1491 if (r300_buffer_is_user_buffer(vbo
->buffer
)) {
1492 any_user_buffer
= TRUE
;
1495 if (vbo
->max_index
== ~0) {
1496 /* if no VBO stride then only one vertex value so max index is 1 */
1497 /* should think about converting to VS constants like svga does */
1502 (vbo
->buffer
->width0
- vbo
->buffer_offset
) / vbo
->stride
;
1505 max_index
= MIN2(vbo
->max_index
, max_index
);
1508 r300
->any_user_vbs
= any_user_buffer
;
1509 r300
->vertex_buffer_max_index
= max_index
;
1513 draw_set_vertex_buffers(r300
->draw
, count
, buffers
);
1517 for (i
= 0; i
< count
; i
++) {
1518 /* Reference our buffer. */
1519 pipe_resource_reference(&r300
->vertex_buffer
[i
].buffer
, buffers
[i
].buffer
);
1521 for (; i
< r300
->vertex_buffer_count
; i
++) {
1522 /* Dereference any old buffers. */
1523 pipe_resource_reference(&r300
->vertex_buffer
[i
].buffer
, NULL
);
1526 memcpy(r300
->vertex_buffer
, buffers
,
1527 sizeof(struct pipe_vertex_buffer
) * count
);
1528 r300
->vertex_buffer_count
= count
;
1531 static void r300_set_index_buffer(struct pipe_context
* pipe
,
1532 const struct pipe_index_buffer
*ib
)
1534 struct r300_context
* r300
= r300_context(pipe
);
1537 pipe_resource_reference(&r300
->index_buffer
.buffer
, ib
->buffer
);
1538 memcpy(&r300
->index_buffer
, ib
, sizeof(r300
->index_buffer
));
1541 pipe_resource_reference(&r300
->index_buffer
.buffer
, NULL
);
1542 memset(&r300
->index_buffer
, 0, sizeof(r300
->index_buffer
));
1545 if (r300
->screen
->caps
.has_tcl
) {
1546 /* TODO make this more like a state */
1549 draw_set_index_buffer(r300
->draw
, ib
);
1553 /* Initialize the PSC tables. */
1554 static void r300_vertex_psc(struct r300_vertex_element_state
*velems
)
1556 struct r300_vertex_stream_state
*vstream
= &velems
->vertex_stream
;
1557 uint16_t type
, swizzle
;
1558 enum pipe_format format
;
1561 if (velems
->count
> 16) {
1562 fprintf(stderr
, "r300: More than 16 vertex elements are not supported,"
1563 " requested %i, using 16.\n", velems
->count
);
1567 /* Vertex shaders have no semantics on their inputs,
1568 * so PSC should just route stuff based on the vertex elements,
1569 * and not on attrib information. */
1570 for (i
= 0; i
< velems
->count
; i
++) {
1571 format
= velems
->hw_format
[i
];
1573 type
= r300_translate_vertex_data_type(format
);
1574 if (type
== R300_INVALID_FORMAT
) {
1575 fprintf(stderr
, "r300: Bad vertex format %s.\n",
1576 util_format_short_name(format
));
1581 type
|= i
<< R300_DST_VEC_LOC_SHIFT
;
1582 swizzle
= r300_translate_vertex_data_swizzle(format
);
1585 vstream
->vap_prog_stream_cntl
[i
>> 1] |= type
<< 16;
1586 vstream
->vap_prog_stream_cntl_ext
[i
>> 1] |= swizzle
<< 16;
1588 vstream
->vap_prog_stream_cntl
[i
>> 1] |= type
;
1589 vstream
->vap_prog_stream_cntl_ext
[i
>> 1] |= swizzle
;
1593 /* Set the last vector in the PSC. */
1597 vstream
->vap_prog_stream_cntl
[i
>> 1] |=
1598 (R300_LAST_VEC
<< (i
& 1 ? 16 : 0));
1600 vstream
->count
= (i
>> 1) + 1;
1603 #define FORMAT_REPLACE(what, withwhat) \
1604 case PIPE_FORMAT_##what: *format = PIPE_FORMAT_##withwhat; break
1606 static void* r300_create_vertex_elements_state(struct pipe_context
* pipe
,
1608 const struct pipe_vertex_element
* attribs
)
1610 struct r300_vertex_element_state
*velems
;
1612 enum pipe_format
*format
;
1613 struct pipe_vertex_element dummy_attrib
= {0};
1615 /* R300 Programmable Stream Control (PSC) doesn't support 0 vertex elements. */
1617 dummy_attrib
.src_format
= PIPE_FORMAT_R8G8B8A8_UNORM
;
1618 attribs
= &dummy_attrib
;
1622 assert(count
<= PIPE_MAX_ATTRIBS
);
1623 velems
= CALLOC_STRUCT(r300_vertex_element_state
);
1624 if (velems
!= NULL
) {
1625 velems
->count
= count
;
1626 memcpy(velems
->velem
, attribs
, sizeof(struct pipe_vertex_element
) * count
);
1628 if (r300_screen(pipe
->screen
)->caps
.has_tcl
) {
1629 /* Set the best hw format in case the original format is not
1630 * supported by hw. */
1631 for (i
= 0; i
< count
; i
++) {
1632 velems
->hw_format
[i
] = velems
->velem
[i
].src_format
;
1633 format
= &velems
->hw_format
[i
];
1635 /* This is basically the list of unsupported formats.
1636 * For now we don't care about the alignment, that's going to
1637 * be sorted out after the PSC setup. */
1639 FORMAT_REPLACE(R64_FLOAT
, R32_FLOAT
);
1640 FORMAT_REPLACE(R64G64_FLOAT
, R32G32_FLOAT
);
1641 FORMAT_REPLACE(R64G64B64_FLOAT
, R32G32B32_FLOAT
);
1642 FORMAT_REPLACE(R64G64B64A64_FLOAT
, R32G32B32A32_FLOAT
);
1644 FORMAT_REPLACE(R32_UNORM
, R32_FLOAT
);
1645 FORMAT_REPLACE(R32G32_UNORM
, R32G32_FLOAT
);
1646 FORMAT_REPLACE(R32G32B32_UNORM
, R32G32B32_FLOAT
);
1647 FORMAT_REPLACE(R32G32B32A32_UNORM
, R32G32B32A32_FLOAT
);
1649 FORMAT_REPLACE(R32_USCALED
, R32_FLOAT
);
1650 FORMAT_REPLACE(R32G32_USCALED
, R32G32_FLOAT
);
1651 FORMAT_REPLACE(R32G32B32_USCALED
, R32G32B32_FLOAT
);
1652 FORMAT_REPLACE(R32G32B32A32_USCALED
,R32G32B32A32_FLOAT
);
1654 FORMAT_REPLACE(R32_SNORM
, R32_FLOAT
);
1655 FORMAT_REPLACE(R32G32_SNORM
, R32G32_FLOAT
);
1656 FORMAT_REPLACE(R32G32B32_SNORM
, R32G32B32_FLOAT
);
1657 FORMAT_REPLACE(R32G32B32A32_SNORM
, R32G32B32A32_FLOAT
);
1659 FORMAT_REPLACE(R32_SSCALED
, R32_FLOAT
);
1660 FORMAT_REPLACE(R32G32_SSCALED
, R32G32_FLOAT
);
1661 FORMAT_REPLACE(R32G32B32_SSCALED
, R32G32B32_FLOAT
);
1662 FORMAT_REPLACE(R32G32B32A32_SSCALED
,R32G32B32A32_FLOAT
);
1664 FORMAT_REPLACE(R32_FIXED
, R32_FLOAT
);
1665 FORMAT_REPLACE(R32G32_FIXED
, R32G32_FLOAT
);
1666 FORMAT_REPLACE(R32G32B32_FIXED
, R32G32B32_FLOAT
);
1667 FORMAT_REPLACE(R32G32B32A32_FIXED
, R32G32B32A32_FLOAT
);
1672 velems
->incompatible_layout
=
1673 velems
->incompatible_layout
||
1674 velems
->velem
[i
].src_format
!= velems
->hw_format
[i
] ||
1675 velems
->velem
[i
].src_offset
% 4 != 0;
1679 * The unused components will be replaced by (..., 0, 1). */
1680 r300_vertex_psc(velems
);
1682 /* Align the formats to the size of DWORD.
1683 * We only care about the blocksizes of the formats since
1684 * swizzles are already set up.
1685 * Also compute the vertex size. */
1686 for (i
= 0; i
< count
; i
++) {
1687 /* This is OK because we check for aligned strides too
1689 velems
->hw_format_size
[i
] =
1690 align(util_format_get_blocksize(velems
->hw_format
[i
]), 4);
1691 velems
->vertex_size_dwords
+= velems
->hw_format_size
[i
] / 4;
1698 static void r300_bind_vertex_elements_state(struct pipe_context
*pipe
,
1701 struct r300_context
*r300
= r300_context(pipe
);
1702 struct r300_vertex_element_state
*velems
= state
;
1704 if (velems
== NULL
) {
1708 r300
->velems
= velems
;
1711 draw_set_vertex_elements(r300
->draw
, velems
->count
, velems
->velem
);
1715 UPDATE_STATE(&velems
->vertex_stream
, r300
->vertex_stream_state
);
1716 r300
->vertex_stream_state
.size
= (1 + velems
->vertex_stream
.count
) * 2;
1719 static void r300_delete_vertex_elements_state(struct pipe_context
*pipe
, void *state
)
1724 static void* r300_create_vs_state(struct pipe_context
* pipe
,
1725 const struct pipe_shader_state
* shader
)
1727 struct r300_context
* r300
= r300_context(pipe
);
1728 struct r300_vertex_shader
* vs
= CALLOC_STRUCT(r300_vertex_shader
);
1730 /* Copy state directly into shader. */
1731 vs
->state
= *shader
;
1732 vs
->state
.tokens
= tgsi_dup_tokens(shader
->tokens
);
1734 if (r300
->screen
->caps
.has_tcl
) {
1735 r300_init_vs_outputs(vs
);
1736 r300_translate_vertex_shader(r300
, vs
);
1738 r300_draw_init_vertex_shader(r300
->draw
, vs
);
1744 static void r300_bind_vs_state(struct pipe_context
* pipe
, void* shader
)
1746 struct r300_context
* r300
= r300_context(pipe
);
1747 struct r300_vertex_shader
* vs
= (struct r300_vertex_shader
*)shader
;
1750 r300
->vs_state
.state
= NULL
;
1753 if (vs
== r300
->vs_state
.state
) {
1756 r300
->vs_state
.state
= vs
;
1758 /* The majority of the RS block bits is dependent on the vertex shader. */
1759 r300
->rs_block_state
.dirty
= TRUE
; /* Will be updated before the emission. */
1761 if (r300
->screen
->caps
.has_tcl
) {
1762 unsigned fc_op_dwords
= r300
->screen
->caps
.is_r500
? 3 : 2;
1763 r300
->vs_state
.dirty
= TRUE
;
1764 r300
->vs_state
.size
=
1765 vs
->code
.length
+ 9 +
1766 (vs
->immediates_count
? vs
->immediates_count
* 4 + 3 : 0) +
1767 (vs
->code
.num_fc_ops
? vs
->code
.num_fc_ops
* fc_op_dwords
+ 4 : 0);
1769 if (vs
->externals_count
) {
1770 r300
->vs_constants
.dirty
= TRUE
;
1771 r300
->vs_constants
.size
= vs
->externals_count
* 4 + 3;
1773 r300
->vs_constants
.size
= 0;
1776 ((struct r300_constant_buffer
*)r300
->vs_constants
.state
)->remap_table
=
1777 vs
->code
.constants_remap_table
;
1779 r300
->pvs_flush
.dirty
= TRUE
;
1781 draw_bind_vertex_shader(r300
->draw
,
1782 (struct draw_vertex_shader
*)vs
->draw_vs
);
1786 static void r300_delete_vs_state(struct pipe_context
* pipe
, void* shader
)
1788 struct r300_context
* r300
= r300_context(pipe
);
1789 struct r300_vertex_shader
* vs
= (struct r300_vertex_shader
*)shader
;
1791 if (r300
->screen
->caps
.has_tcl
) {
1792 rc_constants_destroy(&vs
->code
.constants
);
1793 if (vs
->code
.constants_remap_table
)
1794 FREE(vs
->code
.constants_remap_table
);
1796 draw_delete_vertex_shader(r300
->draw
,
1797 (struct draw_vertex_shader
*)vs
->draw_vs
);
1800 FREE((void*)vs
->state
.tokens
);
1804 static void r300_set_constant_buffer(struct pipe_context
*pipe
,
1805 uint shader
, uint index
,
1806 struct pipe_resource
*buf
)
1808 struct r300_context
* r300
= r300_context(pipe
);
1809 struct r300_constant_buffer
*cbuf
;
1813 case PIPE_SHADER_VERTEX
:
1814 cbuf
= (struct r300_constant_buffer
*)r300
->vs_constants
.state
;
1816 case PIPE_SHADER_FRAGMENT
:
1817 cbuf
= (struct r300_constant_buffer
*)r300
->fs_constants
.state
;
1824 if (buf
== NULL
|| buf
->width0
== 0 ||
1825 (mapped
= r300_buffer(buf
)->constant_buffer
) == NULL
) {
1829 if (shader
== PIPE_SHADER_FRAGMENT
||
1830 (shader
== PIPE_SHADER_VERTEX
&& r300
->screen
->caps
.has_tcl
)) {
1831 assert((buf
->width0
% (4 * sizeof(float))) == 0);
1832 cbuf
->ptr
= mapped
+ index
*4;
1835 if (shader
== PIPE_SHADER_VERTEX
) {
1836 if (r300
->screen
->caps
.has_tcl
) {
1837 if (r300
->vs_constants
.size
) {
1838 r300
->vs_constants
.dirty
= TRUE
;
1840 r300
->pvs_flush
.dirty
= TRUE
;
1841 } else if (r300
->draw
) {
1842 draw_set_mapped_constant_buffer(r300
->draw
, PIPE_SHADER_VERTEX
,
1843 0, mapped
, buf
->width0
);
1845 } else if (shader
== PIPE_SHADER_FRAGMENT
) {
1846 r300
->fs_constants
.dirty
= TRUE
;
1850 void r300_init_state_functions(struct r300_context
* r300
)
1852 r300
->context
.create_blend_state
= r300_create_blend_state
;
1853 r300
->context
.bind_blend_state
= r300_bind_blend_state
;
1854 r300
->context
.delete_blend_state
= r300_delete_blend_state
;
1856 r300
->context
.set_blend_color
= r300_set_blend_color
;
1858 r300
->context
.set_clip_state
= r300_set_clip_state
;
1859 r300
->context
.set_sample_mask
= r300_set_sample_mask
;
1861 r300
->context
.set_constant_buffer
= r300_set_constant_buffer
;
1863 r300
->context
.create_depth_stencil_alpha_state
= r300_create_dsa_state
;
1864 r300
->context
.bind_depth_stencil_alpha_state
= r300_bind_dsa_state
;
1865 r300
->context
.delete_depth_stencil_alpha_state
= r300_delete_dsa_state
;
1867 r300
->context
.set_stencil_ref
= r300_set_stencil_ref
;
1869 r300
->context
.set_framebuffer_state
= r300_set_framebuffer_state
;
1871 r300
->context
.create_fs_state
= r300_create_fs_state
;
1872 r300
->context
.bind_fs_state
= r300_bind_fs_state
;
1873 r300
->context
.delete_fs_state
= r300_delete_fs_state
;
1875 r300
->context
.set_polygon_stipple
= r300_set_polygon_stipple
;
1877 r300
->context
.create_rasterizer_state
= r300_create_rs_state
;
1878 r300
->context
.bind_rasterizer_state
= r300_bind_rs_state
;
1879 r300
->context
.delete_rasterizer_state
= r300_delete_rs_state
;
1881 r300
->context
.create_sampler_state
= r300_create_sampler_state
;
1882 r300
->context
.bind_fragment_sampler_states
= r300_bind_sampler_states
;
1883 r300
->context
.bind_vertex_sampler_states
= r300_lacks_vertex_textures
;
1884 r300
->context
.delete_sampler_state
= r300_delete_sampler_state
;
1886 r300
->context
.set_fragment_sampler_views
= r300_set_fragment_sampler_views
;
1887 r300
->context
.create_sampler_view
= r300_create_sampler_view
;
1888 r300
->context
.sampler_view_destroy
= r300_sampler_view_destroy
;
1890 r300
->context
.set_scissor_state
= r300_set_scissor_state
;
1892 r300
->context
.set_viewport_state
= r300_set_viewport_state
;
1894 r300
->context
.set_vertex_buffers
= r300_set_vertex_buffers
;
1895 r300
->context
.set_index_buffer
= r300_set_index_buffer
;
1897 r300
->context
.create_vertex_elements_state
= r300_create_vertex_elements_state
;
1898 r300
->context
.bind_vertex_elements_state
= r300_bind_vertex_elements_state
;
1899 r300
->context
.delete_vertex_elements_state
= r300_delete_vertex_elements_state
;
1901 r300
->context
.create_vs_state
= r300_create_vs_state
;
1902 r300
->context
.bind_vs_state
= r300_bind_vs_state
;
1903 r300
->context
.delete_vs_state
= r300_delete_vs_state
;