2 * Copyright 2008 Corbin Simpson <MostAwesomeDude@gmail.com>
3 * Copyright 2009 Marek Olšák <maraeo@gmail.com>
5 * Permission is hereby granted, free of charge, to any person obtaining a
6 * copy of this software and associated documentation files (the "Software"),
7 * to deal in the Software without restriction, including without limitation
8 * on the rights to use, copy, modify, merge, publish, distribute, sub
9 * license, and/or sell copies of the Software, and to permit persons to whom
10 * the Software is furnished to do so, subject to the following conditions:
12 * The above copyright notice and this permission notice (including the next
13 * paragraph) shall be included in all copies or substantial portions of the
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
19 * THE AUTHOR(S) AND/OR THEIR SUPPLIERS BE LIABLE FOR ANY CLAIM,
20 * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
21 * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
22 * USE OR OTHER DEALINGS IN THE SOFTWARE. */
24 #include "draw/draw_context.h"
26 #include "util/u_math.h"
27 #include "util/u_memory.h"
28 #include "util/u_pack_color.h"
30 #include "r300_context.h"
32 #include "r300_hyperz.h"
33 #include "r300_screen.h"
34 #include "r300_shader_semantics.h"
35 #include "r300_state_inlines.h"
36 #include "r300_texture.h"
39 /* r300_state_derived: Various bits of state which are dependent upon
40 * currently bound CSO data. */
42 enum r300_rs_swizzle
{
49 enum r300_rs_col_write_type
{
54 static void r300_draw_emit_attrib(struct r300_context
* r300
,
55 enum attrib_emit emit
,
56 enum interp_mode interp
,
59 struct r300_vertex_shader
* vs
= r300
->vs_state
.state
;
60 struct tgsi_shader_info
* info
= &vs
->info
;
63 output
= draw_find_shader_output(r300
->draw
,
64 info
->output_semantic_name
[index
],
65 info
->output_semantic_index
[index
]);
66 draw_emit_vertex_attr(&r300
->vertex_info
, emit
, interp
, output
);
69 static void r300_draw_emit_all_attribs(struct r300_context
* r300
)
71 struct r300_vertex_shader
* vs
= r300
->vs_state
.state
;
72 struct r300_shader_semantics
* vs_outputs
= &vs
->outputs
;
76 if (vs_outputs
->pos
!= ATTR_UNUSED
) {
77 r300_draw_emit_attrib(r300
, EMIT_4F
, INTERP_PERSPECTIVE
,
84 if (vs_outputs
->psize
!= ATTR_UNUSED
) {
85 r300_draw_emit_attrib(r300
, EMIT_1F_PSIZE
, INTERP_POS
,
90 for (i
= 0; i
< ATTR_COLOR_COUNT
; i
++) {
91 if (vs_outputs
->color
[i
] != ATTR_UNUSED
) {
92 r300_draw_emit_attrib(r300
, EMIT_4F
, INTERP_LINEAR
,
93 vs_outputs
->color
[i
]);
97 /* Back-face colors. */
98 for (i
= 0; i
< ATTR_COLOR_COUNT
; i
++) {
99 if (vs_outputs
->bcolor
[i
] != ATTR_UNUSED
) {
100 r300_draw_emit_attrib(r300
, EMIT_4F
, INTERP_LINEAR
,
101 vs_outputs
->bcolor
[i
]);
105 /* Texture coordinates. */
106 /* Only 8 generic vertex attributes can be used. If there are more,
107 * they won't be rasterized. */
109 for (i
= 0; i
< ATTR_GENERIC_COUNT
&& gen_count
< 8; i
++) {
110 if (vs_outputs
->generic
[i
] != ATTR_UNUSED
&&
111 !(r300
->sprite_coord_enable
& (1 << i
))) {
112 r300_draw_emit_attrib(r300
, EMIT_4F
, INTERP_PERSPECTIVE
,
113 vs_outputs
->generic
[i
]);
118 /* Fog coordinates. */
119 if (gen_count
< 8 && vs_outputs
->fog
!= ATTR_UNUSED
) {
120 r300_draw_emit_attrib(r300
, EMIT_4F
, INTERP_PERSPECTIVE
,
126 if (r300_fs(r300
)->shader
->inputs
.wpos
!= ATTR_UNUSED
&& gen_count
< 8) {
127 DBG(r300
, DBG_SWTCL
, "draw_emit_attrib: WPOS, index: %i\n",
129 r300_draw_emit_attrib(r300
, EMIT_4F
, INTERP_PERSPECTIVE
,
134 /* Update the PSC tables for SW TCL, using Draw. */
135 static void r300_swtcl_vertex_psc(struct r300_context
*r300
)
137 struct r300_vertex_stream_state
*vstream
= r300
->vertex_stream_state
.state
;
138 struct vertex_info
*vinfo
= &r300
->vertex_info
;
139 uint16_t type
, swizzle
;
140 enum pipe_format format
;
141 unsigned i
, attrib_count
;
142 int* vs_output_tab
= r300
->stream_loc_notcl
;
144 memset(vstream
, 0, sizeof(struct r300_vertex_stream_state
));
146 /* For each Draw attribute, route it to the fragment shader according
147 * to the vs_output_tab. */
148 attrib_count
= vinfo
->num_attribs
;
149 DBG(r300
, DBG_SWTCL
, "r300: attrib count: %d\n", attrib_count
);
150 for (i
= 0; i
< attrib_count
; i
++) {
151 if (vs_output_tab
[i
] == -1) {
156 format
= draw_translate_vinfo_format(vinfo
->attrib
[i
].emit
);
159 "r300: swtcl_vertex_psc [%i] <- %s\n",
160 vs_output_tab
[i
], util_format_short_name(format
));
162 /* Obtain the type of data in this attribute. */
163 type
= r300_translate_vertex_data_type(format
);
164 if (type
== R300_INVALID_FORMAT
) {
165 fprintf(stderr
, "r300: Bad vertex format %s.\n",
166 util_format_short_name(format
));
171 type
|= vs_output_tab
[i
] << R300_DST_VEC_LOC_SHIFT
;
173 /* Obtain the swizzle for this attribute. Note that the default
174 * swizzle in the hardware is not XYZW! */
175 swizzle
= r300_translate_vertex_data_swizzle(format
);
177 /* Add the attribute to the PSC table. */
179 vstream
->vap_prog_stream_cntl
[i
>> 1] |= type
<< 16;
180 vstream
->vap_prog_stream_cntl_ext
[i
>> 1] |= swizzle
<< 16;
182 vstream
->vap_prog_stream_cntl
[i
>> 1] |= type
;
183 vstream
->vap_prog_stream_cntl_ext
[i
>> 1] |= swizzle
;
187 /* Set the last vector in the PSC. */
191 vstream
->vap_prog_stream_cntl
[i
>> 1] |=
192 (R300_LAST_VEC
<< (i
& 1 ? 16 : 0));
194 vstream
->count
= (i
>> 1) + 1;
195 r300_mark_atom_dirty(r300
, &r300
->vertex_stream_state
);
196 r300
->vertex_stream_state
.size
= (1 + vstream
->count
) * 2;
199 static void r300_rs_col(struct r300_rs_block
* rs
, int id
, int ptr
,
200 enum r300_rs_swizzle swiz
)
202 rs
->ip
[id
] |= R300_RS_COL_PTR(ptr
);
203 if (swiz
== SWIZ_0001
) {
204 rs
->ip
[id
] |= R300_RS_COL_FMT(R300_RS_COL_FMT_0001
);
206 rs
->ip
[id
] |= R300_RS_COL_FMT(R300_RS_COL_FMT_RGBA
);
208 rs
->inst
[id
] |= R300_RS_INST_COL_ID(id
);
211 static void r300_rs_col_write(struct r300_rs_block
* rs
, int id
, int fp_offset
,
212 enum r300_rs_col_write_type type
)
214 assert(type
== WRITE_COLOR
);
215 rs
->inst
[id
] |= R300_RS_INST_COL_CN_WRITE
|
216 R300_RS_INST_COL_ADDR(fp_offset
);
219 static void r300_rs_tex(struct r300_rs_block
* rs
, int id
, int ptr
,
220 enum r300_rs_swizzle swiz
)
222 if (swiz
== SWIZ_X001
) {
223 rs
->ip
[id
] |= R300_RS_TEX_PTR(ptr
) |
224 R300_RS_SEL_S(R300_RS_SEL_C0
) |
225 R300_RS_SEL_T(R300_RS_SEL_K0
) |
226 R300_RS_SEL_R(R300_RS_SEL_K0
) |
227 R300_RS_SEL_Q(R300_RS_SEL_K1
);
228 } else if (swiz
== SWIZ_XY01
) {
229 rs
->ip
[id
] |= R300_RS_TEX_PTR(ptr
) |
230 R300_RS_SEL_S(R300_RS_SEL_C0
) |
231 R300_RS_SEL_T(R300_RS_SEL_C1
) |
232 R300_RS_SEL_R(R300_RS_SEL_K0
) |
233 R300_RS_SEL_Q(R300_RS_SEL_K1
);
235 rs
->ip
[id
] |= R300_RS_TEX_PTR(ptr
) |
236 R300_RS_SEL_S(R300_RS_SEL_C0
) |
237 R300_RS_SEL_T(R300_RS_SEL_C1
) |
238 R300_RS_SEL_R(R300_RS_SEL_C2
) |
239 R300_RS_SEL_Q(R300_RS_SEL_C3
);
241 rs
->inst
[id
] |= R300_RS_INST_TEX_ID(id
);
244 static void r300_rs_tex_write(struct r300_rs_block
* rs
, int id
, int fp_offset
)
246 rs
->inst
[id
] |= R300_RS_INST_TEX_CN_WRITE
|
247 R300_RS_INST_TEX_ADDR(fp_offset
);
250 static void r500_rs_col(struct r300_rs_block
* rs
, int id
, int ptr
,
251 enum r300_rs_swizzle swiz
)
253 rs
->ip
[id
] |= R500_RS_COL_PTR(ptr
);
254 if (swiz
== SWIZ_0001
) {
255 rs
->ip
[id
] |= R500_RS_COL_FMT(R300_RS_COL_FMT_0001
);
257 rs
->ip
[id
] |= R500_RS_COL_FMT(R300_RS_COL_FMT_RGBA
);
259 rs
->inst
[id
] |= R500_RS_INST_COL_ID(id
);
262 static void r500_rs_col_write(struct r300_rs_block
* rs
, int id
, int fp_offset
,
263 enum r300_rs_col_write_type type
)
265 if (type
== WRITE_FACE
)
266 rs
->inst
[id
] |= R500_RS_INST_COL_CN_WRITE_BACKFACE
|
267 R500_RS_INST_COL_ADDR(fp_offset
);
269 rs
->inst
[id
] |= R500_RS_INST_COL_CN_WRITE
|
270 R500_RS_INST_COL_ADDR(fp_offset
);
274 static void r500_rs_tex(struct r300_rs_block
* rs
, int id
, int ptr
,
275 enum r300_rs_swizzle swiz
)
277 if (swiz
== SWIZ_X001
) {
278 rs
->ip
[id
] |= R500_RS_SEL_S(ptr
) |
279 R500_RS_SEL_T(R500_RS_IP_PTR_K0
) |
280 R500_RS_SEL_R(R500_RS_IP_PTR_K0
) |
281 R500_RS_SEL_Q(R500_RS_IP_PTR_K1
);
282 } else if (swiz
== SWIZ_XY01
) {
283 rs
->ip
[id
] |= R500_RS_SEL_S(ptr
) |
284 R500_RS_SEL_T(ptr
+ 1) |
285 R500_RS_SEL_R(R500_RS_IP_PTR_K0
) |
286 R500_RS_SEL_Q(R500_RS_IP_PTR_K1
);
288 rs
->ip
[id
] |= R500_RS_SEL_S(ptr
) |
289 R500_RS_SEL_T(ptr
+ 1) |
290 R500_RS_SEL_R(ptr
+ 2) |
291 R500_RS_SEL_Q(ptr
+ 3);
293 rs
->inst
[id
] |= R500_RS_INST_TEX_ID(id
);
296 static void r500_rs_tex_write(struct r300_rs_block
* rs
, int id
, int fp_offset
)
298 rs
->inst
[id
] |= R500_RS_INST_TEX_CN_WRITE
|
299 R500_RS_INST_TEX_ADDR(fp_offset
);
302 /* Set up the RS block.
304 * This is the part of the chipset that is responsible for linking vertex
305 * and fragment shaders and stuffed texture coordinates.
307 * The rasterizer reads data from VAP, which produces vertex shader outputs,
308 * and GA, which produces stuffed texture coordinates. VAP outputs have
309 * precedence over GA. All outputs must be rasterized otherwise it locks up.
310 * If there are more outputs rasterized than is set in VAP/GA, it locks up
311 * too. The funky part is that this info has been pretty much obtained by trial
313 static void r300_update_rs_block(struct r300_context
*r300
)
315 struct r300_vertex_shader
*vs
= r300
->vs_state
.state
;
316 struct r300_shader_semantics
*vs_outputs
= &vs
->outputs
;
317 struct r300_shader_semantics
*fs_inputs
= &r300_fs(r300
)->shader
->inputs
;
318 struct r300_rs_block rs
= {0};
319 int i
, col_count
= 0, tex_count
= 0, fp_offset
= 0, count
, loc
= 0, tex_ptr
= 0;
320 void (*rX00_rs_col
)(struct r300_rs_block
*, int, int, enum r300_rs_swizzle
);
321 void (*rX00_rs_col_write
)(struct r300_rs_block
*, int, int, enum r300_rs_col_write_type
);
322 void (*rX00_rs_tex
)(struct r300_rs_block
*, int, int, enum r300_rs_swizzle
);
323 void (*rX00_rs_tex_write
)(struct r300_rs_block
*, int, int);
324 boolean any_bcolor_used
= vs_outputs
->bcolor
[0] != ATTR_UNUSED
||
325 vs_outputs
->bcolor
[1] != ATTR_UNUSED
;
326 int *stream_loc_notcl
= r300
->stream_loc_notcl
;
327 uint32_t stuffing_enable
= 0;
329 if (r300
->screen
->caps
.is_r500
) {
330 rX00_rs_col
= r500_rs_col
;
331 rX00_rs_col_write
= r500_rs_col_write
;
332 rX00_rs_tex
= r500_rs_tex
;
333 rX00_rs_tex_write
= r500_rs_tex_write
;
335 rX00_rs_col
= r300_rs_col
;
336 rX00_rs_col_write
= r300_rs_col_write
;
337 rX00_rs_tex
= r300_rs_tex
;
338 rX00_rs_tex_write
= r300_rs_tex_write
;
341 /* 0x5555 copied from classic, which means:
342 * Select user color 0 for COLOR0 up to COLOR7.
343 * What the hell does that mean? */
344 rs
.vap_vtx_state_cntl
= 0x5555;
346 /* The position is always present in VAP. */
347 rs
.vap_vsm_vtx_assm
|= R300_INPUT_CNTL_POS
;
348 rs
.vap_out_vtx_fmt
[0] |= R300_VAP_OUTPUT_VTX_FMT_0__POS_PRESENT
;
349 stream_loc_notcl
[loc
++] = 0;
351 /* Set up the point size in VAP. */
352 if (vs_outputs
->psize
!= ATTR_UNUSED
) {
353 rs
.vap_out_vtx_fmt
[0] |= R300_VAP_OUTPUT_VTX_FMT_0__PT_SIZE_PRESENT
;
354 stream_loc_notcl
[loc
++] = 1;
357 /* Set up and rasterize colors. */
358 for (i
= 0; i
< ATTR_COLOR_COUNT
; i
++) {
359 if (vs_outputs
->color
[i
] != ATTR_UNUSED
|| any_bcolor_used
||
360 vs_outputs
->color
[1] != ATTR_UNUSED
) {
361 /* Set up the color in VAP. */
362 rs
.vap_vsm_vtx_assm
|= R300_INPUT_CNTL_COLOR
;
363 rs
.vap_out_vtx_fmt
[0] |=
364 R300_VAP_OUTPUT_VTX_FMT_0__COLOR_0_PRESENT
<< i
;
365 stream_loc_notcl
[loc
++] = 2 + i
;
368 rX00_rs_col(&rs
, col_count
, col_count
, SWIZ_XYZW
);
370 /* Write it to the FS input register if it's needed by the FS. */
371 if (fs_inputs
->color
[i
] != ATTR_UNUSED
) {
372 rX00_rs_col_write(&rs
, col_count
, fp_offset
, WRITE_COLOR
);
376 "r300: Rasterized color %i written to FS.\n", i
);
378 DBG(r300
, DBG_RS
, "r300: Rasterized color %i unused.\n", i
);
382 /* Skip the FS input register, leave it uninitialized. */
383 /* If we try to set it to (0,0,0,1), it will lock up. */
384 if (fs_inputs
->color
[i
] != ATTR_UNUSED
) {
387 DBG(r300
, DBG_RS
, "r300: FS input color %i unassigned%s.\n",
393 /* Set up back-face colors. The rasterizer will do the color selection
395 if (any_bcolor_used
) {
396 if (r300
->two_sided_color
) {
397 /* Rasterize as back-face colors. */
398 for (i
= 0; i
< ATTR_COLOR_COUNT
; i
++) {
399 rs
.vap_vsm_vtx_assm
|= R300_INPUT_CNTL_COLOR
;
400 rs
.vap_out_vtx_fmt
[0] |= R300_VAP_OUTPUT_VTX_FMT_0__COLOR_0_PRESENT
<< (2+i
);
401 stream_loc_notcl
[loc
++] = 4 + i
;
404 /* Rasterize two fake texcoords to prevent from the two-sided color
406 /* XXX Consider recompiling the vertex shader to save 2 RS units. */
407 for (i
= 0; i
< 2; i
++) {
408 rs
.vap_vsm_vtx_assm
|= (R300_INPUT_CNTL_TC0
<< tex_count
);
409 rs
.vap_out_vtx_fmt
[1] |= (4 << (3 * tex_count
));
410 stream_loc_notcl
[loc
++] = 6 + tex_count
;
413 rX00_rs_tex(&rs
, tex_count
, tex_ptr
, SWIZ_XYZW
);
421 * Note that we can use either the two-sided color selection based on
422 * the front and back vertex shader colors, or gl_FrontFacing,
423 * but not both! It locks up otherwise.
425 * In Direct3D 9, the two-sided color selection can be used
426 * with shaders 2.0 only, while gl_FrontFacing can be used
427 * with shaders 3.0 only. The hardware apparently hasn't been designed
428 * to support both at the same time. */
429 if (r300
->screen
->caps
.is_r500
&& fs_inputs
->face
!= ATTR_UNUSED
&&
430 !(any_bcolor_used
&& r300
->two_sided_color
)) {
431 rX00_rs_col(&rs
, col_count
, col_count
, SWIZ_XYZW
);
432 rX00_rs_col_write(&rs
, col_count
, fp_offset
, WRITE_FACE
);
435 DBG(r300
, DBG_RS
, "r300: Rasterized FACE written to FS.\n");
436 } else if (fs_inputs
->face
!= ATTR_UNUSED
) {
437 fprintf(stderr
, "r300: ERROR: FS input FACE unassigned.\n");
440 /* Rasterize texture coordinates. */
441 for (i
= 0; i
< ATTR_GENERIC_COUNT
&& tex_count
< 8; i
++) {
442 bool sprite_coord
= false;
444 if (fs_inputs
->generic
[i
] != ATTR_UNUSED
) {
445 sprite_coord
= !!(r300
->sprite_coord_enable
& (1 << i
));
448 if (vs_outputs
->generic
[i
] != ATTR_UNUSED
|| sprite_coord
) {
450 /* Set up the texture coordinates in VAP. */
451 rs
.vap_vsm_vtx_assm
|= (R300_INPUT_CNTL_TC0
<< tex_count
);
452 rs
.vap_out_vtx_fmt
[1] |= (4 << (3 * tex_count
));
453 stream_loc_notcl
[loc
++] = 6 + tex_count
;
456 R300_GB_TEX_ST
<< (R300_GB_TEX0_SOURCE_SHIFT
+ (tex_count
*2));
459 rX00_rs_tex(&rs
, tex_count
, tex_ptr
,
460 sprite_coord
? SWIZ_XY01
: SWIZ_XYZW
);
462 /* Write it to the FS input register if it's needed by the FS. */
463 if (fs_inputs
->generic
[i
] != ATTR_UNUSED
) {
464 rX00_rs_tex_write(&rs
, tex_count
, fp_offset
);
468 "r300: Rasterized generic %i written to FS%s in texcoord %d.\n",
469 i
, sprite_coord
? " (sprite coord)" : "", tex_count
);
472 "r300: Rasterized generic %i unused%s.\n",
473 i
, sprite_coord
? " (sprite coord)" : "");
476 tex_ptr
+= sprite_coord
? 2 : 4;
478 /* Skip the FS input register, leave it uninitialized. */
479 /* If we try to set it to (0,0,0,1), it will lock up. */
480 if (fs_inputs
->generic
[i
] != ATTR_UNUSED
) {
483 DBG(r300
, DBG_RS
, "r300: FS input generic %i unassigned%s.\n",
484 i
, sprite_coord
? " (sprite coord)" : "");
489 for (; i
< ATTR_GENERIC_COUNT
; i
++) {
490 if (fs_inputs
->generic
[i
] != ATTR_UNUSED
) {
491 fprintf(stderr
, "r300: ERROR: FS input generic %i unassigned, "
492 "not enough hardware slots.\n", i
);
496 /* Rasterize fog coordinates. */
497 if (vs_outputs
->fog
!= ATTR_UNUSED
&& tex_count
< 8) {
498 /* Set up the fog coordinates in VAP. */
499 rs
.vap_vsm_vtx_assm
|= (R300_INPUT_CNTL_TC0
<< tex_count
);
500 rs
.vap_out_vtx_fmt
[1] |= (4 << (3 * tex_count
));
501 stream_loc_notcl
[loc
++] = 6 + tex_count
;
504 rX00_rs_tex(&rs
, tex_count
, tex_ptr
, SWIZ_X001
);
506 /* Write it to the FS input register if it's needed by the FS. */
507 if (fs_inputs
->fog
!= ATTR_UNUSED
) {
508 rX00_rs_tex_write(&rs
, tex_count
, fp_offset
);
511 DBG(r300
, DBG_RS
, "r300: Rasterized fog written to FS.\n");
513 DBG(r300
, DBG_RS
, "r300: Rasterized fog unused.\n");
518 /* Skip the FS input register, leave it uninitialized. */
519 /* If we try to set it to (0,0,0,1), it will lock up. */
520 if (fs_inputs
->fog
!= ATTR_UNUSED
) {
524 DBG(r300
, DBG_RS
, "r300: FS input fog unassigned.\n");
526 fprintf(stderr
, "r300: ERROR: FS input fog unassigned, "
527 "not enough hardware slots.\n");
532 /* Rasterize WPOS. */
533 /* Don't set it in VAP if the FS doesn't need it. */
534 if (fs_inputs
->wpos
!= ATTR_UNUSED
&& tex_count
< 8) {
535 /* Set up the WPOS coordinates in VAP. */
536 rs
.vap_vsm_vtx_assm
|= (R300_INPUT_CNTL_TC0
<< tex_count
);
537 rs
.vap_out_vtx_fmt
[1] |= (4 << (3 * tex_count
));
538 stream_loc_notcl
[loc
++] = 6 + tex_count
;
541 rX00_rs_tex(&rs
, tex_count
, tex_ptr
, SWIZ_XYZW
);
543 /* Write it to the FS input register. */
544 rX00_rs_tex_write(&rs
, tex_count
, fp_offset
);
546 DBG(r300
, DBG_RS
, "r300: Rasterized WPOS written to FS.\n");
552 if (fs_inputs
->wpos
!= ATTR_UNUSED
&& tex_count
>= 8) {
553 fprintf(stderr
, "r300: ERROR: FS input WPOS unassigned, "
554 "not enough hardware slots.\n");
558 /* Invalidate the rest of the no-TCL (GA) stream locations. */
560 stream_loc_notcl
[loc
++] = -1;
563 /* Rasterize at least one color, or bad things happen. */
564 if (col_count
== 0 && tex_count
== 0) {
565 rX00_rs_col(&rs
, 0, 0, SWIZ_0001
);
568 DBG(r300
, DBG_RS
, "r300: Rasterized color 0 to prevent lockups.\n");
571 DBG(r300
, DBG_RS
, "r300: --- Rasterizer status ---: colors: %i, "
572 "generics: %i.\n", col_count
, tex_count
);
574 rs
.count
= MIN2(tex_ptr
, 32) | (col_count
<< R300_IC_COUNT_SHIFT
) |
577 count
= MAX3(col_count
, tex_count
, 1);
578 rs
.inst_count
= count
- 1;
580 /* set the GB enable flags */
581 if (r300
->sprite_coord_enable
)
582 stuffing_enable
|= R300_GB_POINT_STUFF_ENABLE
;
584 rs
.gb_enable
= stuffing_enable
;
586 /* Now, after all that, see if we actually need to update the state. */
587 if (memcmp(r300
->rs_block_state
.state
, &rs
, sizeof(struct r300_rs_block
))) {
588 memcpy(r300
->rs_block_state
.state
, &rs
, sizeof(struct r300_rs_block
));
589 r300
->rs_block_state
.size
= 13 + count
*2;
593 static uint32_t r300_get_border_color(enum pipe_format format
,
594 const float border
[4],
597 const struct util_format_description
*desc
;
598 float border_swizzled
[4] = {0};
600 union util_color uc
= {0};
602 desc
= util_format_description(format
);
604 /* Do depth formats first. */
605 if (util_format_is_depth_or_stencil(format
)) {
607 case PIPE_FORMAT_Z16_UNORM
:
608 return util_pack_z(PIPE_FORMAT_Z16_UNORM
, border
[0]);
609 case PIPE_FORMAT_X8Z24_UNORM
:
610 case PIPE_FORMAT_S8_USCALED_Z24_UNORM
:
612 return util_pack_z(PIPE_FORMAT_X8Z24_UNORM
, border
[0]);
614 return util_pack_z(PIPE_FORMAT_Z16_UNORM
, border
[0]) << 16;
622 /* Apply inverse swizzle of the format. */
623 for (i
= 0; i
< 4; i
++) {
624 switch (desc
->swizzle
[i
]) {
625 case UTIL_FORMAT_SWIZZLE_X
:
626 border_swizzled
[2] = border
[i
];
628 case UTIL_FORMAT_SWIZZLE_Y
:
629 border_swizzled
[1] = border
[i
];
631 case UTIL_FORMAT_SWIZZLE_Z
:
632 border_swizzled
[0] = border
[i
];
634 case UTIL_FORMAT_SWIZZLE_W
:
635 border_swizzled
[3] = border
[i
];
640 /* Compressed formats. */
641 if (util_format_is_compressed(format
)) {
642 util_pack_color(border_swizzled
, PIPE_FORMAT_R8G8B8A8_UNORM
, &uc
);
646 switch (desc
->channel
[0].size
) {
648 util_pack_color(border_swizzled
, PIPE_FORMAT_B2G3R3_UNORM
, &uc
);
652 util_pack_color(border_swizzled
, PIPE_FORMAT_B4G4R4A4_UNORM
, &uc
);
656 if (desc
->channel
[1].size
== 5) {
657 util_pack_color(border_swizzled
, PIPE_FORMAT_B5G5R5A1_UNORM
, &uc
);
658 } else if (desc
->channel
[1].size
== 6) {
659 util_pack_color(border_swizzled
, PIPE_FORMAT_B5G6R5_UNORM
, &uc
);
667 util_pack_color(border_swizzled
, PIPE_FORMAT_B8G8R8A8_UNORM
, &uc
);
671 util_pack_color(border_swizzled
, PIPE_FORMAT_B10G10R10A2_UNORM
, &uc
);
675 if (desc
->nr_channels
<= 2) {
676 border_swizzled
[0] = border_swizzled
[2];
677 util_pack_color(border_swizzled
, PIPE_FORMAT_R16G16_UNORM
, &uc
);
679 util_pack_color(border_swizzled
, PIPE_FORMAT_B8G8R8A8_UNORM
, &uc
);
687 static void r300_merge_textures_and_samplers(struct r300_context
* r300
)
689 struct r300_textures_state
*state
=
690 (struct r300_textures_state
*)r300
->textures_state
.state
;
691 struct r300_texture_sampler_state
*texstate
;
692 struct r300_sampler_state
*sampler
;
693 struct r300_sampler_view
*view
;
694 struct r300_resource
*tex
;
695 unsigned min_level
, max_level
, i
, j
, size
;
696 unsigned count
= MIN2(state
->sampler_view_count
,
697 state
->sampler_state_count
);
699 /* The KIL opcode fix, see below. */
700 if (!count
&& !r300
->screen
->caps
.is_r500
)
703 state
->tx_enable
= 0;
707 for (i
= 0; i
< count
; i
++) {
708 if (state
->sampler_views
[i
] && state
->sampler_states
[i
]) {
709 state
->tx_enable
|= 1 << i
;
711 view
= state
->sampler_views
[i
];
712 tex
= r300_resource(view
->base
.texture
);
713 sampler
= state
->sampler_states
[i
];
715 texstate
= &state
->regs
[i
];
716 texstate
->format
= view
->format
;
717 texstate
->filter0
= sampler
->filter0
;
718 texstate
->filter1
= sampler
->filter1
;
720 /* Set the border color. */
721 texstate
->border_color
=
722 r300_get_border_color(view
->base
.format
,
723 sampler
->state
.border_color
,
724 r300
->screen
->caps
.is_r500
);
726 /* determine min/max levels */
727 max_level
= MIN3(sampler
->max_lod
+ view
->base
.u
.tex
.first_level
,
728 tex
->b
.b
.b
.last_level
, view
->base
.u
.tex
.last_level
);
729 min_level
= MIN2(sampler
->min_lod
+ view
->base
.u
.tex
.first_level
,
732 if (tex
->tex
.is_npot
&& min_level
> 0) {
733 /* Even though we do not implement mipmapping for NPOT
734 * textures, we should at least honor the minimum level
735 * which is allowed to be displayed. We do this by setting up
736 * an i-th mipmap level as the zero level. */
737 r300_texture_setup_format_state(r300
->screen
, tex
,
740 texstate
->format
.tile_config
|=
741 tex
->tex
.offset_in_bytes
[min_level
] & 0xffffffe0;
742 assert((tex
->tex
.offset_in_bytes
[min_level
] & 0x1f) == 0);
745 /* Assign a texture cache region. */
746 texstate
->format
.format1
|= view
->texcache_region
;
748 /* Depth textures are kinda special. */
749 if (util_format_is_depth_or_stencil(tex
->b
.b
.b
.format
)) {
750 unsigned char depth_swizzle
[4];
752 if (!r300
->screen
->caps
.is_r500
&&
753 util_format_get_blocksizebits(tex
->b
.b
.b
.format
) == 32) {
754 /* X24x8 is sampled as Y16X16 on r3xx-r4xx.
755 * The depth here is at the Y component. */
756 for (j
= 0; j
< 4; j
++)
757 depth_swizzle
[j
] = UTIL_FORMAT_SWIZZLE_Y
;
759 for (j
= 0; j
< 4; j
++)
760 depth_swizzle
[j
] = UTIL_FORMAT_SWIZZLE_X
;
763 /* If compare mode is disabled, sampler view swizzles
764 * are stored in the format.
765 * Otherwise, the swizzles must be applied after the compare
766 * mode in the fragment shader. */
767 if (sampler
->state
.compare_mode
== PIPE_TEX_COMPARE_NONE
) {
768 texstate
->format
.format1
|=
769 r300_get_swizzle_combined(depth_swizzle
,
770 view
->swizzle
, FALSE
);
772 texstate
->format
.format1
|=
773 r300_get_swizzle_combined(depth_swizzle
, 0, FALSE
);
777 if (r300
->screen
->caps
.dxtc_swizzle
&&
778 util_format_is_compressed(tex
->b
.b
.b
.format
)) {
779 texstate
->filter1
|= R400_DXTC_SWIZZLE_ENABLE
;
782 /* to emulate 1D textures through 2D ones correctly */
783 if (tex
->b
.b
.b
.target
== PIPE_TEXTURE_1D
) {
784 texstate
->filter0
&= ~R300_TX_WRAP_T_MASK
;
785 texstate
->filter0
|= R300_TX_WRAP_T(R300_TX_CLAMP_TO_EDGE
);
788 if (tex
->tex
.is_npot
) {
789 /* NPOT textures don't support mip filter, unfortunately.
790 * This prevents incorrect rendering. */
791 texstate
->filter0
&= ~R300_TX_MIN_FILTER_MIP_MASK
;
793 /* Mask out the mirrored flag. */
794 if (texstate
->filter0
& R300_TX_WRAP_S(R300_TX_MIRRORED
)) {
795 texstate
->filter0
&= ~R300_TX_WRAP_S(R300_TX_MIRRORED
);
797 if (texstate
->filter0
& R300_TX_WRAP_T(R300_TX_MIRRORED
)) {
798 texstate
->filter0
&= ~R300_TX_WRAP_T(R300_TX_MIRRORED
);
801 /* Change repeat to clamp-to-edge.
802 * (the repeat bit has a value of 0, no masking needed). */
803 if ((texstate
->filter0
& R300_TX_WRAP_S_MASK
) ==
804 R300_TX_WRAP_S(R300_TX_REPEAT
)) {
805 texstate
->filter0
|= R300_TX_WRAP_S(R300_TX_CLAMP_TO_EDGE
);
807 if ((texstate
->filter0
& R300_TX_WRAP_T_MASK
) ==
808 R300_TX_WRAP_T(R300_TX_REPEAT
)) {
809 texstate
->filter0
|= R300_TX_WRAP_T(R300_TX_CLAMP_TO_EDGE
);
812 /* the MAX_MIP level is the largest (finest) one */
813 texstate
->format
.format0
|= R300_TX_NUM_LEVELS(max_level
);
814 texstate
->filter0
|= R300_TX_MAX_MIP_LEVEL(min_level
);
817 texstate
->filter0
|= i
<< 28;
822 /* For the KIL opcode to work on r3xx-r4xx, the texture unit
823 * assigned to this opcode (it's always the first one) must be
824 * enabled. Otherwise the opcode doesn't work.
826 * In order to not depend on the fragment shader, we just make
827 * the first unit enabled all the time. */
828 if (i
== 0 && !r300
->screen
->caps
.is_r500
) {
829 pipe_sampler_view_reference(
830 (struct pipe_sampler_view
**)&state
->sampler_views
[i
],
831 &r300
->texkill_sampler
->base
);
833 state
->tx_enable
|= 1 << i
;
835 texstate
= &state
->regs
[i
];
837 /* Just set some valid state. */
838 texstate
->format
= r300
->texkill_sampler
->format
;
840 r300_translate_tex_filters(PIPE_TEX_FILTER_NEAREST
,
841 PIPE_TEX_FILTER_NEAREST
,
842 PIPE_TEX_FILTER_NEAREST
,
844 texstate
->filter1
= 0;
845 texstate
->border_color
= 0;
847 texstate
->filter0
|= i
<< 28;
854 r300
->textures_state
.size
= size
;
856 /* Pick a fragment shader based on either the texture compare state
857 * or the uses_pitch flag. */
858 if (r300
->fs
.state
&& count
) {
859 if (r300_pick_fragment_shader(r300
)) {
860 r300_mark_fs_code_dirty(r300
);
865 static void r300_decompress_depth_textures(struct r300_context
*r300
)
867 struct r300_textures_state
*state
=
868 (struct r300_textures_state
*)r300
->textures_state
.state
;
869 struct pipe_resource
*tex
;
870 unsigned count
= MIN2(state
->sampler_view_count
,
871 state
->sampler_state_count
);
874 if (!r300
->zmask_locked
|| !r300
->locked_zbuffer
) {
878 for (i
= 0; i
< count
; i
++) {
879 if (state
->sampler_views
[i
] && state
->sampler_states
[i
]) {
880 tex
= state
->sampler_views
[i
]->base
.texture
;
882 if (tex
== r300
->locked_zbuffer
->texture
) {
883 r300_decompress_zmask_locked(r300
);
890 void r300_update_derived_state(struct r300_context
* r300
)
892 if (r300
->textures_state
.dirty
) {
893 r300_decompress_depth_textures(r300
);
894 r300_merge_textures_and_samplers(r300
);
897 if (r300
->rs_block_state
.dirty
) {
898 r300_update_rs_block(r300
);
901 memset(&r300
->vertex_info
, 0, sizeof(struct vertex_info
));
902 r300_draw_emit_all_attribs(r300
);
903 draw_compute_vertex_size(&r300
->vertex_info
);
904 r300_swtcl_vertex_psc(r300
);
908 r300_update_hyperz_state(r300
);