2 * Copyright 2008 Corbin Simpson <MostAwesomeDude@gmail.com>
3 * Copyright 2009 Marek Olšák <maraeo@gmail.com>
5 * Permission is hereby granted, free of charge, to any person obtaining a
6 * copy of this software and associated documentation files (the "Software"),
7 * to deal in the Software without restriction, including without limitation
8 * on the rights to use, copy, modify, merge, publish, distribute, sub
9 * license, and/or sell copies of the Software, and to permit persons to whom
10 * the Software is furnished to do so, subject to the following conditions:
12 * The above copyright notice and this permission notice (including the next
13 * paragraph) shall be included in all copies or substantial portions of the
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
19 * THE AUTHOR(S) AND/OR THEIR SUPPLIERS BE LIABLE FOR ANY CLAIM,
20 * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
21 * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
22 * USE OR OTHER DEALINGS IN THE SOFTWARE. */
24 #include "draw/draw_context.h"
26 #include "util/u_math.h"
27 #include "util/u_memory.h"
29 #include "r300_context.h"
31 #include "r300_screen.h"
32 #include "r300_shader_semantics.h"
33 #include "r300_state_derived.h"
34 #include "r300_state_inlines.h"
37 /* r300_state_derived: Various bits of state which are dependent upon
38 * currently bound CSO data. */
40 enum r300_rs_swizzle
{
46 static void r300_draw_emit_attrib(struct r300_context
* r300
,
47 enum attrib_emit emit
,
48 enum interp_mode interp
,
51 struct r300_vertex_shader
* vs
= r300
->vs_state
.state
;
52 struct tgsi_shader_info
* info
= &vs
->info
;
55 output
= draw_find_shader_output(r300
->draw
,
56 info
->output_semantic_name
[index
],
57 info
->output_semantic_index
[index
]);
58 draw_emit_vertex_attr(&r300
->vertex_info
, emit
, interp
, output
);
61 static void r300_draw_emit_all_attribs(struct r300_context
* r300
)
63 struct r300_vertex_shader
* vs
= r300
->vs_state
.state
;
64 struct r300_shader_semantics
* vs_outputs
= &vs
->outputs
;
68 if (vs_outputs
->pos
!= ATTR_UNUSED
) {
69 r300_draw_emit_attrib(r300
, EMIT_4F
, INTERP_PERSPECTIVE
,
76 if (vs_outputs
->psize
!= ATTR_UNUSED
) {
77 r300_draw_emit_attrib(r300
, EMIT_1F_PSIZE
, INTERP_POS
,
82 for (i
= 0; i
< ATTR_COLOR_COUNT
; i
++) {
83 if (vs_outputs
->color
[i
] != ATTR_UNUSED
) {
84 r300_draw_emit_attrib(r300
, EMIT_4F
, INTERP_LINEAR
,
85 vs_outputs
->color
[i
]);
89 /* XXX Back-face colors. */
91 /* Texture coordinates. */
92 /* Only 8 generic vertex attributes can be used. If there are more,
93 * they won't be rasterized. */
95 for (i
= 0; i
< ATTR_GENERIC_COUNT
&& gen_count
< 8; i
++) {
96 if (vs_outputs
->generic
[i
] != ATTR_UNUSED
) {
97 r300_draw_emit_attrib(r300
, EMIT_4F
, INTERP_PERSPECTIVE
,
98 vs_outputs
->generic
[i
]);
103 /* Fog coordinates. */
104 if (gen_count
< 8 && vs_outputs
->fog
!= ATTR_UNUSED
) {
105 r300_draw_emit_attrib(r300
, EMIT_4F
, INTERP_PERSPECTIVE
,
111 /* Update the PSC tables for SW TCL, using Draw. */
112 static void r300_swtcl_vertex_psc(struct r300_context
*r300
)
114 struct r300_vertex_stream_state
*vstream
= r300
->vertex_stream_state
.state
;
115 struct r300_vertex_shader
* vs
= r300
->vs_state
.state
;
116 struct vertex_info
* vinfo
= &r300
->vertex_info
;
117 uint16_t type
, swizzle
;
118 enum pipe_format format
;
119 unsigned i
, attrib_count
;
120 int* vs_output_tab
= vs
->stream_loc_notcl
;
123 memset(vstream
, 0, sizeof(struct r300_vertex_stream_state
));
125 /* For each Draw attribute, route it to the fragment shader according
126 * to the vs_output_tab. */
127 attrib_count
= vinfo
->num_attribs
;
128 DBG(r300
, DBG_DRAW
, "r300: attrib count: %d\n", attrib_count
);
129 for (i
= 0; i
< attrib_count
; i
++) {
130 DBG(r300
, DBG_DRAW
, "r300: attrib: offset %d, interp %d, size %d,"
131 " vs_output_tab %d\n", vinfo
->attrib
[i
].src_index
,
132 vinfo
->attrib
[i
].interp_mode
, vinfo
->attrib
[i
].emit
,
135 /* Make sure we have a proper destination for our attribute. */
136 assert(vs_output_tab
[i
] != -1);
138 format
= draw_translate_vinfo_format(vinfo
->attrib
[i
].emit
);
140 /* Obtain the type of data in this attribute. */
141 type
= r300_translate_vertex_data_type(format
) |
142 vs_output_tab
[i
] << R300_DST_VEC_LOC_SHIFT
;
144 /* Obtain the swizzle for this attribute. Note that the default
145 * swizzle in the hardware is not XYZW! */
146 swizzle
= r300_translate_vertex_data_swizzle(format
);
148 /* Add the attribute to the PSC table. */
150 vstream
->vap_prog_stream_cntl
[i
>> 1] |= type
<< 16;
151 vstream
->vap_prog_stream_cntl_ext
[i
>> 1] |= swizzle
<< 16;
153 vstream
->vap_prog_stream_cntl
[i
>> 1] |= type
;
154 vstream
->vap_prog_stream_cntl_ext
[i
>> 1] |= swizzle
;
158 /* Set the last vector in the PSC. */
162 vstream
->vap_prog_stream_cntl
[i
>> 1] |=
163 (R300_LAST_VEC
<< (i
& 1 ? 16 : 0));
165 vstream
->count
= (i
>> 1) + 1;
166 r300
->vertex_stream_state
.dirty
= TRUE
;
167 r300
->vertex_stream_state
.size
= (1 + vstream
->count
) * 2;
170 static void r300_rs_col(struct r300_rs_block
* rs
, int id
, int ptr
,
171 boolean swizzle_0001
)
173 rs
->ip
[id
] |= R300_RS_COL_PTR(ptr
);
175 rs
->ip
[id
] |= R300_RS_COL_FMT(R300_RS_COL_FMT_0001
);
177 rs
->ip
[id
] |= R300_RS_COL_FMT(R300_RS_COL_FMT_RGBA
);
179 rs
->inst
[id
] |= R300_RS_INST_COL_ID(id
);
182 static void r300_rs_col_write(struct r300_rs_block
* rs
, int id
, int fp_offset
)
184 rs
->inst
[id
] |= R300_RS_INST_COL_CN_WRITE
|
185 R300_RS_INST_COL_ADDR(fp_offset
);
188 static void r300_rs_tex(struct r300_rs_block
* rs
, int id
, int ptr
,
189 enum r300_rs_swizzle swiz
)
191 if (swiz
== SWIZ_X001
) {
192 rs
->ip
[id
] |= R300_RS_TEX_PTR(ptr
*4) |
193 R300_RS_SEL_S(R300_RS_SEL_C0
) |
194 R300_RS_SEL_T(R300_RS_SEL_K0
) |
195 R300_RS_SEL_R(R300_RS_SEL_K0
) |
196 R300_RS_SEL_Q(R300_RS_SEL_K1
);
197 } else if (swiz
== SWIZ_XY01
) {
198 rs
->ip
[id
] |= R300_RS_TEX_PTR(ptr
*4) |
199 R300_RS_SEL_S(R300_RS_SEL_C0
) |
200 R300_RS_SEL_T(R300_RS_SEL_C1
) |
201 R300_RS_SEL_R(R300_RS_SEL_K0
) |
202 R300_RS_SEL_Q(R300_RS_SEL_K1
);
204 rs
->ip
[id
] |= R300_RS_TEX_PTR(ptr
*4) |
205 R300_RS_SEL_S(R300_RS_SEL_C0
) |
206 R300_RS_SEL_T(R300_RS_SEL_C1
) |
207 R300_RS_SEL_R(R300_RS_SEL_C2
) |
208 R300_RS_SEL_Q(R300_RS_SEL_C3
);
210 rs
->inst
[id
] |= R300_RS_INST_TEX_ID(id
);
213 static void r300_rs_tex_write(struct r300_rs_block
* rs
, int id
, int fp_offset
)
215 rs
->inst
[id
] |= R300_RS_INST_TEX_CN_WRITE
|
216 R300_RS_INST_TEX_ADDR(fp_offset
);
219 static void r500_rs_col(struct r300_rs_block
* rs
, int id
, int ptr
,
220 boolean swizzle_0001
)
222 rs
->ip
[id
] |= R500_RS_COL_PTR(ptr
);
224 rs
->ip
[id
] |= R500_RS_COL_FMT(R300_RS_COL_FMT_0001
);
226 rs
->ip
[id
] |= R500_RS_COL_FMT(R300_RS_COL_FMT_RGBA
);
228 rs
->inst
[id
] |= R500_RS_INST_COL_ID(id
);
231 static void r500_rs_col_write(struct r300_rs_block
* rs
, int id
, int fp_offset
)
233 rs
->inst
[id
] |= R500_RS_INST_COL_CN_WRITE
|
234 R500_RS_INST_COL_ADDR(fp_offset
);
237 static void r500_rs_tex(struct r300_rs_block
* rs
, int id
, int ptr
,
238 enum r300_rs_swizzle swiz
)
240 int rs_tex_comp
= ptr
*4;
242 if (swiz
== SWIZ_X001
) {
243 rs
->ip
[id
] |= R500_RS_SEL_S(rs_tex_comp
) |
244 R500_RS_SEL_T(R500_RS_IP_PTR_K0
) |
245 R500_RS_SEL_R(R500_RS_IP_PTR_K0
) |
246 R500_RS_SEL_Q(R500_RS_IP_PTR_K1
);
247 } else if (swiz
== SWIZ_XY01
) {
248 rs
->ip
[id
] |= R500_RS_SEL_S(rs_tex_comp
) |
249 R500_RS_SEL_T(rs_tex_comp
+ 1) |
250 R500_RS_SEL_R(R500_RS_IP_PTR_K0
) |
251 R500_RS_SEL_Q(R500_RS_IP_PTR_K1
);
253 rs
->ip
[id
] |= R500_RS_SEL_S(rs_tex_comp
) |
254 R500_RS_SEL_T(rs_tex_comp
+ 1) |
255 R500_RS_SEL_R(rs_tex_comp
+ 2) |
256 R500_RS_SEL_Q(rs_tex_comp
+ 3);
258 rs
->inst
[id
] |= R500_RS_INST_TEX_ID(id
);
261 static void r500_rs_tex_write(struct r300_rs_block
* rs
, int id
, int fp_offset
)
263 rs
->inst
[id
] |= R500_RS_INST_TEX_CN_WRITE
|
264 R500_RS_INST_TEX_ADDR(fp_offset
);
267 /* Set up the RS block.
269 * This is the part of the chipset that actually does the rasterization
270 * of vertices into fragments. This is also the part of the chipset that
271 * locks up if any part of it is even slightly wrong. */
272 static void r300_update_rs_block(struct r300_context
* r300
,
273 struct r300_shader_semantics
* vs_outputs
,
274 struct r300_shader_semantics
* fs_inputs
)
276 struct r300_rs_block rs
= { { 0 } };
277 int i
, col_count
= 0, tex_count
= 0, fp_offset
= 0, count
;
278 void (*rX00_rs_col
)(struct r300_rs_block
*, int, int, boolean
);
279 void (*rX00_rs_col_write
)(struct r300_rs_block
*, int, int);
280 void (*rX00_rs_tex
)(struct r300_rs_block
*, int, int, enum r300_rs_swizzle
);
281 void (*rX00_rs_tex_write
)(struct r300_rs_block
*, int, int);
282 boolean any_bcolor_used
= vs_outputs
->bcolor
[0] != ATTR_UNUSED
||
283 vs_outputs
->bcolor
[1] != ATTR_UNUSED
;
285 if (r300
->screen
->caps
.is_r500
) {
286 rX00_rs_col
= r500_rs_col
;
287 rX00_rs_col_write
= r500_rs_col_write
;
288 rX00_rs_tex
= r500_rs_tex
;
289 rX00_rs_tex_write
= r500_rs_tex_write
;
291 rX00_rs_col
= r300_rs_col
;
292 rX00_rs_col_write
= r300_rs_col_write
;
293 rX00_rs_tex
= r300_rs_tex
;
294 rX00_rs_tex_write
= r300_rs_tex_write
;
297 /* Rasterize colors. */
298 for (i
= 0; i
< ATTR_COLOR_COUNT
; i
++) {
299 if (vs_outputs
->color
[i
] != ATTR_UNUSED
|| any_bcolor_used
||
300 vs_outputs
->color
[1] != ATTR_UNUSED
) {
301 /* Always rasterize if it's written by the VS,
302 * otherwise it locks up. */
303 rX00_rs_col(&rs
, col_count
, i
, FALSE
);
305 /* Write it to the FS input register if it's used by the FS. */
306 if (fs_inputs
->color
[i
] != ATTR_UNUSED
) {
307 rX00_rs_col_write(&rs
, col_count
, fp_offset
);
312 /* Skip the FS input register, leave it uninitialized. */
313 /* If we try to set it to (0,0,0,1), it will lock up. */
314 if (fs_inputs
->color
[i
] != ATTR_UNUSED
) {
320 /* Rasterize texture coordinates. */
321 for (i
= 0; i
< ATTR_GENERIC_COUNT
; i
++) {
322 bool sprite_coord
= !!(r300
->sprite_coord_enable
& (1 << i
));
324 if (vs_outputs
->generic
[i
] != ATTR_UNUSED
|| sprite_coord
) {
325 /* Always rasterize if it's written by the VS,
326 * otherwise it locks up. */
327 rX00_rs_tex(&rs
, tex_count
, tex_count
,
328 sprite_coord
? SWIZ_XY01
: SWIZ_XYZW
);
330 /* Write it to the FS input register if it's used by the FS. */
331 if (fs_inputs
->generic
[i
] != ATTR_UNUSED
) {
332 rX00_rs_tex_write(&rs
, tex_count
, fp_offset
);
334 debug_printf("r300: SpriteCoord (generic index %i) is being written to reg %i\n", i
, fp_offset
);
339 /* Skip the FS input register, leave it uninitialized. */
340 /* If we try to set it to (0,0,0,1), it will lock up. */
341 if (fs_inputs
->generic
[i
] != ATTR_UNUSED
) {
347 /* Rasterize fog coordinates. */
348 if (vs_outputs
->fog
!= ATTR_UNUSED
) {
349 /* Always rasterize if it's written by the VS,
350 * otherwise it locks up. */
351 rX00_rs_tex(&rs
, tex_count
, tex_count
, SWIZ_X001
);
353 /* Write it to the FS input register if it's used by the FS. */
354 if (fs_inputs
->fog
!= ATTR_UNUSED
) {
355 rX00_rs_tex_write(&rs
, tex_count
, fp_offset
);
360 /* Skip the FS input register, leave it uninitialized. */
361 /* If we try to set it to (0,0,0,1), it will lock up. */
362 if (fs_inputs
->fog
!= ATTR_UNUSED
) {
367 /* Rasterize WPOS. */
368 /* If the FS doesn't need it, it's not written by the VS. */
369 if (vs_outputs
->wpos
!= ATTR_UNUSED
&& fs_inputs
->wpos
!= ATTR_UNUSED
) {
370 rX00_rs_tex(&rs
, tex_count
, tex_count
, SWIZ_XYZW
);
371 rX00_rs_tex_write(&rs
, tex_count
, fp_offset
);
377 /* Rasterize at least one color, or bad things happen. */
378 if (col_count
== 0 && tex_count
== 0) {
379 rX00_rs_col(&rs
, 0, 0, TRUE
);
383 rs
.count
= (tex_count
*4) | (col_count
<< R300_IC_COUNT_SHIFT
) |
386 count
= MAX3(col_count
, tex_count
, 1);
387 rs
.inst_count
= count
- 1;
389 /* Now, after all that, see if we actually need to update the state. */
390 if (memcmp(r300
->rs_block_state
.state
, &rs
, sizeof(struct r300_rs_block
))) {
391 memcpy(r300
->rs_block_state
.state
, &rs
, sizeof(struct r300_rs_block
));
392 r300
->rs_block_state
.size
= 5 + count
*2;
396 /* Update the shader-dependant states. */
397 static void r300_update_derived_shader_state(struct r300_context
* r300
)
399 struct r300_vertex_shader
* vs
= r300
->vs_state
.state
;
401 r300_update_rs_block(r300
, &vs
->outputs
, &r300_fs(r300
)->shader
->inputs
);
404 static boolean
r300_dsa_writes_depth_stencil(struct r300_dsa_state
* dsa
)
406 /* We are interested only in the cases when a new depth or stencil value
407 * can be written and changed. */
409 /* We might optionally check for [Z func: never] and inspect the stencil
410 * state in a similar fashion, but it's not terribly important. */
411 return (dsa
->z_buffer_control
& R300_Z_WRITE_ENABLE
) ||
412 (dsa
->stencil_ref_mask
& R300_STENCILWRITEMASK_MASK
) ||
413 ((dsa
->z_buffer_control
& R500_STENCIL_REFMASK_FRONT_BACK
) &&
414 (dsa
->stencil_ref_bf
& R300_STENCILWRITEMASK_MASK
));
417 static boolean
r300_dsa_alpha_test_enabled(struct r300_dsa_state
* dsa
)
419 /* We are interested only in the cases when alpha testing can kill
421 uint32_t af
= dsa
->alpha_function
;
423 return (af
& R300_FG_ALPHA_FUNC_ENABLE
) &&
424 (af
& R300_FG_ALPHA_FUNC_ALWAYS
) != R300_FG_ALPHA_FUNC_ALWAYS
;
427 static void r300_update_ztop(struct r300_context
* r300
)
429 struct r300_ztop_state
* ztop_state
=
430 (struct r300_ztop_state
*)r300
->ztop_state
.state
;
432 /* This is important enough that I felt it warranted a comment.
434 * According to the docs, these are the conditions where ZTOP must be
436 * 1) Alpha testing enabled
437 * 2) Texture kill instructions in fragment shader
438 * 3) Chroma key culling enabled
439 * 4) W-buffering enabled
441 * The docs claim that for the first three cases, if no ZS writes happen,
442 * then ZTOP can be used.
444 * (3) will never apply since we do not support chroma-keyed operations.
445 * (4) will need to be re-examined (and this comment updated) if/when
446 * Hyper-Z becomes supported.
448 * Additionally, the following conditions require disabled ZTOP:
449 * 5) Depth writes in fragment shader
450 * 6) Outstanding occlusion queries
452 * This register causes stalls all the way from SC to CB when changed,
453 * but it is buffered on-chip so it does not hurt to write it if it has
460 if (r300_dsa_writes_depth_stencil(r300
->dsa_state
.state
) &&
461 (r300_dsa_alpha_test_enabled(r300
->dsa_state
.state
) || /* (1) */
462 r300_fs(r300
)->shader
->info
.uses_kill
)) { /* (2) */
463 ztop_state
->z_buffer_top
= R300_ZTOP_DISABLE
;
464 } else if (r300_fragment_shader_writes_depth(r300_fs(r300
))) { /* (5) */
465 ztop_state
->z_buffer_top
= R300_ZTOP_DISABLE
;
466 } else if (r300
->query_current
) { /* (6) */
467 ztop_state
->z_buffer_top
= R300_ZTOP_DISABLE
;
469 ztop_state
->z_buffer_top
= R300_ZTOP_ENABLE
;
472 r300
->ztop_state
.dirty
= TRUE
;
475 static void r300_merge_textures_and_samplers(struct r300_context
* r300
)
477 struct r300_textures_state
*state
=
478 (struct r300_textures_state
*)r300
->textures_state
.state
;
479 struct r300_texture_sampler_state
*texstate
;
480 struct r300_sampler_state
*sampler
;
481 struct r300_sampler_view
*view
;
482 struct r300_texture
*tex
;
483 unsigned min_level
, max_level
, i
, size
;
484 unsigned count
= MIN2(state
->sampler_view_count
,
485 state
->sampler_state_count
);
487 state
->tx_enable
= 0;
491 for (i
= 0; i
< count
; i
++) {
492 if (state
->sampler_views
[i
] && state
->sampler_states
[i
]) {
493 state
->tx_enable
|= 1 << i
;
495 view
= state
->sampler_views
[i
];
496 tex
= r300_texture(view
->base
.texture
);
497 sampler
= state
->sampler_states
[i
];
499 texstate
= &state
->regs
[i
];
500 texstate
->format
= view
->format
;
501 texstate
->filter0
= sampler
->filter0
;
502 texstate
->filter1
= sampler
->filter1
;
503 texstate
->border_color
= sampler
->border_color
;
505 /* to emulate 1D textures through 2D ones correctly */
506 if (tex
->b
.b
.target
== PIPE_TEXTURE_1D
) {
507 texstate
->filter0
&= ~R300_TX_WRAP_T_MASK
;
508 texstate
->filter0
|= R300_TX_WRAP_T(R300_TX_CLAMP_TO_EDGE
);
511 if (tex
->uses_pitch
) {
512 /* NPOT textures don't support mip filter, unfortunately.
513 * This prevents incorrect rendering. */
514 texstate
->filter0
&= ~R300_TX_MIN_FILTER_MIP_MASK
;
516 /* Set repeat or mirrored-repeat to clamp-to-edge. */
518 if ((texstate
->filter0
& R300_TX_WRAP_S_MASK
) ==
519 R300_TX_WRAP_S(R300_TX_REPEAT
) ||
520 (texstate
->filter0
& R300_TX_WRAP_S_MASK
) ==
521 R300_TX_WRAP_S(R300_TX_MIRRORED
)) {
522 texstate
->filter0
&= ~R300_TX_WRAP_S_MASK
;
523 texstate
->filter0
|= R300_TX_WRAP_S(R300_TX_CLAMP_TO_EDGE
);
527 if ((texstate
->filter0
& R300_TX_WRAP_T_MASK
) ==
528 R300_TX_WRAP_T(R300_TX_REPEAT
) ||
529 (texstate
->filter0
& R300_TX_WRAP_T_MASK
) ==
530 R300_TX_WRAP_T(R300_TX_MIRRORED
)) {
531 texstate
->filter0
&= ~R300_TX_WRAP_T_MASK
;
532 texstate
->filter0
|= R300_TX_WRAP_T(R300_TX_CLAMP_TO_EDGE
);
535 /* determine min/max levels */
536 /* the MAX_MIP level is the largest (finest) one */
537 max_level
= MIN3(sampler
->max_lod
+ view
->base
.first_level
,
538 tex
->b
.b
.last_level
, view
->base
.last_level
);
539 min_level
= MIN2(sampler
->min_lod
+ view
->base
.first_level
,
541 texstate
->format
.format0
|= R300_TX_NUM_LEVELS(max_level
);
542 texstate
->filter0
|= R300_TX_MAX_MIP_LEVEL(min_level
);
545 texstate
->filter0
|= i
<< 28;
552 r300
->textures_state
.size
= size
;
555 void r300_update_derived_state(struct r300_context
* r300
)
557 if (r300
->rs_block_state
.dirty
) {
558 r300_update_derived_shader_state(r300
);
561 if (r300
->textures_state
.dirty
) {
562 r300_merge_textures_and_samplers(r300
);
566 memset(&r300
->vertex_info
, 0, sizeof(struct vertex_info
));
567 r300_draw_emit_all_attribs(r300
);
568 draw_compute_vertex_size(&r300
->vertex_info
);
569 r300_swtcl_vertex_psc(r300
);
572 r300_update_ztop(r300
);