feb0faa13c9975aeeeac02c55acb34067e34b93c
[mesa.git] / src / gallium / drivers / r300 / r300_state_derived.c
1 /*
2 * Copyright 2008 Corbin Simpson <MostAwesomeDude@gmail.com>
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * on the rights to use, copy, modify, merge, publish, distribute, sub
8 * license, and/or sell copies of the Software, and to permit persons to whom
9 * the Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
13 * Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHOR(S) AND/OR THEIR SUPPLIERS BE LIABLE FOR ANY CLAIM,
19 * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
20 * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
21 * USE OR OTHER DEALINGS IN THE SOFTWARE. */
22
23 #include "r300_state_derived.h"
24
25 /* r300_state_derived: Various bits of state which are dependent upon
26 * currently bound CSO data. */
27
28 /* Update the vertex_info struct in our r300_context.
29 *
30 * The vertex_info struct describes the post-TCL format of vertices. It is
31 * required for Draw when doing SW TCL, and also for describing the
32 * dreaded RS block on R300 chipsets. */
33 /* XXX this function should be able to handle vert shaders as well as draw */
34 static void r300_update_vertex_layout(struct r300_context* r300)
35 {
36 struct r300_vertex_format vformat;
37 struct vertex_info vinfo;
38 boolean pos = FALSE, psize = FALSE, fog = FALSE;
39 int i, texs = 0, cols = 0;
40 int tab[16];
41
42 struct tgsi_shader_info* info = &r300->fs->info;
43
44 memset(&vinfo, 0, sizeof(vinfo));
45 for (i = 0; i < 16; i++) {
46 tab[i] = -1;
47 }
48
49 assert(info->num_inputs <= 16);
50
51 for (i = 0; i < info->num_inputs; i++) {
52 switch (info->input_semantic_name[i]) {
53 case TGSI_SEMANTIC_POSITION:
54 pos = TRUE;
55 tab[i] = 0;
56 break;
57 case TGSI_SEMANTIC_COLOR:
58 tab[i] = 2 + cols++;
59 break;
60 case TGSI_SEMANTIC_FOG:
61 fog = TRUE;
62 tab[i] = 6 + texs++;
63 break;
64 case TGSI_SEMANTIC_PSIZE:
65 psize = TRUE;
66 tab[i] = 1;
67 break;
68 case TGSI_SEMANTIC_GENERIC:
69 tab[i] = 6 + texs++;
70 break;
71 default:
72 debug_printf("r300: Unknown vertex input %d\n",
73 info->input_semantic_name[i]);
74 break;
75 }
76 }
77
78 /* Do the actual vertex_info setup.
79 *
80 * vertex_info has four uints of hardware-specific data in it.
81 * vinfo.hwfmt[0] is R300_VAP_VTX_STATE_CNTL
82 * vinfo.hwfmt[1] is R300_VAP_VSM_VTX_ASSM
83 * vinfo.hwfmt[2] is R300_VAP_OUTPUT_VTX_FMT_0
84 * vinfo.hwfmt[3] is R300_VAP_OUTPUT_VTX_FMT_1 */
85
86 vinfo.hwfmt[0] = 0x5555; /* XXX this is classic Mesa bonghits */
87
88 if (!pos) {
89 debug_printf("r300: Forcing vertex position attribute emit...\n");
90 /* Make room for the position attribute
91 * at the beginning of the tab. */
92 for (i = 1; i < 16; i++) {
93 tab[i] = tab[i-1];
94 }
95 tab[0] = 0;
96
97 draw_emit_vertex_attr(&vinfo, EMIT_4F, INTERP_POS,
98 draw_find_vs_output(r300->draw, TGSI_SEMANTIC_POSITION, 0));
99 } else {
100 draw_emit_vertex_attr(&vinfo, EMIT_4F, INTERP_PERSPECTIVE,
101 draw_find_vs_output(r300->draw, TGSI_SEMANTIC_POSITION, 0));
102 }
103 vinfo.hwfmt[1] |= R300_INPUT_CNTL_POS;
104 vinfo.hwfmt[2] |= R300_VAP_OUTPUT_VTX_FMT_0__POS_PRESENT;
105
106 if (psize) {
107 draw_emit_vertex_attr(&vinfo, EMIT_1F_PSIZE, INTERP_POS,
108 draw_find_vs_output(r300->draw, TGSI_SEMANTIC_PSIZE, 0));
109 vinfo.hwfmt[2] |= R300_VAP_OUTPUT_VTX_FMT_0__PT_SIZE_PRESENT;
110 }
111
112 for (i = 0; i < cols; i++) {
113 draw_emit_vertex_attr(&vinfo, EMIT_4F, INTERP_LINEAR,
114 draw_find_vs_output(r300->draw, TGSI_SEMANTIC_COLOR, i));
115 vinfo.hwfmt[1] |= R300_INPUT_CNTL_COLOR;
116 vinfo.hwfmt[2] |= (R300_VAP_OUTPUT_VTX_FMT_0__COLOR_0_PRESENT << i);
117 }
118
119 for (i = 0; i < texs; i++) {
120 draw_emit_vertex_attr(&vinfo, EMIT_4F, INTERP_PERSPECTIVE,
121 draw_find_vs_output(r300->draw, TGSI_SEMANTIC_GENERIC, i));
122 vinfo.hwfmt[1] |= (R300_INPUT_CNTL_TC0 << i);
123 vinfo.hwfmt[3] |= (4 << (3 * i));
124 }
125
126 if (fog) {
127 i++;
128 draw_emit_vertex_attr(&vinfo, EMIT_4F, INTERP_PERSPECTIVE,
129 draw_find_vs_output(r300->draw, TGSI_SEMANTIC_FOG, 0));
130 vinfo.hwfmt[1] |= (R300_INPUT_CNTL_TC0 << i);
131 vinfo.hwfmt[3] |= (4 << (3 * i));
132 }
133
134 draw_compute_vertex_size(&vinfo);
135
136 if (memcmp(&r300->vertex_info, &vinfo, sizeof(struct vertex_info))) {
137 uint32_t temp;
138 debug_printf("attrib count: %d, fp input count: %d\n",
139 vinfo.num_attribs, info->num_inputs);
140 for (i = 0; i < vinfo.num_attribs; i++) {
141 debug_printf("attrib: offset %d, interp %d, size %d,"
142 " tab %d\n", vinfo.attrib[i].src_index,
143 vinfo.attrib[i].interp_mode, vinfo.attrib[i].emit,
144 tab[i]);
145 }
146
147 for (i = 0; i < vinfo.num_attribs; i++) {
148 /* Make sure we have a proper destination for our attribute */
149 assert(tab[i] != -1);
150
151 temp = translate_vertex_data_type(vinfo.attrib[i].emit) |
152 (tab[i] << R300_DST_VEC_LOC_SHIFT);
153 if (i & 1) {
154 r300->vertex_info.vap_prog_stream_cntl[i >> 1] &= 0x0000ffff;
155 r300->vertex_info.vap_prog_stream_cntl[i >> 1] |= temp << 16;
156 } else {
157 r300->vertex_info.vap_prog_stream_cntl[i >> 1] &= 0xffff0000;
158 r300->vertex_info.vap_prog_stream_cntl[i >> 1] |= temp;
159 }
160
161 r300->vertex_info.vap_prog_stream_cntl_ext[i >> 1] |=
162 (R300_VAP_SWIZZLE_XYZW << (i & 1 ? 16 : 0));
163 }
164 r300->vertex_info.vap_prog_stream_cntl[i >> 1] |= (R300_LAST_VEC <<
165 (i & 1 ? 16 : 0));
166
167 memcpy(r300->vertex_info.tab, tab, sizeof(tab));
168 memcpy(&r300->vertex_info, &vinfo, sizeof(struct vertex_info));
169 r300->dirty_state |= R300_NEW_VERTEX_FORMAT;
170 }
171 }
172
173 /* Set up the RS block. This is the part of the chipset that actually does
174 * the rasterization of vertices into fragments. This is also the part of the
175 * chipset that locks up if any part of it is even slightly wrong. */
176 static void r300_update_rs_block(struct r300_context* r300)
177 {
178 struct r300_rs_block* rs = r300->rs_block;
179 struct vertex_info* vinfo = &r300->vertex_info.vinfo;
180 int* tab = r300->vertex_info.tab;
181 int col_count = 0, fp_offset = 0, i, memory_pos, tex_count = 0;
182
183 memset(rs, 0, sizeof(struct r300_rs_block));
184
185 if (r300_screen(r300->context.screen)->caps->is_r500) {
186 for (i = 0; i < vinfo->num_attribs; i++) {
187 assert(tab[vinfo->attrib[i].src_index] != -1);
188 memory_pos = tab[vinfo->attrib[i].src_index] * 4;
189 switch (vinfo->attrib[i].interp_mode) {
190 case INTERP_LINEAR:
191 rs->ip[col_count] |=
192 R500_RS_COL_PTR(memory_pos) |
193 R500_RS_COL_FMT(R300_RS_COL_FMT_RGBA);
194 col_count++;
195 break;
196 case INTERP_PERSPECTIVE:
197 rs->ip[tex_count] |=
198 R500_RS_SEL_S(memory_pos) |
199 R500_RS_SEL_T(memory_pos + 1) |
200 R500_RS_SEL_R(memory_pos + 2) |
201 R500_RS_SEL_Q(memory_pos + 3);
202 tex_count++;
203 break;
204 default:
205 break;
206 }
207 }
208
209 /* Set up at least one texture pointer or RS will not be happy. */
210 if (tex_count == 0) {
211 rs->ip[0] |=
212 R500_RS_SEL_S(R500_RS_IP_PTR_K0) |
213 R500_RS_SEL_T(R500_RS_IP_PTR_K0) |
214 R500_RS_SEL_R(R500_RS_IP_PTR_K0) |
215 R500_RS_SEL_Q(R500_RS_IP_PTR_K1);
216 }
217
218 for (i = 0; i < tex_count; i++) {
219 rs->inst[i] |= R500_RS_INST_TEX_ID(i) | R500_RS_INST_TEX_CN_WRITE |
220 R500_RS_INST_TEX_ADDR(fp_offset);
221 fp_offset++;
222 }
223
224 for (i = 0; i < col_count; i++) {
225 rs->inst[i] |= R500_RS_INST_COL_ID(i) | R500_RS_INST_COL_CN_WRITE |
226 R500_RS_INST_COL_ADDR(fp_offset);
227 fp_offset++;
228 }
229
230 rs->inst_count = MAX2(col_count, tex_count);
231 } else {
232 for (i = 0; i < vinfo->num_attribs; i++) {
233 memory_pos = tab[vinfo->attrib[i].src_index] * 4;
234 assert(tab[vinfo->attrib[i].src_index] != -1);
235 switch (vinfo->attrib[i].interp_mode) {
236 case INTERP_LINEAR:
237 rs->ip[col_count] |=
238 R300_RS_COL_PTR(memory_pos) |
239 R300_RS_COL_FMT(R300_RS_COL_FMT_RGBA);
240 col_count++;
241 break;
242 case INTERP_PERSPECTIVE:
243 rs->ip[tex_count] |=
244 R300_RS_TEX_PTR(memory_pos) |
245 R300_RS_SEL_S(R300_RS_SEL_C0) |
246 R300_RS_SEL_T(R300_RS_SEL_C1) |
247 R300_RS_SEL_R(R300_RS_SEL_C2) |
248 R300_RS_SEL_Q(R300_RS_SEL_C3);
249 tex_count++;
250 break;
251 default:
252 break;
253 }
254 }
255
256 if (tex_count == 0) {
257 rs->ip[0] |=
258 R300_RS_SEL_S(R300_RS_SEL_K0) |
259 R300_RS_SEL_T(R300_RS_SEL_K0) |
260 R300_RS_SEL_R(R300_RS_SEL_K0) |
261 R300_RS_SEL_Q(R300_RS_SEL_K1);
262 }
263
264 for (i = 0; i < 8; i++)
265 debug_printf("ip %d: 0x%x\n", i, rs->ip[i]);
266
267 for (i = 0; i < tex_count; i++) {
268 rs->inst[i] |= R300_RS_INST_TEX_ID(i) | R300_RS_INST_TEX_CN_WRITE |
269 R300_RS_INST_TEX_ADDR(fp_offset);
270 fp_offset++;
271 }
272
273 for (i = 0; i < col_count; i++) {
274 rs->inst[i] |= R300_RS_INST_COL_ID(i) | R300_RS_INST_COL_CN_WRITE |
275 R300_RS_INST_COL_ADDR(fp_offset);
276 fp_offset++;
277 }
278
279 for (i = 0; i < 8; i++)
280 debug_printf("inst %d: 0x%x\n", i, rs->inst[i]);
281 }
282
283 rs->count = (tex_count * 4) | (col_count << R300_IC_COUNT_SHIFT) |
284 R300_HIRES_EN;
285
286 rs->inst_count = MAX2(MAX2(col_count - 1, tex_count - 1), 0);
287
288 debug_printf("count: 0x%x, inst_count: 0x%x\n", rs->count, rs->inst_count);
289 }
290
291 void r300_update_derived_state(struct r300_context* r300)
292 {
293 if (r300->dirty_state & R300_NEW_FRAGMENT_SHADER) {
294 r300_update_vertex_layout(r300);
295 }
296
297 if (r300->dirty_state & R300_NEW_VERTEX_FORMAT) {
298 r300_update_rs_block(r300);
299 }
300 }