r300g: use the enum for color swizzles in the rasterizer
[mesa.git] / src / gallium / drivers / r300 / r300_state_derived.c
1 /*
2 * Copyright 2008 Corbin Simpson <MostAwesomeDude@gmail.com>
3 * Copyright 2009 Marek Olšák <maraeo@gmail.com>
4 *
5 * Permission is hereby granted, free of charge, to any person obtaining a
6 * copy of this software and associated documentation files (the "Software"),
7 * to deal in the Software without restriction, including without limitation
8 * on the rights to use, copy, modify, merge, publish, distribute, sub
9 * license, and/or sell copies of the Software, and to permit persons to whom
10 * the Software is furnished to do so, subject to the following conditions:
11 *
12 * The above copyright notice and this permission notice (including the next
13 * paragraph) shall be included in all copies or substantial portions of the
14 * Software.
15 *
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
19 * THE AUTHOR(S) AND/OR THEIR SUPPLIERS BE LIABLE FOR ANY CLAIM,
20 * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
21 * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
22 * USE OR OTHER DEALINGS IN THE SOFTWARE. */
23
24 #include "draw/draw_context.h"
25
26 #include "util/u_math.h"
27 #include "util/u_memory.h"
28
29 #include "r300_context.h"
30 #include "r300_fs.h"
31 #include "r300_hyperz.h"
32 #include "r300_screen.h"
33 #include "r300_shader_semantics.h"
34 #include "r300_state.h"
35 #include "r300_state_derived.h"
36 #include "r300_state_inlines.h"
37 #include "r300_vs.h"
38
39 /* r300_state_derived: Various bits of state which are dependent upon
40 * currently bound CSO data. */
41
42 enum r300_rs_swizzle {
43 SWIZ_XYZW = 0,
44 SWIZ_X001,
45 SWIZ_XY01,
46 SWIZ_0001,
47 };
48
49 static void r300_draw_emit_attrib(struct r300_context* r300,
50 enum attrib_emit emit,
51 enum interp_mode interp,
52 int index)
53 {
54 struct r300_vertex_shader* vs = r300->vs_state.state;
55 struct tgsi_shader_info* info = &vs->info;
56 int output;
57
58 output = draw_find_shader_output(r300->draw,
59 info->output_semantic_name[index],
60 info->output_semantic_index[index]);
61 draw_emit_vertex_attr(&r300->vertex_info, emit, interp, output);
62 }
63
64 static void r300_draw_emit_all_attribs(struct r300_context* r300)
65 {
66 struct r300_vertex_shader* vs = r300->vs_state.state;
67 struct r300_shader_semantics* vs_outputs = &vs->outputs;
68 int i, gen_count;
69
70 /* Position. */
71 if (vs_outputs->pos != ATTR_UNUSED) {
72 r300_draw_emit_attrib(r300, EMIT_4F, INTERP_PERSPECTIVE,
73 vs_outputs->pos);
74 } else {
75 assert(0);
76 }
77
78 /* Point size. */
79 if (vs_outputs->psize != ATTR_UNUSED) {
80 r300_draw_emit_attrib(r300, EMIT_1F_PSIZE, INTERP_POS,
81 vs_outputs->psize);
82 }
83
84 /* Colors. */
85 for (i = 0; i < ATTR_COLOR_COUNT; i++) {
86 if (vs_outputs->color[i] != ATTR_UNUSED) {
87 r300_draw_emit_attrib(r300, EMIT_4F, INTERP_LINEAR,
88 vs_outputs->color[i]);
89 }
90 }
91
92 /* XXX Back-face colors. */
93
94 /* Texture coordinates. */
95 /* Only 8 generic vertex attributes can be used. If there are more,
96 * they won't be rasterized. */
97 gen_count = 0;
98 for (i = 0; i < ATTR_GENERIC_COUNT && gen_count < 8; i++) {
99 if (vs_outputs->generic[i] != ATTR_UNUSED) {
100 r300_draw_emit_attrib(r300, EMIT_4F, INTERP_PERSPECTIVE,
101 vs_outputs->generic[i]);
102 gen_count++;
103 }
104 }
105
106 /* Fog coordinates. */
107 if (gen_count < 8 && vs_outputs->fog != ATTR_UNUSED) {
108 r300_draw_emit_attrib(r300, EMIT_4F, INTERP_PERSPECTIVE,
109 vs_outputs->fog);
110 gen_count++;
111 }
112 }
113
114 /* Update the PSC tables for SW TCL, using Draw. */
115 static void r300_swtcl_vertex_psc(struct r300_context *r300)
116 {
117 struct r300_vertex_stream_state *vstream = r300->vertex_stream_state.state;
118 struct r300_vertex_shader* vs = r300->vs_state.state;
119 struct vertex_info* vinfo = &r300->vertex_info;
120 uint16_t type, swizzle;
121 enum pipe_format format;
122 unsigned i, attrib_count;
123 int* vs_output_tab = vs->stream_loc_notcl;
124
125 /* XXX hax */
126 memset(vstream, 0, sizeof(struct r300_vertex_stream_state));
127
128 /* For each Draw attribute, route it to the fragment shader according
129 * to the vs_output_tab. */
130 attrib_count = vinfo->num_attribs;
131 DBG(r300, DBG_DRAW, "r300: attrib count: %d\n", attrib_count);
132 for (i = 0; i < attrib_count; i++) {
133 DBG(r300, DBG_DRAW, "r300: attrib: offset %d, interp %d, size %d,"
134 " vs_output_tab %d\n", vinfo->attrib[i].src_index,
135 vinfo->attrib[i].interp_mode, vinfo->attrib[i].emit,
136 vs_output_tab[i]);
137
138 /* Make sure we have a proper destination for our attribute. */
139 assert(vs_output_tab[i] != -1);
140
141 format = draw_translate_vinfo_format(vinfo->attrib[i].emit);
142
143 /* Obtain the type of data in this attribute. */
144 type = r300_translate_vertex_data_type(format) |
145 vs_output_tab[i] << R300_DST_VEC_LOC_SHIFT;
146
147 /* Obtain the swizzle for this attribute. Note that the default
148 * swizzle in the hardware is not XYZW! */
149 swizzle = r300_translate_vertex_data_swizzle(format);
150
151 /* Add the attribute to the PSC table. */
152 if (i & 1) {
153 vstream->vap_prog_stream_cntl[i >> 1] |= type << 16;
154 vstream->vap_prog_stream_cntl_ext[i >> 1] |= swizzle << 16;
155 } else {
156 vstream->vap_prog_stream_cntl[i >> 1] |= type;
157 vstream->vap_prog_stream_cntl_ext[i >> 1] |= swizzle;
158 }
159 }
160
161 /* Set the last vector in the PSC. */
162 if (i) {
163 i -= 1;
164 }
165 vstream->vap_prog_stream_cntl[i >> 1] |=
166 (R300_LAST_VEC << (i & 1 ? 16 : 0));
167
168 vstream->count = (i >> 1) + 1;
169 r300->vertex_stream_state.dirty = TRUE;
170 r300->vertex_stream_state.size = (1 + vstream->count) * 2;
171 }
172
173 static void r300_rs_col(struct r300_rs_block* rs, int id, int ptr,
174 enum r300_rs_swizzle swiz)
175 {
176 rs->ip[id] |= R300_RS_COL_PTR(ptr);
177 if (swiz == SWIZ_0001) {
178 rs->ip[id] |= R300_RS_COL_FMT(R300_RS_COL_FMT_0001);
179 } else {
180 rs->ip[id] |= R300_RS_COL_FMT(R300_RS_COL_FMT_RGBA);
181 }
182 rs->inst[id] |= R300_RS_INST_COL_ID(id);
183 }
184
185 static void r300_rs_col_write(struct r300_rs_block* rs, int id, int fp_offset)
186 {
187 rs->inst[id] |= R300_RS_INST_COL_CN_WRITE |
188 R300_RS_INST_COL_ADDR(fp_offset);
189 }
190
191 static void r300_rs_tex(struct r300_rs_block* rs, int id, int ptr,
192 enum r300_rs_swizzle swiz)
193 {
194 if (swiz == SWIZ_X001) {
195 rs->ip[id] |= R300_RS_TEX_PTR(ptr*4) |
196 R300_RS_SEL_S(R300_RS_SEL_C0) |
197 R300_RS_SEL_T(R300_RS_SEL_K0) |
198 R300_RS_SEL_R(R300_RS_SEL_K0) |
199 R300_RS_SEL_Q(R300_RS_SEL_K1);
200 } else if (swiz == SWIZ_XY01) {
201 rs->ip[id] |= R300_RS_TEX_PTR(ptr*4) |
202 R300_RS_SEL_S(R300_RS_SEL_C0) |
203 R300_RS_SEL_T(R300_RS_SEL_C1) |
204 R300_RS_SEL_R(R300_RS_SEL_K0) |
205 R300_RS_SEL_Q(R300_RS_SEL_K1);
206 } else {
207 rs->ip[id] |= R300_RS_TEX_PTR(ptr*4) |
208 R300_RS_SEL_S(R300_RS_SEL_C0) |
209 R300_RS_SEL_T(R300_RS_SEL_C1) |
210 R300_RS_SEL_R(R300_RS_SEL_C2) |
211 R300_RS_SEL_Q(R300_RS_SEL_C3);
212 }
213 rs->inst[id] |= R300_RS_INST_TEX_ID(id);
214 }
215
216 static void r300_rs_tex_write(struct r300_rs_block* rs, int id, int fp_offset)
217 {
218 rs->inst[id] |= R300_RS_INST_TEX_CN_WRITE |
219 R300_RS_INST_TEX_ADDR(fp_offset);
220 }
221
222 static void r500_rs_col(struct r300_rs_block* rs, int id, int ptr,
223 enum r300_rs_swizzle swiz)
224 {
225 rs->ip[id] |= R500_RS_COL_PTR(ptr);
226 if (swiz == SWIZ_0001) {
227 rs->ip[id] |= R500_RS_COL_FMT(R300_RS_COL_FMT_0001);
228 } else {
229 rs->ip[id] |= R500_RS_COL_FMT(R300_RS_COL_FMT_RGBA);
230 }
231 rs->inst[id] |= R500_RS_INST_COL_ID(id);
232 }
233
234 static void r500_rs_col_write(struct r300_rs_block* rs, int id, int fp_offset)
235 {
236 rs->inst[id] |= R500_RS_INST_COL_CN_WRITE |
237 R500_RS_INST_COL_ADDR(fp_offset);
238 }
239
240 static void r500_rs_tex(struct r300_rs_block* rs, int id, int ptr,
241 enum r300_rs_swizzle swiz)
242 {
243 int rs_tex_comp = ptr*4;
244
245 if (swiz == SWIZ_X001) {
246 rs->ip[id] |= R500_RS_SEL_S(rs_tex_comp) |
247 R500_RS_SEL_T(R500_RS_IP_PTR_K0) |
248 R500_RS_SEL_R(R500_RS_IP_PTR_K0) |
249 R500_RS_SEL_Q(R500_RS_IP_PTR_K1);
250 } else if (swiz == SWIZ_XY01) {
251 rs->ip[id] |= R500_RS_SEL_S(rs_tex_comp) |
252 R500_RS_SEL_T(rs_tex_comp + 1) |
253 R500_RS_SEL_R(R500_RS_IP_PTR_K0) |
254 R500_RS_SEL_Q(R500_RS_IP_PTR_K1);
255 } else {
256 rs->ip[id] |= R500_RS_SEL_S(rs_tex_comp) |
257 R500_RS_SEL_T(rs_tex_comp + 1) |
258 R500_RS_SEL_R(rs_tex_comp + 2) |
259 R500_RS_SEL_Q(rs_tex_comp + 3);
260 }
261 rs->inst[id] |= R500_RS_INST_TEX_ID(id);
262 }
263
264 static void r500_rs_tex_write(struct r300_rs_block* rs, int id, int fp_offset)
265 {
266 rs->inst[id] |= R500_RS_INST_TEX_CN_WRITE |
267 R500_RS_INST_TEX_ADDR(fp_offset);
268 }
269
270 /* Set up the RS block.
271 *
272 * This is the part of the chipset that actually does the rasterization
273 * of vertices into fragments. This is also the part of the chipset that
274 * locks up if any part of it is even slightly wrong. */
275 static void r300_update_rs_block(struct r300_context* r300,
276 struct r300_shader_semantics* vs_outputs,
277 struct r300_shader_semantics* fs_inputs)
278 {
279 struct r300_rs_block rs = { { 0 } };
280 int i, col_count = 0, tex_count = 0, fp_offset = 0, count;
281 void (*rX00_rs_col)(struct r300_rs_block*, int, int, enum r300_rs_swizzle);
282 void (*rX00_rs_col_write)(struct r300_rs_block*, int, int);
283 void (*rX00_rs_tex)(struct r300_rs_block*, int, int, enum r300_rs_swizzle);
284 void (*rX00_rs_tex_write)(struct r300_rs_block*, int, int);
285 boolean any_bcolor_used = vs_outputs->bcolor[0] != ATTR_UNUSED ||
286 vs_outputs->bcolor[1] != ATTR_UNUSED;
287
288 if (r300->screen->caps.is_r500) {
289 rX00_rs_col = r500_rs_col;
290 rX00_rs_col_write = r500_rs_col_write;
291 rX00_rs_tex = r500_rs_tex;
292 rX00_rs_tex_write = r500_rs_tex_write;
293 } else {
294 rX00_rs_col = r300_rs_col;
295 rX00_rs_col_write = r300_rs_col_write;
296 rX00_rs_tex = r300_rs_tex;
297 rX00_rs_tex_write = r300_rs_tex_write;
298 }
299
300 /* Rasterize colors. */
301 for (i = 0; i < ATTR_COLOR_COUNT; i++) {
302 if (vs_outputs->color[i] != ATTR_UNUSED || any_bcolor_used ||
303 vs_outputs->color[1] != ATTR_UNUSED) {
304 /* Always rasterize if it's written by the VS,
305 * otherwise it locks up. */
306 rX00_rs_col(&rs, col_count, col_count, SWIZ_XYZW);
307
308 /* Write it to the FS input register if it's used by the FS. */
309 if (fs_inputs->color[i] != ATTR_UNUSED) {
310 rX00_rs_col_write(&rs, col_count, fp_offset);
311 fp_offset++;
312
313 DBG(r300, DBG_RS,
314 "r300: Rasterized color %i written to FS.\n", i);
315 } else {
316 DBG(r300, DBG_RS, "r300: Rasterized color %i unused.\n", i);
317 }
318 col_count++;
319 } else {
320 /* Skip the FS input register, leave it uninitialized. */
321 /* If we try to set it to (0,0,0,1), it will lock up. */
322 if (fs_inputs->color[i] != ATTR_UNUSED) {
323 fp_offset++;
324
325 DBG(r300, DBG_RS, "r300: FS input color %i unassigned%s.\n",
326 i);
327 }
328 }
329 }
330
331 /* Rasterize texture coordinates. */
332 for (i = 0; i < ATTR_GENERIC_COUNT; i++) {
333 bool sprite_coord = !!(r300->sprite_coord_enable & (1 << i));
334
335 if (vs_outputs->generic[i] != ATTR_UNUSED || sprite_coord) {
336 /* Always rasterize if it's written by the VS,
337 * otherwise it locks up. */
338 rX00_rs_tex(&rs, tex_count, tex_count,
339 sprite_coord ? SWIZ_XY01 : SWIZ_XYZW);
340
341 /* Write it to the FS input register if it's used by the FS. */
342 if (fs_inputs->generic[i] != ATTR_UNUSED) {
343 rX00_rs_tex_write(&rs, tex_count, fp_offset);
344 fp_offset++;
345
346 DBG(r300, DBG_RS,
347 "r300: Rasterized generic %i written to FS%s.\n",
348 i, sprite_coord ? " (sprite coord)" : "");
349 } else {
350 DBG(r300, DBG_RS,
351 "r300: Rasterized generic %i unused%s.\n",
352 i, sprite_coord ? " (sprite coord)" : "");
353 }
354 tex_count++;
355 } else {
356 /* Skip the FS input register, leave it uninitialized. */
357 /* If we try to set it to (0,0,0,1), it will lock up. */
358 if (fs_inputs->generic[i] != ATTR_UNUSED) {
359 fp_offset++;
360
361 DBG(r300, DBG_RS, "r300: FS input generic %i unassigned%s.\n",
362 i, sprite_coord ? " (sprite coord)" : "");
363 }
364 }
365 }
366
367 /* Rasterize fog coordinates. */
368 if (vs_outputs->fog != ATTR_UNUSED) {
369 /* Always rasterize if it's written by the VS,
370 * otherwise it locks up. */
371 rX00_rs_tex(&rs, tex_count, tex_count, SWIZ_X001);
372
373 /* Write it to the FS input register if it's used by the FS. */
374 if (fs_inputs->fog != ATTR_UNUSED) {
375 rX00_rs_tex_write(&rs, tex_count, fp_offset);
376 fp_offset++;
377
378 DBG(r300, DBG_RS, "r300: Rasterized fog written to FS.\n");
379 } else {
380 DBG(r300, DBG_RS, "r300: Rasterized fog unused.\n");
381 }
382 tex_count++;
383 } else {
384 /* Skip the FS input register, leave it uninitialized. */
385 /* If we try to set it to (0,0,0,1), it will lock up. */
386 if (fs_inputs->fog != ATTR_UNUSED) {
387 fp_offset++;
388
389 DBG(r300, DBG_RS, "r300: FS input fog unassigned.\n");
390 }
391 }
392
393 /* Rasterize WPOS. */
394 /* If the FS doesn't need it, it's not written by the VS. */
395 if (vs_outputs->wpos != ATTR_UNUSED && fs_inputs->wpos != ATTR_UNUSED) {
396 rX00_rs_tex(&rs, tex_count, vs_tex_count, SWIZ_XYZW);
397 rX00_rs_tex_write(&rs, tex_count, fp_offset);
398
399 DBG(r300, DBG_RS, "r300: Rasterized WPOS written to FS.\n");
400
401 fp_offset++;
402 tex_count++;
403 vs_tex_count++;
404 }
405
406 /* Rasterize at least one color, or bad things happen. */
407 if (col_count == 0 && tex_count == 0) {
408 rX00_rs_col(&rs, 0, 0, SWIZ_0001);
409 col_count++;
410
411 DBG(r300, DBG_RS, "r300: Rasterized color 0 to prevent lockups.\n");
412 }
413
414 DBG(r300, DBG_RS, "r300: --- Rasterizer status ---: colors: %i, "
415 "generics: %i.\n", col_count, tex_count);
416
417 rs.count = (tex_count*4) | (col_count << R300_IC_COUNT_SHIFT) |
418 R300_HIRES_EN;
419
420 count = MAX3(col_count, tex_count, 1);
421 rs.inst_count = count - 1;
422
423 /* Now, after all that, see if we actually need to update the state. */
424 if (memcmp(r300->rs_block_state.state, &rs, sizeof(struct r300_rs_block))) {
425 memcpy(r300->rs_block_state.state, &rs, sizeof(struct r300_rs_block));
426 r300->rs_block_state.size = 5 + count*2;
427 }
428 }
429
430 /* Update the shader-dependant states. */
431 static void r300_update_derived_shader_state(struct r300_context* r300)
432 {
433 struct r300_vertex_shader* vs = r300->vs_state.state;
434
435 r300_update_rs_block(r300, &vs->outputs, &r300_fs(r300)->shader->inputs);
436 }
437
438 static void r300_merge_textures_and_samplers(struct r300_context* r300)
439 {
440 struct r300_textures_state *state =
441 (struct r300_textures_state*)r300->textures_state.state;
442 struct r300_texture_sampler_state *texstate;
443 struct r300_sampler_state *sampler;
444 struct r300_sampler_view *view;
445 struct r300_texture *tex;
446 unsigned min_level, max_level, i, size;
447 unsigned count = MIN2(state->sampler_view_count,
448 state->sampler_state_count);
449
450 state->tx_enable = 0;
451 state->count = 0;
452 size = 2;
453
454 for (i = 0; i < count; i++) {
455 if (state->sampler_views[i] && state->sampler_states[i]) {
456 state->tx_enable |= 1 << i;
457
458 view = state->sampler_views[i];
459 tex = r300_texture(view->base.texture);
460 sampler = state->sampler_states[i];
461
462 texstate = &state->regs[i];
463 texstate->format = view->format;
464 texstate->filter0 = sampler->filter0;
465 texstate->filter1 = sampler->filter1;
466 texstate->border_color = sampler->border_color;
467
468 /* to emulate 1D textures through 2D ones correctly */
469 if (tex->b.b.target == PIPE_TEXTURE_1D) {
470 texstate->filter0 &= ~R300_TX_WRAP_T_MASK;
471 texstate->filter0 |= R300_TX_WRAP_T(R300_TX_CLAMP_TO_EDGE);
472 }
473
474 if (tex->uses_pitch) {
475 /* NPOT textures don't support mip filter, unfortunately.
476 * This prevents incorrect rendering. */
477 texstate->filter0 &= ~R300_TX_MIN_FILTER_MIP_MASK;
478
479 /* Mask out the mirrored flag. */
480 if (texstate->filter0 & R300_TX_WRAP_S(R300_TX_MIRRORED)) {
481 texstate->filter0 &= ~R300_TX_WRAP_S(R300_TX_MIRRORED);
482 }
483 if (texstate->filter0 & R300_TX_WRAP_T(R300_TX_MIRRORED)) {
484 texstate->filter0 &= ~R300_TX_WRAP_T(R300_TX_MIRRORED);
485 }
486
487 /* Change repeat to clamp-to-edge.
488 * (the repeat bit has a value of 0, no masking needed). */
489 if ((texstate->filter0 & R300_TX_WRAP_S_MASK) ==
490 R300_TX_WRAP_S(R300_TX_REPEAT)) {
491 texstate->filter0 |= R300_TX_WRAP_S(R300_TX_CLAMP_TO_EDGE);
492 }
493 if ((texstate->filter0 & R300_TX_WRAP_T_MASK) ==
494 R300_TX_WRAP_T(R300_TX_REPEAT)) {
495 texstate->filter0 |= R300_TX_WRAP_T(R300_TX_CLAMP_TO_EDGE);
496 }
497 } else {
498 /* determine min/max levels */
499 /* the MAX_MIP level is the largest (finest) one */
500 max_level = MIN3(sampler->max_lod + view->base.first_level,
501 tex->b.b.last_level, view->base.last_level);
502 min_level = MIN2(sampler->min_lod + view->base.first_level,
503 max_level);
504 texstate->format.format0 |= R300_TX_NUM_LEVELS(max_level);
505 texstate->filter0 |= R300_TX_MAX_MIP_LEVEL(min_level);
506 }
507
508 texstate->filter0 |= i << 28;
509
510 size += 16;
511 state->count = i+1;
512 }
513 }
514
515 r300->textures_state.size = size;
516
517 /* Pick a fragment shader based on either the texture compare state
518 * or the uses_pitch flag. */
519 if (r300->fs.state && count) {
520 if (r300_pick_fragment_shader(r300)) {
521 r300_mark_fs_code_dirty(r300);
522 }
523 }
524 }
525
526 void r300_update_derived_state(struct r300_context* r300)
527 {
528 if (r300->textures_state.dirty) {
529 r300_merge_textures_and_samplers(r300);
530 }
531
532 if (r300->rs_block_state.dirty) {
533 r300_update_derived_shader_state(r300);
534 }
535
536 if (r300->draw) {
537 memset(&r300->vertex_info, 0, sizeof(struct vertex_info));
538 r300_draw_emit_all_attribs(r300);
539 draw_compute_vertex_size(&r300->vertex_info);
540 r300_swtcl_vertex_psc(r300);
541 }
542
543 r300_update_hyperz_state(r300);
544 }