2 * Copyright 2008 Corbin Simpson <MostAwesomeDude@gmail.com>
3 * Copyright 2009 Marek Olšák <maraeo@gmail.com>
5 * Permission is hereby granted, free of charge, to any person obtaining a
6 * copy of this software and associated documentation files (the "Software"),
7 * to deal in the Software without restriction, including without limitation
8 * on the rights to use, copy, modify, merge, publish, distribute, sub
9 * license, and/or sell copies of the Software, and to permit persons to whom
10 * the Software is furnished to do so, subject to the following conditions:
12 * The above copyright notice and this permission notice (including the next
13 * paragraph) shall be included in all copies or substantial portions of the
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
19 * THE AUTHOR(S) AND/OR THEIR SUPPLIERS BE LIABLE FOR ANY CLAIM,
20 * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
21 * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
22 * USE OR OTHER DEALINGS IN THE SOFTWARE. */
24 #include "draw/draw_context.h"
26 #include "util/u_math.h"
27 #include "util/u_memory.h"
29 #include "r300_context.h"
31 #include "r300_hyperz.h"
32 #include "r300_screen.h"
33 #include "r300_shader_semantics.h"
34 #include "r300_state_derived.h"
35 #include "r300_state_inlines.h"
36 #include "r300_texture.h"
39 /* r300_state_derived: Various bits of state which are dependent upon
40 * currently bound CSO data. */
42 enum r300_rs_swizzle
{
49 static void r300_draw_emit_attrib(struct r300_context
* r300
,
50 enum attrib_emit emit
,
51 enum interp_mode interp
,
54 struct r300_vertex_shader
* vs
= r300
->vs_state
.state
;
55 struct tgsi_shader_info
* info
= &vs
->info
;
58 output
= draw_find_shader_output(r300
->draw
,
59 info
->output_semantic_name
[index
],
60 info
->output_semantic_index
[index
]);
61 draw_emit_vertex_attr(&r300
->vertex_info
, emit
, interp
, output
);
64 static void r300_draw_emit_all_attribs(struct r300_context
* r300
)
66 struct r300_vertex_shader
* vs
= r300
->vs_state
.state
;
67 struct r300_shader_semantics
* vs_outputs
= &vs
->outputs
;
71 if (vs_outputs
->pos
!= ATTR_UNUSED
) {
72 r300_draw_emit_attrib(r300
, EMIT_4F
, INTERP_PERSPECTIVE
,
79 if (vs_outputs
->psize
!= ATTR_UNUSED
) {
80 r300_draw_emit_attrib(r300
, EMIT_1F_PSIZE
, INTERP_POS
,
85 for (i
= 0; i
< ATTR_COLOR_COUNT
; i
++) {
86 if (vs_outputs
->color
[i
] != ATTR_UNUSED
) {
87 r300_draw_emit_attrib(r300
, EMIT_4F
, INTERP_LINEAR
,
88 vs_outputs
->color
[i
]);
92 /* Back-face colors. */
93 for (i
= 0; i
< ATTR_COLOR_COUNT
; i
++) {
94 if (vs_outputs
->bcolor
[i
] != ATTR_UNUSED
) {
95 r300_draw_emit_attrib(r300
, EMIT_4F
, INTERP_LINEAR
,
96 vs_outputs
->bcolor
[i
]);
100 /* Texture coordinates. */
101 /* Only 8 generic vertex attributes can be used. If there are more,
102 * they won't be rasterized. */
104 for (i
= 0; i
< ATTR_GENERIC_COUNT
&& gen_count
< 8; i
++) {
105 if (vs_outputs
->generic
[i
] != ATTR_UNUSED
&&
106 !(r300
->sprite_coord_enable
& (1 << i
))) {
107 r300_draw_emit_attrib(r300
, EMIT_4F
, INTERP_PERSPECTIVE
,
108 vs_outputs
->generic
[i
]);
113 /* Fog coordinates. */
114 if (gen_count
< 8 && vs_outputs
->fog
!= ATTR_UNUSED
) {
115 r300_draw_emit_attrib(r300
, EMIT_4F
, INTERP_PERSPECTIVE
,
121 if (r300_fs(r300
)->shader
->inputs
.wpos
!= ATTR_UNUSED
&& gen_count
< 8) {
122 DBG(r300
, DBG_SWTCL
, "draw_emit_attrib: WPOS, index: %i\n",
124 r300_draw_emit_attrib(r300
, EMIT_4F
, INTERP_PERSPECTIVE
,
129 /* Update the PSC tables for SW TCL, using Draw. */
130 static void r300_swtcl_vertex_psc(struct r300_context
*r300
)
132 struct r300_vertex_stream_state
*vstream
= r300
->vertex_stream_state
.state
;
133 struct vertex_info
*vinfo
= &r300
->vertex_info
;
134 uint16_t type
, swizzle
;
135 enum pipe_format format
;
136 unsigned i
, attrib_count
;
137 int* vs_output_tab
= r300
->stream_loc_notcl
;
139 memset(vstream
, 0, sizeof(struct r300_vertex_stream_state
));
141 /* For each Draw attribute, route it to the fragment shader according
142 * to the vs_output_tab. */
143 attrib_count
= vinfo
->num_attribs
;
144 DBG(r300
, DBG_SWTCL
, "r300: attrib count: %d\n", attrib_count
);
145 for (i
= 0; i
< attrib_count
; i
++) {
146 if (vs_output_tab
[i
] == -1) {
151 format
= draw_translate_vinfo_format(vinfo
->attrib
[i
].emit
);
154 "r300: swtcl_vertex_psc [%i] <- %s\n",
155 vs_output_tab
[i
], util_format_short_name(format
));
157 /* Obtain the type of data in this attribute. */
158 type
= r300_translate_vertex_data_type(format
);
159 if (type
== R300_INVALID_FORMAT
) {
160 fprintf(stderr
, "r300: Bad vertex format %s.\n",
161 util_format_short_name(format
));
166 type
|= vs_output_tab
[i
] << R300_DST_VEC_LOC_SHIFT
;
168 /* Obtain the swizzle for this attribute. Note that the default
169 * swizzle in the hardware is not XYZW! */
170 swizzle
= r300_translate_vertex_data_swizzle(format
);
172 /* Add the attribute to the PSC table. */
174 vstream
->vap_prog_stream_cntl
[i
>> 1] |= type
<< 16;
175 vstream
->vap_prog_stream_cntl_ext
[i
>> 1] |= swizzle
<< 16;
177 vstream
->vap_prog_stream_cntl
[i
>> 1] |= type
;
178 vstream
->vap_prog_stream_cntl_ext
[i
>> 1] |= swizzle
;
182 /* Set the last vector in the PSC. */
186 vstream
->vap_prog_stream_cntl
[i
>> 1] |=
187 (R300_LAST_VEC
<< (i
& 1 ? 16 : 0));
189 vstream
->count
= (i
>> 1) + 1;
190 r300
->vertex_stream_state
.dirty
= TRUE
;
191 r300
->vertex_stream_state
.size
= (1 + vstream
->count
) * 2;
194 static void r300_rs_col(struct r300_rs_block
* rs
, int id
, int ptr
,
195 enum r300_rs_swizzle swiz
)
197 rs
->ip
[id
] |= R300_RS_COL_PTR(ptr
);
198 if (swiz
== SWIZ_0001
) {
199 rs
->ip
[id
] |= R300_RS_COL_FMT(R300_RS_COL_FMT_0001
);
201 rs
->ip
[id
] |= R300_RS_COL_FMT(R300_RS_COL_FMT_RGBA
);
203 rs
->inst
[id
] |= R300_RS_INST_COL_ID(id
);
206 static void r300_rs_col_write(struct r300_rs_block
* rs
, int id
, int fp_offset
)
208 rs
->inst
[id
] |= R300_RS_INST_COL_CN_WRITE
|
209 R300_RS_INST_COL_ADDR(fp_offset
);
212 static void r300_rs_tex(struct r300_rs_block
* rs
, int id
, int ptr
,
213 enum r300_rs_swizzle swiz
)
215 if (swiz
== SWIZ_X001
) {
216 rs
->ip
[id
] |= R300_RS_TEX_PTR(ptr
) |
217 R300_RS_SEL_S(R300_RS_SEL_C0
) |
218 R300_RS_SEL_T(R300_RS_SEL_K0
) |
219 R300_RS_SEL_R(R300_RS_SEL_K0
) |
220 R300_RS_SEL_Q(R300_RS_SEL_K1
);
221 } else if (swiz
== SWIZ_XY01
) {
222 rs
->ip
[id
] |= R300_RS_TEX_PTR(ptr
) |
223 R300_RS_SEL_S(R300_RS_SEL_C0
) |
224 R300_RS_SEL_T(R300_RS_SEL_C1
) |
225 R300_RS_SEL_R(R300_RS_SEL_K0
) |
226 R300_RS_SEL_Q(R300_RS_SEL_K1
);
228 rs
->ip
[id
] |= R300_RS_TEX_PTR(ptr
) |
229 R300_RS_SEL_S(R300_RS_SEL_C0
) |
230 R300_RS_SEL_T(R300_RS_SEL_C1
) |
231 R300_RS_SEL_R(R300_RS_SEL_C2
) |
232 R300_RS_SEL_Q(R300_RS_SEL_C3
);
234 rs
->inst
[id
] |= R300_RS_INST_TEX_ID(id
);
237 static void r300_rs_tex_write(struct r300_rs_block
* rs
, int id
, int fp_offset
)
239 rs
->inst
[id
] |= R300_RS_INST_TEX_CN_WRITE
|
240 R300_RS_INST_TEX_ADDR(fp_offset
);
243 static void r500_rs_col(struct r300_rs_block
* rs
, int id
, int ptr
,
244 enum r300_rs_swizzle swiz
)
246 rs
->ip
[id
] |= R500_RS_COL_PTR(ptr
);
247 if (swiz
== SWIZ_0001
) {
248 rs
->ip
[id
] |= R500_RS_COL_FMT(R300_RS_COL_FMT_0001
);
250 rs
->ip
[id
] |= R500_RS_COL_FMT(R300_RS_COL_FMT_RGBA
);
252 rs
->inst
[id
] |= R500_RS_INST_COL_ID(id
);
255 static void r500_rs_col_write(struct r300_rs_block
* rs
, int id
, int fp_offset
)
257 rs
->inst
[id
] |= R500_RS_INST_COL_CN_WRITE
|
258 R500_RS_INST_COL_ADDR(fp_offset
);
261 static void r500_rs_tex(struct r300_rs_block
* rs
, int id
, int ptr
,
262 enum r300_rs_swizzle swiz
)
264 if (swiz
== SWIZ_X001
) {
265 rs
->ip
[id
] |= R500_RS_SEL_S(ptr
) |
266 R500_RS_SEL_T(R500_RS_IP_PTR_K0
) |
267 R500_RS_SEL_R(R500_RS_IP_PTR_K0
) |
268 R500_RS_SEL_Q(R500_RS_IP_PTR_K1
);
269 } else if (swiz
== SWIZ_XY01
) {
270 rs
->ip
[id
] |= R500_RS_SEL_S(ptr
) |
271 R500_RS_SEL_T(ptr
+ 1) |
272 R500_RS_SEL_R(R500_RS_IP_PTR_K0
) |
273 R500_RS_SEL_Q(R500_RS_IP_PTR_K1
);
275 rs
->ip
[id
] |= R500_RS_SEL_S(ptr
) |
276 R500_RS_SEL_T(ptr
+ 1) |
277 R500_RS_SEL_R(ptr
+ 2) |
278 R500_RS_SEL_Q(ptr
+ 3);
280 rs
->inst
[id
] |= R500_RS_INST_TEX_ID(id
);
283 static void r500_rs_tex_write(struct r300_rs_block
* rs
, int id
, int fp_offset
)
285 rs
->inst
[id
] |= R500_RS_INST_TEX_CN_WRITE
|
286 R500_RS_INST_TEX_ADDR(fp_offset
);
289 /* Set up the RS block.
291 * This is the part of the chipset that is responsible for linking vertex
292 * and fragment shaders and stuffed texture coordinates.
294 * The rasterizer reads data from VAP, which produces vertex shader outputs,
295 * and GA, which produces stuffed texture coordinates. VAP outputs have
296 * precedence over GA. All outputs must be rasterized otherwise it locks up.
297 * If there are more outputs rasterized than is set in VAP/GA, it locks up
298 * too. The funky part is that this info has been pretty much obtained by trial
300 static void r300_update_rs_block(struct r300_context
*r300
)
302 struct r300_vertex_shader
*vs
= r300
->vs_state
.state
;
303 struct r300_shader_semantics
*vs_outputs
= &vs
->outputs
;
304 struct r300_shader_semantics
*fs_inputs
= &r300_fs(r300
)->shader
->inputs
;
305 struct r300_rs_block rs
= {0};
306 int i
, col_count
= 0, tex_count
= 0, fp_offset
= 0, count
, loc
= 0, tex_ptr
= 0;
307 void (*rX00_rs_col
)(struct r300_rs_block
*, int, int, enum r300_rs_swizzle
);
308 void (*rX00_rs_col_write
)(struct r300_rs_block
*, int, int);
309 void (*rX00_rs_tex
)(struct r300_rs_block
*, int, int, enum r300_rs_swizzle
);
310 void (*rX00_rs_tex_write
)(struct r300_rs_block
*, int, int);
311 boolean any_bcolor_used
= vs_outputs
->bcolor
[0] != ATTR_UNUSED
||
312 vs_outputs
->bcolor
[1] != ATTR_UNUSED
;
313 int *stream_loc_notcl
= r300
->stream_loc_notcl
;
315 if (r300
->screen
->caps
.is_r500
) {
316 rX00_rs_col
= r500_rs_col
;
317 rX00_rs_col_write
= r500_rs_col_write
;
318 rX00_rs_tex
= r500_rs_tex
;
319 rX00_rs_tex_write
= r500_rs_tex_write
;
321 rX00_rs_col
= r300_rs_col
;
322 rX00_rs_col_write
= r300_rs_col_write
;
323 rX00_rs_tex
= r300_rs_tex
;
324 rX00_rs_tex_write
= r300_rs_tex_write
;
327 /* The position is always present in VAP. */
328 rs
.vap_vsm_vtx_assm
|= R300_INPUT_CNTL_POS
;
329 rs
.vap_out_vtx_fmt
[0] |= R300_VAP_OUTPUT_VTX_FMT_0__POS_PRESENT
;
330 stream_loc_notcl
[loc
++] = 0;
332 /* Set up the point size in VAP. */
333 if (vs_outputs
->psize
!= ATTR_UNUSED
) {
334 rs
.vap_out_vtx_fmt
[0] |= R300_VAP_OUTPUT_VTX_FMT_0__PT_SIZE_PRESENT
;
335 stream_loc_notcl
[loc
++] = 1;
338 /* Set up and rasterize colors. */
339 for (i
= 0; i
< ATTR_COLOR_COUNT
; i
++) {
340 if (vs_outputs
->color
[i
] != ATTR_UNUSED
|| any_bcolor_used
||
341 vs_outputs
->color
[1] != ATTR_UNUSED
) {
342 /* Set up the color in VAP. */
343 rs
.vap_vsm_vtx_assm
|= R300_INPUT_CNTL_COLOR
;
344 rs
.vap_out_vtx_fmt
[0] |=
345 R300_VAP_OUTPUT_VTX_FMT_0__COLOR_0_PRESENT
<< i
;
346 stream_loc_notcl
[loc
++] = 2 + i
;
349 rX00_rs_col(&rs
, col_count
, col_count
, SWIZ_XYZW
);
351 /* Write it to the FS input register if it's needed by the FS. */
352 if (fs_inputs
->color
[i
] != ATTR_UNUSED
) {
353 rX00_rs_col_write(&rs
, col_count
, fp_offset
);
357 "r300: Rasterized color %i written to FS.\n", i
);
359 DBG(r300
, DBG_RS
, "r300: Rasterized color %i unused.\n", i
);
363 /* Skip the FS input register, leave it uninitialized. */
364 /* If we try to set it to (0,0,0,1), it will lock up. */
365 if (fs_inputs
->color
[i
] != ATTR_UNUSED
) {
368 DBG(r300
, DBG_RS
, "r300: FS input color %i unassigned%s.\n",
374 /* Set up back-face colors. The rasterizer will do the color selection
376 if (any_bcolor_used
) {
377 if (r300
->two_sided_color
) {
378 /* Rasterize as back-face colors. */
379 for (i
= 0; i
< ATTR_COLOR_COUNT
; i
++) {
380 rs
.vap_vsm_vtx_assm
|= R300_INPUT_CNTL_COLOR
;
381 rs
.vap_out_vtx_fmt
[0] |= R300_VAP_OUTPUT_VTX_FMT_0__COLOR_0_PRESENT
<< (2+i
);
382 stream_loc_notcl
[loc
++] = 4 + i
;
385 /* Rasterize two fake texcoords to prevent from the two-sided color
387 /* XXX Consider recompiling the vertex shader to save 2 RS units. */
388 for (i
= 0; i
< 2; i
++) {
389 rs
.vap_vsm_vtx_assm
|= (R300_INPUT_CNTL_TC0
<< tex_count
);
390 rs
.vap_out_vtx_fmt
[1] |= (4 << (3 * tex_count
));
391 stream_loc_notcl
[loc
++] = 6 + tex_count
;
394 rX00_rs_tex(&rs
, tex_count
, tex_ptr
, SWIZ_XYZW
);
401 /* Rasterize texture coordinates. */
402 for (i
= 0; i
< ATTR_GENERIC_COUNT
&& tex_count
< 8; i
++) {
403 bool sprite_coord
= !!(r300
->sprite_coord_enable
& (1 << i
));
405 if (vs_outputs
->generic
[i
] != ATTR_UNUSED
|| sprite_coord
) {
407 /* Set up the texture coordinates in VAP. */
408 rs
.vap_vsm_vtx_assm
|= (R300_INPUT_CNTL_TC0
<< tex_count
);
409 rs
.vap_out_vtx_fmt
[1] |= (4 << (3 * tex_count
));
410 stream_loc_notcl
[loc
++] = 6 + tex_count
;
414 rX00_rs_tex(&rs
, tex_count
, tex_ptr
,
415 sprite_coord
? SWIZ_XY01
: SWIZ_XYZW
);
417 /* Write it to the FS input register if it's needed by the FS. */
418 if (fs_inputs
->generic
[i
] != ATTR_UNUSED
) {
419 rX00_rs_tex_write(&rs
, tex_count
, fp_offset
);
423 "r300: Rasterized generic %i written to FS%s.\n",
424 i
, sprite_coord
? " (sprite coord)" : "");
427 "r300: Rasterized generic %i unused%s.\n",
428 i
, sprite_coord
? " (sprite coord)" : "");
431 tex_ptr
+= sprite_coord
? 2 : 4;
433 /* Skip the FS input register, leave it uninitialized. */
434 /* If we try to set it to (0,0,0,1), it will lock up. */
435 if (fs_inputs
->generic
[i
] != ATTR_UNUSED
) {
438 DBG(r300
, DBG_RS
, "r300: FS input generic %i unassigned%s.\n",
439 i
, sprite_coord
? " (sprite coord)" : "");
444 /* Rasterize fog coordinates. */
445 if (vs_outputs
->fog
!= ATTR_UNUSED
&& tex_count
< 8) {
446 /* Set up the fog coordinates in VAP. */
447 rs
.vap_vsm_vtx_assm
|= (R300_INPUT_CNTL_TC0
<< tex_count
);
448 rs
.vap_out_vtx_fmt
[1] |= (4 << (3 * tex_count
));
449 stream_loc_notcl
[loc
++] = 6 + tex_count
;
452 rX00_rs_tex(&rs
, tex_count
, tex_ptr
, SWIZ_X001
);
454 /* Write it to the FS input register if it's needed by the FS. */
455 if (fs_inputs
->fog
!= ATTR_UNUSED
) {
456 rX00_rs_tex_write(&rs
, tex_count
, fp_offset
);
459 DBG(r300
, DBG_RS
, "r300: Rasterized fog written to FS.\n");
461 DBG(r300
, DBG_RS
, "r300: Rasterized fog unused.\n");
466 /* Skip the FS input register, leave it uninitialized. */
467 /* If we try to set it to (0,0,0,1), it will lock up. */
468 if (fs_inputs
->fog
!= ATTR_UNUSED
) {
471 DBG(r300
, DBG_RS
, "r300: FS input fog unassigned.\n");
475 /* Rasterize WPOS. */
476 /* Don't set it in VAP if the FS doesn't need it. */
477 if (fs_inputs
->wpos
!= ATTR_UNUSED
&& tex_count
< 8) {
478 /* Set up the WPOS coordinates in VAP. */
479 rs
.vap_vsm_vtx_assm
|= (R300_INPUT_CNTL_TC0
<< tex_count
);
480 rs
.vap_out_vtx_fmt
[1] |= (4 << (3 * tex_count
));
481 stream_loc_notcl
[loc
++] = 6 + tex_count
;
484 rX00_rs_tex(&rs
, tex_count
, tex_ptr
, SWIZ_XYZW
);
486 /* Write it to the FS input register. */
487 rX00_rs_tex_write(&rs
, tex_count
, fp_offset
);
489 DBG(r300
, DBG_RS
, "r300: Rasterized WPOS written to FS.\n");
496 /* Invalidate the rest of the no-TCL (GA) stream locations. */
498 stream_loc_notcl
[loc
++] = -1;
501 /* Rasterize at least one color, or bad things happen. */
502 if (col_count
== 0 && tex_count
== 0) {
503 rX00_rs_col(&rs
, 0, 0, SWIZ_0001
);
506 DBG(r300
, DBG_RS
, "r300: Rasterized color 0 to prevent lockups.\n");
509 DBG(r300
, DBG_RS
, "r300: --- Rasterizer status ---: colors: %i, "
510 "generics: %i.\n", col_count
, tex_count
);
512 rs
.count
= MIN2(tex_ptr
, 32) | (col_count
<< R300_IC_COUNT_SHIFT
) |
515 count
= MAX3(col_count
, tex_count
, 1);
516 rs
.inst_count
= count
- 1;
518 /* Now, after all that, see if we actually need to update the state. */
519 if (memcmp(r300
->rs_block_state
.state
, &rs
, sizeof(struct r300_rs_block
))) {
520 memcpy(r300
->rs_block_state
.state
, &rs
, sizeof(struct r300_rs_block
));
521 r300
->rs_block_state
.size
= 11 + count
*2;
525 static void r300_merge_textures_and_samplers(struct r300_context
* r300
)
527 struct r300_textures_state
*state
=
528 (struct r300_textures_state
*)r300
->textures_state
.state
;
529 struct r300_texture_sampler_state
*texstate
;
530 struct r300_sampler_state
*sampler
;
531 struct r300_sampler_view
*view
;
532 struct r300_texture
*tex
;
533 unsigned min_level
, max_level
, i
, j
, size
;
534 unsigned count
= MIN2(state
->sampler_view_count
,
535 state
->sampler_state_count
);
537 /* The KIL opcode fix, see below. */
538 if (!count
&& !r300
->screen
->caps
.is_r500
)
541 state
->tx_enable
= 0;
545 for (i
= 0; i
< count
; i
++) {
546 if (state
->sampler_views
[i
] && state
->sampler_states
[i
]) {
547 state
->tx_enable
|= 1 << i
;
549 view
= state
->sampler_views
[i
];
550 tex
= r300_texture(view
->base
.texture
);
551 sampler
= state
->sampler_states
[i
];
553 texstate
= &state
->regs
[i
];
554 texstate
->format
= view
->format
;
555 texstate
->filter0
= sampler
->filter0
;
556 texstate
->filter1
= sampler
->filter1
;
557 texstate
->border_color
= sampler
->border_color
;
559 /* Assign a texture cache region. */
560 texstate
->format
.format1
|= view
->texcache_region
;
562 /* Depth textures are kinda special. */
563 if (util_format_is_depth_or_stencil(tex
->desc
.b
.b
.format
)) {
564 unsigned char depth_swizzle
[4];
566 if (!r300
->screen
->caps
.is_r500
&&
567 util_format_get_blocksizebits(tex
->desc
.b
.b
.format
) == 32) {
568 /* X24x8 is sampled as Y16X16 on r3xx-r4xx.
569 * The depth here is at the Y component. */
570 for (j
= 0; j
< 4; j
++)
571 depth_swizzle
[j
] = UTIL_FORMAT_SWIZZLE_Y
;
573 for (j
= 0; j
< 4; j
++)
574 depth_swizzle
[j
] = UTIL_FORMAT_SWIZZLE_X
;
577 /* If compare mode is disabled, sampler view swizzles
578 * are stored in the format.
579 * Otherwise, the swizzles must be applied after the compare
580 * mode in the fragment shader. */
581 if (sampler
->state
.compare_mode
== PIPE_TEX_COMPARE_NONE
) {
582 texstate
->format
.format1
|=
583 r300_get_swizzle_combined(depth_swizzle
,
586 texstate
->format
.format1
|=
587 r300_get_swizzle_combined(depth_swizzle
, 0);
591 /* to emulate 1D textures through 2D ones correctly */
592 if (tex
->desc
.b
.b
.target
== PIPE_TEXTURE_1D
) {
593 texstate
->filter0
&= ~R300_TX_WRAP_T_MASK
;
594 texstate
->filter0
|= R300_TX_WRAP_T(R300_TX_CLAMP_TO_EDGE
);
597 if (tex
->desc
.is_npot
) {
598 /* NPOT textures don't support mip filter, unfortunately.
599 * This prevents incorrect rendering. */
600 texstate
->filter0
&= ~R300_TX_MIN_FILTER_MIP_MASK
;
602 /* Mask out the mirrored flag. */
603 if (texstate
->filter0
& R300_TX_WRAP_S(R300_TX_MIRRORED
)) {
604 texstate
->filter0
&= ~R300_TX_WRAP_S(R300_TX_MIRRORED
);
606 if (texstate
->filter0
& R300_TX_WRAP_T(R300_TX_MIRRORED
)) {
607 texstate
->filter0
&= ~R300_TX_WRAP_T(R300_TX_MIRRORED
);
610 /* Change repeat to clamp-to-edge.
611 * (the repeat bit has a value of 0, no masking needed). */
612 if ((texstate
->filter0
& R300_TX_WRAP_S_MASK
) ==
613 R300_TX_WRAP_S(R300_TX_REPEAT
)) {
614 texstate
->filter0
|= R300_TX_WRAP_S(R300_TX_CLAMP_TO_EDGE
);
616 if ((texstate
->filter0
& R300_TX_WRAP_T_MASK
) ==
617 R300_TX_WRAP_T(R300_TX_REPEAT
)) {
618 texstate
->filter0
|= R300_TX_WRAP_T(R300_TX_CLAMP_TO_EDGE
);
621 /* determine min/max levels */
622 /* the MAX_MIP level is the largest (finest) one */
623 max_level
= MIN3(sampler
->max_lod
+ view
->base
.first_level
,
624 tex
->desc
.b
.b
.last_level
, view
->base
.last_level
);
625 min_level
= MIN2(sampler
->min_lod
+ view
->base
.first_level
,
627 texstate
->format
.format0
|= R300_TX_NUM_LEVELS(max_level
);
628 texstate
->filter0
|= R300_TX_MAX_MIP_LEVEL(min_level
);
631 texstate
->filter0
|= i
<< 28;
636 /* For the KIL opcode to work on r3xx-r4xx, the texture unit
637 * assigned to this opcode (it's always the first one) must be
638 * enabled. Otherwise the opcode doesn't work.
640 * In order to not depend on the fragment shader, we just make
641 * the first unit enabled all the time. */
642 if (i
== 0 && !r300
->screen
->caps
.is_r500
) {
643 pipe_sampler_view_reference(
644 (struct pipe_sampler_view
**)&state
->sampler_views
[i
],
645 &r300
->texkill_sampler
->base
);
647 state
->tx_enable
|= 1 << i
;
649 texstate
= &state
->regs
[i
];
651 /* Just set some valid state. */
652 texstate
->format
= r300
->texkill_sampler
->format
;
654 r300_translate_tex_filters(PIPE_TEX_FILTER_NEAREST
,
655 PIPE_TEX_FILTER_NEAREST
,
656 PIPE_TEX_FILTER_NEAREST
,
658 texstate
->filter1
= 0;
659 texstate
->border_color
= 0;
661 texstate
->filter0
|= i
<< 28;
668 r300
->textures_state
.size
= size
;
670 /* Pick a fragment shader based on either the texture compare state
671 * or the uses_pitch flag. */
672 if (r300
->fs
.state
&& count
) {
673 if (r300_pick_fragment_shader(r300
)) {
674 r300_mark_fs_code_dirty(r300
);
679 void r300_update_derived_state(struct r300_context
* r300
)
681 if (r300
->textures_state
.dirty
) {
682 r300_merge_textures_and_samplers(r300
);
685 if (r300
->rs_block_state
.dirty
) {
686 r300_update_rs_block(r300
);
689 memset(&r300
->vertex_info
, 0, sizeof(struct vertex_info
));
690 r300_draw_emit_all_attribs(r300
);
691 draw_compute_vertex_size(&r300
->vertex_info
);
692 r300_swtcl_vertex_psc(r300
);
696 r300_update_hyperz_state(r300
);