2 * Copyright 2008 Corbin Simpson <MostAwesomeDude@gmail.com>
3 * Copyright 2009 Marek Olšák <maraeo@gmail.com>
5 * Permission is hereby granted, free of charge, to any person obtaining a
6 * copy of this software and associated documentation files (the "Software"),
7 * to deal in the Software without restriction, including without limitation
8 * on the rights to use, copy, modify, merge, publish, distribute, sub
9 * license, and/or sell copies of the Software, and to permit persons to whom
10 * the Software is furnished to do so, subject to the following conditions:
12 * The above copyright notice and this permission notice (including the next
13 * paragraph) shall be included in all copies or substantial portions of the
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
19 * THE AUTHOR(S) AND/OR THEIR SUPPLIERS BE LIABLE FOR ANY CLAIM,
20 * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
21 * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
22 * USE OR OTHER DEALINGS IN THE SOFTWARE. */
24 #include "draw/draw_context.h"
26 #include "util/u_math.h"
27 #include "util/u_memory.h"
28 #include "util/u_pack_color.h"
30 #include "r300_context.h"
32 #include "r300_hyperz.h"
33 #include "r300_screen.h"
34 #include "r300_shader_semantics.h"
35 #include "r300_state_derived.h"
36 #include "r300_state_inlines.h"
37 #include "r300_texture.h"
40 /* r300_state_derived: Various bits of state which are dependent upon
41 * currently bound CSO data. */
43 enum r300_rs_swizzle
{
50 enum r300_rs_col_write_type
{
55 static void r300_draw_emit_attrib(struct r300_context
* r300
,
56 enum attrib_emit emit
,
57 enum interp_mode interp
,
60 struct r300_vertex_shader
* vs
= r300
->vs_state
.state
;
61 struct tgsi_shader_info
* info
= &vs
->info
;
64 output
= draw_find_shader_output(r300
->draw
,
65 info
->output_semantic_name
[index
],
66 info
->output_semantic_index
[index
]);
67 draw_emit_vertex_attr(&r300
->vertex_info
, emit
, interp
, output
);
70 static void r300_draw_emit_all_attribs(struct r300_context
* r300
)
72 struct r300_vertex_shader
* vs
= r300
->vs_state
.state
;
73 struct r300_shader_semantics
* vs_outputs
= &vs
->outputs
;
77 if (vs_outputs
->pos
!= ATTR_UNUSED
) {
78 r300_draw_emit_attrib(r300
, EMIT_4F
, INTERP_PERSPECTIVE
,
85 if (vs_outputs
->psize
!= ATTR_UNUSED
) {
86 r300_draw_emit_attrib(r300
, EMIT_1F_PSIZE
, INTERP_POS
,
91 for (i
= 0; i
< ATTR_COLOR_COUNT
; i
++) {
92 if (vs_outputs
->color
[i
] != ATTR_UNUSED
) {
93 r300_draw_emit_attrib(r300
, EMIT_4F
, INTERP_LINEAR
,
94 vs_outputs
->color
[i
]);
98 /* Back-face colors. */
99 for (i
= 0; i
< ATTR_COLOR_COUNT
; i
++) {
100 if (vs_outputs
->bcolor
[i
] != ATTR_UNUSED
) {
101 r300_draw_emit_attrib(r300
, EMIT_4F
, INTERP_LINEAR
,
102 vs_outputs
->bcolor
[i
]);
106 /* Texture coordinates. */
107 /* Only 8 generic vertex attributes can be used. If there are more,
108 * they won't be rasterized. */
110 for (i
= 0; i
< ATTR_GENERIC_COUNT
&& gen_count
< 8; i
++) {
111 if (vs_outputs
->generic
[i
] != ATTR_UNUSED
&&
112 !(r300
->sprite_coord_enable
& (1 << i
))) {
113 r300_draw_emit_attrib(r300
, EMIT_4F
, INTERP_PERSPECTIVE
,
114 vs_outputs
->generic
[i
]);
119 /* Fog coordinates. */
120 if (gen_count
< 8 && vs_outputs
->fog
!= ATTR_UNUSED
) {
121 r300_draw_emit_attrib(r300
, EMIT_4F
, INTERP_PERSPECTIVE
,
127 if (r300_fs(r300
)->shader
->inputs
.wpos
!= ATTR_UNUSED
&& gen_count
< 8) {
128 DBG(r300
, DBG_SWTCL
, "draw_emit_attrib: WPOS, index: %i\n",
130 r300_draw_emit_attrib(r300
, EMIT_4F
, INTERP_PERSPECTIVE
,
135 /* Update the PSC tables for SW TCL, using Draw. */
136 static void r300_swtcl_vertex_psc(struct r300_context
*r300
)
138 struct r300_vertex_stream_state
*vstream
= r300
->vertex_stream_state
.state
;
139 struct vertex_info
*vinfo
= &r300
->vertex_info
;
140 uint16_t type
, swizzle
;
141 enum pipe_format format
;
142 unsigned i
, attrib_count
;
143 int* vs_output_tab
= r300
->stream_loc_notcl
;
145 memset(vstream
, 0, sizeof(struct r300_vertex_stream_state
));
147 /* For each Draw attribute, route it to the fragment shader according
148 * to the vs_output_tab. */
149 attrib_count
= vinfo
->num_attribs
;
150 DBG(r300
, DBG_SWTCL
, "r300: attrib count: %d\n", attrib_count
);
151 for (i
= 0; i
< attrib_count
; i
++) {
152 if (vs_output_tab
[i
] == -1) {
157 format
= draw_translate_vinfo_format(vinfo
->attrib
[i
].emit
);
160 "r300: swtcl_vertex_psc [%i] <- %s\n",
161 vs_output_tab
[i
], util_format_short_name(format
));
163 /* Obtain the type of data in this attribute. */
164 type
= r300_translate_vertex_data_type(format
);
165 if (type
== R300_INVALID_FORMAT
) {
166 fprintf(stderr
, "r300: Bad vertex format %s.\n",
167 util_format_short_name(format
));
172 type
|= vs_output_tab
[i
] << R300_DST_VEC_LOC_SHIFT
;
174 /* Obtain the swizzle for this attribute. Note that the default
175 * swizzle in the hardware is not XYZW! */
176 swizzle
= r300_translate_vertex_data_swizzle(format
);
178 /* Add the attribute to the PSC table. */
180 vstream
->vap_prog_stream_cntl
[i
>> 1] |= type
<< 16;
181 vstream
->vap_prog_stream_cntl_ext
[i
>> 1] |= swizzle
<< 16;
183 vstream
->vap_prog_stream_cntl
[i
>> 1] |= type
;
184 vstream
->vap_prog_stream_cntl_ext
[i
>> 1] |= swizzle
;
188 /* Set the last vector in the PSC. */
192 vstream
->vap_prog_stream_cntl
[i
>> 1] |=
193 (R300_LAST_VEC
<< (i
& 1 ? 16 : 0));
195 vstream
->count
= (i
>> 1) + 1;
196 r300_mark_atom_dirty(r300
, &r300
->vertex_stream_state
);
197 r300
->vertex_stream_state
.size
= (1 + vstream
->count
) * 2;
200 static void r300_rs_col(struct r300_rs_block
* rs
, int id
, int ptr
,
201 enum r300_rs_swizzle swiz
)
203 rs
->ip
[id
] |= R300_RS_COL_PTR(ptr
);
204 if (swiz
== SWIZ_0001
) {
205 rs
->ip
[id
] |= R300_RS_COL_FMT(R300_RS_COL_FMT_0001
);
207 rs
->ip
[id
] |= R300_RS_COL_FMT(R300_RS_COL_FMT_RGBA
);
209 rs
->inst
[id
] |= R300_RS_INST_COL_ID(id
);
212 static void r300_rs_col_write(struct r300_rs_block
* rs
, int id
, int fp_offset
,
213 enum r300_rs_col_write_type type
)
215 assert(type
== WRITE_COLOR
);
216 rs
->inst
[id
] |= R300_RS_INST_COL_CN_WRITE
|
217 R300_RS_INST_COL_ADDR(fp_offset
);
220 static void r300_rs_tex(struct r300_rs_block
* rs
, int id
, int ptr
,
221 enum r300_rs_swizzle swiz
)
223 if (swiz
== SWIZ_X001
) {
224 rs
->ip
[id
] |= R300_RS_TEX_PTR(ptr
) |
225 R300_RS_SEL_S(R300_RS_SEL_C0
) |
226 R300_RS_SEL_T(R300_RS_SEL_K0
) |
227 R300_RS_SEL_R(R300_RS_SEL_K0
) |
228 R300_RS_SEL_Q(R300_RS_SEL_K1
);
229 } else if (swiz
== SWIZ_XY01
) {
230 rs
->ip
[id
] |= R300_RS_TEX_PTR(ptr
) |
231 R300_RS_SEL_S(R300_RS_SEL_C0
) |
232 R300_RS_SEL_T(R300_RS_SEL_C1
) |
233 R300_RS_SEL_R(R300_RS_SEL_K0
) |
234 R300_RS_SEL_Q(R300_RS_SEL_K1
);
236 rs
->ip
[id
] |= R300_RS_TEX_PTR(ptr
) |
237 R300_RS_SEL_S(R300_RS_SEL_C0
) |
238 R300_RS_SEL_T(R300_RS_SEL_C1
) |
239 R300_RS_SEL_R(R300_RS_SEL_C2
) |
240 R300_RS_SEL_Q(R300_RS_SEL_C3
);
242 rs
->inst
[id
] |= R300_RS_INST_TEX_ID(id
);
245 static void r300_rs_tex_write(struct r300_rs_block
* rs
, int id
, int fp_offset
)
247 rs
->inst
[id
] |= R300_RS_INST_TEX_CN_WRITE
|
248 R300_RS_INST_TEX_ADDR(fp_offset
);
251 static void r500_rs_col(struct r300_rs_block
* rs
, int id
, int ptr
,
252 enum r300_rs_swizzle swiz
)
254 rs
->ip
[id
] |= R500_RS_COL_PTR(ptr
);
255 if (swiz
== SWIZ_0001
) {
256 rs
->ip
[id
] |= R500_RS_COL_FMT(R300_RS_COL_FMT_0001
);
258 rs
->ip
[id
] |= R500_RS_COL_FMT(R300_RS_COL_FMT_RGBA
);
260 rs
->inst
[id
] |= R500_RS_INST_COL_ID(id
);
263 static void r500_rs_col_write(struct r300_rs_block
* rs
, int id
, int fp_offset
,
264 enum r300_rs_col_write_type type
)
266 if (type
== WRITE_FACE
)
267 rs
->inst
[id
] |= R500_RS_INST_COL_CN_WRITE_BACKFACE
|
268 R500_RS_INST_COL_ADDR(fp_offset
);
270 rs
->inst
[id
] |= R500_RS_INST_COL_CN_WRITE
|
271 R500_RS_INST_COL_ADDR(fp_offset
);
275 static void r500_rs_tex(struct r300_rs_block
* rs
, int id
, int ptr
,
276 enum r300_rs_swizzle swiz
)
278 if (swiz
== SWIZ_X001
) {
279 rs
->ip
[id
] |= R500_RS_SEL_S(ptr
) |
280 R500_RS_SEL_T(R500_RS_IP_PTR_K0
) |
281 R500_RS_SEL_R(R500_RS_IP_PTR_K0
) |
282 R500_RS_SEL_Q(R500_RS_IP_PTR_K1
);
283 } else if (swiz
== SWIZ_XY01
) {
284 rs
->ip
[id
] |= R500_RS_SEL_S(ptr
) |
285 R500_RS_SEL_T(ptr
+ 1) |
286 R500_RS_SEL_R(R500_RS_IP_PTR_K0
) |
287 R500_RS_SEL_Q(R500_RS_IP_PTR_K1
);
289 rs
->ip
[id
] |= R500_RS_SEL_S(ptr
) |
290 R500_RS_SEL_T(ptr
+ 1) |
291 R500_RS_SEL_R(ptr
+ 2) |
292 R500_RS_SEL_Q(ptr
+ 3);
294 rs
->inst
[id
] |= R500_RS_INST_TEX_ID(id
);
297 static void r500_rs_tex_write(struct r300_rs_block
* rs
, int id
, int fp_offset
)
299 rs
->inst
[id
] |= R500_RS_INST_TEX_CN_WRITE
|
300 R500_RS_INST_TEX_ADDR(fp_offset
);
303 /* Set up the RS block.
305 * This is the part of the chipset that is responsible for linking vertex
306 * and fragment shaders and stuffed texture coordinates.
308 * The rasterizer reads data from VAP, which produces vertex shader outputs,
309 * and GA, which produces stuffed texture coordinates. VAP outputs have
310 * precedence over GA. All outputs must be rasterized otherwise it locks up.
311 * If there are more outputs rasterized than is set in VAP/GA, it locks up
312 * too. The funky part is that this info has been pretty much obtained by trial
314 static void r300_update_rs_block(struct r300_context
*r300
)
316 struct r300_vertex_shader
*vs
= r300
->vs_state
.state
;
317 struct r300_shader_semantics
*vs_outputs
= &vs
->outputs
;
318 struct r300_shader_semantics
*fs_inputs
= &r300_fs(r300
)->shader
->inputs
;
319 struct r300_rs_block rs
= {0};
320 int i
, col_count
= 0, tex_count
= 0, fp_offset
= 0, count
, loc
= 0, tex_ptr
= 0;
321 void (*rX00_rs_col
)(struct r300_rs_block
*, int, int, enum r300_rs_swizzle
);
322 void (*rX00_rs_col_write
)(struct r300_rs_block
*, int, int, enum r300_rs_col_write_type
);
323 void (*rX00_rs_tex
)(struct r300_rs_block
*, int, int, enum r300_rs_swizzle
);
324 void (*rX00_rs_tex_write
)(struct r300_rs_block
*, int, int);
325 boolean any_bcolor_used
= vs_outputs
->bcolor
[0] != ATTR_UNUSED
||
326 vs_outputs
->bcolor
[1] != ATTR_UNUSED
;
327 int *stream_loc_notcl
= r300
->stream_loc_notcl
;
328 uint32_t stuffing_enable
= 0;
330 if (r300
->screen
->caps
.is_r500
) {
331 rX00_rs_col
= r500_rs_col
;
332 rX00_rs_col_write
= r500_rs_col_write
;
333 rX00_rs_tex
= r500_rs_tex
;
334 rX00_rs_tex_write
= r500_rs_tex_write
;
336 rX00_rs_col
= r300_rs_col
;
337 rX00_rs_col_write
= r300_rs_col_write
;
338 rX00_rs_tex
= r300_rs_tex
;
339 rX00_rs_tex_write
= r300_rs_tex_write
;
342 /* 0x5555 copied from classic, which means:
343 * Select user color 0 for COLOR0 up to COLOR7.
344 * What the hell does that mean? */
345 rs
.vap_vtx_state_cntl
= 0x5555;
347 /* The position is always present in VAP. */
348 rs
.vap_vsm_vtx_assm
|= R300_INPUT_CNTL_POS
;
349 rs
.vap_out_vtx_fmt
[0] |= R300_VAP_OUTPUT_VTX_FMT_0__POS_PRESENT
;
350 stream_loc_notcl
[loc
++] = 0;
352 /* Set up the point size in VAP. */
353 if (vs_outputs
->psize
!= ATTR_UNUSED
) {
354 rs
.vap_out_vtx_fmt
[0] |= R300_VAP_OUTPUT_VTX_FMT_0__PT_SIZE_PRESENT
;
355 stream_loc_notcl
[loc
++] = 1;
358 /* Set up and rasterize colors. */
359 for (i
= 0; i
< ATTR_COLOR_COUNT
; i
++) {
360 if (vs_outputs
->color
[i
] != ATTR_UNUSED
|| any_bcolor_used
||
361 vs_outputs
->color
[1] != ATTR_UNUSED
) {
362 /* Set up the color in VAP. */
363 rs
.vap_vsm_vtx_assm
|= R300_INPUT_CNTL_COLOR
;
364 rs
.vap_out_vtx_fmt
[0] |=
365 R300_VAP_OUTPUT_VTX_FMT_0__COLOR_0_PRESENT
<< i
;
366 stream_loc_notcl
[loc
++] = 2 + i
;
369 rX00_rs_col(&rs
, col_count
, col_count
, SWIZ_XYZW
);
371 /* Write it to the FS input register if it's needed by the FS. */
372 if (fs_inputs
->color
[i
] != ATTR_UNUSED
) {
373 rX00_rs_col_write(&rs
, col_count
, fp_offset
, WRITE_COLOR
);
377 "r300: Rasterized color %i written to FS.\n", i
);
379 DBG(r300
, DBG_RS
, "r300: Rasterized color %i unused.\n", i
);
383 /* Skip the FS input register, leave it uninitialized. */
384 /* If we try to set it to (0,0,0,1), it will lock up. */
385 if (fs_inputs
->color
[i
] != ATTR_UNUSED
) {
388 DBG(r300
, DBG_RS
, "r300: FS input color %i unassigned%s.\n",
394 /* Set up back-face colors. The rasterizer will do the color selection
396 if (any_bcolor_used
) {
397 if (r300
->two_sided_color
) {
398 /* Rasterize as back-face colors. */
399 for (i
= 0; i
< ATTR_COLOR_COUNT
; i
++) {
400 rs
.vap_vsm_vtx_assm
|= R300_INPUT_CNTL_COLOR
;
401 rs
.vap_out_vtx_fmt
[0] |= R300_VAP_OUTPUT_VTX_FMT_0__COLOR_0_PRESENT
<< (2+i
);
402 stream_loc_notcl
[loc
++] = 4 + i
;
405 /* Rasterize two fake texcoords to prevent from the two-sided color
407 /* XXX Consider recompiling the vertex shader to save 2 RS units. */
408 for (i
= 0; i
< 2; i
++) {
409 rs
.vap_vsm_vtx_assm
|= (R300_INPUT_CNTL_TC0
<< tex_count
);
410 rs
.vap_out_vtx_fmt
[1] |= (4 << (3 * tex_count
));
411 stream_loc_notcl
[loc
++] = 6 + tex_count
;
414 rX00_rs_tex(&rs
, tex_count
, tex_ptr
, SWIZ_XYZW
);
422 * Note that we can use either the two-sided color selection based on
423 * the front and back vertex shader colors, or gl_FrontFacing,
424 * but not both! It locks up otherwise.
426 * In Direct3D 9, the two-sided color selection can be used
427 * with shaders 2.0 only, while gl_FrontFacing can be used
428 * with shaders 3.0 only. The hardware apparently hasn't been designed
429 * to support both at the same time. */
430 if (r300
->screen
->caps
.is_r500
&& fs_inputs
->face
!= ATTR_UNUSED
&&
431 !(any_bcolor_used
&& r300
->two_sided_color
)) {
432 rX00_rs_col(&rs
, col_count
, col_count
, SWIZ_XYZW
);
433 rX00_rs_col_write(&rs
, col_count
, fp_offset
, WRITE_FACE
);
436 DBG(r300
, DBG_RS
, "r300: Rasterized FACE written to FS.\n");
437 } else if (fs_inputs
->face
!= ATTR_UNUSED
) {
438 fprintf(stderr
, "r300: ERROR: FS input FACE unassigned.\n");
441 /* Rasterize texture coordinates. */
442 for (i
= 0; i
< ATTR_GENERIC_COUNT
&& tex_count
< 8; i
++) {
443 bool sprite_coord
= false;
445 if (fs_inputs
->generic
[i
] != ATTR_UNUSED
) {
446 sprite_coord
= !!(r300
->sprite_coord_enable
& (1 << i
));
449 if (vs_outputs
->generic
[i
] != ATTR_UNUSED
|| sprite_coord
) {
451 /* Set up the texture coordinates in VAP. */
452 rs
.vap_vsm_vtx_assm
|= (R300_INPUT_CNTL_TC0
<< tex_count
);
453 rs
.vap_out_vtx_fmt
[1] |= (4 << (3 * tex_count
));
454 stream_loc_notcl
[loc
++] = 6 + tex_count
;
457 R300_GB_TEX_ST
<< (R300_GB_TEX0_SOURCE_SHIFT
+ (tex_count
*2));
460 rX00_rs_tex(&rs
, tex_count
, tex_ptr
,
461 sprite_coord
? SWIZ_XY01
: SWIZ_XYZW
);
463 /* Write it to the FS input register if it's needed by the FS. */
464 if (fs_inputs
->generic
[i
] != ATTR_UNUSED
) {
465 rX00_rs_tex_write(&rs
, tex_count
, fp_offset
);
469 "r300: Rasterized generic %i written to FS%s in texcoord %d.\n",
470 i
, sprite_coord
? " (sprite coord)" : "", tex_count
);
473 "r300: Rasterized generic %i unused%s.\n",
474 i
, sprite_coord
? " (sprite coord)" : "");
477 tex_ptr
+= sprite_coord
? 2 : 4;
479 /* Skip the FS input register, leave it uninitialized. */
480 /* If we try to set it to (0,0,0,1), it will lock up. */
481 if (fs_inputs
->generic
[i
] != ATTR_UNUSED
) {
484 DBG(r300
, DBG_RS
, "r300: FS input generic %i unassigned%s.\n",
485 i
, sprite_coord
? " (sprite coord)" : "");
490 for (; i
< ATTR_GENERIC_COUNT
; i
++) {
491 if (fs_inputs
->generic
[i
] != ATTR_UNUSED
) {
492 fprintf(stderr
, "r300: ERROR: FS input generic %i unassigned, "
493 "not enough hardware slots.\n", i
);
497 /* Rasterize fog coordinates. */
498 if (vs_outputs
->fog
!= ATTR_UNUSED
&& tex_count
< 8) {
499 /* Set up the fog coordinates in VAP. */
500 rs
.vap_vsm_vtx_assm
|= (R300_INPUT_CNTL_TC0
<< tex_count
);
501 rs
.vap_out_vtx_fmt
[1] |= (4 << (3 * tex_count
));
502 stream_loc_notcl
[loc
++] = 6 + tex_count
;
505 rX00_rs_tex(&rs
, tex_count
, tex_ptr
, SWIZ_X001
);
507 /* Write it to the FS input register if it's needed by the FS. */
508 if (fs_inputs
->fog
!= ATTR_UNUSED
) {
509 rX00_rs_tex_write(&rs
, tex_count
, fp_offset
);
512 DBG(r300
, DBG_RS
, "r300: Rasterized fog written to FS.\n");
514 DBG(r300
, DBG_RS
, "r300: Rasterized fog unused.\n");
519 /* Skip the FS input register, leave it uninitialized. */
520 /* If we try to set it to (0,0,0,1), it will lock up. */
521 if (fs_inputs
->fog
!= ATTR_UNUSED
) {
525 DBG(r300
, DBG_RS
, "r300: FS input fog unassigned.\n");
527 fprintf(stderr
, "r300: ERROR: FS input fog unassigned, "
528 "not enough hardware slots.\n");
533 /* Rasterize WPOS. */
534 /* Don't set it in VAP if the FS doesn't need it. */
535 if (fs_inputs
->wpos
!= ATTR_UNUSED
&& tex_count
< 8) {
536 /* Set up the WPOS coordinates in VAP. */
537 rs
.vap_vsm_vtx_assm
|= (R300_INPUT_CNTL_TC0
<< tex_count
);
538 rs
.vap_out_vtx_fmt
[1] |= (4 << (3 * tex_count
));
539 stream_loc_notcl
[loc
++] = 6 + tex_count
;
542 rX00_rs_tex(&rs
, tex_count
, tex_ptr
, SWIZ_XYZW
);
544 /* Write it to the FS input register. */
545 rX00_rs_tex_write(&rs
, tex_count
, fp_offset
);
547 DBG(r300
, DBG_RS
, "r300: Rasterized WPOS written to FS.\n");
553 if (fs_inputs
->wpos
!= ATTR_UNUSED
&& tex_count
>= 8) {
554 fprintf(stderr
, "r300: ERROR: FS input WPOS unassigned, "
555 "not enough hardware slots.\n");
559 /* Invalidate the rest of the no-TCL (GA) stream locations. */
561 stream_loc_notcl
[loc
++] = -1;
564 /* Rasterize at least one color, or bad things happen. */
565 if (col_count
== 0 && tex_count
== 0) {
566 rX00_rs_col(&rs
, 0, 0, SWIZ_0001
);
569 DBG(r300
, DBG_RS
, "r300: Rasterized color 0 to prevent lockups.\n");
572 DBG(r300
, DBG_RS
, "r300: --- Rasterizer status ---: colors: %i, "
573 "generics: %i.\n", col_count
, tex_count
);
575 rs
.count
= MIN2(tex_ptr
, 32) | (col_count
<< R300_IC_COUNT_SHIFT
) |
578 count
= MAX3(col_count
, tex_count
, 1);
579 rs
.inst_count
= count
- 1;
581 /* set the GB enable flags */
582 if (r300
->sprite_coord_enable
)
583 stuffing_enable
|= R300_GB_POINT_STUFF_ENABLE
;
585 rs
.gb_enable
= stuffing_enable
;
587 /* Now, after all that, see if we actually need to update the state. */
588 if (memcmp(r300
->rs_block_state
.state
, &rs
, sizeof(struct r300_rs_block
))) {
589 memcpy(r300
->rs_block_state
.state
, &rs
, sizeof(struct r300_rs_block
));
590 r300
->rs_block_state
.size
= 13 + count
*2;
594 static uint32_t r300_get_border_color(enum pipe_format format
,
595 const float border
[4],
598 const struct util_format_description
*desc
;
599 float border_swizzled
[4] = {0};
601 union util_color uc
= {0};
603 desc
= util_format_description(format
);
605 /* Do depth formats first. */
606 if (util_format_is_depth_or_stencil(format
)) {
608 case PIPE_FORMAT_Z16_UNORM
:
609 return util_pack_z(PIPE_FORMAT_Z16_UNORM
, border
[0]);
610 case PIPE_FORMAT_X8Z24_UNORM
:
611 case PIPE_FORMAT_S8_USCALED_Z24_UNORM
:
613 return util_pack_z(PIPE_FORMAT_X8Z24_UNORM
, border
[0]);
615 return util_pack_z(PIPE_FORMAT_Z16_UNORM
, border
[0]) << 16;
623 /* Apply inverse swizzle of the format. */
624 for (i
= 0; i
< 4; i
++) {
625 switch (desc
->swizzle
[i
]) {
626 case UTIL_FORMAT_SWIZZLE_X
:
627 border_swizzled
[2] = border
[i
];
629 case UTIL_FORMAT_SWIZZLE_Y
:
630 border_swizzled
[1] = border
[i
];
632 case UTIL_FORMAT_SWIZZLE_Z
:
633 border_swizzled
[0] = border
[i
];
635 case UTIL_FORMAT_SWIZZLE_W
:
636 border_swizzled
[3] = border
[i
];
641 /* Compressed formats. */
642 if (util_format_is_compressed(format
)) {
643 util_pack_color(border_swizzled
, PIPE_FORMAT_R8G8B8A8_UNORM
, &uc
);
647 switch (desc
->channel
[0].size
) {
649 util_pack_color(border_swizzled
, PIPE_FORMAT_B2G3R3_UNORM
, &uc
);
653 util_pack_color(border_swizzled
, PIPE_FORMAT_B4G4R4A4_UNORM
, &uc
);
657 if (desc
->channel
[1].size
== 5) {
658 util_pack_color(border_swizzled
, PIPE_FORMAT_B5G5R5A1_UNORM
, &uc
);
659 } else if (desc
->channel
[1].size
== 6) {
660 util_pack_color(border_swizzled
, PIPE_FORMAT_B5G6R5_UNORM
, &uc
);
668 util_pack_color(border_swizzled
, PIPE_FORMAT_B8G8R8A8_UNORM
, &uc
);
672 util_pack_color(border_swizzled
, PIPE_FORMAT_B10G10R10A2_UNORM
, &uc
);
676 if (desc
->nr_channels
<= 2) {
677 border_swizzled
[0] = border_swizzled
[2];
678 util_pack_color(border_swizzled
, PIPE_FORMAT_R16G16_UNORM
, &uc
);
680 util_pack_color(border_swizzled
, PIPE_FORMAT_B8G8R8A8_UNORM
, &uc
);
688 static void r300_merge_textures_and_samplers(struct r300_context
* r300
)
690 struct r300_textures_state
*state
=
691 (struct r300_textures_state
*)r300
->textures_state
.state
;
692 struct r300_texture_sampler_state
*texstate
;
693 struct r300_sampler_state
*sampler
;
694 struct r300_sampler_view
*view
;
695 struct r300_texture
*tex
;
696 unsigned min_level
, max_level
, i
, j
, size
;
697 unsigned count
= MIN2(state
->sampler_view_count
,
698 state
->sampler_state_count
);
700 /* The KIL opcode fix, see below. */
701 if (!count
&& !r300
->screen
->caps
.is_r500
)
704 state
->tx_enable
= 0;
708 for (i
= 0; i
< count
; i
++) {
709 if (state
->sampler_views
[i
] && state
->sampler_states
[i
]) {
710 state
->tx_enable
|= 1 << i
;
712 view
= state
->sampler_views
[i
];
713 tex
= r300_texture(view
->base
.texture
);
714 sampler
= state
->sampler_states
[i
];
716 texstate
= &state
->regs
[i
];
717 texstate
->format
= view
->format
;
718 texstate
->filter0
= sampler
->filter0
;
719 texstate
->filter1
= sampler
->filter1
;
721 /* Set the border color. */
722 texstate
->border_color
=
723 r300_get_border_color(view
->base
.format
,
724 sampler
->state
.border_color
,
725 r300
->screen
->caps
.is_r500
);
727 /* determine min/max levels */
728 max_level
= MIN3(sampler
->max_lod
+ view
->base
.u
.tex
.first_level
,
729 tex
->desc
.b
.b
.last_level
, view
->base
.u
.tex
.last_level
);
730 min_level
= MIN2(sampler
->min_lod
+ view
->base
.u
.tex
.first_level
,
733 if (tex
->desc
.is_npot
&& min_level
> 0) {
734 /* Even though we do not implement mipmapping for NPOT
735 * textures, we should at least honor the minimum level
736 * which is allowed to be displayed. We do this by setting up
737 * an i-th mipmap level as the zero level. */
738 r300_texture_setup_format_state(r300
->screen
, &tex
->desc
,
741 texstate
->format
.tile_config
|=
742 tex
->desc
.offset_in_bytes
[min_level
] & 0xffffffe0;
743 assert((tex
->desc
.offset_in_bytes
[min_level
] & 0x1f) == 0);
746 /* Assign a texture cache region. */
747 texstate
->format
.format1
|= view
->texcache_region
;
749 /* Depth textures are kinda special. */
750 if (util_format_is_depth_or_stencil(tex
->desc
.b
.b
.format
)) {
751 unsigned char depth_swizzle
[4];
753 if (!r300
->screen
->caps
.is_r500
&&
754 util_format_get_blocksizebits(tex
->desc
.b
.b
.format
) == 32) {
755 /* X24x8 is sampled as Y16X16 on r3xx-r4xx.
756 * The depth here is at the Y component. */
757 for (j
= 0; j
< 4; j
++)
758 depth_swizzle
[j
] = UTIL_FORMAT_SWIZZLE_Y
;
760 for (j
= 0; j
< 4; j
++)
761 depth_swizzle
[j
] = UTIL_FORMAT_SWIZZLE_X
;
764 /* If compare mode is disabled, sampler view swizzles
765 * are stored in the format.
766 * Otherwise, the swizzles must be applied after the compare
767 * mode in the fragment shader. */
768 if (sampler
->state
.compare_mode
== PIPE_TEX_COMPARE_NONE
) {
769 texstate
->format
.format1
|=
770 r300_get_swizzle_combined(depth_swizzle
,
771 view
->swizzle
, FALSE
);
773 texstate
->format
.format1
|=
774 r300_get_swizzle_combined(depth_swizzle
, 0, FALSE
);
778 if (r300
->screen
->caps
.dxtc_swizzle
&&
779 util_format_is_compressed(tex
->desc
.b
.b
.format
)) {
780 texstate
->filter1
|= R400_DXTC_SWIZZLE_ENABLE
;
783 /* to emulate 1D textures through 2D ones correctly */
784 if (tex
->desc
.b
.b
.target
== PIPE_TEXTURE_1D
) {
785 texstate
->filter0
&= ~R300_TX_WRAP_T_MASK
;
786 texstate
->filter0
|= R300_TX_WRAP_T(R300_TX_CLAMP_TO_EDGE
);
789 if (tex
->desc
.is_npot
) {
790 /* NPOT textures don't support mip filter, unfortunately.
791 * This prevents incorrect rendering. */
792 texstate
->filter0
&= ~R300_TX_MIN_FILTER_MIP_MASK
;
794 /* Mask out the mirrored flag. */
795 if (texstate
->filter0
& R300_TX_WRAP_S(R300_TX_MIRRORED
)) {
796 texstate
->filter0
&= ~R300_TX_WRAP_S(R300_TX_MIRRORED
);
798 if (texstate
->filter0
& R300_TX_WRAP_T(R300_TX_MIRRORED
)) {
799 texstate
->filter0
&= ~R300_TX_WRAP_T(R300_TX_MIRRORED
);
802 /* Change repeat to clamp-to-edge.
803 * (the repeat bit has a value of 0, no masking needed). */
804 if ((texstate
->filter0
& R300_TX_WRAP_S_MASK
) ==
805 R300_TX_WRAP_S(R300_TX_REPEAT
)) {
806 texstate
->filter0
|= R300_TX_WRAP_S(R300_TX_CLAMP_TO_EDGE
);
808 if ((texstate
->filter0
& R300_TX_WRAP_T_MASK
) ==
809 R300_TX_WRAP_T(R300_TX_REPEAT
)) {
810 texstate
->filter0
|= R300_TX_WRAP_T(R300_TX_CLAMP_TO_EDGE
);
813 /* the MAX_MIP level is the largest (finest) one */
814 texstate
->format
.format0
|= R300_TX_NUM_LEVELS(max_level
);
815 texstate
->filter0
|= R300_TX_MAX_MIP_LEVEL(min_level
);
818 texstate
->filter0
|= i
<< 28;
823 /* For the KIL opcode to work on r3xx-r4xx, the texture unit
824 * assigned to this opcode (it's always the first one) must be
825 * enabled. Otherwise the opcode doesn't work.
827 * In order to not depend on the fragment shader, we just make
828 * the first unit enabled all the time. */
829 if (i
== 0 && !r300
->screen
->caps
.is_r500
) {
830 pipe_sampler_view_reference(
831 (struct pipe_sampler_view
**)&state
->sampler_views
[i
],
832 &r300
->texkill_sampler
->base
);
834 state
->tx_enable
|= 1 << i
;
836 texstate
= &state
->regs
[i
];
838 /* Just set some valid state. */
839 texstate
->format
= r300
->texkill_sampler
->format
;
841 r300_translate_tex_filters(PIPE_TEX_FILTER_NEAREST
,
842 PIPE_TEX_FILTER_NEAREST
,
843 PIPE_TEX_FILTER_NEAREST
,
845 texstate
->filter1
= 0;
846 texstate
->border_color
= 0;
848 texstate
->filter0
|= i
<< 28;
855 r300
->textures_state
.size
= size
;
857 /* Pick a fragment shader based on either the texture compare state
858 * or the uses_pitch flag. */
859 if (r300
->fs
.state
&& count
) {
860 if (r300_pick_fragment_shader(r300
)) {
861 r300_mark_fs_code_dirty(r300
);
866 /* We can't use compressed zbuffers as samplers. */
867 static void r300_flush_depth_textures(struct r300_context
*r300
)
869 struct r300_textures_state
*state
=
870 (struct r300_textures_state
*)r300
->textures_state
.state
;
872 unsigned count
= MIN2(state
->sampler_view_count
,
873 state
->sampler_state_count
);
875 if (r300
->z_decomp_rd
)
878 for (i
= 0; i
< count
; i
++)
879 if (state
->sampler_views
[i
] && state
->sampler_states
[i
]) {
880 struct pipe_resource
*tex
= state
->sampler_views
[i
]->base
.texture
;
882 if (tex
->target
== PIPE_TEXTURE_3D
||
883 tex
->target
== PIPE_TEXTURE_CUBE
)
886 /* Ignore non-depth textures.
887 * Also ignore reinterpreted depth textures, e.g. resource_copy. */
888 if (!util_format_is_depth_or_stencil(tex
->format
))
891 for (level
= 0; level
<= tex
->last_level
; level
++)
892 if (r300_texture(tex
)->zmask_in_use
[level
]) {
893 /* We don't handle 3D textures and cubemaps yet. */
894 r300_flush_depth_stencil(&r300
->context
, tex
, level
, 0);
899 void r300_update_derived_state(struct r300_context
* r300
)
901 r300_flush_depth_textures(r300
);
903 if (r300
->textures_state
.dirty
) {
904 r300_merge_textures_and_samplers(r300
);
907 if (r300
->rs_block_state
.dirty
) {
908 r300_update_rs_block(r300
);
911 memset(&r300
->vertex_info
, 0, sizeof(struct vertex_info
));
912 r300_draw_emit_all_attribs(r300
);
913 draw_compute_vertex_size(&r300
->vertex_info
);
914 r300_swtcl_vertex_psc(r300
);
918 r300_update_hyperz_state(r300
);