src/gallium/drivers/r300/r300_state_invariant.c

   1 /*
   2  * Copyright 2009 Joakim Sindholt <opensource@zhasha.com>
   3  *                Corbin Simpson <MostAwesomeDude@gmail.com>
   4  *
   5  * Permission is hereby granted, free of charge, to any person obtaining a
   6  * copy of this software and associated documentation files (the "Software"),
   7  * to deal in the Software without restriction, including without limitation
   8  * on the rights to use, copy, modify, merge, publish, distribute, sub
   9  * license, and/or sell copies of the Software, and to permit persons to whom
  10  * the Software is furnished to do so, subject to the following conditions:
  11  *
  12  * The above copyright notice and this permission notice (including the next
  13  * paragraph) shall be included in all copies or substantial portions of the
  14  * Software.
  15  *
  16  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  17  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  18  * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
  19  * THE AUTHOR(S) AND/OR THEIR SUPPLIERS BE LIABLE FOR ANY CLAIM,
  20  * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
  21  * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
  22  * USE OR OTHER DEALINGS IN THE SOFTWARE. */
  23
  24 #include "r300_state_invariant.h"
  25
  26 /* Calculate and emit invariant state. This is data that the 3D engine
  27  * will probably want at the beginning of every CS, but it's not currently
  28  * handled by any CSO setup, and in addition it doesn't really change much.
  29  *
  30  * Note that eventually this should be empty, but it's useful for development
  31  * and general unduplication of code. */
  32 void r300_emit_invariant_state(struct r300_context* r300)
  33 {
  34     struct r300_capabilities* caps = r300_screen(r300->context.screen)->caps;
  35     CS_LOCALS(r300);
  36
  37     BEGIN_CS(24 + (caps->has_tcl ? 2: 0));
  38
  39     /* Various GB enables */
  40     OUT_CS_REG(R300_GB_ENABLE, R300_GB_POINT_STUFF_ENABLE |
  41         R300_GB_LINE_STUFF_ENABLE | R300_GB_TRIANGLE_STUFF_ENABLE);
  42     /* Subpixel multisampling for AA */
  43     OUT_CS_REG(R300_GB_MSPOS0, 0x66666666);
  44     OUT_CS_REG(R300_GB_MSPOS1, 0x66666666);
  45     /* GB tile config and pipe setup */
  46     OUT_CS_REG(R300_GB_TILE_CONFIG, R300_GB_TILE_DISABLE |
  47         r300_translate_gb_pipes(caps->num_frag_pipes));
  48     /* Source of fog depth */
  49     OUT_CS_REG(R300_GB_SELECT, R300_GB_FOG_SELECT_1_1_W);
  50     /* AA enable */
  51     OUT_CS_REG(R300_GB_AA_CONFIG, 0x0);
  52     /* GA errata fixes. */
  53     if (caps->is_r500) {
  54         OUT_CS_REG(R300_GA_ENHANCE,
  55                 R300_GA_ENHANCE_DEADLOCK_CNTL_PREVENT_TCL |
  56                 R300_GA_ENHANCE_FASTSYNC_CNTL_ENABLE |
  57                 R500_GA_ENHANCE_REG_READWRITE_ENABLE |
  58                 R500_GA_ENHANCE_REG_NOSTALL_ENABLE);
  59     } else {
  60         OUT_CS_REG(R300_GA_ENHANCE,
  61                 R300_GA_ENHANCE_DEADLOCK_CNTL_PREVENT_TCL |
  62                 R300_GA_ENHANCE_FASTSYNC_CNTL_ENABLE);
  63     }
  64
  65     /* Fog block. */
  66     OUT_CS_REG(R300_FG_FOG_BLEND, 0x00000000);
  67     OUT_CS_REG(R300_FG_FOG_COLOR_R, 0x00000000);
  68     OUT_CS_REG(R300_FG_FOG_COLOR_G, 0x00000000);
  69     OUT_CS_REG(R300_FG_FOG_COLOR_B, 0x00000000);
  70     OUT_CS_REG(R300_FG_DEPTH_SRC, 0x00000000);
  71
  72     /* TCL-only stuff */
  73     if (caps->has_tcl) {
  74         /* Amount of time to wait for vertex fetches in PVS */
  75         OUT_CS_REG(VAP_PVS_VTX_TIMEOUT_REG, 0xffff);
  76     }
  77
  78     END_CS;
  79
  80     /* XXX unsorted stuff from surface_fill */
  81     BEGIN_CS(99 + (caps->has_tcl ? 26 : 0));
  82     /* Flush PVS. */
  83     OUT_CS_REG(R300_VAP_PVS_STATE_FLUSH_REG, 0x0);
  84
  85     OUT_CS_REG(R300_SE_VTE_CNTL, R300_VPORT_X_SCALE_ENA |
  86         R300_VPORT_X_OFFSET_ENA | R300_VPORT_Y_SCALE_ENA |
  87         R300_VPORT_Y_OFFSET_ENA | R300_VPORT_Z_SCALE_ENA |
  88         R300_VPORT_Z_OFFSET_ENA | R300_VTX_W0_FMT);
  89     /* Max and min vertex index clamp. */
  90     OUT_CS_REG(R300_VAP_VF_MAX_VTX_INDX, 0xFFFFFF);
  91     OUT_CS_REG(R300_VAP_VF_MIN_VTX_INDX, 0x0);
  92     /* XXX endian */
  93     if (caps->has_tcl) {
  94         OUT_CS_REG(R300_VAP_CNTL_STATUS, R300_VC_NO_SWAP);
  95         OUT_CS_REG(R300_VAP_CLIP_CNTL, R300_CLIP_DISABLE |
  96             R300_PS_UCP_MODE_CLIP_AS_TRIFAN);
  97         OUT_CS_REG_SEQ(R300_VAP_GB_VERT_CLIP_ADJ, 4);
  98         OUT_CS_32F(1.0);
  99         OUT_CS_32F(1.0);
 100         OUT_CS_32F(1.0);
 101         OUT_CS_32F(1.0);
 102     } else {
 103         OUT_CS_REG(R300_VAP_CNTL_STATUS, R300_VC_NO_SWAP |
 104                 R300_VAP_TCL_BYPASS);
 105     }
 106     /* XXX magic number not in r300_reg */
 107     OUT_CS_REG(R300_VAP_PSC_SGN_NORM_CNTL, 0xAAAAAAAA);
 108     /* XXX point tex stuffing */
 109     OUT_CS_REG_SEQ(R300_GA_POINT_S0, 1);
 110     OUT_CS_32F(0.0);
 111     OUT_CS_REG_SEQ(R300_GA_POINT_S1, 1);
 112     OUT_CS_32F(1.0);
 113     OUT_CS_REG(R300_GA_TRIANGLE_STIPPLE, 0x5 |
 114         (0x5 << R300_GA_TRIANGLE_STIPPLE_Y_SHIFT_SHIFT));
 115     /* XXX this big chunk should be refactored into rs_state */
 116     OUT_CS_REG(R300_GA_LINE_S0, 0x00000000);
 117     OUT_CS_REG(R300_GA_LINE_S1, 0x3F800000);
 118     OUT_CS_REG(R300_GA_SOLID_RG, 0x00000000);
 119     OUT_CS_REG(R300_GA_SOLID_BA, 0x00000000);
 120     OUT_CS_REG(R300_GA_POLY_MODE, 0x00000000);
 121     OUT_CS_REG(R300_GA_ROUND_MODE, 0x00000001);
 122     OUT_CS_REG(R300_GA_OFFSET, 0x00000000);
 123     OUT_CS_REG(R300_GA_FOG_SCALE, 0x3DBF1412);
 124     OUT_CS_REG(R300_GA_FOG_OFFSET, 0x00000000);
 125     OUT_CS_REG(R300_SU_TEX_WRAP, 0x00000000);
 126     OUT_CS_REG(R300_SU_DEPTH_SCALE, 0x4B7FFFFF);
 127     OUT_CS_REG(R300_SU_DEPTH_OFFSET, 0x00000000);
 128     OUT_CS_REG(R300_SC_HYPERZ, 0x0000001C);
 129     OUT_CS_REG(R300_SC_EDGERULE, 0x2DA49525);
 130     OUT_CS_REG(R300_RB3D_CCTL, 0x00000000);
 131     OUT_CS_REG(RB3D_COLOR_CHANNEL_MASK, 0x0000000F);
 132     OUT_CS_REG(R300_RB3D_AARESOLVE_CTL, 0x00000000);
 133     OUT_CS_REG(R500_RB3D_DISCARD_SRC_PIXEL_LTE_THRESHOLD, 0x00000000);
 134     OUT_CS_REG(R500_RB3D_DISCARD_SRC_PIXEL_GTE_THRESHOLD, 0xFFFFFFFF);
 135     OUT_CS_REG(R300_ZB_FORMAT, 0x00000002);
 136     OUT_CS_REG(R300_ZB_ZCACHE_CTLSTAT, 0x00000003);
 137     OUT_CS_REG(R300_ZB_BW_CNTL, 0x00000000);
 138     OUT_CS_REG(R300_ZB_DEPTHCLEARVALUE, 0x00000000);
 139     OUT_CS_REG(R300_ZB_HIZ_OFFSET, 0x00000000);
 140     OUT_CS_REG(R300_ZB_HIZ_PITCH, 0x00000000);
 141     if (caps->has_tcl) {
 142         OUT_CS_REG(R300_VAP_PROG_STREAM_CNTL_0,
 143             (R300_DATA_TYPE_FLOAT_4 << R300_DATA_TYPE_0_SHIFT) |
 144             ((R300_LAST_VEC | (1 << R300_DST_VEC_LOC_SHIFT) |
 145                 R300_DATA_TYPE_FLOAT_4) << R300_DATA_TYPE_1_SHIFT));
 146     } else {
 147         OUT_CS_REG(R300_VAP_PROG_STREAM_CNTL_0,
 148             (R300_DATA_TYPE_FLOAT_4 << R300_DATA_TYPE_0_SHIFT) |
 149             ((R300_LAST_VEC | (2 << R300_DST_VEC_LOC_SHIFT) |
 150                 R300_DATA_TYPE_FLOAT_4) << R300_DATA_TYPE_1_SHIFT));
 151     }
 152     OUT_CS_REG(R300_VAP_PROG_STREAM_CNTL_EXT_0,
 153             (R300_VAP_SWIZZLE_XYZW << R300_SWIZZLE0_SHIFT) |
 154             (R300_VAP_SWIZZLE_XYZW << R300_SWIZZLE1_SHIFT));
 155     OUT_CS_REG(R300_VAP_VTX_STATE_CNTL, 0x1);
 156     OUT_CS_REG(R300_VAP_VSM_VTX_ASSM, 0x405);
 157     OUT_CS_REG(R300_SE_VTE_CNTL, 0x0000043F);
 158     /* Vertex size. */
 159     OUT_CS_REG(R300_VAP_VTX_SIZE, 0x8);
 160     OUT_CS_REG(R300_VAP_PSC_SGN_NORM_CNTL, 0xAAAAAAAA);
 161     OUT_CS_REG(R300_VAP_OUTPUT_VTX_FMT_0, 0x00000003);
 162     OUT_CS_REG(R300_VAP_OUTPUT_VTX_FMT_1, 0x00000000);
 163     OUT_CS_REG(R300_TX_ENABLE, 0x0);
 164
 165     /* XXX */
 166     OUT_CS_REG(R300_SC_CLIP_RULE, 0xaaaa);
 167
 168     OUT_CS_REG_SEQ(R300_US_OUT_FMT_0, 4);
 169     OUT_CS(R300_C0_SEL_B | R300_C1_SEL_G | R300_C2_SEL_R | R300_C3_SEL_A);
 170     OUT_CS(R300_US_OUT_FMT_UNUSED);
 171     OUT_CS(R300_US_OUT_FMT_UNUSED);
 172     OUT_CS(R300_US_OUT_FMT_UNUSED);
 173     OUT_CS_REG(R300_US_W_FMT, R300_W_FMT_W0);
 174     /* XXX these magic numbers should be explained when
 175      * this becomes a cached state object */
 176     if (caps->has_tcl) {
 177         OUT_CS_REG(R300_VAP_CNTL, 0xA |
 178             (0x5 << R300_PVS_NUM_CNTLRS_SHIFT) |
 179             (0xB << R300_VF_MAX_VTX_NUM_SHIFT) |
 180             (caps->num_vert_fpus << R300_PVS_NUM_FPUS_SHIFT));
 181         OUT_CS_REG(R300_VAP_PVS_CODE_CNTL_0, 0x00100000);
 182         OUT_CS_REG(R300_VAP_PVS_CONST_CNTL, 0x00000000);
 183         OUT_CS_REG(R300_VAP_PVS_CODE_CNTL_1, 0x00000001);
 184         /* XXX translate these back into normal instructions */
 185         OUT_CS_REG(R300_VAP_PVS_STATE_FLUSH_REG, 0x1);
 186         OUT_CS_REG(R300_VAP_PVS_VECTOR_INDX_REG, 0x0);
 187         OUT_CS_ONE_REG(R300_VAP_PVS_UPLOAD_DATA, 8);
 188         OUT_CS(0x00F00203);
 189         OUT_CS(0x00D10001);
 190         OUT_CS(0x01248001);
 191         OUT_CS(0x00000000);
 192         OUT_CS(0x00F02203);
 193         OUT_CS(0x00D10021);
 194         OUT_CS(0x01248021);
 195         OUT_CS(0x00000000);
 196     } else {
 197         OUT_CS_REG(R300_VAP_CNTL, 0xA |
 198             (0x5 << R300_PVS_NUM_CNTLRS_SHIFT) |
 199             (0x5 << R300_VF_MAX_VTX_NUM_SHIFT) |
 200             (caps->num_vert_fpus << R300_PVS_NUM_FPUS_SHIFT));
 201     }
 202     END_CS;
 203 }