2 * Copyright 2008 Corbin Simpson <MostAwesomeDude@gmail.com>
3 * Joakim Sindholt <opensource@zhasha.com>
5 * Permission is hereby granted, free of charge, to any person obtaining a
6 * copy of this software and associated documentation files (the "Software"),
7 * to deal in the Software without restriction, including without limitation
8 * on the rights to use, copy, modify, merge, publish, distribute, sub
9 * license, and/or sell copies of the Software, and to permit persons to whom
10 * the Software is furnished to do so, subject to the following conditions:
12 * The above copyright notice and this permission notice (including the next
13 * paragraph) shall be included in all copies or substantial portions of the
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
19 * THE AUTHOR(S) AND/OR THEIR SUPPLIERS BE LIABLE FOR ANY CLAIM,
20 * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
21 * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
22 * USE OR OTHER DEALINGS IN THE SOFTWARE. */
24 #include "r300_surface.h"
26 /* Provides pipe_context's "surface_fill". Commonly used for clearing
28 static void r300_surface_fill(struct pipe_context
* pipe
,
29 struct pipe_surface
* dest
,
30 unsigned x
, unsigned y
,
31 unsigned w
, unsigned h
,
34 struct r300_context
* r300
= r300_context(pipe
);
36 struct r300_capabilities
* caps
= ((struct r300_screen
*)pipe
->screen
)->caps
;
37 struct r300_texture
* tex
= (struct r300_texture
*)dest
->texture
;
40 unsigned pixpitch
= tex
->stride
/ tex
->tex
.block
.size
;
41 r
= (float)((color
>> 16) & 0xff) / 255.0f
;
42 g
= (float)((color
>> 8) & 0xff) / 255.0f
;
43 b
= (float)((color
>> 0) & 0xff) / 255.0f
;
44 debug_printf("r300: Filling surface %p at (%d,%d),"
45 " dimensions %dx%d (pixel pitch %d), color 0x%x\n",
46 dest
, x
, y
, w
, h
, pixpitch
, color
);
50 debug_printf("r300: Falling back on surface clear...");
51 void* map = pipe->screen->surface_map(pipe->screen, dest,
52 PIPE_BUFFER_USAGE_CPU_WRITE);
53 pipe_fill_rect(map, &dest->block, &dest->stride, x, y, w, h, color);
54 pipe->screen->surface_unmap(pipe->screen, dest);
58 r300_emit_invariant_state(r300
);
60 r300_emit_blend_state(r300
, &blend_clear_state
);
61 r300_emit_blend_color_state(r300
, &blend_color_clear_state
);
62 r300_emit_dsa_state(r300
, &dsa_clear_state
);
63 r300_emit_rs_state(r300
, &rs_clear_state
);
65 BEGIN_CS(129 + (caps
->is_r500
? 22 : 14) + (caps
->has_tcl
? 4 : 2));
67 OUT_CS_REG(R300_VAP_PVS_STATE_FLUSH_REG
, 0x0);
69 OUT_CS_REG(R300_SE_VTE_CNTL
, R300_VPORT_X_SCALE_ENA
|
70 R300_VPORT_X_OFFSET_ENA
| R300_VPORT_Y_SCALE_ENA
|
71 R300_VPORT_Y_OFFSET_ENA
| R300_VPORT_Z_SCALE_ENA
|
72 R300_VPORT_Z_OFFSET_ENA
| R300_VTX_W0_FMT
);
74 OUT_CS_REG(R300_VAP_VTX_SIZE
, 0x8);
75 /* Max and min vertex index clamp. */
76 OUT_CS_REG(R300_VAP_VF_MAX_VTX_INDX
, 0xFFFFFF);
77 OUT_CS_REG(R300_VAP_VF_MIN_VTX_INDX
, 0x0);
80 OUT_CS_REG(R300_VAP_CNTL_STATUS
, R300_VC_NO_SWAP
);
82 OUT_CS_REG(R300_VAP_CNTL_STATUS
, R300_VC_NO_SWAP
|
85 OUT_CS_REG(R300_VAP_PROG_STREAM_CNTL_0
, 0x0);
86 /* XXX magic number not in r300_reg */
87 OUT_CS_REG(R300_VAP_PSC_SGN_NORM_CNTL
, 0xAAAAAAAA);
88 OUT_CS_REG(R300_VAP_CLIP_CNTL
, 0x0);
89 OUT_CS_REG_SEQ(R300_VAP_GB_VERT_CLIP_ADJ
, 4);
94 /* XXX point tex stuffing */
95 OUT_CS_REG_SEQ(R300_GA_POINT_S0
, 1);
97 OUT_CS_REG_SEQ(R300_GA_POINT_S1
, 1);
99 OUT_CS_REG(R300_GA_TRIANGLE_STIPPLE
, 0x5 |
100 (0x5 << R300_GA_TRIANGLE_STIPPLE_Y_SHIFT_SHIFT
));
101 /* XXX should this be related to the actual point size? */
102 OUT_CS_REG(R300_GA_POINT_MINMAX
, 0x6 |
103 (0x1800 << R300_GA_POINT_MINMAX_MAX_SHIFT
));
104 /* XXX this big chunk should be refactored into rs_state */
105 OUT_CS_REG(R300_GA_LINE_S0
, 0x00000000);
106 OUT_CS_REG(R300_GA_LINE_S1
, 0x3F800000);
107 OUT_CS_REG(R300_GA_ENHANCE
, 0x00000002);
108 OUT_CS_REG(R300_GA_COLOR_CONTROL
, 0x0003AAAA);
109 OUT_CS_REG(R300_GA_SOLID_RG
, 0x00000000);
110 OUT_CS_REG(R300_GA_SOLID_BA
, 0x00000000);
111 OUT_CS_REG(R300_GA_POLY_MODE
, 0x00000000);
112 OUT_CS_REG(R300_GA_ROUND_MODE
, 0x00000001);
113 OUT_CS_REG(R300_GA_OFFSET
, 0x00000000);
114 OUT_CS_REG(R300_GA_FOG_SCALE
, 0x3DBF1412);
115 OUT_CS_REG(R300_GA_FOG_OFFSET
, 0x00000000);
116 OUT_CS_REG(R300_SU_TEX_WRAP
, 0x00000000);
117 OUT_CS_REG(R300_SU_DEPTH_SCALE
, 0x4B7FFFFF);
118 OUT_CS_REG(R300_SU_DEPTH_OFFSET
, 0x00000000);
119 OUT_CS_REG(R300_SC_HYPERZ
, 0x0000001C);
120 OUT_CS_REG(R300_SC_EDGERULE
, 0x2DA49525);
121 OUT_CS_REG(R300_FG_FOG_BLEND
, 0x00000002);
122 OUT_CS_REG(R300_FG_FOG_COLOR_R
, 0x00000000);
123 OUT_CS_REG(R300_FG_FOG_COLOR_G
, 0x00000000);
124 OUT_CS_REG(R300_FG_FOG_COLOR_B
, 0x00000000);
125 OUT_CS_REG(R300_FG_DEPTH_SRC
, 0x00000000);
126 OUT_CS_REG(R300_FG_DEPTH_SRC
, 0x00000000);
127 OUT_CS_REG(R300_RB3D_CCTL
, 0x00000000);
128 OUT_CS_REG(RB3D_COLOR_CHANNEL_MASK
, 0x0000000F);
130 /* XXX: Oh the wonderful unknown.
131 * Not writing these 8 regs seems to make no difference at all and seeing
132 * as how they're not documented, we should leave them out for now.
133 OUT_CS_REG_SEQ(0x4E54, 8);
134 for (i = 0; i < 8; i++) {
137 OUT_CS_REG(R300_RB3D_AARESOLVE_CTL
, 0x00000000);
138 OUT_CS_REG(R500_RB3D_DISCARD_SRC_PIXEL_LTE_THRESHOLD
, 0x00000000);
139 OUT_CS_REG(R500_RB3D_DISCARD_SRC_PIXEL_GTE_THRESHOLD
, 0xFFFFFFFF);
140 OUT_CS_REG(R300_ZB_FORMAT
, 0x00000002);
141 OUT_CS_REG(R300_ZB_ZCACHE_CTLSTAT
, 0x00000003);
142 OUT_CS_REG(R300_ZB_BW_CNTL
, 0x00000000);
143 OUT_CS_REG(R300_ZB_DEPTHCLEARVALUE
, 0x00000000);
144 /* XXX Moar unknown that should probably be left out.
145 OUT_CS_REG(0x4F30, 0x00000000);
146 OUT_CS_REG(0x4F34, 0x00000000); */
147 OUT_CS_REG(R300_ZB_HIZ_OFFSET
, 0x00000000);
148 OUT_CS_REG(R300_ZB_HIZ_PITCH
, 0x00000000);
150 OUT_CS_REG(R300_VAP_PROG_STREAM_CNTL_0
,
151 (R300_DATA_TYPE_FLOAT_4
<< R300_DATA_TYPE_0_SHIFT
) |
152 ((R300_LAST_VEC
| (1 << R300_DST_VEC_LOC_SHIFT
) |
153 R300_DATA_TYPE_FLOAT_4
) << R300_DATA_TYPE_1_SHIFT
));
155 OUT_CS_REG(R300_VAP_PROG_STREAM_CNTL_0
,
156 (R300_DATA_TYPE_FLOAT_4
<< R300_DATA_TYPE_0_SHIFT
) |
157 ((R300_LAST_VEC
| (2 << R300_DST_VEC_LOC_SHIFT
) |
158 R300_DATA_TYPE_FLOAT_4
) << R300_DATA_TYPE_1_SHIFT
));
160 OUT_CS_REG(R300_FG_FOG_BLEND
, 0x00000000);
161 OUT_CS_REG(R300_VAP_PROG_STREAM_CNTL_EXT_0
, 0xF688F688);
162 OUT_CS_REG(R300_VAP_VTX_STATE_CNTL
, 0x1);
163 OUT_CS_REG(R300_VAP_VSM_VTX_ASSM
, 0x405);
164 OUT_CS_REG(R300_SE_VTE_CNTL
, 0x0000043F);
165 OUT_CS_REG(R300_VAP_VTX_SIZE
, 0x00000008);
166 OUT_CS_REG(R300_VAP_PSC_SGN_NORM_CNTL
, 0xAAAAAAAA);
167 OUT_CS_REG(R300_VAP_OUTPUT_VTX_FMT_0
, 0x00000003);
168 OUT_CS_REG(R300_VAP_OUTPUT_VTX_FMT_1
, 0x00000000);
169 OUT_CS_REG(R300_TX_ENABLE
, 0x0);
170 /* XXX viewport setup */
171 OUT_CS_REG_SEQ(R300_SE_VPORT_XSCALE
, 6);
173 OUT_CS_32F((float)x
);
175 OUT_CS_32F((float)y
);
180 OUT_CS_REG(R300_VAP_CLIP_CNTL
, R300_CLIP_DISABLE
|
181 R300_PS_UCP_MODE_CLIP_AS_TRIFAN
);
185 OUT_CS_REG(R300_SC_CLIP_RULE
, 0xaaaa);
188 OUT_CS_REG_SEQ(R300_SC_SCISSORS_TL
, 2);
189 OUT_CS((x
<< R300_SCISSORS_X_SHIFT
) | (y
<< R300_SCISSORS_Y_SHIFT
));
190 OUT_CS((w
<< R300_SCISSORS_X_SHIFT
) | (h
<< R300_SCISSORS_Y_SHIFT
));
194 /* XXX We seem to be in disagreement about how many of these we have
195 * RS:RS_IP_[0-15] [R/W] 32 bits Access: 8/16/32 MMReg:0x4074-0x40b0
196 * Now that's from the docs. I don't care what the mesa driver says */
197 OUT_CS_REG_SEQ(R500_RS_IP_0
, 16);
198 for (i
= 0; i
< 16; i
++) {
199 OUT_CS((R500_RS_IP_PTR_K0
<< R500_RS_IP_TEX_PTR_S_SHIFT
) |
200 (R500_RS_IP_PTR_K0
<< R500_RS_IP_TEX_PTR_T_SHIFT
) |
201 (R500_RS_IP_PTR_K0
<< R500_RS_IP_TEX_PTR_R_SHIFT
) |
202 (R500_RS_IP_PTR_K1
<< R500_RS_IP_TEX_PTR_Q_SHIFT
));
204 OUT_CS_REG_SEQ(R300_RS_COUNT
, 2);
205 OUT_CS((1 << R300_IC_COUNT_SHIFT
) | R300_HIRES_EN
);
207 OUT_CS_REG(R500_RS_INST_0
, R500_RS_INST_COL_CN_WRITE
);
209 OUT_CS_REG_SEQ(R300_RS_IP_0
, 8);
210 for (i
= 0; i
< 8; i
++) {
211 OUT_CS(R300_RS_SEL_T(R300_RS_SEL_K0
) |
212 R300_RS_SEL_R(R300_RS_SEL_K0
) | R300_RS_SEL_Q(R300_RS_SEL_K1
));
214 OUT_CS_REG_SEQ(R300_RS_COUNT
, 2);
215 OUT_CS((1 << R300_IC_COUNT_SHIFT
) | R300_HIRES_EN
);
216 /* XXX Shouldn't this be 0? */
218 OUT_CS_REG(R300_RS_INST_0
, R300_RS_INST_COL_CN_WRITE
);
222 /* Fragment shader setup */
224 r500_emit_fragment_shader(r300
, &r500_passthrough_fragment_shader
);
226 r300_emit_fragment_shader(r300
, &r300_passthrough_fragment_shader
);
229 BEGIN_CS(7 + (caps
->has_tcl
? 21 : 2));
230 OUT_CS_REG_SEQ(R300_US_OUT_FMT_0
, 4);
231 OUT_CS(R300_C0_SEL_B
| R300_C1_SEL_G
| R300_C2_SEL_R
| R300_C3_SEL_A
);
232 OUT_CS(R300_US_OUT_FMT_UNUSED
);
233 OUT_CS(R300_US_OUT_FMT_UNUSED
);
234 OUT_CS(R300_US_OUT_FMT_UNUSED
);
235 OUT_CS_REG(R300_US_W_FMT
, R300_W_FMT_W0
);
236 /* XXX these magic numbers should be explained when
237 * this becomes a cached state object */
239 OUT_CS_REG(R300_VAP_CNTL
, 0xA |
240 (0x5 << R300_PVS_NUM_CNTLRS_SHIFT
) |
241 (0xB << R300_VF_MAX_VTX_NUM_SHIFT
) |
242 (caps
->num_vert_fpus
<< R300_PVS_NUM_FPUS_SHIFT
));
243 OUT_CS_REG(R300_VAP_PVS_CODE_CNTL_0
, 0x00100000);
244 OUT_CS_REG(R300_VAP_PVS_CONST_CNTL
, 0x00000000);
245 OUT_CS_REG(R300_VAP_PVS_CODE_CNTL_1
, 0x00000001);
246 /* XXX translate these back into normal instructions */
247 OUT_CS_REG(R300_VAP_PVS_STATE_FLUSH_REG
, 0x1);
248 OUT_CS_REG(R300_VAP_PVS_VECTOR_INDX_REG
, 0x0);
249 OUT_CS_ONE_REG(R300_VAP_PVS_UPLOAD_DATA
, 8);
259 OUT_CS_REG(R300_VAP_CNTL
, 0xA |
260 (0x5 << R300_PVS_NUM_CNTLRS_SHIFT
) |
261 (0x5 << R300_VF_MAX_VTX_NUM_SHIFT
) |
262 (caps
->num_vert_fpus
<< R300_PVS_NUM_FPUS_SHIFT
));
266 /* The size of the point we're about to draw, in sixths of pixels */
267 OUT_CS_REG(R300_GA_POINT_SIZE
,
268 ((h
* 6) & R300_POINTSIZE_Y_MASK
) |
269 ((w
* 6) << R300_POINTSIZE_X_SHIFT
));
272 /* Flush colorbuffer and blend caches. */
273 OUT_CS_REG(R300_RB3D_DSTCACHE_CTLSTAT
,
274 R300_RB3D_DSTCACHE_CTLSTAT_DC_FLUSH_FLUSH_DIRTY_3D
|
275 R300_RB3D_DSTCACHE_CTLSTAT_DC_FINISH_SIGNAL
);
276 OUT_CS_REG(R300_ZB_ZCACHE_CTLSTAT
,
277 R300_ZB_ZCACHE_CTLSTAT_ZC_FLUSH_FLUSH_AND_FREE
|
278 R300_ZB_ZCACHE_CTLSTAT_ZC_FREE_FREE
);
280 OUT_CS_REG_SEQ(R300_RB3D_COLOROFFSET0
, 1);
281 OUT_CS_RELOC(tex
->buffer
, 0, 0, RADEON_GEM_DOMAIN_VRAM
, 0);
282 OUT_CS_REG(R300_RB3D_COLORPITCH0
, pixpitch
|
283 r300_translate_colorformat(tex
->tex
.format
));
284 OUT_CS_REG(RB3D_COLOR_CHANNEL_MASK
, 0x0000000F);
286 OUT_CS(CP_PACKET3(R200_3D_DRAW_IMMD_2
, 8));
287 OUT_CS(R300_PRIM_TYPE_POINT
| R300_PRIM_WALK_RING
|
288 (1 << R300_PRIM_NUM_VERTICES_SHIFT
));
291 /* XXX this should be the depth value to clear to */
299 /* XXX figure out why this is 0xA and not 0x2 */
300 OUT_CS_REG(R300_RB3D_DSTCACHE_CTLSTAT
, 0xA);
301 /* XXX OUT_CS_REG(R300_ZB_ZCACHE_CTLSTAT,
302 R300_ZB_ZCACHE_CTLSTAT_ZC_FLUSH_FLUSH_AND_FREE |
303 R300_ZB_ZCACHE_CTLSTAT_ZC_FREE_FREE); */
310 void r300_init_surface_functions(struct r300_context
* r300
)
312 r300
->context
.surface_fill
= r300_surface_fill
;