src/gallium/drivers/r300/r300_surface.c

   1 /*
   2  * Copyright 2008 Corbin Simpson <MostAwesomeDude@gmail.com>
   3  *                Joakim Sindholt <opensource@zhasha.com>
   4  *
   5  * Permission is hereby granted, free of charge, to any person obtaining a
   6  * copy of this software and associated documentation files (the "Software"),
   7  * to deal in the Software without restriction, including without limitation
   8  * on the rights to use, copy, modify, merge, publish, distribute, sub
   9  * license, and/or sell copies of the Software, and to permit persons to whom
  10  * the Software is furnished to do so, subject to the following conditions:
  11  *
  12  * The above copyright notice and this permission notice (including the next
  13  * paragraph) shall be included in all copies or substantial portions of the
  14  * Software.
  15  *
  16  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  17  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  18  * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
  19  * THE AUTHOR(S) AND/OR THEIR SUPPLIERS BE LIABLE FOR ANY CLAIM,
  20  * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
  21  * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
  22  * USE OR OTHER DEALINGS IN THE SOFTWARE. */
  23
  24 #include "r300_surface.h"
  25
  26 /* Provides pipe_context's "surface_fill". Commonly used for clearing
  27  * buffers. */
  28 static void r300_surface_fill(struct pipe_context* pipe,
  29                               struct pipe_surface* dest,
  30                               unsigned x, unsigned y,
  31                               unsigned w, unsigned h,
  32                               unsigned color)
  33 {
  34     struct r300_context* r300 = r300_context(pipe);
  35     CS_LOCALS(r300);
  36     struct r300_capabilities* caps = ((struct r300_screen*)pipe->screen)->caps;
  37     struct r300_texture* tex = (struct r300_texture*)dest->texture;
  38     int i;
  39     float r, g, b, a;
  40     unsigned pixpitch = tex->stride / tex->tex.block.size;
  41     r = (float)((color >> 16) & 0xff) / 255.0f;
  42     g = (float)((color >>  8) & 0xff) / 255.0f;
  43     b = (float)((color >>  0) & 0xff) / 255.0f;
  44     debug_printf("r300: Filling surface %p at (%d,%d),"
  45         " dimensions %dx%d (pixel pitch %d), color 0x%x\n",
  46         dest, x, y, w, h, pixpitch, color);
  47
  48     /* Fallback? */
  49     /*if (0) {
  50         debug_printf("r300: Falling back on surface clear...");
  51         void* map = pipe->screen->surface_map(pipe->screen, dest,
  52             PIPE_BUFFER_USAGE_CPU_WRITE);
  53         pipe_fill_rect(map, &dest->block, &dest->stride, x, y, w, h, color);
  54         pipe->screen->surface_unmap(pipe->screen, dest);
  55         return;
  56     }*/
  57
  58     r300_emit_blend_state(r300, &blend_clear_state);
  59     r300_emit_blend_color_state(r300, &blend_color_clear_state);
  60     r300_emit_dsa_state(r300, &dsa_clear_state);
  61     r300_emit_rs_state(r300, &rs_clear_state);
  62
  63     BEGIN_CS(143 + (caps->is_r500 ? 22 : 14) + (caps->has_tcl ? 4 : 2));
  64     /* Flush PVS. */
  65     OUT_CS_REG(R300_VAP_PVS_STATE_FLUSH_REG, 0x0);
  66
  67     OUT_CS_REG(R300_SE_VTE_CNTL, R300_VPORT_X_SCALE_ENA |
  68         R300_VPORT_X_OFFSET_ENA | R300_VPORT_Y_SCALE_ENA |
  69         R300_VPORT_Y_OFFSET_ENA | R300_VPORT_Z_SCALE_ENA |
  70         R300_VPORT_Z_OFFSET_ENA | R300_VTX_W0_FMT);
  71     /* Vertex size. */
  72     OUT_CS_REG(R300_VAP_VTX_SIZE, 0x8);
  73     /* Max and min vertex index clamp. */
  74     OUT_CS_REG(R300_VAP_VF_MAX_VTX_INDX, 0xFFFFFF);
  75     OUT_CS_REG(R300_VAP_VF_MIN_VTX_INDX, 0x0);
  76     /* XXX endian */
  77     if (caps->has_tcl) {
  78         OUT_CS_REG(R300_VAP_CNTL_STATUS, R300_VC_NO_SWAP);
  79     } else {
  80         OUT_CS_REG(R300_VAP_CNTL_STATUS, R300_VC_NO_SWAP |
  81                 R300_VAP_TCL_BYPASS);
  82     }
  83     OUT_CS_REG(R300_VAP_PROG_STREAM_CNTL_0, 0x0);
  84     /* XXX magic number not in r300_reg */
  85     OUT_CS_REG(R300_VAP_PSC_SGN_NORM_CNTL, 0xAAAAAAAA);
  86     OUT_CS_REG(R300_VAP_CLIP_CNTL, 0x0);
  87     OUT_CS_REG_SEQ(R300_VAP_GB_VERT_CLIP_ADJ, 4);
  88     OUT_CS_32F(1.0);
  89     OUT_CS_32F(1.0);
  90     OUT_CS_32F(1.0);
  91     OUT_CS_32F(1.0);
  92     /* XXX is this too long? */
  93     OUT_CS_REG(VAP_PVS_VTX_TIMEOUT_REG, 0xFFFF);
  94     OUT_CS_REG(R300_GB_ENABLE, R300_GB_POINT_STUFF_ENABLE |
  95         R300_GB_LINE_STUFF_ENABLE | R300_GB_TRIANGLE_STUFF_ENABLE);
  96     /* XXX more magic numbers */
  97     OUT_CS_REG(R300_GB_MSPOS0, 0x66666666);
  98     OUT_CS_REG(R300_GB_MSPOS1, 0x66666666);
  99     /* XXX why doesn't classic Mesa write the number of pipes, too? */
 100     OUT_CS_REG(R300_GB_TILE_CONFIG, R300_GB_TILE_ENABLE |
 101         R300_GB_TILE_SIZE_16);
 102     OUT_CS_REG(R300_GB_SELECT, R300_GB_FOG_SELECT_1_1_W);
 103     OUT_CS_REG(R300_GB_AA_CONFIG, 0x0);
 104     /* XXX point tex stuffing */
 105     OUT_CS_REG_SEQ(R300_GA_POINT_S0, 1);
 106     OUT_CS_32F(0.0);
 107     OUT_CS_REG_SEQ(R300_GA_POINT_S1, 1);
 108     OUT_CS_32F(1.0);
 109     OUT_CS_REG(R300_GA_TRIANGLE_STIPPLE, 0x5 |
 110         (0x5 << R300_GA_TRIANGLE_STIPPLE_Y_SHIFT_SHIFT));
 111     /* XXX should this be related to the actual point size? */
 112     OUT_CS_REG(R300_GA_POINT_MINMAX, 0x6 |
 113         (0x1800 << R300_GA_POINT_MINMAX_MAX_SHIFT));
 114     /* XXX this big chunk should be refactored into rs_state */
 115     OUT_CS_REG(R300_GA_LINE_S0, 0x00000000);
 116     OUT_CS_REG(R300_GA_LINE_S1, 0x3F800000);
 117     OUT_CS_REG(R300_GA_ENHANCE, 0x00000002);
 118     OUT_CS_REG(R300_GA_COLOR_CONTROL, 0x0003AAAA);
 119     OUT_CS_REG(R300_GA_SOLID_RG, 0x00000000);
 120     OUT_CS_REG(R300_GA_SOLID_BA, 0x00000000);
 121     OUT_CS_REG(R300_GA_POLY_MODE, 0x00000000);
 122     OUT_CS_REG(R300_GA_ROUND_MODE, 0x00000001);
 123     OUT_CS_REG(R300_GA_OFFSET, 0x00000000);
 124     OUT_CS_REG(R300_GA_FOG_SCALE, 0x3DBF1412);
 125     OUT_CS_REG(R300_GA_FOG_OFFSET, 0x00000000);
 126     OUT_CS_REG(R300_SU_TEX_WRAP, 0x00000000);
 127     OUT_CS_REG(R300_SU_DEPTH_SCALE, 0x4B7FFFFF);
 128     OUT_CS_REG(R300_SU_DEPTH_OFFSET, 0x00000000);
 129     OUT_CS_REG(R300_SC_HYPERZ, 0x0000001C);
 130     OUT_CS_REG(R300_SC_EDGERULE, 0x2DA49525);
 131     OUT_CS_REG(R300_FG_FOG_BLEND, 0x00000002);
 132     OUT_CS_REG(R300_FG_FOG_COLOR_R, 0x00000000);
 133     OUT_CS_REG(R300_FG_FOG_COLOR_G, 0x00000000);
 134     OUT_CS_REG(R300_FG_FOG_COLOR_B, 0x00000000);
 135     OUT_CS_REG(R300_FG_DEPTH_SRC, 0x00000000);
 136     OUT_CS_REG(R300_FG_DEPTH_SRC, 0x00000000);
 137     OUT_CS_REG(R300_RB3D_CCTL, 0x00000000);
 138     OUT_CS_REG(RB3D_COLOR_CHANNEL_MASK, 0x0000000F);
 139
 140     /* XXX: Oh the wonderful unknown.
 141      * Not writing these 8 regs seems to make no difference at all and seeing
 142      * as how they're not documented, we should leave them out for now.
 143     OUT_CS_REG_SEQ(0x4E54, 8);
 144     for (i = 0; i < 8; i++) {
 145         OUT_CS(0x00000000);
 146     } */
 147     OUT_CS_REG(R300_RB3D_AARESOLVE_CTL, 0x00000000);
 148     OUT_CS_REG(R500_RB3D_DISCARD_SRC_PIXEL_LTE_THRESHOLD, 0x00000000);
 149     OUT_CS_REG(R500_RB3D_DISCARD_SRC_PIXEL_GTE_THRESHOLD, 0xFFFFFFFF);
 150     OUT_CS_REG(R300_ZB_FORMAT, 0x00000002);
 151     OUT_CS_REG(R300_ZB_ZCACHE_CTLSTAT, 0x00000003);
 152     OUT_CS_REG(R300_ZB_BW_CNTL, 0x00000000);
 153     OUT_CS_REG(R300_ZB_DEPTHCLEARVALUE, 0x00000000);
 154     /* XXX Moar unknown that should probably be left out.
 155     OUT_CS_REG(0x4F30, 0x00000000);
 156     OUT_CS_REG(0x4F34, 0x00000000); */
 157     OUT_CS_REG(R300_ZB_HIZ_OFFSET, 0x00000000);
 158     OUT_CS_REG(R300_ZB_HIZ_PITCH, 0x00000000);
 159     if (caps->has_tcl) {
 160         OUT_CS_REG(R300_VAP_PROG_STREAM_CNTL_0,
 161             (R300_DATA_TYPE_FLOAT_4 << R300_DATA_TYPE_0_SHIFT) |
 162             ((R300_LAST_VEC | (1 << R300_DST_VEC_LOC_SHIFT) |
 163                 R300_DATA_TYPE_FLOAT_4) << R300_DATA_TYPE_1_SHIFT));
 164     } else {
 165         OUT_CS_REG(R300_VAP_PROG_STREAM_CNTL_0,
 166             (R300_DATA_TYPE_FLOAT_4 << R300_DATA_TYPE_0_SHIFT) |
 167             ((R300_LAST_VEC | (2 << R300_DST_VEC_LOC_SHIFT) |
 168                 R300_DATA_TYPE_FLOAT_4) << R300_DATA_TYPE_1_SHIFT));
 169     }
 170     OUT_CS_REG(R300_FG_FOG_BLEND, 0x00000000);
 171     OUT_CS_REG(R300_VAP_PROG_STREAM_CNTL_EXT_0, 0xF688F688);
 172     OUT_CS_REG(R300_VAP_VTX_STATE_CNTL, 0x1);
 173     OUT_CS_REG(R300_VAP_VSM_VTX_ASSM, 0x405);
 174     OUT_CS_REG(R300_SE_VTE_CNTL, 0x0000043F);
 175     OUT_CS_REG(R300_VAP_VTX_SIZE, 0x00000008);
 176     OUT_CS_REG(R300_VAP_PSC_SGN_NORM_CNTL, 0xAAAAAAAA);
 177     OUT_CS_REG(R300_VAP_OUTPUT_VTX_FMT_0, 0x00000003);
 178     OUT_CS_REG(R300_VAP_OUTPUT_VTX_FMT_1, 0x00000000);
 179     OUT_CS_REG(R300_TX_ENABLE, 0x0);
 180     /* XXX viewport setup */
 181     OUT_CS_REG_SEQ(R300_SE_VPORT_XSCALE, 6);
 182     OUT_CS_32F(1.0);
 183     OUT_CS_32F((float)x);
 184     OUT_CS_32F(1.0);
 185     OUT_CS_32F((float)y);
 186     OUT_CS_32F(1.0);
 187     OUT_CS_32F(0.0);
 188
 189     if (caps->has_tcl) {
 190         OUT_CS_REG(R300_VAP_CLIP_CNTL, R300_CLIP_DISABLE |
 191             R300_PS_UCP_MODE_CLIP_AS_TRIFAN);
 192     }
 193
 194     /* XXX */
 195     OUT_CS_REG(R300_SC_CLIP_RULE, 0xaaaa);
 196
 197     /* Pixel scissors */
 198     OUT_CS_REG_SEQ(R300_SC_SCISSORS_TL, 2);
 199     OUT_CS((x << R300_SCISSORS_X_SHIFT) | (y << R300_SCISSORS_Y_SHIFT));
 200     OUT_CS((w << R300_SCISSORS_X_SHIFT) | (h << R300_SCISSORS_Y_SHIFT));
 201
 202     /* RS block setup */
 203     if (caps->is_r500) {
 204         /* XXX We seem to be in disagreement about how many of these we have
 205          * RS:RS_IP_[0-15] [R/W] 32 bits Access: 8/16/32 MMReg:0x4074-0x40b0
 206          * Now that's from the docs. I don't care what the mesa driver says */
 207         OUT_CS_REG_SEQ(R500_RS_IP_0, 16);
 208         for (i = 0; i < 16; i++) {
 209             OUT_CS((R500_RS_IP_PTR_K0 << R500_RS_IP_TEX_PTR_S_SHIFT) |
 210                 (R500_RS_IP_PTR_K0 << R500_RS_IP_TEX_PTR_T_SHIFT) |
 211                 (R500_RS_IP_PTR_K0 << R500_RS_IP_TEX_PTR_R_SHIFT) |
 212                 (R500_RS_IP_PTR_K1 << R500_RS_IP_TEX_PTR_Q_SHIFT));
 213         }
 214         OUT_CS_REG_SEQ(R300_RS_COUNT, 2);
 215         OUT_CS((1 << R300_IC_COUNT_SHIFT) | R300_HIRES_EN);
 216         OUT_CS(0x00000000);
 217         OUT_CS_REG(R500_RS_INST_0, R500_RS_INST_COL_CN_WRITE);
 218     } else {
 219         OUT_CS_REG_SEQ(R300_RS_IP_0, 8);
 220         for (i = 0; i < 8; i++) {
 221             OUT_CS(R300_RS_SEL_T(R300_RS_SEL_K0) |
 222                 R300_RS_SEL_R(R300_RS_SEL_K0) | R300_RS_SEL_Q(R300_RS_SEL_K1));
 223         }
 224         OUT_CS_REG_SEQ(R300_RS_COUNT, 2);
 225         OUT_CS((1 << R300_IC_COUNT_SHIFT) | R300_HIRES_EN);
 226         /* XXX Shouldn't this be 0? */
 227         OUT_CS(1);
 228         OUT_CS_REG(R300_RS_INST_0, R300_RS_INST_COL_CN_WRITE);
 229     }
 230     END_CS;
 231
 232     /* Fragment shader setup */
 233     if (caps->is_r500) {
 234         r500_emit_fragment_shader(r300, &r500_passthrough_fragment_shader);
 235     } else {
 236         r300_emit_fragment_shader(r300, &r300_passthrough_fragment_shader);
 237     }
 238
 239     BEGIN_CS(8 + (caps->has_tcl ? 20 : 2));
 240     OUT_CS_REG_SEQ(R300_US_OUT_FMT_0, 4);
 241     OUT_CS(R300_C0_SEL_B | R300_C1_SEL_G | R300_C2_SEL_R | R300_C3_SEL_A);
 242     OUT_CS(R300_US_OUT_FMT_UNUSED);
 243     OUT_CS(R300_US_OUT_FMT_UNUSED);
 244     OUT_CS(R300_US_OUT_FMT_UNUSED);
 245     OUT_CS_REG(R300_US_W_FMT, R300_W_FMT_W0);
 246     /* XXX these magic numbers should be explained when
 247      * this becomes a cached state object */
 248     if (caps->has_tcl) {
 249         OUT_CS_REG(R300_VAP_CNTL, 0xA |
 250             (0x5 << R300_PVS_NUM_CNTLRS_SHIFT) |
 251             (0xB << R300_VF_MAX_VTX_NUM_SHIFT) |
 252             (caps->num_vert_fpus << R300_PVS_NUM_FPUS_SHIFT));
 253         OUT_CS_REG(R300_VAP_PVS_CODE_CNTL_0, 0x00100000);
 254         OUT_CS_REG(R300_VAP_PVS_CONST_CNTL, 0x00000000);
 255         OUT_CS_REG(R300_VAP_PVS_CODE_CNTL_1, 0x00000001);
 256         /* XXX translate these back into normal instructions */
 257         OUT_CS_REG(R300_VAP_PVS_STATE_FLUSH_REG, 0x1);
 258         OUT_CS_REG(R300_VAP_PVS_VECTOR_INDX_REG, 0x0);
 259         OUT_CS_ONE_REG(R300_VAP_PVS_UPLOAD_DATA, 8);
 260         OUT_CS(0x00F00203);
 261         OUT_CS(0x00D10001);
 262         OUT_CS(0x01248001);
 263         OUT_CS(0x00000000);
 264         OUT_CS(0x00F02203);
 265         OUT_CS(0x00D10021);
 266         OUT_CS(0x01248021);
 267         OUT_CS(0x00000000);
 268     } else {
 269         OUT_CS_REG(R300_VAP_CNTL, 0xA |
 270             (0x5 << R300_PVS_NUM_CNTLRS_SHIFT) |
 271             (0x5 << R300_VF_MAX_VTX_NUM_SHIFT) |
 272             (caps->num_vert_fpus << R300_PVS_NUM_FPUS_SHIFT));
 273     }
 274     END_CS;
 275
 276     /* The size of the point we're about to draw, in sixths of pixels */
 277     OUT_CS_REG(R300_GA_POINT_SIZE,
 278         ((h * 6) & R300_POINTSIZE_Y_MASK) |
 279         ((w * 6) << R300_POINTSIZE_X_SHIFT));
 280
 281     BEGIN_CS(24);
 282     /* Flush colorbuffer and blend caches. */
 283     OUT_CS_REG(R300_RB3D_DSTCACHE_CTLSTAT,
 284         R300_RB3D_DSTCACHE_CTLSTAT_DC_FLUSH_FLUSH_DIRTY_3D |
 285         R300_RB3D_DSTCACHE_CTLSTAT_DC_FINISH_SIGNAL);
 286     OUT_CS_REG(R300_ZB_ZCACHE_CTLSTAT,
 287         R300_ZB_ZCACHE_CTLSTAT_ZC_FLUSH_FLUSH_AND_FREE |
 288         R300_ZB_ZCACHE_CTLSTAT_ZC_FREE_FREE);
 289
 290     OUT_CS_REG_SEQ(R300_RB3D_COLOROFFSET0, 1);
 291     OUT_CS_RELOC(tex->buffer, 0, 0, RADEON_GEM_DOMAIN_VRAM, 0);
 292     OUT_CS_REG(R300_RB3D_COLORPITCH0, pixpitch |
 293         r300_translate_colorformat(tex->tex.format));
 294     OUT_CS_REG(RB3D_COLOR_CHANNEL_MASK, 0x0000000F);
 295     /* XXX Packet3 */
 296     OUT_CS(CP_PACKET3(R200_3D_DRAW_IMMD_2, 8));
 297     OUT_CS(R300_PRIM_TYPE_POINT | R300_PRIM_WALK_RING |
 298     (1 << R300_PRIM_NUM_VERTICES_SHIFT));
 299     OUT_CS_32F(w / 2.0);
 300     OUT_CS_32F(h / 2.0);
 301     /* XXX this should be the depth value to clear to */
 302     OUT_CS_32F(1.0);
 303     OUT_CS_32F(1.0);
 304     OUT_CS_32F(r);
 305     OUT_CS_32F(g);
 306     OUT_CS_32F(b);
 307     OUT_CS_32F(1.0);
 308
 309     /* XXX figure out why this is 0xA and not 0x2 */
 310     OUT_CS_REG(R300_RB3D_DSTCACHE_CTLSTAT, 0xA);
 311     /* XXX OUT_CS_REG(R300_ZB_ZCACHE_CTLSTAT,
 312         R300_ZB_ZCACHE_CTLSTAT_ZC_FLUSH_FLUSH_AND_FREE |
 313         R300_ZB_ZCACHE_CTLSTAT_ZC_FREE_FREE); */
 314
 315     END_CS;
 316
 317     r300->dirty_hw++;
 318 }
 319
 320 void r300_init_surface_functions(struct r300_context* r300)
 321 {
 322     r300->context.surface_fill = r300_surface_fill;
 323 }