src/gallium/drivers/r300/r300_surface.c

   1 /*
   2  * Copyright 2008 Corbin Simpson <MostAwesomeDude@gmail.com>
   3  *                Joakim Sindholt <opensource@zhasha.com>
   4  *
   5  * Permission is hereby granted, free of charge, to any person obtaining a
   6  * copy of this software and associated documentation files (the "Software"),
   7  * to deal in the Software without restriction, including without limitation
   8  * on the rights to use, copy, modify, merge, publish, distribute, sub
   9  * license, and/or sell copies of the Software, and to permit persons to whom
  10  * the Software is furnished to do so, subject to the following conditions:
  11  *
  12  * The above copyright notice and this permission notice (including the next
  13  * paragraph) shall be included in all copies or substantial portions of the
  14  * Software.
  15  *
  16  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  17  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  18  * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
  19  * THE AUTHOR(S) AND/OR THEIR SUPPLIERS BE LIABLE FOR ANY CLAIM,
  20  * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
  21  * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
  22  * USE OR OTHER DEALINGS IN THE SOFTWARE. */
  23
  24 #include "r300_surface.h"
  25
  26 /* Provides pipe_context's "surface_fill". Commonly used for clearing
  27  * buffers. */
  28 static void r300_surface_fill(struct pipe_context* pipe,
  29                               struct pipe_surface* dest,
  30                               unsigned x, unsigned y,
  31                               unsigned w, unsigned h,
  32                               unsigned color)
  33 {
  34     struct r300_context* r300 = r300_context(pipe);
  35     CS_LOCALS(r300);
  36     struct r300_capabilities* caps = r300_screen(pipe->screen)->caps;
  37     struct r300_texture* tex = (struct r300_texture*)dest->texture;
  38     int i;
  39
  40     float r, g, b, a;
  41     unsigned pixpitch = tex->stride / tex->tex.block.size;
  42     r = (float)((color >> 16) & 0xff) / 255.0f;
  43     g = (float)((color >>  8) & 0xff) / 255.0f;
  44     b = (float)((color >>  0) & 0xff) / 255.0f;
  45     debug_printf("r300: Filling surface %p at (%d,%d),"
  46         " dimensions %dx%d (pixel pitch %d), color 0x%x\n",
  47         dest, x, y, w, h, pixpitch, color);
  48
  49     /* Fallback? */
  50     /*if (0) {
  51         debug_printf("r300: Falling back on surface clear...");
  52         void* map = pipe->screen->surface_map(pipe->screen, dest,
  53             PIPE_BUFFER_USAGE_CPU_WRITE);
  54         pipe_fill_rect(map, &dest->block, &dest->stride, x, y, w, h, color);
  55         pipe->screen->surface_unmap(pipe->screen, dest);
  56         return;
  57     }*/
  58
  59     r300_emit_invariant_state(r300);
  60
  61     r300_emit_blend_state(r300, &blend_clear_state);
  62     r300_emit_blend_color_state(r300, &blend_color_clear_state);
  63     r300_emit_dsa_state(r300, &dsa_clear_state);
  64     r300_emit_rs_state(r300, &rs_clear_state);
  65
  66     /* Fragment shader setup */
  67     if (caps->is_r500) {
  68         r500_emit_fragment_shader(r300, &r500_passthrough_fragment_shader);
  69         r300_emit_rs_block_state(r300, &r500_rs_block_clear_state);
  70     } else {
  71         r300_emit_fragment_shader(r300, &r300_passthrough_fragment_shader);
  72         r300_emit_rs_block_state(r300, &r300_rs_block_clear_state);
  73     }
  74
  75     BEGIN_CS(124 + (caps->has_tcl ? 2 : 0));
  76     /* Flush PVS. */
  77     OUT_CS_REG(R300_VAP_PVS_STATE_FLUSH_REG, 0x0);
  78
  79     OUT_CS_REG(R300_SE_VTE_CNTL, R300_VPORT_X_SCALE_ENA |
  80         R300_VPORT_X_OFFSET_ENA | R300_VPORT_Y_SCALE_ENA |
  81         R300_VPORT_Y_OFFSET_ENA | R300_VPORT_Z_SCALE_ENA |
  82         R300_VPORT_Z_OFFSET_ENA | R300_VTX_W0_FMT);
  83     /* Vertex size. */
  84     OUT_CS_REG(R300_VAP_VTX_SIZE, 0x8);
  85     /* Max and min vertex index clamp. */
  86     OUT_CS_REG(R300_VAP_VF_MAX_VTX_INDX, 0xFFFFFF);
  87     OUT_CS_REG(R300_VAP_VF_MIN_VTX_INDX, 0x0);
  88     /* XXX endian */
  89     if (caps->has_tcl) {
  90         OUT_CS_REG(R300_VAP_CNTL_STATUS, R300_VC_NO_SWAP);
  91     } else {
  92         OUT_CS_REG(R300_VAP_CNTL_STATUS, R300_VC_NO_SWAP |
  93                 R300_VAP_TCL_BYPASS);
  94     }
  95     OUT_CS_REG(R300_VAP_PROG_STREAM_CNTL_0, 0x0);
  96     /* XXX magic number not in r300_reg */
  97     OUT_CS_REG(R300_VAP_PSC_SGN_NORM_CNTL, 0xAAAAAAAA);
  98     OUT_CS_REG(R300_VAP_CLIP_CNTL, 0x0);
  99     OUT_CS_REG_SEQ(R300_VAP_GB_VERT_CLIP_ADJ, 4);
 100     OUT_CS_32F(1.0);
 101     OUT_CS_32F(1.0);
 102     OUT_CS_32F(1.0);
 103     OUT_CS_32F(1.0);
 104     /* XXX point tex stuffing */
 105     OUT_CS_REG_SEQ(R300_GA_POINT_S0, 1);
 106     OUT_CS_32F(0.0);
 107     OUT_CS_REG_SEQ(R300_GA_POINT_S1, 1);
 108     OUT_CS_32F(1.0);
 109     OUT_CS_REG(R300_GA_TRIANGLE_STIPPLE, 0x5 |
 110         (0x5 << R300_GA_TRIANGLE_STIPPLE_Y_SHIFT_SHIFT));
 111     /* XXX this big chunk should be refactored into rs_state */
 112     OUT_CS_REG(R300_GA_LINE_S0, 0x00000000);
 113     OUT_CS_REG(R300_GA_LINE_S1, 0x3F800000);
 114     OUT_CS_REG(R300_GA_ENHANCE, 0x00000002);
 115     OUT_CS_REG(R300_GA_SOLID_RG, 0x00000000);
 116     OUT_CS_REG(R300_GA_SOLID_BA, 0x00000000);
 117     OUT_CS_REG(R300_GA_POLY_MODE, 0x00000000);
 118     OUT_CS_REG(R300_GA_ROUND_MODE, 0x00000001);
 119     OUT_CS_REG(R300_GA_OFFSET, 0x00000000);
 120     OUT_CS_REG(R300_GA_FOG_SCALE, 0x3DBF1412);
 121     OUT_CS_REG(R300_GA_FOG_OFFSET, 0x00000000);
 122     OUT_CS_REG(R300_SU_TEX_WRAP, 0x00000000);
 123     OUT_CS_REG(R300_SU_DEPTH_SCALE, 0x4B7FFFFF);
 124     OUT_CS_REG(R300_SU_DEPTH_OFFSET, 0x00000000);
 125     OUT_CS_REG(R300_SC_HYPERZ, 0x0000001C);
 126     OUT_CS_REG(R300_SC_EDGERULE, 0x2DA49525);
 127     OUT_CS_REG(R300_FG_FOG_BLEND, 0x00000002);
 128     OUT_CS_REG(R300_FG_FOG_COLOR_R, 0x00000000);
 129     OUT_CS_REG(R300_FG_FOG_COLOR_G, 0x00000000);
 130     OUT_CS_REG(R300_FG_FOG_COLOR_B, 0x00000000);
 131     OUT_CS_REG(R300_FG_DEPTH_SRC, 0x00000000);
 132     OUT_CS_REG(R300_FG_DEPTH_SRC, 0x00000000);
 133     OUT_CS_REG(R300_RB3D_CCTL, 0x00000000);
 134     OUT_CS_REG(RB3D_COLOR_CHANNEL_MASK, 0x0000000F);
 135
 136     /* XXX: Oh the wonderful unknown.
 137      * Not writing these 8 regs seems to make no difference at all and seeing
 138      * as how they're not documented, we should leave them out for now.
 139     OUT_CS_REG_SEQ(0x4E54, 8);
 140     for (i = 0; i < 8; i++) {
 141         OUT_CS(0x00000000);
 142     } */
 143     OUT_CS_REG(R300_RB3D_AARESOLVE_CTL, 0x00000000);
 144     OUT_CS_REG(R500_RB3D_DISCARD_SRC_PIXEL_LTE_THRESHOLD, 0x00000000);
 145     OUT_CS_REG(R500_RB3D_DISCARD_SRC_PIXEL_GTE_THRESHOLD, 0xFFFFFFFF);
 146     OUT_CS_REG(R300_ZB_FORMAT, 0x00000002);
 147     OUT_CS_REG(R300_ZB_ZCACHE_CTLSTAT, 0x00000003);
 148     OUT_CS_REG(R300_ZB_BW_CNTL, 0x00000000);
 149     OUT_CS_REG(R300_ZB_DEPTHCLEARVALUE, 0x00000000);
 150     /* XXX Moar unknown that should probably be left out.
 151     OUT_CS_REG(0x4F30, 0x00000000);
 152     OUT_CS_REG(0x4F34, 0x00000000); */
 153     OUT_CS_REG(R300_ZB_HIZ_OFFSET, 0x00000000);
 154     OUT_CS_REG(R300_ZB_HIZ_PITCH, 0x00000000);
 155     if (caps->has_tcl) {
 156         OUT_CS_REG(R300_VAP_PROG_STREAM_CNTL_0,
 157             (R300_DATA_TYPE_FLOAT_4 << R300_DATA_TYPE_0_SHIFT) |
 158             ((R300_LAST_VEC | (1 << R300_DST_VEC_LOC_SHIFT) |
 159                 R300_DATA_TYPE_FLOAT_4) << R300_DATA_TYPE_1_SHIFT));
 160     } else {
 161         OUT_CS_REG(R300_VAP_PROG_STREAM_CNTL_0,
 162             (R300_DATA_TYPE_FLOAT_4 << R300_DATA_TYPE_0_SHIFT) |
 163             ((R300_LAST_VEC | (2 << R300_DST_VEC_LOC_SHIFT) |
 164                 R300_DATA_TYPE_FLOAT_4) << R300_DATA_TYPE_1_SHIFT));
 165     }
 166     OUT_CS_REG(R300_FG_FOG_BLEND, 0x00000000);
 167     OUT_CS_REG(R300_VAP_PROG_STREAM_CNTL_EXT_0, 0xF688F688);
 168     OUT_CS_REG(R300_VAP_VTX_STATE_CNTL, 0x1);
 169     OUT_CS_REG(R300_VAP_VSM_VTX_ASSM, 0x405);
 170     OUT_CS_REG(R300_SE_VTE_CNTL, 0x0000043F);
 171     OUT_CS_REG(R300_VAP_VTX_SIZE, 0x00000008);
 172     OUT_CS_REG(R300_VAP_PSC_SGN_NORM_CNTL, 0xAAAAAAAA);
 173     OUT_CS_REG(R300_VAP_OUTPUT_VTX_FMT_0, 0x00000003);
 174     OUT_CS_REG(R300_VAP_OUTPUT_VTX_FMT_1, 0x00000000);
 175     OUT_CS_REG(R300_TX_ENABLE, 0x0);
 176     /* XXX viewport setup */
 177     OUT_CS_REG_SEQ(R300_SE_VPORT_XSCALE, 6);
 178     OUT_CS_32F(1.0);
 179     OUT_CS_32F((float)x);
 180     OUT_CS_32F(1.0);
 181     OUT_CS_32F((float)y);
 182     OUT_CS_32F(1.0);
 183     OUT_CS_32F(0.0);
 184
 185     if (caps->has_tcl) {
 186         OUT_CS_REG(R300_VAP_CLIP_CNTL, R300_CLIP_DISABLE |
 187             R300_PS_UCP_MODE_CLIP_AS_TRIFAN);
 188     }
 189
 190     /* XXX */
 191     OUT_CS_REG(R300_SC_CLIP_RULE, 0xaaaa);
 192     END_CS;
 193
 194     BEGIN_CS(7 + (caps->has_tcl ? 21 : 2));
 195     OUT_CS_REG_SEQ(R300_US_OUT_FMT_0, 4);
 196     OUT_CS(R300_C0_SEL_B | R300_C1_SEL_G | R300_C2_SEL_R | R300_C3_SEL_A);
 197     OUT_CS(R300_US_OUT_FMT_UNUSED);
 198     OUT_CS(R300_US_OUT_FMT_UNUSED);
 199     OUT_CS(R300_US_OUT_FMT_UNUSED);
 200     OUT_CS_REG(R300_US_W_FMT, R300_W_FMT_W0);
 201     /* XXX these magic numbers should be explained when
 202      * this becomes a cached state object */
 203     if (caps->has_tcl) {
 204         OUT_CS_REG(R300_VAP_CNTL, 0xA |
 205             (0x5 << R300_PVS_NUM_CNTLRS_SHIFT) |
 206             (0xB << R300_VF_MAX_VTX_NUM_SHIFT) |
 207             (caps->num_vert_fpus << R300_PVS_NUM_FPUS_SHIFT));
 208         OUT_CS_REG(R300_VAP_PVS_CODE_CNTL_0, 0x00100000);
 209         OUT_CS_REG(R300_VAP_PVS_CONST_CNTL, 0x00000000);
 210         OUT_CS_REG(R300_VAP_PVS_CODE_CNTL_1, 0x00000001);
 211         /* XXX translate these back into normal instructions */
 212         OUT_CS_REG(R300_VAP_PVS_STATE_FLUSH_REG, 0x1);
 213         OUT_CS_REG(R300_VAP_PVS_VECTOR_INDX_REG, 0x0);
 214         OUT_CS_ONE_REG(R300_VAP_PVS_UPLOAD_DATA, 8);
 215         OUT_CS(0x00F00203);
 216         OUT_CS(0x00D10001);
 217         OUT_CS(0x01248001);
 218         OUT_CS(0x00000000);
 219         OUT_CS(0x00F02203);
 220         OUT_CS(0x00D10021);
 221         OUT_CS(0x01248021);
 222         OUT_CS(0x00000000);
 223     } else {
 224         OUT_CS_REG(R300_VAP_CNTL, 0xA |
 225             (0x5 << R300_PVS_NUM_CNTLRS_SHIFT) |
 226             (0x5 << R300_VF_MAX_VTX_NUM_SHIFT) |
 227             (caps->num_vert_fpus << R300_PVS_NUM_FPUS_SHIFT));
 228     }
 229     END_CS;
 230
 231     /* Pixel scissors */
 232     OUT_CS_REG_SEQ(R300_SC_SCISSORS_TL, 2);
 233     OUT_CS((x << R300_SCISSORS_X_SHIFT) | (y << R300_SCISSORS_Y_SHIFT));
 234     OUT_CS((w << R300_SCISSORS_X_SHIFT) | (h << R300_SCISSORS_Y_SHIFT));
 235
 236     /* The size of the point we're about to draw, in sixths of pixels */
 237     OUT_CS_REG(R300_GA_POINT_SIZE,
 238         ((h * 6) & R300_POINTSIZE_Y_MASK) |
 239         ((w * 6) << R300_POINTSIZE_X_SHIFT));
 240
 241     BEGIN_CS(24);
 242     /* Flush colorbuffer and blend caches. */
 243     OUT_CS_REG(R300_RB3D_DSTCACHE_CTLSTAT,
 244         R300_RB3D_DSTCACHE_CTLSTAT_DC_FLUSH_FLUSH_DIRTY_3D |
 245         R300_RB3D_DSTCACHE_CTLSTAT_DC_FINISH_SIGNAL);
 246     OUT_CS_REG(R300_ZB_ZCACHE_CTLSTAT,
 247         R300_ZB_ZCACHE_CTLSTAT_ZC_FLUSH_FLUSH_AND_FREE |
 248         R300_ZB_ZCACHE_CTLSTAT_ZC_FREE_FREE);
 249
 250     OUT_CS_REG_SEQ(R300_RB3D_COLOROFFSET0, 1);
 251     OUT_CS_RELOC(tex->buffer, 0, 0, RADEON_GEM_DOMAIN_VRAM, 0);
 252     OUT_CS_REG(R300_RB3D_COLORPITCH0, pixpitch |
 253         r300_translate_colorformat(tex->tex.format));
 254     OUT_CS_REG(RB3D_COLOR_CHANNEL_MASK, 0x0000000F);
 255     /* XXX Packet3 */
 256     OUT_CS(CP_PACKET3(R200_3D_DRAW_IMMD_2, 8));
 257     OUT_CS(R300_PRIM_TYPE_POINT | R300_PRIM_WALK_RING |
 258     (1 << R300_PRIM_NUM_VERTICES_SHIFT));
 259     OUT_CS_32F(w / 2.0);
 260     OUT_CS_32F(h / 2.0);
 261     /* XXX this should be the depth value to clear to */
 262     OUT_CS_32F(1.0);
 263     OUT_CS_32F(1.0);
 264     OUT_CS_32F(r);
 265     OUT_CS_32F(g);
 266     OUT_CS_32F(b);
 267     OUT_CS_32F(1.0);
 268
 269     /* XXX figure out why this is 0xA and not 0x2 */
 270     OUT_CS_REG(R300_RB3D_DSTCACHE_CTLSTAT, 0xA);
 271     /* XXX OUT_CS_REG(R300_ZB_ZCACHE_CTLSTAT,
 272         R300_ZB_ZCACHE_CTLSTAT_ZC_FLUSH_FLUSH_AND_FREE |
 273         R300_ZB_ZCACHE_CTLSTAT_ZC_FREE_FREE); */
 274
 275     END_CS;
 276
 277     r300->dirty_hw++;
 278 }
 279
 280 static void r300_surface_copy(struct pipe_context* pipe,
 281                               boolean do_flip,
 282                               struct pipe_surface* dest,
 283                               unsigned destx, unsigned desty,
 284                               struct pipe_surface* src,
 285                               unsigned srcx, unsigned srcy,
 286                               unsigned w, unsigned h)
 287 {
 288     struct r300_context* r300 = r300_context(pipe);
 289     CS_LOCALS(r300);
 290     struct r300_texture* srctex = (struct r300_texture*)src->texture;
 291     struct r300_texture* desttex = (struct r300_texture*)dest->texture;
 292
 293     unsigned pixpitch = srctex->stride / srctex->tex.block.size;
 294     debug_printf("r300: Copying surface %p at (%d,%d) to %p at (%d, %d),"
 295         " dimensions %dx%d (pixel pitch %d)\n",
 296         src, srcx, srcy, dest, destx, desty, w, h, pixpitch);
 297
 298     if (TRUE) {
 299         debug_printf("r300: Falling back on surface_copy\n");
 300         return util_surface_copy(pipe, do_flip, dest, destx, desty, src,
 301                 srcx, srcy, w, h);
 302     }
 303 #if 0
 304     BEGIN_CS();
 305     OUT_CS_REG(RADEON_DEFAULT_SC_BOTTOM_RIGHT,(RADEON_DEFAULT_SC_RIGHT_MAX |
 306                 RADEON_DEFAULT_SC_BOTTOM_MAX));
 307     OUT_ACCEL_REG(RADEON_DP_GUI_MASTER_CNTL, (RADEON_GMC_DST_PITCH_OFFSET_CNTL |
 308                                           RADEON_GMC_SRC_PITCH_OFFSET_CNTL |
 309                                           RADEON_GMC_BRUSH_NONE |
 310                                           (datatype << 8) |
 311                                           RADEON_GMC_SRC_DATATYPE_COLOR |
 312                                           RADEON_ROP[rop].rop |
 313                                           RADEON_DP_SRC_SOURCE_MEMORY |
 314                                           RADEON_GMC_CLR_CMP_CNTL_DIS));
 315     OUT_CS_REG(RADEON_DP_BRUSH_FRGD_CLR, 0xffffffff);
 316     OUT_CS_REG(RADEON_DP_BRUSH_BKGD_CLR, 0x0);
 317     OUT_CS_REG(RADEON_DP_SRC_FRGD_CLR, 0xffffffff);
 318     OUT_CS_REG(RADEON_DP_SRC_BKGD_CLR, 0x0);
 319     OUT_ACCEL_REG(RADEON_DP_WRITE_MASK, planemask);
 320     OUT_ACCEL_REG(RADEON_DP_CNTL, ((info->accel_state->xdir >= 0 ? RADEON_DST_X_LEFT_TO_RIGHT : 0) |
 321                                (info->accel_state->ydir >= 0 ? RADEON_DST_Y_TOP_TO_BOTTOM : 0));
 322 );
 323
 324     OUT_CS_REG_SEQ(RADEON_DST_PITCH_OFFSET, 1);
 325     OUT_CS_RELOC(desttex->buffer, 0, 0, RADEON_GEM_DOMAIN_VRAM, 0);
 326
 327     OUT_CS_REG_SEQ(RADEON_SRC_PITCH_OFFSET, 1);
 328     OUT_CS_RELOC(srctex->buffer, 0,
 329             RADEON_GEM_DOMAIN_GTT | RADEON_GEM_DOMAIN_VRAM, 0, 0);
 330
 331     OUT_CS_REG(RADEON_SRC_Y_X, (srcy << 16) | srcx);
 332     OUT_CS_REG(RADEON_DST_Y_X, (desty << 16) | destx);
 333     OUT_CS_REG(RADEON_DST_HEIGHT_WIDTH, (h << 16) | w);
 334     OUT_CS_REG(RADEON_DSTCACHE_CTLSTAT, RADEON_RB2D_DC_FLUSH_ALL);
 335     OUT_CS_REG(RADEON_WAIT_UNTIL,
 336                   RADEON_WAIT_2D_IDLECLEAN | RADEON_WAIT_DMA_GUI_IDLE);
 337     END_CS;
 338 #endif
 339 }
 340
 341 void r300_init_surface_functions(struct r300_context* r300)
 342 {
 343     r300->context.surface_fill = r300_surface_fill;
 344     r300->context.surface_copy = r300_surface_copy;
 345 }