2 * Copyright 2008 Corbin Simpson <MostAwesomeDude@gmail.com>
3 * Joakim Sindholt <opensource@zhasha.com>
5 * Permission is hereby granted, free of charge, to any person obtaining a
6 * copy of this software and associated documentation files (the "Software"),
7 * to deal in the Software without restriction, including without limitation
8 * on the rights to use, copy, modify, merge, publish, distribute, sub
9 * license, and/or sell copies of the Software, and to permit persons to whom
10 * the Software is furnished to do so, subject to the following conditions:
12 * The above copyright notice and this permission notice (including the next
13 * paragraph) shall be included in all copies or substantial portions of the
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
19 * THE AUTHOR(S) AND/OR THEIR SUPPLIERS BE LIABLE FOR ANY CLAIM,
20 * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
21 * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
22 * USE OR OTHER DEALINGS IN THE SOFTWARE. */
24 #include "r300_surface.h"
26 /* Provides pipe_context's "surface_fill". Commonly used for clearing
28 static void r300_surface_fill(struct pipe_context
* pipe
,
29 struct pipe_surface
* dest
,
30 unsigned x
, unsigned y
,
31 unsigned w
, unsigned h
,
34 struct r300_context
* r300
= r300_context(pipe
);
36 struct r300_capabilities
* caps
= r300_screen(pipe
->screen
)->caps
;
37 struct r300_texture
* tex
= (struct r300_texture
*)dest
->texture
;
41 unsigned pixpitch
= tex
->stride
/ tex
->tex
.block
.size
;
42 r
= (float)((color
>> 16) & 0xff) / 255.0f
;
43 g
= (float)((color
>> 8) & 0xff) / 255.0f
;
44 b
= (float)((color
>> 0) & 0xff) / 255.0f
;
45 debug_printf("r300: Filling surface %p at (%d,%d),"
46 " dimensions %dx%d (pixel pitch %d), color 0x%x\n",
47 dest
, x
, y
, w
, h
, pixpitch
, color
);
50 if (tex
->tex
.format
!= PIPE_FORMAT_A8R8G8B8_UNORM
) {
51 debug_printf("r300: Falling back on surface clear...");
52 util_surface_fill(pipe
, dest
, x
, y
, w
, h
, color
);
56 r300_emit_invariant_state(r300
);
58 r300_emit_blend_state(r300
, &blend_clear_state
);
59 r300_emit_blend_color_state(r300
, &blend_color_clear_state
);
60 r300_emit_dsa_state(r300
, &dsa_clear_state
);
61 r300_emit_rs_state(r300
, &rs_clear_state
);
63 /* Fragment shader setup */
65 r500_emit_fragment_shader(r300
, &r500_passthrough_fragment_shader
);
66 r300_emit_rs_block_state(r300
, &r500_rs_block_clear_state
);
68 r300_emit_fragment_shader(r300
, &r300_passthrough_fragment_shader
);
69 r300_emit_rs_block_state(r300
, &r300_rs_block_clear_state
);
72 BEGIN_CS(97 + (caps
->has_tcl
? 9 : 0));
74 OUT_CS_REG(R300_VAP_PVS_STATE_FLUSH_REG
, 0x0);
76 OUT_CS_REG(R300_SE_VTE_CNTL
, R300_VPORT_X_SCALE_ENA
|
77 R300_VPORT_X_OFFSET_ENA
| R300_VPORT_Y_SCALE_ENA
|
78 R300_VPORT_Y_OFFSET_ENA
| R300_VPORT_Z_SCALE_ENA
|
79 R300_VPORT_Z_OFFSET_ENA
| R300_VTX_W0_FMT
);
80 /* Max and min vertex index clamp. */
81 OUT_CS_REG(R300_VAP_VF_MAX_VTX_INDX
, 0xFFFFFF);
82 OUT_CS_REG(R300_VAP_VF_MIN_VTX_INDX
, 0x0);
85 OUT_CS_REG(R300_VAP_CNTL_STATUS
, R300_VC_NO_SWAP
);
86 OUT_CS_REG(R300_VAP_CLIP_CNTL
, R300_CLIP_DISABLE
|
87 R300_PS_UCP_MODE_CLIP_AS_TRIFAN
);
88 OUT_CS_REG_SEQ(R300_VAP_GB_VERT_CLIP_ADJ
, 4);
94 OUT_CS_REG(R300_VAP_CNTL_STATUS
, R300_VC_NO_SWAP
|
97 /* XXX magic number not in r300_reg */
98 OUT_CS_REG(R300_VAP_PSC_SGN_NORM_CNTL
, 0xAAAAAAAA);
99 /* XXX point tex stuffing */
100 OUT_CS_REG_SEQ(R300_GA_POINT_S0
, 1);
102 OUT_CS_REG_SEQ(R300_GA_POINT_S1
, 1);
104 OUT_CS_REG(R300_GA_TRIANGLE_STIPPLE
, 0x5 |
105 (0x5 << R300_GA_TRIANGLE_STIPPLE_Y_SHIFT_SHIFT
));
106 /* XXX this big chunk should be refactored into rs_state */
107 OUT_CS_REG(R300_GA_LINE_S0
, 0x00000000);
108 OUT_CS_REG(R300_GA_LINE_S1
, 0x3F800000);
109 OUT_CS_REG(R300_GA_SOLID_RG
, 0x00000000);
110 OUT_CS_REG(R300_GA_SOLID_BA
, 0x00000000);
111 OUT_CS_REG(R300_GA_POLY_MODE
, 0x00000000);
112 OUT_CS_REG(R300_GA_ROUND_MODE
, 0x00000001);
113 OUT_CS_REG(R300_GA_OFFSET
, 0x00000000);
114 OUT_CS_REG(R300_GA_FOG_SCALE
, 0x3DBF1412);
115 OUT_CS_REG(R300_GA_FOG_OFFSET
, 0x00000000);
116 OUT_CS_REG(R300_SU_TEX_WRAP
, 0x00000000);
117 OUT_CS_REG(R300_SU_DEPTH_SCALE
, 0x4B7FFFFF);
118 OUT_CS_REG(R300_SU_DEPTH_OFFSET
, 0x00000000);
119 OUT_CS_REG(R300_SC_HYPERZ
, 0x0000001C);
120 OUT_CS_REG(R300_SC_EDGERULE
, 0x2DA49525);
121 OUT_CS_REG(R300_RB3D_CCTL
, 0x00000000);
122 OUT_CS_REG(RB3D_COLOR_CHANNEL_MASK
, 0x0000000F);
123 OUT_CS_REG(R300_RB3D_AARESOLVE_CTL
, 0x00000000);
124 OUT_CS_REG(R500_RB3D_DISCARD_SRC_PIXEL_LTE_THRESHOLD
, 0x00000000);
125 OUT_CS_REG(R500_RB3D_DISCARD_SRC_PIXEL_GTE_THRESHOLD
, 0xFFFFFFFF);
126 OUT_CS_REG(R300_ZB_FORMAT
, 0x00000002);
127 OUT_CS_REG(R300_ZB_ZCACHE_CTLSTAT
, 0x00000003);
128 OUT_CS_REG(R300_ZB_BW_CNTL
, 0x00000000);
129 OUT_CS_REG(R300_ZB_DEPTHCLEARVALUE
, 0x00000000);
130 OUT_CS_REG(R300_ZB_HIZ_OFFSET
, 0x00000000);
131 OUT_CS_REG(R300_ZB_HIZ_PITCH
, 0x00000000);
133 OUT_CS_REG(R300_VAP_PROG_STREAM_CNTL_0
,
134 (R300_DATA_TYPE_FLOAT_4
<< R300_DATA_TYPE_0_SHIFT
) |
135 ((R300_LAST_VEC
| (1 << R300_DST_VEC_LOC_SHIFT
) |
136 R300_DATA_TYPE_FLOAT_4
) << R300_DATA_TYPE_1_SHIFT
));
138 OUT_CS_REG(R300_VAP_PROG_STREAM_CNTL_0
,
139 (R300_DATA_TYPE_FLOAT_4
<< R300_DATA_TYPE_0_SHIFT
) |
140 ((R300_LAST_VEC
| (2 << R300_DST_VEC_LOC_SHIFT
) |
141 R300_DATA_TYPE_FLOAT_4
) << R300_DATA_TYPE_1_SHIFT
));
143 OUT_CS_REG(R300_VAP_PROG_STREAM_CNTL_EXT_0
,
144 (R300_VAP_SWIZZLE_XYZW
<< R300_SWIZZLE0_SHIFT
) |
145 (R300_VAP_SWIZZLE_XYZW
<< R300_SWIZZLE1_SHIFT
));
146 OUT_CS_REG(R300_VAP_VTX_STATE_CNTL
, 0x1);
147 OUT_CS_REG(R300_VAP_VSM_VTX_ASSM
, 0x405);
148 OUT_CS_REG(R300_SE_VTE_CNTL
, 0x0000043F);
150 OUT_CS_REG(R300_VAP_VTX_SIZE
, 0x8);
151 OUT_CS_REG(R300_VAP_PSC_SGN_NORM_CNTL
, 0xAAAAAAAA);
152 OUT_CS_REG(R300_VAP_OUTPUT_VTX_FMT_0
, 0x00000003);
153 OUT_CS_REG(R300_VAP_OUTPUT_VTX_FMT_1
, 0x00000000);
154 OUT_CS_REG(R300_TX_ENABLE
, 0x0);
155 /* XXX viewport setup */
156 OUT_CS_REG_SEQ(R300_SE_VPORT_XSCALE
, 6);
158 OUT_CS_32F((float)x
);
160 OUT_CS_32F((float)y
);
165 OUT_CS_REG(R300_SC_CLIP_RULE
, 0xaaaa);
168 BEGIN_CS(7 + (caps
->has_tcl
? 21 : 2));
169 OUT_CS_REG_SEQ(R300_US_OUT_FMT_0
, 4);
170 OUT_CS(R300_C0_SEL_B
| R300_C1_SEL_G
| R300_C2_SEL_R
| R300_C3_SEL_A
);
171 OUT_CS(R300_US_OUT_FMT_UNUSED
);
172 OUT_CS(R300_US_OUT_FMT_UNUSED
);
173 OUT_CS(R300_US_OUT_FMT_UNUSED
);
174 OUT_CS_REG(R300_US_W_FMT
, R300_W_FMT_W0
);
175 /* XXX these magic numbers should be explained when
176 * this becomes a cached state object */
178 OUT_CS_REG(R300_VAP_CNTL
, 0xA |
179 (0x5 << R300_PVS_NUM_CNTLRS_SHIFT
) |
180 (0xB << R300_VF_MAX_VTX_NUM_SHIFT
) |
181 (caps
->num_vert_fpus
<< R300_PVS_NUM_FPUS_SHIFT
));
182 OUT_CS_REG(R300_VAP_PVS_CODE_CNTL_0
, 0x00100000);
183 OUT_CS_REG(R300_VAP_PVS_CONST_CNTL
, 0x00000000);
184 OUT_CS_REG(R300_VAP_PVS_CODE_CNTL_1
, 0x00000001);
185 /* XXX translate these back into normal instructions */
186 OUT_CS_REG(R300_VAP_PVS_STATE_FLUSH_REG
, 0x1);
187 OUT_CS_REG(R300_VAP_PVS_VECTOR_INDX_REG
, 0x0);
188 OUT_CS_ONE_REG(R300_VAP_PVS_UPLOAD_DATA
, 8);
198 OUT_CS_REG(R300_VAP_CNTL
, 0xA |
199 (0x5 << R300_PVS_NUM_CNTLRS_SHIFT
) |
200 (0x5 << R300_VF_MAX_VTX_NUM_SHIFT
) |
201 (caps
->num_vert_fpus
<< R300_PVS_NUM_FPUS_SHIFT
));
208 OUT_CS_REG_SEQ(R300_SC_SCISSORS_TL
, 2);
209 OUT_CS((x
<< R300_SCISSORS_X_SHIFT
) | (y
<< R300_SCISSORS_Y_SHIFT
));
210 OUT_CS((w
<< R300_SCISSORS_X_SHIFT
) | (h
<< R300_SCISSORS_Y_SHIFT
));
212 /* The size of the point we're about to draw, in sixths of pixels */
213 OUT_CS_REG(R300_GA_POINT_SIZE
,
214 ((h
* 6) & R300_POINTSIZE_Y_MASK
) |
215 ((w
* 6) << R300_POINTSIZE_X_SHIFT
));
217 /* Flush colorbuffer and blend caches. */
218 OUT_CS_REG(R300_RB3D_DSTCACHE_CTLSTAT
,
219 R300_RB3D_DSTCACHE_CTLSTAT_DC_FLUSH_FLUSH_DIRTY_3D
|
220 R300_RB3D_DSTCACHE_CTLSTAT_DC_FINISH_SIGNAL
);
221 OUT_CS_REG(R300_ZB_ZCACHE_CTLSTAT
,
222 R300_ZB_ZCACHE_CTLSTAT_ZC_FLUSH_FLUSH_AND_FREE
|
223 R300_ZB_ZCACHE_CTLSTAT_ZC_FREE_FREE
);
225 OUT_CS_REG_SEQ(R300_RB3D_COLOROFFSET0
, 1);
226 OUT_CS_RELOC(tex
->buffer
, 0, 0, RADEON_GEM_DOMAIN_VRAM
, 0);
227 OUT_CS_REG(R300_RB3D_COLORPITCH0
, pixpitch
|
228 r300_translate_colorformat(tex
->tex
.format
));
229 OUT_CS_REG(RB3D_COLOR_CHANNEL_MASK
, 0x0000000F);
231 OUT_CS(CP_PACKET3(R200_3D_DRAW_IMMD_2
, 8));
232 OUT_CS(R300_PRIM_TYPE_POINT
| R300_PRIM_WALK_RING
|
233 (1 << R300_PRIM_NUM_VERTICES_SHIFT
));
236 /* XXX this should be the depth value to clear to */
244 /* XXX figure out why this is 0xA and not 0x2 */
245 OUT_CS_REG(R300_RB3D_DSTCACHE_CTLSTAT
, 0xA);
246 /* XXX OUT_CS_REG(R300_ZB_ZCACHE_CTLSTAT,
247 R300_ZB_ZCACHE_CTLSTAT_ZC_FLUSH_FLUSH_AND_FREE |
248 R300_ZB_ZCACHE_CTLSTAT_ZC_FREE_FREE); */
255 static void r300_surface_copy(struct pipe_context
* pipe
,
256 struct pipe_surface
* dest
,
257 unsigned destx
, unsigned desty
,
258 struct pipe_surface
* src
,
259 unsigned srcx
, unsigned srcy
,
260 unsigned w
, unsigned h
)
262 struct r300_context
* r300
= r300_context(pipe
);
264 struct r300_texture
* srctex
= (struct r300_texture
*)src
->texture
;
265 struct r300_texture
* desttex
= (struct r300_texture
*)dest
->texture
;
267 unsigned pixpitch
= srctex
->stride
/ srctex
->tex
.block
.size
;
268 debug_printf("r300: Copying surface %p at (%d,%d) to %p at (%d, %d),"
269 " dimensions %dx%d (pixel pitch %d)\n",
270 src
, srcx
, srcy
, dest
, destx
, desty
, w
, h
, pixpitch
);
273 debug_printf("r300: Falling back on surface_copy\n");
274 return util_surface_copy(pipe
, FALSE
, dest
, destx
, desty
, src
,
279 OUT_CS_REG(RADEON_DEFAULT_SC_BOTTOM_RIGHT
,(RADEON_DEFAULT_SC_RIGHT_MAX
|
280 RADEON_DEFAULT_SC_BOTTOM_MAX
));
281 OUT_ACCEL_REG(RADEON_DP_GUI_MASTER_CNTL
, (RADEON_GMC_DST_PITCH_OFFSET_CNTL
|
282 RADEON_GMC_SRC_PITCH_OFFSET_CNTL
|
283 RADEON_GMC_BRUSH_NONE
|
285 RADEON_GMC_SRC_DATATYPE_COLOR
|
286 RADEON_ROP
[rop
].rop
|
287 RADEON_DP_SRC_SOURCE_MEMORY
|
288 RADEON_GMC_CLR_CMP_CNTL_DIS
));
289 OUT_CS_REG(RADEON_DP_BRUSH_FRGD_CLR
, 0xffffffff);
290 OUT_CS_REG(RADEON_DP_BRUSH_BKGD_CLR
, 0x0);
291 OUT_CS_REG(RADEON_DP_SRC_FRGD_CLR
, 0xffffffff);
292 OUT_CS_REG(RADEON_DP_SRC_BKGD_CLR
, 0x0);
293 OUT_ACCEL_REG(RADEON_DP_WRITE_MASK
, planemask
);
294 OUT_ACCEL_REG(RADEON_DP_CNTL
, ((info
->accel_state
->xdir
>= 0 ? RADEON_DST_X_LEFT_TO_RIGHT
: 0) |
295 (info
->accel_state
->ydir
>= 0 ? RADEON_DST_Y_TOP_TO_BOTTOM
: 0));
298 OUT_CS_REG_SEQ(RADEON_DST_PITCH_OFFSET
, 1);
299 OUT_CS_RELOC(desttex
->buffer
, 0, 0, RADEON_GEM_DOMAIN_VRAM
, 0);
301 OUT_CS_REG_SEQ(RADEON_SRC_PITCH_OFFSET
, 1);
302 OUT_CS_RELOC(srctex
->buffer
, 0,
303 RADEON_GEM_DOMAIN_GTT
| RADEON_GEM_DOMAIN_VRAM
, 0, 0);
305 OUT_CS_REG(RADEON_SRC_Y_X
, (srcy
<< 16) | srcx
);
306 OUT_CS_REG(RADEON_DST_Y_X
, (desty
<< 16) | destx
);
307 OUT_CS_REG(RADEON_DST_HEIGHT_WIDTH
, (h
<< 16) | w
);
308 OUT_CS_REG(RADEON_DSTCACHE_CTLSTAT
, RADEON_RB2D_DC_FLUSH_ALL
);
309 OUT_CS_REG(RADEON_WAIT_UNTIL
,
310 RADEON_WAIT_2D_IDLECLEAN
| RADEON_WAIT_DMA_GUI_IDLE
);
315 void r300_init_surface_functions(struct r300_context
* r300
)
317 r300
->context
.surface_fill
= r300_surface_fill
;
318 r300
->context
.surface_copy
= r300_surface_copy
;