src/gallium/drivers/r300/r300_surface.c

   1 /*
   2  * Copyright 2008 Corbin Simpson <MostAwesomeDude@gmail.com>
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * on the rights to use, copy, modify, merge, publish, distribute, sub
   8  * license, and/or sell copies of the Software, and to permit persons to whom
   9  * the Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice (including the next
  12  * paragraph) shall be included in all copies or substantial portions of the
  13  * Software.
  14  *
  15  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  16  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  17  * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
  18  * THE AUTHOR(S) AND/OR THEIR SUPPLIERS BE LIABLE FOR ANY CLAIM,
  19  * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
  20  * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
  21  * USE OR OTHER DEALINGS IN THE SOFTWARE. */
  22
  23 #include "r300_surface.h"
  24
  25 /* Provides pipe_context's "surface_fill". Commonly used for clearing
  26  * buffers. */
  27 static void r300_surface_fill(struct pipe_context* pipe,
  28                               struct pipe_surface* dest,
  29                               unsigned x, unsigned y,
  30                               unsigned w, unsigned h,
  31                               unsigned color)
  32 {
  33     struct r300_context* r300 = r300_context(pipe);
  34     CS_LOCALS(r300);
  35     struct r300_capabilities* caps = ((struct r300_screen*)pipe->screen)->caps;
  36     int i;
  37     float r, g, b, a;
  38     r = (float)((color >> 16) & 0xff) / 255.0f;
  39     g = (float)((color >>  8) & 0xff) / 255.0f;
  40     b = (float)((color >>  0) & 0xff) / 255.0f;
  41     debug_printf("r300: Filling surface %p at (%d,%d),"
  42         " dimensions %dx%d, color 0x%x\n",
  43         dest, x, y, w, h, color);
  44
  45 BEGIN_CS((caps->is_r500) ? 367 : 276);
  46 R300_PACIFY;
  47 OUT_CS_REG(R300_TX_INVALTAGS, 0x0);
  48 R300_PACIFY;
  49 /* Viewport setup */
  50 OUT_CS_REG(R300_SE_VPORT_XSCALE, 0x43000000);
  51 OUT_CS_REG(R300_SE_VPORT_XOFFSET, 0x43002000);
  52 OUT_CS_REG(R300_SE_VPORT_YSCALE, 0xC3000000);
  53 OUT_CS_REG(R300_SE_VPORT_YOFFSET, 0x43002000);
  54 OUT_CS_REG(R300_SE_VPORT_ZSCALE, 0x3F000000);
  55 OUT_CS_REG(R300_SE_VPORT_ZOFFSET, 0x3F000000);
  56 /* Flush PVS. */
  57 OUT_CS_REG(R300_VAP_PVS_STATE_FLUSH_REG, 0x0);
  58
  59 OUT_CS_REG(R300_SE_VTE_CNTL, R300_VPORT_X_SCALE_ENA |
  60     R300_VPORT_X_OFFSET_ENA | R300_VPORT_Y_SCALE_ENA |
  61     R300_VPORT_Y_OFFSET_ENA | R300_VPORT_Z_SCALE_ENA |
  62     R300_VPORT_Z_OFFSET_ENA | R300_VTX_W0_FMT);
  63 /* Vertex size. */
  64 OUT_CS_REG(R300_VAP_VTX_SIZE, 0x8);
  65 /* Max and min vertex index clamp. */
  66 OUT_CS_REG(R300_VAP_VF_MAX_VTX_INDX, 0xFFFFFF);
  67 OUT_CS_REG(R300_VAP_VF_MIN_VTX_INDX, 0x0);
  68 /* XXX endian */
  69 OUT_CS_REG(R300_VAP_CNTL_STATUS, R300_VC_NO_SWAP);
  70 OUT_CS_REG(R300_VAP_PROG_STREAM_CNTL_0, 0x0);
  71 /* XXX magic number not in r300_reg */
  72 OUT_CS_REG(R300_VAP_PSC_SGN_NORM_CNTL, 0xAAAAAAAA);
  73 OUT_CS_REG(R300_VAP_CLIP_CNTL, 0x0);
  74 OUT_CS_REG(R300_VAP_GB_VERT_CLIP_ADJ, 4);
  75 OUT_CS_32F(1.0);
  76 OUT_CS_32F(1.0);
  77 OUT_CS_32F(1.0);
  78 OUT_CS_32F(1.0);
  79 /* XXX is this too long? */
  80 OUT_CS_REG(VAP_PVS_VTX_TIMEOUT_REG, 0xFFFF);
  81 OUT_CS_REG(R300_GB_ENABLE, R300_GB_POINT_STUFF_ENABLE |
  82     R300_GB_LINE_STUFF_ENABLE | R300_GB_TRIANGLE_STUFF_ENABLE);
  83 /* XXX more magic numbers */
  84 OUT_CS_REG(R300_GB_MSPOS0, 0x66666666);
  85 OUT_CS_REG(R300_GB_MSPOS1, 0x66666666);
  86 /* XXX why doesn't classic Mesa write the number of pipes, too? */
  87 OUT_CS_REG(R300_GB_TILE_CONFIG, R300_GB_TILE_ENABLE | R300_GB_TILE_SIZE_16);
  88 OUT_CS_REG(R300_GB_SELECT, R300_GB_FOG_SELECT_1_1_W);
  89 OUT_CS_REG(R300_GB_AA_CONFIG, 0x0);
  90 /* XXX point tex stuffing */
  91 OUT_CS_REG_SEQ(R300_GA_POINT_S0, 1);
  92 OUT_CS_32F(0.0);
  93 OUT_CS_REG_SEQ(R300_GA_POINT_S1, 1);
  94 OUT_CS_32F(1.0);
  95 OUT_CS_REG(R300_GA_TRIANGLE_STIPPLE, 0x5 |
  96     (0x5 << R300_GA_TRIANGLE_STIPPLE_Y_SHIFT_SHIFT));
  97 /* XXX should this be related to the actual point size? */
  98 OUT_CS_REG(R300_GA_POINT_MINMAX, 0x6 |
  99     (0x1800 << R300_GA_POINT_MINMAX_MAX_SHIFT));
 100 OUT_CS_REG(R300_GA_LINE_CNTL, 0x00030006);
 101 OUT_CS_REG(R300_GA_LINE_STIPPLE_CONFIG, 0x3BAAAAAB);
 102 OUT_CS_REG(R300_GA_LINE_STIPPLE_VALUE, 0x00000000);
 103 OUT_CS_REG(R300_GA_LINE_S0, 0x00000000);
 104 OUT_CS_REG(R300_GA_LINE_S1, 0x3F800000);
 105 OUT_CS_REG(R300_GA_ENHANCE, 0x00000002);
 106 OUT_CS_REG(R300_GA_COLOR_CONTROL, 0x0003AAAA);
 107 OUT_CS_REG(R300_GA_SOLID_RG, 0x00000000);
 108 OUT_CS_REG(R300_GA_SOLID_BA, 0x00000000);
 109 OUT_CS_REG(R300_GA_POLY_MODE, 0x00000000);
 110 OUT_CS_REG(R300_GA_ROUND_MODE, 0x00000001);
 111 OUT_CS_REG(R300_GA_OFFSET, 0x00000000);
 112 OUT_CS_REG(R300_GA_FOG_SCALE, 0x3DBF1412);
 113 OUT_CS_REG(R300_GA_FOG_OFFSET, 0x00000000);
 114 OUT_CS_REG(R300_SU_TEX_WRAP, 0x00000000);
 115 OUT_CS_REG(R300_SU_POLY_OFFSET_FRONT_SCALE, 0x00000000);
 116 OUT_CS_REG(R300_SU_POLY_OFFSET_FRONT_OFFSET, 0x00000000);
 117 OUT_CS_REG(R300_SU_POLY_OFFSET_BACK_SCALE, 0x00000000);
 118 OUT_CS_REG(R300_SU_POLY_OFFSET_BACK_OFFSET, 0x00000000);
 119 OUT_CS_REG(R300_SU_POLY_OFFSET_ENABLE, 0x00000000);
 120 OUT_CS_REG(R300_SU_CULL_MODE, 0x00000000);
 121 OUT_CS_REG(R300_SU_DEPTH_SCALE, 0x4B7FFFFF);
 122 OUT_CS_REG(R300_SU_DEPTH_OFFSET, 0x00000000);
 123 OUT_CS_REG(R300_SC_HYPERZ, 0x0000001C);
 124 OUT_CS_REG(R300_SC_EDGERULE, 0x2DA49525);
 125 OUT_CS_REG(R300_SC_SCREENDOOR, 0x00FFFFFF);
 126 OUT_CS_REG_SEQ(R300_US_OUT_FMT_0, 4);
 127 OUT_CS(R300_C0_SEL_B | R300_C1_SEL_G | R300_C2_SEL_R);
 128 OUT_CS(R300_C0_SEL_B | R300_C1_SEL_G | R300_C2_SEL_R | R300_US_OUT_FMT_UNUSED);
 129 OUT_CS(R300_C0_SEL_B | R300_C1_SEL_G | R300_C2_SEL_R | R300_US_OUT_FMT_UNUSED);
 130 OUT_CS(R300_C0_SEL_B | R300_C1_SEL_G | R300_C2_SEL_R | R300_US_OUT_FMT_UNUSED);
 131 OUT_CS_REG(R300_US_W_FMT, 0x00000001);
 132 OUT_CS_REG(R300_US_CONFIG, 0x00000000);
 133 OUT_CS_REG(R300_US_PIXSIZE, 0x00000000);
 134 OUT_CS_REG(R300_US_CODE_OFFSET, 0x00000000);
 135 OUT_CS_REG(R300_US_CODE_ADDR_0, 0x00000000);
 136 OUT_CS_REG(R300_US_CODE_ADDR_1, 0x00000000);
 137 OUT_CS_REG(R300_US_CODE_ADDR_2, 0x00000000);
 138 OUT_CS_REG(R300_US_CODE_ADDR_3, 0x00000000);
 139 OUT_CS_REG(R300_US_ALU_RGB_INST_0, 0x00000000);
 140 OUT_CS_REG(R300_US_ALU_RGB_ADDR_0, 0x00000000);
 141 OUT_CS_REG(R300_US_ALU_ALPHA_INST_0, 0x00000000);
 142 OUT_CS_REG(R300_US_ALU_ALPHA_ADDR_0, 0x00000000);
 143 OUT_CS_REG(R300_FG_FOG_BLEND, 0x00000002);
 144 OUT_CS_REG(R300_FG_FOG_COLOR_R, 0x00000000);
 145 OUT_CS_REG(R300_FG_FOG_COLOR_G, 0x00000000);
 146 OUT_CS_REG(R300_FG_FOG_COLOR_B, 0x00000000);
 147 OUT_CS_REG(R300_FG_DEPTH_SRC, 0x00000000);
 148 OUT_CS_REG(R300_FG_DEPTH_SRC, 0x00000000);
 149 OUT_CS_REG(R300_RB3D_CCTL, 0x00000000);
 150 OUT_CS_REG(RB3D_COLOR_CHANNEL_MASK, 0x0000000F);
 151
 152 r300_emit_blend_color_state(r300, &blend_color_clear_state);
 153
 154 OUT_CS_REG(R300_RB3D_BLEND_COLOR, 0x00000000);
 155 /* XXX: Oh the wonderful unknown */
 156 OUT_CS_REG_SEQ(0x4E54, 8);
 157 for (i = 0; i < 8; i++)
 158     OUT_CS(0x00000000);
 159 OUT_CS_REG(R300_RB3D_AARESOLVE_CTL, 0x00000000);
 160 OUT_CS_REG(R500_RB3D_DISCARD_SRC_PIXEL_LTE_THRESHOLD, 0x00000000);
 161 OUT_CS_REG(R500_RB3D_DISCARD_SRC_PIXEL_GTE_THRESHOLD, 0xFFFFFFFF);
 162 OUT_CS_REG(R300_ZB_CNTL, 0x00000010);
 163 OUT_CS_REG(R300_ZB_ZSTENCILCNTL, 0x00038038);
 164 OUT_CS_REG(R300_ZB_STENCILREFMASK, 0x00FFFF00);
 165 OUT_CS_REG(R300_ZB_FORMAT, 0x00000002);
 166 OUT_CS_REG(R300_ZB_ZCACHE_CTLSTAT, 0x00000003);
 167 OUT_CS_REG(R300_ZB_BW_CNTL, 0x00000000);
 168 OUT_CS_REG(R300_ZB_DEPTHCLEARVALUE, 0x00000000);
 169 OUT_CS_REG(0x4F30, 0x00000000);
 170 OUT_CS_REG(0x4F34, 0x00000000);
 171 OUT_CS_REG(R300_ZB_HIZ_OFFSET, 0x00000000);
 172 OUT_CS_REG(R300_ZB_HIZ_PITCH, 0x00000000);
 173 OUT_CS_REG(R300_SC_SCREENDOOR, 0x00000000);
 174 R300_PACIFY;
 175 OUT_CS_REG(R300_SC_SCREENDOOR, 0x00FFFFFF);
 176 OUT_CS_REG(R300_VAP_PROG_STREAM_CNTL_0, 0x21030003);
 177 OUT_CS_REG(R300_FG_FOG_BLEND, 0x00000000);
 178 OUT_CS_REG(R300_VAP_PROG_STREAM_CNTL_EXT_0, 0xF688F688);
 179 OUT_CS_REG(R300_VAP_VTX_STATE_CNTL, 0x1);
 180 OUT_CS_REG(R300_VAP_VSM_VTX_ASSM, 0x405);
 181 OUT_CS_REG(R300_SE_VTE_CNTL, 0x0000043F);
 182 OUT_CS_REG(R300_VAP_VTX_SIZE, 0x00000008);
 183 OUT_CS_REG(R300_VAP_PSC_SGN_NORM_CNTL, 0xAAAAAAAA);
 184 OUT_CS_REG(R300_VAP_OUTPUT_VTX_FMT_0, 0x00000003);
 185 OUT_CS_REG(R300_VAP_OUTPUT_VTX_FMT_1, 0x00000000);
 186 OUT_CS_REG(R300_TX_ENABLE, 0x0);
 187 OUT_CS_REG(R300_SE_VPORT_XSCALE, 0x3F800000);
 188 OUT_CS_REG(R300_SE_VPORT_XOFFSET, 0x00000000);
 189 OUT_CS_REG(R300_SE_VPORT_YSCALE, 0x3F800000);
 190 OUT_CS_REG(R300_SE_VPORT_YOFFSET, 0x00000000);
 191 OUT_CS_REG(R300_SE_VPORT_ZSCALE, 0x3F800000);
 192 OUT_CS_REG(R300_SE_VPORT_ZOFFSET, 0x00000000);
 193 OUT_CS_REG(R300_FG_ALPHA_FUNC, 0x00000000);
 194
 195 r300_emit_blend_state(r300, &blend_clear_state);
 196
 197 OUT_CS_REG(R300_VAP_CLIP_CNTL, 0x0001C000);
 198 OUT_CS_REG(R300_GA_POINT_SIZE, ((h * 6) & R300_POINTSIZE_Y_MASK) |
 199     ((w * 6) << R300_POINTSIZE_X_SHIFT));
 200
 201 /* XXX RS block and fp setup */
 202 if (caps->is_r500) {
 203     OUT_CS_REG_SEQ(R500_RS_IP_0, 16);
 204     for (i = 0; i < 16; i++) {
 205         /* I like the operator macros more than the shift macros... */
 206         OUT_CS((R500_RS_IP_PTR_K0 << R500_RS_IP_TEX_PTR_S_SHIFT) |
 207             (R500_RS_IP_PTR_K0 << R500_RS_IP_TEX_PTR_T_SHIFT) |
 208             (R500_RS_IP_PTR_K0 << R500_RS_IP_TEX_PTR_R_SHIFT) |
 209             (R500_RS_IP_PTR_K1 << R500_RS_IP_TEX_PTR_Q_SHIFT));
 210     }
 211     R300_PACIFY;
 212     OUT_CS_REG(R500_US_CONFIG, R500_ZERO_TIMES_ANYTHING_EQUALS_ZERO);
 213     OUT_CS_REG(R500_US_CODE_ADDR, R500_US_CODE_START_ADDR(0) |
 214         R500_US_CODE_END_ADDR(1));
 215     OUT_CS_REG(R500_US_CODE_RANGE, R500_US_CODE_RANGE_ADDR(0) |
 216         R500_US_CODE_RANGE_SIZE(1));
 217     OUT_CS_REG(R500_US_CODE_OFFSET, R500_US_CODE_OFFSET_ADDR(0));
 218     R300_PACIFY;
 219     OUT_CS_REG(R500_US_CMN_INST_0,
 220                R500_INST_TYPE_OUT |
 221                R500_INST_TEX_SEM_WAIT |
 222                R500_INST_LAST |
 223                R500_INST_RGB_OMASK_R |
 224                R500_INST_RGB_OMASK_G |
 225                R500_INST_RGB_OMASK_B |
 226                R500_INST_ALPHA_OMASK |
 227                R500_INST_RGB_CLAMP |
 228                R500_INST_ALPHA_CLAMP);
 229     OUT_CS_REG(R500_US_ALU_RGB_ADDR_0,
 230                R500_RGB_ADDR0(0) |
 231                R500_RGB_ADDR1(0) |
 232                R500_RGB_ADDR1_CONST |
 233                R500_RGB_ADDR2(0) |
 234                R500_RGB_ADDR2_CONST);
 235     OUT_CS_REG(R500_US_ALU_ALPHA_ADDR_0,
 236                R500_ALPHA_ADDR0(0) |
 237                R500_ALPHA_ADDR1(0) |
 238                R500_ALPHA_ADDR1_CONST |
 239                R500_ALPHA_ADDR2(0) |
 240                R500_ALPHA_ADDR2_CONST);
 241     OUT_CS_REG(R500_US_ALU_RGB_INST_0,
 242                R500_ALU_RGB_SEL_A_SRC0 |
 243                R500_ALU_RGB_R_SWIZ_A_R |
 244                R500_ALU_RGB_G_SWIZ_A_G |
 245                R500_ALU_RGB_B_SWIZ_A_B |
 246                R500_ALU_RGB_SEL_B_SRC0 |
 247                R500_ALU_RGB_R_SWIZ_B_R |
 248                R500_ALU_RGB_B_SWIZ_B_G |
 249                R500_ALU_RGB_G_SWIZ_B_B);
 250     OUT_CS_REG(R500_US_ALU_ALPHA_INST_0,
 251                R500_ALPHA_OP_CMP |
 252                R500_ALPHA_SWIZ_A_A |
 253                R500_ALPHA_SWIZ_B_A);
 254     OUT_CS_REG(R500_US_ALU_RGBA_INST_0,
 255                R500_ALU_RGBA_OP_CMP |
 256                R500_ALU_RGBA_R_SWIZ_0 |
 257                R500_ALU_RGBA_G_SWIZ_0 |
 258                R500_ALU_RGBA_B_SWIZ_0 |
 259                R500_ALU_RGBA_A_SWIZ_0);
 260 } else {
 261     OUT_CS_REG_SEQ(R300_RS_IP_0, 8);
 262     for (i = 0; i < 8; i++) {
 263         OUT_CS(R300_RS_SEL_T(1) | R300_RS_SEL_R(2) | R300_RS_SEL_Q(3));
 264     }
 265 }
 266 OUT_CS_REG(R300_RS_COUNT, (1 << R300_IC_COUNT_SHIFT) | R300_HIRES_EN);
 267 OUT_CS_REG(R300_RS_INST_COUNT, 0x0);
 268
 269 OUT_CS_REG(R300_RS_INST_0, 0x00004000);
 270 OUT_CS_REG(R300_US_CONFIG, 0x00000000);
 271 OUT_CS_REG(R300_US_PIXSIZE, 0x00000000);
 272 OUT_CS_REG(R300_US_CODE_OFFSET, 0x00000000);
 273 OUT_CS_REG(R300_US_CODE_ADDR_0, 0x00000000);
 274 OUT_CS_REG(R300_US_CODE_ADDR_1, 0x00000000);
 275 OUT_CS_REG(R300_US_CODE_ADDR_2, 0x00000000);
 276 OUT_CS_REG(R300_US_CODE_ADDR_3, 0x00400000);
 277 OUT_CS_REG(R300_US_ALU_RGB_INST_0, 0x00050A80);
 278 OUT_CS_REG(R300_US_ALU_RGB_ADDR_0, 0x1C000000);
 279 OUT_CS_REG(R300_US_ALU_ALPHA_INST_0, 0x00040889);
 280 OUT_CS_REG(R300_US_ALU_ALPHA_ADDR_0, 0x01000000);
 281 /* XXX these magic numbers should be explained when
 282  * this becomes a cached state object */
 283 OUT_CS_REG(R300_VAP_CNTL, 0xA | (0x5 << R300_PVS_NUM_CNTLRS_SHIFT) |
 284     (caps->num_vert_fpus << R300_PVS_NUM_FPUS_SHIFT));
 285 OUT_CS_REG(R300_VAP_PVS_CODE_CNTL_0, 0x00100000);
 286 OUT_CS_REG(R300_VAP_PVS_CONST_CNTL, 0x00000000);
 287 OUT_CS_REG(R300_VAP_PVS_CODE_CNTL_1, 0x00000001);
 288 OUT_CS_REG(R300_SC_SCREENDOOR, 0x00000000);
 289 R300_PACIFY;
 290 OUT_CS_REG(R300_SC_SCREENDOOR, 0x00FFFFFF);
 291 /* XXX translate these back into normal instructions */
 292 OUT_CS_REG(R300_VAP_PVS_STATE_FLUSH_REG, 0x1);
 293 OUT_CS_REG(R300_VAP_PVS_VECTOR_INDX_REG, 0x0);
 294 OUT_CS_REG(R300_VAP_PVS_UPLOAD_DATA, 0xF00203);
 295 OUT_CS_REG(R300_VAP_PVS_UPLOAD_DATA, 0xD10001);
 296 OUT_CS_REG(R300_VAP_PVS_UPLOAD_DATA, 0x1248001);
 297 OUT_CS_REG(R300_VAP_PVS_UPLOAD_DATA, 0x0);
 298 OUT_CS_REG(R300_VAP_PVS_UPLOAD_DATA, 0xF02203);
 299 OUT_CS_REG(R300_VAP_PVS_UPLOAD_DATA, 0xD10021);
 300 OUT_CS_REG(R300_VAP_PVS_UPLOAD_DATA, 0x1248021);
 301 OUT_CS_REG(R300_VAP_PVS_UPLOAD_DATA, 0x0);
 302
 303 r300_emit_dsa_state(r300, &dsa_clear_state);
 304
 305 R300_PACIFY;
 306 OUT_CS_REG_SEQ(R300_RB3D_COLOROFFSET0, 1);
 307 OUT_CS_RELOC(dest->buffer, 0, 0, RADEON_GEM_DOMAIN_VRAM, 0);
 308 //OUT_CS_REG(R300_RB3D_COLORPITCH0, 0x00C00100);
 309 OUT_CS_REG(RB3D_COLOR_CHANNEL_MASK, 0x0000000F);
 310 /* XXX Packet3 */
 311 OUT_CS(CP_PACKET3(R200_3D_DRAW_IMMD_2, 8));
 312 OUT_CS(R300_PRIM_TYPE_POINT | R300_PRIM_WALK_RING |
 313 (1 << R300_PRIM_NUM_VERTICES_SHIFT));
 314 OUT_CS_32F(w / 2.0);
 315 OUT_CS_32F(h / 2.0);
 316 /* XXX this should be the depth value to clear to */
 317 OUT_CS_32F(1.0);
 318 OUT_CS_32F(1.0);
 319 OUT_CS_32F(r);
 320 OUT_CS_32F(g);
 321 OUT_CS_32F(b);
 322 OUT_CS_32F(1.0);
 323
 324 /* XXX figure out why this is 0xA and not 0x2 */
 325 /* XXX OUT_CS_REG(R300_RB3D_DSTCACHE_CTLSTAT, 0xA);
 326 OUT_CS_REG(R300_ZB_ZCACHE_CTLSTAT,
 327     R300_ZB_ZCACHE_CTLSTAT_ZC_FLUSH_FLUSH_AND_FREE |
 328     R300_ZB_ZCACHE_CTLSTAT_ZC_FREE_FREE); */
 329 R300_PACIFY;
 330
 331 END_CS;
 332 FLUSH_CS;
 333
 334     r300->dirty_state = R300_NEW_KITCHEN_SINK;
 335 }
 336
 337 void r300_init_surface_functions(struct r300_context* r300)
 338 {
 339     r300->context.surface_fill = r300_surface_fill;
 340 }