2 * Copyright 2008 Corbin Simpson <MostAwesomeDude@gmail.com>
3 * Copyright 2010 Marek Olšák <maraeo@gmail.com>
5 * Permission is hereby granted, free of charge, to any person obtaining a
6 * copy of this software and associated documentation files (the "Software"),
7 * to deal in the Software without restriction, including without limitation
8 * on the rights to use, copy, modify, merge, publish, distribute, sub
9 * license, and/or sell copies of the Software, and to permit persons to whom
10 * the Software is furnished to do so, subject to the following conditions:
12 * The above copyright notice and this permission notice (including the next
13 * paragraph) shall be included in all copies or substantial portions of the
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
19 * THE AUTHOR(S) AND/OR THEIR SUPPLIERS BE LIABLE FOR ANY CLAIM,
20 * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
21 * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
22 * USE OR OTHER DEALINGS IN THE SOFTWARE. */
24 #include "r300_texture_desc.h"
25 #include "r300_context.h"
27 #include "util/format/u_format.h"
30 /* Returns the number of pixels that the texture should be aligned to
31 * in the given dimension. */
32 unsigned r300_get_pixel_alignment(enum pipe_format format
,
34 enum radeon_bo_layout microtile
,
35 enum radeon_bo_layout macrotile
,
36 enum r300_dim dim
, boolean is_rs690
)
38 static const unsigned table
[2][5][3][2] =
41 /* Macro: linear linear linear
42 Micro: linear tiled square-tiled */
43 {{ 32, 1}, { 8, 4}, { 0, 0}}, /* 8 bits per pixel */
44 {{ 16, 1}, { 8, 2}, { 4, 4}}, /* 16 bits per pixel */
45 {{ 8, 1}, { 4, 2}, { 0, 0}}, /* 32 bits per pixel */
46 {{ 4, 1}, { 2, 2}, { 0, 0}}, /* 64 bits per pixel */
47 {{ 2, 1}, { 0, 0}, { 0, 0}} /* 128 bits per pixel */
50 /* Macro: tiled tiled tiled
51 Micro: linear tiled square-tiled */
52 {{256, 8}, {64, 32}, { 0, 0}}, /* 8 bits per pixel */
53 {{128, 8}, {64, 16}, {32, 32}}, /* 16 bits per pixel */
54 {{ 64, 8}, {32, 16}, { 0, 0}}, /* 32 bits per pixel */
55 {{ 32, 8}, {16, 16}, { 0, 0}}, /* 64 bits per pixel */
56 {{ 16, 8}, { 0, 0}, { 0, 0}} /* 128 bits per pixel */
61 unsigned pixsize
= util_format_get_blocksize(format
);
63 assert(macrotile
<= RADEON_LAYOUT_TILED
);
64 assert(microtile
<= RADEON_LAYOUT_SQUARETILED
);
65 assert(pixsize
<= 16);
66 assert(dim
<= DIM_HEIGHT
);
68 tile
= table
[macrotile
][util_logbase2(pixsize
)][microtile
][dim
];
69 if (macrotile
== 0 && is_rs690
&& dim
== DIM_WIDTH
) {
72 h_tile
= table
[macrotile
][util_logbase2(pixsize
)][microtile
][DIM_HEIGHT
];
73 align
= 64 / (pixsize
* h_tile
);
82 /* Return true if macrotiling should be enabled on the miplevel. */
83 static boolean
r300_texture_macro_switch(struct r300_resource
*tex
,
88 unsigned tile
, texdim
;
90 if (tex
->b
.b
.nr_samples
> 1) {
94 tile
= r300_get_pixel_alignment(tex
->b
.b
.format
, tex
->b
.b
.nr_samples
,
95 tex
->tex
.microtile
, RADEON_LAYOUT_TILED
, dim
, 0);
96 if (dim
== DIM_WIDTH
) {
97 texdim
= u_minify(tex
->tex
.width0
, level
);
99 texdim
= u_minify(tex
->tex
.height0
, level
);
102 /* See TX_FILTER1_n.MACRO_SWITCH. */
104 return texdim
>= tile
;
106 return texdim
> tile
;
111 * Return the stride, in bytes, of the texture image of the given texture
112 * at the given level.
114 static unsigned r300_texture_get_stride(struct r300_screen
*screen
,
115 struct r300_resource
*tex
,
118 unsigned tile_width
, width
, stride
;
119 boolean is_rs690
= (screen
->caps
.family
== CHIP_RS600
||
120 screen
->caps
.family
== CHIP_RS690
||
121 screen
->caps
.family
== CHIP_RS740
);
123 if (tex
->tex
.stride_in_bytes_override
)
124 return tex
->tex
.stride_in_bytes_override
;
126 /* Check the level. */
127 if (level
> tex
->b
.b
.last_level
) {
128 SCREEN_DBG(screen
, DBG_TEX
, "%s: level (%u) > last_level (%u)\n",
129 __FUNCTION__
, level
, tex
->b
.b
.last_level
);
133 width
= u_minify(tex
->tex
.width0
, level
);
135 if (util_format_is_plain(tex
->b
.b
.format
)) {
136 tile_width
= r300_get_pixel_alignment(tex
->b
.b
.format
,
139 tex
->tex
.macrotile
[level
],
140 DIM_WIDTH
, is_rs690
);
141 width
= align(width
, tile_width
);
143 stride
= util_format_get_stride(tex
->b
.b
.format
, width
);
144 /* The alignment to 32 bytes is sort of implied by the layout... */
147 return align(util_format_get_stride(tex
->b
.b
.format
, width
), is_rs690
? 64 : 32);
151 static unsigned r300_texture_get_nblocksy(struct r300_resource
*tex
,
153 boolean
*out_aligned_for_cbzb
)
155 unsigned height
, tile_height
;
157 height
= u_minify(tex
->tex
.height0
, level
);
159 /* Mipmapped and 3D textures must have their height aligned to POT. */
160 if ((tex
->b
.b
.target
!= PIPE_TEXTURE_1D
&&
161 tex
->b
.b
.target
!= PIPE_TEXTURE_2D
&&
162 tex
->b
.b
.target
!= PIPE_TEXTURE_RECT
) ||
163 tex
->b
.b
.last_level
!= 0) {
164 height
= util_next_power_of_two(height
);
167 if (util_format_is_plain(tex
->b
.b
.format
)) {
168 tile_height
= r300_get_pixel_alignment(tex
->b
.b
.format
,
171 tex
->tex
.macrotile
[level
],
173 height
= align(height
, tile_height
);
175 /* See if the CBZB clear can be used on the buffer,
176 * taking the texture size into account. */
177 if (out_aligned_for_cbzb
) {
178 if (tex
->tex
.macrotile
[level
]) {
179 /* When clearing, the layer (width*height) is horizontally split
180 * into two, and the upper and lower halves are cleared by the CB
181 * and ZB units, respectively. Therefore, the number of macrotiles
182 * in the Y direction must be even. */
184 /* Align the height so that there is an even number of macrotiles.
185 * Do so for 3 or more macrotiles in the Y direction. */
186 if (level
== 0 && tex
->b
.b
.last_level
== 0 &&
187 (tex
->b
.b
.target
== PIPE_TEXTURE_1D
||
188 tex
->b
.b
.target
== PIPE_TEXTURE_2D
||
189 tex
->b
.b
.target
== PIPE_TEXTURE_RECT
) &&
190 height
>= tile_height
* 3) {
191 height
= align(height
, tile_height
* 2);
194 *out_aligned_for_cbzb
= height
% (tile_height
* 2) == 0;
196 *out_aligned_for_cbzb
= FALSE
;
201 return util_format_get_nblocksy(tex
->b
.b
.format
, height
);
204 /* Get a width in pixels from a stride in bytes. */
205 unsigned r300_stride_to_width(enum pipe_format format
,
206 unsigned stride_in_bytes
)
208 return (stride_in_bytes
/ util_format_get_blocksize(format
)) *
209 util_format_get_blockwidth(format
);
212 static void r300_setup_miptree(struct r300_screen
*screen
,
213 struct r300_resource
*tex
,
214 boolean align_for_cbzb
)
216 struct pipe_resource
*base
= &tex
->b
.b
;
217 unsigned stride
, size
, layer_size
, nblocksy
, i
;
218 boolean rv350_mode
= screen
->caps
.family
>= CHIP_R350
;
219 boolean aligned_for_cbzb
;
221 tex
->tex
.size_in_bytes
= 0;
223 SCREEN_DBG(screen
, DBG_TEXALLOC
,
224 "r300: Making miptree for texture, format %s\n",
225 util_format_short_name(base
->format
));
227 for (i
= 0; i
<= base
->last_level
; i
++) {
228 /* Let's see if this miplevel can be macrotiled. */
229 tex
->tex
.macrotile
[i
] =
230 (tex
->tex
.macrotile
[0] == RADEON_LAYOUT_TILED
&&
231 r300_texture_macro_switch(tex
, i
, rv350_mode
, DIM_WIDTH
) &&
232 r300_texture_macro_switch(tex
, i
, rv350_mode
, DIM_HEIGHT
)) ?
233 RADEON_LAYOUT_TILED
: RADEON_LAYOUT_LINEAR
;
235 stride
= r300_texture_get_stride(screen
, tex
, i
);
237 /* Compute the number of blocks in Y, see if the CBZB clear can be
238 * used on the texture. */
239 aligned_for_cbzb
= FALSE
;
240 if (align_for_cbzb
&& tex
->tex
.cbzb_allowed
[i
])
241 nblocksy
= r300_texture_get_nblocksy(tex
, i
, &aligned_for_cbzb
);
243 nblocksy
= r300_texture_get_nblocksy(tex
, i
, NULL
);
245 layer_size
= stride
* nblocksy
;
247 if (base
->nr_samples
> 1) {
248 layer_size
*= base
->nr_samples
;
251 if (base
->target
== PIPE_TEXTURE_CUBE
)
252 size
= layer_size
* 6;
254 size
= layer_size
* u_minify(tex
->tex
.depth0
, i
);
256 tex
->tex
.offset_in_bytes
[i
] = tex
->tex
.size_in_bytes
;
257 tex
->tex
.size_in_bytes
= tex
->tex
.offset_in_bytes
[i
] + size
;
258 tex
->tex
.layer_size_in_bytes
[i
] = layer_size
;
259 tex
->tex
.stride_in_bytes
[i
] = stride
;
260 tex
->tex
.cbzb_allowed
[i
] = tex
->tex
.cbzb_allowed
[i
] && aligned_for_cbzb
;
262 SCREEN_DBG(screen
, DBG_TEXALLOC
, "r300: Texture miptree: Level %d "
263 "(%dx%dx%d px, pitch %d bytes) %d bytes total, macrotiled %s\n",
264 i
, u_minify(tex
->tex
.width0
, i
), u_minify(tex
->tex
.height0
, i
),
265 u_minify(tex
->tex
.depth0
, i
), stride
, tex
->tex
.size_in_bytes
,
266 tex
->tex
.macrotile
[i
] ? "TRUE" : "FALSE");
270 static void r300_setup_flags(struct r300_resource
*tex
)
272 tex
->tex
.uses_stride_addressing
=
273 !util_is_power_of_two_or_zero(tex
->b
.b
.width0
) ||
274 (tex
->tex
.stride_in_bytes_override
&&
275 r300_stride_to_width(tex
->b
.b
.format
,
276 tex
->tex
.stride_in_bytes_override
) != tex
->b
.b
.width0
);
279 tex
->tex
.uses_stride_addressing
||
280 !util_is_power_of_two_or_zero(tex
->b
.b
.height0
) ||
281 !util_is_power_of_two_or_zero(tex
->b
.b
.depth0
);
284 static void r300_setup_cbzb_flags(struct r300_screen
*rscreen
,
285 struct r300_resource
*tex
)
288 boolean first_level_valid
;
290 bpp
= util_format_get_blocksizebits(tex
->b
.b
.format
);
292 /* 1) The texture must be point-sampled,
293 * 2) The depth must be 16 or 32 bits.
294 * 3) If the midpoint ZB offset is not aligned to 2048, it returns garbage
295 * with certain texture sizes. Macrotiling ensures the alignment. */
296 first_level_valid
= tex
->b
.b
.nr_samples
<= 1 &&
297 (bpp
== 16 || bpp
== 32) &&
298 tex
->tex
.macrotile
[0];
300 if (SCREEN_DBG_ON(rscreen
, DBG_NO_CBZB
))
301 first_level_valid
= FALSE
;
303 for (i
= 0; i
<= tex
->b
.b
.last_level
; i
++)
304 tex
->tex
.cbzb_allowed
[i
] = first_level_valid
&& tex
->tex
.macrotile
[i
];
307 static unsigned r300_pixels_to_dwords(unsigned stride
,
309 unsigned xblock
, unsigned yblock
)
311 return (util_align_npot(stride
, xblock
) * align(height
, yblock
)) / (xblock
* yblock
);
314 static void r300_setup_hyperz_properties(struct r300_screen
*screen
,
315 struct r300_resource
*tex
)
317 /* The tile size of 1 DWORD in ZMASK RAM is:
319 * GPU Pipes 4x4 mode 8x8 mode
320 * ------------------------------------------
321 * R580 4P/1Z 32x32 64x64
322 * RV570 3P/1Z 48x16 96x32
323 * RV530 1P/2Z 32x16 64x32
326 static unsigned zmask_blocks_x_per_dw
[4] = {4, 8, 12, 8};
327 static unsigned zmask_blocks_y_per_dw
[4] = {4, 4, 4, 8};
329 /* In HIZ RAM, one dword is always 8x8 pixels (each byte is 4x4 pixels),
330 * but the blocks have very weird ordering.
332 * With 2 pipes and an image of size 8xY, where Y >= 1,
333 * clearing 4 dwords clears blocks like this:
337 * where numbers correspond to dword indices. The blocks are interleaved
338 * in the X direction, so the alignment must be 4x1 blocks (32x8 pixels).
340 * With 4 pipes and an image of size 8xY, where Y >= 4,
341 * clearing 8 dwords clears blocks like this:
346 * where numbers correspond to dword indices. The blocks are interleaved
347 * in both directions, so the alignment must be 4x4 blocks (32x32 pixels)
349 static unsigned hiz_align_x
[4] = {8, 32, 48, 32};
350 static unsigned hiz_align_y
[4] = {8, 8, 8, 32};
352 if (util_format_is_depth_or_stencil(tex
->b
.b
.format
) &&
353 util_format_get_blocksizebits(tex
->b
.b
.format
) == 32 &&
354 tex
->tex
.microtile
) {
357 if (screen
->caps
.family
== CHIP_RV530
) {
358 pipes
= screen
->info
.r300_num_z_pipes
;
360 pipes
= screen
->info
.r300_num_gb_pipes
;
363 for (i
= 0; i
<= tex
->b
.b
.last_level
; i
++) {
364 unsigned zcomp_numdw
, zcompsize
, hiz_numdw
, stride
, height
;
366 stride
= r300_stride_to_width(tex
->b
.b
.format
,
367 tex
->tex
.stride_in_bytes
[i
]);
368 stride
= align(stride
, 16);
369 height
= u_minify(tex
->b
.b
.height0
, i
);
371 /* The 8x8 compression mode needs macrotiling. */
372 zcompsize
= screen
->caps
.z_compress
== R300_ZCOMP_8X8
&&
373 tex
->tex
.macrotile
[i
] &&
374 tex
->b
.b
.nr_samples
<= 1 ? 8 : 4;
376 /* Get the ZMASK buffer size in dwords. */
377 zcomp_numdw
= r300_pixels_to_dwords(stride
, height
,
378 zmask_blocks_x_per_dw
[pipes
-1] * zcompsize
,
379 zmask_blocks_y_per_dw
[pipes
-1] * zcompsize
);
381 /* Check whether we have enough ZMASK memory. */
382 if (util_format_get_blocksizebits(tex
->b
.b
.format
) == 32 &&
383 zcomp_numdw
<= screen
->caps
.zmask_ram
* pipes
) {
384 tex
->tex
.zmask_dwords
[i
] = zcomp_numdw
;
385 tex
->tex
.zcomp8x8
[i
] = zcompsize
== 8;
387 tex
->tex
.zmask_stride_in_pixels
[i
] =
388 util_align_npot(stride
, zmask_blocks_x_per_dw
[pipes
-1] * zcompsize
);
390 tex
->tex
.zmask_dwords
[i
] = 0;
391 tex
->tex
.zcomp8x8
[i
] = FALSE
;
392 tex
->tex
.zmask_stride_in_pixels
[i
] = 0;
396 stride
= util_align_npot(stride
, hiz_align_x
[pipes
-1]);
397 height
= align(height
, hiz_align_y
[pipes
-1]);
399 /* Get the HIZ buffer size in dwords. */
400 hiz_numdw
= (stride
* height
) / (8*8 * pipes
);
402 /* Check whether we have enough HIZ memory. */
403 if (hiz_numdw
<= screen
->caps
.hiz_ram
* pipes
) {
404 tex
->tex
.hiz_dwords
[i
] = hiz_numdw
;
405 tex
->tex
.hiz_stride_in_pixels
[i
] = stride
;
407 tex
->tex
.hiz_dwords
[i
] = 0;
408 tex
->tex
.hiz_stride_in_pixels
[i
] = 0;
414 static void r300_setup_cmask_properties(struct r300_screen
*screen
,
415 struct r300_resource
*tex
)
417 static unsigned cmask_align_x
[4] = {16, 32, 48, 32};
418 static unsigned cmask_align_y
[4] = {16, 16, 16, 32};
419 unsigned pipes
, stride
, cmask_num_dw
, cmask_max_size
;
421 if (!screen
->caps
.has_cmask
) {
425 /* We need an AA colorbuffer, no mipmaps. */
426 if (tex
->b
.b
.nr_samples
<= 1 ||
427 tex
->b
.b
.last_level
> 0 ||
428 util_format_is_depth_or_stencil(tex
->b
.b
.format
)) {
432 /* FP16 AA needs R500 and a fairly new DRM. */
433 if ((tex
->b
.b
.format
== PIPE_FORMAT_R16G16B16A16_FLOAT
||
434 tex
->b
.b
.format
== PIPE_FORMAT_R16G16B16X16_FLOAT
) &&
435 (!screen
->caps
.is_r500
|| screen
->info
.drm_minor
< 29)) {
439 if (SCREEN_DBG_ON(screen
, DBG_NO_CMASK
)) {
443 /* CMASK is part of raster pipes. The number of Z pipes doesn't matter. */
444 pipes
= screen
->info
.r300_num_gb_pipes
;
446 /* The single-pipe cards have 5120 dwords of CMASK RAM,
447 * the other cards have 4096 dwords of CMASK RAM per pipe. */
448 cmask_max_size
= pipes
== 1 ? 5120 : pipes
* 4096;
450 stride
= r300_stride_to_width(tex
->b
.b
.format
,
451 tex
->tex
.stride_in_bytes
[0]);
452 stride
= align(stride
, 16);
454 /* Get the CMASK size in dwords. */
455 cmask_num_dw
= r300_pixels_to_dwords(stride
, tex
->b
.b
.height0
,
456 cmask_align_x
[pipes
-1],
457 cmask_align_y
[pipes
-1]);
459 /* Check the CMASK size against the CMASK memory limit. */
460 if (cmask_num_dw
<= cmask_max_size
) {
461 tex
->tex
.cmask_dwords
= cmask_num_dw
;
462 tex
->tex
.cmask_stride_in_pixels
=
463 util_align_npot(stride
, cmask_align_x
[pipes
-1]);
467 static void r300_setup_tiling(struct r300_screen
*screen
,
468 struct r300_resource
*tex
)
470 enum pipe_format format
= tex
->b
.b
.format
;
471 boolean rv350_mode
= screen
->caps
.family
>= CHIP_R350
;
472 boolean is_zb
= util_format_is_depth_or_stencil(format
);
473 boolean dbg_no_tiling
= SCREEN_DBG_ON(screen
, DBG_NO_TILING
);
474 boolean force_microtiling
=
475 (tex
->b
.b
.flags
& R300_RESOURCE_FORCE_MICROTILING
) != 0;
477 if (tex
->b
.b
.nr_samples
> 1) {
478 tex
->tex
.microtile
= RADEON_LAYOUT_TILED
;
479 tex
->tex
.macrotile
[0] = RADEON_LAYOUT_TILED
;
483 tex
->tex
.microtile
= RADEON_LAYOUT_LINEAR
;
484 tex
->tex
.macrotile
[0] = RADEON_LAYOUT_LINEAR
;
486 if (tex
->b
.b
.usage
== PIPE_USAGE_STAGING
) {
490 if (!util_format_is_plain(format
)) {
494 /* If height == 1, disable microtiling except for zbuffer. */
495 if (!force_microtiling
&& !is_zb
&&
496 (tex
->b
.b
.height0
== 1 || dbg_no_tiling
)) {
500 /* Set microtiling. */
501 switch (util_format_get_blocksize(format
)) {
505 tex
->tex
.microtile
= RADEON_LAYOUT_TILED
;
509 tex
->tex
.microtile
= RADEON_LAYOUT_SQUARETILED
;
517 /* Set macrotiling. */
518 if (r300_texture_macro_switch(tex
, 0, rv350_mode
, DIM_WIDTH
) &&
519 r300_texture_macro_switch(tex
, 0, rv350_mode
, DIM_HEIGHT
)) {
520 tex
->tex
.macrotile
[0] = RADEON_LAYOUT_TILED
;
524 static void r300_tex_print_info(struct r300_resource
*tex
,
528 "r300: %s: Macro: %s, Micro: %s, Pitch: %i, Dim: %ix%ix%i, "
529 "LastLevel: %i, Size: %i, Format: %s, Samples: %i\n",
531 tex
->tex
.macrotile
[0] ? "YES" : " NO",
532 tex
->tex
.microtile
? "YES" : " NO",
533 r300_stride_to_width(tex
->b
.b
.format
, tex
->tex
.stride_in_bytes
[0]),
534 tex
->b
.b
.width0
, tex
->b
.b
.height0
, tex
->b
.b
.depth0
,
535 tex
->b
.b
.last_level
, tex
->tex
.size_in_bytes
,
536 util_format_short_name(tex
->b
.b
.format
),
537 tex
->b
.b
.nr_samples
);
540 void r300_texture_desc_init(struct r300_screen
*rscreen
,
541 struct r300_resource
*tex
,
542 const struct pipe_resource
*base
)
544 tex
->b
.b
.target
= base
->target
;
545 tex
->b
.b
.format
= base
->format
;
546 tex
->b
.b
.width0
= base
->width0
;
547 tex
->b
.b
.height0
= base
->height0
;
548 tex
->b
.b
.depth0
= base
->depth0
;
549 tex
->b
.b
.array_size
= base
->array_size
;
550 tex
->b
.b
.last_level
= base
->last_level
;
551 tex
->b
.b
.nr_samples
= base
->nr_samples
;
552 tex
->tex
.width0
= base
->width0
;
553 tex
->tex
.height0
= base
->height0
;
554 tex
->tex
.depth0
= base
->depth0
;
556 /* There is a CB memory addressing hardware bug that limits the width
557 * of the MSAA buffer in some cases in R520. In order to get around it,
558 * the following code lowers the sample count depending on the format and
561 * The only catch is that all MSAA colorbuffers and a zbuffer which are
562 * supposed to be used together should always be bound together. Only
563 * then the correct minimum sample count of all bound buffers is used
565 if (rscreen
->caps
.is_r500
) {
566 /* FP16 6x MSAA buffers are limited to a width of 1360 pixels. */
567 if ((tex
->b
.b
.format
== PIPE_FORMAT_R16G16B16A16_FLOAT
||
568 tex
->b
.b
.format
== PIPE_FORMAT_R16G16B16X16_FLOAT
) &&
569 tex
->b
.b
.nr_samples
== 6 && tex
->b
.b
.width0
> 1360) {
570 tex
->b
.b
.nr_samples
= 4;
573 /* FP16 4x MSAA buffers are limited to a width of 2048 pixels. */
574 if ((tex
->b
.b
.format
== PIPE_FORMAT_R16G16B16A16_FLOAT
||
575 tex
->b
.b
.format
== PIPE_FORMAT_R16G16B16X16_FLOAT
) &&
576 tex
->b
.b
.nr_samples
== 4 && tex
->b
.b
.width0
> 2048) {
577 tex
->b
.b
.nr_samples
= 2;
581 /* 32-bit 6x MSAA buffers are limited to a width of 2720 pixels.
582 * This applies to all R300-R500 cards. */
583 if (util_format_get_blocksizebits(tex
->b
.b
.format
) == 32 &&
584 !util_format_is_depth_or_stencil(tex
->b
.b
.format
) &&
585 tex
->b
.b
.nr_samples
== 6 && tex
->b
.b
.width0
> 2720) {
586 tex
->b
.b
.nr_samples
= 4;
589 r300_setup_flags(tex
);
591 /* Align a 3D NPOT texture to POT. */
592 if (base
->target
== PIPE_TEXTURE_3D
&& tex
->tex
.is_npot
) {
593 tex
->tex
.width0
= util_next_power_of_two(tex
->tex
.width0
);
594 tex
->tex
.height0
= util_next_power_of_two(tex
->tex
.height0
);
595 tex
->tex
.depth0
= util_next_power_of_two(tex
->tex
.depth0
);
599 if (tex
->tex
.microtile
== RADEON_LAYOUT_UNKNOWN
) {
600 r300_setup_tiling(rscreen
, tex
);
603 r300_setup_cbzb_flags(rscreen
, tex
);
605 /* Setup the miptree description. */
606 r300_setup_miptree(rscreen
, tex
, TRUE
);
607 /* If the required buffer size is larger than the given max size,
608 * try again without the alignment for the CBZB clear. */
609 if (tex
->buf
&& tex
->tex
.size_in_bytes
> tex
->buf
->size
) {
610 r300_setup_miptree(rscreen
, tex
, FALSE
);
612 /* Make sure the buffer we got is large enough. */
613 if (tex
->tex
.size_in_bytes
> tex
->buf
->size
) {
615 "r300: I got a pre-allocated buffer to use it as a texture "
616 "storage, but the buffer is too small. I'll use the buffer "
617 "anyway, because I can't crash here, but it's dangerous. "
618 "This can be a DDX bug. Got: %"PRIu64
"B, Need: %uB, Info:\n",
619 tex
->buf
->size
, tex
->tex
.size_in_bytes
);
620 r300_tex_print_info(tex
, "texture_desc_init");
621 /* Ooops, what now. Apps will break if we fail this,
622 * so just pretend everything's okay. */
626 r300_setup_hyperz_properties(rscreen
, tex
);
627 r300_setup_cmask_properties(rscreen
, tex
);
629 if (SCREEN_DBG_ON(rscreen
, DBG_TEX
))
630 r300_tex_print_info(tex
, "texture_desc_init");
633 unsigned r300_texture_get_offset(struct r300_resource
*tex
,
634 unsigned level
, unsigned layer
)
636 unsigned offset
= tex
->tex
.offset_in_bytes
[level
];
638 switch (tex
->b
.b
.target
) {
639 case PIPE_TEXTURE_3D
:
640 case PIPE_TEXTURE_CUBE
:
641 return offset
+ layer
* tex
->tex
.layer_size_in_bytes
[level
];