629e587be4d0b57f7062592468b910845890bd29
[mesa.git] / src / gallium / drivers / r300 / r5xx_fs.h
1 /*
2 * Copyright 2008 Corbin Simpson <MostAwesomeDude@gmail.com>
3 * Joakim Sindholt <opensource@zhasha.com>
4 *
5 * Permission is hereby granted, free of charge, to any person obtaining a
6 * copy of this software and associated documentation files (the "Software"),
7 * to deal in the Software without restriction, including without limitation
8 * on the rights to use, copy, modify, merge, publish, distribute, sub
9 * license, and/or sell copies of the Software, and to permit persons to whom
10 * the Software is furnished to do so, subject to the following conditions:
11 *
12 * The above copyright notice and this permission notice (including the next
13 * paragraph) shall be included in all copies or substantial portions of the
14 * Software.
15 *
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
19 * THE AUTHOR(S) AND/OR THEIR SUPPLIERS BE LIABLE FOR ANY CLAIM,
20 * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
21 * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
22 * USE OR OTHER DEALINGS IN THE SOFTWARE. */
23
24 #ifndef R5XX_FS_H
25 #define R5XX_FS_H
26
27 #include "r300_fs_inlines.h"
28
29 /* XXX this all should find its way back to r300_reg */
30 /* Swizzle tools */
31 #define R500_SWIZZLE_ZERO 4
32 #define R500_SWIZZLE_HALF 5
33 #define R500_SWIZZLE_ONE 6
34 #define R500_SWIZ_RGB_ZERO ((4 << 0) | (4 << 3) | (4 << 6))
35 #define R500_SWIZ_RGB_ONE ((6 << 0) | (6 << 3) | (6 << 6))
36 #define R500_SWIZ_RGB_RGB ((0 << 0) | (1 << 3) | (2 << 6))
37 #define R500_SWIZ_MOD_NEG 1
38 #define R500_SWIZ_MOD_ABS 2
39 #define R500_SWIZ_MOD_NEG_ABS 3
40 /* Swizzles for inst2 */
41 #define R500_SWIZ_TEX_STRQ(x) ((x) << 8)
42 #define R500_SWIZ_TEX_RGBA(x) ((x) << 24)
43 /* Swizzles for inst3 */
44 #define R500_SWIZ_RGB_A(x) ((x) << 2)
45 #define R500_SWIZ_RGB_B(x) ((x) << 15)
46 /* Swizzles for inst4 */
47 #define R500_SWIZ_ALPHA_A(x) ((x) << 14)
48 #define R500_SWIZ_ALPHA_B(x) ((x) << 21)
49 /* Swizzle for inst5 */
50 #define R500_SWIZ_RGBA_C(x) ((x) << 14)
51 #define R500_SWIZ_ALPHA_C(x) ((x) << 27)
52 /* Writemasks */
53 #define R500_TEX_WMASK(x) ((x) << 11)
54 #define R500_ALU_WMASK(x) ((x) << 11)
55 #define R500_ALU_OMASK(x) ((x) << 15)
56 #define R500_W_OMASK (1 << 31)
57
58 static struct r5xx_fragment_shader r5xx_passthrough_fragment_shader = {
59 .shader.stack_size = 0,
60 .instruction_count = 1,
61 .instructions[0].inst0 = R500_INST_TYPE_OUT |
62 R500_INST_TEX_SEM_WAIT | R500_INST_LAST |
63 R500_INST_RGB_OMASK_RGB | R500_INST_ALPHA_OMASK |
64 R500_INST_RGB_CLAMP | R500_INST_ALPHA_CLAMP,
65 .instructions[0].inst1 =
66 R500_RGB_ADDR0(0) | R500_RGB_ADDR1(0) | R500_RGB_ADDR1_CONST |
67 R500_RGB_ADDR2(0) | R500_RGB_ADDR2_CONST,
68 .instructions[0].inst2 =
69 R500_ALPHA_ADDR0(0) | R500_ALPHA_ADDR1(0) | R500_ALPHA_ADDR1_CONST |
70 R500_ALPHA_ADDR2(0) | R500_ALPHA_ADDR2_CONST,
71 .instructions[0].inst3 =
72 R500_ALU_RGB_SEL_A_SRC0 | R500_ALU_RGB_R_SWIZ_A_R |
73 R500_ALU_RGB_G_SWIZ_A_G | R500_ALU_RGB_B_SWIZ_A_B |
74 R500_ALU_RGB_SEL_B_SRC0 | R500_ALU_RGB_R_SWIZ_B_R |
75 R500_ALU_RGB_B_SWIZ_B_G | R500_ALU_RGB_G_SWIZ_B_B,
76 .instructions[0].inst4 =
77 R500_ALPHA_OP_CMP | R500_ALPHA_SWIZ_A_A | R500_ALPHA_SWIZ_B_A,
78 .instructions[0].inst5 =
79 R500_ALU_RGBA_OP_CMP | R500_ALU_RGBA_R_SWIZ_0 |
80 R500_ALU_RGBA_G_SWIZ_0 | R500_ALU_RGBA_B_SWIZ_0 |
81 R500_ALU_RGBA_A_SWIZ_0,
82 };
83
84 static struct r5xx_fragment_shader r5xx_texture_fragment_shader = {
85 .shader.stack_size = 1,
86 .instruction_count = 2,
87 .instructions[0].inst0 = R500_INST_TYPE_TEX |
88 R500_INST_TEX_SEM_WAIT |
89 R500_INST_RGB_WMASK_RGB | R500_INST_ALPHA_WMASK |
90 R500_INST_RGB_CLAMP | R500_INST_ALPHA_CLAMP,
91 .instructions[0].inst1 = R500_TEX_ID(0) | R500_TEX_INST_LD |
92 R500_TEX_SEM_ACQUIRE | R500_TEX_IGNORE_UNCOVERED,
93 .instructions[0].inst2 = R500_TEX_SRC_ADDR(0) |
94 R500_TEX_SRC_S_SWIZ_R | R500_TEX_SRC_T_SWIZ_G |
95 R500_TEX_SRC_R_SWIZ_B | R500_TEX_SRC_Q_SWIZ_A |
96 R500_TEX_DST_ADDR(0) |
97 R500_TEX_DST_R_SWIZ_R | R500_TEX_DST_G_SWIZ_G |
98 R500_TEX_DST_B_SWIZ_B | R500_TEX_DST_A_SWIZ_A,
99 .instructions[0].inst3 = 0x0,
100 .instructions[0].inst4 = 0x0,
101 .instructions[0].inst5 = 0x0,
102 .instructions[1].inst0 = R500_INST_TYPE_OUT |
103 R500_INST_TEX_SEM_WAIT | R500_INST_LAST |
104 R500_INST_RGB_OMASK_RGB | R500_INST_ALPHA_OMASK |
105 R500_INST_RGB_CLAMP | R500_INST_ALPHA_CLAMP,
106 .instructions[1].inst1 =
107 R500_RGB_ADDR0(0) | R500_RGB_ADDR1(0) | R500_RGB_ADDR1_CONST |
108 R500_RGB_ADDR2(0) | R500_RGB_ADDR2_CONST,
109 .instructions[1].inst2 =
110 R500_ALPHA_ADDR0(0) | R500_ALPHA_ADDR1(0) | R500_ALPHA_ADDR1_CONST |
111 R500_ALPHA_ADDR2(0) | R500_ALPHA_ADDR2_CONST,
112 .instructions[1].inst3 =
113 R500_ALU_RGB_SEL_A_SRC0 | R500_ALU_RGB_R_SWIZ_A_R |
114 R500_ALU_RGB_G_SWIZ_A_G | R500_ALU_RGB_B_SWIZ_A_B |
115 R500_ALU_RGB_SEL_B_SRC0 | R500_ALU_RGB_R_SWIZ_B_R |
116 R500_ALU_RGB_B_SWIZ_B_G | R500_ALU_RGB_G_SWIZ_B_B,
117 .instructions[1].inst4 =
118 R500_ALPHA_OP_CMP | R500_ALPHA_SWIZ_A_A | R500_ALPHA_SWIZ_B_A,
119 .instructions[1].inst5 =
120 R500_ALU_RGBA_OP_CMP | R500_ALU_RGBA_R_SWIZ_0 |
121 R500_ALU_RGBA_G_SWIZ_0 | R500_ALU_RGBA_B_SWIZ_0 |
122 R500_ALU_RGBA_A_SWIZ_0,
123 };
124
125 void r5xx_fs_finalize(struct r5xx_fragment_shader* fs,
126 struct r300_fs_asm* assembler);
127
128 void r5xx_fs_instruction(struct r5xx_fragment_shader* fs,
129 struct r300_fs_asm* assembler,
130 struct tgsi_full_instruction* inst);
131
132 #endif /* R5XX_FS_H */