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889eedadef55b82dd76a6f8487654f373340280f
[mesa.git] / src / gallium / drivers / r600 / eg_hw_states.c
1 /*
2 * Copyright 2010 Jerome Glisse <glisse@freedesktop.org>
3 * 2010 Red Hat Inc.
4 *
5 * Permission is hereby granted, free of charge, to any person obtaining a
6 * copy of this software and associated documentation files (the "Software"),
7 * to deal in the Software without restriction, including without limitation
8 * on the rights to use, copy, modify, merge, publish, distribute, sub
9 * license, and/or sell copies of the Software, and to permit persons to whom
10 * the Software is furnished to do so, subject to the following conditions:
11 *
12 * The above copyright notice and this permission notice (including the next
13 * paragraph) shall be included in all copies or substantial portions of the
14 * Software.
15 *
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
19 * THE AUTHOR(S) AND/OR THEIR SUPPLIERS BE LIABLE FOR ANY CLAIM,
20 * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
21 * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
22 * USE OR OTHER DEALINGS IN THE SOFTWARE.
23 *
24 * Authors:
25 * Jerome Glisse
26 * Dave Airlie
27 */
28 #include <util/u_inlines.h>
29 #include <util/u_format.h>
30 #include <util/u_memory.h>
31 #include <util/u_blitter.h>
32 #include "util/u_pack_color.h"
33 #include "r600_screen.h"
34 #include "r600_context.h"
35 #include "r600_resource.h"
36 #include "eg_state_inlines.h"
37 #include "evergreend.h"
38
39 #include "eg_states_inc.h"
40
41 static void eg_blend(struct r600_context *rctx, struct radeon_state *rstate, const struct pipe_blend_state *state)
42 {
43 struct r600_screen *rscreen = rctx->screen;
44 int i;
45
46 radeon_state_init(rstate, rscreen->rw, R600_STATE_BLEND, 0, 0);
47 rstate->states[EG_BLEND__CB_BLEND_RED] = fui(rctx->blend_color.color[0]);
48 rstate->states[EG_BLEND__CB_BLEND_GREEN] = fui(rctx->blend_color.color[1]);
49 rstate->states[EG_BLEND__CB_BLEND_BLUE] = fui(rctx->blend_color.color[2]);
50 rstate->states[EG_BLEND__CB_BLEND_ALPHA] = fui(rctx->blend_color.color[3]);
51 rstate->states[EG_BLEND__CB_BLEND0_CONTROL] = 0x00000000;
52 rstate->states[EG_BLEND__CB_BLEND1_CONTROL] = 0x00000000;
53 rstate->states[EG_BLEND__CB_BLEND2_CONTROL] = 0x00000000;
54 rstate->states[EG_BLEND__CB_BLEND3_CONTROL] = 0x00000000;
55 rstate->states[EG_BLEND__CB_BLEND4_CONTROL] = 0x00000000;
56 rstate->states[EG_BLEND__CB_BLEND5_CONTROL] = 0x00000000;
57 rstate->states[EG_BLEND__CB_BLEND6_CONTROL] = 0x00000000;
58 rstate->states[EG_BLEND__CB_BLEND7_CONTROL] = 0x00000000;
59
60 for (i = 0; i < 8; i++) {
61 unsigned eqRGB = state->rt[i].rgb_func;
62 unsigned srcRGB = state->rt[i].rgb_src_factor;
63 unsigned dstRGB = state->rt[i].rgb_dst_factor;
64
65 unsigned eqA = state->rt[i].alpha_func;
66 unsigned srcA = state->rt[i].alpha_src_factor;
67 unsigned dstA = state->rt[i].alpha_dst_factor;
68 uint32_t bc = 0;
69
70 if (!state->rt[i].blend_enable)
71 continue;
72
73 bc |= S_028780_BLEND_CONTROL_ENABLE(1);
74
75 bc |= S_028780_COLOR_COMB_FCN(r600_translate_blend_function(eqRGB));
76 bc |= S_028780_COLOR_SRCBLEND(r600_translate_blend_factor(srcRGB));
77 bc |= S_028780_COLOR_DESTBLEND(r600_translate_blend_factor(dstRGB));
78
79 if (srcA != srcRGB || dstA != dstRGB || eqA != eqRGB) {
80 bc |= S_028780_SEPARATE_ALPHA_BLEND(1);
81 bc |= S_028780_ALPHA_COMB_FCN(r600_translate_blend_function(eqA));
82 bc |= S_028780_ALPHA_SRCBLEND(r600_translate_blend_factor(srcA));
83 bc |= S_028780_ALPHA_DESTBLEND(r600_translate_blend_factor(dstA));
84 }
85
86 rstate->states[EG_BLEND__CB_BLEND0_CONTROL + i] = bc;
87 }
88
89 radeon_state_pm4(rstate);
90 }
91
92 static void eg_ucp(struct r600_context *rctx, struct radeon_state *rstate,
93 const struct pipe_clip_state *state)
94 {
95 struct r600_screen *rscreen = rctx->screen;
96
97 radeon_state_init(rstate, rscreen->rw, R600_STATE_UCP, 0, 0);
98
99 for (int i = 0; i < state->nr; i++) {
100 rstate->states[i * 4 + 0] = fui(state->ucp[i][0]);
101 rstate->states[i * 4 + 1] = fui(state->ucp[i][1]);
102 rstate->states[i * 4 + 2] = fui(state->ucp[i][2]);
103 rstate->states[i * 4 + 3] = fui(state->ucp[i][3]);
104 }
105 radeon_state_pm4(rstate);
106 }
107
108 static void eg_cb(struct r600_context *rctx, struct radeon_state *rstate,
109 const struct pipe_framebuffer_state *state, int cb)
110 {
111 struct r600_screen *rscreen = rctx->screen;
112 struct r600_resource_texture *rtex;
113 struct r600_resource *rbuffer;
114 unsigned level = state->cbufs[cb]->level;
115 unsigned pitch, slice;
116 unsigned color_info;
117 unsigned format, swap, ntype;
118 const struct util_format_description *desc;
119
120 radeon_state_init(rstate, rscreen->rw, R600_STATE_CB0, cb, 0);
121 rtex = (struct r600_resource_texture*)state->cbufs[cb]->texture;
122 rbuffer = &rtex->resource;
123 radeon_ws_bo_reference(rscreen->rw, &rstate->bo[0], rbuffer->bo);
124 rstate->placement[0] = RADEON_GEM_DOMAIN_VRAM;
125 rstate->nbo = 1;
126 pitch = (rtex->pitch[level] / rtex->bpt) / 8 - 1;
127 slice = (rtex->pitch[level] / rtex->bpt) * state->cbufs[cb]->height / 64 - 1;
128
129 ntype = 0;
130 desc = util_format_description(rtex->resource.base.b.format);
131 if (desc->colorspace == UTIL_FORMAT_COLORSPACE_SRGB)
132 ntype = V_028C70_NUMBER_SRGB;
133
134 format = r600_translate_colorformat(rtex->resource.base.b.format);
135 swap = r600_translate_colorswap(rtex->resource.base.b.format);
136
137 color_info = S_028C70_FORMAT(format) |
138 S_028C70_COMP_SWAP(swap) |
139 S_028C70_BLEND_CLAMP(1) |
140 S_028C70_SOURCE_FORMAT(1) |
141 S_028C70_NUMBER_TYPE(ntype);
142
143 rstate->states[EG_CB__CB_COLOR0_BASE] = state->cbufs[cb]->offset >> 8;
144 rstate->states[EG_CB__CB_COLOR0_INFO] = color_info;
145 rstate->states[EG_CB__CB_COLOR0_PITCH] = S_028C64_PITCH_TILE_MAX(pitch);
146 rstate->states[EG_CB__CB_COLOR0_SLICE] = S_028C68_SLICE_TILE_MAX(slice);
147 rstate->states[EG_CB__CB_COLOR0_VIEW] = 0x00000000;
148 rstate->states[EG_CB__CB_COLOR0_ATTRIB] = S_028C74_NON_DISP_TILING_ORDER(1);
149
150 radeon_state_pm4(rstate);
151 }
152
153 static void eg_db(struct r600_context *rctx, struct radeon_state *rstate,
154 const struct pipe_framebuffer_state *state)
155 {
156 struct r600_screen *rscreen = rctx->screen;
157 struct r600_resource_texture *rtex;
158 struct r600_resource *rbuffer;
159 unsigned level;
160 unsigned pitch, slice, format;
161
162 radeon_state_init(rstate, rscreen->rw, R600_STATE_DB, 0, 0);
163 if (state->zsbuf == NULL)
164 return;
165
166 rtex = (struct r600_resource_texture*)state->zsbuf->texture;
167 rtex->tiled = 1;
168 rtex->array_mode = 2;
169 rtex->tile_type = 1;
170 rtex->depth = 1;
171 rbuffer = &rtex->resource;
172
173 radeon_ws_bo_reference(rscreen->rw, &rstate->bo[0], rbuffer->bo);
174 rstate->nbo = 1;
175 rstate->placement[0] = RADEON_GEM_DOMAIN_VRAM;
176 level = state->zsbuf->level;
177 pitch = (rtex->pitch[level] / rtex->bpt) / 8 - 1;
178 slice = (rtex->pitch[level] / rtex->bpt) * state->zsbuf->height / 64 - 1;
179 format = r600_translate_dbformat(state->zsbuf->texture->format);
180 rstate->states[EG_DB__DB_HTILE_DATA_BASE] = state->zsbuf->offset >> 8;
181 rstate->states[EG_DB__DB_Z_READ_BASE] = state->zsbuf->offset >> 8;
182 rstate->states[EG_DB__DB_Z_WRITE_BASE] = state->zsbuf->offset >> 8;
183 rstate->states[EG_DB__DB_STENCIL_READ_BASE] = state->zsbuf->offset >> 8;
184 rstate->states[EG_DB__DB_STENCIL_WRITE_BASE] = state->zsbuf->offset >> 8;
185 rstate->states[EG_DB__DB_Z_INFO] = S_028040_ARRAY_MODE(rtex->array_mode) | S_028040_FORMAT(format);
186 rstate->states[EG_DB__DB_DEPTH_VIEW] = 0x00000000;
187 rstate->states[EG_DB__DB_DEPTH_SIZE] = S_028058_PITCH_TILE_MAX(pitch);
188 rstate->states[EG_DB__DB_DEPTH_SLICE] = S_02805C_SLICE_TILE_MAX(slice);
189 radeon_state_pm4(rstate);
190 }
191
192 static void eg_rasterizer(struct r600_context *rctx, struct radeon_state *rstate)
193 {
194 const struct pipe_rasterizer_state *state = &rctx->rasterizer->state.rasterizer;
195 const struct pipe_framebuffer_state *fb = &rctx->framebuffer->state.framebuffer;
196 const struct pipe_clip_state *clip = NULL;
197 struct r600_screen *rscreen = rctx->screen;
198 float offset_units = 0, offset_scale = 0;
199 char depth = 0;
200 unsigned offset_db_fmt_cntl = 0;
201 unsigned tmp;
202 unsigned prov_vtx = 1;
203 unsigned polygon_dual_mode;
204
205 if (rctx->clip)
206 clip = &rctx->clip->state.clip;
207 if (fb->zsbuf) {
208 offset_units = state->offset_units;
209 offset_scale = state->offset_scale * 12.0f;
210 switch (fb->zsbuf->texture->format) {
211 case PIPE_FORMAT_Z24X8_UNORM:
212 case PIPE_FORMAT_Z24_UNORM_S8_USCALED:
213 depth = -24;
214 offset_units *= 2.0f;
215 break;
216 case PIPE_FORMAT_Z32_FLOAT:
217 depth = -23;
218 offset_units *= 1.0f;
219 offset_db_fmt_cntl |= S_028B78_POLY_OFFSET_DB_IS_FLOAT_FMT(1);
220 break;
221 case PIPE_FORMAT_Z16_UNORM:
222 depth = -16;
223 offset_units *= 4.0f;
224 break;
225 default:
226 R600_ERR("unsupported %d\n", fb->zsbuf->texture->format);
227 return;
228 }
229 }
230 offset_db_fmt_cntl |= S_028B78_POLY_OFFSET_NEG_NUM_DB_BITS(depth);
231
232 if (state->flatshade_first)
233 prov_vtx = 0;
234
235 rctx->flat_shade = state->flatshade;
236 radeon_state_init(rstate, rscreen->rw, R600_STATE_RASTERIZER, 0, 0);
237 rstate->states[EG_RASTERIZER__SPI_INTERP_CONTROL_0] = 0x00000000;
238 if (rctx->flat_shade)
239 rstate->states[EG_RASTERIZER__SPI_INTERP_CONTROL_0] |= S_0286D4_FLAT_SHADE_ENA(1);
240 if (state->sprite_coord_enable) {
241 rstate->states[EG_RASTERIZER__SPI_INTERP_CONTROL_0] |=
242 S_0286D4_PNT_SPRITE_ENA(1) |
243 S_0286D4_PNT_SPRITE_OVRD_X(2) |
244 S_0286D4_PNT_SPRITE_OVRD_Y(3) |
245 S_0286D4_PNT_SPRITE_OVRD_Z(0) |
246 S_0286D4_PNT_SPRITE_OVRD_W(1);
247 if (state->sprite_coord_mode != PIPE_SPRITE_COORD_UPPER_LEFT) {
248 rstate->states[EG_RASTERIZER__SPI_INTERP_CONTROL_0] |=
249 S_0286D4_PNT_SPRITE_TOP_1(1);
250 }
251 }
252 rstate->states[EG_RASTERIZER__PA_CL_CLIP_CNTL] = 0;
253 if (clip) {
254 rstate->states[EG_RASTERIZER__PA_CL_CLIP_CNTL] = S_028810_PS_UCP_MODE(3) | ((1 << clip->nr) - 1);
255 rstate->states[EG_RASTERIZER__PA_CL_CLIP_CNTL] |= S_028810_ZCLIP_NEAR_DISABLE(clip->depth_clamp);
256 rstate->states[EG_RASTERIZER__PA_CL_CLIP_CNTL] |= S_028810_ZCLIP_FAR_DISABLE(clip->depth_clamp);
257 }
258 polygon_dual_mode = (state->fill_front != PIPE_POLYGON_MODE_FILL ||
259 state->fill_back != PIPE_POLYGON_MODE_FILL);
260
261 rstate->states[EG_RASTERIZER__PA_SU_SC_MODE_CNTL] =
262 S_028814_PROVOKING_VTX_LAST(prov_vtx) |
263 S_028814_CULL_FRONT((state->cull_face & PIPE_FACE_FRONT) ? 1 : 0) |
264 S_028814_CULL_BACK((state->cull_face & PIPE_FACE_BACK) ? 1 : 0) |
265 S_028814_FACE(!state->front_ccw) |
266 S_028814_POLY_OFFSET_FRONT_ENABLE(state->offset_tri) |
267 S_028814_POLY_OFFSET_BACK_ENABLE(state->offset_tri) |
268 S_028814_POLY_OFFSET_PARA_ENABLE(state->offset_tri) |
269 S_028814_POLY_MODE(polygon_dual_mode) |
270 S_028814_POLYMODE_FRONT_PTYPE(r600_translate_fill(state->fill_front)) |
271 S_028814_POLYMODE_BACK_PTYPE(r600_translate_fill(state->fill_back));
272 rstate->states[EG_RASTERIZER__PA_CL_VS_OUT_CNTL] =
273 S_02881C_USE_VTX_POINT_SIZE(state->point_size_per_vertex) |
274 S_02881C_VS_OUT_MISC_VEC_ENA(state->point_size_per_vertex);
275 rstate->states[EG_RASTERIZER__PA_CL_NANINF_CNTL] = 0x00000000;
276 /* point size 12.4 fixed point */
277 tmp = (unsigned)(state->point_size * 8.0);
278 rstate->states[EG_RASTERIZER__PA_SU_POINT_SIZE] = S_028A00_HEIGHT(tmp) | S_028A00_WIDTH(tmp);
279 rstate->states[EG_RASTERIZER__PA_SU_POINT_MINMAX] = 0x80000000;
280 rstate->states[EG_RASTERIZER__PA_SU_LINE_CNTL] = 0x00000008;
281 rstate->states[EG_RASTERIZER__PA_SU_VTX_CNTL] = 0x00000005;
282
283 rstate->states[EG_RASTERIZER__PA_SC_MPASS_PS_CNTL] = 0x00000000;
284 rstate->states[EG_RASTERIZER__PA_SC_LINE_CNTL] = 0x00000400;
285 rstate->states[EG_RASTERIZER__PA_CL_GB_VERT_CLIP_ADJ] = 0x3F800000;
286 rstate->states[EG_RASTERIZER__PA_CL_GB_VERT_DISC_ADJ] = 0x3F800000;
287 rstate->states[EG_RASTERIZER__PA_CL_GB_HORZ_CLIP_ADJ] = 0x3F800000;
288 rstate->states[EG_RASTERIZER__PA_CL_GB_HORZ_DISC_ADJ] = 0x3F800000;
289 rstate->states[EG_RASTERIZER__PA_SU_POLY_OFFSET_DB_FMT_CNTL] = offset_db_fmt_cntl;
290 rstate->states[EG_RASTERIZER__PA_SU_POLY_OFFSET_CLAMP] = 0x00000000;
291 rstate->states[EG_RASTERIZER__PA_SU_POLY_OFFSET_FRONT_SCALE] = fui(offset_scale);
292 rstate->states[EG_RASTERIZER__PA_SU_POLY_OFFSET_FRONT_OFFSET] = fui(offset_units);
293 rstate->states[EG_RASTERIZER__PA_SU_POLY_OFFSET_BACK_SCALE] = fui(offset_scale);
294 rstate->states[EG_RASTERIZER__PA_SU_POLY_OFFSET_BACK_OFFSET] = fui(offset_units);
295 radeon_state_pm4(rstate);
296 }
297
298 static void eg_scissor(struct r600_context *rctx, struct radeon_state *rstate)
299 {
300 const struct pipe_scissor_state *state = &rctx->scissor->state.scissor;
301 const struct pipe_framebuffer_state *fb = &rctx->framebuffer->state.framebuffer;
302 struct r600_screen *rscreen = rctx->screen;
303 unsigned minx, maxx, miny, maxy;
304 u32 tl, br;
305
306 if (state == NULL) {
307 minx = 0;
308 miny = 0;
309 maxx = fb->cbufs[0]->width;
310 maxy = fb->cbufs[0]->height;
311 } else {
312 minx = state->minx;
313 miny = state->miny;
314 maxx = state->maxx;
315 maxy = state->maxy;
316 }
317 tl = S_028240_TL_X(minx) | S_028240_TL_Y(miny);
318 br = S_028244_BR_X(maxx) | S_028244_BR_Y(maxy);
319 radeon_state_init(rstate, rscreen->rw, R600_STATE_SCISSOR, 0, 0);
320 /* screen scissor has no WINDOW OFFSET */
321 rstate->states[EG_SCISSOR__PA_SC_SCREEN_SCISSOR_TL] = tl;
322 rstate->states[EG_SCISSOR__PA_SC_SCREEN_SCISSOR_BR] = br;
323 rstate->states[EG_SCISSOR__PA_SC_WINDOW_OFFSET] = 0x00000000;
324 rstate->states[EG_SCISSOR__PA_SC_WINDOW_SCISSOR_TL] = tl | S_028204_WINDOW_OFFSET_DISABLE(1);
325 rstate->states[EG_SCISSOR__PA_SC_WINDOW_SCISSOR_BR] = br;
326 rstate->states[EG_SCISSOR__PA_SC_CLIPRECT_RULE] = 0x0000FFFF;
327 rstate->states[EG_SCISSOR__PA_SC_CLIPRECT_0_TL] = tl;
328 rstate->states[EG_SCISSOR__PA_SC_CLIPRECT_0_BR] = br;
329 rstate->states[EG_SCISSOR__PA_SC_CLIPRECT_1_TL] = tl;
330 rstate->states[EG_SCISSOR__PA_SC_CLIPRECT_1_BR] = br;
331 rstate->states[EG_SCISSOR__PA_SC_CLIPRECT_2_TL] = tl;
332 rstate->states[EG_SCISSOR__PA_SC_CLIPRECT_2_BR] = br;
333 rstate->states[EG_SCISSOR__PA_SC_CLIPRECT_3_TL] = tl;
334 rstate->states[EG_SCISSOR__PA_SC_CLIPRECT_3_BR] = br;
335 rstate->states[EG_SCISSOR__PA_SC_EDGERULE] = 0xAAAAAAAA;
336 rstate->states[EG_SCISSOR__PA_SC_GENERIC_SCISSOR_TL] = tl | S_028240_WINDOW_OFFSET_DISABLE(1);
337 rstate->states[EG_SCISSOR__PA_SC_GENERIC_SCISSOR_BR] = br;
338 rstate->states[EG_SCISSOR__PA_SC_VPORT_SCISSOR_0_TL] = tl | S_028240_WINDOW_OFFSET_DISABLE(1);
339 rstate->states[EG_SCISSOR__PA_SC_VPORT_SCISSOR_0_BR] = br;
340 radeon_state_pm4(rstate);
341 }
342
343 static void eg_viewport(struct r600_context *rctx, struct radeon_state *rstate, const struct pipe_viewport_state *state)
344 {
345 struct r600_screen *rscreen = rctx->screen;
346
347 radeon_state_init(rstate, rscreen->rw, R600_STATE_VIEWPORT, 0, 0);
348 rstate->states[EG_VIEWPORT__PA_SC_VPORT_ZMIN_0] = 0x00000000;
349 rstate->states[EG_VIEWPORT__PA_SC_VPORT_ZMAX_0] = 0x3F800000;
350 rstate->states[EG_VIEWPORT__PA_CL_VPORT_XSCALE_0] = fui(state->scale[0]);
351 rstate->states[EG_VIEWPORT__PA_CL_VPORT_YSCALE_0] = fui(state->scale[1]);
352 rstate->states[EG_VIEWPORT__PA_CL_VPORT_ZSCALE_0] = fui(state->scale[2]);
353 rstate->states[EG_VIEWPORT__PA_CL_VPORT_XOFFSET_0] = fui(state->translate[0]);
354 rstate->states[EG_VIEWPORT__PA_CL_VPORT_YOFFSET_0] = fui(state->translate[1]);
355 rstate->states[EG_VIEWPORT__PA_CL_VPORT_ZOFFSET_0] = fui(state->translate[2]);
356 rstate->states[EG_VIEWPORT__PA_CL_VTE_CNTL] = 0x0000043F;
357 radeon_state_pm4(rstate);
358 }
359
360 static void eg_dsa(struct r600_context *rctx, struct radeon_state *rstate)
361 {
362 const struct pipe_depth_stencil_alpha_state *state = &rctx->dsa->state.dsa;
363 const struct pipe_stencil_ref *stencil_ref = &rctx->stencil_ref->state.stencil_ref;
364 struct r600_screen *rscreen = rctx->screen;
365 unsigned db_depth_control, alpha_test_control, alpha_ref, db_shader_control;
366 unsigned stencil_ref_mask, stencil_ref_mask_bf, db_render_override, db_render_control;
367 unsigned db_count_control = 0;
368 struct r600_shader *rshader;
369 struct r600_query *rquery = NULL;
370 boolean query_running;
371 int i;
372
373 if (rctx->ps_shader == NULL) {
374 return;
375 }
376 radeon_state_init(rstate, rscreen->rw, R600_STATE_DSA, 0, 0);
377
378 db_shader_control = 0;
379 db_shader_control |= S_02880C_DUAL_EXPORT_ENABLE(1);
380 db_shader_control |= S_02880C_Z_ORDER(V_02880C_EARLY_Z_THEN_LATE_Z);
381
382 rshader = &rctx->ps_shader->shader;
383 if (rshader->uses_kill)
384 db_shader_control |= S_02880C_KILL_ENABLE(1);
385 for (i = 0; i < rshader->noutput; i++) {
386 if (rshader->output[i].name == TGSI_SEMANTIC_POSITION)
387 db_shader_control |= S_02880C_Z_EXPORT_ENABLE(1);
388 }
389 stencil_ref_mask = 0;
390 stencil_ref_mask_bf = 0;
391 db_depth_control = S_028800_Z_ENABLE(state->depth.enabled) |
392 S_028800_Z_WRITE_ENABLE(state->depth.writemask) |
393 S_028800_ZFUNC(state->depth.func);
394 /* set stencil enable */
395
396 if (state->stencil[0].enabled) {
397 db_depth_control |= S_028800_STENCIL_ENABLE(1);
398 db_depth_control |= S_028800_STENCILFUNC(r600_translate_ds_func(state->stencil[0].func));
399 db_depth_control |= S_028800_STENCILFAIL(r600_translate_stencil_op(state->stencil[0].fail_op));
400 db_depth_control |= S_028800_STENCILZPASS(r600_translate_stencil_op(state->stencil[0].zpass_op));
401 db_depth_control |= S_028800_STENCILZFAIL(r600_translate_stencil_op(state->stencil[0].zfail_op));
402
403 stencil_ref_mask = S_028430_STENCILMASK(state->stencil[0].valuemask) |
404 S_028430_STENCILWRITEMASK(state->stencil[0].writemask);
405 stencil_ref_mask |= S_028430_STENCILREF(stencil_ref->ref_value[0]);
406 if (state->stencil[1].enabled) {
407 db_depth_control |= S_028800_BACKFACE_ENABLE(1);
408 db_depth_control |= S_028800_STENCILFUNC_BF(r600_translate_ds_func(state->stencil[1].func));
409 db_depth_control |= S_028800_STENCILFAIL_BF(r600_translate_stencil_op(state->stencil[1].fail_op));
410 db_depth_control |= S_028800_STENCILZPASS_BF(r600_translate_stencil_op(state->stencil[1].zpass_op));
411 db_depth_control |= S_028800_STENCILZFAIL_BF(r600_translate_stencil_op(state->stencil[1].zfail_op));
412 stencil_ref_mask_bf = S_028434_STENCILMASK_BF(state->stencil[1].valuemask) |
413 S_028434_STENCILWRITEMASK_BF(state->stencil[1].writemask);
414 stencil_ref_mask_bf |= S_028430_STENCILREF(stencil_ref->ref_value[1]);
415 }
416 }
417
418 alpha_test_control = 0;
419 alpha_ref = 0;
420 if (state->alpha.enabled) {
421 alpha_test_control = S_028410_ALPHA_FUNC(state->alpha.func);
422 alpha_test_control |= S_028410_ALPHA_TEST_ENABLE(1);
423 alpha_ref = fui(state->alpha.ref_value);
424 }
425
426 db_render_control = 0;
427 /// db_render_control = S_028D0C_STENCIL_COMPRESS_DISABLE(1) |
428 /// S_028D0C_DEPTH_COMPRESS_DISABLE(1);
429 db_render_override = S_02800C_FORCE_HIZ_ENABLE(V_02800C_FORCE_DISABLE) |
430 S_02800C_FORCE_HIS_ENABLE0(V_02800C_FORCE_DISABLE) |
431 S_02800C_FORCE_HIS_ENABLE1(V_02800C_FORCE_DISABLE);
432
433 query_running = FALSE;
434
435 LIST_FOR_EACH_ENTRY(rquery, &rctx->query_list, list) {
436 if (rquery->state & R600_QUERY_STATE_STARTED) {
437 query_running = TRUE;
438 }
439 }
440
441 if (query_running) {
442 db_render_override |= S_02800C_NOOP_CULL_DISABLE(1);
443 db_count_control |= S_028004_PERFECT_ZPASS_COUNTS(1);
444 }
445
446 rstate->states[EG_DSA__DB_STENCIL_CLEAR] = 0x00000000;
447 rstate->states[EG_DSA__DB_DEPTH_CLEAR] = 0x3F800000;
448 rstate->states[EG_DSA__SX_ALPHA_TEST_CONTROL] = alpha_test_control;
449 rstate->states[EG_DSA__DB_STENCILREFMASK] = stencil_ref_mask;
450 rstate->states[EG_DSA__DB_STENCILREFMASK_BF] = stencil_ref_mask_bf;
451 rstate->states[EG_DSA__SX_ALPHA_REF] = alpha_ref;
452 // rstate->states[EG_DSA__SPI_FOG_FUNC_SCALE] = 0x00000000;
453 // rstate->states[EG_DSA__SPI_FOG_FUNC_BIAS] = 0x00000000;
454 rstate->states[EG_DSA__SPI_FOG_CNTL] = 0x00000000;
455 rstate->states[EG_DSA__DB_DEPTH_CONTROL] = db_depth_control;
456 rstate->states[EG_DSA__DB_SHADER_CONTROL] = db_shader_control;
457 rstate->states[EG_DSA__DB_RENDER_CONTROL] = db_render_control;
458 rstate->states[EG_DSA__DB_RENDER_OVERRIDE] = db_render_override;
459 rstate->states[EG_DSA__DB_COUNT_CONTROL] = db_count_control;
460 rstate->states[EG_DSA__DB_SRESULTS_COMPARE_STATE1] = 0x00000000;
461 rstate->states[EG_DSA__DB_PRELOAD_CONTROL] = 0x00000000;
462 rstate->states[EG_DSA__DB_ALPHA_TO_MASK] = 0x0000AA00;
463 radeon_state_pm4(rstate);
464 }
465
466
467 static INLINE u32 S_FIXED(float value, u32 frac_bits)
468 {
469 return value * (1 << frac_bits);
470 }
471
472 static void eg_sampler_border(struct r600_context *rctx, struct radeon_state *rstate,
473 const struct pipe_sampler_state *state, unsigned id)
474 {
475 struct r600_screen *rscreen = rctx->screen;
476 union util_color uc;
477
478 util_pack_color(state->border_color, PIPE_FORMAT_B8G8R8A8_UNORM, &uc);
479
480 radeon_state_init(rstate, rscreen->rw, R600_STATE_SAMPLER_BORDER, id, R600_SHADER_PS);
481 if (uc.ui) {
482 rstate->states[EG_PS_SAMPLER_BORDER__TD_PS_SAMPLER0_BORDER_INDEX] = id;
483 rstate->states[EG_PS_SAMPLER_BORDER__TD_PS_SAMPLER0_BORDER_RED] = fui(state->border_color[0]);
484 rstate->states[EG_PS_SAMPLER_BORDER__TD_PS_SAMPLER0_BORDER_GREEN] = fui(state->border_color[1]);
485 rstate->states[EG_PS_SAMPLER_BORDER__TD_PS_SAMPLER0_BORDER_BLUE] = fui(state->border_color[2]);
486 rstate->states[EG_PS_SAMPLER_BORDER__TD_PS_SAMPLER0_BORDER_ALPHA] = fui(state->border_color[3]);
487 }
488 radeon_state_pm4(rstate);
489 }
490
491 static void eg_sampler(struct r600_context *rctx, struct radeon_state *rstate,
492 const struct pipe_sampler_state *state, unsigned id)
493 {
494 struct r600_screen *rscreen = rctx->screen;
495 union util_color uc;
496
497 util_pack_color(state->border_color, PIPE_FORMAT_B8G8R8A8_UNORM, &uc);
498
499 radeon_state_init(rstate, rscreen->rw, R600_STATE_SAMPLER, id, R600_SHADER_PS);
500 rstate->states[EG_PS_SAMPLER__SQ_TEX_SAMPLER_WORD0_0] =
501 S_03C000_CLAMP_X(r600_tex_wrap(state->wrap_s)) |
502 S_03C000_CLAMP_Y(r600_tex_wrap(state->wrap_t)) |
503 S_03C000_CLAMP_Z(r600_tex_wrap(state->wrap_r)) |
504 S_03C000_XY_MAG_FILTER(r600_tex_filter(state->mag_img_filter)) |
505 S_03C000_XY_MIN_FILTER(r600_tex_filter(state->min_img_filter)) |
506 S_03C000_MIP_FILTER(r600_tex_mipfilter(state->min_mip_filter)) |
507 S_03C000_DEPTH_COMPARE_FUNCTION(r600_tex_compare(state->compare_func)) |
508 S_03C000_BORDER_COLOR_TYPE(uc.ui ? V_03C000_SQ_TEX_BORDER_COLOR_REGISTER : 0);
509 /* FIXME LOD it depends on texture base level ... */
510 rstate->states[EG_PS_SAMPLER__SQ_TEX_SAMPLER_WORD1_0] =
511 S_03C004_MIN_LOD(S_FIXED(CLAMP(state->min_lod, 0, 15), 6)) |
512 S_03C004_MAX_LOD(S_FIXED(CLAMP(state->max_lod, 0, 15), 6));
513
514 rstate->states[EG_PS_SAMPLER__SQ_TEX_SAMPLER_WORD2_0] =
515 S_03C008_LOD_BIAS(S_FIXED(CLAMP(state->lod_bias, -16, 16), 6)) |
516 S_03C008_TYPE(1);
517 radeon_state_pm4(rstate);
518
519 }
520
521
522 static void eg_resource(struct pipe_context *ctx, struct radeon_state *rstate,
523 const struct pipe_sampler_view *view, unsigned id)
524 {
525 struct r600_context *rctx = r600_context(ctx);
526 struct r600_screen *rscreen = rctx->screen;
527 const struct util_format_description *desc;
528 struct r600_resource_texture *tmp;
529 struct r600_resource *rbuffer;
530 unsigned format;
531 uint32_t word4 = 0, yuv_format = 0, pitch = 0;
532 unsigned char swizzle[4];
533
534 rstate->cpm4 = 0;
535 swizzle[0] = view->swizzle_r;
536 swizzle[1] = view->swizzle_g;
537 swizzle[2] = view->swizzle_b;
538 swizzle[3] = view->swizzle_a;
539 format = r600_translate_texformat(view->texture->format,
540 swizzle,
541 &word4, &yuv_format);
542 if (format == ~0) {
543 return;
544 }
545 desc = util_format_description(view->texture->format);
546 if (desc == NULL) {
547 R600_ERR("unknow format %d\n", view->texture->format);
548 return;
549 }
550 radeon_state_init(rstate, rscreen->rw, R600_STATE_RESOURCE, id, R600_SHADER_PS);
551 tmp = (struct r600_resource_texture*)view->texture;
552 rbuffer = &tmp->resource;
553 radeon_ws_bo_reference(rscreen->rw, &rstate->bo[0], rbuffer->bo);
554 radeon_ws_bo_reference(rscreen->rw, &rstate->bo[1], rbuffer->bo);
555
556 rstate->nbo = 2;
557 rstate->placement[0] = RADEON_GEM_DOMAIN_GTT;
558 rstate->placement[1] = RADEON_GEM_DOMAIN_GTT;
559 rstate->placement[2] = RADEON_GEM_DOMAIN_GTT;
560 rstate->placement[3] = RADEON_GEM_DOMAIN_GTT;
561
562 pitch = align(tmp->pitch[0] / tmp->bpt, 8);
563
564 /* FIXME properly handle first level != 0 */
565 rstate->states[EG_PS_RESOURCE__RESOURCE0_WORD0] =
566 S_030000_DIM(r600_tex_dim(view->texture->target)) |
567 S_030000_PITCH((pitch / 8) - 1) |
568 S_030000_TEX_WIDTH(view->texture->width0 - 1);
569 rstate->states[EG_PS_RESOURCE__RESOURCE0_WORD1] =
570 S_030004_TEX_HEIGHT(view->texture->height0 - 1) |
571 S_030004_TEX_DEPTH(view->texture->depth0 - 1);
572 rstate->states[EG_PS_RESOURCE__RESOURCE0_WORD2] = tmp->offset[0] >> 8;
573 rstate->states[EG_PS_RESOURCE__RESOURCE0_WORD3] = tmp->offset[1] >> 8;
574 rstate->states[EG_PS_RESOURCE__RESOURCE0_WORD4] =
575 word4 |
576 S_030010_NUM_FORMAT_ALL(V_030010_SQ_NUM_FORMAT_NORM) |
577 S_030010_SRF_MODE_ALL(V_030010_SFR_MODE_NO_ZERO) |
578 S_030010_REQUEST_SIZE(1) |
579 S_030010_BASE_LEVEL(view->first_level);
580 rstate->states[EG_PS_RESOURCE__RESOURCE0_WORD5] =
581 S_030014_LAST_LEVEL(view->last_level) |
582 S_030014_BASE_ARRAY(0) |
583 S_030014_LAST_ARRAY(0);
584 rstate->states[EG_PS_RESOURCE__RESOURCE0_WORD6] = 0;
585 rstate->states[EG_PS_RESOURCE__RESOURCE0_WORD7] =
586 S_03001C_DATA_FORMAT(format) |
587 S_03001C_TYPE(V_03001C_SQ_TEX_VTX_VALID_TEXTURE);
588 radeon_state_pm4(rstate);
589 }
590
591 static void eg_cb_cntl(struct r600_context *rctx, struct radeon_state *rstate)
592 {
593 struct r600_screen *rscreen = rctx->screen;
594 const struct pipe_blend_state *pbs = &rctx->blend->state.blend;
595 int nr_cbufs = rctx->framebuffer->state.framebuffer.nr_cbufs;
596 uint32_t color_control, target_mask, shader_mask;
597 int i;
598
599 target_mask = 0;
600 shader_mask = 0;
601 color_control = S_028808_MODE(1);
602
603 for (i = 0; i < nr_cbufs; i++) {
604 shader_mask |= 0xf << (i * 4);
605 }
606
607 if (pbs->logicop_enable) {
608 color_control |= (pbs->logicop_func << 16) | (pbs->logicop_func << 20);
609 } else {
610 color_control |= (0xcc << 16);
611 }
612
613 if (pbs->independent_blend_enable) {
614 for (i = 0; i < nr_cbufs; i++) {
615 target_mask |= (pbs->rt[i].colormask << (4 * i));
616 }
617 } else {
618 for (i = 0; i < nr_cbufs; i++) {
619 target_mask |= (pbs->rt[0].colormask << (4 * i));
620 }
621 }
622 radeon_state_init(rstate, rscreen->rw, R600_STATE_CB_CNTL, 0, 0);
623 rstate->states[EG_CB_CNTL__CB_SHADER_MASK] = shader_mask;
624 rstate->states[EG_CB_CNTL__CB_TARGET_MASK] = target_mask;
625 rstate->states[EG_CB_CNTL__CB_COLOR_CONTROL] = color_control;
626 rstate->states[EG_CB_CNTL__PA_SC_AA_CONFIG] = 0x00000000;
627 rstate->states[EG_CB_CNTL__PA_SC_AA_SAMPLE_LOCS_MCTX] = 0x00000000;
628 rstate->states[EG_CB_CNTL__PA_SC_AA_MASK] = 0xFFFFFFFF;
629 radeon_state_pm4(rstate);
630 }
631
632
633 static void eg_init_config(struct r600_context *rctx)
634 {
635 int ps_prio;
636 int vs_prio;
637 int gs_prio;
638 int es_prio;
639 int hs_prio, cs_prio, ls_prio;
640 int num_ps_gprs;
641 int num_vs_gprs;
642 int num_gs_gprs;
643 int num_es_gprs;
644 int num_hs_gprs;
645 int num_ls_gprs;
646 int num_temp_gprs;
647 int num_ps_threads;
648 int num_vs_threads;
649 int num_gs_threads;
650 int num_es_threads;
651 int num_hs_threads;
652 int num_ls_threads;
653 int num_ps_stack_entries;
654 int num_vs_stack_entries;
655 int num_gs_stack_entries;
656 int num_es_stack_entries;
657 int num_hs_stack_entries;
658 int num_ls_stack_entries;
659 enum radeon_family family;
660
661 family = radeon_get_family(rctx->rw);
662 ps_prio = 0;
663 vs_prio = 1;
664 gs_prio = 2;
665 es_prio = 3;
666 hs_prio = 0;
667 ls_prio = 0;
668 cs_prio = 0;
669
670 switch (family) {
671 case CHIP_CEDAR:
672 default:
673 num_ps_gprs = 93;
674 num_vs_gprs = 46;
675 num_temp_gprs = 4;
676 num_gs_gprs = 31;
677 num_es_gprs = 31;
678 num_hs_gprs = 23;
679 num_ls_gprs = 23;
680 num_ps_threads = 96;
681 num_vs_threads = 16;
682 num_gs_threads = 16;
683 num_es_threads = 16;
684 num_hs_threads = 16;
685 num_ls_threads = 16;
686 num_ps_stack_entries = 42;
687 num_vs_stack_entries = 42;
688 num_gs_stack_entries = 42;
689 num_es_stack_entries = 42;
690 num_hs_stack_entries = 42;
691 num_ls_stack_entries = 42;
692 break;
693 case CHIP_REDWOOD:
694 num_ps_gprs = 93;
695 num_vs_gprs = 46;
696 num_temp_gprs = 4;
697 num_gs_gprs = 31;
698 num_es_gprs = 31;
699 num_hs_gprs = 23;
700 num_ls_gprs = 23;
701 num_ps_threads = 128;
702 num_vs_threads = 20;
703 num_gs_threads = 20;
704 num_es_threads = 20;
705 num_hs_threads = 20;
706 num_ls_threads = 20;
707 num_ps_stack_entries = 42;
708 num_vs_stack_entries = 42;
709 num_gs_stack_entries = 42;
710 num_es_stack_entries = 42;
711 num_hs_stack_entries = 42;
712 num_ls_stack_entries = 42;
713 break;
714 case CHIP_JUNIPER:
715 num_ps_gprs = 93;
716 num_vs_gprs = 46;
717 num_temp_gprs = 4;
718 num_gs_gprs = 31;
719 num_es_gprs = 31;
720 num_hs_gprs = 23;
721 num_ls_gprs = 23;
722 num_ps_threads = 128;
723 num_vs_threads = 20;
724 num_gs_threads = 20;
725 num_es_threads = 20;
726 num_hs_threads = 20;
727 num_ls_threads = 20;
728 num_ps_stack_entries = 85;
729 num_vs_stack_entries = 85;
730 num_gs_stack_entries = 85;
731 num_es_stack_entries = 85;
732 num_hs_stack_entries = 85;
733 num_ls_stack_entries = 85;
734 break;
735 case CHIP_CYPRESS:
736 case CHIP_HEMLOCK:
737 num_ps_gprs = 93;
738 num_vs_gprs = 46;
739 num_temp_gprs = 4;
740 num_gs_gprs = 31;
741 num_es_gprs = 31;
742 num_hs_gprs = 23;
743 num_ls_gprs = 23;
744 num_ps_threads = 128;
745 num_vs_threads = 20;
746 num_gs_threads = 20;
747 num_es_threads = 20;
748 num_hs_threads = 20;
749 num_ls_threads = 20;
750 num_ps_stack_entries = 85;
751 num_vs_stack_entries = 85;
752 num_gs_stack_entries = 85;
753 num_es_stack_entries = 85;
754 num_hs_stack_entries = 85;
755 num_ls_stack_entries = 85;
756 break;
757 }
758
759 radeon_state_init(&rctx->config, rctx->rw, R600_STATE_CONFIG, 0, 0);
760
761 rctx->config.states[EG_CONFIG__SQ_CONFIG] = 0x00000000;
762 switch (family) {
763 case CHIP_CEDAR:
764 break;
765 default:
766 rctx->config.states[EG_CONFIG__SQ_CONFIG] |= S_008C00_VC_ENABLE(1);
767 break;
768 }
769 rctx->config.states[EG_CONFIG__SQ_CONFIG] |= S_008C00_EXPORT_SRC_C(1);
770 rctx->config.states[EG_CONFIG__SQ_CONFIG] |= S_008C00_CS_PRIO(cs_prio);
771 rctx->config.states[EG_CONFIG__SQ_CONFIG] |= S_008C00_LS_PRIO(ls_prio);
772 rctx->config.states[EG_CONFIG__SQ_CONFIG] |= S_008C00_HS_PRIO(hs_prio);
773 rctx->config.states[EG_CONFIG__SQ_CONFIG] |= S_008C00_PS_PRIO(ps_prio);
774 rctx->config.states[EG_CONFIG__SQ_CONFIG] |= S_008C00_VS_PRIO(vs_prio);
775 rctx->config.states[EG_CONFIG__SQ_CONFIG] |= S_008C00_GS_PRIO(gs_prio);
776 rctx->config.states[EG_CONFIG__SQ_CONFIG] |= S_008C00_ES_PRIO(es_prio);
777
778 rctx->config.states[EG_CONFIG__SQ_GPR_RESOURCE_MGMT_1] = 0;
779 rctx->config.states[EG_CONFIG__SQ_GPR_RESOURCE_MGMT_1] |= S_008C04_NUM_PS_GPRS(num_ps_gprs);
780 rctx->config.states[EG_CONFIG__SQ_GPR_RESOURCE_MGMT_1] |= S_008C04_NUM_VS_GPRS(num_vs_gprs);
781 rctx->config.states[EG_CONFIG__SQ_GPR_RESOURCE_MGMT_1] |= S_008C04_NUM_CLAUSE_TEMP_GPRS(num_temp_gprs);
782
783 rctx->config.states[EG_CONFIG__SQ_GPR_RESOURCE_MGMT_2] = 0;
784 rctx->config.states[EG_CONFIG__SQ_GPR_RESOURCE_MGMT_2] |= S_008C08_NUM_GS_GPRS(num_gs_gprs);
785 rctx->config.states[EG_CONFIG__SQ_GPR_RESOURCE_MGMT_2] |= S_008C08_NUM_ES_GPRS(num_es_gprs);
786
787 rctx->config.states[EG_CONFIG__SQ_GPR_RESOURCE_MGMT_3] = 0;
788 rctx->config.states[EG_CONFIG__SQ_GPR_RESOURCE_MGMT_3] |= S_008C0C_NUM_HS_GPRS(num_hs_gprs);
789 rctx->config.states[EG_CONFIG__SQ_GPR_RESOURCE_MGMT_3] |= S_008C0C_NUM_LS_GPRS(num_ls_gprs);
790
791 rctx->config.states[EG_CONFIG__SQ_THREAD_RESOURCE_MGMT_1] = 0;
792 rctx->config.states[EG_CONFIG__SQ_THREAD_RESOURCE_MGMT_1] |= S_008C18_NUM_PS_THREADS(num_ps_threads);
793 rctx->config.states[EG_CONFIG__SQ_THREAD_RESOURCE_MGMT_1] |= S_008C18_NUM_VS_THREADS(num_vs_threads);
794 rctx->config.states[EG_CONFIG__SQ_THREAD_RESOURCE_MGMT_1] |= S_008C18_NUM_GS_THREADS(num_gs_threads);
795 rctx->config.states[EG_CONFIG__SQ_THREAD_RESOURCE_MGMT_1] |= S_008C18_NUM_ES_THREADS(num_es_threads);
796
797 rctx->config.states[EG_CONFIG__SQ_THREAD_RESOURCE_MGMT_2] = 0;
798 rctx->config.states[EG_CONFIG__SQ_THREAD_RESOURCE_MGMT_2] |= S_008C1C_NUM_HS_THREADS(num_hs_threads);
799 rctx->config.states[EG_CONFIG__SQ_THREAD_RESOURCE_MGMT_2] |= S_008C1C_NUM_LS_THREADS(num_ls_threads);
800
801 rctx->config.states[EG_CONFIG__SQ_STACK_RESOURCE_MGMT_1] = 0;
802 rctx->config.states[EG_CONFIG__SQ_STACK_RESOURCE_MGMT_1] |= S_008C20_NUM_PS_STACK_ENTRIES(num_ps_stack_entries);
803 rctx->config.states[EG_CONFIG__SQ_STACK_RESOURCE_MGMT_1] |= S_008C20_NUM_VS_STACK_ENTRIES(num_vs_stack_entries);
804
805 rctx->config.states[EG_CONFIG__SQ_STACK_RESOURCE_MGMT_2] = 0;
806 rctx->config.states[EG_CONFIG__SQ_STACK_RESOURCE_MGMT_2] |= S_008C24_NUM_GS_STACK_ENTRIES(num_gs_stack_entries);
807 rctx->config.states[EG_CONFIG__SQ_STACK_RESOURCE_MGMT_2] |= S_008C24_NUM_ES_STACK_ENTRIES(num_es_stack_entries);
808
809 rctx->config.states[EG_CONFIG__SQ_STACK_RESOURCE_MGMT_3] = 0;
810 rctx->config.states[EG_CONFIG__SQ_STACK_RESOURCE_MGMT_3] |= S_008C28_NUM_HS_STACK_ENTRIES(num_hs_stack_entries);
811 rctx->config.states[EG_CONFIG__SQ_STACK_RESOURCE_MGMT_3] |= S_008C28_NUM_LS_STACK_ENTRIES(num_ls_stack_entries);
812
813 rctx->config.states[EG_CONFIG__SPI_CONFIG_CNTL] = 0x00000000;
814 rctx->config.states[EG_CONFIG__SPI_CONFIG_CNTL_1] = S_00913C_VTX_DONE_DELAY(4);
815
816 rctx->config.states[EG_CONFIG__SX_MISC] = 0x00000000;
817
818 rctx->config.states[EG_CONFIG__SQ_DYN_GPR_CNTL_PS_FLUSH_REQ] = 0x00000000;
819 rctx->config.states[EG_CONFIG__PA_SC_MODE_CNTL_0] = 0x0;
820 rctx->config.states[EG_CONFIG__PA_SC_MODE_CNTL_1] = 0x0;
821
822 rctx->config.states[EG_CONFIG__SQ_ESGS_RING_ITEMSIZE] = 0x00000000;
823 rctx->config.states[EG_CONFIG__SQ_GSVS_RING_ITEMSIZE] = 0x00000000;
824 rctx->config.states[EG_CONFIG__SQ_ESTMP_RING_ITEMSIZE] = 0x00000000;
825 rctx->config.states[EG_CONFIG__SQ_GSTMP_RING_ITEMSIZE] = 0x00000000;
826 rctx->config.states[EG_CONFIG__SQ_VSTMP_RING_ITEMSIZE] = 0x00000000;
827 rctx->config.states[EG_CONFIG__SQ_PSTMP_RING_ITEMSIZE] = 0x00000000;
828
829 rctx->config.states[EG_CONFIG__SQ_GS_VERT_ITEMSIZE] = 0x00000000;
830 rctx->config.states[EG_CONFIG__SQ_GS_VERT_ITEMSIZE_1] = 0x00000000;
831 rctx->config.states[EG_CONFIG__SQ_GS_VERT_ITEMSIZE_2] = 0x00000000;
832 rctx->config.states[EG_CONFIG__SQ_GS_VERT_ITEMSIZE_3] = 0x00000000;
833
834 rctx->config.states[EG_CONFIG__VGT_OUTPUT_PATH_CNTL] = 0x00000000;
835 rctx->config.states[EG_CONFIG__VGT_HOS_CNTL] = 0x00000000;
836 rctx->config.states[EG_CONFIG__VGT_HOS_MAX_TESS_LEVEL] = 0x00000000;
837 rctx->config.states[EG_CONFIG__VGT_HOS_MIN_TESS_LEVEL] = 0x00000000;
838 rctx->config.states[EG_CONFIG__VGT_HOS_REUSE_DEPTH] = 0x00000000;
839 rctx->config.states[EG_CONFIG__VGT_GROUP_PRIM_TYPE] = 0x00000000;
840 rctx->config.states[EG_CONFIG__VGT_GROUP_FIRST_DECR] = 0x00000000;
841 rctx->config.states[EG_CONFIG__VGT_GROUP_DECR] = 0x00000000;
842 rctx->config.states[EG_CONFIG__VGT_GROUP_VECT_0_CNTL] = 0x00000000;
843 rctx->config.states[EG_CONFIG__VGT_GROUP_VECT_1_CNTL] = 0x00000000;
844 rctx->config.states[EG_CONFIG__VGT_GROUP_VECT_0_FMT_CNTL] = 0x00000000;
845 rctx->config.states[EG_CONFIG__VGT_GROUP_VECT_1_FMT_CNTL] = 0x00000000;
846 rctx->config.states[EG_CONFIG__VGT_GS_MODE] = 0x00000000;
847 rctx->config.states[EG_CONFIG__VGT_STRMOUT_CONFIG] = 0x00000000;
848 rctx->config.states[EG_CONFIG__VGT_STRMOUT_BUFFER_CONFIG] = 0x00000000;
849 rctx->config.states[EG_CONFIG__VGT_REUSE_OFF] = 0x00000001;
850 rctx->config.states[EG_CONFIG__VGT_VTX_CNT_EN] = 0x00000000;
851 // rctx->config.states[EG_CONFIG__VGT_CACHE_INVALIDATION] = 0x2;
852 // rctx->config.states[EG_CONFIG__VGT_GS_VERTEX_REUSE] = 0x16;
853 rctx->config.states[EG_CONFIG__PA_CL_ENHANCE] = (3 << 1) | 1;
854
855 radeon_state_pm4(&rctx->config);
856 }
857
858 static int eg_vs_resource(struct r600_context *rctx, int id, struct r600_resource *rbuffer, uint32_t offset,
859 uint32_t stride, uint32_t src_format)
860 {
861 struct radeon_state *vs_resource = &rctx->vs_resource[id];
862 struct r600_screen *rscreen = rctx->screen;
863 unsigned format, num_format = 0, format_comp = 0;
864
865 format = r600_translate_colorformat(src_format);
866
867 r600_translate_vertex_num_format(src_format, &num_format, &format_comp);
868 format = S_030008_DATA_FORMAT(format) | S_030008_NUM_FORMAT_ALL(num_format) |
869 S_030008_FORMAT_COMP_ALL(format_comp);
870
871 radeon_state_init(vs_resource, rscreen->rw, R600_STATE_RESOURCE, id, R600_SHADER_VS);
872
873 radeon_ws_bo_reference(rscreen->rw, &vs_resource->bo[0], rbuffer->bo);
874 vs_resource->nbo = 1;
875 vs_resource->states[EG_PS_RESOURCE__RESOURCE0_WORD0] = offset;
876 vs_resource->states[EG_PS_RESOURCE__RESOURCE0_WORD1] = rbuffer->size - offset - 1;
877 vs_resource->states[EG_PS_RESOURCE__RESOURCE0_WORD2] = S_030008_STRIDE(stride) | format;
878 vs_resource->states[EG_PS_RESOURCE__RESOURCE0_WORD3] = S_03000C_DST_SEL_X(V_03000C_SQ_SEL_X) |
879 S_03000C_DST_SEL_Y(V_03000C_SQ_SEL_Y) |
880 S_03000C_DST_SEL_Z(V_03000C_SQ_SEL_Z) |
881 S_03000C_DST_SEL_W(V_03000C_SQ_SEL_W);
882
883 vs_resource->states[EG_PS_RESOURCE__RESOURCE0_WORD4] = 0x00000000;
884 vs_resource->states[EG_PS_RESOURCE__RESOURCE0_WORD5] = 0x00000000;
885 vs_resource->states[EG_PS_RESOURCE__RESOURCE0_WORD6] = 0x00000000;
886 vs_resource->states[EG_PS_RESOURCE__RESOURCE0_WORD7] = 0xC0000000;
887 vs_resource->placement[0] = RADEON_GEM_DOMAIN_GTT;
888 vs_resource->placement[1] = RADEON_GEM_DOMAIN_GTT;
889 return radeon_state_pm4(vs_resource);
890 }
891
892 static int eg_draw_vgt_init(struct r600_draw *draw,
893 int vgt_draw_initiator)
894 {
895 struct r600_context *rctx = r600_context(draw->ctx);
896 struct r600_screen *rscreen = rctx->screen;
897 struct r600_resource *rbuffer = (struct r600_resource *)draw->index_buffer;
898 radeon_state_init(&draw->draw, rscreen->rw, R600_STATE_DRAW, 0, 0);
899 draw->draw.states[EG_DRAW__VGT_NUM_INDICES] = draw->count;
900 draw->draw.states[EG_DRAW__VGT_DRAW_INITIATOR] = vgt_draw_initiator;
901 draw->draw.states[EG_DRAW__VGT_DMA_BASE] = draw->index_buffer_offset;
902 if (rbuffer) {
903 radeon_ws_bo_reference(rscreen->rw, &draw->draw.bo[0], rbuffer->bo);
904 draw->draw.placement[0] = RADEON_GEM_DOMAIN_GTT;
905 draw->draw.placement[1] = RADEON_GEM_DOMAIN_GTT;
906 draw->draw.nbo = 1;
907 }
908 return radeon_state_pm4(&draw->draw);
909 }
910
911 static int eg_draw_vgt_prim(struct r600_draw *draw,
912 uint32_t prim, uint32_t vgt_dma_index_type)
913 {
914 struct r600_context *rctx = r600_context(draw->ctx);
915 struct r600_screen *rscreen = rctx->screen;
916 radeon_state_init(&draw->vgt, rscreen->rw, R600_STATE_VGT, 0, 0);
917 draw->vgt.states[EG_VGT__VGT_PRIMITIVE_TYPE] = prim;
918 draw->vgt.states[EG_VGT__VGT_MAX_VTX_INDX] = draw->max_index;
919 draw->vgt.states[EG_VGT__VGT_MIN_VTX_INDX] = draw->min_index;
920 draw->vgt.states[EG_VGT__VGT_INDX_OFFSET] = draw->index_bias;
921 draw->vgt.states[EG_VGT__VGT_DMA_INDEX_TYPE] = vgt_dma_index_type;
922 draw->vgt.states[EG_VGT__VGT_PRIMITIVEID_EN] = 0x00000000;
923 draw->vgt.states[EG_VGT__VGT_DMA_NUM_INSTANCES] = 0x00000001;
924 draw->vgt.states[EG_VGT__VGT_MULTI_PRIM_IB_RESET_EN] = 0x00000000;
925 draw->vgt.states[EG_VGT__VGT_INSTANCE_STEP_RATE_0] = 0x00000000;
926 draw->vgt.states[EG_VGT__VGT_INSTANCE_STEP_RATE_1] = 0x00000000;
927 return radeon_state_pm4(&draw->vgt);
928 }
929
930
931 static int eg_ps_shader(struct r600_context *rctx, struct r600_context_state *rpshader,
932 struct radeon_state *state)
933 {
934 struct r600_screen *rscreen = rctx->screen;
935 const struct pipe_rasterizer_state *rasterizer;
936 struct r600_shader *rshader = &rpshader->shader;
937 unsigned i, tmp, exports_ps, num_cout;
938 boolean have_pos = FALSE, have_face = FALSE;
939
940 rasterizer = &rctx->rasterizer->state.rasterizer;
941
942 radeon_state_init(state, rscreen->rw, R600_STATE_SHADER, 0, R600_SHADER_PS);
943 for (i = 0; i < rshader->ninput; i++) {
944 tmp = S_028644_SEMANTIC(r600_find_vs_semantic_index(rctx, rshader, i));
945 tmp |= S_028644_SEL_CENTROID(1);
946 if (rshader->input[i].name == TGSI_SEMANTIC_POSITION)
947 have_pos = TRUE;
948 if (rshader->input[i].name == TGSI_SEMANTIC_COLOR ||
949 rshader->input[i].name == TGSI_SEMANTIC_BCOLOR ||
950 rshader->input[i].name == TGSI_SEMANTIC_POSITION) {
951 tmp |= S_028644_FLAT_SHADE(rshader->flat_shade);
952 }
953
954 if (rshader->input[i].name == TGSI_SEMANTIC_FACE)
955 have_face = TRUE;
956
957 if (rasterizer->sprite_coord_enable & (1 << i)) {
958 tmp |= S_028644_PT_SPRITE_TEX(1);
959 }
960 state->states[EG_PS_SHADER__SPI_PS_INPUT_CNTL_0 + i] = tmp;
961 }
962
963 exports_ps = 0;
964 num_cout = 0;
965 for (i = 0; i < rshader->noutput; i++) {
966 if (rshader->output[i].name == TGSI_SEMANTIC_POSITION)
967 exports_ps |= 1;
968 else if (rshader->output[i].name == TGSI_SEMANTIC_COLOR) {
969 num_cout++;
970 }
971 }
972 exports_ps |= (1 << num_cout);
973 if (!exports_ps) {
974 /* always at least export 1 component per pixel */
975 exports_ps = 2;
976 }
977 state->states[EG_PS_SHADER__SPI_PS_IN_CONTROL_0] = S_0286CC_NUM_INTERP(rshader->ninput) |
978 S_0286CC_PERSP_GRADIENT_ENA(1);
979 if (have_pos) {
980 state->states[EG_PS_SHADER__SPI_PS_IN_CONTROL_0] |= S_0286CC_POSITION_ENA(1);
981 state->states[EG_PS_SHADER__SPI_INPUT_Z] |= 1;
982 }
983
984 state->states[EG_PS_SHADER__SPI_PS_IN_CONTROL_1] = 0x00000000;
985 state->states[EG_PS_SHADER__SPI_PS_IN_CONTROL_1] |= S_0286D0_FRONT_FACE_ENA(have_face);
986
987 state->states[EG_PS_SHADER__SQ_PGM_RESOURCES_PS] = S_028844_NUM_GPRS(rshader->bc.ngpr) | S_028844_PRIME_CACHE_ON_DRAW(1) |
988 S_028844_STACK_SIZE(rshader->bc.nstack);
989 state->states[EG_PS_SHADER__SQ_PGM_EXPORTS_PS] = exports_ps;
990 state->states[EG_PS_SHADER__SPI_BARYC_CNTL] = S_0286E0_PERSP_CENTROID_ENA(1) |
991 S_0286E0_LINEAR_CENTROID_ENA(1);
992 radeon_ws_bo_reference(rscreen->rw, &state->bo[0], rpshader->bo);
993 state->nbo = 1;
994 state->placement[0] = RADEON_GEM_DOMAIN_GTT;
995 return radeon_state_pm4(state);
996 }
997
998 static int eg_vs_shader(struct r600_context *rctx, struct r600_context_state *rpshader,
999 struct radeon_state *state)
1000 {
1001 struct r600_screen *rscreen = rctx->screen;
1002 struct r600_shader *rshader = &rpshader->shader;
1003 unsigned i, tmp;
1004
1005 radeon_state_init(state, rscreen->rw, R600_STATE_SHADER, 0, R600_SHADER_VS);
1006 for (i = 0; i < 10; i++) {
1007 state->states[EG_VS_SHADER__SPI_VS_OUT_ID_0 + i] = 0;
1008 }
1009 /* so far never got proper semantic id from tgsi */
1010 for (i = 0; i < 32; i++) {
1011 tmp = i << ((i & 3) * 8);
1012 state->states[EG_VS_SHADER__SPI_VS_OUT_ID_0 + i / 4] |= tmp;
1013 }
1014 state->states[EG_VS_SHADER__SPI_VS_OUT_CONFIG] = S_0286C4_VS_EXPORT_COUNT(rshader->noutput - 2);
1015 state->states[EG_VS_SHADER__SQ_PGM_RESOURCES_VS] = S_028860_NUM_GPRS(rshader->bc.ngpr) |
1016 S_028860_STACK_SIZE(rshader->bc.nstack);
1017 radeon_ws_bo_reference(rscreen->rw, &state->bo[0], rpshader->bo);
1018 radeon_ws_bo_reference(rscreen->rw, &state->bo[1], rpshader->bo);
1019 state->nbo = 2;
1020 state->placement[0] = RADEON_GEM_DOMAIN_GTT;
1021 state->placement[2] = RADEON_GEM_DOMAIN_GTT;
1022 return radeon_state_pm4(state);
1023
1024 }
1025
1026 struct r600_context_hw_state_vtbl eg_hw_state_vtbl = {
1027 .blend = eg_blend,
1028 .ucp = eg_ucp,
1029 .cb = eg_cb,
1030 .db = eg_db,
1031 .rasterizer = eg_rasterizer,
1032 .scissor = eg_scissor,
1033 .viewport = eg_viewport,
1034 .dsa = eg_dsa,
1035 .sampler_border = eg_sampler_border,
1036 .sampler = eg_sampler,
1037 .resource = eg_resource,
1038 .cb_cntl = eg_cb_cntl,
1039 .vs_resource = eg_vs_resource,
1040 .vgt_init = eg_draw_vgt_init,
1041 .vgt_prim = eg_draw_vgt_prim,
1042 .vs_shader = eg_vs_shader,
1043 .ps_shader = eg_ps_shader,
1044 .init_config = eg_init_config,
1045 };
1046
1047 void eg_set_constant_buffer(struct pipe_context *ctx,
1048 uint shader, uint index,
1049 struct pipe_resource *buffer)
1050 {
1051 struct r600_screen *rscreen = r600_screen(ctx->screen);
1052 struct r600_context *rctx = r600_context(ctx);
1053 unsigned nconstant = 0, type, shader_class, size;
1054 struct radeon_state *rstate, *rstates;
1055 struct r600_resource *rbuffer = (struct r600_resource*)buffer;
1056
1057 type = R600_STATE_CBUF;
1058
1059 switch (shader) {
1060 case PIPE_SHADER_VERTEX:
1061 shader_class = R600_SHADER_VS;
1062 rstates = rctx->vs_constant;
1063 break;
1064 case PIPE_SHADER_FRAGMENT:
1065 shader_class = R600_SHADER_PS;
1066 rstates = rctx->ps_constant;
1067 break;
1068 default:
1069 R600_ERR("unsupported %d\n", shader);
1070 return;
1071 }
1072
1073 rstate = &rstates[0];
1074
1075 #define ALIGN_DIVUP(x, y) (((x) + (y) - 1) / (y))
1076 nconstant = buffer->width0 / 16;
1077 size = ALIGN_DIVUP(nconstant, 16);
1078
1079 radeon_state_init(rstate, rscreen->rw, type, 0, shader_class);
1080 rstate->states[EG_VS_CBUF__ALU_CONST_BUFFER_SIZE_VS_0] = size;
1081 rstate->states[EG_VS_CBUF__ALU_CONST_CACHE_VS_0] = 0;
1082
1083 radeon_ws_bo_reference(rscreen->rw, &rstate->bo[0], rbuffer->bo);
1084 rstate->nbo = 1;
1085 rstate->placement[0] = RADEON_GEM_DOMAIN_VRAM;
1086 if (radeon_state_pm4(rstate))
1087 return;
1088 radeon_draw_bind(&rctx->draw, rstate);
1089 }