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r600g: fix evergreen new path
[mesa.git] / src / gallium / drivers / r600 / eg_hw_states.c
1 /*
2 * Copyright 2010 Jerome Glisse <glisse@freedesktop.org>
3 * 2010 Red Hat Inc.
4 *
5 * Permission is hereby granted, free of charge, to any person obtaining a
6 * copy of this software and associated documentation files (the "Software"),
7 * to deal in the Software without restriction, including without limitation
8 * on the rights to use, copy, modify, merge, publish, distribute, sub
9 * license, and/or sell copies of the Software, and to permit persons to whom
10 * the Software is furnished to do so, subject to the following conditions:
11 *
12 * The above copyright notice and this permission notice (including the next
13 * paragraph) shall be included in all copies or substantial portions of the
14 * Software.
15 *
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
19 * THE AUTHOR(S) AND/OR THEIR SUPPLIERS BE LIABLE FOR ANY CLAIM,
20 * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
21 * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
22 * USE OR OTHER DEALINGS IN THE SOFTWARE.
23 *
24 * Authors:
25 * Jerome Glisse
26 * Dave Airlie
27 */
28 #include <util/u_inlines.h>
29 #include <util/u_format.h>
30 #include <util/u_memory.h>
31 #include <util/u_blitter.h>
32 #include "util/u_pack_color.h"
33 #include "r600_screen.h"
34 #include "r600_context.h"
35 #include "r600_resource.h"
36 #include "eg_state_inlines.h"
37 #include "evergreend.h"
38
39 #include "eg_states_inc.h"
40
41 static void eg_blend(struct r600_context *rctx, struct radeon_state *rstate, const struct pipe_blend_state *state)
42 {
43 struct r600_screen *rscreen = rctx->screen;
44 int i;
45
46 radeon_state_init(rstate, rscreen->rw, R600_STATE_BLEND, 0, 0);
47 rstate->states[EG_BLEND__CB_BLEND_RED] = fui(rctx->blend_color.color[0]);
48 rstate->states[EG_BLEND__CB_BLEND_GREEN] = fui(rctx->blend_color.color[1]);
49 rstate->states[EG_BLEND__CB_BLEND_BLUE] = fui(rctx->blend_color.color[2]);
50 rstate->states[EG_BLEND__CB_BLEND_ALPHA] = fui(rctx->blend_color.color[3]);
51 rstate->states[EG_BLEND__CB_BLEND0_CONTROL] = 0x00000000;
52 rstate->states[EG_BLEND__CB_BLEND1_CONTROL] = 0x00000000;
53 rstate->states[EG_BLEND__CB_BLEND2_CONTROL] = 0x00000000;
54 rstate->states[EG_BLEND__CB_BLEND3_CONTROL] = 0x00000000;
55 rstate->states[EG_BLEND__CB_BLEND4_CONTROL] = 0x00000000;
56 rstate->states[EG_BLEND__CB_BLEND5_CONTROL] = 0x00000000;
57 rstate->states[EG_BLEND__CB_BLEND6_CONTROL] = 0x00000000;
58 rstate->states[EG_BLEND__CB_BLEND7_CONTROL] = 0x00000000;
59
60 for (i = 0; i < 8; i++) {
61 unsigned eqRGB = state->rt[i].rgb_func;
62 unsigned srcRGB = state->rt[i].rgb_src_factor;
63 unsigned dstRGB = state->rt[i].rgb_dst_factor;
64
65 unsigned eqA = state->rt[i].alpha_func;
66 unsigned srcA = state->rt[i].alpha_src_factor;
67 unsigned dstA = state->rt[i].alpha_dst_factor;
68 uint32_t bc = 0;
69
70 if (!state->rt[i].blend_enable)
71 continue;
72
73 bc |= S_028780_BLEND_CONTROL_ENABLE(1);
74
75 bc |= S_028780_COLOR_COMB_FCN(r600_translate_blend_function(eqRGB));
76 bc |= S_028780_COLOR_SRCBLEND(r600_translate_blend_factor(srcRGB));
77 bc |= S_028780_COLOR_DESTBLEND(r600_translate_blend_factor(dstRGB));
78
79 if (srcA != srcRGB || dstA != dstRGB || eqA != eqRGB) {
80 bc |= S_028780_SEPARATE_ALPHA_BLEND(1);
81 bc |= S_028780_ALPHA_COMB_FCN(r600_translate_blend_function(eqA));
82 bc |= S_028780_ALPHA_SRCBLEND(r600_translate_blend_factor(srcA));
83 bc |= S_028780_ALPHA_DESTBLEND(r600_translate_blend_factor(dstA));
84 }
85
86 rstate->states[EG_BLEND__CB_BLEND0_CONTROL + i] = bc;
87 }
88
89 radeon_state_pm4(rstate);
90 }
91
92 static void eg_ucp(struct r600_context *rctx, struct radeon_state *rstate,
93 const struct pipe_clip_state *state)
94 {
95 struct r600_screen *rscreen = rctx->screen;
96
97 radeon_state_init(rstate, rscreen->rw, R600_STATE_UCP, 0, 0);
98
99 for (int i = 0; i < state->nr; i++) {
100 rstate->states[i * 4 + 0] = fui(state->ucp[i][0]);
101 rstate->states[i * 4 + 1] = fui(state->ucp[i][1]);
102 rstate->states[i * 4 + 2] = fui(state->ucp[i][2]);
103 rstate->states[i * 4 + 3] = fui(state->ucp[i][3]);
104 }
105 radeon_state_pm4(rstate);
106 }
107
108 static void eg_cb(struct r600_context *rctx, struct radeon_state *rstate,
109 const struct pipe_framebuffer_state *state, int cb)
110 {
111 struct r600_screen *rscreen = rctx->screen;
112 struct r600_resource_texture *rtex;
113 struct r600_resource *rbuffer;
114 unsigned level = state->cbufs[cb]->level;
115 unsigned pitch, slice;
116 unsigned color_info;
117 unsigned format, swap, ntype;
118 const struct util_format_description *desc;
119
120 radeon_state_init(rstate, rscreen->rw, R600_STATE_CB0, cb, 0);
121 rtex = (struct r600_resource_texture*)state->cbufs[cb]->texture;
122 rbuffer = &rtex->resource;
123 radeon_ws_bo_reference(rscreen->rw, &rstate->bo[0], rbuffer->bo);
124 rstate->placement[0] = RADEON_GEM_DOMAIN_VRAM;
125 rstate->nbo = 1;
126 pitch = (rtex->pitch[level] / rtex->bpt) / 8 - 1;
127 slice = (rtex->pitch[level] / rtex->bpt) * state->cbufs[cb]->height / 64 - 1;
128
129 ntype = 0;
130 desc = util_format_description(rtex->resource.base.b.format);
131 if (desc->colorspace == UTIL_FORMAT_COLORSPACE_SRGB)
132 ntype = V_028C70_NUMBER_SRGB;
133
134 format = r600_translate_colorformat(rtex->resource.base.b.format);
135 swap = r600_translate_colorswap(rtex->resource.base.b.format);
136
137 color_info = S_028C70_FORMAT(format) |
138 S_028C70_COMP_SWAP(swap) |
139 S_028C70_BLEND_CLAMP(1) |
140 S_028C70_SOURCE_FORMAT(1) |
141 S_028C70_NUMBER_TYPE(ntype);
142
143 rstate->states[EG_CB__CB_COLOR0_BASE] = state->cbufs[cb]->offset >> 8;
144 rstate->states[EG_CB__CB_COLOR0_INFO] = color_info;
145 rstate->states[EG_CB__CB_COLOR0_PITCH] = S_028C64_PITCH_TILE_MAX(pitch);
146 rstate->states[EG_CB__CB_COLOR0_SLICE] = S_028C68_SLICE_TILE_MAX(slice);
147 rstate->states[EG_CB__CB_COLOR0_VIEW] = 0x00000000;
148 rstate->states[EG_CB__CB_COLOR0_ATTRIB] = S_028C74_NON_DISP_TILING_ORDER(1);
149
150 radeon_state_pm4(rstate);
151 }
152
153 static void eg_db(struct r600_context *rctx, struct radeon_state *rstate,
154 const struct pipe_framebuffer_state *state)
155 {
156 struct r600_screen *rscreen = rctx->screen;
157 struct r600_resource_texture *rtex;
158 struct r600_resource *rbuffer;
159 unsigned level;
160 unsigned pitch, slice, format;
161
162 radeon_state_init(rstate, rscreen->rw, R600_STATE_DB, 0, 0);
163 if (state->zsbuf == NULL)
164 return;
165
166 rtex = (struct r600_resource_texture*)state->zsbuf->texture;
167 rtex->tiled = 1;
168 rtex->array_mode = 2;
169 rtex->tile_type = 1;
170 rtex->depth = 1;
171 rbuffer = &rtex->resource;
172
173 radeon_ws_bo_reference(rscreen->rw, &rstate->bo[0], rbuffer->bo);
174 rstate->nbo = 1;
175 rstate->placement[0] = RADEON_GEM_DOMAIN_VRAM;
176 level = state->zsbuf->level;
177 pitch = (rtex->pitch[level] / rtex->bpt) / 8 - 1;
178 slice = (rtex->pitch[level] / rtex->bpt) * state->zsbuf->height / 64 - 1;
179 format = r600_translate_dbformat(state->zsbuf->texture->format);
180 rstate->states[EG_DB__DB_HTILE_DATA_BASE] = state->zsbuf->offset >> 8;
181 rstate->states[EG_DB__DB_Z_READ_BASE] = state->zsbuf->offset >> 8;
182 rstate->states[EG_DB__DB_Z_WRITE_BASE] = state->zsbuf->offset >> 8;
183 rstate->states[EG_DB__DB_STENCIL_READ_BASE] = state->zsbuf->offset >> 8;
184 rstate->states[EG_DB__DB_STENCIL_WRITE_BASE] = state->zsbuf->offset >> 8;
185 rstate->states[EG_DB__DB_Z_INFO] = S_028040_ARRAY_MODE(rtex->array_mode) | S_028040_FORMAT(format);
186 rstate->states[EG_DB__DB_DEPTH_VIEW] = 0x00000000;
187 rstate->states[EG_DB__DB_DEPTH_SIZE] = S_028058_PITCH_TILE_MAX(pitch);
188 rstate->states[EG_DB__DB_DEPTH_SLICE] = S_02805C_SLICE_TILE_MAX(slice);
189 radeon_state_pm4(rstate);
190 }
191
192 static void eg_rasterizer(struct r600_context *rctx, struct radeon_state *rstate)
193 {
194 const struct pipe_rasterizer_state *state = &rctx->rasterizer->state.rasterizer;
195 const struct pipe_framebuffer_state *fb = &rctx->framebuffer->state.framebuffer;
196 const struct pipe_clip_state *clip = NULL;
197 struct r600_screen *rscreen = rctx->screen;
198 float offset_units = 0, offset_scale = 0;
199 char depth = 0;
200 unsigned offset_db_fmt_cntl = 0;
201 unsigned tmp;
202 unsigned prov_vtx = 1;
203
204 if (rctx->clip)
205 clip = &rctx->clip->state.clip;
206 if (fb->zsbuf) {
207 offset_units = state->offset_units;
208 offset_scale = state->offset_scale * 12.0f;
209 switch (fb->zsbuf->texture->format) {
210 case PIPE_FORMAT_Z24X8_UNORM:
211 case PIPE_FORMAT_Z24_UNORM_S8_USCALED:
212 depth = -24;
213 offset_units *= 2.0f;
214 break;
215 case PIPE_FORMAT_Z32_FLOAT:
216 depth = -23;
217 offset_units *= 1.0f;
218 offset_db_fmt_cntl |= S_028B78_POLY_OFFSET_DB_IS_FLOAT_FMT(1);
219 break;
220 case PIPE_FORMAT_Z16_UNORM:
221 depth = -16;
222 offset_units *= 4.0f;
223 break;
224 default:
225 R600_ERR("unsupported %d\n", fb->zsbuf->texture->format);
226 return;
227 }
228 }
229 offset_db_fmt_cntl |= S_028B78_POLY_OFFSET_NEG_NUM_DB_BITS(depth);
230
231 if (state->flatshade_first)
232 prov_vtx = 0;
233
234 rctx->flat_shade = state->flatshade;
235 radeon_state_init(rstate, rscreen->rw, R600_STATE_RASTERIZER, 0, 0);
236 rstate->states[EG_RASTERIZER__SPI_INTERP_CONTROL_0] = 0x00000000;
237 if (rctx->flat_shade)
238 rstate->states[EG_RASTERIZER__SPI_INTERP_CONTROL_0] |= S_0286D4_FLAT_SHADE_ENA(1);
239 if (state->sprite_coord_enable) {
240 rstate->states[EG_RASTERIZER__SPI_INTERP_CONTROL_0] |=
241 S_0286D4_PNT_SPRITE_ENA(1) |
242 S_0286D4_PNT_SPRITE_OVRD_X(2) |
243 S_0286D4_PNT_SPRITE_OVRD_Y(3) |
244 S_0286D4_PNT_SPRITE_OVRD_Z(0) |
245 S_0286D4_PNT_SPRITE_OVRD_W(1);
246 if (state->sprite_coord_mode != PIPE_SPRITE_COORD_UPPER_LEFT) {
247 rstate->states[EG_RASTERIZER__SPI_INTERP_CONTROL_0] |=
248 S_0286D4_PNT_SPRITE_TOP_1(1);
249 }
250 }
251 rstate->states[EG_RASTERIZER__PA_CL_CLIP_CNTL] = 0;
252 if (clip) {
253 rstate->states[EG_RASTERIZER__PA_CL_CLIP_CNTL] = S_028810_PS_UCP_MODE(3) | ((1 << clip->nr) - 1);
254 rstate->states[EG_RASTERIZER__PA_CL_CLIP_CNTL] |= S_028810_ZCLIP_NEAR_DISABLE(clip->depth_clamp);
255 rstate->states[EG_RASTERIZER__PA_CL_CLIP_CNTL] |= S_028810_ZCLIP_FAR_DISABLE(clip->depth_clamp);
256 }
257 rstate->states[EG_RASTERIZER__PA_SU_SC_MODE_CNTL] =
258 S_028814_PROVOKING_VTX_LAST(prov_vtx) |
259 S_028814_CULL_FRONT((state->cull_face & PIPE_FACE_FRONT) ? 1 : 0) |
260 S_028814_CULL_BACK((state->cull_face & PIPE_FACE_BACK) ? 1 : 0) |
261 S_028814_FACE(!state->front_ccw) |
262 S_028814_POLY_OFFSET_FRONT_ENABLE(state->offset_tri) |
263 S_028814_POLY_OFFSET_BACK_ENABLE(state->offset_tri) |
264 S_028814_POLY_OFFSET_PARA_ENABLE(state->offset_tri);
265 rstate->states[EG_RASTERIZER__PA_CL_VS_OUT_CNTL] =
266 S_02881C_USE_VTX_POINT_SIZE(state->point_size_per_vertex) |
267 S_02881C_VS_OUT_MISC_VEC_ENA(state->point_size_per_vertex);
268 rstate->states[EG_RASTERIZER__PA_CL_NANINF_CNTL] = 0x00000000;
269 /* point size 12.4 fixed point */
270 tmp = (unsigned)(state->point_size * 8.0);
271 rstate->states[EG_RASTERIZER__PA_SU_POINT_SIZE] = S_028A00_HEIGHT(tmp) | S_028A00_WIDTH(tmp);
272 rstate->states[EG_RASTERIZER__PA_SU_POINT_MINMAX] = 0x80000000;
273 rstate->states[EG_RASTERIZER__PA_SU_LINE_CNTL] = 0x00000008;
274 rstate->states[EG_RASTERIZER__PA_SU_VTX_CNTL] = 0x00000005;
275
276 rstate->states[EG_RASTERIZER__PA_SC_MPASS_PS_CNTL] = 0x00000000;
277 rstate->states[EG_RASTERIZER__PA_SC_LINE_CNTL] = 0x00000400;
278 rstate->states[EG_RASTERIZER__PA_CL_GB_VERT_CLIP_ADJ] = 0x3F800000;
279 rstate->states[EG_RASTERIZER__PA_CL_GB_VERT_DISC_ADJ] = 0x3F800000;
280 rstate->states[EG_RASTERIZER__PA_CL_GB_HORZ_CLIP_ADJ] = 0x3F800000;
281 rstate->states[EG_RASTERIZER__PA_CL_GB_HORZ_DISC_ADJ] = 0x3F800000;
282 rstate->states[EG_RASTERIZER__PA_SU_POLY_OFFSET_DB_FMT_CNTL] = offset_db_fmt_cntl;
283 rstate->states[EG_RASTERIZER__PA_SU_POLY_OFFSET_CLAMP] = 0x00000000;
284 rstate->states[EG_RASTERIZER__PA_SU_POLY_OFFSET_FRONT_SCALE] = fui(offset_scale);
285 rstate->states[EG_RASTERIZER__PA_SU_POLY_OFFSET_FRONT_OFFSET] = fui(offset_units);
286 rstate->states[EG_RASTERIZER__PA_SU_POLY_OFFSET_BACK_SCALE] = fui(offset_scale);
287 rstate->states[EG_RASTERIZER__PA_SU_POLY_OFFSET_BACK_OFFSET] = fui(offset_units);
288 radeon_state_pm4(rstate);
289 }
290
291 static void eg_scissor(struct r600_context *rctx, struct radeon_state *rstate)
292 {
293 const struct pipe_scissor_state *state = &rctx->scissor->state.scissor;
294 const struct pipe_framebuffer_state *fb = &rctx->framebuffer->state.framebuffer;
295 struct r600_screen *rscreen = rctx->screen;
296 unsigned minx, maxx, miny, maxy;
297 u32 tl, br;
298
299 if (state == NULL) {
300 minx = 0;
301 miny = 0;
302 maxx = fb->cbufs[0]->width;
303 maxy = fb->cbufs[0]->height;
304 } else {
305 minx = state->minx;
306 miny = state->miny;
307 maxx = state->maxx;
308 maxy = state->maxy;
309 }
310 tl = S_028240_TL_X(minx) | S_028240_TL_Y(miny);
311 br = S_028244_BR_X(maxx) | S_028244_BR_Y(maxy);
312 radeon_state_init(rstate, rscreen->rw, R600_STATE_SCISSOR, 0, 0);
313 /* screen scissor has no WINDOW OFFSET */
314 rstate->states[EG_SCISSOR__PA_SC_SCREEN_SCISSOR_TL] = tl;
315 rstate->states[EG_SCISSOR__PA_SC_SCREEN_SCISSOR_BR] = br;
316 rstate->states[EG_SCISSOR__PA_SC_WINDOW_OFFSET] = 0x00000000;
317 rstate->states[EG_SCISSOR__PA_SC_WINDOW_SCISSOR_TL] = tl | S_028204_WINDOW_OFFSET_DISABLE(1);
318 rstate->states[EG_SCISSOR__PA_SC_WINDOW_SCISSOR_BR] = br;
319 rstate->states[EG_SCISSOR__PA_SC_CLIPRECT_RULE] = 0x0000FFFF;
320 rstate->states[EG_SCISSOR__PA_SC_CLIPRECT_0_TL] = tl;
321 rstate->states[EG_SCISSOR__PA_SC_CLIPRECT_0_BR] = br;
322 rstate->states[EG_SCISSOR__PA_SC_CLIPRECT_1_TL] = tl;
323 rstate->states[EG_SCISSOR__PA_SC_CLIPRECT_1_BR] = br;
324 rstate->states[EG_SCISSOR__PA_SC_CLIPRECT_2_TL] = tl;
325 rstate->states[EG_SCISSOR__PA_SC_CLIPRECT_2_BR] = br;
326 rstate->states[EG_SCISSOR__PA_SC_CLIPRECT_3_TL] = tl;
327 rstate->states[EG_SCISSOR__PA_SC_CLIPRECT_3_BR] = br;
328 rstate->states[EG_SCISSOR__PA_SC_EDGERULE] = 0xAAAAAAAA;
329 rstate->states[EG_SCISSOR__PA_SC_GENERIC_SCISSOR_TL] = tl | S_028240_WINDOW_OFFSET_DISABLE(1);
330 rstate->states[EG_SCISSOR__PA_SC_GENERIC_SCISSOR_BR] = br;
331 rstate->states[EG_SCISSOR__PA_SC_VPORT_SCISSOR_0_TL] = tl | S_028240_WINDOW_OFFSET_DISABLE(1);
332 rstate->states[EG_SCISSOR__PA_SC_VPORT_SCISSOR_0_BR] = br;
333 radeon_state_pm4(rstate);
334 }
335
336 static void eg_viewport(struct r600_context *rctx, struct radeon_state *rstate, const struct pipe_viewport_state *state)
337 {
338 struct r600_screen *rscreen = rctx->screen;
339
340 radeon_state_init(rstate, rscreen->rw, R600_STATE_VIEWPORT, 0, 0);
341 rstate->states[EG_VIEWPORT__PA_SC_VPORT_ZMIN_0] = 0x00000000;
342 rstate->states[EG_VIEWPORT__PA_SC_VPORT_ZMAX_0] = 0x3F800000;
343 rstate->states[EG_VIEWPORT__PA_CL_VPORT_XSCALE_0] = fui(state->scale[0]);
344 rstate->states[EG_VIEWPORT__PA_CL_VPORT_YSCALE_0] = fui(state->scale[1]);
345 rstate->states[EG_VIEWPORT__PA_CL_VPORT_ZSCALE_0] = fui(state->scale[2]);
346 rstate->states[EG_VIEWPORT__PA_CL_VPORT_XOFFSET_0] = fui(state->translate[0]);
347 rstate->states[EG_VIEWPORT__PA_CL_VPORT_YOFFSET_0] = fui(state->translate[1]);
348 rstate->states[EG_VIEWPORT__PA_CL_VPORT_ZOFFSET_0] = fui(state->translate[2]);
349 rstate->states[EG_VIEWPORT__PA_CL_VTE_CNTL] = 0x0000043F;
350 radeon_state_pm4(rstate);
351 }
352
353 static void eg_dsa(struct r600_context *rctx, struct radeon_state *rstate)
354 {
355 const struct pipe_depth_stencil_alpha_state *state = &rctx->dsa->state.dsa;
356 const struct pipe_stencil_ref *stencil_ref = &rctx->stencil_ref->state.stencil_ref;
357 struct r600_screen *rscreen = rctx->screen;
358 unsigned db_depth_control, alpha_test_control, alpha_ref, db_shader_control;
359 unsigned stencil_ref_mask, stencil_ref_mask_bf, db_render_override, db_render_control;
360 struct r600_shader *rshader;
361 struct r600_query *rquery = NULL;
362 boolean query_running;
363 int i;
364
365 if (rctx->ps_shader == NULL) {
366 return;
367 }
368 radeon_state_init(rstate, rscreen->rw, R600_STATE_DSA, 0, 0);
369
370 db_shader_control = 0;
371 db_shader_control |= S_02880C_DUAL_EXPORT_ENABLE(1);
372 db_shader_control |= S_02880C_Z_ORDER(V_02880C_EARLY_Z_THEN_LATE_Z);
373
374 rshader = &rctx->ps_shader->shader;
375 if (rshader->uses_kill)
376 db_shader_control |= S_02880C_KILL_ENABLE(1);
377 for (i = 0; i < rshader->noutput; i++) {
378 if (rshader->output[i].name == TGSI_SEMANTIC_POSITION)
379 db_shader_control |= S_02880C_Z_EXPORT_ENABLE(1);
380 }
381 stencil_ref_mask = 0;
382 stencil_ref_mask_bf = 0;
383 db_depth_control = S_028800_Z_ENABLE(state->depth.enabled) |
384 S_028800_Z_WRITE_ENABLE(state->depth.writemask) |
385 S_028800_ZFUNC(state->depth.func);
386 /* set stencil enable */
387
388 if (state->stencil[0].enabled) {
389 db_depth_control |= S_028800_STENCIL_ENABLE(1);
390 db_depth_control |= S_028800_STENCILFUNC(r600_translate_ds_func(state->stencil[0].func));
391 db_depth_control |= S_028800_STENCILFAIL(r600_translate_stencil_op(state->stencil[0].fail_op));
392 db_depth_control |= S_028800_STENCILZPASS(r600_translate_stencil_op(state->stencil[0].zpass_op));
393 db_depth_control |= S_028800_STENCILZFAIL(r600_translate_stencil_op(state->stencil[0].zfail_op));
394
395 stencil_ref_mask = S_028430_STENCILMASK(state->stencil[0].valuemask) |
396 S_028430_STENCILWRITEMASK(state->stencil[0].writemask);
397 stencil_ref_mask |= S_028430_STENCILREF(stencil_ref->ref_value[0]);
398 if (state->stencil[1].enabled) {
399 db_depth_control |= S_028800_BACKFACE_ENABLE(1);
400 db_depth_control |= S_028800_STENCILFUNC_BF(r600_translate_ds_func(state->stencil[1].func));
401 db_depth_control |= S_028800_STENCILFAIL_BF(r600_translate_stencil_op(state->stencil[1].fail_op));
402 db_depth_control |= S_028800_STENCILZPASS_BF(r600_translate_stencil_op(state->stencil[1].zpass_op));
403 db_depth_control |= S_028800_STENCILZFAIL_BF(r600_translate_stencil_op(state->stencil[1].zfail_op));
404 stencil_ref_mask_bf = S_028434_STENCILMASK_BF(state->stencil[1].valuemask) |
405 S_028434_STENCILWRITEMASK_BF(state->stencil[1].writemask);
406 stencil_ref_mask_bf |= S_028430_STENCILREF(stencil_ref->ref_value[1]);
407 }
408 }
409
410 alpha_test_control = 0;
411 alpha_ref = 0;
412 if (state->alpha.enabled) {
413 alpha_test_control = S_028410_ALPHA_FUNC(state->alpha.func);
414 alpha_test_control |= S_028410_ALPHA_TEST_ENABLE(1);
415 alpha_ref = fui(state->alpha.ref_value);
416 }
417
418 db_render_control = 0;
419 /// db_render_control = S_028D0C_STENCIL_COMPRESS_DISABLE(1) |
420 /// S_028D0C_DEPTH_COMPRESS_DISABLE(1);
421 db_render_override = S_02800C_FORCE_HIZ_ENABLE(V_02800C_FORCE_DISABLE) |
422 S_02800C_FORCE_HIS_ENABLE0(V_02800C_FORCE_DISABLE) |
423 S_02800C_FORCE_HIS_ENABLE1(V_02800C_FORCE_DISABLE);
424
425 query_running = FALSE;
426
427 LIST_FOR_EACH_ENTRY(rquery, &rctx->query_list, list) {
428 if (rquery->state & R600_QUERY_STATE_STARTED) {
429 query_running = TRUE;
430 }
431 }
432
433 if (query_running) {
434 db_render_override |= S_02800C_NOOP_CULL_DISABLE(1);
435 // db_render_control |= S_028000_PERFECT_ZPASS_COUNTS(1);
436 }
437
438 rstate->states[EG_DSA__DB_STENCIL_CLEAR] = 0x00000000;
439 rstate->states[EG_DSA__DB_DEPTH_CLEAR] = 0x3F800000;
440 rstate->states[EG_DSA__SX_ALPHA_TEST_CONTROL] = alpha_test_control;
441 rstate->states[EG_DSA__DB_STENCILREFMASK] = stencil_ref_mask;
442 rstate->states[EG_DSA__DB_STENCILREFMASK_BF] = stencil_ref_mask_bf;
443 rstate->states[EG_DSA__SX_ALPHA_REF] = alpha_ref;
444 // rstate->states[EG_DSA__SPI_FOG_FUNC_SCALE] = 0x00000000;
445 // rstate->states[EG_DSA__SPI_FOG_FUNC_BIAS] = 0x00000000;
446 rstate->states[EG_DSA__SPI_FOG_CNTL] = 0x00000000;
447 rstate->states[EG_DSA__DB_DEPTH_CONTROL] = db_depth_control;
448 rstate->states[EG_DSA__DB_SHADER_CONTROL] = db_shader_control;
449 rstate->states[EG_DSA__DB_RENDER_CONTROL] = db_render_control;
450 rstate->states[EG_DSA__DB_RENDER_OVERRIDE] = db_render_override;
451
452 rstate->states[EG_DSA__DB_SRESULTS_COMPARE_STATE1] = 0x00000000;
453 rstate->states[EG_DSA__DB_PRELOAD_CONTROL] = 0x00000000;
454 rstate->states[EG_DSA__DB_ALPHA_TO_MASK] = 0x0000AA00;
455 radeon_state_pm4(rstate);
456 }
457
458
459 static INLINE u32 S_FIXED(float value, u32 frac_bits)
460 {
461 return value * (1 << frac_bits);
462 }
463
464 static void eg_sampler_border(struct r600_context *rctx, struct radeon_state *rstate,
465 const struct pipe_sampler_state *state, unsigned id)
466 {
467 struct r600_screen *rscreen = rctx->screen;
468 union util_color uc;
469
470 util_pack_color(state->border_color, PIPE_FORMAT_B8G8R8A8_UNORM, &uc);
471
472 radeon_state_init(rstate, rscreen->rw, R600_STATE_SAMPLER_BORDER, id, R600_SHADER_PS);
473 if (uc.ui) {
474 rstate->states[EG_PS_SAMPLER_BORDER__TD_PS_SAMPLER0_BORDER_INDEX] = id;
475 rstate->states[EG_PS_SAMPLER_BORDER__TD_PS_SAMPLER0_BORDER_RED] = fui(state->border_color[0]);
476 rstate->states[EG_PS_SAMPLER_BORDER__TD_PS_SAMPLER0_BORDER_GREEN] = fui(state->border_color[1]);
477 rstate->states[EG_PS_SAMPLER_BORDER__TD_PS_SAMPLER0_BORDER_BLUE] = fui(state->border_color[2]);
478 rstate->states[EG_PS_SAMPLER_BORDER__TD_PS_SAMPLER0_BORDER_ALPHA] = fui(state->border_color[3]);
479 }
480 radeon_state_pm4(rstate);
481 }
482
483 static void eg_sampler(struct r600_context *rctx, struct radeon_state *rstate,
484 const struct pipe_sampler_state *state, unsigned id)
485 {
486 struct r600_screen *rscreen = rctx->screen;
487 union util_color uc;
488
489 util_pack_color(state->border_color, PIPE_FORMAT_B8G8R8A8_UNORM, &uc);
490
491 radeon_state_init(rstate, rscreen->rw, R600_STATE_SAMPLER, id, R600_SHADER_PS);
492 rstate->states[EG_PS_SAMPLER__SQ_TEX_SAMPLER_WORD0_0] =
493 S_03C000_CLAMP_X(r600_tex_wrap(state->wrap_s)) |
494 S_03C000_CLAMP_Y(r600_tex_wrap(state->wrap_t)) |
495 S_03C000_CLAMP_Z(r600_tex_wrap(state->wrap_r)) |
496 S_03C000_XY_MAG_FILTER(r600_tex_filter(state->mag_img_filter)) |
497 S_03C000_XY_MIN_FILTER(r600_tex_filter(state->min_img_filter)) |
498 S_03C000_MIP_FILTER(r600_tex_mipfilter(state->min_mip_filter)) |
499 S_03C000_DEPTH_COMPARE_FUNCTION(r600_tex_compare(state->compare_func)) |
500 S_03C000_BORDER_COLOR_TYPE(uc.ui ? V_03C000_SQ_TEX_BORDER_COLOR_REGISTER : 0);
501 /* FIXME LOD it depends on texture base level ... */
502 rstate->states[EG_PS_SAMPLER__SQ_TEX_SAMPLER_WORD1_0] =
503 S_03C004_MIN_LOD(S_FIXED(CLAMP(state->min_lod, 0, 15), 6)) |
504 S_03C004_MAX_LOD(S_FIXED(CLAMP(state->max_lod, 0, 15), 6));
505
506 rstate->states[EG_PS_SAMPLER__SQ_TEX_SAMPLER_WORD2_0] =
507 S_03C008_LOD_BIAS(S_FIXED(CLAMP(state->lod_bias, -16, 16), 6)) |
508 S_03C008_TYPE(1);
509 radeon_state_pm4(rstate);
510
511 }
512
513
514 static void eg_resource(struct pipe_context *ctx, struct radeon_state *rstate,
515 const struct pipe_sampler_view *view, unsigned id)
516 {
517 struct r600_context *rctx = r600_context(ctx);
518 struct r600_screen *rscreen = rctx->screen;
519 const struct util_format_description *desc;
520 struct r600_resource_texture *tmp;
521 struct r600_resource *rbuffer;
522 unsigned format;
523 uint32_t word4 = 0, yuv_format = 0, pitch = 0;
524 unsigned char swizzle[4];
525 int r;
526
527 rstate->cpm4 = 0;
528 swizzle[0] = view->swizzle_r;
529 swizzle[1] = view->swizzle_g;
530 swizzle[2] = view->swizzle_b;
531 swizzle[3] = view->swizzle_a;
532 format = r600_translate_texformat(view->texture->format,
533 swizzle,
534 &word4, &yuv_format);
535 if (format == ~0) {
536 return;
537 }
538 desc = util_format_description(view->texture->format);
539 if (desc == NULL) {
540 R600_ERR("unknow format %d\n", view->texture->format);
541 return;
542 }
543 radeon_state_init(rstate, rscreen->rw, R600_STATE_RESOURCE, id, R600_SHADER_PS);
544 tmp = (struct r600_resource_texture*)view->texture;
545 rbuffer = &tmp->resource;
546 radeon_ws_bo_reference(rscreen->rw, &rstate->bo[0], rbuffer->bo);
547 radeon_ws_bo_reference(rscreen->rw, &rstate->bo[1], rbuffer->bo);
548
549 rstate->nbo = 2;
550 rstate->placement[0] = RADEON_GEM_DOMAIN_GTT;
551 rstate->placement[1] = RADEON_GEM_DOMAIN_GTT;
552 rstate->placement[2] = RADEON_GEM_DOMAIN_GTT;
553 rstate->placement[3] = RADEON_GEM_DOMAIN_GTT;
554
555 pitch = align(tmp->pitch[0] / tmp->bpt, 8);
556
557 /* FIXME properly handle first level != 0 */
558 rstate->states[EG_PS_RESOURCE__RESOURCE0_WORD0] =
559 S_030000_DIM(r600_tex_dim(view->texture->target)) |
560 S_030000_PITCH((pitch / 8) - 1) |
561 S_030000_TEX_WIDTH(view->texture->width0 - 1);
562 rstate->states[EG_PS_RESOURCE__RESOURCE0_WORD1] =
563 S_030004_TEX_HEIGHT(view->texture->height0 - 1) |
564 S_030004_TEX_DEPTH(view->texture->depth0 - 1);
565 rstate->states[EG_PS_RESOURCE__RESOURCE0_WORD2] = tmp->offset[0] >> 8;
566 rstate->states[EG_PS_RESOURCE__RESOURCE0_WORD3] = tmp->offset[1] >> 8;
567 rstate->states[EG_PS_RESOURCE__RESOURCE0_WORD4] =
568 word4 |
569 S_030010_NUM_FORMAT_ALL(V_030010_SQ_NUM_FORMAT_NORM) |
570 S_030010_SRF_MODE_ALL(V_030010_SFR_MODE_NO_ZERO) |
571 S_030010_REQUEST_SIZE(1) |
572 S_030010_BASE_LEVEL(view->first_level);
573 rstate->states[EG_PS_RESOURCE__RESOURCE0_WORD5] =
574 S_030014_LAST_LEVEL(view->last_level) |
575 S_030014_BASE_ARRAY(0) |
576 S_030014_LAST_ARRAY(0);
577 rstate->states[EG_PS_RESOURCE__RESOURCE0_WORD6] = 0;
578 rstate->states[EG_PS_RESOURCE__RESOURCE0_WORD7] =
579 S_03001C_DATA_FORMAT(format) |
580 S_03001C_TYPE(V_03001C_SQ_TEX_VTX_VALID_TEXTURE);
581 radeon_state_pm4(rstate);
582 }
583
584 static void eg_cb_cntl(struct r600_context *rctx, struct radeon_state *rstate)
585 {
586 struct r600_screen *rscreen = rctx->screen;
587 const struct pipe_blend_state *pbs = &rctx->blend->state.blend;
588 int nr_cbufs = rctx->framebuffer->state.framebuffer.nr_cbufs;
589 uint32_t color_control, target_mask, shader_mask;
590 int i;
591
592 target_mask = 0;
593 shader_mask = 0;
594 color_control = S_028808_MODE(1);
595
596 for (i = 0; i < nr_cbufs; i++) {
597 shader_mask |= 0xf << (i * 4);
598 }
599
600 if (pbs->logicop_enable) {
601 color_control |= (pbs->logicop_func << 16) | (pbs->logicop_func << 20);
602 } else {
603 color_control |= (0xcc << 16);
604 }
605
606 if (pbs->independent_blend_enable) {
607 for (i = 0; i < nr_cbufs; i++) {
608 target_mask |= (pbs->rt[i].colormask << (4 * i));
609 }
610 } else {
611 for (i = 0; i < nr_cbufs; i++) {
612 target_mask |= (pbs->rt[0].colormask << (4 * i));
613 }
614 }
615 radeon_state_init(rstate, rscreen->rw, R600_STATE_CB_CNTL, 0, 0);
616 rstate->states[EG_CB_CNTL__CB_SHADER_MASK] = shader_mask;
617 rstate->states[EG_CB_CNTL__CB_TARGET_MASK] = target_mask;
618 rstate->states[EG_CB_CNTL__CB_COLOR_CONTROL] = color_control;
619 rstate->states[EG_CB_CNTL__PA_SC_AA_CONFIG] = 0x00000000;
620 rstate->states[EG_CB_CNTL__PA_SC_AA_SAMPLE_LOCS_MCTX] = 0x00000000;
621 rstate->states[EG_CB_CNTL__PA_SC_AA_MASK] = 0xFFFFFFFF;
622 radeon_state_pm4(rstate);
623 }
624
625
626 static void eg_init_config(struct r600_context *rctx)
627 {
628 int ps_prio;
629 int vs_prio;
630 int gs_prio;
631 int es_prio;
632 int hs_prio, cs_prio, ls_prio;
633 int num_ps_gprs;
634 int num_vs_gprs;
635 int num_gs_gprs;
636 int num_es_gprs;
637 int num_hs_gprs;
638 int num_ls_gprs;
639 int num_temp_gprs;
640 int num_ps_threads;
641 int num_vs_threads;
642 int num_gs_threads;
643 int num_es_threads;
644 int num_hs_threads;
645 int num_ls_threads;
646 int num_ps_stack_entries;
647 int num_vs_stack_entries;
648 int num_gs_stack_entries;
649 int num_es_stack_entries;
650 int num_hs_stack_entries;
651 int num_ls_stack_entries;
652 enum radeon_family family;
653
654 family = radeon_get_family(rctx->rw);
655 ps_prio = 0;
656 vs_prio = 1;
657 gs_prio = 2;
658 es_prio = 3;
659 hs_prio = 0;
660 ls_prio = 0;
661 cs_prio = 0;
662
663 switch (family) {
664 case CHIP_CEDAR:
665 default:
666 num_ps_gprs = 93;
667 num_vs_gprs = 46;
668 num_temp_gprs = 4;
669 num_gs_gprs = 31;
670 num_es_gprs = 31;
671 num_hs_gprs = 23;
672 num_ls_gprs = 23;
673 num_ps_threads = 96;
674 num_vs_threads = 16;
675 num_gs_threads = 16;
676 num_es_threads = 16;
677 num_hs_threads = 16;
678 num_ls_threads = 16;
679 num_ps_stack_entries = 42;
680 num_vs_stack_entries = 42;
681 num_gs_stack_entries = 42;
682 num_es_stack_entries = 42;
683 num_hs_stack_entries = 42;
684 num_ls_stack_entries = 42;
685 break;
686 case CHIP_REDWOOD:
687 num_ps_gprs = 93;
688 num_vs_gprs = 46;
689 num_temp_gprs = 4;
690 num_gs_gprs = 31;
691 num_es_gprs = 31;
692 num_hs_gprs = 23;
693 num_ls_gprs = 23;
694 num_ps_threads = 128;
695 num_vs_threads = 20;
696 num_gs_threads = 20;
697 num_es_threads = 20;
698 num_hs_threads = 20;
699 num_ls_threads = 20;
700 num_ps_stack_entries = 42;
701 num_vs_stack_entries = 42;
702 num_gs_stack_entries = 42;
703 num_es_stack_entries = 42;
704 num_hs_stack_entries = 42;
705 num_ls_stack_entries = 42;
706 break;
707 case CHIP_JUNIPER:
708 num_ps_gprs = 93;
709 num_vs_gprs = 46;
710 num_temp_gprs = 4;
711 num_gs_gprs = 31;
712 num_es_gprs = 31;
713 num_hs_gprs = 23;
714 num_ls_gprs = 23;
715 num_ps_threads = 128;
716 num_vs_threads = 20;
717 num_gs_threads = 20;
718 num_es_threads = 20;
719 num_hs_threads = 20;
720 num_ls_threads = 20;
721 num_ps_stack_entries = 85;
722 num_vs_stack_entries = 85;
723 num_gs_stack_entries = 85;
724 num_es_stack_entries = 85;
725 num_hs_stack_entries = 85;
726 num_ls_stack_entries = 85;
727 break;
728 case CHIP_CYPRESS:
729 case CHIP_HEMLOCK:
730 num_ps_gprs = 93;
731 num_vs_gprs = 46;
732 num_temp_gprs = 4;
733 num_gs_gprs = 31;
734 num_es_gprs = 31;
735 num_hs_gprs = 23;
736 num_ls_gprs = 23;
737 num_ps_threads = 128;
738 num_vs_threads = 20;
739 num_gs_threads = 20;
740 num_es_threads = 20;
741 num_hs_threads = 20;
742 num_ls_threads = 20;
743 num_ps_stack_entries = 85;
744 num_vs_stack_entries = 85;
745 num_gs_stack_entries = 85;
746 num_es_stack_entries = 85;
747 num_hs_stack_entries = 85;
748 num_ls_stack_entries = 85;
749 break;
750 }
751
752 radeon_state_init(&rctx->config, rctx->rw, R600_STATE_CONFIG, 0, 0);
753
754 rctx->config.states[EG_CONFIG__SQ_CONFIG] = 0x00000000;
755 switch (family) {
756 case CHIP_CEDAR:
757 break;
758 default:
759 rctx->config.states[EG_CONFIG__SQ_CONFIG] |= S_008C00_VC_ENABLE(1);
760 break;
761 }
762 rctx->config.states[EG_CONFIG__SQ_CONFIG] |= S_008C00_EXPORT_SRC_C(1);
763 rctx->config.states[EG_CONFIG__SQ_CONFIG] |= S_008C00_CS_PRIO(cs_prio);
764 rctx->config.states[EG_CONFIG__SQ_CONFIG] |= S_008C00_LS_PRIO(ls_prio);
765 rctx->config.states[EG_CONFIG__SQ_CONFIG] |= S_008C00_HS_PRIO(hs_prio);
766 rctx->config.states[EG_CONFIG__SQ_CONFIG] |= S_008C00_PS_PRIO(ps_prio);
767 rctx->config.states[EG_CONFIG__SQ_CONFIG] |= S_008C00_VS_PRIO(vs_prio);
768 rctx->config.states[EG_CONFIG__SQ_CONFIG] |= S_008C00_GS_PRIO(gs_prio);
769 rctx->config.states[EG_CONFIG__SQ_CONFIG] |= S_008C00_ES_PRIO(es_prio);
770
771 rctx->config.states[EG_CONFIG__SQ_GPR_RESOURCE_MGMT_1] = 0;
772 rctx->config.states[EG_CONFIG__SQ_GPR_RESOURCE_MGMT_1] |= S_008C04_NUM_PS_GPRS(num_ps_gprs);
773 rctx->config.states[EG_CONFIG__SQ_GPR_RESOURCE_MGMT_1] |= S_008C04_NUM_VS_GPRS(num_vs_gprs);
774 rctx->config.states[EG_CONFIG__SQ_GPR_RESOURCE_MGMT_1] |= S_008C04_NUM_CLAUSE_TEMP_GPRS(num_temp_gprs);
775
776 rctx->config.states[EG_CONFIG__SQ_GPR_RESOURCE_MGMT_2] = 0;
777 rctx->config.states[EG_CONFIG__SQ_GPR_RESOURCE_MGMT_2] |= S_008C08_NUM_GS_GPRS(num_gs_gprs);
778 rctx->config.states[EG_CONFIG__SQ_GPR_RESOURCE_MGMT_2] |= S_008C08_NUM_ES_GPRS(num_es_gprs);
779
780 rctx->config.states[EG_CONFIG__SQ_GPR_RESOURCE_MGMT_3] = 0;
781 rctx->config.states[EG_CONFIG__SQ_GPR_RESOURCE_MGMT_3] |= S_008C0C_NUM_HS_GPRS(num_hs_gprs);
782 rctx->config.states[EG_CONFIG__SQ_GPR_RESOURCE_MGMT_3] |= S_008C0C_NUM_LS_GPRS(num_ls_gprs);
783
784 rctx->config.states[EG_CONFIG__SQ_THREAD_RESOURCE_MGMT_1] = 0;
785 rctx->config.states[EG_CONFIG__SQ_THREAD_RESOURCE_MGMT_1] |= S_008C18_NUM_PS_THREADS(num_ps_threads);
786 rctx->config.states[EG_CONFIG__SQ_THREAD_RESOURCE_MGMT_1] |= S_008C18_NUM_VS_THREADS(num_vs_threads);
787 rctx->config.states[EG_CONFIG__SQ_THREAD_RESOURCE_MGMT_1] |= S_008C18_NUM_GS_THREADS(num_gs_threads);
788 rctx->config.states[EG_CONFIG__SQ_THREAD_RESOURCE_MGMT_1] |= S_008C18_NUM_ES_THREADS(num_es_threads);
789
790 rctx->config.states[EG_CONFIG__SQ_THREAD_RESOURCE_MGMT_2] = 0;
791 rctx->config.states[EG_CONFIG__SQ_THREAD_RESOURCE_MGMT_2] |= S_008C1C_NUM_HS_THREADS(num_hs_threads);
792 rctx->config.states[EG_CONFIG__SQ_THREAD_RESOURCE_MGMT_2] |= S_008C1C_NUM_LS_THREADS(num_ls_threads);
793
794 rctx->config.states[EG_CONFIG__SQ_STACK_RESOURCE_MGMT_1] = 0;
795 rctx->config.states[EG_CONFIG__SQ_STACK_RESOURCE_MGMT_1] |= S_008C20_NUM_PS_STACK_ENTRIES(num_ps_stack_entries);
796 rctx->config.states[EG_CONFIG__SQ_STACK_RESOURCE_MGMT_1] |= S_008C20_NUM_VS_STACK_ENTRIES(num_vs_stack_entries);
797
798 rctx->config.states[EG_CONFIG__SQ_STACK_RESOURCE_MGMT_2] = 0;
799 rctx->config.states[EG_CONFIG__SQ_STACK_RESOURCE_MGMT_2] |= S_008C24_NUM_GS_STACK_ENTRIES(num_gs_stack_entries);
800 rctx->config.states[EG_CONFIG__SQ_STACK_RESOURCE_MGMT_2] |= S_008C24_NUM_ES_STACK_ENTRIES(num_es_stack_entries);
801
802 rctx->config.states[EG_CONFIG__SQ_STACK_RESOURCE_MGMT_3] = 0;
803 rctx->config.states[EG_CONFIG__SQ_STACK_RESOURCE_MGMT_3] |= S_008C28_NUM_HS_STACK_ENTRIES(num_hs_stack_entries);
804 rctx->config.states[EG_CONFIG__SQ_STACK_RESOURCE_MGMT_3] |= S_008C28_NUM_LS_STACK_ENTRIES(num_ls_stack_entries);
805
806 rctx->config.states[EG_CONFIG__SPI_CONFIG_CNTL] = 0x00000000;
807 rctx->config.states[EG_CONFIG__SPI_CONFIG_CNTL_1] = S_00913C_VTX_DONE_DELAY(4);
808
809 rctx->config.states[EG_CONFIG__SX_MISC] = 0x00000000;
810
811 rctx->config.states[EG_CONFIG__SQ_DYN_GPR_CNTL_PS_FLUSH_REQ] = 0x00000000;
812 rctx->config.states[EG_CONFIG__PA_SC_MODE_CNTL_0] = 0x0;
813 rctx->config.states[EG_CONFIG__PA_SC_MODE_CNTL_1] = 0x0;
814
815 rctx->config.states[EG_CONFIG__SQ_ESGS_RING_ITEMSIZE] = 0x00000000;
816 rctx->config.states[EG_CONFIG__SQ_GSVS_RING_ITEMSIZE] = 0x00000000;
817 rctx->config.states[EG_CONFIG__SQ_ESTMP_RING_ITEMSIZE] = 0x00000000;
818 rctx->config.states[EG_CONFIG__SQ_GSTMP_RING_ITEMSIZE] = 0x00000000;
819 rctx->config.states[EG_CONFIG__SQ_VSTMP_RING_ITEMSIZE] = 0x00000000;
820 rctx->config.states[EG_CONFIG__SQ_PSTMP_RING_ITEMSIZE] = 0x00000000;
821
822 rctx->config.states[EG_CONFIG__SQ_GS_VERT_ITEMSIZE] = 0x00000000;
823 rctx->config.states[EG_CONFIG__SQ_GS_VERT_ITEMSIZE_1] = 0x00000000;
824 rctx->config.states[EG_CONFIG__SQ_GS_VERT_ITEMSIZE_2] = 0x00000000;
825 rctx->config.states[EG_CONFIG__SQ_GS_VERT_ITEMSIZE_3] = 0x00000000;
826
827 rctx->config.states[EG_CONFIG__VGT_OUTPUT_PATH_CNTL] = 0x00000000;
828 rctx->config.states[EG_CONFIG__VGT_HOS_CNTL] = 0x00000000;
829 rctx->config.states[EG_CONFIG__VGT_HOS_MAX_TESS_LEVEL] = 0x00000000;
830 rctx->config.states[EG_CONFIG__VGT_HOS_MIN_TESS_LEVEL] = 0x00000000;
831 rctx->config.states[EG_CONFIG__VGT_HOS_REUSE_DEPTH] = 0x00000000;
832 rctx->config.states[EG_CONFIG__VGT_GROUP_PRIM_TYPE] = 0x00000000;
833 rctx->config.states[EG_CONFIG__VGT_GROUP_FIRST_DECR] = 0x00000000;
834 rctx->config.states[EG_CONFIG__VGT_GROUP_DECR] = 0x00000000;
835 rctx->config.states[EG_CONFIG__VGT_GROUP_VECT_0_CNTL] = 0x00000000;
836 rctx->config.states[EG_CONFIG__VGT_GROUP_VECT_1_CNTL] = 0x00000000;
837 rctx->config.states[EG_CONFIG__VGT_GROUP_VECT_0_FMT_CNTL] = 0x00000000;
838 rctx->config.states[EG_CONFIG__VGT_GROUP_VECT_1_FMT_CNTL] = 0x00000000;
839 rctx->config.states[EG_CONFIG__VGT_GS_MODE] = 0x00000000;
840 rctx->config.states[EG_CONFIG__VGT_STRMOUT_CONFIG] = 0x00000000;
841 rctx->config.states[EG_CONFIG__VGT_STRMOUT_BUFFER_CONFIG] = 0x00000000;
842 rctx->config.states[EG_CONFIG__VGT_REUSE_OFF] = 0x00000001;
843 rctx->config.states[EG_CONFIG__VGT_VTX_CNT_EN] = 0x00000000;
844 // rctx->config.states[EG_CONFIG__VGT_CACHE_INVALIDATION] = 0x2;
845 // rctx->config.states[EG_CONFIG__VGT_GS_VERTEX_REUSE] = 0x16;
846 rctx->config.states[EG_CONFIG__PA_CL_ENHANCE] = (3 << 1) | 1;
847
848 radeon_state_pm4(&rctx->config);
849 }
850
851 static int eg_vs_resource(struct r600_context *rctx, int id, struct r600_resource *rbuffer, uint32_t offset,
852 uint32_t stride, uint32_t src_format)
853 {
854 struct radeon_state *vs_resource = &rctx->vs_resource[id];
855 struct r600_screen *rscreen = rctx->screen;
856 unsigned format, num_format = 0, format_comp = 0;
857
858 format = r600_translate_colorformat(src_format);
859
860 r600_translate_vertex_num_format(src_format, &num_format, &format_comp);
861 format = S_030008_DATA_FORMAT(format) | S_030008_NUM_FORMAT_ALL(num_format) |
862 S_030008_FORMAT_COMP_ALL(format_comp);
863
864 radeon_state_init(vs_resource, rscreen->rw, R600_STATE_RESOURCE, id, R600_SHADER_VS);
865
866 radeon_ws_bo_reference(rscreen->rw, &vs_resource->bo[0], rbuffer->bo);
867 vs_resource->nbo = 1;
868 vs_resource->states[EG_PS_RESOURCE__RESOURCE0_WORD0] = offset;
869 vs_resource->states[EG_PS_RESOURCE__RESOURCE0_WORD1] = rbuffer->size - offset - 1;
870 vs_resource->states[EG_PS_RESOURCE__RESOURCE0_WORD2] = S_030008_STRIDE(stride) | format;
871 vs_resource->states[EG_PS_RESOURCE__RESOURCE0_WORD3] = S_03000C_DST_SEL_X(V_03000C_SQ_SEL_X) |
872 S_03000C_DST_SEL_Y(V_03000C_SQ_SEL_Y) |
873 S_03000C_DST_SEL_Z(V_03000C_SQ_SEL_Z) |
874 S_03000C_DST_SEL_W(V_03000C_SQ_SEL_W);
875
876 vs_resource->states[EG_PS_RESOURCE__RESOURCE0_WORD4] = 0x00000000;
877 vs_resource->states[EG_PS_RESOURCE__RESOURCE0_WORD5] = 0x00000000;
878 vs_resource->states[EG_PS_RESOURCE__RESOURCE0_WORD6] = 0x00000000;
879 vs_resource->states[EG_PS_RESOURCE__RESOURCE0_WORD7] = 0xC0000000;
880 vs_resource->placement[0] = RADEON_GEM_DOMAIN_GTT;
881 vs_resource->placement[1] = RADEON_GEM_DOMAIN_GTT;
882 return radeon_state_pm4(vs_resource);
883 }
884
885 static int eg_draw_vgt_init(struct r600_draw *draw,
886 int vgt_draw_initiator)
887 {
888 struct r600_context *rctx = r600_context(draw->ctx);
889 struct r600_screen *rscreen = rctx->screen;
890 struct r600_resource *rbuffer = (struct r600_resource *)draw->index_buffer;
891 radeon_state_init(&draw->draw, rscreen->rw, R600_STATE_DRAW, 0, 0);
892 draw->draw.states[EG_DRAW__VGT_NUM_INDICES] = draw->count;
893 draw->draw.states[EG_DRAW__VGT_DRAW_INITIATOR] = vgt_draw_initiator;
894 draw->draw.states[EG_DRAW__VGT_DMA_BASE] = draw->index_buffer_offset;
895 if (rbuffer) {
896 radeon_ws_bo_reference(rscreen->rw, &draw->draw.bo[0], rbuffer->bo);
897 draw->draw.placement[0] = RADEON_GEM_DOMAIN_GTT;
898 draw->draw.placement[1] = RADEON_GEM_DOMAIN_GTT;
899 draw->draw.nbo = 1;
900 }
901 return radeon_state_pm4(&draw->draw);
902 }
903
904 static int eg_draw_vgt_prim(struct r600_draw *draw,
905 uint32_t prim, uint32_t vgt_dma_index_type)
906 {
907 struct r600_context *rctx = r600_context(draw->ctx);
908 struct r600_screen *rscreen = rctx->screen;
909 radeon_state_init(&draw->vgt, rscreen->rw, R600_STATE_VGT, 0, 0);
910 draw->vgt.states[EG_VGT__VGT_PRIMITIVE_TYPE] = prim;
911 draw->vgt.states[EG_VGT__VGT_MAX_VTX_INDX] = draw->max_index;
912 draw->vgt.states[EG_VGT__VGT_MIN_VTX_INDX] = draw->min_index;
913 draw->vgt.states[EG_VGT__VGT_INDX_OFFSET] = draw->start;
914 draw->vgt.states[EG_VGT__VGT_DMA_INDEX_TYPE] = vgt_dma_index_type;
915 draw->vgt.states[EG_VGT__VGT_PRIMITIVEID_EN] = 0x00000000;
916 draw->vgt.states[EG_VGT__VGT_DMA_NUM_INSTANCES] = 0x00000001;
917 draw->vgt.states[EG_VGT__VGT_MULTI_PRIM_IB_RESET_EN] = 0x00000000;
918 draw->vgt.states[EG_VGT__VGT_INSTANCE_STEP_RATE_0] = 0x00000000;
919 draw->vgt.states[EG_VGT__VGT_INSTANCE_STEP_RATE_1] = 0x00000000;
920 return radeon_state_pm4(&draw->vgt);
921 }
922
923
924 static int eg_ps_shader(struct r600_context *rctx, struct r600_context_state *rpshader,
925 struct radeon_state *state)
926 {
927 struct r600_screen *rscreen = rctx->screen;
928 const struct pipe_rasterizer_state *rasterizer;
929 struct r600_shader *rshader = &rpshader->shader;
930 unsigned i, tmp, exports_ps, num_cout;
931 boolean have_pos = FALSE, have_face = FALSE;
932
933 rasterizer = &rctx->rasterizer->state.rasterizer;
934
935 radeon_state_init(state, rscreen->rw, R600_STATE_SHADER, 0, R600_SHADER_PS);
936 for (i = 0; i < rshader->ninput; i++) {
937 tmp = S_028644_SEMANTIC(r600_find_vs_semantic_index(rctx, rshader, i));
938 tmp |= S_028644_SEL_CENTROID(1);
939 if (rshader->input[i].name == TGSI_SEMANTIC_POSITION)
940 have_pos = TRUE;
941 if (rshader->input[i].name == TGSI_SEMANTIC_COLOR ||
942 rshader->input[i].name == TGSI_SEMANTIC_BCOLOR ||
943 rshader->input[i].name == TGSI_SEMANTIC_POSITION) {
944 tmp |= S_028644_FLAT_SHADE(rshader->flat_shade);
945 }
946
947 if (rshader->input[i].name == TGSI_SEMANTIC_FACE)
948 have_face = TRUE;
949
950 if (rasterizer->sprite_coord_enable & (1 << i)) {
951 tmp |= S_028644_PT_SPRITE_TEX(1);
952 }
953 state->states[EG_PS_SHADER__SPI_PS_INPUT_CNTL_0 + i] = tmp;
954 }
955
956 exports_ps = 0;
957 num_cout = 0;
958 for (i = 0; i < rshader->noutput; i++) {
959 if (rshader->output[i].name == TGSI_SEMANTIC_POSITION)
960 exports_ps |= 1;
961 else if (rshader->output[i].name == TGSI_SEMANTIC_COLOR) {
962 num_cout++;
963 }
964 }
965 exports_ps |= (1 << num_cout);
966 if (!exports_ps) {
967 /* always at least export 1 component per pixel */
968 exports_ps = 2;
969 }
970 state->states[EG_PS_SHADER__SPI_PS_IN_CONTROL_0] = S_0286CC_NUM_INTERP(rshader->ninput) |
971 S_0286CC_PERSP_GRADIENT_ENA(1);
972 if (have_pos) {
973 state->states[EG_PS_SHADER__SPI_PS_IN_CONTROL_0] |= S_0286CC_POSITION_ENA(1);
974 state->states[EG_PS_SHADER__SPI_INPUT_Z] |= 1;
975 }
976
977 state->states[EG_PS_SHADER__SPI_PS_IN_CONTROL_1] = 0x00000000;
978 state->states[EG_PS_SHADER__SPI_PS_IN_CONTROL_1] |= S_0286D0_FRONT_FACE_ENA(have_face);
979
980 state->states[EG_PS_SHADER__SQ_PGM_RESOURCES_PS] = S_028844_NUM_GPRS(rshader->bc.ngpr) | S_028844_PRIME_CACHE_ON_DRAW(1) |
981 S_028844_STACK_SIZE(rshader->bc.nstack);
982 state->states[EG_PS_SHADER__SQ_PGM_EXPORTS_PS] = exports_ps;
983 state->states[EG_PS_SHADER__SPI_BARYC_CNTL] = S_0286E0_PERSP_CENTROID_ENA(1) |
984 S_0286E0_LINEAR_CENTROID_ENA(1);
985 radeon_ws_bo_reference(rscreen->rw, &state->bo[0], rpshader->bo);
986 state->nbo = 1;
987 state->placement[0] = RADEON_GEM_DOMAIN_GTT;
988 return radeon_state_pm4(state);
989 }
990
991 static int eg_vs_shader(struct r600_context *rctx, struct r600_context_state *rpshader,
992 struct radeon_state *state)
993 {
994 struct r600_screen *rscreen = rctx->screen;
995 struct r600_shader *rshader = &rpshader->shader;
996 unsigned i, tmp;
997
998 radeon_state_init(state, rscreen->rw, R600_STATE_SHADER, 0, R600_SHADER_VS);
999 for (i = 0; i < 10; i++) {
1000 state->states[EG_VS_SHADER__SPI_VS_OUT_ID_0 + i] = 0;
1001 }
1002 /* so far never got proper semantic id from tgsi */
1003 for (i = 0; i < 32; i++) {
1004 tmp = i << ((i & 3) * 8);
1005 state->states[EG_VS_SHADER__SPI_VS_OUT_ID_0 + i / 4] |= tmp;
1006 }
1007 state->states[EG_VS_SHADER__SPI_VS_OUT_CONFIG] = S_0286C4_VS_EXPORT_COUNT(rshader->noutput - 2);
1008 state->states[EG_VS_SHADER__SQ_PGM_RESOURCES_VS] = S_028860_NUM_GPRS(rshader->bc.ngpr) |
1009 S_028860_STACK_SIZE(rshader->bc.nstack);
1010 radeon_ws_bo_reference(rscreen->rw, &state->bo[0], rpshader->bo);
1011 radeon_ws_bo_reference(rscreen->rw, &state->bo[1], rpshader->bo);
1012 state->nbo = 2;
1013 state->placement[0] = RADEON_GEM_DOMAIN_GTT;
1014 state->placement[2] = RADEON_GEM_DOMAIN_GTT;
1015 return radeon_state_pm4(state);
1016
1017 }
1018
1019 struct r600_context_hw_state_vtbl eg_hw_state_vtbl = {
1020 .blend = eg_blend,
1021 .ucp = eg_ucp,
1022 .cb = eg_cb,
1023 .db = eg_db,
1024 .rasterizer = eg_rasterizer,
1025 .scissor = eg_scissor,
1026 .viewport = eg_viewport,
1027 .dsa = eg_dsa,
1028 .sampler_border = eg_sampler_border,
1029 .sampler = eg_sampler,
1030 .resource = eg_resource,
1031 .cb_cntl = eg_cb_cntl,
1032 .vs_resource = eg_vs_resource,
1033 .vgt_init = eg_draw_vgt_init,
1034 .vgt_prim = eg_draw_vgt_prim,
1035 .vs_shader = eg_vs_shader,
1036 .ps_shader = eg_ps_shader,
1037 .init_config = eg_init_config,
1038 };
1039
1040 void eg_set_constant_buffer(struct pipe_context *ctx,
1041 uint shader, uint index,
1042 struct pipe_resource *buffer)
1043 {
1044 struct r600_screen *rscreen = r600_screen(ctx->screen);
1045 struct r600_context *rctx = r600_context(ctx);
1046 unsigned nconstant = 0, type, shader_class, size;
1047 struct radeon_state *rstate, *rstates;
1048 struct r600_resource *rbuffer = (struct r600_resource*)buffer;
1049
1050 type = R600_STATE_CBUF;
1051
1052 switch (shader) {
1053 case PIPE_SHADER_VERTEX:
1054 shader_class = R600_SHADER_VS;
1055 rstates = rctx->vs_constant;
1056 break;
1057 case PIPE_SHADER_FRAGMENT:
1058 shader_class = R600_SHADER_PS;
1059 rstates = rctx->ps_constant;
1060 break;
1061 default:
1062 R600_ERR("unsupported %d\n", shader);
1063 return;
1064 }
1065
1066 rstate = &rstates[0];
1067
1068 #define ALIGN_DIVUP(x, y) (((x) + (y) - 1) / (y))
1069 nconstant = buffer->width0 / 16;
1070 size = ALIGN_DIVUP(nconstant, 16);
1071
1072 radeon_state_init(rstate, rscreen->rw, type, 0, shader_class);
1073 rstate->states[EG_VS_CBUF__ALU_CONST_BUFFER_SIZE_VS_0] = size;
1074 rstate->states[EG_VS_CBUF__ALU_CONST_CACHE_VS_0] = 0;
1075
1076 radeon_ws_bo_reference(rscreen->rw, &rstate->bo[0], rbuffer->bo);
1077 rstate->nbo = 1;
1078 rstate->placement[0] = RADEON_GEM_DOMAIN_VRAM;
1079 if (radeon_state_pm4(rstate))
1080 return;
1081 radeon_draw_bind(&rctx->draw, rstate);
1082 }