projects / mesa.git / blob
? search:


f3f1dc7b0a7da609d3da86720c7b9bcf9fd2713d
[mesa.git] / src / gallium / drivers / r600 / eg_hw_states.c
1 /*
2 * Copyright 2010 Jerome Glisse <glisse@freedesktop.org>
3 * 2010 Red Hat Inc.
4 *
5 * Permission is hereby granted, free of charge, to any person obtaining a
6 * copy of this software and associated documentation files (the "Software"),
7 * to deal in the Software without restriction, including without limitation
8 * on the rights to use, copy, modify, merge, publish, distribute, sub
9 * license, and/or sell copies of the Software, and to permit persons to whom
10 * the Software is furnished to do so, subject to the following conditions:
11 *
12 * The above copyright notice and this permission notice (including the next
13 * paragraph) shall be included in all copies or substantial portions of the
14 * Software.
15 *
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
19 * THE AUTHOR(S) AND/OR THEIR SUPPLIERS BE LIABLE FOR ANY CLAIM,
20 * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
21 * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
22 * USE OR OTHER DEALINGS IN THE SOFTWARE.
23 *
24 * Authors:
25 * Jerome Glisse
26 * Dave Airlie
27 */
28 #include <util/u_inlines.h>
29 #include <util/u_format.h>
30 #include <util/u_memory.h>
31 #include <util/u_blitter.h>
32 #include "util/u_pack_color.h"
33 #include "r600_screen.h"
34 #include "r600_context.h"
35 #include "r600_resource.h"
36 #include "eg_state_inlines.h"
37 #include "evergreend.h"
38
39 #include "eg_states_inc.h"
40
41 static void eg_blend(struct r600_context *rctx, struct radeon_state *rstate, const struct pipe_blend_state *state)
42 {
43 struct r600_screen *rscreen = rctx->screen;
44 int i;
45
46 radeon_state_init(rstate, rscreen->rw, R600_STATE_BLEND, 0, 0);
47 rstate->states[EG_BLEND__CB_BLEND_RED] = fui(rctx->blend_color.color[0]);
48 rstate->states[EG_BLEND__CB_BLEND_GREEN] = fui(rctx->blend_color.color[1]);
49 rstate->states[EG_BLEND__CB_BLEND_BLUE] = fui(rctx->blend_color.color[2]);
50 rstate->states[EG_BLEND__CB_BLEND_ALPHA] = fui(rctx->blend_color.color[3]);
51 rstate->states[EG_BLEND__CB_BLEND0_CONTROL] = 0x00000000;
52 rstate->states[EG_BLEND__CB_BLEND1_CONTROL] = 0x00000000;
53 rstate->states[EG_BLEND__CB_BLEND2_CONTROL] = 0x00000000;
54 rstate->states[EG_BLEND__CB_BLEND3_CONTROL] = 0x00000000;
55 rstate->states[EG_BLEND__CB_BLEND4_CONTROL] = 0x00000000;
56 rstate->states[EG_BLEND__CB_BLEND5_CONTROL] = 0x00000000;
57 rstate->states[EG_BLEND__CB_BLEND6_CONTROL] = 0x00000000;
58 rstate->states[EG_BLEND__CB_BLEND7_CONTROL] = 0x00000000;
59
60 for (i = 0; i < 8; i++) {
61 unsigned eqRGB = state->rt[i].rgb_func;
62 unsigned srcRGB = state->rt[i].rgb_src_factor;
63 unsigned dstRGB = state->rt[i].rgb_dst_factor;
64
65 unsigned eqA = state->rt[i].alpha_func;
66 unsigned srcA = state->rt[i].alpha_src_factor;
67 unsigned dstA = state->rt[i].alpha_dst_factor;
68 uint32_t bc = 0;
69
70 if (!state->rt[i].blend_enable)
71 continue;
72
73 bc |= S_028780_BLEND_CONTROL_ENABLE(1);
74
75 bc |= S_028780_COLOR_COMB_FCN(r600_translate_blend_function(eqRGB));
76 bc |= S_028780_COLOR_SRCBLEND(r600_translate_blend_factor(srcRGB));
77 bc |= S_028780_COLOR_DESTBLEND(r600_translate_blend_factor(dstRGB));
78
79 if (srcA != srcRGB || dstA != dstRGB || eqA != eqRGB) {
80 bc |= S_028780_SEPARATE_ALPHA_BLEND(1);
81 bc |= S_028780_ALPHA_COMB_FCN(r600_translate_blend_function(eqA));
82 bc |= S_028780_ALPHA_SRCBLEND(r600_translate_blend_factor(srcA));
83 bc |= S_028780_ALPHA_DESTBLEND(r600_translate_blend_factor(dstA));
84 }
85
86 rstate->states[EG_BLEND__CB_BLEND0_CONTROL + i] = bc;
87 }
88
89 radeon_state_pm4(rstate);
90 }
91
92 static void eg_ucp(struct r600_context *rctx, struct radeon_state *rstate,
93 const struct pipe_clip_state *state)
94 {
95 struct r600_screen *rscreen = rctx->screen;
96
97 radeon_state_init(rstate, rscreen->rw, R600_STATE_UCP, 0, 0);
98
99 for (int i = 0; i < state->nr; i++) {
100 rstate->states[i * 4 + 0] = fui(state->ucp[i][0]);
101 rstate->states[i * 4 + 1] = fui(state->ucp[i][1]);
102 rstate->states[i * 4 + 2] = fui(state->ucp[i][2]);
103 rstate->states[i * 4 + 3] = fui(state->ucp[i][3]);
104 }
105 radeon_state_pm4(rstate);
106 }
107
108 static void eg_cb(struct r600_context *rctx, struct radeon_state *rstate,
109 const struct pipe_framebuffer_state *state, int cb)
110 {
111 struct r600_screen *rscreen = rctx->screen;
112 struct r600_resource_texture *rtex;
113 struct r600_resource *rbuffer;
114 unsigned level = state->cbufs[cb]->level;
115 unsigned pitch, slice;
116 unsigned color_info;
117 unsigned format, swap, ntype;
118 const struct util_format_description *desc;
119
120 radeon_state_init(rstate, rscreen->rw, R600_STATE_CB0, cb, 0);
121 rtex = (struct r600_resource_texture*)state->cbufs[cb]->texture;
122 rbuffer = &rtex->resource;
123 rstate->bo[0] = radeon_bo_incref(rscreen->rw, rbuffer->bo);
124 rstate->placement[0] = RADEON_GEM_DOMAIN_VRAM;
125 rstate->nbo = 1;
126 pitch = (rtex->pitch[level] / rtex->bpt) / 8 - 1;
127 slice = (rtex->pitch[level] / rtex->bpt) * state->cbufs[cb]->height / 64 - 1;
128
129 ntype = 0;
130 desc = util_format_description(rtex->resource.base.b.format);
131 if (desc->colorspace == UTIL_FORMAT_COLORSPACE_SRGB)
132 ntype = V_028C70_NUMBER_SRGB;
133
134 format = r600_translate_colorformat(rtex->resource.base.b.format);
135 swap = r600_translate_colorswap(rtex->resource.base.b.format);
136
137 color_info = S_028C70_FORMAT(format) |
138 S_028C70_COMP_SWAP(swap) |
139 S_028C70_BLEND_CLAMP(1) |
140 S_028C70_SOURCE_FORMAT(1) |
141 S_028C70_NUMBER_TYPE(ntype);
142
143 rstate->states[EG_CB__CB_COLOR0_BASE] = state->cbufs[cb]->offset >> 8;
144 rstate->states[EG_CB__CB_COLOR0_INFO] = color_info;
145 rstate->states[EG_CB__CB_COLOR0_PITCH] = S_028C64_PITCH_TILE_MAX(pitch);
146 rstate->states[EG_CB__CB_COLOR0_SLICE] = S_028C68_SLICE_TILE_MAX(slice);
147 rstate->states[EG_CB__CB_COLOR0_VIEW] = 0x00000000;
148 rstate->states[EG_CB__CB_COLOR0_ATTRIB] = S_028C74_NON_DISP_TILING_ORDER(1);
149
150 radeon_state_pm4(rstate);
151 }
152
153 static void eg_db(struct r600_context *rctx, struct radeon_state *rstate,
154 const struct pipe_framebuffer_state *state)
155 {
156 struct r600_screen *rscreen = rctx->screen;
157 struct r600_resource_texture *rtex;
158 struct r600_resource *rbuffer;
159 unsigned level;
160 unsigned pitch, slice, format;
161
162 radeon_state_init(rstate, rscreen->rw, R600_STATE_DB, 0, 0);
163 if (state->zsbuf == NULL)
164 return;
165
166 rtex = (struct r600_resource_texture*)state->zsbuf->texture;
167 rtex->tilled = 1;
168 rtex->array_mode = 2;
169 rtex->tile_type = 1;
170 rtex->depth = 1;
171 rbuffer = &rtex->resource;
172
173 rstate->bo[0] = radeon_bo_incref(rscreen->rw, rbuffer->bo);
174 rstate->nbo = 1;
175 rstate->placement[0] = RADEON_GEM_DOMAIN_VRAM;
176 level = state->zsbuf->level;
177 pitch = (rtex->pitch[level] / rtex->bpt) / 8 - 1;
178 slice = (rtex->pitch[level] / rtex->bpt) * state->zsbuf->height / 64 - 1;
179 format = r600_translate_dbformat(state->zsbuf->texture->format);
180 rstate->states[EG_DB__DB_HTILE_DATA_BASE] = state->zsbuf->offset >> 8;
181 rstate->states[EG_DB__DB_Z_READ_BASE] = state->zsbuf->offset >> 8;
182 rstate->states[EG_DB__DB_Z_WRITE_BASE] = state->zsbuf->offset >> 8;
183 rstate->states[EG_DB__DB_STENCIL_READ_BASE] = state->zsbuf->offset >> 8;
184 rstate->states[EG_DB__DB_STENCIL_WRITE_BASE] = state->zsbuf->offset >> 8;
185 rstate->states[EG_DB__DB_Z_INFO] = S_028040_ARRAY_MODE(rtex->array_mode) | S_028040_FORMAT(format);
186 rstate->states[EG_DB__DB_DEPTH_VIEW] = 0x00000000;
187 rstate->states[EG_DB__DB_DEPTH_SIZE] = S_028058_PITCH_TILE_MAX(pitch);
188 rstate->states[EG_DB__DB_DEPTH_SLICE] = S_02805C_SLICE_TILE_MAX(slice);
189 radeon_state_pm4(rstate);
190 }
191
192 static void eg_rasterizer(struct r600_context *rctx, struct radeon_state *rstate)
193 {
194 const struct pipe_rasterizer_state *state = &rctx->rasterizer->state.rasterizer;
195 const struct pipe_framebuffer_state *fb = &rctx->framebuffer->state.framebuffer;
196 const struct pipe_clip_state *clip = NULL;
197 struct r600_screen *rscreen = rctx->screen;
198 float offset_units = 0, offset_scale = 0;
199 char depth = 0;
200 unsigned offset_db_fmt_cntl = 0;
201 unsigned tmp;
202 unsigned prov_vtx = 1;
203
204 if (rctx->clip)
205 clip = &rctx->clip->state.clip;
206 if (fb->zsbuf) {
207 offset_units = state->offset_units;
208 offset_scale = state->offset_scale * 12.0f;
209 switch (fb->zsbuf->texture->format) {
210 case PIPE_FORMAT_Z24X8_UNORM:
211 case PIPE_FORMAT_Z24_UNORM_S8_USCALED:
212 depth = -24;
213 offset_units *= 2.0f;
214 break;
215 case PIPE_FORMAT_Z32_FLOAT:
216 depth = -23;
217 offset_units *= 1.0f;
218 offset_db_fmt_cntl |= S_028DF8_POLY_OFFSET_DB_IS_FLOAT_FMT(1);
219 break;
220 case PIPE_FORMAT_Z16_UNORM:
221 depth = -16;
222 offset_units *= 4.0f;
223 break;
224 default:
225 R600_ERR("unsupported %d\n", fb->zsbuf->texture->format);
226 return;
227 }
228 }
229 offset_db_fmt_cntl |= S_028DF8_POLY_OFFSET_NEG_NUM_DB_BITS(depth);
230
231 if (state->flatshade_first)
232 prov_vtx = 0;
233
234 rctx->flat_shade = state->flatshade;
235 radeon_state_init(rstate, rscreen->rw, R600_STATE_RASTERIZER, 0, 0);
236 rstate->states[EG_RASTERIZER__SPI_INTERP_CONTROL_0] = 0x00000000;
237 if (rctx->flat_shade)
238 rstate->states[EG_RASTERIZER__SPI_INTERP_CONTROL_0] |= S_0286D4_FLAT_SHADE_ENA(1);
239 if (state->sprite_coord_enable) {
240 rstate->states[EG_RASTERIZER__SPI_INTERP_CONTROL_0] |=
241 S_0286D4_PNT_SPRITE_ENA(1) |
242 S_0286D4_PNT_SPRITE_OVRD_X(2) |
243 S_0286D4_PNT_SPRITE_OVRD_Y(3) |
244 S_0286D4_PNT_SPRITE_OVRD_Z(0) |
245 S_0286D4_PNT_SPRITE_OVRD_W(1);
246 if (state->sprite_coord_mode != PIPE_SPRITE_COORD_UPPER_LEFT) {
247 rstate->states[EG_RASTERIZER__SPI_INTERP_CONTROL_0] |=
248 S_0286D4_PNT_SPRITE_TOP_1(1);
249 }
250 }
251 rstate->states[EG_RASTERIZER__PA_CL_CLIP_CNTL] = 0;
252 if (clip) {
253 rstate->states[EG_RASTERIZER__PA_CL_CLIP_CNTL] = S_028810_PS_UCP_MODE(3) | ((1 << clip->nr) - 1);
254 rstate->states[EG_RASTERIZER__PA_CL_CLIP_CNTL] |= S_028810_ZCLIP_NEAR_DISABLE(clip->depth_clamp);
255 rstate->states[EG_RASTERIZER__PA_CL_CLIP_CNTL] |= S_028810_ZCLIP_FAR_DISABLE(clip->depth_clamp);
256 }
257 rstate->states[EG_RASTERIZER__PA_SU_SC_MODE_CNTL] =
258 S_028814_PROVOKING_VTX_LAST(prov_vtx) |
259 S_028814_CULL_FRONT((state->cull_face & PIPE_FACE_FRONT) ? 1 : 0) |
260 S_028814_CULL_BACK((state->cull_face & PIPE_FACE_BACK) ? 1 : 0) |
261 S_028814_FACE(!state->front_ccw) |
262 S_028814_POLY_OFFSET_FRONT_ENABLE(state->offset_tri) |
263 S_028814_POLY_OFFSET_BACK_ENABLE(state->offset_tri) |
264 S_028814_POLY_OFFSET_PARA_ENABLE(state->offset_tri);
265 rstate->states[EG_RASTERIZER__PA_CL_VS_OUT_CNTL] =
266 S_02881C_USE_VTX_POINT_SIZE(state->point_size_per_vertex) |
267 S_02881C_VS_OUT_MISC_VEC_ENA(state->point_size_per_vertex);
268 rstate->states[EG_RASTERIZER__PA_CL_NANINF_CNTL] = 0x00000000;
269 /* point size 12.4 fixed point */
270 tmp = (unsigned)(state->point_size * 8.0);
271 rstate->states[EG_RASTERIZER__PA_SU_POINT_SIZE] = S_028A00_HEIGHT(tmp) | S_028A00_WIDTH(tmp);
272 rstate->states[EG_RASTERIZER__PA_SU_POINT_MINMAX] = 0x80000000;
273 rstate->states[EG_RASTERIZER__PA_SU_LINE_CNTL] = 0x00000008;
274 rstate->states[EG_RASTERIZER__PA_SU_VTX_CNTL] = 0x00000005;
275
276 rstate->states[EG_RASTERIZER__PA_SC_MPASS_PS_CNTL] = 0x00000000;
277 rstate->states[EG_RASTERIZER__PA_SC_LINE_CNTL] = 0x00000400;
278 rstate->states[EG_RASTERIZER__PA_CL_GB_VERT_CLIP_ADJ] = 0x3F800000;
279 rstate->states[EG_RASTERIZER__PA_CL_GB_VERT_DISC_ADJ] = 0x3F800000;
280 rstate->states[EG_RASTERIZER__PA_CL_GB_HORZ_CLIP_ADJ] = 0x3F800000;
281 rstate->states[EG_RASTERIZER__PA_CL_GB_HORZ_DISC_ADJ] = 0x3F800000;
282 rstate->states[EG_RASTERIZER__PA_SU_POLY_OFFSET_DB_FMT_CNTL] = offset_db_fmt_cntl;
283 rstate->states[EG_RASTERIZER__PA_SU_POLY_OFFSET_CLAMP] = 0x00000000;
284 rstate->states[EG_RASTERIZER__PA_SU_POLY_OFFSET_FRONT_SCALE] = fui(offset_scale);
285 rstate->states[EG_RASTERIZER__PA_SU_POLY_OFFSET_FRONT_OFFSET] = fui(offset_units);
286 rstate->states[EG_RASTERIZER__PA_SU_POLY_OFFSET_BACK_SCALE] = fui(offset_scale);
287 rstate->states[EG_RASTERIZER__PA_SU_POLY_OFFSET_BACK_OFFSET] = fui(offset_units);
288 radeon_state_pm4(rstate);
289 }
290
291 static void eg_scissor(struct r600_context *rctx, struct radeon_state *rstate)
292 {
293 const struct pipe_scissor_state *state = &rctx->scissor->state.scissor;
294 const struct pipe_framebuffer_state *fb = &rctx->framebuffer->state.framebuffer;
295 struct r600_screen *rscreen = rctx->screen;
296 unsigned minx, maxx, miny, maxy;
297 u32 tl, br;
298
299 if (state == NULL) {
300 minx = 0;
301 miny = 0;
302 maxx = fb->cbufs[0]->width;
303 maxy = fb->cbufs[0]->height;
304 } else {
305 minx = state->minx;
306 miny = state->miny;
307 maxx = state->maxx;
308 maxy = state->maxy;
309 }
310 tl = S_028240_TL_X(minx) | S_028240_TL_Y(miny);
311 br = S_028244_BR_X(maxx) | S_028244_BR_Y(maxy);
312 radeon_state_init(rstate, rscreen->rw, R600_STATE_SCISSOR, 0, 0);
313 /* screen scissor has no WINDOW OFFSET */
314 rstate->states[EG_SCISSOR__PA_SC_SCREEN_SCISSOR_TL] = tl;
315 rstate->states[EG_SCISSOR__PA_SC_SCREEN_SCISSOR_BR] = br;
316 rstate->states[EG_SCISSOR__PA_SC_WINDOW_OFFSET] = 0x00000000;
317 rstate->states[EG_SCISSOR__PA_SC_WINDOW_SCISSOR_TL] = tl | S_028204_WINDOW_OFFSET_DISABLE(1);
318 rstate->states[EG_SCISSOR__PA_SC_WINDOW_SCISSOR_BR] = br;
319 rstate->states[EG_SCISSOR__PA_SC_CLIPRECT_RULE] = 0x0000FFFF;
320 rstate->states[EG_SCISSOR__PA_SC_CLIPRECT_0_TL] = tl;
321 rstate->states[EG_SCISSOR__PA_SC_CLIPRECT_0_BR] = br;
322 rstate->states[EG_SCISSOR__PA_SC_CLIPRECT_1_TL] = tl;
323 rstate->states[EG_SCISSOR__PA_SC_CLIPRECT_1_BR] = br;
324 rstate->states[EG_SCISSOR__PA_SC_CLIPRECT_2_TL] = tl;
325 rstate->states[EG_SCISSOR__PA_SC_CLIPRECT_2_BR] = br;
326 rstate->states[EG_SCISSOR__PA_SC_CLIPRECT_3_TL] = tl;
327 rstate->states[EG_SCISSOR__PA_SC_CLIPRECT_3_BR] = br;
328 rstate->states[EG_SCISSOR__PA_SC_EDGERULE] = 0xAAAAAAAA;
329 rstate->states[EG_SCISSOR__PA_SC_GENERIC_SCISSOR_TL] = tl | S_028240_WINDOW_OFFSET_DISABLE(1);
330 rstate->states[EG_SCISSOR__PA_SC_GENERIC_SCISSOR_BR] = br;
331 rstate->states[EG_SCISSOR__PA_SC_VPORT_SCISSOR_0_TL] = tl | S_028240_WINDOW_OFFSET_DISABLE(1);
332 rstate->states[EG_SCISSOR__PA_SC_VPORT_SCISSOR_0_BR] = br;
333 radeon_state_pm4(rstate);
334 }
335
336 static void eg_viewport(struct r600_context *rctx, struct radeon_state *rstate, const struct pipe_viewport_state *state)
337 {
338 struct r600_screen *rscreen = rctx->screen;
339
340 radeon_state_init(rstate, rscreen->rw, R600_STATE_VIEWPORT, 0, 0);
341 rstate->states[EG_VIEWPORT__PA_SC_VPORT_ZMIN_0] = 0x00000000;
342 rstate->states[EG_VIEWPORT__PA_SC_VPORT_ZMAX_0] = 0x3F800000;
343 rstate->states[EG_VIEWPORT__PA_CL_VPORT_XSCALE_0] = fui(state->scale[0]);
344 rstate->states[EG_VIEWPORT__PA_CL_VPORT_YSCALE_0] = fui(state->scale[1]);
345 rstate->states[EG_VIEWPORT__PA_CL_VPORT_ZSCALE_0] = fui(state->scale[2]);
346 rstate->states[EG_VIEWPORT__PA_CL_VPORT_XOFFSET_0] = fui(state->translate[0]);
347 rstate->states[EG_VIEWPORT__PA_CL_VPORT_YOFFSET_0] = fui(state->translate[1]);
348 rstate->states[EG_VIEWPORT__PA_CL_VPORT_ZOFFSET_0] = fui(state->translate[2]);
349 rstate->states[EG_VIEWPORT__PA_CL_VTE_CNTL] = 0x0000043F;
350 radeon_state_pm4(rstate);
351 }
352
353 static void eg_dsa(struct r600_context *rctx, struct radeon_state *rstate)
354 {
355 const struct pipe_depth_stencil_alpha_state *state = &rctx->dsa->state.dsa;
356 const struct pipe_stencil_ref *stencil_ref = &rctx->stencil_ref->state.stencil_ref;
357 struct r600_screen *rscreen = rctx->screen;
358 unsigned db_depth_control, alpha_test_control, alpha_ref, db_shader_control;
359 unsigned stencil_ref_mask, stencil_ref_mask_bf, db_render_override, db_render_control;
360 struct r600_shader *rshader;
361 struct r600_query *rquery;
362 boolean query_running;
363 int i;
364
365 if (rctx->ps_shader == NULL) {
366 return;
367 }
368 radeon_state_init(rstate, rscreen->rw, R600_STATE_DSA, 0, 0);
369
370 db_shader_control = 0x210;
371 rshader = &rctx->ps_shader->shader;
372 if (rshader->uses_kill)
373 db_shader_control |= (1 << 6);
374 for (i = 0; i < rshader->noutput; i++) {
375 if (rshader->output[i].name == TGSI_SEMANTIC_POSITION)
376 db_shader_control |= 1;
377 }
378 stencil_ref_mask = 0;
379 stencil_ref_mask_bf = 0;
380 db_depth_control = S_028800_Z_ENABLE(state->depth.enabled) |
381 S_028800_Z_WRITE_ENABLE(state->depth.writemask) |
382 S_028800_ZFUNC(state->depth.func);
383 /* set stencil enable */
384
385 if (state->stencil[0].enabled) {
386 db_depth_control |= S_028800_STENCIL_ENABLE(1);
387 db_depth_control |= S_028800_STENCILFUNC(r600_translate_ds_func(state->stencil[0].func));
388 db_depth_control |= S_028800_STENCILFAIL(r600_translate_stencil_op(state->stencil[0].fail_op));
389 db_depth_control |= S_028800_STENCILZPASS(r600_translate_stencil_op(state->stencil[0].zpass_op));
390 db_depth_control |= S_028800_STENCILZFAIL(r600_translate_stencil_op(state->stencil[0].zfail_op));
391
392 stencil_ref_mask = S_028430_STENCILMASK(state->stencil[0].valuemask) |
393 S_028430_STENCILWRITEMASK(state->stencil[0].writemask);
394 stencil_ref_mask |= S_028430_STENCILREF(stencil_ref->ref_value[0]);
395 if (state->stencil[1].enabled) {
396 db_depth_control |= S_028800_BACKFACE_ENABLE(1);
397 db_depth_control |= S_028800_STENCILFUNC_BF(r600_translate_ds_func(state->stencil[1].func));
398 db_depth_control |= S_028800_STENCILFAIL_BF(r600_translate_stencil_op(state->stencil[1].fail_op));
399 db_depth_control |= S_028800_STENCILZPASS_BF(r600_translate_stencil_op(state->stencil[1].zpass_op));
400 db_depth_control |= S_028800_STENCILZFAIL_BF(r600_translate_stencil_op(state->stencil[1].zfail_op));
401 stencil_ref_mask_bf = S_028434_STENCILMASK_BF(state->stencil[1].valuemask) |
402 S_028434_STENCILWRITEMASK_BF(state->stencil[1].writemask);
403 stencil_ref_mask_bf |= S_028430_STENCILREF(stencil_ref->ref_value[1]);
404 }
405 }
406
407 alpha_test_control = 0;
408 alpha_ref = 0;
409 if (state->alpha.enabled) {
410 alpha_test_control = S_028410_ALPHA_FUNC(state->alpha.func);
411 alpha_test_control |= S_028410_ALPHA_TEST_ENABLE(1);
412 alpha_ref = fui(state->alpha.ref_value);
413 }
414
415 db_render_control = 0;
416 /// db_render_control = S_028D0C_STENCIL_COMPRESS_DISABLE(1) |
417 /// S_028D0C_DEPTH_COMPRESS_DISABLE(1);
418 db_render_override = S_028D10_FORCE_HIZ_ENABLE(V_028D10_FORCE_DISABLE) |
419 S_028D10_FORCE_HIS_ENABLE0(V_028D10_FORCE_DISABLE) |
420 S_028D10_FORCE_HIS_ENABLE1(V_028D10_FORCE_DISABLE);
421
422 query_running = false;
423
424 LIST_FOR_EACH_ENTRY(rquery, &rctx->query_list, list) {
425 if (rquery->state & R600_QUERY_STATE_STARTED) {
426 query_running = true;
427 }
428 }
429
430 if (query_running) {
431 db_render_override |= S_028D10_NOOP_CULL_DISABLE(1);
432 db_render_control |= S_028D0C_PERFECT_ZPASS_COUNTS(1);
433 }
434
435 rstate->states[EG_DSA__DB_STENCIL_CLEAR] = 0x00000000;
436 rstate->states[EG_DSA__DB_DEPTH_CLEAR] = 0x3F800000;
437 rstate->states[EG_DSA__SX_ALPHA_TEST_CONTROL] = alpha_test_control;
438 rstate->states[EG_DSA__DB_STENCILREFMASK] = stencil_ref_mask;
439 rstate->states[EG_DSA__DB_STENCILREFMASK_BF] = stencil_ref_mask_bf;
440 rstate->states[EG_DSA__SX_ALPHA_REF] = alpha_ref;
441 // rstate->states[EG_DSA__SPI_FOG_FUNC_SCALE] = 0x00000000;
442 // rstate->states[EG_DSA__SPI_FOG_FUNC_BIAS] = 0x00000000;
443 rstate->states[EG_DSA__SPI_FOG_CNTL] = 0x00000000;
444 rstate->states[EG_DSA__DB_DEPTH_CONTROL] = db_depth_control;
445 rstate->states[EG_DSA__DB_SHADER_CONTROL] = db_shader_control;
446 rstate->states[EG_DSA__DB_RENDER_CONTROL] = db_render_control;
447 rstate->states[EG_DSA__DB_RENDER_OVERRIDE] = db_render_override;
448
449 rstate->states[EG_DSA__DB_SRESULTS_COMPARE_STATE1] = 0x00000000;
450 rstate->states[EG_DSA__DB_PRELOAD_CONTROL] = 0x00000000;
451 rstate->states[EG_DSA__DB_ALPHA_TO_MASK] = 0x0000AA00;
452 radeon_state_pm4(rstate);
453 }
454
455
456 static INLINE u32 S_FIXED(float value, u32 frac_bits)
457 {
458 return value * (1 << frac_bits);
459 }
460
461 static void eg_sampler_border(struct r600_context *rctx, struct radeon_state *rstate,
462 const struct pipe_sampler_state *state, unsigned id)
463 {
464 struct r600_screen *rscreen = rctx->screen;
465 union util_color uc;
466
467 util_pack_color(state->border_color, PIPE_FORMAT_B8G8R8A8_UNORM, &uc);
468
469 radeon_state_init(rstate, rscreen->rw, R600_STATE_SAMPLER_BORDER, id, R600_SHADER_PS);
470 if (uc.ui) {
471 rstate->states[EG_PS_SAMPLER_BORDER__TD_PS_SAMPLER0_BORDER_RED] = fui(state->border_color[0]);
472 rstate->states[EG_PS_SAMPLER_BORDER__TD_PS_SAMPLER0_BORDER_GREEN] = fui(state->border_color[1]);
473 rstate->states[EG_PS_SAMPLER_BORDER__TD_PS_SAMPLER0_BORDER_BLUE] = fui(state->border_color[2]);
474 rstate->states[EG_PS_SAMPLER_BORDER__TD_PS_SAMPLER0_BORDER_ALPHA] = fui(state->border_color[3]);
475 }
476 radeon_state_pm4(rstate);
477 }
478
479 static void eg_sampler(struct r600_context *rctx, struct radeon_state *rstate,
480 const struct pipe_sampler_state *state, unsigned id)
481 {
482 struct r600_screen *rscreen = rctx->screen;
483 union util_color uc;
484
485 util_pack_color(state->border_color, PIPE_FORMAT_B8G8R8A8_UNORM, &uc);
486
487 radeon_state_init(rstate, rscreen->rw, R600_STATE_SAMPLER, id, R600_SHADER_PS);
488 rstate->states[EG_PS_SAMPLER__SQ_TEX_SAMPLER_WORD0_0] =
489 S_03C000_CLAMP_X(r600_tex_wrap(state->wrap_s)) |
490 S_03C000_CLAMP_Y(r600_tex_wrap(state->wrap_t)) |
491 S_03C000_CLAMP_Z(r600_tex_wrap(state->wrap_r)) |
492 S_03C000_XY_MAG_FILTER(r600_tex_filter(state->mag_img_filter)) |
493 S_03C000_XY_MIN_FILTER(r600_tex_filter(state->min_img_filter)) |
494 S_03C000_MIP_FILTER(r600_tex_mipfilter(state->min_mip_filter)) |
495 S_03C000_DEPTH_COMPARE_FUNCTION(r600_tex_compare(state->compare_func)) |
496 S_03C000_BORDER_COLOR_TYPE(uc.ui ? V_03C000_SQ_TEX_BORDER_COLOR_REGISTER : 0);
497 /* FIXME LOD it depends on texture base level ... */
498 rstate->states[EG_PS_SAMPLER__SQ_TEX_SAMPLER_WORD1_0] =
499 S_03C004_MIN_LOD(S_FIXED(CLAMP(state->min_lod, 0, 15), 6)) |
500 S_03C004_MAX_LOD(S_FIXED(CLAMP(state->max_lod, 0, 15), 6));
501
502 rstate->states[EG_PS_SAMPLER__SQ_TEX_SAMPLER_WORD2_0] =
503 S_03C008_LOD_BIAS(S_FIXED(CLAMP(state->lod_bias, -16, 16), 6)) |
504 S_03C008_TYPE(1);
505 radeon_state_pm4(rstate);
506
507 }
508
509
510 static void eg_resource(struct pipe_context *ctx, struct radeon_state *rstate,
511 const struct pipe_sampler_view *view, unsigned id)
512 {
513 struct r600_context *rctx = r600_context(ctx);
514 struct r600_screen *rscreen = rctx->screen;
515 const struct util_format_description *desc;
516 struct r600_resource_texture *tmp;
517 struct r600_resource *rbuffer;
518 unsigned format;
519 uint32_t word4 = 0, yuv_format = 0, pitch = 0;
520 unsigned char swizzle[4];
521 int r;
522
523 rstate->cpm4 = 0;
524 swizzle[0] = view->swizzle_r;
525 swizzle[1] = view->swizzle_g;
526 swizzle[2] = view->swizzle_b;
527 swizzle[3] = view->swizzle_a;
528 format = r600_translate_texformat(view->texture->format,
529 swizzle,
530 &word4, &yuv_format);
531 if (format == ~0) {
532 return;
533 }
534 desc = util_format_description(view->texture->format);
535 if (desc == NULL) {
536 R600_ERR("unknow format %d\n", view->texture->format);
537 return;
538 }
539 radeon_state_init(rstate, rscreen->rw, R600_STATE_RESOURCE, id, R600_SHADER_PS);
540 tmp = (struct r600_resource_texture*)view->texture;
541 rbuffer = &tmp->resource;
542 if (tmp->depth) {
543 r = r600_texture_from_depth(ctx, tmp, view->first_level);
544 if (r) {
545 return;
546 }
547 rstate->bo[0] = radeon_bo_incref(rscreen->rw, tmp->uncompressed);
548 rstate->bo[1] = radeon_bo_incref(rscreen->rw, tmp->uncompressed);
549 } else {
550 rstate->bo[0] = radeon_bo_incref(rscreen->rw, rbuffer->bo);
551 rstate->bo[1] = radeon_bo_incref(rscreen->rw, rbuffer->bo);
552 }
553 rstate->nbo = 2;
554 rstate->placement[0] = RADEON_GEM_DOMAIN_GTT;
555 rstate->placement[1] = RADEON_GEM_DOMAIN_GTT;
556 rstate->placement[2] = RADEON_GEM_DOMAIN_GTT;
557 rstate->placement[3] = RADEON_GEM_DOMAIN_GTT;
558
559 pitch = (tmp->pitch[0] / tmp->bpt);
560 pitch = (pitch + 0x7) & ~0x7;
561
562 /* FIXME properly handle first level != 0 */
563 rstate->states[EG_PS_RESOURCE__RESOURCE0_WORD0] =
564 S_030000_DIM(r600_tex_dim(view->texture->target)) |
565 S_030000_PITCH((pitch / 8) - 1) |
566 S_030000_TEX_WIDTH(view->texture->width0 - 1);
567 rstate->states[EG_PS_RESOURCE__RESOURCE0_WORD1] =
568 S_030004_TEX_HEIGHT(view->texture->height0 - 1) |
569 S_030004_TEX_DEPTH(view->texture->depth0 - 1);
570 rstate->states[EG_PS_RESOURCE__RESOURCE0_WORD2] = tmp->offset[0] >> 8;
571 rstate->states[EG_PS_RESOURCE__RESOURCE0_WORD3] = tmp->offset[1] >> 8;
572 rstate->states[EG_PS_RESOURCE__RESOURCE0_WORD4] =
573 word4 |
574 S_030010_NUM_FORMAT_ALL(V_030010_SQ_NUM_FORMAT_NORM) |
575 S_030010_SRF_MODE_ALL(V_030010_SFR_MODE_NO_ZERO) |
576 S_030010_REQUEST_SIZE(1) |
577 S_030010_BASE_LEVEL(view->first_level);
578 rstate->states[EG_PS_RESOURCE__RESOURCE0_WORD5] =
579 S_030014_LAST_LEVEL(view->last_level) |
580 S_030014_BASE_ARRAY(0) |
581 S_030014_LAST_ARRAY(0);
582 rstate->states[EG_PS_RESOURCE__RESOURCE0_WORD6] = 0;
583 rstate->states[EG_PS_RESOURCE__RESOURCE0_WORD7] =
584 S_03001C_DATA_FORMAT(format) |
585 S_03001C_TYPE(V_03001C_SQ_TEX_VTX_VALID_TEXTURE);
586 radeon_state_pm4(rstate);
587 }
588
589 static void eg_cb_cntl(struct r600_context *rctx, struct radeon_state *rstate)
590 {
591 struct r600_screen *rscreen = rctx->screen;
592 const struct pipe_blend_state *pbs = &rctx->blend->state.blend;
593 int nr_cbufs = rctx->framebuffer->state.framebuffer.nr_cbufs;
594 uint32_t color_control, target_mask, shader_mask;
595 int i;
596
597 target_mask = 0;
598 shader_mask = 0;
599 color_control = S_028808_MODE(1);
600
601 for (i = 0; i < nr_cbufs; i++) {
602 shader_mask |= 0xf << (i * 4);
603 }
604
605 if (pbs->logicop_enable) {
606 color_control |= (pbs->logicop_func << 16) | (pbs->logicop_func << 20);
607 } else {
608 color_control |= (0xcc << 16);
609 }
610
611 if (pbs->independent_blend_enable) {
612 for (i = 0; i < nr_cbufs; i++) {
613 target_mask |= (pbs->rt[i].colormask << (4 * i));
614 }
615 } else {
616 for (i = 0; i < nr_cbufs; i++) {
617 target_mask |= (pbs->rt[0].colormask << (4 * i));
618 }
619 }
620 radeon_state_init(rstate, rscreen->rw, R600_STATE_CB_CNTL, 0, 0);
621 rstate->states[EG_CB_CNTL__CB_SHADER_MASK] = shader_mask;
622 rstate->states[EG_CB_CNTL__CB_TARGET_MASK] = target_mask;
623 rstate->states[EG_CB_CNTL__CB_COLOR_CONTROL] = color_control;
624 rstate->states[EG_CB_CNTL__PA_SC_AA_CONFIG] = 0x00000000;
625 rstate->states[EG_CB_CNTL__PA_SC_AA_SAMPLE_LOCS_MCTX] = 0x00000000;
626 rstate->states[EG_CB_CNTL__PA_SC_AA_MASK] = 0xFFFFFFFF;
627 radeon_state_pm4(rstate);
628 }
629
630
631 static void eg_init_config(struct r600_context *rctx)
632 {
633 int ps_prio;
634 int vs_prio;
635 int gs_prio;
636 int es_prio;
637 int hs_prio, cs_prio, ls_prio;
638 int num_ps_gprs;
639 int num_vs_gprs;
640 int num_gs_gprs;
641 int num_es_gprs;
642 int num_hs_gprs;
643 int num_ls_gprs;
644 int num_temp_gprs;
645 int num_ps_threads;
646 int num_vs_threads;
647 int num_gs_threads;
648 int num_es_threads;
649 int num_hs_threads;
650 int num_ls_threads;
651 int num_ps_stack_entries;
652 int num_vs_stack_entries;
653 int num_gs_stack_entries;
654 int num_es_stack_entries;
655 int num_hs_stack_entries;
656 int num_ls_stack_entries;
657 enum radeon_family family;
658
659 family = radeon_get_family(rctx->rw);
660 ps_prio = 0;
661 vs_prio = 1;
662 gs_prio = 2;
663 es_prio = 3;
664 hs_prio = 0;
665 ls_prio = 0;
666 cs_prio = 0;
667
668 switch (family) {
669 case CHIP_CEDAR:
670 default:
671 num_ps_gprs = 93;
672 num_vs_gprs = 46;
673 num_temp_gprs = 4;
674 num_gs_gprs = 31;
675 num_es_gprs = 31;
676 num_hs_gprs = 23;
677 num_ls_gprs = 23;
678 num_ps_threads = 96;
679 num_vs_threads = 16;
680 num_gs_threads = 16;
681 num_es_threads = 16;
682 num_hs_threads = 16;
683 num_ls_threads = 16;
684 num_ps_stack_entries = 42;
685 num_vs_stack_entries = 42;
686 num_gs_stack_entries = 42;
687 num_es_stack_entries = 42;
688 num_hs_stack_entries = 42;
689 num_ls_stack_entries = 42;
690 break;
691 case CHIP_REDWOOD:
692 num_ps_gprs = 93;
693 num_vs_gprs = 46;
694 num_temp_gprs = 4;
695 num_gs_gprs = 31;
696 num_es_gprs = 31;
697 num_hs_gprs = 23;
698 num_ls_gprs = 23;
699 num_ps_threads = 128;
700 num_vs_threads = 20;
701 num_gs_threads = 20;
702 num_es_threads = 20;
703 num_hs_threads = 20;
704 num_ls_threads = 20;
705 num_ps_stack_entries = 42;
706 num_vs_stack_entries = 42;
707 num_gs_stack_entries = 42;
708 num_es_stack_entries = 42;
709 num_hs_stack_entries = 42;
710 num_ls_stack_entries = 42;
711 break;
712 case CHIP_JUNIPER:
713 num_ps_gprs = 93;
714 num_vs_gprs = 46;
715 num_temp_gprs = 4;
716 num_gs_gprs = 31;
717 num_es_gprs = 31;
718 num_hs_gprs = 23;
719 num_ls_gprs = 23;
720 num_ps_threads = 128;
721 num_vs_threads = 20;
722 num_gs_threads = 20;
723 num_es_threads = 20;
724 num_hs_threads = 20;
725 num_ls_threads = 20;
726 num_ps_stack_entries = 85;
727 num_vs_stack_entries = 85;
728 num_gs_stack_entries = 85;
729 num_es_stack_entries = 85;
730 num_hs_stack_entries = 85;
731 num_ls_stack_entries = 85;
732 break;
733 case CHIP_CYPRESS:
734 case CHIP_HEMLOCK:
735 num_ps_gprs = 93;
736 num_vs_gprs = 46;
737 num_temp_gprs = 4;
738 num_gs_gprs = 31;
739 num_es_gprs = 31;
740 num_hs_gprs = 23;
741 num_ls_gprs = 23;
742 num_ps_threads = 128;
743 num_vs_threads = 20;
744 num_gs_threads = 20;
745 num_es_threads = 20;
746 num_hs_threads = 20;
747 num_ls_threads = 20;
748 num_ps_stack_entries = 85;
749 num_vs_stack_entries = 85;
750 num_gs_stack_entries = 85;
751 num_es_stack_entries = 85;
752 num_hs_stack_entries = 85;
753 num_ls_stack_entries = 85;
754 break;
755 }
756
757 radeon_state_init(&rctx->config, rctx->rw, R600_STATE_CONFIG, 0, 0);
758
759 rctx->config.states[EG_CONFIG__SQ_CONFIG] = 0x00000000;
760 switch (family) {
761 case CHIP_CEDAR:
762 break;
763 default:
764 rctx->config.states[EG_CONFIG__SQ_CONFIG] |= S_008C00_VC_ENABLE(1);
765 break;
766 }
767 rctx->config.states[EG_CONFIG__SQ_CONFIG] |= S_008C00_EXPORT_SRC_C(1);
768 rctx->config.states[EG_CONFIG__SQ_CONFIG] |= S_008C00_CS_PRIO(cs_prio);
769 rctx->config.states[EG_CONFIG__SQ_CONFIG] |= S_008C00_LS_PRIO(ls_prio);
770 rctx->config.states[EG_CONFIG__SQ_CONFIG] |= S_008C00_HS_PRIO(hs_prio);
771 rctx->config.states[EG_CONFIG__SQ_CONFIG] |= S_008C00_PS_PRIO(ps_prio);
772 rctx->config.states[EG_CONFIG__SQ_CONFIG] |= S_008C00_VS_PRIO(vs_prio);
773 rctx->config.states[EG_CONFIG__SQ_CONFIG] |= S_008C00_GS_PRIO(gs_prio);
774 rctx->config.states[EG_CONFIG__SQ_CONFIG] |= S_008C00_ES_PRIO(es_prio);
775
776 rctx->config.states[EG_CONFIG__SQ_GPR_RESOURCE_MGMT_1] = 0;
777 rctx->config.states[EG_CONFIG__SQ_GPR_RESOURCE_MGMT_1] |= S_008C04_NUM_PS_GPRS(num_ps_gprs);
778 rctx->config.states[EG_CONFIG__SQ_GPR_RESOURCE_MGMT_1] |= S_008C04_NUM_VS_GPRS(num_vs_gprs);
779 rctx->config.states[EG_CONFIG__SQ_GPR_RESOURCE_MGMT_1] |= S_008C04_NUM_CLAUSE_TEMP_GPRS(num_temp_gprs);
780
781 rctx->config.states[EG_CONFIG__SQ_GPR_RESOURCE_MGMT_2] = 0;
782 rctx->config.states[EG_CONFIG__SQ_GPR_RESOURCE_MGMT_2] |= S_008C08_NUM_GS_GPRS(num_gs_gprs);
783 rctx->config.states[EG_CONFIG__SQ_GPR_RESOURCE_MGMT_2] |= S_008C08_NUM_ES_GPRS(num_es_gprs);
784
785 rctx->config.states[EG_CONFIG__SQ_GPR_RESOURCE_MGMT_3] = 0;
786 rctx->config.states[EG_CONFIG__SQ_GPR_RESOURCE_MGMT_3] |= S_008C0C_NUM_HS_GPRS(num_hs_gprs);
787 rctx->config.states[EG_CONFIG__SQ_GPR_RESOURCE_MGMT_3] |= S_008C0C_NUM_LS_GPRS(num_ls_gprs);
788
789 rctx->config.states[EG_CONFIG__SQ_THREAD_RESOURCE_MGMT_1] = 0;
790 rctx->config.states[EG_CONFIG__SQ_THREAD_RESOURCE_MGMT_1] |= S_008C18_NUM_PS_THREADS(num_ps_threads);
791 rctx->config.states[EG_CONFIG__SQ_THREAD_RESOURCE_MGMT_1] |= S_008C18_NUM_VS_THREADS(num_vs_threads);
792 rctx->config.states[EG_CONFIG__SQ_THREAD_RESOURCE_MGMT_1] |= S_008C18_NUM_GS_THREADS(num_gs_threads);
793 rctx->config.states[EG_CONFIG__SQ_THREAD_RESOURCE_MGMT_1] |= S_008C18_NUM_ES_THREADS(num_es_threads);
794
795 rctx->config.states[EG_CONFIG__SQ_THREAD_RESOURCE_MGMT_2] = 0;
796 rctx->config.states[EG_CONFIG__SQ_THREAD_RESOURCE_MGMT_2] |= S_008C1C_NUM_HS_THREADS(num_hs_threads);
797 rctx->config.states[EG_CONFIG__SQ_THREAD_RESOURCE_MGMT_2] |= S_008C1C_NUM_LS_THREADS(num_ls_threads);
798
799 rctx->config.states[EG_CONFIG__SQ_STACK_RESOURCE_MGMT_1] = 0;
800 rctx->config.states[EG_CONFIG__SQ_STACK_RESOURCE_MGMT_1] |= S_008C20_NUM_PS_STACK_ENTRIES(num_ps_stack_entries);
801 rctx->config.states[EG_CONFIG__SQ_STACK_RESOURCE_MGMT_1] |= S_008C20_NUM_VS_STACK_ENTRIES(num_vs_stack_entries);
802
803 rctx->config.states[EG_CONFIG__SQ_STACK_RESOURCE_MGMT_2] = 0;
804 rctx->config.states[EG_CONFIG__SQ_STACK_RESOURCE_MGMT_2] |= S_008C24_NUM_GS_STACK_ENTRIES(num_gs_stack_entries);
805 rctx->config.states[EG_CONFIG__SQ_STACK_RESOURCE_MGMT_2] |= S_008C24_NUM_ES_STACK_ENTRIES(num_es_stack_entries);
806
807 rctx->config.states[EG_CONFIG__SQ_STACK_RESOURCE_MGMT_3] = 0;
808 rctx->config.states[EG_CONFIG__SQ_STACK_RESOURCE_MGMT_3] |= S_008C28_NUM_HS_STACK_ENTRIES(num_hs_stack_entries);
809 rctx->config.states[EG_CONFIG__SQ_STACK_RESOURCE_MGMT_3] |= S_008C28_NUM_LS_STACK_ENTRIES(num_ls_stack_entries);
810
811 rctx->config.states[EG_CONFIG__SPI_CONFIG_CNTL] = 0x00000000;
812 rctx->config.states[EG_CONFIG__SPI_CONFIG_CNTL_1] = S_00913C_VTX_DONE_DELAY(4);
813
814 rctx->config.states[EG_CONFIG__SX_MISC] = 0x00000000;
815
816 rctx->config.states[EG_CONFIG__SQ_DYN_GPR_CNTL_PS_FLUSH_REQ] = 0x00000000;
817 rctx->config.states[EG_CONFIG__PA_SC_MODE_CNTL_0] = 0x0;
818 rctx->config.states[EG_CONFIG__PA_SC_MODE_CNTL_1] = 0x0;
819
820 rctx->config.states[EG_CONFIG__SQ_ESGS_RING_ITEMSIZE] = 0x00000000;
821 rctx->config.states[EG_CONFIG__SQ_GSVS_RING_ITEMSIZE] = 0x00000000;
822 rctx->config.states[EG_CONFIG__SQ_ESTMP_RING_ITEMSIZE] = 0x00000000;
823 rctx->config.states[EG_CONFIG__SQ_GSTMP_RING_ITEMSIZE] = 0x00000000;
824 rctx->config.states[EG_CONFIG__SQ_VSTMP_RING_ITEMSIZE] = 0x00000000;
825 rctx->config.states[EG_CONFIG__SQ_PSTMP_RING_ITEMSIZE] = 0x00000000;
826
827 rctx->config.states[EG_CONFIG__SQ_GS_VERT_ITEMSIZE] = 0x00000000;
828 rctx->config.states[EG_CONFIG__SQ_GS_VERT_ITEMSIZE_1] = 0x00000000;
829 rctx->config.states[EG_CONFIG__SQ_GS_VERT_ITEMSIZE_2] = 0x00000000;
830 rctx->config.states[EG_CONFIG__SQ_GS_VERT_ITEMSIZE_3] = 0x00000000;
831
832 rctx->config.states[EG_CONFIG__VGT_OUTPUT_PATH_CNTL] = 0x00000000;
833 rctx->config.states[EG_CONFIG__VGT_HOS_CNTL] = 0x00000000;
834 rctx->config.states[EG_CONFIG__VGT_HOS_MAX_TESS_LEVEL] = 0x00000000;
835 rctx->config.states[EG_CONFIG__VGT_HOS_MIN_TESS_LEVEL] = 0x00000000;
836 rctx->config.states[EG_CONFIG__VGT_HOS_REUSE_DEPTH] = 0x00000000;
837 rctx->config.states[EG_CONFIG__VGT_GROUP_PRIM_TYPE] = 0x00000000;
838 rctx->config.states[EG_CONFIG__VGT_GROUP_FIRST_DECR] = 0x00000000;
839 rctx->config.states[EG_CONFIG__VGT_GROUP_DECR] = 0x00000000;
840 rctx->config.states[EG_CONFIG__VGT_GROUP_VECT_0_CNTL] = 0x00000000;
841 rctx->config.states[EG_CONFIG__VGT_GROUP_VECT_1_CNTL] = 0x00000000;
842 rctx->config.states[EG_CONFIG__VGT_GROUP_VECT_0_FMT_CNTL] = 0x00000000;
843 rctx->config.states[EG_CONFIG__VGT_GROUP_VECT_1_FMT_CNTL] = 0x00000000;
844 rctx->config.states[EG_CONFIG__VGT_GS_MODE] = 0x00000000;
845 rctx->config.states[EG_CONFIG__VGT_STRMOUT_CONFIG] = 0x00000000;
846 rctx->config.states[EG_CONFIG__VGT_STRMOUT_BUFFER_CONFIG] = 0x00000000;
847 rctx->config.states[EG_CONFIG__VGT_REUSE_OFF] = 0x00000001;
848 rctx->config.states[EG_CONFIG__VGT_VTX_CNT_EN] = 0x00000000;
849 // rctx->config.states[EG_CONFIG__VGT_CACHE_INVALIDATION] = 0x2;
850 // rctx->config.states[EG_CONFIG__VGT_GS_VERTEX_REUSE] = 0x16;
851 rctx->config.states[EG_CONFIG__PA_CL_ENHANCE] = (3 << 1) | 1;
852
853 radeon_state_pm4(&rctx->config);
854 }
855
856 static int eg_vs_resource(struct r600_context *rctx, int id, struct r600_resource *rbuffer, uint32_t offset,
857 uint32_t stride, uint32_t format)
858 {
859 struct radeon_state *vs_resource = &rctx->vs_resource[id];
860 struct r600_screen *rscreen = rctx->screen;
861
862 radeon_state_init(vs_resource, rscreen->rw, R600_STATE_RESOURCE, id, R600_SHADER_VS);
863 vs_resource->bo[0] = radeon_bo_incref(rscreen->rw, rbuffer->bo);
864 vs_resource->nbo = 1;
865 vs_resource->states[EG_PS_RESOURCE__RESOURCE0_WORD0] = offset;
866 vs_resource->states[EG_PS_RESOURCE__RESOURCE0_WORD1] = rbuffer->bo->size - offset - 1;
867 vs_resource->states[EG_PS_RESOURCE__RESOURCE0_WORD2] = S_030008_STRIDE(stride) |
868 S_030008_DATA_FORMAT(format);
869 vs_resource->states[EG_PS_RESOURCE__RESOURCE0_WORD3] = S_03000C_DST_SEL_X(V_03000C_SQ_SEL_X) |
870 S_03000C_DST_SEL_Y(V_03000C_SQ_SEL_Y) |
871 S_03000C_DST_SEL_Z(V_03000C_SQ_SEL_Z) |
872 S_03000C_DST_SEL_W(V_03000C_SQ_SEL_W);
873
874 vs_resource->states[EG_PS_RESOURCE__RESOURCE0_WORD4] = 0x00000000;
875 vs_resource->states[EG_PS_RESOURCE__RESOURCE0_WORD5] = 0x00000000;
876 vs_resource->states[EG_PS_RESOURCE__RESOURCE0_WORD6] = 0x00000000;
877 vs_resource->states[EG_PS_RESOURCE__RESOURCE0_WORD7] = 0xC0000000;
878 vs_resource->placement[0] = RADEON_GEM_DOMAIN_GTT;
879 vs_resource->placement[1] = RADEON_GEM_DOMAIN_GTT;
880 return radeon_state_pm4(vs_resource);
881 }
882
883 static int eg_draw_vgt_init(struct r600_context *rctx, struct radeon_state *draw,
884 struct r600_resource *rbuffer,
885 uint32_t count, int vgt_draw_initiator)
886 {
887 struct r600_screen *rscreen = rctx->screen;
888
889 radeon_state_init(draw, rscreen->rw, R600_STATE_DRAW, 0, 0);
890 draw->states[EG_DRAW__VGT_NUM_INDICES] = count;
891 draw->states[EG_DRAW__VGT_DRAW_INITIATOR] = vgt_draw_initiator;
892 if (rbuffer) {
893 draw->bo[0] = radeon_bo_incref(rscreen->rw, rbuffer->bo);
894 draw->placement[0] = RADEON_GEM_DOMAIN_GTT;
895 draw->placement[1] = RADEON_GEM_DOMAIN_GTT;
896 draw->nbo = 1;
897 }
898 return radeon_state_pm4(draw);
899 }
900
901 static int eg_draw_vgt_prim(struct r600_context *rctx, struct radeon_state *vgt,
902 uint32_t prim, uint32_t start, uint32_t vgt_dma_index_type)
903 {
904 struct r600_screen *rscreen = rctx->screen;
905 radeon_state_init(vgt, rscreen->rw, R600_STATE_VGT, 0, 0);
906 vgt->states[EG_VGT__VGT_PRIMITIVE_TYPE] = prim;
907 vgt->states[EG_VGT__VGT_MAX_VTX_INDX] = 0x00FFFFFF;
908 vgt->states[EG_VGT__VGT_MIN_VTX_INDX] = 0x00000000;
909 vgt->states[EG_VGT__VGT_INDX_OFFSET] = start;
910 vgt->states[EG_VGT__VGT_DMA_INDEX_TYPE] = vgt_dma_index_type;
911 vgt->states[EG_VGT__VGT_PRIMITIVEID_EN] = 0x00000000;
912 vgt->states[EG_VGT__VGT_DMA_NUM_INSTANCES] = 0x00000001;
913 vgt->states[EG_VGT__VGT_MULTI_PRIM_IB_RESET_EN] = 0x00000000;
914 vgt->states[EG_VGT__VGT_INSTANCE_STEP_RATE_0] = 0x00000000;
915 vgt->states[EG_VGT__VGT_INSTANCE_STEP_RATE_1] = 0x00000000;
916 return radeon_state_pm4(vgt);
917 }
918
919
920 static int eg_ps_shader(struct r600_context *rctx, struct r600_context_state *rpshader,
921 struct radeon_state *state)
922 {
923 struct r600_screen *rscreen = rctx->screen;
924 const struct pipe_rasterizer_state *rasterizer;
925 struct r600_shader *rshader = &rpshader->shader;
926 unsigned i, tmp, exports_ps, num_cout;
927 boolean have_pos = FALSE;
928
929 rasterizer = &rctx->rasterizer->state.rasterizer;
930
931 radeon_state_init(state, rscreen->rw, R600_STATE_SHADER, 0, R600_SHADER_PS);
932 for (i = 0; i < rshader->ninput; i++) {
933 tmp = S_028644_SEMANTIC(i);
934 tmp |= S_028644_SEL_CENTROID(1);
935 if (rshader->input[i].name == TGSI_SEMANTIC_POSITION)
936 have_pos = TRUE;
937 if (rshader->input[i].name == TGSI_SEMANTIC_COLOR ||
938 rshader->input[i].name == TGSI_SEMANTIC_BCOLOR ||
939 rshader->input[i].name == TGSI_SEMANTIC_POSITION) {
940 tmp |= S_028644_FLAT_SHADE(rshader->flat_shade);
941 }
942 if (rasterizer->sprite_coord_enable & (1 << i)) {
943 tmp |= S_028644_PT_SPRITE_TEX(1);
944 }
945 state->states[EG_PS_SHADER__SPI_PS_INPUT_CNTL_0 + i] = tmp;
946 }
947
948 exports_ps = 0;
949 num_cout = 0;
950 for (i = 0; i < rshader->noutput; i++) {
951 if (rshader->output[i].name == TGSI_SEMANTIC_POSITION)
952 exports_ps |= 1;
953 else if (rshader->output[i].name == TGSI_SEMANTIC_COLOR) {
954 exports_ps |= (1 << (num_cout+1));
955 num_cout++;
956 }
957 }
958 if (!exports_ps) {
959 /* always at least export 1 component per pixel */
960 exports_ps = 2;
961 }
962 state->states[EG_PS_SHADER__SPI_PS_IN_CONTROL_0] = S_0286CC_NUM_INTERP(rshader->ninput) |
963 S_0286CC_PERSP_GRADIENT_ENA(1);
964 if (have_pos) {
965 state->states[EG_PS_SHADER__SPI_PS_IN_CONTROL_0] |= S_0286CC_POSITION_ENA(1);
966 state->states[EG_PS_SHADER__SPI_INPUT_Z] |= 1;
967 }
968 state->states[EG_PS_SHADER__SPI_PS_IN_CONTROL_1] = 0x00000000;
969 state->states[EG_PS_SHADER__SQ_PGM_RESOURCES_PS] = S_028844_NUM_GPRS(rshader->bc.ngpr) | S_028844_PRIME_CACHE_ON_DRAW(1) |
970 S_028844_STACK_SIZE(rshader->bc.nstack);
971 state->states[EG_PS_SHADER__SQ_PGM_EXPORTS_PS] = exports_ps;
972 state->states[EG_PS_SHADER__SPI_BARYC_CNTL] = S_0286E0_PERSP_CENTROID_ENA(1) |
973 S_0286E0_LINEAR_CENTROID_ENA(1);
974 state->bo[0] = radeon_bo_incref(rscreen->rw, rpshader->bo);
975 state->nbo = 1;
976 state->placement[0] = RADEON_GEM_DOMAIN_GTT;
977 return radeon_state_pm4(state);
978 }
979
980 static int eg_vs_shader(struct r600_context *rctx, struct r600_context_state *rpshader,
981 struct radeon_state *state)
982 {
983 struct r600_screen *rscreen = rctx->screen;
984 struct r600_shader *rshader = &rpshader->shader;
985 unsigned i, tmp;
986
987 radeon_state_init(state, rscreen->rw, R600_STATE_SHADER, 0, R600_SHADER_VS);
988 for (i = 0; i < 10; i++) {
989 state->states[EG_VS_SHADER__SPI_VS_OUT_ID_0 + i] = 0;
990 }
991 /* so far never got proper semantic id from tgsi */
992 for (i = 0; i < 32; i++) {
993 tmp = i << ((i & 3) * 8);
994 state->states[EG_VS_SHADER__SPI_VS_OUT_ID_0 + i / 4] |= tmp;
995 }
996 state->states[EG_VS_SHADER__SPI_VS_OUT_CONFIG] = S_0286C4_VS_EXPORT_COUNT(rshader->noutput - 2);
997 state->states[EG_VS_SHADER__SQ_PGM_RESOURCES_VS] = S_028860_NUM_GPRS(rshader->bc.ngpr) |
998 S_028860_STACK_SIZE(rshader->bc.nstack);
999 state->bo[0] = radeon_bo_incref(rscreen->rw, rpshader->bo);
1000 state->bo[1] = radeon_bo_incref(rscreen->rw, rpshader->bo);
1001 state->nbo = 2;
1002 state->placement[0] = RADEON_GEM_DOMAIN_GTT;
1003 state->placement[2] = RADEON_GEM_DOMAIN_GTT;
1004 return radeon_state_pm4(state);
1005 }
1006
1007 struct r600_context_hw_state_vtbl eg_hw_state_vtbl = {
1008 .blend = eg_blend,
1009 .ucp = eg_ucp,
1010 .cb = eg_cb,
1011 .db = eg_db,
1012 .rasterizer = eg_rasterizer,
1013 .scissor = eg_scissor,
1014 .viewport = eg_viewport,
1015 .dsa = eg_dsa,
1016 .sampler_border = eg_sampler_border,
1017 .sampler = eg_sampler,
1018 .resource = eg_resource,
1019 .cb_cntl = eg_cb_cntl,
1020 .vs_resource = eg_vs_resource,
1021 .vgt_init = eg_draw_vgt_init,
1022 .vgt_prim = eg_draw_vgt_prim,
1023 .vs_shader = eg_vs_shader,
1024 .ps_shader = eg_ps_shader,
1025 .init_config = eg_init_config,
1026 };
1027
1028 void eg_set_constant_buffer(struct pipe_context *ctx,
1029 uint shader, uint index,
1030 struct pipe_resource *buffer)
1031 {
1032 struct r600_screen *rscreen = r600_screen(ctx->screen);
1033 struct r600_context *rctx = r600_context(ctx);
1034 unsigned nconstant = 0, type, shader_class, size;
1035 struct radeon_state *rstate, *rstates;
1036 struct r600_resource *rbuffer = (struct r600_resource*)buffer;
1037
1038 type = R600_STATE_CBUF;
1039
1040 switch (shader) {
1041 case PIPE_SHADER_VERTEX:
1042 shader_class = R600_SHADER_VS;
1043 rstates = rctx->vs_constant;
1044 break;
1045 case PIPE_SHADER_FRAGMENT:
1046 shader_class = R600_SHADER_PS;
1047 rstates = rctx->ps_constant;
1048 break;
1049 default:
1050 R600_ERR("unsupported %d\n", shader);
1051 return;
1052 }
1053
1054 rstate = &rstates[0];
1055
1056 #define ALIGN_DIVUP(x, y) (((x) + (y) - 1) / (y))
1057 nconstant = buffer->width0 / 16;
1058 size = ALIGN_DIVUP(nconstant, 16);
1059
1060 radeon_state_init(rstate, rscreen->rw, type, 0, shader_class);
1061 rstate->states[EG_VS_CBUF__ALU_CONST_BUFFER_SIZE_VS_0] = size;
1062 rstate->states[EG_VS_CBUF__ALU_CONST_CACHE_VS_0] = 0;
1063
1064 rstate->bo[0] = radeon_bo_incref(rscreen->rw, rbuffer->bo);
1065 rstate->nbo = 1;
1066 rstate->placement[0] = RADEON_GEM_DOMAIN_VRAM;
1067 if (radeon_state_pm4(rstate))
1068 return;
1069 radeon_draw_bind(&rctx->draw, rstate);
1070 }