462f31cc79894bd92c9d87f03e60d9a2dc7bde7c
[mesa.git] / src / gallium / drivers / r600 / eg_states_inc.h
1 /* This file is autogenerated from eg_states.h - do not edit directly */
2 /* autogenerating script is gen_eg_states.py */
3
4 /* EG_CONFIG */
5 #define EG_CONFIG__SQ_CONFIG 0
6 #define EG_CONFIG__SPI_CONFIG_CNTL 1
7 #define EG_CONFIG__SPI_CONFIG_CNTL_1 2
8 #define EG_CONFIG__SQ_GPR_RESOURCE_MGMT_1 3
9 #define EG_CONFIG__SQ_GPR_RESOURCE_MGMT_2 4
10 #define EG_CONFIG__SQ_GPR_RESOURCE_MGMT_3 5
11 #define EG_CONFIG__SQ_THREAD_RESOURCE_MGMT_1 6
12 #define EG_CONFIG__SQ_THREAD_RESOURCE_MGMT_2 7
13 #define EG_CONFIG__SQ_STACK_RESOURCE_MGMT_1 8
14 #define EG_CONFIG__SQ_STACK_RESOURCE_MGMT_2 9
15 #define EG_CONFIG__SQ_STACK_RESOURCE_MGMT_3 10
16 #define EG_CONFIG__SQ_DYN_GPR_CNTL_PS_FLUSH_REQ 11
17 #define EG_CONFIG__PA_CL_ENHANCE 12
18 #define EG_CONFIG__SQ_DYN_GPR_RESOURCE_LIMIT_1 13
19 #define EG_CONFIG__SQ_LDS_ALLOC_PS 14
20 #define EG_CONFIG__SX_MISC 15
21 #define EG_CONFIG__SQ_ESGS_RING_ITEMSIZE 16
22 #define EG_CONFIG__SQ_GSVS_RING_ITEMSIZE 17
23 #define EG_CONFIG__SQ_ESTMP_RING_ITEMSIZE 18
24 #define EG_CONFIG__SQ_GSTMP_RING_ITEMSIZE 19
25 #define EG_CONFIG__SQ_VSTMP_RING_ITEMSIZE 20
26 #define EG_CONFIG__SQ_PSTMP_RING_ITEMSIZE 21
27 #define EG_CONFIG__SQ_GS_VERT_ITEMSIZE 22
28 #define EG_CONFIG__SQ_GS_VERT_ITEMSIZE_1 23
29 #define EG_CONFIG__SQ_GS_VERT_ITEMSIZE_2 24
30 #define EG_CONFIG__SQ_GS_VERT_ITEMSIZE_3 25
31 #define EG_CONFIG__VGT_OUTPUT_PATH_CNTL 26
32 #define EG_CONFIG__VGT_HOS_CNTL 27
33 #define EG_CONFIG__VGT_HOS_MAX_TESS_LEVEL 28
34 #define EG_CONFIG__VGT_HOS_MIN_TESS_LEVEL 29
35 #define EG_CONFIG__VGT_HOS_REUSE_DEPTH 30
36 #define EG_CONFIG__VGT_GROUP_PRIM_TYPE 31
37 #define EG_CONFIG__VGT_GROUP_FIRST_DECR 32
38 #define EG_CONFIG__VGT_GROUP_DECR 33
39 #define EG_CONFIG__VGT_GROUP_VECT_0_CNTL 34
40 #define EG_CONFIG__VGT_GROUP_VECT_1_CNTL 35
41 #define EG_CONFIG__VGT_GROUP_VECT_0_FMT_CNTL 36
42 #define EG_CONFIG__VGT_GROUP_VECT_1_FMT_CNTL 37
43 #define EG_CONFIG__VGT_GS_MODE 38
44 #define EG_CONFIG__PA_SC_MODE_CNTL_0 39
45 #define EG_CONFIG__PA_SC_MODE_CNTL_1 40
46 #define EG_CONFIG__VGT_REUSE_OFF 41
47 #define EG_CONFIG__VGT_VTX_CNT_EN 42
48 #define EG_CONFIG__VGT_SHADER_STAGES_EN 43
49 #define EG_CONFIG__VGT_STRMOUT_CONFIG 44
50 #define EG_CONFIG__VGT_STRMOUT_BUFFER_CONFIG 45
51 #define EG_CONFIG_SIZE 46
52 #define EG_CONFIG_PM4 128
53
54 /* EG_CB_CNTL */
55 #define EG_CB_CNTL__CB_TARGET_MASK 0
56 #define EG_CB_CNTL__CB_SHADER_MASK 1
57 #define EG_CB_CNTL__CB_COLOR_CONTROL 2
58 #define EG_CB_CNTL__PA_SC_AA_CONFIG 3
59 #define EG_CB_CNTL__PA_SC_AA_SAMPLE_LOCS_MCTX 4
60 #define EG_CB_CNTL__PA_SC_AA_MASK 5
61 #define EG_CB_CNTL_SIZE 6
62 #define EG_CB_CNTL_PM4 128
63
64 /* EG_RASTERIZER */
65 #define EG_RASTERIZER__SPI_INTERP_CONTROL_0 0
66 #define EG_RASTERIZER__PA_CL_CLIP_CNTL 1
67 #define EG_RASTERIZER__PA_SU_SC_MODE_CNTL 2
68 #define EG_RASTERIZER__PA_CL_VS_OUT_CNTL 3
69 #define EG_RASTERIZER__PA_CL_NANINF_CNTL 4
70 #define EG_RASTERIZER__PA_SU_POINT_SIZE 5
71 #define EG_RASTERIZER__PA_SU_POINT_MINMAX 6
72 #define EG_RASTERIZER__PA_SU_LINE_CNTL 7
73 #define EG_RASTERIZER__PA_SC_MPASS_PS_CNTL 8
74 #define EG_RASTERIZER__PA_SC_LINE_CNTL 9
75 #define EG_RASTERIZER__PA_SU_VTX_CNTL 10
76 #define EG_RASTERIZER__PA_CL_GB_VERT_CLIP_ADJ 11
77 #define EG_RASTERIZER__PA_CL_GB_VERT_DISC_ADJ 12
78 #define EG_RASTERIZER__PA_CL_GB_HORZ_CLIP_ADJ 13
79 #define EG_RASTERIZER__PA_CL_GB_HORZ_DISC_ADJ 14
80 #define EG_RASTERIZER__PA_SU_POLY_OFFSET_DB_FMT_CNTL 15
81 #define EG_RASTERIZER__PA_SU_POLY_OFFSET_CLAMP 16
82 #define EG_RASTERIZER__PA_SU_POLY_OFFSET_FRONT_SCALE 17
83 #define EG_RASTERIZER__PA_SU_POLY_OFFSET_FRONT_OFFSET 18
84 #define EG_RASTERIZER__PA_SU_POLY_OFFSET_BACK_SCALE 19
85 #define EG_RASTERIZER__PA_SU_POLY_OFFSET_BACK_OFFSET 20
86 #define EG_RASTERIZER_SIZE 21
87 #define EG_RASTERIZER_PM4 128
88
89 /* EG_VIEWPORT */
90 #define EG_VIEWPORT__PA_SC_VPORT_ZMIN_0 0
91 #define EG_VIEWPORT__PA_SC_VPORT_ZMAX_0 1
92 #define EG_VIEWPORT__PA_CL_VPORT_XSCALE_0 2
93 #define EG_VIEWPORT__PA_CL_VPORT_YSCALE_0 3
94 #define EG_VIEWPORT__PA_CL_VPORT_ZSCALE_0 4
95 #define EG_VIEWPORT__PA_CL_VPORT_XOFFSET_0 5
96 #define EG_VIEWPORT__PA_CL_VPORT_YOFFSET_0 6
97 #define EG_VIEWPORT__PA_CL_VPORT_ZOFFSET_0 7
98 #define EG_VIEWPORT__PA_CL_VTE_CNTL 8
99 #define EG_VIEWPORT_SIZE 9
100 #define EG_VIEWPORT_PM4 128
101
102 /* EG_SCISSOR */
103 #define EG_SCISSOR__PA_SC_SCREEN_SCISSOR_TL 0
104 #define EG_SCISSOR__PA_SC_SCREEN_SCISSOR_BR 1
105 #define EG_SCISSOR__PA_SC_WINDOW_OFFSET 2
106 #define EG_SCISSOR__PA_SC_WINDOW_SCISSOR_TL 3
107 #define EG_SCISSOR__PA_SC_WINDOW_SCISSOR_BR 4
108 #define EG_SCISSOR__PA_SC_CLIPRECT_RULE 5
109 #define EG_SCISSOR__PA_SC_CLIPRECT_0_TL 6
110 #define EG_SCISSOR__PA_SC_CLIPRECT_0_BR 7
111 #define EG_SCISSOR__PA_SC_CLIPRECT_1_TL 8
112 #define EG_SCISSOR__PA_SC_CLIPRECT_1_BR 9
113 #define EG_SCISSOR__PA_SC_CLIPRECT_2_TL 10
114 #define EG_SCISSOR__PA_SC_CLIPRECT_2_BR 11
115 #define EG_SCISSOR__PA_SC_CLIPRECT_3_TL 12
116 #define EG_SCISSOR__PA_SC_CLIPRECT_3_BR 13
117 #define EG_SCISSOR__PA_SC_EDGERULE 14
118 #define EG_SCISSOR__PA_SC_GENERIC_SCISSOR_TL 15
119 #define EG_SCISSOR__PA_SC_GENERIC_SCISSOR_BR 16
120 #define EG_SCISSOR__PA_SC_VPORT_SCISSOR_0_TL 17
121 #define EG_SCISSOR__PA_SC_VPORT_SCISSOR_0_BR 18
122 #define EG_SCISSOR__PA_SU_HARDWARE_SCREEN_OFFSET 19
123 #define EG_SCISSOR_SIZE 20
124 #define EG_SCISSOR_PM4 128
125
126 /* EG_BLEND */
127 #define EG_BLEND__CB_BLEND_RED 0
128 #define EG_BLEND__CB_BLEND_GREEN 1
129 #define EG_BLEND__CB_BLEND_BLUE 2
130 #define EG_BLEND__CB_BLEND_ALPHA 3
131 #define EG_BLEND__CB_BLEND0_CONTROL 4
132 #define EG_BLEND__CB_BLEND1_CONTROL 5
133 #define EG_BLEND__CB_BLEND2_CONTROL 6
134 #define EG_BLEND__CB_BLEND3_CONTROL 7
135 #define EG_BLEND__CB_BLEND4_CONTROL 8
136 #define EG_BLEND__CB_BLEND5_CONTROL 9
137 #define EG_BLEND__CB_BLEND6_CONTROL 10
138 #define EG_BLEND__CB_BLEND7_CONTROL 11
139 #define EG_BLEND_SIZE 12
140 #define EG_BLEND_PM4 128
141
142 /* EG_DSA */
143 #define EG_DSA__DB_STENCIL_CLEAR 0
144 #define EG_DSA__DB_DEPTH_CLEAR 1
145 #define EG_DSA__SX_ALPHA_TEST_CONTROL 2
146 #define EG_DSA__DB_STENCILREFMASK 3
147 #define EG_DSA__DB_STENCILREFMASK_BF 4
148 #define EG_DSA__SX_ALPHA_REF 5
149 #define EG_DSA__SPI_FOG_CNTL 6
150 #define EG_DSA__DB_DEPTH_CONTROL 7
151 #define EG_DSA__DB_SHADER_CONTROL 8
152 #define EG_DSA__DB_RENDER_CONTROL 9
153 #define EG_DSA__DB_RENDER_OVERRIDE 10
154 #define EG_DSA__DB_RENDER_OVERRIDE2 11
155 #define EG_DSA__DB_SRESULTS_COMPARE_STATE0 12
156 #define EG_DSA__DB_SRESULTS_COMPARE_STATE1 13
157 #define EG_DSA__DB_PRELOAD_CONTROL 14
158 #define EG_DSA__DB_ALPHA_TO_MASK 15
159 #define EG_DSA_SIZE 16
160 #define EG_DSA_PM4 128
161
162 /* EG_VS_SHADER */
163 #define EG_VS_SHADER__SQ_VTX_SEMANTIC_0 0
164 #define EG_VS_SHADER__SQ_VTX_SEMANTIC_1 1
165 #define EG_VS_SHADER__SQ_VTX_SEMANTIC_2 2
166 #define EG_VS_SHADER__SQ_VTX_SEMANTIC_3 3
167 #define EG_VS_SHADER__SQ_VTX_SEMANTIC_4 4
168 #define EG_VS_SHADER__SQ_VTX_SEMANTIC_5 5
169 #define EG_VS_SHADER__SQ_VTX_SEMANTIC_6 6
170 #define EG_VS_SHADER__SQ_VTX_SEMANTIC_7 7
171 #define EG_VS_SHADER__SQ_VTX_SEMANTIC_8 8
172 #define EG_VS_SHADER__SQ_VTX_SEMANTIC_9 9
173 #define EG_VS_SHADER__SQ_VTX_SEMANTIC_10 10
174 #define EG_VS_SHADER__SQ_VTX_SEMANTIC_11 11
175 #define EG_VS_SHADER__SQ_VTX_SEMANTIC_12 12
176 #define EG_VS_SHADER__SQ_VTX_SEMANTIC_13 13
177 #define EG_VS_SHADER__SQ_VTX_SEMANTIC_14 14
178 #define EG_VS_SHADER__SQ_VTX_SEMANTIC_15 15
179 #define EG_VS_SHADER__SQ_VTX_SEMANTIC_16 16
180 #define EG_VS_SHADER__SQ_VTX_SEMANTIC_17 17
181 #define EG_VS_SHADER__SQ_VTX_SEMANTIC_18 18
182 #define EG_VS_SHADER__SQ_VTX_SEMANTIC_19 19
183 #define EG_VS_SHADER__SQ_VTX_SEMANTIC_20 20
184 #define EG_VS_SHADER__SQ_VTX_SEMANTIC_21 21
185 #define EG_VS_SHADER__SQ_VTX_SEMANTIC_22 22
186 #define EG_VS_SHADER__SQ_VTX_SEMANTIC_23 23
187 #define EG_VS_SHADER__SQ_VTX_SEMANTIC_24 24
188 #define EG_VS_SHADER__SQ_VTX_SEMANTIC_25 25
189 #define EG_VS_SHADER__SQ_VTX_SEMANTIC_26 26
190 #define EG_VS_SHADER__SQ_VTX_SEMANTIC_27 27
191 #define EG_VS_SHADER__SQ_VTX_SEMANTIC_28 28
192 #define EG_VS_SHADER__SQ_VTX_SEMANTIC_29 29
193 #define EG_VS_SHADER__SQ_VTX_SEMANTIC_30 30
194 #define EG_VS_SHADER__SQ_VTX_SEMANTIC_31 31
195 #define EG_VS_SHADER__SPI_VS_OUT_ID_0 32
196 #define EG_VS_SHADER__SPI_VS_OUT_ID_1 33
197 #define EG_VS_SHADER__SPI_VS_OUT_ID_2 34
198 #define EG_VS_SHADER__SPI_VS_OUT_ID_3 35
199 #define EG_VS_SHADER__SPI_VS_OUT_ID_4 36
200 #define EG_VS_SHADER__SPI_VS_OUT_ID_5 37
201 #define EG_VS_SHADER__SPI_VS_OUT_ID_6 38
202 #define EG_VS_SHADER__SPI_VS_OUT_ID_7 39
203 #define EG_VS_SHADER__SPI_VS_OUT_ID_8 40
204 #define EG_VS_SHADER__SPI_VS_OUT_ID_9 41
205 #define EG_VS_SHADER__SPI_VS_OUT_CONFIG 42
206 #define EG_VS_SHADER__SQ_PGM_START_VS 43
207 #define EG_VS_SHADER__SQ_PGM_RESOURCES_VS 44
208 #define EG_VS_SHADER__SQ_PGM_RESOURCES_2_VS 45
209 #define EG_VS_SHADER__SQ_PGM_START_FS 46
210 #define EG_VS_SHADER__SQ_PGM_RESOURCES_FS 47
211 #define EG_VS_SHADER_SIZE 48
212 #define EG_VS_SHADER_PM4 128
213
214 /* EG_PS_SHADER */
215 #define EG_PS_SHADER__SPI_PS_INPUT_CNTL_0 0
216 #define EG_PS_SHADER__SPI_PS_INPUT_CNTL_1 1
217 #define EG_PS_SHADER__SPI_PS_INPUT_CNTL_2 2
218 #define EG_PS_SHADER__SPI_PS_INPUT_CNTL_3 3
219 #define EG_PS_SHADER__SPI_PS_INPUT_CNTL_4 4
220 #define EG_PS_SHADER__SPI_PS_INPUT_CNTL_5 5
221 #define EG_PS_SHADER__SPI_PS_INPUT_CNTL_6 6
222 #define EG_PS_SHADER__SPI_PS_INPUT_CNTL_7 7
223 #define EG_PS_SHADER__SPI_PS_INPUT_CNTL_8 8
224 #define EG_PS_SHADER__SPI_PS_INPUT_CNTL_9 9
225 #define EG_PS_SHADER__SPI_PS_INPUT_CNTL_10 10
226 #define EG_PS_SHADER__SPI_PS_INPUT_CNTL_11 11
227 #define EG_PS_SHADER__SPI_PS_INPUT_CNTL_12 12
228 #define EG_PS_SHADER__SPI_PS_INPUT_CNTL_13 13
229 #define EG_PS_SHADER__SPI_PS_INPUT_CNTL_14 14
230 #define EG_PS_SHADER__SPI_PS_INPUT_CNTL_15 15
231 #define EG_PS_SHADER__SPI_PS_INPUT_CNTL_16 16
232 #define EG_PS_SHADER__SPI_PS_INPUT_CNTL_17 17
233 #define EG_PS_SHADER__SPI_PS_INPUT_CNTL_18 18
234 #define EG_PS_SHADER__SPI_PS_INPUT_CNTL_19 19
235 #define EG_PS_SHADER__SPI_PS_INPUT_CNTL_20 20
236 #define EG_PS_SHADER__SPI_PS_INPUT_CNTL_21 21
237 #define EG_PS_SHADER__SPI_PS_INPUT_CNTL_22 22
238 #define EG_PS_SHADER__SPI_PS_INPUT_CNTL_23 23
239 #define EG_PS_SHADER__SPI_PS_INPUT_CNTL_24 24
240 #define EG_PS_SHADER__SPI_PS_INPUT_CNTL_25 25
241 #define EG_PS_SHADER__SPI_PS_INPUT_CNTL_26 26
242 #define EG_PS_SHADER__SPI_PS_INPUT_CNTL_27 27
243 #define EG_PS_SHADER__SPI_PS_INPUT_CNTL_28 28
244 #define EG_PS_SHADER__SPI_PS_INPUT_CNTL_29 29
245 #define EG_PS_SHADER__SPI_PS_INPUT_CNTL_30 30
246 #define EG_PS_SHADER__SPI_PS_INPUT_CNTL_31 31
247 #define EG_PS_SHADER__SPI_THREAD_GROUPING 32
248 #define EG_PS_SHADER__SPI_PS_IN_CONTROL_0 33
249 #define EG_PS_SHADER__SPI_PS_IN_CONTROL_1 34
250 #define EG_PS_SHADER__SPI_INPUT_Z 35
251 #define EG_PS_SHADER__SPI_BARYC_CNTL 36
252 #define EG_PS_SHADER__SPI_PS_IN_CONTROL_2 37
253 #define EG_PS_SHADER__SPI_COMPUTE_INPUT_CNTL 38
254 #define EG_PS_SHADER__SQ_PGM_START_PS 39
255 #define EG_PS_SHADER__SQ_PGM_RESOURCES_PS 40
256 #define EG_PS_SHADER__SQ_PGM_RESOURCES_2_PS 41
257 #define EG_PS_SHADER__SQ_PGM_EXPORTS_PS 42
258 #define EG_PS_SHADER_SIZE 43
259 #define EG_PS_SHADER_PM4 128
260
261 /* EG_UCP */
262 #define EG_UCP__PA_CL_UCP0_X 0
263 #define EG_UCP__PA_CL_UCP0_Y 1
264 #define EG_UCP__PA_CL_UCP0_Z 2
265 #define EG_UCP__PA_CL_UCP0_W 3
266 #define EG_UCP__PA_CL_UCP1_X 4
267 #define EG_UCP__PA_CL_UCP1_Y 5
268 #define EG_UCP__PA_CL_UCP1_Z 6
269 #define EG_UCP__PA_CL_UCP1_W 7
270 #define EG_UCP__PA_CL_UCP2_X 8
271 #define EG_UCP__PA_CL_UCP2_Y 9
272 #define EG_UCP__PA_CL_UCP2_Z 10
273 #define EG_UCP__PA_CL_UCP2_W 11
274 #define EG_UCP__PA_CL_UCP3_X 12
275 #define EG_UCP__PA_CL_UCP3_Y 13
276 #define EG_UCP__PA_CL_UCP3_Z 14
277 #define EG_UCP__PA_CL_UCP3_W 15
278 #define EG_UCP__PA_CL_UCP4_X 16
279 #define EG_UCP__PA_CL_UCP4_Y 17
280 #define EG_UCP__PA_CL_UCP4_Z 18
281 #define EG_UCP__PA_CL_UCP4_W 19
282 #define EG_UCP__PA_CL_UCP5_X 20
283 #define EG_UCP__PA_CL_UCP5_Y 21
284 #define EG_UCP__PA_CL_UCP5_Z 22
285 #define EG_UCP__PA_CL_UCP5_W 23
286 #define EG_UCP_SIZE 24
287 #define EG_UCP_PM4 128
288
289 /* EG_VS_CBUF */
290 #define EG_VS_CBUF__ALU_CONST_BUFFER_SIZE_VS_0 0
291 #define EG_VS_CBUF__ALU_CONST_CACHE_VS_0 1
292 #define EG_VS_CBUF_SIZE 2
293 #define EG_VS_CBUF_PM4 128
294
295 /* EG_PS_CBUF */
296 #define EG_PS_CBUF__ALU_CONST_BUFFER_SIZE_PS_0 0
297 #define EG_PS_CBUF__ALU_CONST_CACHE_PS_0 1
298 #define EG_PS_CBUF_SIZE 2
299 #define EG_PS_CBUF_PM4 128
300
301 /* EG_PS_RESOURCE */
302 #define EG_PS_RESOURCE__RESOURCE0_WORD0 0
303 #define EG_PS_RESOURCE__RESOURCE0_WORD1 1
304 #define EG_PS_RESOURCE__RESOURCE0_WORD2 2
305 #define EG_PS_RESOURCE__RESOURCE0_WORD3 3
306 #define EG_PS_RESOURCE__RESOURCE0_WORD4 4
307 #define EG_PS_RESOURCE__RESOURCE0_WORD5 5
308 #define EG_PS_RESOURCE__RESOURCE0_WORD6 6
309 #define EG_PS_RESOURCE__RESOURCE0_WORD7 7
310 #define EG_PS_RESOURCE_SIZE 8
311 #define EG_PS_RESOURCE_PM4 128
312
313 /* EG_VS_RESOURCE */
314 #define EG_VS_RESOURCE__RESOURCE160_WORD0 0
315 #define EG_VS_RESOURCE__RESOURCE160_WORD1 1
316 #define EG_VS_RESOURCE__RESOURCE160_WORD2 2
317 #define EG_VS_RESOURCE__RESOURCE160_WORD3 3
318 #define EG_VS_RESOURCE__RESOURCE160_WORD4 4
319 #define EG_VS_RESOURCE__RESOURCE160_WORD5 5
320 #define EG_VS_RESOURCE__RESOURCE160_WORD6 6
321 #define EG_VS_RESOURCE__RESOURCE160_WORD7 7
322 #define EG_VS_RESOURCE_SIZE 8
323 #define EG_VS_RESOURCE_PM4 128
324
325 /* EG_FS_RESOURCE */
326 #define EG_FS_RESOURCE__RESOURCE320_WORD0 0
327 #define EG_FS_RESOURCE__RESOURCE320_WORD1 1
328 #define EG_FS_RESOURCE__RESOURCE320_WORD2 2
329 #define EG_FS_RESOURCE__RESOURCE320_WORD3 3
330 #define EG_FS_RESOURCE__RESOURCE320_WORD4 4
331 #define EG_FS_RESOURCE__RESOURCE320_WORD5 5
332 #define EG_FS_RESOURCE__RESOURCE320_WORD6 6
333 #define EG_FS_RESOURCE__RESOURCE320_WORD7 7
334 #define EG_FS_RESOURCE_SIZE 8
335 #define EG_FS_RESOURCE_PM4 128
336
337 /* EG_GS_RESOURCE */
338 #define EG_GS_RESOURCE__RESOURCE336_WORD0 0
339 #define EG_GS_RESOURCE__RESOURCE336_WORD1 1
340 #define EG_GS_RESOURCE__RESOURCE336_WORD2 2
341 #define EG_GS_RESOURCE__RESOURCE336_WORD3 3
342 #define EG_GS_RESOURCE__RESOURCE336_WORD4 4
343 #define EG_GS_RESOURCE__RESOURCE336_WORD5 5
344 #define EG_GS_RESOURCE__RESOURCE336_WORD6 6
345 #define EG_GS_RESOURCE__RESOURCE336_WORD7 7
346 #define EG_GS_RESOURCE_SIZE 8
347 #define EG_GS_RESOURCE_PM4 128
348
349 /* EG_PS_SAMPLER */
350 #define EG_PS_SAMPLER__SQ_TEX_SAMPLER_WORD0_0 0
351 #define EG_PS_SAMPLER__SQ_TEX_SAMPLER_WORD1_0 1
352 #define EG_PS_SAMPLER__SQ_TEX_SAMPLER_WORD2_0 2
353 #define EG_PS_SAMPLER_SIZE 3
354 #define EG_PS_SAMPLER_PM4 128
355
356 /* EG_VS_SAMPLER */
357 #define EG_VS_SAMPLER__SQ_TEX_SAMPLER_WORD0_18 0
358 #define EG_VS_SAMPLER__SQ_TEX_SAMPLER_WORD1_18 1
359 #define EG_VS_SAMPLER__SQ_TEX_SAMPLER_WORD2_18 2
360 #define EG_VS_SAMPLER_SIZE 3
361 #define EG_VS_SAMPLER_PM4 128
362
363 /* EG_GS_SAMPLER */
364 #define EG_GS_SAMPLER__SQ_TEX_SAMPLER_WORD0_36 0
365 #define EG_GS_SAMPLER__SQ_TEX_SAMPLER_WORD1_36 1
366 #define EG_GS_SAMPLER__SQ_TEX_SAMPLER_WORD2_36 2
367 #define EG_GS_SAMPLER_SIZE 3
368 #define EG_GS_SAMPLER_PM4 128
369
370 /* EG_PS_SAMPLER_BORDER */
371 #define EG_PS_SAMPLER_BORDER__TD_PS_SAMPLER0_BORDER_RED 0
372 #define EG_PS_SAMPLER_BORDER__TD_PS_SAMPLER0_BORDER_GREEN 1
373 #define EG_PS_SAMPLER_BORDER__TD_PS_SAMPLER0_BORDER_BLUE 2
374 #define EG_PS_SAMPLER_BORDER__TD_PS_SAMPLER0_BORDER_ALPHA 3
375 #define EG_PS_SAMPLER_BORDER_SIZE 4
376 #define EG_PS_SAMPLER_BORDER_PM4 128
377
378 /* EG_VS_SAMPLER_BORDER */
379 #define EG_VS_SAMPLER_BORDER__TD_VS_SAMPLER0_BORDER_RED 0
380 #define EG_VS_SAMPLER_BORDER__TD_VS_SAMPLER0_BORDER_GREEN 1
381 #define EG_VS_SAMPLER_BORDER__TD_VS_SAMPLER0_BORDER_BLUE 2
382 #define EG_VS_SAMPLER_BORDER__TD_VS_SAMPLER0_BORDER_ALPHA 3
383 #define EG_VS_SAMPLER_BORDER_SIZE 4
384 #define EG_VS_SAMPLER_BORDER_PM4 128
385
386 /* EG_GS_SAMPLER_BORDER */
387 #define EG_GS_SAMPLER_BORDER__TD_GS_SAMPLER0_BORDER_RED 0
388 #define EG_GS_SAMPLER_BORDER__TD_GS_SAMPLER0_BORDER_GREEN 1
389 #define EG_GS_SAMPLER_BORDER__TD_GS_SAMPLER0_BORDER_BLUE 2
390 #define EG_GS_SAMPLER_BORDER__TD_GS_SAMPLER0_BORDER_ALPHA 3
391 #define EG_GS_SAMPLER_BORDER_SIZE 4
392 #define EG_GS_SAMPLER_BORDER_PM4 128
393
394 /* EG_CB */
395 #define EG_CB__CB_COLOR0_BASE 0
396 #define EG_CB__CB_COLOR0_PITCH 1
397 #define EG_CB__CB_COLOR0_SLICE 2
398 #define EG_CB__CB_COLOR0_VIEW 3
399 #define EG_CB__CB_COLOR0_INFO 4
400 #define EG_CB__CB_COLOR0_ATTRIB 5
401 #define EG_CB__CB_COLOR0_DIM 6
402 #define EG_CB_SIZE 7
403 #define EG_CB_PM4 128
404
405 /* EG_DB */
406 #define EG_DB__DB_HTILE_DATA_BASE 0
407 #define EG_DB__DB_Z_INFO 1
408 #define EG_DB__DB_STENCIL_INFO 2
409 #define EG_DB__DB_DEPTH_SIZE 3
410 #define EG_DB__DB_DEPTH_SLICE 4
411 #define EG_DB__DB_DEPTH_VIEW 5
412 #define EG_DB__DB_HTILE_SURFACE 6
413 #define EG_DB__DB_Z_READ_BASE 7
414 #define EG_DB__DB_STENCIL_READ_BASE 8
415 #define EG_DB__DB_Z_WRITE_BASE 9
416 #define EG_DB__DB_STENCIL_WRITE_BASE 10
417 #define EG_DB_SIZE 11
418 #define EG_DB_PM4 128
419
420 /* EG_VGT */
421 #define EG_VGT__VGT_PRIMITIVE_TYPE 0
422 #define EG_VGT__VGT_MAX_VTX_INDX 1
423 #define EG_VGT__VGT_MIN_VTX_INDX 2
424 #define EG_VGT__VGT_INDX_OFFSET 3
425 #define EG_VGT__VGT_DMA_INDEX_TYPE 4
426 #define EG_VGT__VGT_PRIMITIVEID_EN 5
427 #define EG_VGT__VGT_DMA_NUM_INSTANCES 6
428 #define EG_VGT__VGT_MULTI_PRIM_IB_RESET_EN 7
429 #define EG_VGT__VGT_INSTANCE_STEP_RATE_0 8
430 #define EG_VGT__VGT_INSTANCE_STEP_RATE_1 9
431 #define EG_VGT_SIZE 10
432 #define EG_VGT_PM4 128
433
434 /* EG_DRAW */
435 #define EG_DRAW__VGT_NUM_INDICES 0
436 #define EG_DRAW__VGT_DMA_BASE_HI 1
437 #define EG_DRAW__VGT_DMA_BASE 2
438 #define EG_DRAW__VGT_DRAW_INITIATOR 3
439 #define EG_DRAW_SIZE 4
440 #define EG_DRAW_PM4 128
441
442 /* EG_VGT_EVENT */
443 #define EG_VGT_EVENT__VGT_EVENT_INITIATOR 0
444 #define EG_VGT_EVENT_SIZE 1
445 #define EG_VGT_EVENT_PM4 128
446
447 /* EG_CB_FLUSH */
448 #define EG_CB_FLUSH_SIZE 0
449 #define EG_CB_FLUSH_PM4 128
450
451 /* EG_DB_FLUSH */
452 #define EG_DB_FLUSH_SIZE 0
453 #define EG_DB_FLUSH_PM4 128
454