2 * Permission is hereby granted, free of charge, to any person obtaining a
3 * copy of this software and associated documentation files (the "Software"),
4 * to deal in the Software without restriction, including without limitation
5 * on the rights to use, copy, modify, merge, publish, distribute, sub
6 * license, and/or sell copies of the Software, and to permit persons to whom
7 * the Software is furnished to do so, subject to the following conditions:
9 * The above copyright notice and this permission notice (including the next
10 * paragraph) shall be included in all copies or substantial portions of the
13 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
14 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
15 * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
16 * THE AUTHOR(S) AND/OR THEIR SUPPLIERS BE LIABLE FOR ANY CLAIM,
17 * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
18 * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
19 * USE OR OTHER DEALINGS IN THE SOFTWARE.
22 * Adam Rak <adam.rak@streamnovation.com>
28 #include "pipe/p_defines.h"
29 #include "pipe/p_state.h"
30 #include "pipe/p_context.h"
31 #include "util/u_blitter.h"
32 #include "util/u_double_list.h"
33 #include "util/u_transfer.h"
34 #include "util/u_surface.h"
35 #include "util/u_pack_color.h"
36 #include "util/u_memory.h"
37 #include "util/u_inlines.h"
38 #include "util/u_framebuffer.h"
40 #include "r600_resource.h"
41 #include "r600_shader.h"
42 #include "r600_pipe.h"
43 #include "r600_formats.h"
44 #include "evergreend.h"
45 #include "evergreen_compute_internal.h"
46 #include "r600_hw_context_priv.h"
48 int get_compute_resource_num(void)
51 #define DECL_COMPUTE_RESOURCE(name, n) num += n;
52 #include "compute_resource.def"
53 #undef DECL_COMPUTE_RESOURCE
57 void evergreen_emit_raw_value(
58 struct evergreen_compute_resource
* res
,
61 res
->cs
[res
->cs_end
++] = value
;
64 void evergreen_emit_ctx_value(struct r600_context
*ctx
, unsigned value
)
66 ctx
->cs
->buf
[ctx
->cs
->cdw
++] = value
;
69 void evergreen_mult_reg_set_(
70 struct evergreen_compute_resource
* res
,
77 evergreen_emit_raw_reg_set(res
, index
, size
/ 4);
79 for (i
= 0; i
< size
; i
+=4) {
80 res
->cs
[res
->cs_end
++] = array
[i
/ 4];
84 void evergreen_reg_set(
85 struct evergreen_compute_resource
* res
,
89 evergreen_emit_raw_reg_set(res
, index
, 1);
90 res
->cs
[res
->cs_end
++] = value
;
93 struct evergreen_compute_resource
* get_empty_res(
94 struct r600_pipe_compute
* pipe
,
95 enum evergreen_compute_resources res_code
,
103 #define DECL_COMPUTE_RESOURCE(name, n) if (COMPUTE_RESOURCE_ ## name == res_code) {code_index = i; code_size = n;} i += n;
104 #include "compute_resource.def"
105 #undef DECL_COMPUTE_RESOURCE
108 assert(code_index
!= -1 && "internal error: resouce index not found");
109 assert(offset_index
< code_size
&& "internal error: overindexing resource");
111 int index
= code_index
+ offset_index
;
113 struct evergreen_compute_resource
* res
= &pipe
->resources
[index
];
118 bzero(&res
->do_reloc
, sizeof(res
->do_reloc
));
123 void evergreen_emit_raw_reg_set(
124 struct evergreen_compute_resource
* res
,
129 int cs_end
= res
->cs_end
;
131 if (index
>= EVERGREEN_CONFIG_REG_OFFSET
132 && index
< EVERGREEN_CONFIG_REG_END
) {
133 res
->cs
[cs_end
] = PKT3C(PKT3_SET_CONFIG_REG
, num
, 0);
134 res
->cs
[cs_end
+1] = (index
- EVERGREEN_CONFIG_REG_OFFSET
) >> 2;
135 } else if (index
>= EVERGREEN_CONTEXT_REG_OFFSET
136 && index
< EVERGREEN_CONTEXT_REG_END
) {
137 res
->cs
[cs_end
] = PKT3C(PKT3_SET_CONTEXT_REG
, num
, 0);
138 res
->cs
[cs_end
+1] = (index
- EVERGREEN_CONTEXT_REG_OFFSET
) >> 2;
139 } else if (index
>= EVERGREEN_RESOURCE_OFFSET
140 && index
< EVERGREEN_RESOURCE_END
) {
141 res
->cs
[cs_end
] = PKT3C(PKT3_SET_RESOURCE
, num
, 0);
142 res
->cs
[cs_end
+1] = (index
- EVERGREEN_RESOURCE_OFFSET
) >> 2;
143 } else if (index
>= EVERGREEN_SAMPLER_OFFSET
144 && index
< EVERGREEN_SAMPLER_END
) {
145 res
->cs
[cs_end
] = PKT3C(PKT3_SET_SAMPLER
, num
, 0);
146 res
->cs
[cs_end
+1] = (index
- EVERGREEN_SAMPLER_OFFSET
) >> 2;
147 } else if (index
>= EVERGREEN_CTL_CONST_OFFSET
148 && index
< EVERGREEN_CTL_CONST_END
) {
149 res
->cs
[cs_end
] = PKT3C(PKT3_SET_CTL_CONST
, num
, 0);
150 res
->cs
[cs_end
+1] = (index
- EVERGREEN_CTL_CONST_OFFSET
) >> 2;
151 } else if (index
>= EVERGREEN_LOOP_CONST_OFFSET
152 && index
< EVERGREEN_LOOP_CONST_END
) {
153 res
->cs
[cs_end
] = PKT3C(PKT3_SET_LOOP_CONST
, num
, 0);
154 res
->cs
[cs_end
+1] = (index
- EVERGREEN_LOOP_CONST_OFFSET
) >> 2;
155 } else if (index
>= EVERGREEN_BOOL_CONST_OFFSET
156 && index
< EVERGREEN_BOOL_CONST_END
) {
157 res
->cs
[cs_end
] = PKT3C(PKT3_SET_BOOL_CONST
, num
, 0);
158 res
->cs
[cs_end
+1] = (index
- EVERGREEN_BOOL_CONST_OFFSET
) >> 2;
160 res
->cs
[cs_end
] = PKT0(index
, num
-1);
167 void evergreen_emit_force_reloc(struct evergreen_compute_resource
* res
)
169 res
->do_reloc
[res
->cs_end
] += 1;
172 void evergreen_emit_ctx_reg_set(
173 struct r600_context
*ctx
,
178 if (index
>= EVERGREEN_CONFIG_REG_OFFSET
179 && index
< EVERGREEN_CONFIG_REG_END
) {
180 ctx
->cs
->buf
[ctx
->cs
->cdw
++] = PKT3C(PKT3_SET_CONFIG_REG
, num
, 0);
181 ctx
->cs
->buf
[ctx
->cs
->cdw
++] = (index
- EVERGREEN_CONFIG_REG_OFFSET
) >> 2;
182 } else if (index
>= EVERGREEN_CONTEXT_REG_OFFSET
183 && index
< EVERGREEN_CONTEXT_REG_END
) {
184 ctx
->cs
->buf
[ctx
->cs
->cdw
++] = PKT3C(PKT3_SET_CONTEXT_REG
, num
, 0);
185 ctx
->cs
->buf
[ctx
->cs
->cdw
++] = (index
- EVERGREEN_CONTEXT_REG_OFFSET
) >> 2;
186 } else if (index
>= EVERGREEN_RESOURCE_OFFSET
187 && index
< EVERGREEN_RESOURCE_END
) {
188 ctx
->cs
->buf
[ctx
->cs
->cdw
++] = PKT3C(PKT3_SET_RESOURCE
, num
, 0);
189 ctx
->cs
->buf
[ctx
->cs
->cdw
++] = (index
- EVERGREEN_RESOURCE_OFFSET
) >> 2;
190 } else if (index
>= EVERGREEN_SAMPLER_OFFSET
191 && index
< EVERGREEN_SAMPLER_END
) {
192 ctx
->cs
->buf
[ctx
->cs
->cdw
++] = PKT3C(PKT3_SET_SAMPLER
, num
, 0);
193 ctx
->cs
->buf
[ctx
->cs
->cdw
++] = (index
- EVERGREEN_SAMPLER_OFFSET
) >> 2;
194 } else if (index
>= EVERGREEN_CTL_CONST_OFFSET
195 && index
< EVERGREEN_CTL_CONST_END
) {
196 ctx
->cs
->buf
[ctx
->cs
->cdw
++] = PKT3C(PKT3_SET_CTL_CONST
, num
, 0);
197 ctx
->cs
->buf
[ctx
->cs
->cdw
++] = (index
- EVERGREEN_CTL_CONST_OFFSET
) >> 2;
198 } else if (index
>= EVERGREEN_LOOP_CONST_OFFSET
199 && index
< EVERGREEN_LOOP_CONST_END
) {
200 ctx
->cs
->buf
[ctx
->cs
->cdw
++] = PKT3C(PKT3_SET_LOOP_CONST
, num
, 0);
201 ctx
->cs
->buf
[ctx
->cs
->cdw
++] = (index
- EVERGREEN_LOOP_CONST_OFFSET
) >> 2;
202 } else if (index
>= EVERGREEN_BOOL_CONST_OFFSET
203 && index
< EVERGREEN_BOOL_CONST_END
) {
204 ctx
->cs
->buf
[ctx
->cs
->cdw
++] = PKT3C(PKT3_SET_BOOL_CONST
, num
, 0);
205 ctx
->cs
->buf
[ctx
->cs
->cdw
++] = (index
- EVERGREEN_BOOL_CONST_OFFSET
) >> 2;
207 ctx
->cs
->buf
[ctx
->cs
->cdw
++] = PKT0(index
, num
-1);
211 void evergreen_emit_ctx_reloc(
212 struct r600_context
*ctx
,
213 struct r600_resource
*bo
,
214 enum radeon_bo_usage usage
)
218 ctx
->cs
->buf
[ctx
->cs
->cdw
++] = PKT3(PKT3_NOP
, 0, 0);
219 u32 rr
= r600_context_bo_reloc(ctx
, bo
, usage
);
220 ctx
->cs
->buf
[ctx
->cs
->cdw
++] = rr
;
223 int evergreen_compute_get_gpu_format(
224 struct number_type_and_format
* fmt
,
225 struct r600_resource
*bo
)
227 switch (bo
->b
.b
.format
)
229 case PIPE_FORMAT_R8_UNORM
:
230 case PIPE_FORMAT_R32_UNORM
:
231 case PIPE_FORMAT_R32_UINT
:
232 fmt
->format
= V_028C70_COLOR_32
;
233 fmt
->number_type
= V_028C70_NUMBER_UNORM
;
234 fmt
->num_format_all
= 0;
236 case PIPE_FORMAT_R32_FLOAT
:
237 fmt
->format
= V_028C70_COLOR_32_FLOAT
;
238 fmt
->number_type
= V_028C70_NUMBER_FLOAT
;
239 fmt
->num_format_all
= 0;
241 case PIPE_FORMAT_R32G32B32A32_FLOAT
:
242 fmt
->format
= V_028C70_COLOR_32_32_32_32_FLOAT
;
243 fmt
->number_type
= V_028C70_NUMBER_FLOAT
;
244 fmt
->num_format_all
= 0;
247 ///TODO: other formats...
256 void evergreen_set_rat(
257 struct r600_pipe_compute
*pipe
,
259 struct r600_resource
* bo
,
264 assert((size
& 3) == 0);
265 assert((start
& 0xFF) == 0);
267 struct pipe_surface rat_templ
;
268 struct r600_surface
*surf
;
269 struct r600_context
*rctx
= pipe
->ctx
;
271 COMPUTE_DBG("bind rat: %i \n", id
);
273 /* Create the RAT surface */
274 memset(&rat_templ
, 0, sizeof(rat_templ
));
275 rat_templ
.format
= PIPE_FORMAT_R32_UINT
;
276 rat_templ
.u
.tex
.level
= 0;
277 rat_templ
.u
.tex
.first_layer
= 0;
278 rat_templ
.u
.tex
.last_layer
= 0;
280 /* Add the RAT the list of color buffers */
281 pipe
->ctx
->framebuffer
.state
.cbufs
[id
] = pipe
->ctx
->context
.create_surface(
282 (struct pipe_context
*)pipe
->ctx
,
283 (struct pipe_resource
*)bo
, &rat_templ
);
285 /* Update the number of color buffers */
286 pipe
->ctx
->framebuffer
.state
.nr_cbufs
=
287 MAX2(id
+ 1, pipe
->ctx
->framebuffer
.state
.nr_cbufs
);
289 /* Update the cb_target_mask
290 * XXX: I think this is a potential spot for bugs once we start doing
291 * GL interop. cb_target_mask may be modified in the 3D sections
293 pipe
->ctx
->compute_cb_target_mask
|= (0xf << (id
* 4));
295 surf
= (struct r600_surface
*)pipe
->ctx
->framebuffer
.state
.cbufs
[id
];
296 evergreen_init_color_surface_rat(rctx
, surf
);
299 void evergreen_set_gds(
300 struct r600_pipe_compute
*pipe
,
304 struct evergreen_compute_resource
* res
=
305 get_empty_res(pipe
, COMPUTE_RESOURCE_GDS
, 0);
307 evergreen_reg_set(res
, R_028728_GDS_ORDERED_WAVE_PER_SE
, 1);
308 evergreen_reg_set(res
, R_028720_GDS_ADDR_BASE
, addr
);
309 evergreen_reg_set(res
, R_028724_GDS_ADDR_SIZE
, size
);
312 void evergreen_set_export(
313 struct r600_pipe_compute
*pipe
,
314 struct r600_resource
* bo
,
315 int offset
, int size
)
317 #define SX_MEMORY_EXPORT_BASE 0x9010
318 #define SX_MEMORY_EXPORT_SIZE 0x9014
320 struct evergreen_compute_resource
* res
=
321 get_empty_res(pipe
, COMPUTE_RESOURCE_EXPORT
, 0);
323 evergreen_reg_set(res
, SX_MEMORY_EXPORT_SIZE
, size
);
326 evergreen_reg_set(res
, SX_MEMORY_EXPORT_BASE
, offset
);
328 res
->usage
= RADEON_USAGE_WRITE
;
329 res
->coher_bo_size
= size
;
334 void evergreen_set_loop_const(
335 struct r600_pipe_compute
*pipe
,
336 int id
, int count
, int init
, int inc
) {
338 struct evergreen_compute_resource
* res
=
339 get_empty_res(pipe
, COMPUTE_RESOURCE_LOOP
, id
);
342 assert(count
<= 0xFFF);
343 assert(init
<= 0xFF);
346 /* Compute shaders use LOOP_CONST registers SQ_LOOP_CONST_160 to
347 * SQ_LOOP_CONST_191 */
348 evergreen_reg_set(res
, R_03A200_SQ_LOOP_CONST_0
+ (160 * 4) + (id
* 4),
349 count
| init
<< 12 | inc
<< 24);
352 void evergreen_set_tmp_ring(
353 struct r600_pipe_compute
*pipe
,
354 struct r600_resource
* bo
,
355 int offset
, int size
, int se
)
357 #define SQ_LSTMP_RING_BASE 0x00008e10
358 #define SQ_LSTMP_RING_SIZE 0x00008e14
359 #define GRBM_GFX_INDEX 0x802C
360 #define INSTANCE_INDEX(x) ((x) << 0)
361 #define SE_INDEX(x) ((x) << 16)
362 #define INSTANCE_BROADCAST_WRITES (1 << 30)
363 #define SE_BROADCAST_WRITES (1 << 31)
365 struct evergreen_compute_resource
* res
=
366 get_empty_res(pipe
, COMPUTE_RESOURCE_TMPRING
, se
);
368 evergreen_reg_set(res
,
369 GRBM_GFX_INDEX
,INSTANCE_INDEX(0)
371 | INSTANCE_BROADCAST_WRITES
);
372 evergreen_reg_set(res
, SQ_LSTMP_RING_SIZE
, size
);
377 evergreen_reg_set(res
, SQ_LSTMP_RING_BASE
, offset
);
379 res
->usage
= RADEON_USAGE_WRITE
;
380 res
->coher_bo_size
= 0;
385 evergreen_emit_force_reloc(res
);
388 evergreen_reg_set(res
,
389 GRBM_GFX_INDEX
,INSTANCE_INDEX(0)
391 | INSTANCE_BROADCAST_WRITES
392 | SE_BROADCAST_WRITES
);
395 static uint32_t r600_colorformat_endian_swap(uint32_t colorformat
)
397 if (R600_BIG_ENDIAN
) {
398 switch(colorformat
) {
399 case V_028C70_COLOR_4_4
:
403 case V_028C70_COLOR_8
:
406 /* 16-bit buffers. */
407 case V_028C70_COLOR_5_6_5
:
408 case V_028C70_COLOR_1_5_5_5
:
409 case V_028C70_COLOR_4_4_4_4
:
410 case V_028C70_COLOR_16
:
411 case V_028C70_COLOR_8_8
:
414 /* 32-bit buffers. */
415 case V_028C70_COLOR_8_8_8_8
:
416 case V_028C70_COLOR_2_10_10_10
:
417 case V_028C70_COLOR_8_24
:
418 case V_028C70_COLOR_24_8
:
419 case V_028C70_COLOR_32_FLOAT
:
420 case V_028C70_COLOR_16_16_FLOAT
:
421 case V_028C70_COLOR_16_16
:
424 /* 64-bit buffers. */
425 case V_028C70_COLOR_16_16_16_16
:
426 case V_028C70_COLOR_16_16_16_16_FLOAT
:
429 case V_028C70_COLOR_32_32_FLOAT
:
430 case V_028C70_COLOR_32_32
:
431 case V_028C70_COLOR_X24_8_32_FLOAT
:
434 /* 96-bit buffers. */
435 case V_028C70_COLOR_32_32_32_FLOAT
:
436 /* 128-bit buffers. */
437 case V_028C70_COLOR_32_32_32_32_FLOAT
:
438 case V_028C70_COLOR_32_32_32_32
:
441 return ENDIAN_NONE
; /* Unsupported. */
448 static unsigned r600_tex_dim(unsigned dim
)
452 case PIPE_TEXTURE_1D
:
453 return V_030000_SQ_TEX_DIM_1D
;
454 case PIPE_TEXTURE_1D_ARRAY
:
455 return V_030000_SQ_TEX_DIM_1D_ARRAY
;
456 case PIPE_TEXTURE_2D
:
457 case PIPE_TEXTURE_RECT
:
458 return V_030000_SQ_TEX_DIM_2D
;
459 case PIPE_TEXTURE_2D_ARRAY
:
460 return V_030000_SQ_TEX_DIM_2D_ARRAY
;
461 case PIPE_TEXTURE_3D
:
462 return V_030000_SQ_TEX_DIM_3D
;
463 case PIPE_TEXTURE_CUBE
:
464 return V_030000_SQ_TEX_DIM_CUBEMAP
;
468 void evergreen_set_tex_resource(
469 struct r600_pipe_compute
*pipe
,
470 struct r600_pipe_sampler_view
* view
,
473 struct evergreen_compute_resource
* res
=
474 get_empty_res(pipe
, COMPUTE_RESOURCE_TEX
, id
);
475 struct r600_texture
*tmp
=
476 (struct r600_texture
*)view
->base
.texture
;
478 unsigned format
, endian
;
479 uint32_t word4
= 0, yuv_format
= 0, pitch
= 0;
480 unsigned char swizzle
[4], array_mode
= 0, non_disp_tiling
= 0;
481 unsigned height
, depth
;
488 format
= r600_translate_texformat((struct pipe_screen
*)pipe
->ctx
->screen
,
489 view
->base
.format
, swizzle
, &word4
, &yuv_format
);
495 endian
= r600_colorformat_endian_swap(format
);
497 height
= view
->base
.texture
->height0
;
498 depth
= view
->base
.texture
->depth0
;
500 pitch
= align(tmp
->surface
.level
[0].nblk_x
*
501 util_format_get_blockwidth(tmp
->resource
.b
.b
.format
), 8);
502 array_mode
= tmp
->array_mode
[0];
503 non_disp_tiling
= tmp
->non_disp_tiling
;
505 assert(view
->base
.texture
->target
!= PIPE_TEXTURE_1D_ARRAY
);
506 assert(view
->base
.texture
->target
!= PIPE_TEXTURE_2D_ARRAY
);
508 evergreen_emit_raw_value(res
, PKT3C(PKT3_SET_RESOURCE
, 8, 0));
509 evergreen_emit_raw_value(res
, (id
+816)*32 >> 2); ///TODO: check this line
510 evergreen_emit_raw_value(res
,
511 (S_030000_DIM(r600_tex_dim(view
->base
.texture
->target
)) |
512 S_030000_PITCH((pitch
/ 8) - 1) |
513 S_030000_NON_DISP_TILING_ORDER(non_disp_tiling
) |
514 S_030000_TEX_WIDTH(view
->base
.texture
->width0
- 1)));
515 evergreen_emit_raw_value(res
, (S_030004_TEX_HEIGHT(height
- 1) |
516 S_030004_TEX_DEPTH(depth
- 1) |
517 S_030004_ARRAY_MODE(array_mode
)));
518 evergreen_emit_raw_value(res
, tmp
->surface
.level
[0].offset
>> 8);
519 evergreen_emit_raw_value(res
, tmp
->surface
.level
[0].offset
>> 8);
520 evergreen_emit_raw_value(res
, (word4
|
521 S_030010_SRF_MODE_ALL(V_030010_SRF_MODE_ZERO_CLAMP_MINUS_ONE
) |
522 S_030010_ENDIAN_SWAP(endian
) |
523 S_030010_BASE_LEVEL(0)));
524 evergreen_emit_raw_value(res
, (S_030014_LAST_LEVEL(0) |
525 S_030014_BASE_ARRAY(0) |
526 S_030014_LAST_ARRAY(0)));
527 evergreen_emit_raw_value(res
, (S_030018_MAX_ANISO(4 /* max 16 samples */)));
528 evergreen_emit_raw_value(res
,
529 S_03001C_TYPE(V_03001C_SQ_TEX_VTX_VALID_TEXTURE
)
530 | S_03001C_DATA_FORMAT(format
));
532 res
->bo
= (struct r600_resource
*)view
->base
.texture
;
534 res
->usage
= RADEON_USAGE_READ
;
536 res
->coher_bo_size
= tmp
->surface
.level
[0].offset
+
537 util_format_get_blockwidth(tmp
->resource
.b
.b
.format
) *
538 view
->base
.texture
->width0
*height
*depth
;
540 pipe
->ctx
->flags
|= R600_CONTEXT_TEX_FLUSH
;
542 evergreen_emit_force_reloc(res
);
543 evergreen_emit_force_reloc(res
);
546 void evergreen_set_sampler_resource(
547 struct r600_pipe_compute
*pipe
,
548 struct compute_sampler_state
*sampler
,
551 struct evergreen_compute_resource
* res
=
552 get_empty_res(pipe
, COMPUTE_RESOURCE_SAMPLER
, id
);
554 unsigned aniso_flag_offset
= sampler
->state
.max_anisotropy
> 1 ? 2 : 0;
556 evergreen_emit_raw_value(res
, PKT3C(PKT3_SET_SAMPLER
, 3, 0));
557 evergreen_emit_raw_value(res
, (id
+ 90)*3);
558 evergreen_emit_raw_value(res
,
559 S_03C000_CLAMP_X(r600_tex_wrap(sampler
->state
.wrap_s
)) |
560 S_03C000_CLAMP_Y(r600_tex_wrap(sampler
->state
.wrap_t
)) |
561 S_03C000_CLAMP_Z(r600_tex_wrap(sampler
->state
.wrap_r
)) |
562 S_03C000_XY_MAG_FILTER(r600_tex_filter(sampler
->state
.mag_img_filter
) | aniso_flag_offset
) |
563 S_03C000_XY_MIN_FILTER(r600_tex_filter(sampler
->state
.min_img_filter
) | aniso_flag_offset
) |
564 S_03C000_BORDER_COLOR_TYPE(V_03C000_SQ_TEX_BORDER_COLOR_OPAQUE_BLACK
)
566 evergreen_emit_raw_value(res
,
567 S_03C004_MIN_LOD(S_FIXED(CLAMP(sampler
->state
.min_lod
, 0, 15), 8)) |
568 S_03C004_MAX_LOD(S_FIXED(CLAMP(sampler
->state
.max_lod
, 0, 15), 8))
570 evergreen_emit_raw_value(res
,
571 S_03C008_LOD_BIAS(S_FIXED(CLAMP(sampler
->state
.lod_bias
, -16, 16), 8)) |
572 (sampler
->state
.seamless_cube_map
? 0 : S_03C008_DISABLE_CUBE_WRAP(1)) |
577 void evergreen_set_const_cache(
578 struct r600_pipe_compute
*pipe
,
580 struct r600_resource
* cbo
,
581 int size
, int offset
)
583 #define SQ_ALU_CONST_BUFFER_SIZE_LS_0 0x00028fc0
584 #define SQ_ALU_CONST_CACHE_LS_0 0x00028f40
586 struct evergreen_compute_resource
* res
=
587 get_empty_res(pipe
, COMPUTE_RESOURCE_CONST_MEM
, cache_id
);
589 assert(size
< 0x200);
590 assert((offset
& 0xFF) == 0);
591 assert(cache_id
< 16);
593 evergreen_reg_set(res
, SQ_ALU_CONST_BUFFER_SIZE_LS_0
+ cache_id
*4, size
);
594 evergreen_reg_set(res
, SQ_ALU_CONST_CACHE_LS_0
+ cache_id
*4, offset
>> 8);
596 res
->usage
= RADEON_USAGE_READ
;
597 res
->coher_bo_size
= size
;
599 pipe
->ctx
->flags
|= R600_CONTEXT_SHADERCONST_FLUSH
;
602 struct r600_resource
* r600_compute_buffer_alloc_vram(
603 struct r600_screen
*screen
,
608 struct pipe_resource
* buffer
= pipe_buffer_create(
609 (struct pipe_screen
*) screen
,
611 PIPE_USAGE_IMMUTABLE
,
614 return (struct r600_resource
*)buffer
;