src/gallium/drivers/r600/evergreen_hw_context.c

   1 /*
   2  * Copyright 2010 Jerome Glisse <glisse@freedesktop.org>
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * on the rights to use, copy, modify, merge, publish, distribute, sub
   8  * license, and/or sell copies of the Software, and to permit persons to whom
   9  * the Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice (including the next
  12  * paragraph) shall be included in all copies or substantial portions of the
  13  * Software.
  14  *
  15  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  16  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  17  * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
  18  * THE AUTHOR(S) AND/OR THEIR SUPPLIERS BE LIABLE FOR ANY CLAIM,
  19  * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
  20  * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
  21  * USE OR OTHER DEALINGS IN THE SOFTWARE.
  22  *
  23  * Authors:
  24  *      Jerome Glisse
  25  */
  26 #include "r600_hw_context_priv.h"
  27 #include "evergreend.h"
  28 #include "util/u_memory.h"
  29
  30 static const struct r600_reg evergreen_config_reg_list[] = {
  31         {R_008958_VGT_PRIMITIVE_TYPE, 0},
  32 };
  33
  34
  35 static const struct r600_reg cayman_config_reg_list[] = {
  36         {R_008958_VGT_PRIMITIVE_TYPE, 0, 0},
  37         {R_009100_SPI_CONFIG_CNTL, REG_FLAG_ENABLE_ALWAYS | REG_FLAG_FLUSH_CHANGE, 0},
  38         {R_00913C_SPI_CONFIG_CNTL_1, REG_FLAG_ENABLE_ALWAYS | REG_FLAG_FLUSH_CHANGE, 0},
  39 };
  40
  41 static const struct r600_reg evergreen_ctl_const_list[] = {
  42         {R_03CFF4_SQ_VTX_START_INST_LOC, 0, 0},
  43 };
  44
  45 static const struct r600_reg evergreen_context_reg_list[] = {
  46         {R_028000_DB_RENDER_CONTROL, 0, 0},
  47         {R_028008_DB_DEPTH_VIEW, 0, 0},
  48         {R_028010_DB_RENDER_OVERRIDE2, 0, 0},
  49         {GROUP_FORCE_NEW_BLOCK, 0, 0},
  50         {R_028014_DB_HTILE_DATA_BASE, REG_FLAG_NEED_BO, 0},
  51         {GROUP_FORCE_NEW_BLOCK, 0, 0},
  52         {R_028040_DB_Z_INFO, REG_FLAG_NEED_BO, 0},
  53         {GROUP_FORCE_NEW_BLOCK, 0, 0},
  54         {R_028044_DB_STENCIL_INFO, 0, 0},
  55         {GROUP_FORCE_NEW_BLOCK, 0, 0},
  56         {R_028048_DB_Z_READ_BASE, REG_FLAG_NEED_BO, 0},
  57         {GROUP_FORCE_NEW_BLOCK, 0, 0},
  58         {R_02804C_DB_STENCIL_READ_BASE, REG_FLAG_NEED_BO, 0},
  59         {GROUP_FORCE_NEW_BLOCK, 0, 0},
  60         {R_028050_DB_Z_WRITE_BASE, REG_FLAG_NEED_BO, 0},
  61         {GROUP_FORCE_NEW_BLOCK, 0, 0},
  62         {R_028054_DB_STENCIL_WRITE_BASE, REG_FLAG_NEED_BO, 0},
  63         {GROUP_FORCE_NEW_BLOCK, 0, 0},
  64         {R_028058_DB_DEPTH_SIZE, 0, 0},
  65         {R_02805C_DB_DEPTH_SLICE, 0, 0},
  66         {R_028140_ALU_CONST_BUFFER_SIZE_PS_0, REG_FLAG_DIRTY_ALWAYS, 0},
  67         {R_028144_ALU_CONST_BUFFER_SIZE_PS_1, REG_FLAG_DIRTY_ALWAYS, 0},
  68         {R_028180_ALU_CONST_BUFFER_SIZE_VS_0, REG_FLAG_DIRTY_ALWAYS, 0},
  69         {R_028184_ALU_CONST_BUFFER_SIZE_VS_1, REG_FLAG_DIRTY_ALWAYS, 0},
  70         {R_028204_PA_SC_WINDOW_SCISSOR_TL, 0, 0},
  71         {R_028208_PA_SC_WINDOW_SCISSOR_BR, 0, 0},
  72         {R_028234_PA_SU_HARDWARE_SCREEN_OFFSET, 0, 0},
  73         {R_028238_CB_TARGET_MASK, 0, 0},
  74         {R_02823C_CB_SHADER_MASK, 0, 0},
  75         {R_028250_PA_SC_VPORT_SCISSOR_0_TL, 0, 0},
  76         {R_028254_PA_SC_VPORT_SCISSOR_0_BR, 0, 0},
  77         {R_028350_SX_MISC, 0, 0},
  78         {GROUP_FORCE_NEW_BLOCK, 0, 0},
  79         {R_028408_VGT_INDX_OFFSET, 0, 0},
  80         {R_02840C_VGT_MULTI_PRIM_IB_RESET_INDX, 0, 0},
  81         {R_028A94_VGT_MULTI_PRIM_IB_RESET_EN, 0, 0},
  82         {GROUP_FORCE_NEW_BLOCK, 0, 0},
  83         {R_028410_SX_ALPHA_TEST_CONTROL, 0, 0},
  84         {R_028414_CB_BLEND_RED, 0, 0},
  85         {R_028418_CB_BLEND_GREEN, 0, 0},
  86         {R_02841C_CB_BLEND_BLUE, 0, 0},
  87         {R_028420_CB_BLEND_ALPHA, 0, 0},
  88         {R_028430_DB_STENCILREFMASK, 0, 0},
  89         {R_028434_DB_STENCILREFMASK_BF, 0, 0},
  90         {R_028438_SX_ALPHA_REF, 0, 0},
  91         {R_02843C_PA_CL_VPORT_XSCALE_0, 0, 0},
  92         {R_028440_PA_CL_VPORT_XOFFSET_0, 0, 0},
  93         {R_028444_PA_CL_VPORT_YSCALE_0, 0, 0},
  94         {R_028448_PA_CL_VPORT_YOFFSET_0, 0, 0},
  95         {R_02844C_PA_CL_VPORT_ZSCALE_0, 0, 0},
  96         {R_028450_PA_CL_VPORT_ZOFFSET_0, 0, 0},
  97         {R_0285BC_PA_CL_UCP0_X, 0, 0},
  98         {R_0285C0_PA_CL_UCP0_Y, 0, 0},
  99         {R_0285C4_PA_CL_UCP0_Z, 0, 0},
 100         {R_0285C8_PA_CL_UCP0_W, 0, 0},
 101         {R_0285CC_PA_CL_UCP1_X, 0, 0},
 102         {R_0285D0_PA_CL_UCP1_Y, 0, 0},
 103         {R_0285D4_PA_CL_UCP1_Z, 0, 0},
 104         {R_0285D8_PA_CL_UCP1_W, 0, 0},
 105         {R_0285DC_PA_CL_UCP2_X, 0, 0},
 106         {R_0285E0_PA_CL_UCP2_Y, 0, 0},
 107         {R_0285E4_PA_CL_UCP2_Z, 0, 0},
 108         {R_0285E8_PA_CL_UCP2_W, 0, 0},
 109         {R_0285EC_PA_CL_UCP3_X, 0, 0},
 110         {R_0285F0_PA_CL_UCP3_Y, 0, 0},
 111         {R_0285F4_PA_CL_UCP3_Z, 0, 0},
 112         {R_0285F8_PA_CL_UCP3_W, 0, 0},
 113         {R_0285FC_PA_CL_UCP4_X, 0, 0},
 114         {R_028600_PA_CL_UCP4_Y, 0, 0},
 115         {R_028604_PA_CL_UCP4_Z, 0, 0},
 116         {R_028608_PA_CL_UCP4_W, 0, 0},
 117         {R_02860C_PA_CL_UCP5_X, 0, 0},
 118         {R_028610_PA_CL_UCP5_Y, 0, 0},
 119         {R_028614_PA_CL_UCP5_Z, 0, 0},
 120         {R_028618_PA_CL_UCP5_W, 0, 0},
 121         {GROUP_FORCE_NEW_BLOCK, 0, 0},
 122         {R_02861C_SPI_VS_OUT_ID_0, 0, 0},
 123         {R_028620_SPI_VS_OUT_ID_1, 0, 0},
 124         {R_028624_SPI_VS_OUT_ID_2, 0, 0},
 125         {R_028628_SPI_VS_OUT_ID_3, 0, 0},
 126         {R_02862C_SPI_VS_OUT_ID_4, 0, 0},
 127         {R_028630_SPI_VS_OUT_ID_5, 0, 0},
 128         {R_028634_SPI_VS_OUT_ID_6, 0, 0},
 129         {R_028638_SPI_VS_OUT_ID_7, 0, 0},
 130         {R_02863C_SPI_VS_OUT_ID_8, 0, 0},
 131         {R_028640_SPI_VS_OUT_ID_9, 0, 0},
 132         {GROUP_FORCE_NEW_BLOCK, 0, 0},
 133         {R_028644_SPI_PS_INPUT_CNTL_0, 0, 0},
 134         {R_028648_SPI_PS_INPUT_CNTL_1, 0, 0},
 135         {R_02864C_SPI_PS_INPUT_CNTL_2, 0, 0},
 136         {R_028650_SPI_PS_INPUT_CNTL_3, 0, 0},
 137         {R_028654_SPI_PS_INPUT_CNTL_4, 0, 0},
 138         {R_028658_SPI_PS_INPUT_CNTL_5, 0, 0},
 139         {R_02865C_SPI_PS_INPUT_CNTL_6, 0, 0},
 140         {R_028660_SPI_PS_INPUT_CNTL_7, 0, 0},
 141         {R_028664_SPI_PS_INPUT_CNTL_8, 0, 0},
 142         {R_028668_SPI_PS_INPUT_CNTL_9, 0, 0},
 143         {R_02866C_SPI_PS_INPUT_CNTL_10, 0, 0},
 144         {R_028670_SPI_PS_INPUT_CNTL_11, 0, 0},
 145         {R_028674_SPI_PS_INPUT_CNTL_12, 0, 0},
 146         {R_028678_SPI_PS_INPUT_CNTL_13, 0, 0},
 147         {R_02867C_SPI_PS_INPUT_CNTL_14, 0, 0},
 148         {R_028680_SPI_PS_INPUT_CNTL_15, 0, 0},
 149         {R_028684_SPI_PS_INPUT_CNTL_16, 0, 0},
 150         {R_028688_SPI_PS_INPUT_CNTL_17, 0, 0},
 151         {R_02868C_SPI_PS_INPUT_CNTL_18, 0, 0},
 152         {R_028690_SPI_PS_INPUT_CNTL_19, 0, 0},
 153         {R_028694_SPI_PS_INPUT_CNTL_20, 0, 0},
 154         {R_028698_SPI_PS_INPUT_CNTL_21, 0, 0},
 155         {R_02869C_SPI_PS_INPUT_CNTL_22, 0, 0},
 156         {R_0286A0_SPI_PS_INPUT_CNTL_23, 0, 0},
 157         {R_0286A4_SPI_PS_INPUT_CNTL_24, 0, 0},
 158         {R_0286A8_SPI_PS_INPUT_CNTL_25, 0, 0},
 159         {R_0286AC_SPI_PS_INPUT_CNTL_26, 0, 0},
 160         {R_0286B0_SPI_PS_INPUT_CNTL_27, 0, 0},
 161         {R_0286B4_SPI_PS_INPUT_CNTL_28, 0, 0},
 162         {R_0286B8_SPI_PS_INPUT_CNTL_29, 0, 0},
 163         {R_0286BC_SPI_PS_INPUT_CNTL_30, 0, 0},
 164         {R_0286C0_SPI_PS_INPUT_CNTL_31, 0, 0},
 165         {GROUP_FORCE_NEW_BLOCK, 0, 0},
 166         {R_0286C4_SPI_VS_OUT_CONFIG, 0, 0},
 167         {R_0286C8_SPI_THREAD_GROUPING, 0, 0},
 168         {R_0286CC_SPI_PS_IN_CONTROL_0, 0, 0},
 169         {R_0286D0_SPI_PS_IN_CONTROL_1, 0, 0},
 170         {R_0286D4_SPI_INTERP_CONTROL_0, 0, 0},
 171         {R_0286D8_SPI_INPUT_Z, 0, 0},
 172         {R_0286E0_SPI_BARYC_CNTL, 0, 0},
 173         {R_0286E4_SPI_PS_IN_CONTROL_2, 0, 0},
 174         {R_0286E8_SPI_COMPUTE_INPUT_CNTL, 0, 0},
 175         {R_028780_CB_BLEND0_CONTROL, 0, 0},
 176         {R_028784_CB_BLEND1_CONTROL, 0, 0},
 177         {R_028788_CB_BLEND2_CONTROL, 0, 0},
 178         {R_02878C_CB_BLEND3_CONTROL, 0, 0},
 179         {R_028790_CB_BLEND4_CONTROL, 0, 0},
 180         {R_028794_CB_BLEND5_CONTROL, 0, 0},
 181         {R_028798_CB_BLEND6_CONTROL, 0, 0},
 182         {R_02879C_CB_BLEND7_CONTROL, 0, 0},
 183         {R_028800_DB_DEPTH_CONTROL, 0, 0},
 184         {R_02880C_DB_SHADER_CONTROL, 0, 0},
 185         {R_028808_CB_COLOR_CONTROL, 0, 0},
 186         {R_028810_PA_CL_CLIP_CNTL, 0, 0},
 187         {R_028814_PA_SU_SC_MODE_CNTL, 0, 0},
 188         {R_02881C_PA_CL_VS_OUT_CNTL, 0, 0},
 189         {R_028840_SQ_PGM_START_PS, REG_FLAG_NEED_BO, 0},
 190         {R_028844_SQ_PGM_RESOURCES_PS, 0, 0},
 191         {R_02884C_SQ_PGM_EXPORTS_PS, 0, 0},
 192         {R_02885C_SQ_PGM_START_VS, REG_FLAG_NEED_BO, 0},
 193         {R_028860_SQ_PGM_RESOURCES_VS, 0, 0},
 194         {R_0288A4_SQ_PGM_START_FS, REG_FLAG_NEED_BO, 0},
 195         {R_0288EC_SQ_LDS_ALLOC_PS, 0, 0},
 196         {R_028940_ALU_CONST_CACHE_PS_0, REG_FLAG_NEED_BO, 0},
 197         {R_028944_ALU_CONST_CACHE_PS_1, REG_FLAG_NEED_BO, 0},
 198         {R_028980_ALU_CONST_CACHE_VS_0, REG_FLAG_NEED_BO, 0},
 199         {R_028984_ALU_CONST_CACHE_VS_1, REG_FLAG_NEED_BO, 0},
 200         {R_028A00_PA_SU_POINT_SIZE, 0, 0},
 201         {R_028A04_PA_SU_POINT_MINMAX, 0, 0},
 202         {R_028A08_PA_SU_LINE_CNTL, 0, 0},
 203         {R_028A0C_PA_SC_LINE_STIPPLE, 0, 0},
 204         {R_028A48_PA_SC_MODE_CNTL_0, 0, 0},
 205         {R_028A6C_VGT_GS_OUT_PRIM_TYPE, 0, 0},
 206         {R_028ABC_DB_HTILE_SURFACE, 0, 0},
 207         {R_028B54_VGT_SHADER_STAGES_EN, 0, 0},
 208         {R_028B78_PA_SU_POLY_OFFSET_DB_FMT_CNTL, 0, 0},
 209         {R_028B7C_PA_SU_POLY_OFFSET_CLAMP, 0, 0},
 210         {R_028B80_PA_SU_POLY_OFFSET_FRONT_SCALE, 0, 0},
 211         {R_028B84_PA_SU_POLY_OFFSET_FRONT_OFFSET, 0, 0},
 212         {R_028B88_PA_SU_POLY_OFFSET_BACK_SCALE, 0, 0},
 213         {R_028B8C_PA_SU_POLY_OFFSET_BACK_OFFSET, 0, 0},
 214         {R_028C08_PA_SU_VTX_CNTL, 0, 0},
 215         {GROUP_FORCE_NEW_BLOCK, 0, 0},
 216         {R_028C60_CB_COLOR0_BASE, REG_FLAG_NEED_BO, 0},
 217         {R_028C64_CB_COLOR0_PITCH, 0, 0},
 218         {R_028C68_CB_COLOR0_SLICE, 0, 0},
 219         {R_028C6C_CB_COLOR0_VIEW, 0, 0},
 220         {R_028C70_CB_COLOR0_INFO, REG_FLAG_NEED_BO, 0},
 221         {R_028C74_CB_COLOR0_ATTRIB, REG_FLAG_NEED_BO, 0},
 222         {R_028C78_CB_COLOR0_DIM, 0, 0},
 223         {GROUP_FORCE_NEW_BLOCK, 0, 0},
 224         {R_028C9C_CB_COLOR1_BASE, REG_FLAG_NEED_BO, 0},
 225         {R_028CA0_CB_COLOR1_PITCH, 0, 0},
 226         {R_028CA4_CB_COLOR1_SLICE, 0, 0},
 227         {R_028CA8_CB_COLOR1_VIEW, 0, 0},
 228         {R_028CAC_CB_COLOR1_INFO, REG_FLAG_NEED_BO, 0},
 229         {R_028CB0_CB_COLOR1_ATTRIB, REG_FLAG_NEED_BO, 0},
 230         {R_028CB4_CB_COLOR1_DIM, 0, 0},
 231         {GROUP_FORCE_NEW_BLOCK, 0, 0},
 232         {R_028CD8_CB_COLOR2_BASE, REG_FLAG_NEED_BO, 0},
 233         {R_028CDC_CB_COLOR2_PITCH, 0, 0},
 234         {R_028CE0_CB_COLOR2_SLICE, 0, 0},
 235         {R_028CE4_CB_COLOR2_VIEW, 0, 0},
 236         {R_028CE8_CB_COLOR2_INFO, REG_FLAG_NEED_BO, 0},
 237         {R_028CEC_CB_COLOR2_ATTRIB, REG_FLAG_NEED_BO, 0},
 238         {R_028CF0_CB_COLOR2_DIM, 0, 0},
 239         {GROUP_FORCE_NEW_BLOCK, 0, 0},
 240         {R_028D14_CB_COLOR3_BASE, REG_FLAG_NEED_BO, 0},
 241         {R_028D18_CB_COLOR3_PITCH, 0, 0},
 242         {R_028D1C_CB_COLOR3_SLICE, 0, 0},
 243         {R_028D20_CB_COLOR3_VIEW, 0, 0},
 244         {R_028D24_CB_COLOR3_INFO, REG_FLAG_NEED_BO, 0},
 245         {R_028D28_CB_COLOR3_ATTRIB, REG_FLAG_NEED_BO, 0},
 246         {R_028D2C_CB_COLOR3_DIM, 0, 0},
 247         {GROUP_FORCE_NEW_BLOCK, 0, 0},
 248         {R_028D50_CB_COLOR4_BASE, REG_FLAG_NEED_BO, 0},
 249         {R_028D54_CB_COLOR4_PITCH, 0, 0},
 250         {R_028D58_CB_COLOR4_SLICE, 0, 0},
 251         {R_028D5C_CB_COLOR4_VIEW, 0, 0},
 252         {R_028D60_CB_COLOR4_INFO, REG_FLAG_NEED_BO, 0},
 253         {R_028D64_CB_COLOR4_ATTRIB, REG_FLAG_NEED_BO, 0},
 254         {R_028D68_CB_COLOR4_DIM, 0, 0},
 255         {GROUP_FORCE_NEW_BLOCK, 0, 0},
 256         {R_028D8C_CB_COLOR5_BASE, REG_FLAG_NEED_BO, 0},
 257         {R_028D90_CB_COLOR5_PITCH, 0, 0},
 258         {R_028D94_CB_COLOR5_SLICE, 0, 0},
 259         {R_028D98_CB_COLOR5_VIEW, 0, 0},
 260         {R_028D9C_CB_COLOR5_INFO, REG_FLAG_NEED_BO, 0},
 261         {R_028DA0_CB_COLOR5_ATTRIB, REG_FLAG_NEED_BO, 0},
 262         {R_028DA4_CB_COLOR5_DIM, 0, 0},
 263         {GROUP_FORCE_NEW_BLOCK, 0, 0},
 264         {R_028DC8_CB_COLOR6_BASE, REG_FLAG_NEED_BO, 0},
 265         {R_028DCC_CB_COLOR6_PITCH, 0, 0},
 266         {R_028DD0_CB_COLOR6_SLICE, 0, 0},
 267         {R_028DD4_CB_COLOR6_VIEW, 0, 0},
 268         {R_028DD8_CB_COLOR6_INFO, REG_FLAG_NEED_BO, 0},
 269         {R_028DDC_CB_COLOR6_ATTRIB, REG_FLAG_NEED_BO, 0},
 270         {R_028DE0_CB_COLOR6_DIM, 0, 0},
 271         {GROUP_FORCE_NEW_BLOCK, 0, 0},
 272         {R_028E04_CB_COLOR7_BASE, REG_FLAG_NEED_BO, 0},
 273         {R_028E08_CB_COLOR7_PITCH, 0, 0},
 274         {R_028E0C_CB_COLOR7_SLICE, 0, 0},
 275         {R_028E10_CB_COLOR7_VIEW, 0, 0},
 276         {R_028E14_CB_COLOR7_INFO, REG_FLAG_NEED_BO, 0},
 277         {R_028E18_CB_COLOR7_ATTRIB, REG_FLAG_NEED_BO, 0},
 278         {R_028E1C_CB_COLOR7_DIM, 0, 0},
 279         {GROUP_FORCE_NEW_BLOCK, 0, 0},
 280         {R_028E40_CB_COLOR8_BASE, REG_FLAG_NEED_BO, 0},
 281         {R_028E44_CB_COLOR8_PITCH, 0, 0},
 282         {R_028E48_CB_COLOR8_SLICE, 0, 0},
 283         {R_028E4C_CB_COLOR8_VIEW, 0, 0},
 284         {R_028E50_CB_COLOR8_INFO, REG_FLAG_NEED_BO, 0},
 285         {R_028E54_CB_COLOR8_ATTRIB, REG_FLAG_NEED_BO, 0},
 286         {R_028E58_CB_COLOR8_DIM, 0, 0},
 287         {GROUP_FORCE_NEW_BLOCK, 0, 0},
 288         {R_028E5C_CB_COLOR9_BASE, REG_FLAG_NEED_BO, 0},
 289         {R_028E60_CB_COLOR9_PITCH, 0, 0},
 290         {R_028E64_CB_COLOR9_SLICE, 0, 0},
 291         {R_028E68_CB_COLOR9_VIEW, 0, 0},
 292         {R_028E6C_CB_COLOR9_INFO, REG_FLAG_NEED_BO, 0},
 293         {R_028E70_CB_COLOR9_ATTRIB, REG_FLAG_NEED_BO, 0},
 294         {R_028E74_CB_COLOR9_DIM, 0, 0},
 295         {GROUP_FORCE_NEW_BLOCK, 0, 0},
 296         {R_028E78_CB_COLOR10_BASE, REG_FLAG_NEED_BO, 0},
 297         {R_028E7C_CB_COLOR10_PITCH, 0, 0},
 298         {R_028E80_CB_COLOR10_SLICE, 0, 0},
 299         {R_028E84_CB_COLOR10_VIEW, 0, 0},
 300         {R_028E88_CB_COLOR10_INFO, REG_FLAG_NEED_BO, 0},
 301         {R_028E8C_CB_COLOR10_ATTRIB, REG_FLAG_NEED_BO, 0},
 302         {R_028E90_CB_COLOR10_DIM, 0, 0},
 303         {GROUP_FORCE_NEW_BLOCK, 0, 0},
 304         {R_028E94_CB_COLOR11_BASE, REG_FLAG_NEED_BO, 0},
 305         {R_028E98_CB_COLOR11_PITCH, 0, 0},
 306         {R_028E9C_CB_COLOR11_SLICE, 0, 0},
 307         {R_028EA0_CB_COLOR11_VIEW, 0, 0},
 308         {R_028EA4_CB_COLOR11_INFO, REG_FLAG_NEED_BO, 0},
 309         {R_028EA8_CB_COLOR11_ATTRIB, REG_FLAG_NEED_BO, 0},
 310         {R_028EAC_CB_COLOR11_DIM, 0, 0},
 311 };
 312
 313 static const struct r600_reg cayman_context_reg_list[] = {
 314         {R_028000_DB_RENDER_CONTROL, 0, 0},
 315         {R_028008_DB_DEPTH_VIEW, 0, 0},
 316         {R_028010_DB_RENDER_OVERRIDE2, 0, 0},
 317         {GROUP_FORCE_NEW_BLOCK, 0, 0},
 318         {R_028014_DB_HTILE_DATA_BASE, REG_FLAG_NEED_BO, 0},
 319         {GROUP_FORCE_NEW_BLOCK, 0, 0},
 320         {R_028040_DB_Z_INFO, REG_FLAG_NEED_BO, 0},
 321         {GROUP_FORCE_NEW_BLOCK, 0, 0},
 322         {R_028044_DB_STENCIL_INFO, 0, 0},
 323         {GROUP_FORCE_NEW_BLOCK, 0, 0},
 324         {R_028048_DB_Z_READ_BASE, REG_FLAG_NEED_BO, 0},
 325         {GROUP_FORCE_NEW_BLOCK, 0, 0},
 326         {R_02804C_DB_STENCIL_READ_BASE, REG_FLAG_NEED_BO, 0},
 327         {GROUP_FORCE_NEW_BLOCK, 0, 0},
 328         {R_028050_DB_Z_WRITE_BASE, REG_FLAG_NEED_BO, 0},
 329         {GROUP_FORCE_NEW_BLOCK, 0, 0},
 330         {R_028054_DB_STENCIL_WRITE_BASE, REG_FLAG_NEED_BO, 0},
 331         {GROUP_FORCE_NEW_BLOCK, 0, 0},
 332         {R_028058_DB_DEPTH_SIZE, 0, 0},
 333         {R_02805C_DB_DEPTH_SLICE, 0, 0},
 334         {R_028140_ALU_CONST_BUFFER_SIZE_PS_0, REG_FLAG_DIRTY_ALWAYS, 0},
 335         {R_028144_ALU_CONST_BUFFER_SIZE_PS_1, REG_FLAG_DIRTY_ALWAYS, 0},
 336         {R_028180_ALU_CONST_BUFFER_SIZE_VS_0, REG_FLAG_DIRTY_ALWAYS, 0},
 337         {R_028184_ALU_CONST_BUFFER_SIZE_VS_1, REG_FLAG_DIRTY_ALWAYS, 0},
 338         {R_028204_PA_SC_WINDOW_SCISSOR_TL, 0, 0},
 339         {R_028208_PA_SC_WINDOW_SCISSOR_BR, 0, 0},
 340         {R_028234_PA_SU_HARDWARE_SCREEN_OFFSET, 0, 0},
 341         {R_028238_CB_TARGET_MASK, 0, 0},
 342         {R_02823C_CB_SHADER_MASK, 0, 0},
 343         {R_028250_PA_SC_VPORT_SCISSOR_0_TL, 0, 0},
 344         {R_028254_PA_SC_VPORT_SCISSOR_0_BR, 0, 0},
 345         {R_028350_SX_MISC, 0, 0},
 346         {GROUP_FORCE_NEW_BLOCK, 0, 0},
 347         {R_028408_VGT_INDX_OFFSET, 0, 0},
 348         {R_02840C_VGT_MULTI_PRIM_IB_RESET_INDX, 0, 0},
 349         {R_028A94_VGT_MULTI_PRIM_IB_RESET_EN, 0, 0},
 350         {GROUP_FORCE_NEW_BLOCK, 0, 0},
 351         {R_028410_SX_ALPHA_TEST_CONTROL, 0, 0},
 352         {R_028414_CB_BLEND_RED, 0, 0},
 353         {R_028418_CB_BLEND_GREEN, 0, 0},
 354         {R_02841C_CB_BLEND_BLUE, 0, 0},
 355         {R_028420_CB_BLEND_ALPHA, 0, 0},
 356         {R_028430_DB_STENCILREFMASK, 0, 0},
 357         {R_028434_DB_STENCILREFMASK_BF, 0, 0},
 358         {R_028438_SX_ALPHA_REF, 0, 0},
 359         {R_02843C_PA_CL_VPORT_XSCALE_0, 0, 0},
 360         {R_028440_PA_CL_VPORT_XOFFSET_0, 0, 0},
 361         {R_028444_PA_CL_VPORT_YSCALE_0, 0, 0},
 362         {R_028448_PA_CL_VPORT_YOFFSET_0, 0, 0},
 363         {R_02844C_PA_CL_VPORT_ZSCALE_0, 0, 0},
 364         {R_028450_PA_CL_VPORT_ZOFFSET_0, 0, 0},
 365         {R_0285BC_PA_CL_UCP0_X, 0, 0},
 366         {R_0285C0_PA_CL_UCP0_Y, 0, 0},
 367         {R_0285C4_PA_CL_UCP0_Z, 0, 0},
 368         {R_0285C8_PA_CL_UCP0_W, 0, 0},
 369         {R_0285CC_PA_CL_UCP1_X, 0, 0},
 370         {R_0285D0_PA_CL_UCP1_Y, 0, 0},
 371         {R_0285D4_PA_CL_UCP1_Z, 0, 0},
 372         {R_0285D8_PA_CL_UCP1_W, 0, 0},
 373         {R_0285DC_PA_CL_UCP2_X, 0, 0},
 374         {R_0285E0_PA_CL_UCP2_Y, 0, 0},
 375         {R_0285E4_PA_CL_UCP2_Z, 0, 0},
 376         {R_0285E8_PA_CL_UCP2_W, 0, 0},
 377         {R_0285EC_PA_CL_UCP3_X, 0, 0},
 378         {R_0285F0_PA_CL_UCP3_Y, 0, 0},
 379         {R_0285F4_PA_CL_UCP3_Z, 0, 0},
 380         {R_0285F8_PA_CL_UCP3_W, 0, 0},
 381         {R_0285FC_PA_CL_UCP4_X, 0, 0},
 382         {R_028600_PA_CL_UCP4_Y, 0, 0},
 383         {R_028604_PA_CL_UCP4_Z, 0, 0},
 384         {R_028608_PA_CL_UCP4_W, 0, 0},
 385         {R_02860C_PA_CL_UCP5_X, 0, 0},
 386         {R_028610_PA_CL_UCP5_Y, 0, 0},
 387         {R_028614_PA_CL_UCP5_Z, 0, 0},
 388         {R_028618_PA_CL_UCP5_W, 0, 0},
 389         {R_02861C_SPI_VS_OUT_ID_0, 0, 0},
 390         {R_028620_SPI_VS_OUT_ID_1, 0, 0},
 391         {R_028624_SPI_VS_OUT_ID_2, 0, 0},
 392         {R_028628_SPI_VS_OUT_ID_3, 0, 0},
 393         {R_02862C_SPI_VS_OUT_ID_4, 0, 0},
 394         {R_028630_SPI_VS_OUT_ID_5, 0, 0},
 395         {R_028634_SPI_VS_OUT_ID_6, 0, 0},
 396         {R_028638_SPI_VS_OUT_ID_7, 0, 0},
 397         {R_02863C_SPI_VS_OUT_ID_8, 0, 0},
 398         {R_028640_SPI_VS_OUT_ID_9, 0, 0},
 399         {R_028644_SPI_PS_INPUT_CNTL_0, 0, 0},
 400         {R_028648_SPI_PS_INPUT_CNTL_1, 0, 0},
 401         {R_02864C_SPI_PS_INPUT_CNTL_2, 0, 0},
 402         {R_028650_SPI_PS_INPUT_CNTL_3, 0, 0},
 403         {R_028654_SPI_PS_INPUT_CNTL_4, 0, 0},
 404         {R_028658_SPI_PS_INPUT_CNTL_5, 0, 0},
 405         {R_02865C_SPI_PS_INPUT_CNTL_6, 0, 0},
 406         {R_028660_SPI_PS_INPUT_CNTL_7, 0, 0},
 407         {R_028664_SPI_PS_INPUT_CNTL_8, 0, 0},
 408         {R_028668_SPI_PS_INPUT_CNTL_9, 0, 0},
 409         {R_02866C_SPI_PS_INPUT_CNTL_10, 0, 0},
 410         {R_028670_SPI_PS_INPUT_CNTL_11, 0, 0},
 411         {R_028674_SPI_PS_INPUT_CNTL_12, 0, 0},
 412         {R_028678_SPI_PS_INPUT_CNTL_13, 0, 0},
 413         {R_02867C_SPI_PS_INPUT_CNTL_14, 0, 0},
 414         {R_028680_SPI_PS_INPUT_CNTL_15, 0, 0},
 415         {R_028684_SPI_PS_INPUT_CNTL_16, 0, 0},
 416         {R_028688_SPI_PS_INPUT_CNTL_17, 0, 0},
 417         {R_02868C_SPI_PS_INPUT_CNTL_18, 0, 0},
 418         {R_028690_SPI_PS_INPUT_CNTL_19, 0, 0},
 419         {R_028694_SPI_PS_INPUT_CNTL_20, 0, 0},
 420         {R_028698_SPI_PS_INPUT_CNTL_21, 0, 0},
 421         {R_02869C_SPI_PS_INPUT_CNTL_22, 0, 0},
 422         {R_0286A0_SPI_PS_INPUT_CNTL_23, 0, 0},
 423         {R_0286A4_SPI_PS_INPUT_CNTL_24, 0, 0},
 424         {R_0286A8_SPI_PS_INPUT_CNTL_25, 0, 0},
 425         {R_0286AC_SPI_PS_INPUT_CNTL_26, 0, 0},
 426         {R_0286B0_SPI_PS_INPUT_CNTL_27, 0, 0},
 427         {R_0286B4_SPI_PS_INPUT_CNTL_28, 0, 0},
 428         {R_0286B8_SPI_PS_INPUT_CNTL_29, 0, 0},
 429         {R_0286BC_SPI_PS_INPUT_CNTL_30, 0, 0},
 430         {R_0286C0_SPI_PS_INPUT_CNTL_31, 0, 0},
 431         {R_0286C4_SPI_VS_OUT_CONFIG, 0, 0},
 432         {R_0286C8_SPI_THREAD_GROUPING, 0, 0},
 433         {R_0286CC_SPI_PS_IN_CONTROL_0, 0, 0},
 434         {R_0286D0_SPI_PS_IN_CONTROL_1, 0, 0},
 435         {R_0286D4_SPI_INTERP_CONTROL_0, 0, 0},
 436         {R_0286D8_SPI_INPUT_Z, 0, 0},
 437         {R_0286E0_SPI_BARYC_CNTL, 0, 0},
 438         {R_0286E4_SPI_PS_IN_CONTROL_2, 0, 0},
 439         {R_0286E8_SPI_COMPUTE_INPUT_CNTL, 0, 0},
 440         {R_028780_CB_BLEND0_CONTROL, 0, 0},
 441         {R_028784_CB_BLEND1_CONTROL, 0, 0},
 442         {R_028788_CB_BLEND2_CONTROL, 0, 0},
 443         {R_02878C_CB_BLEND3_CONTROL, 0, 0},
 444         {R_028790_CB_BLEND4_CONTROL, 0, 0},
 445         {R_028794_CB_BLEND5_CONTROL, 0, 0},
 446         {R_028798_CB_BLEND6_CONTROL, 0, 0},
 447         {R_02879C_CB_BLEND7_CONTROL, 0, 0},
 448         {R_028800_DB_DEPTH_CONTROL, 0, 0},
 449         {R_028808_CB_COLOR_CONTROL, 0, 0},
 450         {R_02880C_DB_SHADER_CONTROL, 0, 0},
 451         {R_028810_PA_CL_CLIP_CNTL, 0, 0},
 452         {R_028814_PA_SU_SC_MODE_CNTL, 0, 0},
 453         {R_02881C_PA_CL_VS_OUT_CNTL, 0, 0},
 454         {R_028838_SQ_DYN_GPR_RESOURCE_LIMIT_1, 0, 0},
 455         {R_028840_SQ_PGM_START_PS, REG_FLAG_NEED_BO, 0},
 456         {R_028844_SQ_PGM_RESOURCES_PS, 0, 0},
 457         {R_02884C_SQ_PGM_EXPORTS_PS, 0, 0},
 458         {R_02885C_SQ_PGM_START_VS, REG_FLAG_NEED_BO, 0},
 459         {R_028860_SQ_PGM_RESOURCES_VS, 0, 0},
 460         {R_0288A4_SQ_PGM_START_FS, REG_FLAG_NEED_BO, 0},
 461         {R_028900_SQ_ESGS_RING_ITEMSIZE, 0, 0},
 462         {R_028904_SQ_GSVS_RING_ITEMSIZE, 0, 0},
 463         {R_028908_SQ_ESTMP_RING_ITEMSIZE, 0, 0},
 464         {R_02890C_SQ_GSTMP_RING_ITEMSIZE, 0, 0},
 465         {R_028910_SQ_VSTMP_RING_ITEMSIZE, 0, 0},
 466         {R_028914_SQ_PSTMP_RING_ITEMSIZE, 0, 0},
 467         {R_02891C_SQ_GS_VERT_ITEMSIZE, 0, 0},
 468         {R_028920_SQ_GS_VERT_ITEMSIZE_1, 0, 0},
 469         {R_028924_SQ_GS_VERT_ITEMSIZE_2, 0, 0},
 470         {R_028928_SQ_GS_VERT_ITEMSIZE_3, 0, 0},
 471         {R_028940_ALU_CONST_CACHE_PS_0, REG_FLAG_NEED_BO, 0},
 472         {R_028944_ALU_CONST_CACHE_PS_1, REG_FLAG_NEED_BO, 0},
 473         {R_028980_ALU_CONST_CACHE_VS_0, REG_FLAG_NEED_BO, 0},
 474         {R_028984_ALU_CONST_CACHE_VS_1, REG_FLAG_NEED_BO, 0},
 475         {R_028A00_PA_SU_POINT_SIZE, 0, 0},
 476         {R_028A04_PA_SU_POINT_MINMAX, 0, 0},
 477         {R_028A08_PA_SU_LINE_CNTL, 0, 0},
 478         {R_028A0C_PA_SC_LINE_STIPPLE, 0, 0},
 479         {R_028A48_PA_SC_MODE_CNTL_0, 0, 0},
 480         {R_028A6C_VGT_GS_OUT_PRIM_TYPE, 0, 0},
 481         {R_028ABC_DB_HTILE_SURFACE, 0, 0},
 482         {R_028B54_VGT_SHADER_STAGES_EN, 0, 0},
 483         {R_028B78_PA_SU_POLY_OFFSET_DB_FMT_CNTL, 0, 0},
 484         {R_028B7C_PA_SU_POLY_OFFSET_CLAMP, 0, 0},
 485         {R_028B80_PA_SU_POLY_OFFSET_FRONT_SCALE, 0, 0},
 486         {R_028B84_PA_SU_POLY_OFFSET_FRONT_OFFSET, 0, 0},
 487         {R_028B88_PA_SU_POLY_OFFSET_BACK_SCALE, 0, 0},
 488         {R_028B8C_PA_SU_POLY_OFFSET_BACK_OFFSET, 0, 0},
 489         {CM_R_028BE4_PA_SU_VTX_CNTL, 0, 0},
 490         {CM_R_028BF8_PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_0, 0, 0},
 491         {CM_R_028BFC_PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_1, 0, 0},
 492         {CM_R_028C00_PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_2, 0, 0},
 493         {CM_R_028C04_PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_3, 0, 0},
 494         {CM_R_028C08_PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_0, 0, 0},
 495         {CM_R_028C0C_PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_1, 0, 0},
 496         {CM_R_028C10_PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_2, 0, 0},
 497         {CM_R_028C14_PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_3, 0, 0},
 498         {CM_R_028C18_PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_0, 0, 0},
 499         {CM_R_028C1C_PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_1, 0, 0},
 500         {CM_R_028C20_PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_2, 0, 0},
 501         {CM_R_028C24_PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_3, 0, 0},
 502         {CM_R_028C28_PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_0, 0, 0},
 503         {CM_R_028C2C_PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_1, 0, 0},
 504         {CM_R_028C30_PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_2, 0, 0},
 505         {CM_R_028C34_PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_3, 0, 0},
 506         {GROUP_FORCE_NEW_BLOCK, 0, 0},
 507         {R_028C60_CB_COLOR0_BASE, REG_FLAG_NEED_BO, 0},
 508         {R_028C64_CB_COLOR0_PITCH, 0, 0},
 509         {R_028C68_CB_COLOR0_SLICE, 0, 0},
 510         {R_028C6C_CB_COLOR0_VIEW, 0, 0},
 511         {R_028C70_CB_COLOR0_INFO, REG_FLAG_NEED_BO, 0},
 512         {R_028C74_CB_COLOR0_ATTRIB, REG_FLAG_NEED_BO, 0},
 513         {R_028C78_CB_COLOR0_DIM, 0, 0},
 514         {GROUP_FORCE_NEW_BLOCK, 0, 0},
 515         {R_028C9C_CB_COLOR1_BASE, REG_FLAG_NEED_BO, 0},
 516         {R_028CA0_CB_COLOR1_PITCH, 0, 0},
 517         {R_028CA4_CB_COLOR1_SLICE, 0, 0},
 518         {R_028CA8_CB_COLOR1_VIEW, 0, 0},
 519         {R_028CAC_CB_COLOR1_INFO, REG_FLAG_NEED_BO, 0},
 520         {R_028CB0_CB_COLOR1_ATTRIB, REG_FLAG_NEED_BO, 0},
 521         {R_028CB4_CB_COLOR1_DIM, 0, 0},
 522         {GROUP_FORCE_NEW_BLOCK, 0, 0},
 523         {R_028CD8_CB_COLOR2_BASE, REG_FLAG_NEED_BO, 0},
 524         {R_028CDC_CB_COLOR2_PITCH, 0, 0},
 525         {R_028CE0_CB_COLOR2_SLICE, 0, 0},
 526         {R_028CE4_CB_COLOR2_VIEW, 0, 0},
 527         {R_028CE8_CB_COLOR2_INFO, REG_FLAG_NEED_BO, 0},
 528         {R_028CEC_CB_COLOR2_ATTRIB, REG_FLAG_NEED_BO, 0},
 529         {R_028CF0_CB_COLOR2_DIM, 0, 0},
 530         {GROUP_FORCE_NEW_BLOCK, 0, 0},
 531         {R_028D14_CB_COLOR3_BASE, REG_FLAG_NEED_BO, 0},
 532         {R_028D18_CB_COLOR3_PITCH, 0, 0},
 533         {R_028D1C_CB_COLOR3_SLICE, 0, 0},
 534         {R_028D20_CB_COLOR3_VIEW, 0, 0},
 535         {R_028D24_CB_COLOR3_INFO, REG_FLAG_NEED_BO, 0},
 536         {R_028D28_CB_COLOR3_ATTRIB, REG_FLAG_NEED_BO, 0},
 537         {R_028D2C_CB_COLOR3_DIM, 0, 0},
 538         {GROUP_FORCE_NEW_BLOCK, 0, 0},
 539         {R_028D50_CB_COLOR4_BASE, REG_FLAG_NEED_BO, 0},
 540         {R_028D54_CB_COLOR4_PITCH, 0, 0},
 541         {R_028D58_CB_COLOR4_SLICE, 0, 0},
 542         {R_028D5C_CB_COLOR4_VIEW, 0, 0},
 543         {R_028D60_CB_COLOR4_INFO, REG_FLAG_NEED_BO, 0},
 544         {R_028D64_CB_COLOR4_ATTRIB, REG_FLAG_NEED_BO, 0},
 545         {R_028D68_CB_COLOR4_DIM, 0, 0},
 546         {GROUP_FORCE_NEW_BLOCK, 0, 0},
 547         {R_028D8C_CB_COLOR5_BASE, REG_FLAG_NEED_BO, 0},
 548         {R_028D90_CB_COLOR5_PITCH, 0, 0},
 549         {R_028D94_CB_COLOR5_SLICE, 0, 0},
 550         {R_028D98_CB_COLOR5_VIEW, 0, 0},
 551         {R_028D9C_CB_COLOR5_INFO, REG_FLAG_NEED_BO, 0},
 552         {R_028DA0_CB_COLOR5_ATTRIB, REG_FLAG_NEED_BO, 0},
 553         {R_028DA4_CB_COLOR5_DIM, 0, 0},
 554         {GROUP_FORCE_NEW_BLOCK, 0, 0},
 555         {R_028DC8_CB_COLOR6_BASE, REG_FLAG_NEED_BO, 0},
 556         {R_028DCC_CB_COLOR6_PITCH, 0, 0},
 557         {R_028DD0_CB_COLOR6_SLICE, 0, 0},
 558         {R_028DD4_CB_COLOR6_VIEW, 0, 0},
 559         {R_028DD8_CB_COLOR6_INFO, REG_FLAG_NEED_BO, 0},
 560         {R_028DDC_CB_COLOR6_ATTRIB, REG_FLAG_NEED_BO, 0},
 561         {R_028DE0_CB_COLOR6_DIM, 0, 0},
 562         {GROUP_FORCE_NEW_BLOCK, 0, 0},
 563         {R_028E04_CB_COLOR7_BASE, REG_FLAG_NEED_BO, 0},
 564         {R_028E08_CB_COLOR7_PITCH, 0, 0},
 565         {R_028E0C_CB_COLOR7_SLICE, 0, 0},
 566         {R_028E10_CB_COLOR7_VIEW, 0, 0},
 567         {R_028E14_CB_COLOR7_INFO, REG_FLAG_NEED_BO, 0},
 568         {R_028E18_CB_COLOR7_ATTRIB, REG_FLAG_NEED_BO, 0},
 569         {R_028E1C_CB_COLOR7_DIM, 0, 0},
 570         {GROUP_FORCE_NEW_BLOCK, 0, 0},
 571         {R_028E40_CB_COLOR8_BASE, REG_FLAG_NEED_BO, 0},
 572         {R_028E44_CB_COLOR8_PITCH, 0, 0},
 573         {R_028E48_CB_COLOR8_SLICE, 0, 0},
 574         {R_028E4C_CB_COLOR8_VIEW, 0, 0},
 575         {R_028E50_CB_COLOR8_INFO, REG_FLAG_NEED_BO, 0},
 576         {R_028E54_CB_COLOR8_ATTRIB, REG_FLAG_NEED_BO, 0},
 577         {R_028E58_CB_COLOR8_DIM, 0, 0},
 578         {GROUP_FORCE_NEW_BLOCK, 0, 0},
 579         {R_028E5C_CB_COLOR9_BASE, REG_FLAG_NEED_BO, 0},
 580         {R_028E60_CB_COLOR9_PITCH, 0, 0},
 581         {R_028E64_CB_COLOR9_SLICE, 0, 0},
 582         {R_028E68_CB_COLOR9_VIEW, 0, 0},
 583         {R_028E6C_CB_COLOR9_INFO, REG_FLAG_NEED_BO, 0},
 584         {R_028E70_CB_COLOR9_ATTRIB, REG_FLAG_NEED_BO, 0},
 585         {R_028E74_CB_COLOR9_DIM, 0, 0},
 586         {GROUP_FORCE_NEW_BLOCK, 0, 0},
 587         {R_028E78_CB_COLOR10_BASE, REG_FLAG_NEED_BO, 0},
 588         {R_028E7C_CB_COLOR10_PITCH, 0, 0},
 589         {R_028E80_CB_COLOR10_SLICE, 0, 0},
 590         {R_028E84_CB_COLOR10_VIEW, 0, 0},
 591         {R_028E88_CB_COLOR10_INFO, REG_FLAG_NEED_BO, 0},
 592         {R_028E8C_CB_COLOR10_ATTRIB, REG_FLAG_NEED_BO, 0},
 593         {R_028E90_CB_COLOR10_DIM, 0, 0},
 594         {GROUP_FORCE_NEW_BLOCK, 0, 0},
 595         {R_028E94_CB_COLOR11_BASE, REG_FLAG_NEED_BO, 0},
 596         {R_028E98_CB_COLOR11_PITCH, 0, 0},
 597         {R_028E9C_CB_COLOR11_SLICE, 0, 0},
 598         {R_028EA0_CB_COLOR11_VIEW, 0, 0},
 599         {R_028EA4_CB_COLOR11_INFO, REG_FLAG_NEED_BO, 0},
 600         {R_028EA8_CB_COLOR11_ATTRIB, REG_FLAG_NEED_BO, 0},
 601         {R_028EAC_CB_COLOR11_DIM, 0, 0},
 602 };
 603
 604 /* SHADER RESOURCE EG/CM */
 605 static int evergreen_resource_range_init(struct r600_context *ctx, struct r600_range *range, unsigned offset, unsigned nblocks, unsigned stride)
 606 {
 607         struct r600_reg r600_shader_resource[] = {
 608                 {R_030000_RESOURCE0_WORD0, REG_FLAG_NEED_BO, 0},
 609                 {R_030004_RESOURCE0_WORD1, REG_FLAG_NEED_BO, 0},
 610                 {R_030008_RESOURCE0_WORD2, 0, 0},
 611                 {R_03000C_RESOURCE0_WORD3, 0, 0},
 612                 {R_030010_RESOURCE0_WORD4, 0, 0},
 613                 {R_030014_RESOURCE0_WORD5, 0, 0},
 614                 {R_030018_RESOURCE0_WORD6, 0, 0},
 615                 {R_03001C_RESOURCE0_WORD7, 0, 0},
 616         };
 617         unsigned nreg = Elements(r600_shader_resource);
 618
 619         return r600_resource_init(ctx, range, offset, nblocks, stride, r600_shader_resource, nreg, EVERGREEN_RESOURCE_OFFSET);
 620 }
 621
 622 /* SHADER SAMPLER BORDER EG/CM */
 623 static int evergreen_state_sampler_border_init(struct r600_context *ctx, uint32_t offset, unsigned id)
 624 {
 625         struct r600_reg r600_shader_sampler_border[] = {
 626                 {R_00A400_TD_PS_SAMPLER0_BORDER_INDEX, 0, 0},
 627                 {R_00A404_TD_PS_SAMPLER0_BORDER_RED, 0, 0},
 628                 {R_00A408_TD_PS_SAMPLER0_BORDER_GREEN, 0, 0},
 629                 {R_00A40C_TD_PS_SAMPLER0_BORDER_BLUE, 0, 0},
 630                 {R_00A410_TD_PS_SAMPLER0_BORDER_ALPHA, 0, 0},
 631         };
 632         unsigned nreg = Elements(r600_shader_sampler_border);
 633         unsigned fake_offset = (offset - R_00A400_TD_PS_SAMPLER0_BORDER_INDEX) * 0x100 + 0x40000 + id * 0x1C;
 634         struct r600_range *range;
 635         struct r600_block *block;
 636         int r;
 637
 638         for (int i = 0; i < nreg; i++) {
 639                 r600_shader_sampler_border[i].offset -= R_00A400_TD_PS_SAMPLER0_BORDER_INDEX;
 640                 r600_shader_sampler_border[i].offset += fake_offset;
 641         }
 642         r = r600_context_add_block(ctx, r600_shader_sampler_border, nreg, PKT3_SET_CONFIG_REG, 0);
 643         if (r) {
 644                 return r;
 645         }
 646         /* set proper offset */
 647         range = &ctx->range[CTX_RANGE_ID(r600_shader_sampler_border[0].offset)];
 648         block = range->blocks[CTX_BLOCK_ID(r600_shader_sampler_border[0].offset)];
 649         block->pm4[1] = (offset - EVERGREEN_CONFIG_REG_OFFSET) >> 2;
 650         return 0;
 651 }
 652
 653 static int evergreen_loop_const_init(struct r600_context *ctx, uint32_t offset)
 654 {
 655         unsigned nreg = 32;
 656         struct r600_reg r600_loop_consts[32];
 657         int i;
 658
 659         for (i = 0; i < nreg; i++) {
 660                 r600_loop_consts[i].offset = EVERGREEN_LOOP_CONST_OFFSET + ((offset + i) * 4);
 661                 r600_loop_consts[i].flags = REG_FLAG_DIRTY_ALWAYS;
 662                 r600_loop_consts[i].sbu_flags = 0;
 663         }
 664         return r600_context_add_block(ctx, r600_loop_consts, nreg, PKT3_SET_LOOP_CONST, EVERGREEN_LOOP_CONST_OFFSET);
 665 }
 666
 667 int evergreen_context_init(struct r600_context *ctx)
 668 {
 669         int r;
 670
 671         /* add blocks */
 672         if (ctx->family == CHIP_CAYMAN)
 673                 r = r600_context_add_block(ctx, cayman_config_reg_list,
 674                                            Elements(cayman_config_reg_list), PKT3_SET_CONFIG_REG, EVERGREEN_CONFIG_REG_OFFSET);
 675         else
 676                 r = r600_context_add_block(ctx, evergreen_config_reg_list,
 677                                            Elements(evergreen_config_reg_list), PKT3_SET_CONFIG_REG, EVERGREEN_CONFIG_REG_OFFSET);
 678         if (r)
 679                 goto out_err;
 680         if (ctx->family == CHIP_CAYMAN)
 681                 r = r600_context_add_block(ctx, cayman_context_reg_list,
 682                                            Elements(cayman_context_reg_list), PKT3_SET_CONTEXT_REG, EVERGREEN_CONTEXT_REG_OFFSET);
 683         else
 684                 r = r600_context_add_block(ctx, evergreen_context_reg_list,
 685                                            Elements(evergreen_context_reg_list), PKT3_SET_CONTEXT_REG, EVERGREEN_CONTEXT_REG_OFFSET);
 686         if (r)
 687                 goto out_err;
 688         r = r600_context_add_block(ctx, evergreen_ctl_const_list,
 689                                    Elements(evergreen_ctl_const_list), PKT3_SET_CTL_CONST, EVERGREEN_CTL_CONST_OFFSET);
 690         if (r)
 691                 goto out_err;
 692
 693
 694         /* PS SAMPLER */
 695         for (int j = 0, offset = 0; j < 18; j++, offset += 0xC) {
 696                 r = r600_state_sampler_init(ctx, offset);
 697                 if (r)
 698                         goto out_err;
 699         }
 700         /* VS SAMPLER */
 701         for (int j = 0, offset = 0xD8; j < 18; j++, offset += 0xC) {
 702                 r = r600_state_sampler_init(ctx, offset);
 703                 if (r)
 704                         goto out_err;
 705         }
 706         /* PS SAMPLER BORDER */
 707         for (int j = 0; j < 18; j++) {
 708                 r = evergreen_state_sampler_border_init(ctx, R_00A400_TD_PS_SAMPLER0_BORDER_INDEX, j);
 709                 if (r)
 710                         goto out_err;
 711         }
 712         /* VS SAMPLER BORDER */
 713         for (int j = 0; j < 18; j++) {
 714                 r = evergreen_state_sampler_border_init(ctx, R_00A414_TD_VS_SAMPLER0_BORDER_INDEX, j);
 715                 if (r)
 716                         goto out_err;
 717         }
 718
 719         ctx->num_ps_resources = 176;
 720         ctx->num_vs_resources = 160;
 721         ctx->num_fs_resources = 16;
 722         r = evergreen_resource_range_init(ctx, &ctx->ps_resources, 0, 176, 0x20);
 723         if (r)
 724                 goto out_err;
 725         r = evergreen_resource_range_init(ctx, &ctx->vs_resources, 0x1600, 160, 0x20);
 726         if (r)
 727                 goto out_err;
 728         r = evergreen_resource_range_init(ctx, &ctx->fs_resources, 0x7C00, 16, 0x20);
 729         if (r)
 730                 goto out_err;
 731
 732         /* PS loop const */
 733         evergreen_loop_const_init(ctx, 0);
 734         /* VS loop const */
 735         evergreen_loop_const_init(ctx, 32);
 736
 737         r = r600_setup_block_table(ctx);
 738         if (r)
 739                 goto out_err;
 740
 741         ctx->max_db = 8;
 742         return 0;
 743 out_err:
 744         r600_context_fini(ctx);
 745         return r;
 746 }
 747
 748 static inline void evergreen_context_pipe_state_set_sampler_border(struct r600_context *ctx, struct r600_pipe_state *state, unsigned offset, unsigned id)
 749 {
 750         unsigned fake_offset = (offset - R_00A400_TD_PS_SAMPLER0_BORDER_INDEX) * 0x100 + 0x40000 + id * 0x1C;
 751         struct r600_range *range;
 752         struct r600_block *block;
 753         int i;
 754         int dirty;
 755
 756         range = &ctx->range[CTX_RANGE_ID(fake_offset)];
 757         block = range->blocks[CTX_BLOCK_ID(fake_offset)];
 758         if (state == NULL) {
 759                 block->status &= ~(R600_BLOCK_STATUS_ENABLED | R600_BLOCK_STATUS_DIRTY);
 760                 LIST_DELINIT(&block->list);
 761                 LIST_DELINIT(&block->enable_list);
 762                 return;
 763         }
 764         if (state->nregs <= 3) {
 765                 return;
 766         }
 767
 768         dirty = block->status & R600_BLOCK_STATUS_DIRTY;
 769         if (block->reg[0] != id) {
 770                 block->reg[0] = id;
 771                 dirty |= R600_BLOCK_STATUS_DIRTY;
 772         }
 773
 774         for (i = 1; i < 5; i++) {
 775                 if (block->reg[i] != state->regs[i + 2].value) {
 776                         block->reg[i] = state->regs[i + 2].value;
 777                         dirty |= R600_BLOCK_STATUS_DIRTY;
 778                 }
 779         }
 780
 781         /* We have to flush the shaders before we change the border color
 782          * registers, or previous draw commands that haven't completed yet
 783          * will end up using the new border color. */
 784         if (dirty & R600_BLOCK_STATUS_DIRTY)
 785                 r600_context_ps_partial_flush(ctx);
 786         if (dirty)
 787                 r600_context_dirty_block(ctx, block, dirty, 4);
 788 }
 789
 790 void evergreen_context_pipe_state_set_ps_sampler(struct r600_context *ctx, struct r600_pipe_state *state, unsigned id)
 791 {
 792         unsigned offset;
 793
 794         offset = R_03C000_SQ_TEX_SAMPLER_WORD0_0 + 12*id;
 795         r600_context_pipe_state_set_sampler(ctx, state, offset);
 796         evergreen_context_pipe_state_set_sampler_border(ctx, state, R_00A400_TD_PS_SAMPLER0_BORDER_INDEX, id);
 797 }
 798
 799 void evergreen_context_pipe_state_set_vs_sampler(struct r600_context *ctx, struct r600_pipe_state *state, unsigned id)
 800 {
 801         unsigned offset;
 802
 803         offset = R_03C000_SQ_TEX_SAMPLER_WORD0_0 + 12*(id + 18);
 804         r600_context_pipe_state_set_sampler(ctx, state, offset);
 805         evergreen_context_pipe_state_set_sampler_border(ctx, state, R_00A414_TD_VS_SAMPLER0_BORDER_INDEX, id);
 806 }
 807
 808 void evergreen_flush_vgt_streamout(struct r600_context *ctx)
 809 {
 810         struct radeon_winsys_cs *cs = ctx->cs;
 811
 812         cs->buf[cs->cdw++] = PKT3(PKT3_SET_CONFIG_REG, 1, 0);
 813         cs->buf[cs->cdw++] = (R_0084FC_CP_STRMOUT_CNTL - EVERGREEN_CONFIG_REG_OFFSET) >> 2;
 814         cs->buf[cs->cdw++] = 0;
 815
 816         cs->buf[cs->cdw++] = PKT3(PKT3_EVENT_WRITE, 0, 0);
 817         cs->buf[cs->cdw++] = EVENT_TYPE(EVENT_TYPE_SO_VGTSTREAMOUT_FLUSH) | EVENT_INDEX(0);
 818
 819         cs->buf[cs->cdw++] = PKT3(PKT3_WAIT_REG_MEM, 5, 0);
 820         cs->buf[cs->cdw++] = WAIT_REG_MEM_EQUAL; /* wait until the register is equal to the reference value */
 821         cs->buf[cs->cdw++] = R_0084FC_CP_STRMOUT_CNTL >> 2;  /* register */
 822         cs->buf[cs->cdw++] = 0;
 823         cs->buf[cs->cdw++] = S_0084FC_OFFSET_UPDATE_DONE(1); /* reference value */
 824         cs->buf[cs->cdw++] = S_0084FC_OFFSET_UPDATE_DONE(1); /* mask */
 825         cs->buf[cs->cdw++] = 4; /* poll interval */
 826 }
 827
 828 void evergreen_set_streamout_enable(struct r600_context *ctx, unsigned buffer_enable_bit)
 829 {
 830         struct radeon_winsys_cs *cs = ctx->cs;
 831         bool enable = buffer_enable_bit != 0;
 832
 833         if (enable != ctx->atom_eg_strmout_config.stream0_enable) {
 834                 ctx->atom_eg_strmout_config.stream0_enable = enable;
 835                 r600_emit_atom(ctx, &ctx->atom_eg_strmout_config.atom);
 836         }
 837
 838         if (buffer_enable_bit) {
 839                 cs->buf[cs->cdw++] = PKT3(PKT3_SET_CONTEXT_REG, 1, 0);
 840                 cs->buf[cs->cdw++] = (R_028B98_VGT_STRMOUT_BUFFER_CONFIG - EVERGREEN_CONTEXT_REG_OFFSET) >> 2;
 841                 cs->buf[cs->cdw++] = S_028B98_STREAM_0_BUFFER_EN(buffer_enable_bit);
 842         }
 843 }