src/gallium/drivers/r600/evergreen_hw_context.c

   1 /*
   2  * Copyright 2010 Jerome Glisse <glisse@freedesktop.org>
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * on the rights to use, copy, modify, merge, publish, distribute, sub
   8  * license, and/or sell copies of the Software, and to permit persons to whom
   9  * the Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice (including the next
  12  * paragraph) shall be included in all copies or substantial portions of the
  13  * Software.
  14  *
  15  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  16  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  17  * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
  18  * THE AUTHOR(S) AND/OR THEIR SUPPLIERS BE LIABLE FOR ANY CLAIM,
  19  * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
  20  * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
  21  * USE OR OTHER DEALINGS IN THE SOFTWARE.
  22  *
  23  * Authors:
  24  *      Jerome Glisse
  25  */
  26 #include "r600_hw_context_priv.h"
  27 #include "evergreend.h"
  28 #include "util/u_memory.h"
  29
  30 static const struct r600_reg cayman_config_reg_list[] = {
  31         {R_009100_SPI_CONFIG_CNTL, REG_FLAG_ENABLE_ALWAYS | REG_FLAG_FLUSH_CHANGE, 0},
  32         {R_00913C_SPI_CONFIG_CNTL_1, REG_FLAG_ENABLE_ALWAYS | REG_FLAG_FLUSH_CHANGE, 0},
  33 };
  34
  35 static const struct r600_reg evergreen_context_reg_list[] = {
  36         {R_028010_DB_RENDER_OVERRIDE2, 0, 0},
  37         {GROUP_FORCE_NEW_BLOCK, 0, 0},
  38         {R_028014_DB_HTILE_DATA_BASE, REG_FLAG_NEED_BO, 0},
  39         {GROUP_FORCE_NEW_BLOCK, 0, 0},
  40         {R_028234_PA_SU_HARDWARE_SCREEN_OFFSET, 0, 0},
  41         {R_028350_SX_MISC, 0, 0},
  42         {GROUP_FORCE_NEW_BLOCK, 0, 0},
  43         {R_02861C_SPI_VS_OUT_ID_0, 0, 0},
  44         {R_028620_SPI_VS_OUT_ID_1, 0, 0},
  45         {R_028624_SPI_VS_OUT_ID_2, 0, 0},
  46         {R_028628_SPI_VS_OUT_ID_3, 0, 0},
  47         {R_02862C_SPI_VS_OUT_ID_4, 0, 0},
  48         {R_028630_SPI_VS_OUT_ID_5, 0, 0},
  49         {R_028634_SPI_VS_OUT_ID_6, 0, 0},
  50         {R_028638_SPI_VS_OUT_ID_7, 0, 0},
  51         {R_02863C_SPI_VS_OUT_ID_8, 0, 0},
  52         {R_028640_SPI_VS_OUT_ID_9, 0, 0},
  53         {GROUP_FORCE_NEW_BLOCK, 0, 0},
  54         {R_028644_SPI_PS_INPUT_CNTL_0, 0, 0},
  55         {R_028648_SPI_PS_INPUT_CNTL_1, 0, 0},
  56         {R_02864C_SPI_PS_INPUT_CNTL_2, 0, 0},
  57         {R_028650_SPI_PS_INPUT_CNTL_3, 0, 0},
  58         {R_028654_SPI_PS_INPUT_CNTL_4, 0, 0},
  59         {R_028658_SPI_PS_INPUT_CNTL_5, 0, 0},
  60         {R_02865C_SPI_PS_INPUT_CNTL_6, 0, 0},
  61         {R_028660_SPI_PS_INPUT_CNTL_7, 0, 0},
  62         {R_028664_SPI_PS_INPUT_CNTL_8, 0, 0},
  63         {R_028668_SPI_PS_INPUT_CNTL_9, 0, 0},
  64         {R_02866C_SPI_PS_INPUT_CNTL_10, 0, 0},
  65         {R_028670_SPI_PS_INPUT_CNTL_11, 0, 0},
  66         {R_028674_SPI_PS_INPUT_CNTL_12, 0, 0},
  67         {R_028678_SPI_PS_INPUT_CNTL_13, 0, 0},
  68         {R_02867C_SPI_PS_INPUT_CNTL_14, 0, 0},
  69         {R_028680_SPI_PS_INPUT_CNTL_15, 0, 0},
  70         {R_028684_SPI_PS_INPUT_CNTL_16, 0, 0},
  71         {R_028688_SPI_PS_INPUT_CNTL_17, 0, 0},
  72         {R_02868C_SPI_PS_INPUT_CNTL_18, 0, 0},
  73         {R_028690_SPI_PS_INPUT_CNTL_19, 0, 0},
  74         {R_028694_SPI_PS_INPUT_CNTL_20, 0, 0},
  75         {R_028698_SPI_PS_INPUT_CNTL_21, 0, 0},
  76         {R_02869C_SPI_PS_INPUT_CNTL_22, 0, 0},
  77         {R_0286A0_SPI_PS_INPUT_CNTL_23, 0, 0},
  78         {R_0286A4_SPI_PS_INPUT_CNTL_24, 0, 0},
  79         {R_0286A8_SPI_PS_INPUT_CNTL_25, 0, 0},
  80         {R_0286AC_SPI_PS_INPUT_CNTL_26, 0, 0},
  81         {R_0286B0_SPI_PS_INPUT_CNTL_27, 0, 0},
  82         {R_0286B4_SPI_PS_INPUT_CNTL_28, 0, 0},
  83         {R_0286B8_SPI_PS_INPUT_CNTL_29, 0, 0},
  84         {R_0286BC_SPI_PS_INPUT_CNTL_30, 0, 0},
  85         {R_0286C0_SPI_PS_INPUT_CNTL_31, 0, 0},
  86         {GROUP_FORCE_NEW_BLOCK, 0, 0},
  87         {R_0286C4_SPI_VS_OUT_CONFIG, 0, 0},
  88         {R_0286C8_SPI_THREAD_GROUPING, 0, 0},
  89         {R_0286CC_SPI_PS_IN_CONTROL_0, 0, 0},
  90         {R_0286D0_SPI_PS_IN_CONTROL_1, 0, 0},
  91         {R_0286D4_SPI_INTERP_CONTROL_0, 0, 0},
  92         {R_0286D8_SPI_INPUT_Z, 0, 0},
  93         {R_0286E0_SPI_BARYC_CNTL, 0, 0},
  94         {R_0286E4_SPI_PS_IN_CONTROL_2, 0, 0},
  95         {R_0286E8_SPI_COMPUTE_INPUT_CNTL, 0, 0},
  96         {R_028800_DB_DEPTH_CONTROL, 0, 0},
  97         {R_02880C_DB_SHADER_CONTROL, 0, 0},
  98         {R_028814_PA_SU_SC_MODE_CNTL, 0, 0},
  99         {R_028840_SQ_PGM_START_PS, REG_FLAG_NEED_BO, 0},
 100         {R_028844_SQ_PGM_RESOURCES_PS, 0, 0},
 101         {R_02884C_SQ_PGM_EXPORTS_PS, 0, 0},
 102         {R_02885C_SQ_PGM_START_VS, REG_FLAG_NEED_BO, 0},
 103         {R_028860_SQ_PGM_RESOURCES_VS, 0, 0},
 104         {R_0288EC_SQ_LDS_ALLOC_PS, 0, 0},
 105         {R_028A00_PA_SU_POINT_SIZE, 0, 0},
 106         {R_028A04_PA_SU_POINT_MINMAX, 0, 0},
 107         {R_028A08_PA_SU_LINE_CNTL, 0, 0},
 108         {R_028A48_PA_SC_MODE_CNTL_0, 0, 0},
 109         {R_028ABC_DB_HTILE_SURFACE, 0, 0},
 110         {R_028B54_VGT_SHADER_STAGES_EN, 0, 0},
 111         {R_028B7C_PA_SU_POLY_OFFSET_CLAMP, 0, 0},
 112         {R_028C08_PA_SU_VTX_CNTL, 0, 0},
 113 };
 114
 115 static const struct r600_reg cayman_context_reg_list[] = {
 116         {R_028010_DB_RENDER_OVERRIDE2, 0, 0},
 117         {GROUP_FORCE_NEW_BLOCK, 0, 0},
 118         {R_028014_DB_HTILE_DATA_BASE, REG_FLAG_NEED_BO, 0},
 119         {GROUP_FORCE_NEW_BLOCK, 0, 0},
 120         {R_028234_PA_SU_HARDWARE_SCREEN_OFFSET, 0, 0},
 121         {R_028350_SX_MISC, 0, 0},
 122         {GROUP_FORCE_NEW_BLOCK, 0, 0},
 123         {R_02861C_SPI_VS_OUT_ID_0, 0, 0},
 124         {R_028620_SPI_VS_OUT_ID_1, 0, 0},
 125         {R_028624_SPI_VS_OUT_ID_2, 0, 0},
 126         {R_028628_SPI_VS_OUT_ID_3, 0, 0},
 127         {R_02862C_SPI_VS_OUT_ID_4, 0, 0},
 128         {R_028630_SPI_VS_OUT_ID_5, 0, 0},
 129         {R_028634_SPI_VS_OUT_ID_6, 0, 0},
 130         {R_028638_SPI_VS_OUT_ID_7, 0, 0},
 131         {R_02863C_SPI_VS_OUT_ID_8, 0, 0},
 132         {R_028640_SPI_VS_OUT_ID_9, 0, 0},
 133         {R_028644_SPI_PS_INPUT_CNTL_0, 0, 0},
 134         {R_028648_SPI_PS_INPUT_CNTL_1, 0, 0},
 135         {R_02864C_SPI_PS_INPUT_CNTL_2, 0, 0},
 136         {R_028650_SPI_PS_INPUT_CNTL_3, 0, 0},
 137         {R_028654_SPI_PS_INPUT_CNTL_4, 0, 0},
 138         {R_028658_SPI_PS_INPUT_CNTL_5, 0, 0},
 139         {R_02865C_SPI_PS_INPUT_CNTL_6, 0, 0},
 140         {R_028660_SPI_PS_INPUT_CNTL_7, 0, 0},
 141         {R_028664_SPI_PS_INPUT_CNTL_8, 0, 0},
 142         {R_028668_SPI_PS_INPUT_CNTL_9, 0, 0},
 143         {R_02866C_SPI_PS_INPUT_CNTL_10, 0, 0},
 144         {R_028670_SPI_PS_INPUT_CNTL_11, 0, 0},
 145         {R_028674_SPI_PS_INPUT_CNTL_12, 0, 0},
 146         {R_028678_SPI_PS_INPUT_CNTL_13, 0, 0},
 147         {R_02867C_SPI_PS_INPUT_CNTL_14, 0, 0},
 148         {R_028680_SPI_PS_INPUT_CNTL_15, 0, 0},
 149         {R_028684_SPI_PS_INPUT_CNTL_16, 0, 0},
 150         {R_028688_SPI_PS_INPUT_CNTL_17, 0, 0},
 151         {R_02868C_SPI_PS_INPUT_CNTL_18, 0, 0},
 152         {R_028690_SPI_PS_INPUT_CNTL_19, 0, 0},
 153         {R_028694_SPI_PS_INPUT_CNTL_20, 0, 0},
 154         {R_028698_SPI_PS_INPUT_CNTL_21, 0, 0},
 155         {R_02869C_SPI_PS_INPUT_CNTL_22, 0, 0},
 156         {R_0286A0_SPI_PS_INPUT_CNTL_23, 0, 0},
 157         {R_0286A4_SPI_PS_INPUT_CNTL_24, 0, 0},
 158         {R_0286A8_SPI_PS_INPUT_CNTL_25, 0, 0},
 159         {R_0286AC_SPI_PS_INPUT_CNTL_26, 0, 0},
 160         {R_0286B0_SPI_PS_INPUT_CNTL_27, 0, 0},
 161         {R_0286B4_SPI_PS_INPUT_CNTL_28, 0, 0},
 162         {R_0286B8_SPI_PS_INPUT_CNTL_29, 0, 0},
 163         {R_0286BC_SPI_PS_INPUT_CNTL_30, 0, 0},
 164         {R_0286C0_SPI_PS_INPUT_CNTL_31, 0, 0},
 165         {R_0286C4_SPI_VS_OUT_CONFIG, 0, 0},
 166         {R_0286C8_SPI_THREAD_GROUPING, 0, 0},
 167         {R_0286CC_SPI_PS_IN_CONTROL_0, 0, 0},
 168         {R_0286D0_SPI_PS_IN_CONTROL_1, 0, 0},
 169         {R_0286D4_SPI_INTERP_CONTROL_0, 0, 0},
 170         {R_0286D8_SPI_INPUT_Z, 0, 0},
 171         {R_0286E0_SPI_BARYC_CNTL, 0, 0},
 172         {R_0286E4_SPI_PS_IN_CONTROL_2, 0, 0},
 173         {R_0286E8_SPI_COMPUTE_INPUT_CNTL, 0, 0},
 174         {R_028800_DB_DEPTH_CONTROL, 0, 0},
 175         {R_02880C_DB_SHADER_CONTROL, 0, 0},
 176         {R_028814_PA_SU_SC_MODE_CNTL, 0, 0},
 177         {R_028838_SQ_DYN_GPR_RESOURCE_LIMIT_1, 0, 0},
 178         {R_028840_SQ_PGM_START_PS, REG_FLAG_NEED_BO, 0},
 179         {R_028844_SQ_PGM_RESOURCES_PS, 0, 0},
 180         {R_02884C_SQ_PGM_EXPORTS_PS, 0, 0},
 181         {R_02885C_SQ_PGM_START_VS, REG_FLAG_NEED_BO, 0},
 182         {R_028860_SQ_PGM_RESOURCES_VS, 0, 0},
 183         {R_028900_SQ_ESGS_RING_ITEMSIZE, 0, 0},
 184         {R_028904_SQ_GSVS_RING_ITEMSIZE, 0, 0},
 185         {R_028908_SQ_ESTMP_RING_ITEMSIZE, 0, 0},
 186         {R_02890C_SQ_GSTMP_RING_ITEMSIZE, 0, 0},
 187         {R_028910_SQ_VSTMP_RING_ITEMSIZE, 0, 0},
 188         {R_028914_SQ_PSTMP_RING_ITEMSIZE, 0, 0},
 189         {R_02891C_SQ_GS_VERT_ITEMSIZE, 0, 0},
 190         {R_028920_SQ_GS_VERT_ITEMSIZE_1, 0, 0},
 191         {R_028924_SQ_GS_VERT_ITEMSIZE_2, 0, 0},
 192         {R_028928_SQ_GS_VERT_ITEMSIZE_3, 0, 0},
 193         {R_028A00_PA_SU_POINT_SIZE, 0, 0},
 194         {R_028A04_PA_SU_POINT_MINMAX, 0, 0},
 195         {R_028A08_PA_SU_LINE_CNTL, 0, 0},
 196         {R_028A48_PA_SC_MODE_CNTL_0, 0, 0},
 197         {R_028ABC_DB_HTILE_SURFACE, 0, 0},
 198         {R_028B54_VGT_SHADER_STAGES_EN, 0, 0},
 199         {R_028B7C_PA_SU_POLY_OFFSET_CLAMP, 0, 0},
 200         {CM_R_028BE4_PA_SU_VTX_CNTL, 0, 0},
 201 };
 202
 203 int evergreen_context_init(struct r600_context *ctx)
 204 {
 205         int r = 0;
 206
 207         /* add blocks */
 208         if (ctx->family >= CHIP_CAYMAN)
 209                 r = r600_context_add_block(ctx, cayman_config_reg_list,
 210                                            Elements(cayman_config_reg_list), PKT3_SET_CONFIG_REG, EVERGREEN_CONFIG_REG_OFFSET);
 211         if (r)
 212                 goto out_err;
 213         if (ctx->family >= CHIP_CAYMAN)
 214                 r = r600_context_add_block(ctx, cayman_context_reg_list,
 215                                            Elements(cayman_context_reg_list), PKT3_SET_CONTEXT_REG, EVERGREEN_CONTEXT_REG_OFFSET);
 216         else
 217                 r = r600_context_add_block(ctx, evergreen_context_reg_list,
 218                                            Elements(evergreen_context_reg_list), PKT3_SET_CONTEXT_REG, EVERGREEN_CONTEXT_REG_OFFSET);
 219         if (r)
 220                 goto out_err;
 221
 222         r = r600_setup_block_table(ctx);
 223         if (r)
 224                 goto out_err;
 225
 226         ctx->max_db = 8;
 227         return 0;
 228 out_err:
 229         r600_context_fini(ctx);
 230         return r;
 231 }
 232
 233 void evergreen_flush_vgt_streamout(struct r600_context *ctx)
 234 {
 235         struct radeon_winsys_cs *cs = ctx->cs;
 236
 237         r600_write_config_reg(cs, R_0084FC_CP_STRMOUT_CNTL, 0);
 238
 239         cs->buf[cs->cdw++] = PKT3(PKT3_EVENT_WRITE, 0, 0);
 240         cs->buf[cs->cdw++] = EVENT_TYPE(EVENT_TYPE_SO_VGTSTREAMOUT_FLUSH) | EVENT_INDEX(0);
 241
 242         cs->buf[cs->cdw++] = PKT3(PKT3_WAIT_REG_MEM, 5, 0);
 243         cs->buf[cs->cdw++] = WAIT_REG_MEM_EQUAL; /* wait until the register is equal to the reference value */
 244         cs->buf[cs->cdw++] = R_0084FC_CP_STRMOUT_CNTL >> 2;  /* register */
 245         cs->buf[cs->cdw++] = 0;
 246         cs->buf[cs->cdw++] = S_0084FC_OFFSET_UPDATE_DONE(1); /* reference value */
 247         cs->buf[cs->cdw++] = S_0084FC_OFFSET_UPDATE_DONE(1); /* mask */
 248         cs->buf[cs->cdw++] = 4; /* poll interval */
 249 }
 250
 251 void evergreen_set_streamout_enable(struct r600_context *ctx, unsigned buffer_enable_bit)
 252 {
 253         struct radeon_winsys_cs *cs = ctx->cs;
 254
 255         if (buffer_enable_bit) {
 256                 r600_write_context_reg_seq(cs, R_028B94_VGT_STRMOUT_CONFIG, 2);
 257                 r600_write_value(cs, S_028B94_STREAMOUT_0_EN(1)); /* R_028B94_VGT_STRMOUT_CONFIG */
 258                 r600_write_value(cs, S_028B98_STREAM_0_BUFFER_EN(buffer_enable_bit)); /* R_028B98_VGT_STRMOUT_BUFFER_CONFIG */
 259         } else {
 260                 r600_write_context_reg(cs, R_028B94_VGT_STRMOUT_CONFIG, S_028B94_STREAMOUT_0_EN(0));
 261         }
 262 }