src/gallium/drivers/r600/evergreen_hw_context.c

   1 /*
   2  * Copyright 2010 Jerome Glisse <glisse@freedesktop.org>
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * on the rights to use, copy, modify, merge, publish, distribute, sub
   8  * license, and/or sell copies of the Software, and to permit persons to whom
   9  * the Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice (including the next
  12  * paragraph) shall be included in all copies or substantial portions of the
  13  * Software.
  14  *
  15  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  16  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  17  * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
  18  * THE AUTHOR(S) AND/OR THEIR SUPPLIERS BE LIABLE FOR ANY CLAIM,
  19  * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
  20  * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
  21  * USE OR OTHER DEALINGS IN THE SOFTWARE.
  22  *
  23  * Authors:
  24  *      Jerome Glisse
  25  */
  26 #include "r600_pipe.h"
  27 #include "evergreend.h"
  28 #include "util/u_memory.h"
  29 #include "util/u_math.h"
  30
  31 void evergreen_dma_copy(struct r600_context *rctx,
  32                 struct pipe_resource *dst,
  33                 struct pipe_resource *src,
  34                 uint64_t dst_offset,
  35                 uint64_t src_offset,
  36                 uint64_t size)
  37 {
  38         struct radeon_winsys_cs *cs = rctx->b.rings.dma.cs;
  39         unsigned i, ncopy, csize, sub_cmd, shift;
  40         struct r600_resource *rdst = (struct r600_resource*)dst;
  41         struct r600_resource *rsrc = (struct r600_resource*)src;
  42
  43         /* make sure that the dma ring is only one active */
  44         rctx->b.rings.gfx.flush(rctx, RADEON_FLUSH_ASYNC);
  45         dst_offset += r600_resource_va(&rctx->screen->b.b, dst);
  46         src_offset += r600_resource_va(&rctx->screen->b.b, src);
  47
  48         /* see if we use dword or byte copy */
  49         if (!(dst_offset & 0x3) && !(src_offset & 0x3) && !(size & 0x3)) {
  50                 size >>= 2;
  51                 sub_cmd = 0x00;
  52                 shift = 2;
  53         } else {
  54                 sub_cmd = 0x40;
  55                 shift = 0;
  56         }
  57         ncopy = (size / 0x000fffff) + !!(size % 0x000fffff);
  58
  59         r600_need_dma_space(rctx, ncopy * 5);
  60         for (i = 0; i < ncopy; i++) {
  61                 csize = size < 0x000fffff ? size : 0x000fffff;
  62                 /* emit reloc before writting cs so that cs is always in consistent state */
  63                 r600_context_bo_reloc(&rctx->b, &rctx->b.rings.dma, rsrc, RADEON_USAGE_READ);
  64                 r600_context_bo_reloc(&rctx->b, &rctx->b.rings.dma, rdst, RADEON_USAGE_WRITE);
  65                 cs->buf[cs->cdw++] = DMA_PACKET(DMA_PACKET_COPY, sub_cmd, csize);
  66                 cs->buf[cs->cdw++] = dst_offset & 0xffffffff;
  67                 cs->buf[cs->cdw++] = src_offset & 0xffffffff;
  68                 cs->buf[cs->cdw++] = (dst_offset >> 32UL) & 0xff;
  69                 cs->buf[cs->cdw++] = (src_offset >> 32UL) & 0xff;
  70                 dst_offset += csize << shift;
  71                 src_offset += csize << shift;
  72                 size -= csize;
  73         }
  74
  75         util_range_add(&rdst->valid_buffer_range, dst_offset,
  76                        dst_offset + size);
  77 }
  78
  79 /* The max number of bytes to copy per packet. */
  80 #define CP_DMA_MAX_BYTE_COUNT ((1 << 21) - 8)
  81
  82 void evergreen_cp_dma_clear_buffer(struct r600_context *rctx,
  83                                    struct pipe_resource *dst, uint64_t offset,
  84                                    unsigned size, uint32_t clear_value)
  85 {
  86         struct radeon_winsys_cs *cs = rctx->b.rings.gfx.cs;
  87
  88         assert(size);
  89         assert(rctx->screen->has_cp_dma);
  90
  91         offset += r600_resource_va(&rctx->screen->b.b, dst);
  92
  93         /* Flush the cache where the resource is bound. */
  94         rctx->b.flags |= R600_CONTEXT_INV_CONST_CACHE |
  95                          R600_CONTEXT_INV_VERTEX_CACHE |
  96                          R600_CONTEXT_INV_TEX_CACHE |
  97                          R600_CONTEXT_FLUSH_AND_INV |
  98                          R600_CONTEXT_FLUSH_AND_INV_CB |
  99                          R600_CONTEXT_FLUSH_AND_INV_DB |
 100                          R600_CONTEXT_FLUSH_AND_INV_CB_META |
 101                          R600_CONTEXT_FLUSH_AND_INV_DB_META |
 102                          R600_CONTEXT_STREAMOUT_FLUSH |
 103                          R600_CONTEXT_WAIT_3D_IDLE;
 104
 105         while (size) {
 106                 unsigned sync = 0;
 107                 unsigned byte_count = MIN2(size, CP_DMA_MAX_BYTE_COUNT);
 108                 unsigned reloc;
 109
 110                 r600_need_cs_space(rctx, 10 + (rctx->b.flags ? R600_MAX_FLUSH_CS_DWORDS : 0), FALSE);
 111
 112                 /* Flush the caches for the first copy only. */
 113                 if (rctx->b.flags) {
 114                         r600_flush_emit(rctx);
 115                 }
 116
 117                 /* Do the synchronization after the last copy, so that all data is written to memory. */
 118                 if (size == byte_count) {
 119                         sync = PKT3_CP_DMA_CP_SYNC;
 120                 }
 121
 122                 /* This must be done after r600_need_cs_space. */
 123                 reloc = r600_context_bo_reloc(&rctx->b, &rctx->b.rings.gfx,
 124                                               (struct r600_resource*)dst, RADEON_USAGE_WRITE);
 125
 126                 radeon_emit(cs, PKT3(PKT3_CP_DMA, 4, 0));
 127                 radeon_emit(cs, clear_value);   /* DATA [31:0] */
 128                 radeon_emit(cs, sync | PKT3_CP_DMA_SRC_SEL(2)); /* CP_SYNC [31] | SRC_SEL[30:29] */
 129                 radeon_emit(cs, offset);        /* DST_ADDR_LO [31:0] */
 130                 radeon_emit(cs, (offset >> 32) & 0xff);         /* DST_ADDR_HI [7:0] */
 131                 radeon_emit(cs, byte_count);    /* COMMAND [29:22] | BYTE_COUNT [20:0] */
 132
 133                 radeon_emit(cs, PKT3(PKT3_NOP, 0, 0));
 134                 radeon_emit(cs, reloc);
 135
 136                 size -= byte_count;
 137                 offset += byte_count;
 138         }
 139
 140         /* Invalidate the read caches. */
 141         rctx->b.flags |= R600_CONTEXT_INV_CONST_CACHE |
 142                          R600_CONTEXT_INV_VERTEX_CACHE |
 143                          R600_CONTEXT_INV_TEX_CACHE;
 144
 145         util_range_add(&r600_resource(dst)->valid_buffer_range, offset,
 146                        offset + size);
 147 }
 148