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r600g: consolidate the main draw code
[mesa.git] / src / gallium / drivers / r600 / evergreen_hw_context.c
1 /*
2 * Copyright 2010 Jerome Glisse <glisse@freedesktop.org>
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * on the rights to use, copy, modify, merge, publish, distribute, sub
8 * license, and/or sell copies of the Software, and to permit persons to whom
9 * the Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
13 * Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHOR(S) AND/OR THEIR SUPPLIERS BE LIABLE FOR ANY CLAIM,
19 * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
20 * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
21 * USE OR OTHER DEALINGS IN THE SOFTWARE.
22 *
23 * Authors:
24 * Jerome Glisse
25 */
26 #include "r600.h"
27 #include "r600_hw_context_priv.h"
28 #include "r600_pipe.h"
29 #include "evergreend.h"
30 #include "util/u_memory.h"
31 #include <errno.h>
32
33 #define GROUP_FORCE_NEW_BLOCK 0
34
35 static const struct r600_reg evergreen_config_reg_list[] = {
36 {R_008958_VGT_PRIMITIVE_TYPE, 0},
37 };
38
39
40 static const struct r600_reg cayman_config_reg_list[] = {
41 {R_008958_VGT_PRIMITIVE_TYPE, 0, 0},
42 {R_009100_SPI_CONFIG_CNTL, REG_FLAG_ENABLE_ALWAYS | REG_FLAG_FLUSH_CHANGE, 0},
43 {R_00913C_SPI_CONFIG_CNTL_1, REG_FLAG_ENABLE_ALWAYS | REG_FLAG_FLUSH_CHANGE, 0},
44 };
45
46 static const struct r600_reg evergreen_ctl_const_list[] = {
47 {R_03CFF4_SQ_VTX_START_INST_LOC, 0, 0},
48 };
49
50 static const struct r600_reg evergreen_context_reg_list[] = {
51 {R_028000_DB_RENDER_CONTROL, 0, 0},
52 {R_028004_DB_COUNT_CONTROL, 0, 0},
53 {R_028008_DB_DEPTH_VIEW, 0, 0},
54 {R_02800C_DB_RENDER_OVERRIDE, 0, 0},
55 {R_028010_DB_RENDER_OVERRIDE2, 0, 0},
56 {GROUP_FORCE_NEW_BLOCK, 0, 0},
57 {R_028014_DB_HTILE_DATA_BASE, REG_FLAG_NEED_BO, 0},
58 {GROUP_FORCE_NEW_BLOCK, 0, 0},
59 {R_028028_DB_STENCIL_CLEAR, 0, 0},
60 {R_02802C_DB_DEPTH_CLEAR, 0, 0},
61 {R_028030_PA_SC_SCREEN_SCISSOR_TL, 0, 0},
62 {R_028034_PA_SC_SCREEN_SCISSOR_BR, 0, 0},
63 {GROUP_FORCE_NEW_BLOCK, 0, 0},
64 {R_028040_DB_Z_INFO, REG_FLAG_NEED_BO, 0},
65 {GROUP_FORCE_NEW_BLOCK, 0, 0},
66 {R_028044_DB_STENCIL_INFO, 0, 0},
67 {GROUP_FORCE_NEW_BLOCK, 0, 0},
68 {R_028048_DB_Z_READ_BASE, REG_FLAG_NEED_BO, 0},
69 {GROUP_FORCE_NEW_BLOCK, 0, 0},
70 {R_02804C_DB_STENCIL_READ_BASE, REG_FLAG_NEED_BO, 0},
71 {GROUP_FORCE_NEW_BLOCK, 0, 0},
72 {R_028050_DB_Z_WRITE_BASE, REG_FLAG_NEED_BO, 0},
73 {GROUP_FORCE_NEW_BLOCK, 0, 0},
74 {R_028054_DB_STENCIL_WRITE_BASE, REG_FLAG_NEED_BO, 0},
75 {GROUP_FORCE_NEW_BLOCK, 0, 0},
76 {R_028058_DB_DEPTH_SIZE, 0, 0},
77 {R_02805C_DB_DEPTH_SLICE, 0, 0},
78 {R_028140_ALU_CONST_BUFFER_SIZE_PS_0, REG_FLAG_DIRTY_ALWAYS, 0},
79 {R_028144_ALU_CONST_BUFFER_SIZE_PS_1, REG_FLAG_DIRTY_ALWAYS, 0},
80 {R_028180_ALU_CONST_BUFFER_SIZE_VS_0, REG_FLAG_DIRTY_ALWAYS, 0},
81 {R_028184_ALU_CONST_BUFFER_SIZE_VS_1, REG_FLAG_DIRTY_ALWAYS, 0},
82 {R_028200_PA_SC_WINDOW_OFFSET, 0, 0},
83 {R_028204_PA_SC_WINDOW_SCISSOR_TL, 0, 0},
84 {R_028208_PA_SC_WINDOW_SCISSOR_BR, 0, 0},
85 {R_02820C_PA_SC_CLIPRECT_RULE, 0, 0},
86 {R_028210_PA_SC_CLIPRECT_0_TL, 0, 0},
87 {R_028214_PA_SC_CLIPRECT_0_BR, 0, 0},
88 {R_028218_PA_SC_CLIPRECT_1_TL, 0, 0},
89 {R_02821C_PA_SC_CLIPRECT_1_BR, 0, 0},
90 {R_028220_PA_SC_CLIPRECT_2_TL, 0, 0},
91 {R_028224_PA_SC_CLIPRECT_2_BR, 0, 0},
92 {R_028228_PA_SC_CLIPRECT_3_TL, 0, 0},
93 {R_02822C_PA_SC_CLIPRECT_3_BR, 0, 0},
94 {R_028230_PA_SC_EDGERULE, 0, 0},
95 {R_028234_PA_SU_HARDWARE_SCREEN_OFFSET, 0, 0},
96 {R_028238_CB_TARGET_MASK, 0, 0},
97 {R_02823C_CB_SHADER_MASK, 0, 0},
98 {R_028240_PA_SC_GENERIC_SCISSOR_TL, 0, 0},
99 {R_028244_PA_SC_GENERIC_SCISSOR_BR, 0, 0},
100 {R_028250_PA_SC_VPORT_SCISSOR_0_TL, 0, 0},
101 {R_028254_PA_SC_VPORT_SCISSOR_0_BR, 0, 0},
102 {R_0282D0_PA_SC_VPORT_ZMIN_0, 0, 0},
103 {R_0282D4_PA_SC_VPORT_ZMAX_0, 0, 0},
104 {R_028350_SX_MISC, 0, 0},
105 {GROUP_FORCE_NEW_BLOCK, 0, 0},
106 {R_028408_VGT_INDX_OFFSET, 0, 0},
107 {R_02840C_VGT_MULTI_PRIM_IB_RESET_INDX, 0, 0},
108 {R_028A94_VGT_MULTI_PRIM_IB_RESET_EN, 0, 0},
109 {GROUP_FORCE_NEW_BLOCK, 0, 0},
110 {R_028410_SX_ALPHA_TEST_CONTROL, 0, 0},
111 {R_028414_CB_BLEND_RED, 0, 0},
112 {R_028418_CB_BLEND_GREEN, 0, 0},
113 {R_02841C_CB_BLEND_BLUE, 0, 0},
114 {R_028420_CB_BLEND_ALPHA, 0, 0},
115 {R_028430_DB_STENCILREFMASK, 0, 0},
116 {R_028434_DB_STENCILREFMASK_BF, 0, 0},
117 {R_028438_SX_ALPHA_REF, 0, 0},
118 {R_02843C_PA_CL_VPORT_XSCALE_0, 0, 0},
119 {R_028440_PA_CL_VPORT_XOFFSET_0, 0, 0},
120 {R_028444_PA_CL_VPORT_YSCALE_0, 0, 0},
121 {R_028448_PA_CL_VPORT_YOFFSET_0, 0, 0},
122 {R_02844C_PA_CL_VPORT_ZSCALE_0, 0, 0},
123 {R_028450_PA_CL_VPORT_ZOFFSET_0, 0, 0},
124 {R_0285BC_PA_CL_UCP0_X, 0, 0},
125 {R_0285C0_PA_CL_UCP0_Y, 0, 0},
126 {R_0285C4_PA_CL_UCP0_Z, 0, 0},
127 {R_0285C8_PA_CL_UCP0_W, 0, 0},
128 {R_0285CC_PA_CL_UCP1_X, 0, 0},
129 {R_0285D0_PA_CL_UCP1_Y, 0, 0},
130 {R_0285D4_PA_CL_UCP1_Z, 0, 0},
131 {R_0285D8_PA_CL_UCP1_W, 0, 0},
132 {R_0285DC_PA_CL_UCP2_X, 0, 0},
133 {R_0285E0_PA_CL_UCP2_Y, 0, 0},
134 {R_0285E4_PA_CL_UCP2_Z, 0, 0},
135 {R_0285E8_PA_CL_UCP2_W, 0, 0},
136 {R_0285EC_PA_CL_UCP3_X, 0, 0},
137 {R_0285F0_PA_CL_UCP3_Y, 0, 0},
138 {R_0285F4_PA_CL_UCP3_Z, 0, 0},
139 {R_0285F8_PA_CL_UCP3_W, 0, 0},
140 {R_0285FC_PA_CL_UCP4_X, 0, 0},
141 {R_028600_PA_CL_UCP4_Y, 0, 0},
142 {R_028604_PA_CL_UCP4_Z, 0, 0},
143 {R_028608_PA_CL_UCP4_W, 0, 0},
144 {R_02860C_PA_CL_UCP5_X, 0, 0},
145 {R_028610_PA_CL_UCP5_Y, 0, 0},
146 {R_028614_PA_CL_UCP5_Z, 0, 0},
147 {R_028618_PA_CL_UCP5_W, 0, 0},
148 {GROUP_FORCE_NEW_BLOCK, 0, 0},
149 {R_02861C_SPI_VS_OUT_ID_0, 0, 0},
150 {R_028620_SPI_VS_OUT_ID_1, 0, 0},
151 {R_028624_SPI_VS_OUT_ID_2, 0, 0},
152 {R_028628_SPI_VS_OUT_ID_3, 0, 0},
153 {R_02862C_SPI_VS_OUT_ID_4, 0, 0},
154 {R_028630_SPI_VS_OUT_ID_5, 0, 0},
155 {R_028634_SPI_VS_OUT_ID_6, 0, 0},
156 {R_028638_SPI_VS_OUT_ID_7, 0, 0},
157 {R_02863C_SPI_VS_OUT_ID_8, 0, 0},
158 {R_028640_SPI_VS_OUT_ID_9, 0, 0},
159 {GROUP_FORCE_NEW_BLOCK, 0, 0},
160 {R_028644_SPI_PS_INPUT_CNTL_0, 0, 0},
161 {R_028648_SPI_PS_INPUT_CNTL_1, 0, 0},
162 {R_02864C_SPI_PS_INPUT_CNTL_2, 0, 0},
163 {R_028650_SPI_PS_INPUT_CNTL_3, 0, 0},
164 {R_028654_SPI_PS_INPUT_CNTL_4, 0, 0},
165 {R_028658_SPI_PS_INPUT_CNTL_5, 0, 0},
166 {R_02865C_SPI_PS_INPUT_CNTL_6, 0, 0},
167 {R_028660_SPI_PS_INPUT_CNTL_7, 0, 0},
168 {R_028664_SPI_PS_INPUT_CNTL_8, 0, 0},
169 {R_028668_SPI_PS_INPUT_CNTL_9, 0, 0},
170 {R_02866C_SPI_PS_INPUT_CNTL_10, 0, 0},
171 {R_028670_SPI_PS_INPUT_CNTL_11, 0, 0},
172 {R_028674_SPI_PS_INPUT_CNTL_12, 0, 0},
173 {R_028678_SPI_PS_INPUT_CNTL_13, 0, 0},
174 {R_02867C_SPI_PS_INPUT_CNTL_14, 0, 0},
175 {R_028680_SPI_PS_INPUT_CNTL_15, 0, 0},
176 {R_028684_SPI_PS_INPUT_CNTL_16, 0, 0},
177 {R_028688_SPI_PS_INPUT_CNTL_17, 0, 0},
178 {R_02868C_SPI_PS_INPUT_CNTL_18, 0, 0},
179 {R_028690_SPI_PS_INPUT_CNTL_19, 0, 0},
180 {R_028694_SPI_PS_INPUT_CNTL_20, 0, 0},
181 {R_028698_SPI_PS_INPUT_CNTL_21, 0, 0},
182 {R_02869C_SPI_PS_INPUT_CNTL_22, 0, 0},
183 {R_0286A0_SPI_PS_INPUT_CNTL_23, 0, 0},
184 {R_0286A4_SPI_PS_INPUT_CNTL_24, 0, 0},
185 {R_0286A8_SPI_PS_INPUT_CNTL_25, 0, 0},
186 {R_0286AC_SPI_PS_INPUT_CNTL_26, 0, 0},
187 {R_0286B0_SPI_PS_INPUT_CNTL_27, 0, 0},
188 {R_0286B4_SPI_PS_INPUT_CNTL_28, 0, 0},
189 {R_0286B8_SPI_PS_INPUT_CNTL_29, 0, 0},
190 {R_0286BC_SPI_PS_INPUT_CNTL_30, 0, 0},
191 {R_0286C0_SPI_PS_INPUT_CNTL_31, 0, 0},
192 {GROUP_FORCE_NEW_BLOCK, 0, 0},
193 {R_0286C4_SPI_VS_OUT_CONFIG, 0, 0},
194 {R_0286C8_SPI_THREAD_GROUPING, 0, 0},
195 {R_0286CC_SPI_PS_IN_CONTROL_0, 0, 0},
196 {R_0286D0_SPI_PS_IN_CONTROL_1, 0, 0},
197 {R_0286D4_SPI_INTERP_CONTROL_0, 0, 0},
198 {R_0286D8_SPI_INPUT_Z, 0, 0},
199 {R_0286DC_SPI_FOG_CNTL, 0, 0},
200 {R_0286E0_SPI_BARYC_CNTL, 0, 0},
201 {R_0286E4_SPI_PS_IN_CONTROL_2, 0, 0},
202 {R_0286E8_SPI_COMPUTE_INPUT_CNTL, 0, 0},
203 {R_028780_CB_BLEND0_CONTROL, 0, 0},
204 {R_028784_CB_BLEND1_CONTROL, 0, 0},
205 {R_028788_CB_BLEND2_CONTROL, 0, 0},
206 {R_02878C_CB_BLEND3_CONTROL, 0, 0},
207 {R_028790_CB_BLEND4_CONTROL, 0, 0},
208 {R_028794_CB_BLEND5_CONTROL, 0, 0},
209 {R_028798_CB_BLEND6_CONTROL, 0, 0},
210 {R_02879C_CB_BLEND7_CONTROL, 0, 0},
211 {R_028800_DB_DEPTH_CONTROL, 0, 0},
212 {R_02880C_DB_SHADER_CONTROL, 0, 0},
213 {R_028808_CB_COLOR_CONTROL, 0, 0},
214 {R_028810_PA_CL_CLIP_CNTL, 0, 0},
215 {R_028814_PA_SU_SC_MODE_CNTL, 0, 0},
216 {R_028818_PA_CL_VTE_CNTL, 0, 0},
217 {R_02881C_PA_CL_VS_OUT_CNTL, 0, 0},
218 {R_028820_PA_CL_NANINF_CNTL, 0, 0},
219 {R_028840_SQ_PGM_START_PS, REG_FLAG_NEED_BO, 0},
220 {R_028844_SQ_PGM_RESOURCES_PS, 0, 0},
221 {R_028848_SQ_PGM_RESOURCES_2_PS, 0, 0},
222 {R_02884C_SQ_PGM_EXPORTS_PS, 0, 0},
223 {R_02885C_SQ_PGM_START_VS, REG_FLAG_NEED_BO, 0},
224 {R_028860_SQ_PGM_RESOURCES_VS, 0, 0},
225 {R_028864_SQ_PGM_RESOURCES_2_VS, 0, 0},
226 {R_0288A4_SQ_PGM_START_FS, REG_FLAG_NEED_BO, 0},
227 {R_0288A8_SQ_PGM_RESOURCES_FS, 0, 0},
228 {R_0288EC_SQ_LDS_ALLOC_PS, 0, 0},
229 {R_028940_ALU_CONST_CACHE_PS_0, REG_FLAG_NEED_BO, 0},
230 {R_028944_ALU_CONST_CACHE_PS_1, REG_FLAG_NEED_BO, 0},
231 {R_028980_ALU_CONST_CACHE_VS_0, REG_FLAG_NEED_BO, 0},
232 {R_028984_ALU_CONST_CACHE_VS_1, REG_FLAG_NEED_BO, 0},
233 {R_028A00_PA_SU_POINT_SIZE, 0, 0},
234 {R_028A04_PA_SU_POINT_MINMAX, 0, 0},
235 {R_028A08_PA_SU_LINE_CNTL, 0, 0},
236 {R_028A0C_PA_SC_LINE_STIPPLE, 0, 0},
237 {R_028A48_PA_SC_MODE_CNTL_0, 0, 0},
238 {R_028ABC_DB_HTILE_SURFACE, 0, 0},
239 {R_028AC0_DB_SRESULTS_COMPARE_STATE0, 0, 0},
240 {R_028AC4_DB_SRESULTS_COMPARE_STATE1, 0, 0},
241 {R_028AC8_DB_PRELOAD_CONTROL, 0, 0},
242 {R_028B54_VGT_SHADER_STAGES_EN, 0, 0},
243 {R_028B70_DB_ALPHA_TO_MASK, 0, 0},
244 {R_028B78_PA_SU_POLY_OFFSET_DB_FMT_CNTL, 0, 0},
245 {R_028B7C_PA_SU_POLY_OFFSET_CLAMP, 0, 0},
246 {R_028B80_PA_SU_POLY_OFFSET_FRONT_SCALE, 0, 0},
247 {R_028B84_PA_SU_POLY_OFFSET_FRONT_OFFSET, 0, 0},
248 {R_028B88_PA_SU_POLY_OFFSET_BACK_SCALE, 0, 0},
249 {R_028B8C_PA_SU_POLY_OFFSET_BACK_OFFSET, 0, 0},
250 {R_028C00_PA_SC_LINE_CNTL, 0, 0},
251 {R_028C04_PA_SC_AA_CONFIG, 0, 0},
252 {R_028C08_PA_SU_VTX_CNTL, 0, 0},
253 {R_028C0C_PA_CL_GB_VERT_CLIP_ADJ, 0, 0},
254 {R_028C10_PA_CL_GB_VERT_DISC_ADJ, 0, 0},
255 {R_028C14_PA_CL_GB_HORZ_CLIP_ADJ, 0, 0},
256 {R_028C18_PA_CL_GB_HORZ_DISC_ADJ, 0, 0},
257 {R_028C1C_PA_SC_AA_SAMPLE_LOCS_0, 0, 0},
258 {R_028C3C_PA_SC_AA_MASK, 0, 0},
259 {GROUP_FORCE_NEW_BLOCK, 0, 0},
260 {R_028C60_CB_COLOR0_BASE, REG_FLAG_NEED_BO, 0},
261 {R_028C64_CB_COLOR0_PITCH, 0, 0},
262 {R_028C68_CB_COLOR0_SLICE, 0, 0},
263 {R_028C6C_CB_COLOR0_VIEW, 0, 0},
264 {R_028C70_CB_COLOR0_INFO, REG_FLAG_NEED_BO, 0},
265 {R_028C74_CB_COLOR0_ATTRIB, REG_FLAG_NEED_BO, 0},
266 {R_028C78_CB_COLOR0_DIM, 0, 0},
267 {GROUP_FORCE_NEW_BLOCK, 0, 0},
268 {R_028C9C_CB_COLOR1_BASE, REG_FLAG_NEED_BO, 0},
269 {R_028CA0_CB_COLOR1_PITCH, 0, 0},
270 {R_028CA4_CB_COLOR1_SLICE, 0, 0},
271 {R_028CA8_CB_COLOR1_VIEW, 0, 0},
272 {R_028CAC_CB_COLOR1_INFO, REG_FLAG_NEED_BO, 0},
273 {R_028CB0_CB_COLOR1_ATTRIB, REG_FLAG_NEED_BO, 0},
274 {R_028CB4_CB_COLOR1_DIM, 0, 0},
275 {GROUP_FORCE_NEW_BLOCK, 0, 0},
276 {R_028CD8_CB_COLOR2_BASE, REG_FLAG_NEED_BO, 0},
277 {R_028CDC_CB_COLOR2_PITCH, 0, 0},
278 {R_028CE0_CB_COLOR2_SLICE, 0, 0},
279 {R_028CE4_CB_COLOR2_VIEW, 0, 0},
280 {R_028CE8_CB_COLOR2_INFO, REG_FLAG_NEED_BO, 0},
281 {R_028CEC_CB_COLOR2_ATTRIB, REG_FLAG_NEED_BO, 0},
282 {R_028CF0_CB_COLOR2_DIM, 0, 0},
283 {GROUP_FORCE_NEW_BLOCK, 0, 0},
284 {R_028D14_CB_COLOR3_BASE, REG_FLAG_NEED_BO, 0},
285 {R_028D18_CB_COLOR3_PITCH, 0, 0},
286 {R_028D1C_CB_COLOR3_SLICE, 0, 0},
287 {R_028D20_CB_COLOR3_VIEW, 0, 0},
288 {R_028D24_CB_COLOR3_INFO, REG_FLAG_NEED_BO, 0},
289 {R_028D28_CB_COLOR3_ATTRIB, REG_FLAG_NEED_BO, 0},
290 {R_028D2C_CB_COLOR3_DIM, 0, 0},
291 {GROUP_FORCE_NEW_BLOCK, 0, 0},
292 {R_028D50_CB_COLOR4_BASE, REG_FLAG_NEED_BO, 0},
293 {R_028D54_CB_COLOR4_PITCH, 0, 0},
294 {R_028D58_CB_COLOR4_SLICE, 0, 0},
295 {R_028D5C_CB_COLOR4_VIEW, 0, 0},
296 {R_028D60_CB_COLOR4_INFO, REG_FLAG_NEED_BO, 0},
297 {R_028D64_CB_COLOR4_ATTRIB, REG_FLAG_NEED_BO, 0},
298 {R_028D68_CB_COLOR4_DIM, 0, 0},
299 {GROUP_FORCE_NEW_BLOCK, 0, 0},
300 {R_028D8C_CB_COLOR5_BASE, REG_FLAG_NEED_BO, 0},
301 {R_028D90_CB_COLOR5_PITCH, 0, 0},
302 {R_028D94_CB_COLOR5_SLICE, 0, 0},
303 {R_028D98_CB_COLOR5_VIEW, 0, 0},
304 {R_028D9C_CB_COLOR5_INFO, REG_FLAG_NEED_BO, 0},
305 {R_028DA0_CB_COLOR5_ATTRIB, REG_FLAG_NEED_BO, 0},
306 {R_028DA4_CB_COLOR5_DIM, 0, 0},
307 {GROUP_FORCE_NEW_BLOCK, 0, 0},
308 {R_028DC8_CB_COLOR6_BASE, REG_FLAG_NEED_BO, 0},
309 {R_028DCC_CB_COLOR6_PITCH, 0, 0},
310 {R_028DD0_CB_COLOR6_SLICE, 0, 0},
311 {R_028DD4_CB_COLOR6_VIEW, 0, 0},
312 {R_028DD8_CB_COLOR6_INFO, REG_FLAG_NEED_BO, 0},
313 {R_028DDC_CB_COLOR6_ATTRIB, REG_FLAG_NEED_BO, 0},
314 {R_028DE0_CB_COLOR6_DIM, 0, 0},
315 {GROUP_FORCE_NEW_BLOCK, 0, 0},
316 {R_028E04_CB_COLOR7_BASE, REG_FLAG_NEED_BO, 0},
317 {R_028E08_CB_COLOR7_PITCH, 0, 0},
318 {R_028E0C_CB_COLOR7_SLICE, 0, 0},
319 {R_028E10_CB_COLOR7_VIEW, 0, 0},
320 {R_028E14_CB_COLOR7_INFO, REG_FLAG_NEED_BO, 0},
321 {R_028E18_CB_COLOR7_ATTRIB, REG_FLAG_NEED_BO, 0},
322 {R_028E1C_CB_COLOR7_DIM, 0, 0},
323 {GROUP_FORCE_NEW_BLOCK, 0, 0},
324 {R_028E40_CB_COLOR8_BASE, REG_FLAG_NEED_BO, 0},
325 {R_028E44_CB_COLOR8_PITCH, 0, 0},
326 {R_028E48_CB_COLOR8_SLICE, 0, 0},
327 {R_028E4C_CB_COLOR8_VIEW, 0, 0},
328 {R_028E50_CB_COLOR8_INFO, REG_FLAG_NEED_BO, 0},
329 {R_028E54_CB_COLOR8_ATTRIB, REG_FLAG_NEED_BO, 0},
330 {R_028E58_CB_COLOR8_DIM, 0, 0},
331 {GROUP_FORCE_NEW_BLOCK, 0, 0},
332 {R_028E5C_CB_COLOR9_BASE, REG_FLAG_NEED_BO, 0},
333 {R_028E60_CB_COLOR9_PITCH, 0, 0},
334 {R_028E64_CB_COLOR9_SLICE, 0, 0},
335 {R_028E68_CB_COLOR9_VIEW, 0, 0},
336 {R_028E6C_CB_COLOR9_INFO, REG_FLAG_NEED_BO, 0},
337 {R_028E70_CB_COLOR9_ATTRIB, REG_FLAG_NEED_BO, 0},
338 {R_028E74_CB_COLOR9_DIM, 0, 0},
339 {GROUP_FORCE_NEW_BLOCK, 0, 0},
340 {R_028E78_CB_COLOR10_BASE, REG_FLAG_NEED_BO, 0},
341 {R_028E7C_CB_COLOR10_PITCH, 0, 0},
342 {R_028E80_CB_COLOR10_SLICE, 0, 0},
343 {R_028E84_CB_COLOR10_VIEW, 0, 0},
344 {R_028E88_CB_COLOR10_INFO, REG_FLAG_NEED_BO, 0},
345 {R_028E8C_CB_COLOR10_ATTRIB, REG_FLAG_NEED_BO, 0},
346 {R_028E90_CB_COLOR10_DIM, 0, 0},
347 {GROUP_FORCE_NEW_BLOCK, 0, 0},
348 {R_028E94_CB_COLOR11_BASE, REG_FLAG_NEED_BO, 0},
349 {R_028E98_CB_COLOR11_PITCH, 0, 0},
350 {R_028E9C_CB_COLOR11_SLICE, 0, 0},
351 {R_028EA0_CB_COLOR11_VIEW, 0, 0},
352 {R_028EA4_CB_COLOR11_INFO, REG_FLAG_NEED_BO, 0},
353 {R_028EA8_CB_COLOR11_ATTRIB, REG_FLAG_NEED_BO, 0},
354 {R_028EAC_CB_COLOR11_DIM, 0, 0},
355 };
356
357 static const struct r600_reg cayman_context_reg_list[] = {
358 {R_028000_DB_RENDER_CONTROL, 0, 0},
359 {R_028004_DB_COUNT_CONTROL, 0, 0},
360 {R_028008_DB_DEPTH_VIEW, 0, 0},
361 {R_02800C_DB_RENDER_OVERRIDE, 0, 0},
362 {R_028010_DB_RENDER_OVERRIDE2, 0, 0},
363 {GROUP_FORCE_NEW_BLOCK, 0, 0},
364 {R_028014_DB_HTILE_DATA_BASE, REG_FLAG_NEED_BO, 0},
365 {GROUP_FORCE_NEW_BLOCK, 0, 0},
366 {R_028028_DB_STENCIL_CLEAR, 0, 0},
367 {R_02802C_DB_DEPTH_CLEAR, 0, 0},
368 {R_028030_PA_SC_SCREEN_SCISSOR_TL, 0, 0},
369 {R_028034_PA_SC_SCREEN_SCISSOR_BR, 0, 0},
370 {GROUP_FORCE_NEW_BLOCK, 0, 0},
371 {R_028040_DB_Z_INFO, REG_FLAG_NEED_BO, 0},
372 {GROUP_FORCE_NEW_BLOCK, 0, 0},
373 {R_028044_DB_STENCIL_INFO, 0, 0},
374 {GROUP_FORCE_NEW_BLOCK, 0, 0},
375 {R_028048_DB_Z_READ_BASE, REG_FLAG_NEED_BO, 0},
376 {GROUP_FORCE_NEW_BLOCK, 0, 0},
377 {R_02804C_DB_STENCIL_READ_BASE, REG_FLAG_NEED_BO, 0},
378 {GROUP_FORCE_NEW_BLOCK, 0, 0},
379 {R_028050_DB_Z_WRITE_BASE, REG_FLAG_NEED_BO, 0},
380 {GROUP_FORCE_NEW_BLOCK, 0, 0},
381 {R_028054_DB_STENCIL_WRITE_BASE, REG_FLAG_NEED_BO, 0},
382 {GROUP_FORCE_NEW_BLOCK, 0, 0},
383 {R_028058_DB_DEPTH_SIZE, 0, 0},
384 {R_02805C_DB_DEPTH_SLICE, 0, 0},
385 {R_028140_ALU_CONST_BUFFER_SIZE_PS_0, REG_FLAG_DIRTY_ALWAYS, 0},
386 {R_028144_ALU_CONST_BUFFER_SIZE_PS_1, REG_FLAG_DIRTY_ALWAYS, 0},
387 {R_028180_ALU_CONST_BUFFER_SIZE_VS_0, REG_FLAG_DIRTY_ALWAYS, 0},
388 {R_028184_ALU_CONST_BUFFER_SIZE_VS_1, REG_FLAG_DIRTY_ALWAYS, 0},
389 {R_028200_PA_SC_WINDOW_OFFSET, 0, 0},
390 {R_028204_PA_SC_WINDOW_SCISSOR_TL, 0, 0},
391 {R_028208_PA_SC_WINDOW_SCISSOR_BR, 0, 0},
392 {R_02820C_PA_SC_CLIPRECT_RULE, 0, 0},
393 {R_028210_PA_SC_CLIPRECT_0_TL, 0, 0},
394 {R_028214_PA_SC_CLIPRECT_0_BR, 0, 0},
395 {R_028218_PA_SC_CLIPRECT_1_TL, 0, 0},
396 {R_02821C_PA_SC_CLIPRECT_1_BR, 0, 0},
397 {R_028220_PA_SC_CLIPRECT_2_TL, 0, 0},
398 {R_028224_PA_SC_CLIPRECT_2_BR, 0, 0},
399 {R_028228_PA_SC_CLIPRECT_3_TL, 0, 0},
400 {R_02822C_PA_SC_CLIPRECT_3_BR, 0, 0},
401 {R_028230_PA_SC_EDGERULE, 0, 0},
402 {R_028234_PA_SU_HARDWARE_SCREEN_OFFSET, 0, 0},
403 {R_028238_CB_TARGET_MASK, 0, 0},
404 {R_02823C_CB_SHADER_MASK, 0, 0},
405 {R_028240_PA_SC_GENERIC_SCISSOR_TL, 0, 0},
406 {R_028244_PA_SC_GENERIC_SCISSOR_BR, 0, 0},
407 {R_028250_PA_SC_VPORT_SCISSOR_0_TL, 0, 0},
408 {R_028254_PA_SC_VPORT_SCISSOR_0_BR, 0, 0},
409 {R_0282D0_PA_SC_VPORT_ZMIN_0, 0, 0},
410 {R_0282D4_PA_SC_VPORT_ZMAX_0, 0, 0},
411 {R_028350_SX_MISC, 0, 0},
412 {GROUP_FORCE_NEW_BLOCK, 0, 0},
413 {R_028408_VGT_INDX_OFFSET, 0, 0},
414 {R_02840C_VGT_MULTI_PRIM_IB_RESET_INDX, 0, 0},
415 {R_028A94_VGT_MULTI_PRIM_IB_RESET_EN, 0, 0},
416 {GROUP_FORCE_NEW_BLOCK, 0, 0},
417 {R_028410_SX_ALPHA_TEST_CONTROL, 0, 0},
418 {R_028414_CB_BLEND_RED, 0, 0},
419 {R_028418_CB_BLEND_GREEN, 0, 0},
420 {R_02841C_CB_BLEND_BLUE, 0, 0},
421 {R_028420_CB_BLEND_ALPHA, 0, 0},
422 {R_028430_DB_STENCILREFMASK, 0, 0},
423 {R_028434_DB_STENCILREFMASK_BF, 0, 0},
424 {R_028438_SX_ALPHA_REF, 0, 0},
425 {R_02843C_PA_CL_VPORT_XSCALE_0, 0, 0},
426 {R_028440_PA_CL_VPORT_XOFFSET_0, 0, 0},
427 {R_028444_PA_CL_VPORT_YSCALE_0, 0, 0},
428 {R_028448_PA_CL_VPORT_YOFFSET_0, 0, 0},
429 {R_02844C_PA_CL_VPORT_ZSCALE_0, 0, 0},
430 {R_028450_PA_CL_VPORT_ZOFFSET_0, 0, 0},
431 {R_0285BC_PA_CL_UCP0_X, 0, 0},
432 {R_0285C0_PA_CL_UCP0_Y, 0, 0},
433 {R_0285C4_PA_CL_UCP0_Z, 0, 0},
434 {R_0285C8_PA_CL_UCP0_W, 0, 0},
435 {R_0285CC_PA_CL_UCP1_X, 0, 0},
436 {R_0285D0_PA_CL_UCP1_Y, 0, 0},
437 {R_0285D4_PA_CL_UCP1_Z, 0, 0},
438 {R_0285D8_PA_CL_UCP1_W, 0, 0},
439 {R_0285DC_PA_CL_UCP2_X, 0, 0},
440 {R_0285E0_PA_CL_UCP2_Y, 0, 0},
441 {R_0285E4_PA_CL_UCP2_Z, 0, 0},
442 {R_0285E8_PA_CL_UCP2_W, 0, 0},
443 {R_0285EC_PA_CL_UCP3_X, 0, 0},
444 {R_0285F0_PA_CL_UCP3_Y, 0, 0},
445 {R_0285F4_PA_CL_UCP3_Z, 0, 0},
446 {R_0285F8_PA_CL_UCP3_W, 0, 0},
447 {R_0285FC_PA_CL_UCP4_X, 0, 0},
448 {R_028600_PA_CL_UCP4_Y, 0, 0},
449 {R_028604_PA_CL_UCP4_Z, 0, 0},
450 {R_028608_PA_CL_UCP4_W, 0, 0},
451 {R_02860C_PA_CL_UCP5_X, 0, 0},
452 {R_028610_PA_CL_UCP5_Y, 0, 0},
453 {R_028614_PA_CL_UCP5_Z, 0, 0},
454 {R_028618_PA_CL_UCP5_W, 0, 0},
455 {R_02861C_SPI_VS_OUT_ID_0, 0, 0},
456 {R_028620_SPI_VS_OUT_ID_1, 0, 0},
457 {R_028624_SPI_VS_OUT_ID_2, 0, 0},
458 {R_028628_SPI_VS_OUT_ID_3, 0, 0},
459 {R_02862C_SPI_VS_OUT_ID_4, 0, 0},
460 {R_028630_SPI_VS_OUT_ID_5, 0, 0},
461 {R_028634_SPI_VS_OUT_ID_6, 0, 0},
462 {R_028638_SPI_VS_OUT_ID_7, 0, 0},
463 {R_02863C_SPI_VS_OUT_ID_8, 0, 0},
464 {R_028640_SPI_VS_OUT_ID_9, 0, 0},
465 {R_028644_SPI_PS_INPUT_CNTL_0, 0, 0},
466 {R_028648_SPI_PS_INPUT_CNTL_1, 0, 0},
467 {R_02864C_SPI_PS_INPUT_CNTL_2, 0, 0},
468 {R_028650_SPI_PS_INPUT_CNTL_3, 0, 0},
469 {R_028654_SPI_PS_INPUT_CNTL_4, 0, 0},
470 {R_028658_SPI_PS_INPUT_CNTL_5, 0, 0},
471 {R_02865C_SPI_PS_INPUT_CNTL_6, 0, 0},
472 {R_028660_SPI_PS_INPUT_CNTL_7, 0, 0},
473 {R_028664_SPI_PS_INPUT_CNTL_8, 0, 0},
474 {R_028668_SPI_PS_INPUT_CNTL_9, 0, 0},
475 {R_02866C_SPI_PS_INPUT_CNTL_10, 0, 0},
476 {R_028670_SPI_PS_INPUT_CNTL_11, 0, 0},
477 {R_028674_SPI_PS_INPUT_CNTL_12, 0, 0},
478 {R_028678_SPI_PS_INPUT_CNTL_13, 0, 0},
479 {R_02867C_SPI_PS_INPUT_CNTL_14, 0, 0},
480 {R_028680_SPI_PS_INPUT_CNTL_15, 0, 0},
481 {R_028684_SPI_PS_INPUT_CNTL_16, 0, 0},
482 {R_028688_SPI_PS_INPUT_CNTL_17, 0, 0},
483 {R_02868C_SPI_PS_INPUT_CNTL_18, 0, 0},
484 {R_028690_SPI_PS_INPUT_CNTL_19, 0, 0},
485 {R_028694_SPI_PS_INPUT_CNTL_20, 0, 0},
486 {R_028698_SPI_PS_INPUT_CNTL_21, 0, 0},
487 {R_02869C_SPI_PS_INPUT_CNTL_22, 0, 0},
488 {R_0286A0_SPI_PS_INPUT_CNTL_23, 0, 0},
489 {R_0286A4_SPI_PS_INPUT_CNTL_24, 0, 0},
490 {R_0286A8_SPI_PS_INPUT_CNTL_25, 0, 0},
491 {R_0286AC_SPI_PS_INPUT_CNTL_26, 0, 0},
492 {R_0286B0_SPI_PS_INPUT_CNTL_27, 0, 0},
493 {R_0286B4_SPI_PS_INPUT_CNTL_28, 0, 0},
494 {R_0286B8_SPI_PS_INPUT_CNTL_29, 0, 0},
495 {R_0286BC_SPI_PS_INPUT_CNTL_30, 0, 0},
496 {R_0286C0_SPI_PS_INPUT_CNTL_31, 0, 0},
497 {R_0286C4_SPI_VS_OUT_CONFIG, 0, 0},
498 {R_0286C8_SPI_THREAD_GROUPING, 0, 0},
499 {R_0286CC_SPI_PS_IN_CONTROL_0, 0, 0},
500 {R_0286D0_SPI_PS_IN_CONTROL_1, 0, 0},
501 {R_0286D4_SPI_INTERP_CONTROL_0, 0, 0},
502 {R_0286D8_SPI_INPUT_Z, 0, 0},
503 {R_0286DC_SPI_FOG_CNTL, 0, 0},
504 {R_0286E0_SPI_BARYC_CNTL, 0, 0},
505 {R_0286E4_SPI_PS_IN_CONTROL_2, 0, 0},
506 {R_0286E8_SPI_COMPUTE_INPUT_CNTL, 0, 0},
507 {R_028780_CB_BLEND0_CONTROL, 0, 0},
508 {R_028784_CB_BLEND1_CONTROL, 0, 0},
509 {R_028788_CB_BLEND2_CONTROL, 0, 0},
510 {R_02878C_CB_BLEND3_CONTROL, 0, 0},
511 {R_028790_CB_BLEND4_CONTROL, 0, 0},
512 {R_028794_CB_BLEND5_CONTROL, 0, 0},
513 {R_028798_CB_BLEND6_CONTROL, 0, 0},
514 {R_02879C_CB_BLEND7_CONTROL, 0, 0},
515 {R_028800_DB_DEPTH_CONTROL, 0, 0},
516 {R_028808_CB_COLOR_CONTROL, 0, 0},
517 {R_02880C_DB_SHADER_CONTROL, 0, 0},
518 {R_028810_PA_CL_CLIP_CNTL, 0, 0},
519 {R_028814_PA_SU_SC_MODE_CNTL, 0, 0},
520 {R_028818_PA_CL_VTE_CNTL, 0, 0},
521 {R_02881C_PA_CL_VS_OUT_CNTL, 0, 0},
522 {R_028820_PA_CL_NANINF_CNTL, 0, 0},
523 {R_028838_SQ_DYN_GPR_RESOURCE_LIMIT_1, 0, 0},
524 {R_028840_SQ_PGM_START_PS, REG_FLAG_NEED_BO, 0},
525 {R_028844_SQ_PGM_RESOURCES_PS, 0, 0},
526 {R_028848_SQ_PGM_RESOURCES_2_PS, 0, 0},
527 {R_02884C_SQ_PGM_EXPORTS_PS, 0, 0},
528 {R_02885C_SQ_PGM_START_VS, REG_FLAG_NEED_BO, 0},
529 {R_028860_SQ_PGM_RESOURCES_VS, 0, 0},
530 {R_028864_SQ_PGM_RESOURCES_2_VS, 0, 0},
531 {R_0288A4_SQ_PGM_START_FS, REG_FLAG_NEED_BO, 0},
532 {R_0288A8_SQ_PGM_RESOURCES_FS, 0, 0},
533 {R_028900_SQ_ESGS_RING_ITEMSIZE, 0, 0},
534 {R_028904_SQ_GSVS_RING_ITEMSIZE, 0, 0},
535 {R_028908_SQ_ESTMP_RING_ITEMSIZE, 0, 0},
536 {R_02890C_SQ_GSTMP_RING_ITEMSIZE, 0, 0},
537 {R_028910_SQ_VSTMP_RING_ITEMSIZE, 0, 0},
538 {R_028914_SQ_PSTMP_RING_ITEMSIZE, 0, 0},
539 {R_02891C_SQ_GS_VERT_ITEMSIZE, 0, 0},
540 {R_028920_SQ_GS_VERT_ITEMSIZE_1, 0, 0},
541 {R_028924_SQ_GS_VERT_ITEMSIZE_2, 0, 0},
542 {R_028928_SQ_GS_VERT_ITEMSIZE_3, 0, 0},
543 {R_028940_ALU_CONST_CACHE_PS_0, REG_FLAG_NEED_BO, 0},
544 {R_028944_ALU_CONST_CACHE_PS_1, REG_FLAG_NEED_BO, 0},
545 {R_028980_ALU_CONST_CACHE_VS_0, REG_FLAG_NEED_BO, 0},
546 {R_028984_ALU_CONST_CACHE_VS_1, REG_FLAG_NEED_BO, 0},
547 {R_028A00_PA_SU_POINT_SIZE, 0, 0},
548 {R_028A04_PA_SU_POINT_MINMAX, 0, 0},
549 {R_028A08_PA_SU_LINE_CNTL, 0, 0},
550 {R_028A0C_PA_SC_LINE_STIPPLE, 0, 0},
551 {R_028A48_PA_SC_MODE_CNTL_0, 0, 0},
552 {R_028ABC_DB_HTILE_SURFACE, 0, 0},
553 {R_028AC0_DB_SRESULTS_COMPARE_STATE0, 0, 0},
554 {R_028AC4_DB_SRESULTS_COMPARE_STATE1, 0, 0},
555 {R_028AC8_DB_PRELOAD_CONTROL, 0, 0},
556 {R_028B54_VGT_SHADER_STAGES_EN, 0, 0},
557 {R_028B70_DB_ALPHA_TO_MASK, 0, 0},
558 {R_028B78_PA_SU_POLY_OFFSET_DB_FMT_CNTL, 0, 0},
559 {R_028B7C_PA_SU_POLY_OFFSET_CLAMP, 0, 0},
560 {R_028B80_PA_SU_POLY_OFFSET_FRONT_SCALE, 0, 0},
561 {R_028B84_PA_SU_POLY_OFFSET_FRONT_OFFSET, 0, 0},
562 {R_028B88_PA_SU_POLY_OFFSET_BACK_SCALE, 0, 0},
563 {R_028B8C_PA_SU_POLY_OFFSET_BACK_OFFSET, 0, 0},
564 {CM_R_028BDC_PA_SC_LINE_CNTL, 0, 0},
565 {CM_R_028BE0_PA_SC_AA_CONFIG, 0, 0},
566 {CM_R_028BE4_PA_SU_VTX_CNTL, 0, 0},
567 {CM_R_028BE8_PA_CL_GB_VERT_CLIP_ADJ, 0, 0},
568 {CM_R_028BEC_PA_CL_GB_VERT_DISC_ADJ, 0, 0},
569 {CM_R_028BF0_PA_CL_GB_HORZ_CLIP_ADJ, 0, 0},
570 {CM_R_028BF4_PA_CL_GB_HORZ_DISC_ADJ, 0, 0},
571 {CM_R_028BF8_PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_0, 0, 0},
572 {CM_R_028BFC_PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_1, 0, 0},
573 {CM_R_028C00_PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_2, 0, 0},
574 {CM_R_028C04_PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_3, 0, 0},
575 {CM_R_028C08_PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_0, 0, 0},
576 {CM_R_028C0C_PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_1, 0, 0},
577 {CM_R_028C10_PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_2, 0, 0},
578 {CM_R_028C14_PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_3, 0, 0},
579 {CM_R_028C18_PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_0, 0, 0},
580 {CM_R_028C1C_PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_1, 0, 0},
581 {CM_R_028C20_PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_2, 0, 0},
582 {CM_R_028C24_PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_3, 0, 0},
583 {CM_R_028C28_PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_0, 0, 0},
584 {CM_R_028C2C_PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_1, 0, 0},
585 {CM_R_028C30_PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_2, 0, 0},
586 {CM_R_028C34_PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_3, 0, 0},
587 {CM_R_028C38_PA_SC_AA_MASK_X0Y0_X1Y0, 0, 0},
588 {CM_R_028C3C_PA_SC_AA_MASK_X0Y1_X1Y1, 0, 0},
589 {GROUP_FORCE_NEW_BLOCK, 0, 0},
590 {R_028C60_CB_COLOR0_BASE, REG_FLAG_NEED_BO, 0},
591 {R_028C64_CB_COLOR0_PITCH, 0, 0},
592 {R_028C68_CB_COLOR0_SLICE, 0, 0},
593 {R_028C6C_CB_COLOR0_VIEW, 0, 0},
594 {R_028C70_CB_COLOR0_INFO, REG_FLAG_NEED_BO, 0},
595 {R_028C74_CB_COLOR0_ATTRIB, REG_FLAG_NEED_BO, 0},
596 {R_028C78_CB_COLOR0_DIM, 0, 0},
597 {GROUP_FORCE_NEW_BLOCK, 0, 0},
598 {R_028C9C_CB_COLOR1_BASE, REG_FLAG_NEED_BO, 0},
599 {R_028CA0_CB_COLOR1_PITCH, 0, 0},
600 {R_028CA4_CB_COLOR1_SLICE, 0, 0},
601 {R_028CA8_CB_COLOR1_VIEW, 0, 0},
602 {R_028CAC_CB_COLOR1_INFO, REG_FLAG_NEED_BO, 0},
603 {R_028CB0_CB_COLOR1_ATTRIB, REG_FLAG_NEED_BO, 0},
604 {R_028CB4_CB_COLOR1_DIM, 0, 0},
605 {GROUP_FORCE_NEW_BLOCK, 0, 0},
606 {R_028CD8_CB_COLOR2_BASE, REG_FLAG_NEED_BO, 0},
607 {R_028CDC_CB_COLOR2_PITCH, 0, 0},
608 {R_028CE0_CB_COLOR2_SLICE, 0, 0},
609 {R_028CE4_CB_COLOR2_VIEW, 0, 0},
610 {R_028CE8_CB_COLOR2_INFO, REG_FLAG_NEED_BO, 0},
611 {R_028CEC_CB_COLOR2_ATTRIB, REG_FLAG_NEED_BO, 0},
612 {R_028CF0_CB_COLOR2_DIM, 0, 0},
613 {GROUP_FORCE_NEW_BLOCK, 0, 0},
614 {R_028D14_CB_COLOR3_BASE, REG_FLAG_NEED_BO, 0},
615 {R_028D18_CB_COLOR3_PITCH, 0, 0},
616 {R_028D1C_CB_COLOR3_SLICE, 0, 0},
617 {R_028D20_CB_COLOR3_VIEW, 0, 0},
618 {R_028D24_CB_COLOR3_INFO, REG_FLAG_NEED_BO, 0},
619 {R_028D28_CB_COLOR3_ATTRIB, REG_FLAG_NEED_BO, 0},
620 {R_028D2C_CB_COLOR3_DIM, 0, 0},
621 {GROUP_FORCE_NEW_BLOCK, 0, 0},
622 {R_028D50_CB_COLOR4_BASE, REG_FLAG_NEED_BO, 0},
623 {R_028D54_CB_COLOR4_PITCH, 0, 0},
624 {R_028D58_CB_COLOR4_SLICE, 0, 0},
625 {R_028D5C_CB_COLOR4_VIEW, 0, 0},
626 {R_028D60_CB_COLOR4_INFO, REG_FLAG_NEED_BO, 0},
627 {R_028D64_CB_COLOR4_ATTRIB, REG_FLAG_NEED_BO, 0},
628 {R_028D68_CB_COLOR4_DIM, 0, 0},
629 {GROUP_FORCE_NEW_BLOCK, 0, 0},
630 {R_028D8C_CB_COLOR5_BASE, REG_FLAG_NEED_BO, 0},
631 {R_028D90_CB_COLOR5_PITCH, 0, 0},
632 {R_028D94_CB_COLOR5_SLICE, 0, 0},
633 {R_028D98_CB_COLOR5_VIEW, 0, 0},
634 {R_028D9C_CB_COLOR5_INFO, REG_FLAG_NEED_BO, 0},
635 {R_028DA0_CB_COLOR5_ATTRIB, REG_FLAG_NEED_BO, 0},
636 {R_028DA4_CB_COLOR5_DIM, 0, 0},
637 {GROUP_FORCE_NEW_BLOCK, 0, 0},
638 {R_028DC8_CB_COLOR6_BASE, REG_FLAG_NEED_BO, 0},
639 {R_028DCC_CB_COLOR6_PITCH, 0, 0},
640 {R_028DD0_CB_COLOR6_SLICE, 0, 0},
641 {R_028DD4_CB_COLOR6_VIEW, 0, 0},
642 {R_028DD8_CB_COLOR6_INFO, REG_FLAG_NEED_BO, 0},
643 {R_028DDC_CB_COLOR6_ATTRIB, REG_FLAG_NEED_BO, 0},
644 {R_028DE0_CB_COLOR6_DIM, 0, 0},
645 {GROUP_FORCE_NEW_BLOCK, 0, 0},
646 {R_028E04_CB_COLOR7_BASE, REG_FLAG_NEED_BO, 0},
647 {R_028E08_CB_COLOR7_PITCH, 0, 0},
648 {R_028E0C_CB_COLOR7_SLICE, 0, 0},
649 {R_028E10_CB_COLOR7_VIEW, 0, 0},
650 {R_028E14_CB_COLOR7_INFO, REG_FLAG_NEED_BO, 0},
651 {R_028E18_CB_COLOR7_ATTRIB, REG_FLAG_NEED_BO, 0},
652 {R_028E1C_CB_COLOR7_DIM, 0, 0},
653 {GROUP_FORCE_NEW_BLOCK, 0, 0},
654 {R_028E40_CB_COLOR8_BASE, REG_FLAG_NEED_BO, 0},
655 {R_028E44_CB_COLOR8_PITCH, 0, 0},
656 {R_028E48_CB_COLOR8_SLICE, 0, 0},
657 {R_028E4C_CB_COLOR8_VIEW, 0, 0},
658 {R_028E50_CB_COLOR8_INFO, REG_FLAG_NEED_BO, 0},
659 {R_028E54_CB_COLOR8_ATTRIB, REG_FLAG_NEED_BO, 0},
660 {R_028E58_CB_COLOR8_DIM, 0, 0},
661 {GROUP_FORCE_NEW_BLOCK, 0, 0},
662 {R_028E5C_CB_COLOR9_BASE, REG_FLAG_NEED_BO, 0},
663 {R_028E60_CB_COLOR9_PITCH, 0, 0},
664 {R_028E64_CB_COLOR9_SLICE, 0, 0},
665 {R_028E68_CB_COLOR9_VIEW, 0, 0},
666 {R_028E6C_CB_COLOR9_INFO, REG_FLAG_NEED_BO, 0},
667 {R_028E70_CB_COLOR9_ATTRIB, REG_FLAG_NEED_BO, 0},
668 {R_028E74_CB_COLOR9_DIM, 0, 0},
669 {GROUP_FORCE_NEW_BLOCK, 0, 0},
670 {R_028E78_CB_COLOR10_BASE, REG_FLAG_NEED_BO, 0},
671 {R_028E7C_CB_COLOR10_PITCH, 0, 0},
672 {R_028E80_CB_COLOR10_SLICE, 0, 0},
673 {R_028E84_CB_COLOR10_VIEW, 0, 0},
674 {R_028E88_CB_COLOR10_INFO, REG_FLAG_NEED_BO, 0},
675 {R_028E8C_CB_COLOR10_ATTRIB, REG_FLAG_NEED_BO, 0},
676 {R_028E90_CB_COLOR10_DIM, 0, 0},
677 {GROUP_FORCE_NEW_BLOCK, 0, 0},
678 {R_028E94_CB_COLOR11_BASE, REG_FLAG_NEED_BO, 0},
679 {R_028E98_CB_COLOR11_PITCH, 0, 0},
680 {R_028E9C_CB_COLOR11_SLICE, 0, 0},
681 {R_028EA0_CB_COLOR11_VIEW, 0, 0},
682 {R_028EA4_CB_COLOR11_INFO, REG_FLAG_NEED_BO, 0},
683 {R_028EA8_CB_COLOR11_ATTRIB, REG_FLAG_NEED_BO, 0},
684 {R_028EAC_CB_COLOR11_DIM, 0, 0},
685 };
686
687 /* SHADER RESOURCE R600/R700 */
688 static int r600_resource_range_init(struct r600_context *ctx, struct r600_range *range, unsigned offset, unsigned nblocks, unsigned stride)
689 {
690 struct r600_reg r600_shader_resource[] = {
691 {R_030000_RESOURCE0_WORD0, REG_FLAG_NEED_BO, 0},
692 {R_030004_RESOURCE0_WORD1, REG_FLAG_NEED_BO, 0},
693 {R_030008_RESOURCE0_WORD2, 0, 0},
694 {R_03000C_RESOURCE0_WORD3, 0, 0},
695 {R_030010_RESOURCE0_WORD4, 0, 0},
696 {R_030014_RESOURCE0_WORD5, 0, 0},
697 {R_030018_RESOURCE0_WORD6, 0, 0},
698 {R_03001C_RESOURCE0_WORD7, 0, 0},
699 };
700 unsigned nreg = Elements(r600_shader_resource);
701
702 return r600_resource_init(ctx, range, offset, nblocks, stride, r600_shader_resource, nreg, EVERGREEN_RESOURCE_OFFSET);
703 }
704
705 /* SHADER SAMPLER R600/R700 */
706 static int r600_state_sampler_init(struct r600_context *ctx, uint32_t offset)
707 {
708 struct r600_reg r600_shader_sampler[] = {
709 {R_03C000_SQ_TEX_SAMPLER_WORD0_0, 0, 0},
710 {R_03C004_SQ_TEX_SAMPLER_WORD1_0, 0, 0},
711 {R_03C008_SQ_TEX_SAMPLER_WORD2_0, 0, 0},
712 };
713 unsigned nreg = Elements(r600_shader_sampler);
714
715 for (int i = 0; i < nreg; i++) {
716 r600_shader_sampler[i].offset += offset;
717 }
718 return r600_context_add_block(ctx, r600_shader_sampler, nreg, PKT3_SET_SAMPLER, EVERGREEN_SAMPLER_OFFSET);
719 }
720
721 /* SHADER SAMPLER BORDER EG/CM */
722 static int evergreen_state_sampler_border_init(struct r600_context *ctx, uint32_t offset, unsigned id)
723 {
724 struct r600_reg r600_shader_sampler_border[] = {
725 {R_00A400_TD_PS_SAMPLER0_BORDER_INDEX, 0, 0},
726 {R_00A404_TD_PS_SAMPLER0_BORDER_RED, 0, 0},
727 {R_00A408_TD_PS_SAMPLER0_BORDER_GREEN, 0, 0},
728 {R_00A40C_TD_PS_SAMPLER0_BORDER_BLUE, 0, 0},
729 {R_00A410_TD_PS_SAMPLER0_BORDER_ALPHA, 0, 0},
730 };
731 unsigned nreg = Elements(r600_shader_sampler_border);
732 unsigned fake_offset = (offset - R_00A400_TD_PS_SAMPLER0_BORDER_INDEX) * 0x100 + 0x40000 + id * 0x1C;
733 struct r600_range *range;
734 struct r600_block *block;
735 int r;
736
737 for (int i = 0; i < nreg; i++) {
738 r600_shader_sampler_border[i].offset -= R_00A400_TD_PS_SAMPLER0_BORDER_INDEX;
739 r600_shader_sampler_border[i].offset += fake_offset;
740 }
741 r = r600_context_add_block(ctx, r600_shader_sampler_border, nreg, PKT3_SET_CONFIG_REG, 0);
742 if (r) {
743 return r;
744 }
745 /* set proper offset */
746 range = &ctx->range[CTX_RANGE_ID(r600_shader_sampler_border[0].offset)];
747 block = range->blocks[CTX_BLOCK_ID(r600_shader_sampler_border[0].offset)];
748 block->pm4[1] = (offset - EVERGREEN_CONFIG_REG_OFFSET) >> 2;
749 return 0;
750 }
751
752 static int evergreen_loop_const_init(struct r600_context *ctx, uint32_t offset)
753 {
754 unsigned nreg = 32;
755 struct r600_reg r600_loop_consts[32];
756 int i;
757
758 for (i = 0; i < nreg; i++) {
759 r600_loop_consts[i].offset = EVERGREEN_LOOP_CONST_OFFSET + ((offset + i) * 4);
760 r600_loop_consts[i].flags = REG_FLAG_DIRTY_ALWAYS;
761 r600_loop_consts[i].sbu_flags = 0;
762 }
763 return r600_context_add_block(ctx, r600_loop_consts, nreg, PKT3_SET_LOOP_CONST, EVERGREEN_LOOP_CONST_OFFSET);
764 }
765
766 int evergreen_context_init(struct r600_context *ctx)
767 {
768 int r;
769
770 LIST_INITHEAD(&ctx->active_query_list);
771
772 /* init dirty list */
773 LIST_INITHEAD(&ctx->dirty);
774 LIST_INITHEAD(&ctx->resource_dirty);
775 LIST_INITHEAD(&ctx->enable_list);
776
777 ctx->range = calloc(NUM_RANGES, sizeof(struct r600_range));
778 if (!ctx->range) {
779 r = -ENOMEM;
780 goto out_err;
781 }
782
783 /* add blocks */
784 if (ctx->family == CHIP_CAYMAN)
785 r = r600_context_add_block(ctx, cayman_config_reg_list,
786 Elements(cayman_config_reg_list), PKT3_SET_CONFIG_REG, EVERGREEN_CONFIG_REG_OFFSET);
787 else
788 r = r600_context_add_block(ctx, evergreen_config_reg_list,
789 Elements(evergreen_config_reg_list), PKT3_SET_CONFIG_REG, EVERGREEN_CONFIG_REG_OFFSET);
790 if (r)
791 goto out_err;
792 if (ctx->family == CHIP_CAYMAN)
793 r = r600_context_add_block(ctx, cayman_context_reg_list,
794 Elements(cayman_context_reg_list), PKT3_SET_CONTEXT_REG, EVERGREEN_CONTEXT_REG_OFFSET);
795 else
796 r = r600_context_add_block(ctx, evergreen_context_reg_list,
797 Elements(evergreen_context_reg_list), PKT3_SET_CONTEXT_REG, EVERGREEN_CONTEXT_REG_OFFSET);
798 if (r)
799 goto out_err;
800 r = r600_context_add_block(ctx, evergreen_ctl_const_list,
801 Elements(evergreen_ctl_const_list), PKT3_SET_CTL_CONST, EVERGREEN_CTL_CONST_OFFSET);
802 if (r)
803 goto out_err;
804
805
806 /* PS SAMPLER */
807 for (int j = 0, offset = 0; j < 18; j++, offset += 0xC) {
808 r = r600_state_sampler_init(ctx, offset);
809 if (r)
810 goto out_err;
811 }
812 /* VS SAMPLER */
813 for (int j = 0, offset = 0xD8; j < 18; j++, offset += 0xC) {
814 r = r600_state_sampler_init(ctx, offset);
815 if (r)
816 goto out_err;
817 }
818 /* PS SAMPLER BORDER */
819 for (int j = 0; j < 18; j++) {
820 r = evergreen_state_sampler_border_init(ctx, R_00A400_TD_PS_SAMPLER0_BORDER_INDEX, j);
821 if (r)
822 goto out_err;
823 }
824 /* VS SAMPLER BORDER */
825 for (int j = 0; j < 18; j++) {
826 r = evergreen_state_sampler_border_init(ctx, R_00A414_TD_VS_SAMPLER0_BORDER_INDEX, j);
827 if (r)
828 goto out_err;
829 }
830
831 ctx->num_ps_resources = 176;
832 ctx->num_vs_resources = 160;
833 ctx->num_fs_resources = 16;
834 r = r600_resource_range_init(ctx, &ctx->ps_resources, 0, 176, 0x20);
835 if (r)
836 goto out_err;
837 r = r600_resource_range_init(ctx, &ctx->vs_resources, 0x1600, 160, 0x20);
838 if (r)
839 goto out_err;
840 r = r600_resource_range_init(ctx, &ctx->fs_resources, 0x7C00, 16, 0x20);
841 if (r)
842 goto out_err;
843
844 /* PS loop const */
845 evergreen_loop_const_init(ctx, 0);
846 /* VS loop const */
847 evergreen_loop_const_init(ctx, 32);
848
849 r = r600_setup_block_table(ctx);
850 if (r)
851 goto out_err;
852
853 ctx->cs = ctx->ws->cs_create(ctx->ws);
854 r600_emit_atom(ctx, &ctx->atom_start_cs.atom);
855
856 ctx->max_db = 8;
857 return 0;
858 out_err:
859 r600_context_fini(ctx);
860 return r;
861 }
862
863 void evergreen_context_pipe_state_set_ps_resource(struct r600_context *ctx, struct r600_pipe_resource_state *state, unsigned rid)
864 {
865 struct r600_block *block = ctx->ps_resources.blocks[rid];
866
867 r600_context_pipe_state_set_resource(ctx, state, block);
868 }
869
870 void evergreen_context_pipe_state_set_vs_resource(struct r600_context *ctx, struct r600_pipe_resource_state *state, unsigned rid)
871 {
872 struct r600_block *block = ctx->vs_resources.blocks[rid];
873
874 r600_context_pipe_state_set_resource(ctx, state, block);
875 }
876
877 void evergreen_context_pipe_state_set_fs_resource(struct r600_context *ctx, struct r600_pipe_resource_state *state, unsigned rid)
878 {
879 struct r600_block *block = ctx->fs_resources.blocks[rid];
880
881 r600_context_pipe_state_set_resource(ctx, state, block);
882 }
883
884 static inline void evergreen_context_pipe_state_set_sampler(struct r600_context *ctx, struct r600_pipe_state *state, unsigned offset)
885 {
886 struct r600_range *range;
887 struct r600_block *block;
888 int i;
889 int dirty;
890
891 range = &ctx->range[CTX_RANGE_ID(offset)];
892 block = range->blocks[CTX_BLOCK_ID(offset)];
893 if (state == NULL) {
894 block->status &= ~(R600_BLOCK_STATUS_ENABLED | R600_BLOCK_STATUS_DIRTY);
895 LIST_DELINIT(&block->list);
896 LIST_DELINIT(&block->enable_list);
897 return;
898 }
899 dirty = block->status & R600_BLOCK_STATUS_DIRTY;
900
901 for (i = 0; i < 3; i++) {
902 if (block->reg[i] != state->regs[i].value) {
903 dirty |= R600_BLOCK_STATUS_DIRTY;
904 block->reg[i] = state->regs[i].value;
905 }
906 }
907 if (dirty)
908 r600_context_dirty_block(ctx, block, dirty, 2);
909 }
910
911 static inline void evergreen_context_ps_partial_flush(struct r600_context *ctx)
912 {
913 struct radeon_winsys_cs *cs = ctx->cs;
914
915 if (!(ctx->flags & R600_CONTEXT_DRAW_PENDING))
916 return;
917
918 cs->buf[cs->cdw++] = PKT3(PKT3_EVENT_WRITE, 0, 0);
919 cs->buf[cs->cdw++] = EVENT_TYPE(EVENT_TYPE_PS_PARTIAL_FLUSH) | EVENT_INDEX(4);
920
921 ctx->flags &= ~R600_CONTEXT_DRAW_PENDING;
922 }
923
924 static inline void evergreen_context_pipe_state_set_sampler_border(struct r600_context *ctx, struct r600_pipe_state *state, unsigned offset, unsigned id)
925 {
926 unsigned fake_offset = (offset - R_00A400_TD_PS_SAMPLER0_BORDER_INDEX) * 0x100 + 0x40000 + id * 0x1C;
927 struct r600_range *range;
928 struct r600_block *block;
929 int i;
930 int dirty;
931
932 range = &ctx->range[CTX_RANGE_ID(fake_offset)];
933 block = range->blocks[CTX_BLOCK_ID(fake_offset)];
934 if (state == NULL) {
935 block->status &= ~(R600_BLOCK_STATUS_ENABLED | R600_BLOCK_STATUS_DIRTY);
936 LIST_DELINIT(&block->list);
937 LIST_DELINIT(&block->enable_list);
938 return;
939 }
940 if (state->nregs <= 3) {
941 return;
942 }
943
944 dirty = block->status & R600_BLOCK_STATUS_DIRTY;
945 if (block->reg[0] != id) {
946 block->reg[0] = id;
947 dirty |= R600_BLOCK_STATUS_DIRTY;
948 }
949
950 for (i = 1; i < 5; i++) {
951 if (block->reg[i] != state->regs[i + 2].value) {
952 block->reg[i] = state->regs[i + 2].value;
953 dirty |= R600_BLOCK_STATUS_DIRTY;
954 }
955 }
956
957 /* We have to flush the shaders before we change the border color
958 * registers, or previous draw commands that haven't completed yet
959 * will end up using the new border color. */
960 if (dirty & R600_BLOCK_STATUS_DIRTY)
961 evergreen_context_ps_partial_flush(ctx);
962 if (dirty)
963 r600_context_dirty_block(ctx, block, dirty, 4);
964 }
965
966 void evergreen_context_pipe_state_set_ps_sampler(struct r600_context *ctx, struct r600_pipe_state *state, unsigned id)
967 {
968 unsigned offset;
969
970 offset = 0x0003C000 + id * 0xc;
971 evergreen_context_pipe_state_set_sampler(ctx, state, offset);
972 evergreen_context_pipe_state_set_sampler_border(ctx, state, R_00A400_TD_PS_SAMPLER0_BORDER_INDEX, id);
973 }
974
975 void evergreen_context_pipe_state_set_vs_sampler(struct r600_context *ctx, struct r600_pipe_state *state, unsigned id)
976 {
977 unsigned offset;
978
979 offset = 0x0003C0D8 + id * 0xc;
980 evergreen_context_pipe_state_set_sampler(ctx, state, offset);
981 evergreen_context_pipe_state_set_sampler_border(ctx, state, R_00A414_TD_VS_SAMPLER0_BORDER_INDEX, id);
982 }
983
984 /* XXX make a proper state object (atom or pipe_state) out of this */
985 void evergreen_context_draw_prepare(struct r600_context *ctx)
986 {
987 struct r600_pipe_dsa *dsa = (struct r600_pipe_dsa*)ctx->states[R600_PIPE_STATE_DSA];
988 struct radeon_winsys_cs *cs = ctx->cs;
989
990 /* queries need some special values
991 * (this is non-zero if any query is active) */
992 if (ctx->num_cs_dw_queries_suspend) {
993 cs->buf[cs->cdw++] = PKT3(PKT3_SET_CONTEXT_REG, 1, 0);
994 cs->buf[cs->cdw++] = (R_028004_DB_COUNT_CONTROL - EVERGREEN_CONTEXT_REG_OFFSET) >> 2;
995 cs->buf[cs->cdw++] = S_028004_PERFECT_ZPASS_COUNTS(1);
996 cs->buf[cs->cdw++] = PKT3(PKT3_SET_CONTEXT_REG, 1, 0);
997 cs->buf[cs->cdw++] = (R_02800C_DB_RENDER_OVERRIDE - EVERGREEN_CONTEXT_REG_OFFSET) >> 2;
998 cs->buf[cs->cdw++] = dsa->db_render_override | S_02800C_NOOP_CULL_DISABLE(1);
999 }
1000 }
1001
1002 void evergreen_flush_vgt_streamout(struct r600_context *ctx)
1003 {
1004 struct radeon_winsys_cs *cs = ctx->cs;
1005
1006 cs->buf[cs->cdw++] = PKT3(PKT3_SET_CONFIG_REG, 1, 0);
1007 cs->buf[cs->cdw++] = (R_0084FC_CP_STRMOUT_CNTL - EVERGREEN_CONFIG_REG_OFFSET) >> 2;
1008 cs->buf[cs->cdw++] = 0;
1009
1010 cs->buf[cs->cdw++] = PKT3(PKT3_EVENT_WRITE, 0, 0);
1011 cs->buf[cs->cdw++] = EVENT_TYPE(EVENT_TYPE_SO_VGTSTREAMOUT_FLUSH) | EVENT_INDEX(0);
1012
1013 cs->buf[cs->cdw++] = PKT3(PKT3_WAIT_REG_MEM, 5, 0);
1014 cs->buf[cs->cdw++] = WAIT_REG_MEM_EQUAL; /* wait until the register is equal to the reference value */
1015 cs->buf[cs->cdw++] = R_0084FC_CP_STRMOUT_CNTL >> 2; /* register */
1016 cs->buf[cs->cdw++] = 0;
1017 cs->buf[cs->cdw++] = S_0084FC_OFFSET_UPDATE_DONE(1); /* reference value */
1018 cs->buf[cs->cdw++] = S_0084FC_OFFSET_UPDATE_DONE(1); /* mask */
1019 cs->buf[cs->cdw++] = 4; /* poll interval */
1020 }
1021
1022 void evergreen_set_streamout_enable(struct r600_context *ctx, unsigned buffer_enable_bit)
1023 {
1024 struct radeon_winsys_cs *cs = ctx->cs;
1025
1026 if (buffer_enable_bit) {
1027 cs->buf[cs->cdw++] = PKT3(PKT3_SET_CONTEXT_REG, 1, 0);
1028 cs->buf[cs->cdw++] = (R_028B94_VGT_STRMOUT_CONFIG - EVERGREEN_CONTEXT_REG_OFFSET) >> 2;
1029 cs->buf[cs->cdw++] = S_028B94_STREAMOUT_0_EN(1);
1030
1031 cs->buf[cs->cdw++] = PKT3(PKT3_SET_CONTEXT_REG, 1, 0);
1032 cs->buf[cs->cdw++] = (R_028B98_VGT_STRMOUT_BUFFER_CONFIG - EVERGREEN_CONTEXT_REG_OFFSET) >> 2;
1033 cs->buf[cs->cdw++] = S_028B98_STREAM_0_BUFFER_EN(buffer_enable_bit);
1034 } else {
1035 cs->buf[cs->cdw++] = PKT3(PKT3_SET_CONTEXT_REG, 1, 0);
1036 cs->buf[cs->cdw++] = (R_028B94_VGT_STRMOUT_CONFIG - EVERGREEN_CONTEXT_REG_OFFSET) >> 2;
1037 cs->buf[cs->cdw++] = S_028B94_STREAMOUT_0_EN(0);
1038 }
1039 }