2 * Copyright 2010 Jerome Glisse <glisse@freedesktop.org>
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * on the rights to use, copy, modify, merge, publish, distribute, sub
8 * license, and/or sell copies of the Software, and to permit persons to whom
9 * the Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHOR(S) AND/OR THEIR SUPPLIERS BE LIABLE FOR ANY CLAIM,
19 * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
20 * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
21 * USE OR OTHER DEALINGS IN THE SOFTWARE.
26 #include "r600_hw_context_priv.h"
27 #include "evergreend.h"
28 #include "util/u_memory.h"
30 static const struct r600_reg evergreen_config_reg_list
[] = {
31 {R_008958_VGT_PRIMITIVE_TYPE
, 0},
35 static const struct r600_reg cayman_config_reg_list
[] = {
36 {R_008958_VGT_PRIMITIVE_TYPE
, 0, 0},
37 {R_009100_SPI_CONFIG_CNTL
, REG_FLAG_ENABLE_ALWAYS
| REG_FLAG_FLUSH_CHANGE
, 0},
38 {R_00913C_SPI_CONFIG_CNTL_1
, REG_FLAG_ENABLE_ALWAYS
| REG_FLAG_FLUSH_CHANGE
, 0},
41 static const struct r600_reg evergreen_ctl_const_list
[] = {
42 {R_03CFF4_SQ_VTX_START_INST_LOC
, 0, 0},
45 static const struct r600_reg evergreen_context_reg_list
[] = {
46 {R_028008_DB_DEPTH_VIEW
, 0, 0},
47 {R_028010_DB_RENDER_OVERRIDE2
, 0, 0},
48 {GROUP_FORCE_NEW_BLOCK
, 0, 0},
49 {R_028014_DB_HTILE_DATA_BASE
, REG_FLAG_NEED_BO
, 0},
50 {GROUP_FORCE_NEW_BLOCK
, 0, 0},
51 {R_028040_DB_Z_INFO
, REG_FLAG_NEED_BO
, 0},
52 {GROUP_FORCE_NEW_BLOCK
, 0, 0},
53 {R_028044_DB_STENCIL_INFO
, 0, 0},
54 {GROUP_FORCE_NEW_BLOCK
, 0, 0},
55 {R_028048_DB_Z_READ_BASE
, REG_FLAG_NEED_BO
, 0},
56 {GROUP_FORCE_NEW_BLOCK
, 0, 0},
57 {R_02804C_DB_STENCIL_READ_BASE
, REG_FLAG_NEED_BO
, 0},
58 {GROUP_FORCE_NEW_BLOCK
, 0, 0},
59 {R_028050_DB_Z_WRITE_BASE
, REG_FLAG_NEED_BO
, 0},
60 {GROUP_FORCE_NEW_BLOCK
, 0, 0},
61 {R_028054_DB_STENCIL_WRITE_BASE
, REG_FLAG_NEED_BO
, 0},
62 {GROUP_FORCE_NEW_BLOCK
, 0, 0},
63 {R_028058_DB_DEPTH_SIZE
, 0, 0},
64 {R_02805C_DB_DEPTH_SLICE
, 0, 0},
65 {R_028204_PA_SC_WINDOW_SCISSOR_TL
, 0, 0},
66 {R_028208_PA_SC_WINDOW_SCISSOR_BR
, 0, 0},
67 {R_028234_PA_SU_HARDWARE_SCREEN_OFFSET
, 0, 0},
68 {R_028250_PA_SC_VPORT_SCISSOR_0_TL
, 0, 0},
69 {R_028254_PA_SC_VPORT_SCISSOR_0_BR
, 0, 0},
70 {R_028350_SX_MISC
, 0, 0},
71 {GROUP_FORCE_NEW_BLOCK
, 0, 0},
72 {R_028408_VGT_INDX_OFFSET
, 0, 0},
73 {R_02840C_VGT_MULTI_PRIM_IB_RESET_INDX
, 0, 0},
74 {R_028A94_VGT_MULTI_PRIM_IB_RESET_EN
, 0, 0},
75 {GROUP_FORCE_NEW_BLOCK
, 0, 0},
76 {R_02861C_SPI_VS_OUT_ID_0
, 0, 0},
77 {R_028620_SPI_VS_OUT_ID_1
, 0, 0},
78 {R_028624_SPI_VS_OUT_ID_2
, 0, 0},
79 {R_028628_SPI_VS_OUT_ID_3
, 0, 0},
80 {R_02862C_SPI_VS_OUT_ID_4
, 0, 0},
81 {R_028630_SPI_VS_OUT_ID_5
, 0, 0},
82 {R_028634_SPI_VS_OUT_ID_6
, 0, 0},
83 {R_028638_SPI_VS_OUT_ID_7
, 0, 0},
84 {R_02863C_SPI_VS_OUT_ID_8
, 0, 0},
85 {R_028640_SPI_VS_OUT_ID_9
, 0, 0},
86 {GROUP_FORCE_NEW_BLOCK
, 0, 0},
87 {R_028644_SPI_PS_INPUT_CNTL_0
, 0, 0},
88 {R_028648_SPI_PS_INPUT_CNTL_1
, 0, 0},
89 {R_02864C_SPI_PS_INPUT_CNTL_2
, 0, 0},
90 {R_028650_SPI_PS_INPUT_CNTL_3
, 0, 0},
91 {R_028654_SPI_PS_INPUT_CNTL_4
, 0, 0},
92 {R_028658_SPI_PS_INPUT_CNTL_5
, 0, 0},
93 {R_02865C_SPI_PS_INPUT_CNTL_6
, 0, 0},
94 {R_028660_SPI_PS_INPUT_CNTL_7
, 0, 0},
95 {R_028664_SPI_PS_INPUT_CNTL_8
, 0, 0},
96 {R_028668_SPI_PS_INPUT_CNTL_9
, 0, 0},
97 {R_02866C_SPI_PS_INPUT_CNTL_10
, 0, 0},
98 {R_028670_SPI_PS_INPUT_CNTL_11
, 0, 0},
99 {R_028674_SPI_PS_INPUT_CNTL_12
, 0, 0},
100 {R_028678_SPI_PS_INPUT_CNTL_13
, 0, 0},
101 {R_02867C_SPI_PS_INPUT_CNTL_14
, 0, 0},
102 {R_028680_SPI_PS_INPUT_CNTL_15
, 0, 0},
103 {R_028684_SPI_PS_INPUT_CNTL_16
, 0, 0},
104 {R_028688_SPI_PS_INPUT_CNTL_17
, 0, 0},
105 {R_02868C_SPI_PS_INPUT_CNTL_18
, 0, 0},
106 {R_028690_SPI_PS_INPUT_CNTL_19
, 0, 0},
107 {R_028694_SPI_PS_INPUT_CNTL_20
, 0, 0},
108 {R_028698_SPI_PS_INPUT_CNTL_21
, 0, 0},
109 {R_02869C_SPI_PS_INPUT_CNTL_22
, 0, 0},
110 {R_0286A0_SPI_PS_INPUT_CNTL_23
, 0, 0},
111 {R_0286A4_SPI_PS_INPUT_CNTL_24
, 0, 0},
112 {R_0286A8_SPI_PS_INPUT_CNTL_25
, 0, 0},
113 {R_0286AC_SPI_PS_INPUT_CNTL_26
, 0, 0},
114 {R_0286B0_SPI_PS_INPUT_CNTL_27
, 0, 0},
115 {R_0286B4_SPI_PS_INPUT_CNTL_28
, 0, 0},
116 {R_0286B8_SPI_PS_INPUT_CNTL_29
, 0, 0},
117 {R_0286BC_SPI_PS_INPUT_CNTL_30
, 0, 0},
118 {R_0286C0_SPI_PS_INPUT_CNTL_31
, 0, 0},
119 {GROUP_FORCE_NEW_BLOCK
, 0, 0},
120 {R_0286C4_SPI_VS_OUT_CONFIG
, 0, 0},
121 {R_0286C8_SPI_THREAD_GROUPING
, 0, 0},
122 {R_0286CC_SPI_PS_IN_CONTROL_0
, 0, 0},
123 {R_0286D0_SPI_PS_IN_CONTROL_1
, 0, 0},
124 {R_0286D4_SPI_INTERP_CONTROL_0
, 0, 0},
125 {R_0286D8_SPI_INPUT_Z
, 0, 0},
126 {R_0286E0_SPI_BARYC_CNTL
, 0, 0},
127 {R_0286E4_SPI_PS_IN_CONTROL_2
, 0, 0},
128 {R_0286E8_SPI_COMPUTE_INPUT_CNTL
, 0, 0},
129 {R_028780_CB_BLEND0_CONTROL
, 0, 0},
130 {R_028784_CB_BLEND1_CONTROL
, 0, 0},
131 {R_028788_CB_BLEND2_CONTROL
, 0, 0},
132 {R_02878C_CB_BLEND3_CONTROL
, 0, 0},
133 {R_028790_CB_BLEND4_CONTROL
, 0, 0},
134 {R_028794_CB_BLEND5_CONTROL
, 0, 0},
135 {R_028798_CB_BLEND6_CONTROL
, 0, 0},
136 {R_02879C_CB_BLEND7_CONTROL
, 0, 0},
137 {R_028800_DB_DEPTH_CONTROL
, 0, 0},
138 {R_02880C_DB_SHADER_CONTROL
, 0, 0},
139 {R_028808_CB_COLOR_CONTROL
, 0, 0},
140 {R_028814_PA_SU_SC_MODE_CNTL
, 0, 0},
141 {R_028840_SQ_PGM_START_PS
, REG_FLAG_NEED_BO
, 0},
142 {R_028844_SQ_PGM_RESOURCES_PS
, 0, 0},
143 {R_02884C_SQ_PGM_EXPORTS_PS
, 0, 0},
144 {R_02885C_SQ_PGM_START_VS
, REG_FLAG_NEED_BO
, 0},
145 {R_028860_SQ_PGM_RESOURCES_VS
, 0, 0},
146 {R_0288A4_SQ_PGM_START_FS
, REG_FLAG_NEED_BO
, 0},
147 {R_0288EC_SQ_LDS_ALLOC_PS
, 0, 0},
148 {R_028A00_PA_SU_POINT_SIZE
, 0, 0},
149 {R_028A04_PA_SU_POINT_MINMAX
, 0, 0},
150 {R_028A08_PA_SU_LINE_CNTL
, 0, 0},
151 {R_028A0C_PA_SC_LINE_STIPPLE
, 0, 0},
152 {R_028A48_PA_SC_MODE_CNTL_0
, 0, 0},
153 {R_028A6C_VGT_GS_OUT_PRIM_TYPE
, 0, 0},
154 {R_028ABC_DB_HTILE_SURFACE
, 0, 0},
155 {R_028B54_VGT_SHADER_STAGES_EN
, 0, 0},
156 {R_028B70_DB_ALPHA_TO_MASK
, 0, 0},
157 {R_028B78_PA_SU_POLY_OFFSET_DB_FMT_CNTL
, 0, 0},
158 {R_028B7C_PA_SU_POLY_OFFSET_CLAMP
, 0, 0},
159 {R_028B80_PA_SU_POLY_OFFSET_FRONT_SCALE
, 0, 0},
160 {R_028B84_PA_SU_POLY_OFFSET_FRONT_OFFSET
, 0, 0},
161 {R_028B88_PA_SU_POLY_OFFSET_BACK_SCALE
, 0, 0},
162 {R_028B8C_PA_SU_POLY_OFFSET_BACK_OFFSET
, 0, 0},
163 {R_028C00_PA_SC_LINE_CNTL
, 0, 0},
164 {R_028C04_PA_SC_AA_CONFIG
, 0, 0},
165 {R_028C08_PA_SU_VTX_CNTL
, 0, 0},
166 {GROUP_FORCE_NEW_BLOCK
, 0, 0},
167 {R_028C1C_PA_SC_AA_SAMPLE_LOCS_0
, 0, 0},
168 {R_028C20_PA_SC_AA_SAMPLE_LOCS_1
, 0, 0},
169 {R_028C24_PA_SC_AA_SAMPLE_LOCS_2
, 0, 0},
170 {R_028C28_PA_SC_AA_SAMPLE_LOCS_3
, 0, 0},
171 {R_028C2C_PA_SC_AA_SAMPLE_LOCS_4
, 0, 0},
172 {R_028C30_PA_SC_AA_SAMPLE_LOCS_5
, 0, 0},
173 {R_028C34_PA_SC_AA_SAMPLE_LOCS_6
, 0, 0},
174 {R_028C38_PA_SC_AA_SAMPLE_LOCS_7
, 0, 0},
175 {GROUP_FORCE_NEW_BLOCK
, 0, 0},
176 {R_028C60_CB_COLOR0_BASE
, REG_FLAG_NEED_BO
, 0},
177 {R_028C64_CB_COLOR0_PITCH
, 0, 0},
178 {R_028C68_CB_COLOR0_SLICE
, 0, 0},
179 {R_028C6C_CB_COLOR0_VIEW
, 0, 0},
180 {R_028C70_CB_COLOR0_INFO
, REG_FLAG_NEED_BO
, 0},
181 {R_028C74_CB_COLOR0_ATTRIB
, REG_FLAG_NEED_BO
, 0},
182 {R_028C78_CB_COLOR0_DIM
, 0, 0},
183 {R_028C7C_CB_COLOR0_CMASK
, REG_FLAG_NEED_BO
},
184 {R_028C80_CB_COLOR0_CMASK_SLICE
},
185 {R_028C84_CB_COLOR0_FMASK
, REG_FLAG_NEED_BO
},
186 {R_028C88_CB_COLOR0_FMASK_SLICE
},
187 {R_028C8C_CB_COLOR0_CLEAR_WORD0
},
188 {R_028C90_CB_COLOR0_CLEAR_WORD1
},
189 {R_028C94_CB_COLOR0_CLEAR_WORD2
},
190 {R_028C98_CB_COLOR0_CLEAR_WORD3
},
191 {GROUP_FORCE_NEW_BLOCK
, 0, 0},
192 {R_028C9C_CB_COLOR1_BASE
, REG_FLAG_NEED_BO
, 0},
193 {R_028CA0_CB_COLOR1_PITCH
, 0, 0},
194 {R_028CA4_CB_COLOR1_SLICE
, 0, 0},
195 {R_028CA8_CB_COLOR1_VIEW
, 0, 0},
196 {R_028CAC_CB_COLOR1_INFO
, REG_FLAG_NEED_BO
, 0},
197 {R_028CB0_CB_COLOR1_ATTRIB
, REG_FLAG_NEED_BO
, 0},
198 {R_028CB4_CB_COLOR1_DIM
, 0, 0},
199 {R_028CB8_CB_COLOR1_CMASK
, REG_FLAG_NEED_BO
, 0},
200 {R_028CBC_CB_COLOR1_CMASK_SLICE
, 0, 0},
201 {R_028CC0_CB_COLOR1_FMASK
, REG_FLAG_NEED_BO
, 0},
202 {R_028CC4_CB_COLOR1_FMASK_SLICE
, 0, 0},
203 {R_028CC8_CB_COLOR1_CLEAR_WORD0
},
204 {R_028CCC_CB_COLOR1_CLEAR_WORD1
},
205 {R_028CD0_CB_COLOR1_CLEAR_WORD2
},
206 {R_028CD4_CB_COLOR1_CLEAR_WORD3
},
207 {GROUP_FORCE_NEW_BLOCK
, 0, 0},
208 {R_028CD8_CB_COLOR2_BASE
, REG_FLAG_NEED_BO
, 0},
209 {R_028CDC_CB_COLOR2_PITCH
, 0, 0},
210 {R_028CE0_CB_COLOR2_SLICE
, 0, 0},
211 {R_028CE4_CB_COLOR2_VIEW
, 0, 0},
212 {R_028CE8_CB_COLOR2_INFO
, REG_FLAG_NEED_BO
, 0},
213 {R_028CEC_CB_COLOR2_ATTRIB
, REG_FLAG_NEED_BO
, 0},
214 {R_028CF0_CB_COLOR2_DIM
, 0, 0},
215 {R_028CF4_CB_COLOR2_CMASK
, REG_FLAG_NEED_BO
, 0},
216 {R_028CF8_CB_COLOR2_CMASK_SLICE
, 0, 0},
217 {R_028CFC_CB_COLOR2_FMASK
, REG_FLAG_NEED_BO
, 0},
218 {R_028D00_CB_COLOR2_FMASK_SLICE
, 0, 0},
219 {R_028D04_CB_COLOR2_CLEAR_WORD0
},
220 {R_028D08_CB_COLOR2_CLEAR_WORD1
},
221 {R_028D0C_CB_COLOR2_CLEAR_WORD2
},
222 {R_028D10_CB_COLOR2_CLEAR_WORD3
},
223 {GROUP_FORCE_NEW_BLOCK
, 0, 0},
224 {R_028D14_CB_COLOR3_BASE
, REG_FLAG_NEED_BO
, 0},
225 {R_028D18_CB_COLOR3_PITCH
, 0, 0},
226 {R_028D1C_CB_COLOR3_SLICE
, 0, 0},
227 {R_028D20_CB_COLOR3_VIEW
, 0, 0},
228 {R_028D24_CB_COLOR3_INFO
, REG_FLAG_NEED_BO
, 0},
229 {R_028D28_CB_COLOR3_ATTRIB
, REG_FLAG_NEED_BO
, 0},
230 {R_028D2C_CB_COLOR3_DIM
, 0, 0},
231 {R_028D30_CB_COLOR3_CMASK
, REG_FLAG_NEED_BO
},
232 {R_028D34_CB_COLOR3_CMASK_SLICE
},
233 {R_028D38_CB_COLOR3_FMASK
, REG_FLAG_NEED_BO
},
234 {R_028D3C_CB_COLOR3_FMASK_SLICE
},
235 {R_028D40_CB_COLOR3_CLEAR_WORD0
},
236 {R_028D44_CB_COLOR3_CLEAR_WORD1
},
237 {R_028D48_CB_COLOR3_CLEAR_WORD2
},
238 {R_028D4C_CB_COLOR3_CLEAR_WORD3
},
239 {GROUP_FORCE_NEW_BLOCK
, 0, 0},
240 {R_028D50_CB_COLOR4_BASE
, REG_FLAG_NEED_BO
, 0},
241 {R_028D54_CB_COLOR4_PITCH
, 0, 0},
242 {R_028D58_CB_COLOR4_SLICE
, 0, 0},
243 {R_028D5C_CB_COLOR4_VIEW
, 0, 0},
244 {R_028D60_CB_COLOR4_INFO
, REG_FLAG_NEED_BO
, 0},
245 {R_028D64_CB_COLOR4_ATTRIB
, REG_FLAG_NEED_BO
, 0},
246 {R_028D68_CB_COLOR4_DIM
, 0, 0},
247 {R_028D6C_CB_COLOR4_CMASK
, REG_FLAG_NEED_BO
},
248 {R_028D70_CB_COLOR4_CMASK_SLICE
},
249 {R_028D74_CB_COLOR4_FMASK
, REG_FLAG_NEED_BO
},
250 {R_028D78_CB_COLOR4_FMASK_SLICE
},
251 {R_028D7C_CB_COLOR4_CLEAR_WORD0
},
252 {R_028D80_CB_COLOR4_CLEAR_WORD1
},
253 {R_028D84_CB_COLOR4_CLEAR_WORD2
},
254 {R_028D88_CB_COLOR4_CLEAR_WORD3
},
255 {GROUP_FORCE_NEW_BLOCK
, 0, 0},
256 {R_028D8C_CB_COLOR5_BASE
, REG_FLAG_NEED_BO
, 0},
257 {R_028D90_CB_COLOR5_PITCH
, 0, 0},
258 {R_028D94_CB_COLOR5_SLICE
, 0, 0},
259 {R_028D98_CB_COLOR5_VIEW
, 0, 0},
260 {R_028D9C_CB_COLOR5_INFO
, REG_FLAG_NEED_BO
, 0},
261 {R_028DA0_CB_COLOR5_ATTRIB
, REG_FLAG_NEED_BO
, 0},
262 {R_028DA4_CB_COLOR5_DIM
, 0, 0},
263 {R_028DA8_CB_COLOR5_CMASK
, REG_FLAG_NEED_BO
},
264 {R_028DAC_CB_COLOR5_CMASK_SLICE
},
265 {R_028DB0_CB_COLOR5_FMASK
, REG_FLAG_NEED_BO
},
266 {R_028DB4_CB_COLOR5_FMASK_SLICE
},
267 {R_028DB8_CB_COLOR5_CLEAR_WORD0
},
268 {R_028DBC_CB_COLOR5_CLEAR_WORD1
},
269 {R_028DC0_CB_COLOR5_CLEAR_WORD2
},
270 {R_028DC4_CB_COLOR5_CLEAR_WORD3
},
271 {GROUP_FORCE_NEW_BLOCK
, 0, 0},
272 {R_028DC8_CB_COLOR6_BASE
, REG_FLAG_NEED_BO
, 0},
273 {R_028DCC_CB_COLOR6_PITCH
, 0, 0},
274 {R_028DD0_CB_COLOR6_SLICE
, 0, 0},
275 {R_028DD4_CB_COLOR6_VIEW
, 0, 0},
276 {R_028DD8_CB_COLOR6_INFO
, REG_FLAG_NEED_BO
, 0},
277 {R_028DDC_CB_COLOR6_ATTRIB
, REG_FLAG_NEED_BO
, 0},
278 {R_028DE0_CB_COLOR6_DIM
, 0, 0},
279 {R_028DE4_CB_COLOR6_CMASK
, REG_FLAG_NEED_BO
},
280 {R_028DE8_CB_COLOR6_CMASK_SLICE
},
281 {R_028DEC_CB_COLOR6_FMASK
, REG_FLAG_NEED_BO
},
282 {R_028DF0_CB_COLOR6_FMASK_SLICE
},
283 {R_028DF4_CB_COLOR6_CLEAR_WORD0
},
284 {R_028DF8_CB_COLOR6_CLEAR_WORD1
},
285 {R_028DFC_CB_COLOR6_CLEAR_WORD2
},
286 {R_028E00_CB_COLOR6_CLEAR_WORD3
},
287 {GROUP_FORCE_NEW_BLOCK
, 0, 0},
288 {R_028E04_CB_COLOR7_BASE
, REG_FLAG_NEED_BO
, 0},
289 {R_028E08_CB_COLOR7_PITCH
, 0, 0},
290 {R_028E0C_CB_COLOR7_SLICE
, 0, 0},
291 {R_028E10_CB_COLOR7_VIEW
, 0, 0},
292 {R_028E14_CB_COLOR7_INFO
, REG_FLAG_NEED_BO
, 0},
293 {R_028E18_CB_COLOR7_ATTRIB
, REG_FLAG_NEED_BO
, 0},
294 {R_028E1C_CB_COLOR7_DIM
, 0, 0},
295 {R_028E20_CB_COLOR7_CMASK
, REG_FLAG_NEED_BO
},
296 {R_028E24_CB_COLOR7_CMASK_SLICE
},
297 {R_028E28_CB_COLOR7_FMASK
, REG_FLAG_NEED_BO
},
298 {R_028E2C_CB_COLOR7_FMASK_SLICE
},
299 {R_028E30_CB_COLOR7_CLEAR_WORD0
},
300 {R_028E34_CB_COLOR7_CLEAR_WORD1
},
301 {R_028E38_CB_COLOR7_CLEAR_WORD2
},
302 {R_028E3C_CB_COLOR7_CLEAR_WORD3
},
303 {GROUP_FORCE_NEW_BLOCK
, 0, 0},
304 {R_028E40_CB_COLOR8_BASE
, REG_FLAG_NEED_BO
, 0},
305 {R_028E44_CB_COLOR8_PITCH
, 0, 0},
306 {R_028E48_CB_COLOR8_SLICE
, 0, 0},
307 {R_028E4C_CB_COLOR8_VIEW
, 0, 0},
308 {R_028E50_CB_COLOR8_INFO
, REG_FLAG_NEED_BO
, 0},
309 {R_028E54_CB_COLOR8_ATTRIB
, REG_FLAG_NEED_BO
, 0},
310 {R_028E58_CB_COLOR8_DIM
, 0, 0},
311 {GROUP_FORCE_NEW_BLOCK
, 0, 0},
312 {R_028E5C_CB_COLOR9_BASE
, REG_FLAG_NEED_BO
, 0},
313 {R_028E60_CB_COLOR9_PITCH
, 0, 0},
314 {R_028E64_CB_COLOR9_SLICE
, 0, 0},
315 {R_028E68_CB_COLOR9_VIEW
, 0, 0},
316 {R_028E6C_CB_COLOR9_INFO
, REG_FLAG_NEED_BO
, 0},
317 {R_028E70_CB_COLOR9_ATTRIB
, REG_FLAG_NEED_BO
, 0},
318 {R_028E74_CB_COLOR9_DIM
, 0, 0},
319 {GROUP_FORCE_NEW_BLOCK
, 0, 0},
320 {R_028E78_CB_COLOR10_BASE
, REG_FLAG_NEED_BO
, 0},
321 {R_028E7C_CB_COLOR10_PITCH
, 0, 0},
322 {R_028E80_CB_COLOR10_SLICE
, 0, 0},
323 {R_028E84_CB_COLOR10_VIEW
, 0, 0},
324 {R_028E88_CB_COLOR10_INFO
, REG_FLAG_NEED_BO
, 0},
325 {R_028E8C_CB_COLOR10_ATTRIB
, REG_FLAG_NEED_BO
, 0},
326 {R_028E90_CB_COLOR10_DIM
, 0, 0},
327 {GROUP_FORCE_NEW_BLOCK
, 0, 0},
328 {R_028E94_CB_COLOR11_BASE
, REG_FLAG_NEED_BO
, 0},
329 {R_028E98_CB_COLOR11_PITCH
, 0, 0},
330 {R_028E9C_CB_COLOR11_SLICE
, 0, 0},
331 {R_028EA0_CB_COLOR11_VIEW
, 0, 0},
332 {R_028EA4_CB_COLOR11_INFO
, REG_FLAG_NEED_BO
, 0},
333 {R_028EA8_CB_COLOR11_ATTRIB
, REG_FLAG_NEED_BO
, 0},
334 {R_028EAC_CB_COLOR11_DIM
, 0, 0},
337 static const struct r600_reg cayman_context_reg_list
[] = {
338 {R_028008_DB_DEPTH_VIEW
, 0, 0},
339 {R_028010_DB_RENDER_OVERRIDE2
, 0, 0},
340 {GROUP_FORCE_NEW_BLOCK
, 0, 0},
341 {R_028014_DB_HTILE_DATA_BASE
, REG_FLAG_NEED_BO
, 0},
342 {GROUP_FORCE_NEW_BLOCK
, 0, 0},
343 {R_028040_DB_Z_INFO
, REG_FLAG_NEED_BO
, 0},
344 {GROUP_FORCE_NEW_BLOCK
, 0, 0},
345 {R_028044_DB_STENCIL_INFO
, 0, 0},
346 {GROUP_FORCE_NEW_BLOCK
, 0, 0},
347 {R_028048_DB_Z_READ_BASE
, REG_FLAG_NEED_BO
, 0},
348 {GROUP_FORCE_NEW_BLOCK
, 0, 0},
349 {R_02804C_DB_STENCIL_READ_BASE
, REG_FLAG_NEED_BO
, 0},
350 {GROUP_FORCE_NEW_BLOCK
, 0, 0},
351 {R_028050_DB_Z_WRITE_BASE
, REG_FLAG_NEED_BO
, 0},
352 {GROUP_FORCE_NEW_BLOCK
, 0, 0},
353 {R_028054_DB_STENCIL_WRITE_BASE
, REG_FLAG_NEED_BO
, 0},
354 {GROUP_FORCE_NEW_BLOCK
, 0, 0},
355 {R_028058_DB_DEPTH_SIZE
, 0, 0},
356 {R_02805C_DB_DEPTH_SLICE
, 0, 0},
357 {R_028204_PA_SC_WINDOW_SCISSOR_TL
, 0, 0},
358 {R_028208_PA_SC_WINDOW_SCISSOR_BR
, 0, 0},
359 {R_028234_PA_SU_HARDWARE_SCREEN_OFFSET
, 0, 0},
360 {R_028250_PA_SC_VPORT_SCISSOR_0_TL
, 0, 0},
361 {R_028254_PA_SC_VPORT_SCISSOR_0_BR
, 0, 0},
362 {R_028350_SX_MISC
, 0, 0},
363 {GROUP_FORCE_NEW_BLOCK
, 0, 0},
364 {R_028408_VGT_INDX_OFFSET
, 0, 0},
365 {R_02840C_VGT_MULTI_PRIM_IB_RESET_INDX
, 0, 0},
366 {R_028A94_VGT_MULTI_PRIM_IB_RESET_EN
, 0, 0},
367 {GROUP_FORCE_NEW_BLOCK
, 0, 0},
368 {R_02861C_SPI_VS_OUT_ID_0
, 0, 0},
369 {R_028620_SPI_VS_OUT_ID_1
, 0, 0},
370 {R_028624_SPI_VS_OUT_ID_2
, 0, 0},
371 {R_028628_SPI_VS_OUT_ID_3
, 0, 0},
372 {R_02862C_SPI_VS_OUT_ID_4
, 0, 0},
373 {R_028630_SPI_VS_OUT_ID_5
, 0, 0},
374 {R_028634_SPI_VS_OUT_ID_6
, 0, 0},
375 {R_028638_SPI_VS_OUT_ID_7
, 0, 0},
376 {R_02863C_SPI_VS_OUT_ID_8
, 0, 0},
377 {R_028640_SPI_VS_OUT_ID_9
, 0, 0},
378 {R_028644_SPI_PS_INPUT_CNTL_0
, 0, 0},
379 {R_028648_SPI_PS_INPUT_CNTL_1
, 0, 0},
380 {R_02864C_SPI_PS_INPUT_CNTL_2
, 0, 0},
381 {R_028650_SPI_PS_INPUT_CNTL_3
, 0, 0},
382 {R_028654_SPI_PS_INPUT_CNTL_4
, 0, 0},
383 {R_028658_SPI_PS_INPUT_CNTL_5
, 0, 0},
384 {R_02865C_SPI_PS_INPUT_CNTL_6
, 0, 0},
385 {R_028660_SPI_PS_INPUT_CNTL_7
, 0, 0},
386 {R_028664_SPI_PS_INPUT_CNTL_8
, 0, 0},
387 {R_028668_SPI_PS_INPUT_CNTL_9
, 0, 0},
388 {R_02866C_SPI_PS_INPUT_CNTL_10
, 0, 0},
389 {R_028670_SPI_PS_INPUT_CNTL_11
, 0, 0},
390 {R_028674_SPI_PS_INPUT_CNTL_12
, 0, 0},
391 {R_028678_SPI_PS_INPUT_CNTL_13
, 0, 0},
392 {R_02867C_SPI_PS_INPUT_CNTL_14
, 0, 0},
393 {R_028680_SPI_PS_INPUT_CNTL_15
, 0, 0},
394 {R_028684_SPI_PS_INPUT_CNTL_16
, 0, 0},
395 {R_028688_SPI_PS_INPUT_CNTL_17
, 0, 0},
396 {R_02868C_SPI_PS_INPUT_CNTL_18
, 0, 0},
397 {R_028690_SPI_PS_INPUT_CNTL_19
, 0, 0},
398 {R_028694_SPI_PS_INPUT_CNTL_20
, 0, 0},
399 {R_028698_SPI_PS_INPUT_CNTL_21
, 0, 0},
400 {R_02869C_SPI_PS_INPUT_CNTL_22
, 0, 0},
401 {R_0286A0_SPI_PS_INPUT_CNTL_23
, 0, 0},
402 {R_0286A4_SPI_PS_INPUT_CNTL_24
, 0, 0},
403 {R_0286A8_SPI_PS_INPUT_CNTL_25
, 0, 0},
404 {R_0286AC_SPI_PS_INPUT_CNTL_26
, 0, 0},
405 {R_0286B0_SPI_PS_INPUT_CNTL_27
, 0, 0},
406 {R_0286B4_SPI_PS_INPUT_CNTL_28
, 0, 0},
407 {R_0286B8_SPI_PS_INPUT_CNTL_29
, 0, 0},
408 {R_0286BC_SPI_PS_INPUT_CNTL_30
, 0, 0},
409 {R_0286C0_SPI_PS_INPUT_CNTL_31
, 0, 0},
410 {R_0286C4_SPI_VS_OUT_CONFIG
, 0, 0},
411 {R_0286C8_SPI_THREAD_GROUPING
, 0, 0},
412 {R_0286CC_SPI_PS_IN_CONTROL_0
, 0, 0},
413 {R_0286D0_SPI_PS_IN_CONTROL_1
, 0, 0},
414 {R_0286D4_SPI_INTERP_CONTROL_0
, 0, 0},
415 {R_0286D8_SPI_INPUT_Z
, 0, 0},
416 {R_0286E0_SPI_BARYC_CNTL
, 0, 0},
417 {R_0286E4_SPI_PS_IN_CONTROL_2
, 0, 0},
418 {R_0286E8_SPI_COMPUTE_INPUT_CNTL
, 0, 0},
419 {R_028780_CB_BLEND0_CONTROL
, 0, 0},
420 {R_028784_CB_BLEND1_CONTROL
, 0, 0},
421 {R_028788_CB_BLEND2_CONTROL
, 0, 0},
422 {R_02878C_CB_BLEND3_CONTROL
, 0, 0},
423 {R_028790_CB_BLEND4_CONTROL
, 0, 0},
424 {R_028794_CB_BLEND5_CONTROL
, 0, 0},
425 {R_028798_CB_BLEND6_CONTROL
, 0, 0},
426 {R_02879C_CB_BLEND7_CONTROL
, 0, 0},
427 {R_028800_DB_DEPTH_CONTROL
, 0, 0},
428 {CM_R_028804_DB_EQAA
},
429 {R_028808_CB_COLOR_CONTROL
, 0, 0},
430 {R_02880C_DB_SHADER_CONTROL
, 0, 0},
431 {R_028814_PA_SU_SC_MODE_CNTL
, 0, 0},
432 {R_028838_SQ_DYN_GPR_RESOURCE_LIMIT_1
, 0, 0},
433 {R_028840_SQ_PGM_START_PS
, REG_FLAG_NEED_BO
, 0},
434 {R_028844_SQ_PGM_RESOURCES_PS
, 0, 0},
435 {R_02884C_SQ_PGM_EXPORTS_PS
, 0, 0},
436 {R_02885C_SQ_PGM_START_VS
, REG_FLAG_NEED_BO
, 0},
437 {R_028860_SQ_PGM_RESOURCES_VS
, 0, 0},
438 {R_0288A4_SQ_PGM_START_FS
, REG_FLAG_NEED_BO
, 0},
439 {R_028900_SQ_ESGS_RING_ITEMSIZE
, 0, 0},
440 {R_028904_SQ_GSVS_RING_ITEMSIZE
, 0, 0},
441 {R_028908_SQ_ESTMP_RING_ITEMSIZE
, 0, 0},
442 {R_02890C_SQ_GSTMP_RING_ITEMSIZE
, 0, 0},
443 {R_028910_SQ_VSTMP_RING_ITEMSIZE
, 0, 0},
444 {R_028914_SQ_PSTMP_RING_ITEMSIZE
, 0, 0},
445 {R_02891C_SQ_GS_VERT_ITEMSIZE
, 0, 0},
446 {R_028920_SQ_GS_VERT_ITEMSIZE_1
, 0, 0},
447 {R_028924_SQ_GS_VERT_ITEMSIZE_2
, 0, 0},
448 {R_028928_SQ_GS_VERT_ITEMSIZE_3
, 0, 0},
449 {R_028A00_PA_SU_POINT_SIZE
, 0, 0},
450 {R_028A04_PA_SU_POINT_MINMAX
, 0, 0},
451 {R_028A08_PA_SU_LINE_CNTL
, 0, 0},
452 {R_028A0C_PA_SC_LINE_STIPPLE
, 0, 0},
453 {R_028A48_PA_SC_MODE_CNTL_0
, 0, 0},
454 {R_028A6C_VGT_GS_OUT_PRIM_TYPE
, 0, 0},
455 {R_028ABC_DB_HTILE_SURFACE
, 0, 0},
456 {R_028B54_VGT_SHADER_STAGES_EN
, 0, 0},
457 {R_028B70_DB_ALPHA_TO_MASK
, 0, 0},
458 {R_028B78_PA_SU_POLY_OFFSET_DB_FMT_CNTL
, 0, 0},
459 {R_028B7C_PA_SU_POLY_OFFSET_CLAMP
, 0, 0},
460 {R_028B80_PA_SU_POLY_OFFSET_FRONT_SCALE
, 0, 0},
461 {R_028B84_PA_SU_POLY_OFFSET_FRONT_OFFSET
, 0, 0},
462 {R_028B88_PA_SU_POLY_OFFSET_BACK_SCALE
, 0, 0},
463 {R_028B8C_PA_SU_POLY_OFFSET_BACK_OFFSET
, 0, 0},
464 {CM_R_028BDC_PA_SC_LINE_CNTL
, 0, 0},
465 {CM_R_028BE0_PA_SC_AA_CONFIG
, 0, 0},
466 {CM_R_028BE4_PA_SU_VTX_CNTL
, 0, 0},
467 {CM_R_028BF8_PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_0
, 0, 0},
468 {CM_R_028BFC_PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_1
, 0, 0},
469 {CM_R_028C00_PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_2
, 0, 0},
470 {CM_R_028C04_PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_3
, 0, 0},
471 {CM_R_028C08_PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_0
, 0, 0},
472 {CM_R_028C0C_PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_1
, 0, 0},
473 {CM_R_028C10_PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_2
, 0, 0},
474 {CM_R_028C14_PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_3
, 0, 0},
475 {CM_R_028C18_PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_0
, 0, 0},
476 {CM_R_028C1C_PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_1
, 0, 0},
477 {CM_R_028C20_PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_2
, 0, 0},
478 {CM_R_028C24_PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_3
, 0, 0},
479 {CM_R_028C28_PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_0
, 0, 0},
480 {CM_R_028C2C_PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_1
, 0, 0},
481 {CM_R_028C30_PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_2
, 0, 0},
482 {CM_R_028C34_PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_3
, 0, 0},
483 {GROUP_FORCE_NEW_BLOCK
, 0, 0},
484 {R_028C60_CB_COLOR0_BASE
, REG_FLAG_NEED_BO
, 0},
485 {R_028C64_CB_COLOR0_PITCH
, 0, 0},
486 {R_028C68_CB_COLOR0_SLICE
, 0, 0},
487 {R_028C6C_CB_COLOR0_VIEW
, 0, 0},
488 {R_028C70_CB_COLOR0_INFO
, REG_FLAG_NEED_BO
, 0},
489 {R_028C74_CB_COLOR0_ATTRIB
, REG_FLAG_NEED_BO
, 0},
490 {R_028C78_CB_COLOR0_DIM
, 0, 0},
491 {R_028C7C_CB_COLOR0_CMASK
, REG_FLAG_NEED_BO
},
492 {R_028C80_CB_COLOR0_CMASK_SLICE
},
493 {R_028C84_CB_COLOR0_FMASK
, REG_FLAG_NEED_BO
},
494 {R_028C88_CB_COLOR0_FMASK_SLICE
},
495 {R_028C8C_CB_COLOR0_CLEAR_WORD0
},
496 {R_028C90_CB_COLOR0_CLEAR_WORD1
},
497 {R_028C94_CB_COLOR0_CLEAR_WORD2
},
498 {R_028C98_CB_COLOR0_CLEAR_WORD3
},
499 {GROUP_FORCE_NEW_BLOCK
, 0, 0},
500 {R_028C9C_CB_COLOR1_BASE
, REG_FLAG_NEED_BO
, 0},
501 {R_028CA0_CB_COLOR1_PITCH
, 0, 0},
502 {R_028CA4_CB_COLOR1_SLICE
, 0, 0},
503 {R_028CA8_CB_COLOR1_VIEW
, 0, 0},
504 {R_028CAC_CB_COLOR1_INFO
, REG_FLAG_NEED_BO
, 0},
505 {R_028CB0_CB_COLOR1_ATTRIB
, REG_FLAG_NEED_BO
, 0},
506 {R_028CB4_CB_COLOR1_DIM
, 0, 0},
507 {R_028CB8_CB_COLOR1_CMASK
, REG_FLAG_NEED_BO
, 0},
508 {R_028CBC_CB_COLOR1_CMASK_SLICE
, 0, 0},
509 {R_028CC0_CB_COLOR1_FMASK
, REG_FLAG_NEED_BO
, 0},
510 {R_028CC4_CB_COLOR1_FMASK_SLICE
, 0, 0},
511 {R_028CC8_CB_COLOR1_CLEAR_WORD0
},
512 {R_028CCC_CB_COLOR1_CLEAR_WORD1
},
513 {R_028CD0_CB_COLOR1_CLEAR_WORD2
},
514 {R_028CD4_CB_COLOR1_CLEAR_WORD3
},
515 {GROUP_FORCE_NEW_BLOCK
, 0, 0},
516 {R_028CD8_CB_COLOR2_BASE
, REG_FLAG_NEED_BO
, 0},
517 {R_028CDC_CB_COLOR2_PITCH
, 0, 0},
518 {R_028CE0_CB_COLOR2_SLICE
, 0, 0},
519 {R_028CE4_CB_COLOR2_VIEW
, 0, 0},
520 {R_028CE8_CB_COLOR2_INFO
, REG_FLAG_NEED_BO
, 0},
521 {R_028CEC_CB_COLOR2_ATTRIB
, REG_FLAG_NEED_BO
, 0},
522 {R_028CF0_CB_COLOR2_DIM
, 0, 0},
523 {R_028CF4_CB_COLOR2_CMASK
, REG_FLAG_NEED_BO
, 0},
524 {R_028CF8_CB_COLOR2_CMASK_SLICE
, 0, 0},
525 {R_028CFC_CB_COLOR2_FMASK
, REG_FLAG_NEED_BO
, 0},
526 {R_028D00_CB_COLOR2_FMASK_SLICE
, 0, 0},
527 {R_028D04_CB_COLOR2_CLEAR_WORD0
},
528 {R_028D08_CB_COLOR2_CLEAR_WORD1
},
529 {R_028D0C_CB_COLOR2_CLEAR_WORD2
},
530 {R_028D10_CB_COLOR2_CLEAR_WORD3
},
531 {GROUP_FORCE_NEW_BLOCK
, 0, 0},
532 {R_028D14_CB_COLOR3_BASE
, REG_FLAG_NEED_BO
, 0},
533 {R_028D18_CB_COLOR3_PITCH
, 0, 0},
534 {R_028D1C_CB_COLOR3_SLICE
, 0, 0},
535 {R_028D20_CB_COLOR3_VIEW
, 0, 0},
536 {R_028D24_CB_COLOR3_INFO
, REG_FLAG_NEED_BO
, 0},
537 {R_028D28_CB_COLOR3_ATTRIB
, REG_FLAG_NEED_BO
, 0},
538 {R_028D2C_CB_COLOR3_DIM
, 0, 0},
539 {R_028D30_CB_COLOR3_CMASK
, REG_FLAG_NEED_BO
},
540 {R_028D34_CB_COLOR3_CMASK_SLICE
},
541 {R_028D38_CB_COLOR3_FMASK
, REG_FLAG_NEED_BO
},
542 {R_028D3C_CB_COLOR3_FMASK_SLICE
},
543 {R_028D40_CB_COLOR3_CLEAR_WORD0
},
544 {R_028D44_CB_COLOR3_CLEAR_WORD1
},
545 {R_028D48_CB_COLOR3_CLEAR_WORD2
},
546 {R_028D4C_CB_COLOR3_CLEAR_WORD3
},
547 {GROUP_FORCE_NEW_BLOCK
, 0, 0},
548 {R_028D50_CB_COLOR4_BASE
, REG_FLAG_NEED_BO
, 0},
549 {R_028D54_CB_COLOR4_PITCH
, 0, 0},
550 {R_028D58_CB_COLOR4_SLICE
, 0, 0},
551 {R_028D5C_CB_COLOR4_VIEW
, 0, 0},
552 {R_028D60_CB_COLOR4_INFO
, REG_FLAG_NEED_BO
, 0},
553 {R_028D64_CB_COLOR4_ATTRIB
, REG_FLAG_NEED_BO
, 0},
554 {R_028D68_CB_COLOR4_DIM
, 0, 0},
555 {R_028D6C_CB_COLOR4_CMASK
, REG_FLAG_NEED_BO
},
556 {R_028D70_CB_COLOR4_CMASK_SLICE
},
557 {R_028D74_CB_COLOR4_FMASK
, REG_FLAG_NEED_BO
},
558 {R_028D78_CB_COLOR4_FMASK_SLICE
},
559 {R_028D7C_CB_COLOR4_CLEAR_WORD0
},
560 {R_028D80_CB_COLOR4_CLEAR_WORD1
},
561 {R_028D84_CB_COLOR4_CLEAR_WORD2
},
562 {R_028D88_CB_COLOR4_CLEAR_WORD3
},
563 {GROUP_FORCE_NEW_BLOCK
, 0, 0},
564 {R_028D8C_CB_COLOR5_BASE
, REG_FLAG_NEED_BO
, 0},
565 {R_028D90_CB_COLOR5_PITCH
, 0, 0},
566 {R_028D94_CB_COLOR5_SLICE
, 0, 0},
567 {R_028D98_CB_COLOR5_VIEW
, 0, 0},
568 {R_028D9C_CB_COLOR5_INFO
, REG_FLAG_NEED_BO
, 0},
569 {R_028DA0_CB_COLOR5_ATTRIB
, REG_FLAG_NEED_BO
, 0},
570 {R_028DA4_CB_COLOR5_DIM
, 0, 0},
571 {R_028DA8_CB_COLOR5_CMASK
, REG_FLAG_NEED_BO
},
572 {R_028DAC_CB_COLOR5_CMASK_SLICE
},
573 {R_028DB0_CB_COLOR5_FMASK
, REG_FLAG_NEED_BO
},
574 {R_028DB4_CB_COLOR5_FMASK_SLICE
},
575 {R_028DB8_CB_COLOR5_CLEAR_WORD0
},
576 {R_028DBC_CB_COLOR5_CLEAR_WORD1
},
577 {R_028DC0_CB_COLOR5_CLEAR_WORD2
},
578 {R_028DC4_CB_COLOR5_CLEAR_WORD3
},
579 {GROUP_FORCE_NEW_BLOCK
, 0, 0},
580 {R_028DC8_CB_COLOR6_BASE
, REG_FLAG_NEED_BO
, 0},
581 {R_028DCC_CB_COLOR6_PITCH
, 0, 0},
582 {R_028DD0_CB_COLOR6_SLICE
, 0, 0},
583 {R_028DD4_CB_COLOR6_VIEW
, 0, 0},
584 {R_028DD8_CB_COLOR6_INFO
, REG_FLAG_NEED_BO
, 0},
585 {R_028DDC_CB_COLOR6_ATTRIB
, REG_FLAG_NEED_BO
, 0},
586 {R_028DE0_CB_COLOR6_DIM
, 0, 0},
587 {R_028DE4_CB_COLOR6_CMASK
, REG_FLAG_NEED_BO
},
588 {R_028DE8_CB_COLOR6_CMASK_SLICE
},
589 {R_028DEC_CB_COLOR6_FMASK
, REG_FLAG_NEED_BO
},
590 {R_028DF0_CB_COLOR6_FMASK_SLICE
},
591 {R_028DF4_CB_COLOR6_CLEAR_WORD0
},
592 {R_028DF8_CB_COLOR6_CLEAR_WORD1
},
593 {R_028DFC_CB_COLOR6_CLEAR_WORD2
},
594 {R_028E00_CB_COLOR6_CLEAR_WORD3
},
595 {GROUP_FORCE_NEW_BLOCK
, 0, 0},
596 {R_028E04_CB_COLOR7_BASE
, REG_FLAG_NEED_BO
, 0},
597 {R_028E08_CB_COLOR7_PITCH
, 0, 0},
598 {R_028E0C_CB_COLOR7_SLICE
, 0, 0},
599 {R_028E10_CB_COLOR7_VIEW
, 0, 0},
600 {R_028E14_CB_COLOR7_INFO
, REG_FLAG_NEED_BO
, 0},
601 {R_028E18_CB_COLOR7_ATTRIB
, REG_FLAG_NEED_BO
, 0},
602 {R_028E1C_CB_COLOR7_DIM
, 0, 0},
603 {R_028E20_CB_COLOR7_CMASK
, REG_FLAG_NEED_BO
},
604 {R_028E24_CB_COLOR7_CMASK_SLICE
},
605 {R_028E28_CB_COLOR7_FMASK
, REG_FLAG_NEED_BO
},
606 {R_028E2C_CB_COLOR7_FMASK_SLICE
},
607 {R_028E30_CB_COLOR7_CLEAR_WORD0
},
608 {R_028E34_CB_COLOR7_CLEAR_WORD1
},
609 {R_028E38_CB_COLOR7_CLEAR_WORD2
},
610 {R_028E3C_CB_COLOR7_CLEAR_WORD3
},
611 {GROUP_FORCE_NEW_BLOCK
, 0, 0},
612 {R_028E40_CB_COLOR8_BASE
, REG_FLAG_NEED_BO
, 0},
613 {R_028E44_CB_COLOR8_PITCH
, 0, 0},
614 {R_028E48_CB_COLOR8_SLICE
, 0, 0},
615 {R_028E4C_CB_COLOR8_VIEW
, 0, 0},
616 {R_028E50_CB_COLOR8_INFO
, REG_FLAG_NEED_BO
, 0},
617 {R_028E54_CB_COLOR8_ATTRIB
, REG_FLAG_NEED_BO
, 0},
618 {R_028E58_CB_COLOR8_DIM
, 0, 0},
619 {GROUP_FORCE_NEW_BLOCK
, 0, 0},
620 {R_028E5C_CB_COLOR9_BASE
, REG_FLAG_NEED_BO
, 0},
621 {R_028E60_CB_COLOR9_PITCH
, 0, 0},
622 {R_028E64_CB_COLOR9_SLICE
, 0, 0},
623 {R_028E68_CB_COLOR9_VIEW
, 0, 0},
624 {R_028E6C_CB_COLOR9_INFO
, REG_FLAG_NEED_BO
, 0},
625 {R_028E70_CB_COLOR9_ATTRIB
, REG_FLAG_NEED_BO
, 0},
626 {R_028E74_CB_COLOR9_DIM
, 0, 0},
627 {GROUP_FORCE_NEW_BLOCK
, 0, 0},
628 {R_028E78_CB_COLOR10_BASE
, REG_FLAG_NEED_BO
, 0},
629 {R_028E7C_CB_COLOR10_PITCH
, 0, 0},
630 {R_028E80_CB_COLOR10_SLICE
, 0, 0},
631 {R_028E84_CB_COLOR10_VIEW
, 0, 0},
632 {R_028E88_CB_COLOR10_INFO
, REG_FLAG_NEED_BO
, 0},
633 {R_028E8C_CB_COLOR10_ATTRIB
, REG_FLAG_NEED_BO
, 0},
634 {R_028E90_CB_COLOR10_DIM
, 0, 0},
635 {GROUP_FORCE_NEW_BLOCK
, 0, 0},
636 {R_028E94_CB_COLOR11_BASE
, REG_FLAG_NEED_BO
, 0},
637 {R_028E98_CB_COLOR11_PITCH
, 0, 0},
638 {R_028E9C_CB_COLOR11_SLICE
, 0, 0},
639 {R_028EA0_CB_COLOR11_VIEW
, 0, 0},
640 {R_028EA4_CB_COLOR11_INFO
, REG_FLAG_NEED_BO
, 0},
641 {R_028EA8_CB_COLOR11_ATTRIB
, REG_FLAG_NEED_BO
, 0},
642 {R_028EAC_CB_COLOR11_DIM
, 0, 0},
645 static int evergreen_loop_const_init(struct r600_context
*ctx
, uint32_t offset
)
648 struct r600_reg r600_loop_consts
[32];
651 for (i
= 0; i
< nreg
; i
++) {
652 r600_loop_consts
[i
].offset
= EVERGREEN_LOOP_CONST_OFFSET
+ ((offset
+ i
) * 4);
653 r600_loop_consts
[i
].flags
= REG_FLAG_DIRTY_ALWAYS
;
654 r600_loop_consts
[i
].sbu_flags
= 0;
656 return r600_context_add_block(ctx
, r600_loop_consts
, nreg
, PKT3_SET_LOOP_CONST
, EVERGREEN_LOOP_CONST_OFFSET
);
659 int evergreen_context_init(struct r600_context
*ctx
)
664 if (ctx
->family
>= CHIP_CAYMAN
)
665 r
= r600_context_add_block(ctx
, cayman_config_reg_list
,
666 Elements(cayman_config_reg_list
), PKT3_SET_CONFIG_REG
, EVERGREEN_CONFIG_REG_OFFSET
);
668 r
= r600_context_add_block(ctx
, evergreen_config_reg_list
,
669 Elements(evergreen_config_reg_list
), PKT3_SET_CONFIG_REG
, EVERGREEN_CONFIG_REG_OFFSET
);
672 if (ctx
->family
>= CHIP_CAYMAN
)
673 r
= r600_context_add_block(ctx
, cayman_context_reg_list
,
674 Elements(cayman_context_reg_list
), PKT3_SET_CONTEXT_REG
, EVERGREEN_CONTEXT_REG_OFFSET
);
676 r
= r600_context_add_block(ctx
, evergreen_context_reg_list
,
677 Elements(evergreen_context_reg_list
), PKT3_SET_CONTEXT_REG
, EVERGREEN_CONTEXT_REG_OFFSET
);
680 r
= r600_context_add_block(ctx
, evergreen_ctl_const_list
,
681 Elements(evergreen_ctl_const_list
), PKT3_SET_CTL_CONST
, EVERGREEN_CTL_CONST_OFFSET
);
686 evergreen_loop_const_init(ctx
, 0);
688 evergreen_loop_const_init(ctx
, 32);
690 r
= r600_setup_block_table(ctx
);
697 r600_context_fini(ctx
);
701 void evergreen_flush_vgt_streamout(struct r600_context
*ctx
)
703 struct radeon_winsys_cs
*cs
= ctx
->cs
;
705 cs
->buf
[cs
->cdw
++] = PKT3(PKT3_SET_CONFIG_REG
, 1, 0);
706 cs
->buf
[cs
->cdw
++] = (R_0084FC_CP_STRMOUT_CNTL
- EVERGREEN_CONFIG_REG_OFFSET
) >> 2;
707 cs
->buf
[cs
->cdw
++] = 0;
709 cs
->buf
[cs
->cdw
++] = PKT3(PKT3_EVENT_WRITE
, 0, 0);
710 cs
->buf
[cs
->cdw
++] = EVENT_TYPE(EVENT_TYPE_SO_VGTSTREAMOUT_FLUSH
) | EVENT_INDEX(0);
712 cs
->buf
[cs
->cdw
++] = PKT3(PKT3_WAIT_REG_MEM
, 5, 0);
713 cs
->buf
[cs
->cdw
++] = WAIT_REG_MEM_EQUAL
; /* wait until the register is equal to the reference value */
714 cs
->buf
[cs
->cdw
++] = R_0084FC_CP_STRMOUT_CNTL
>> 2; /* register */
715 cs
->buf
[cs
->cdw
++] = 0;
716 cs
->buf
[cs
->cdw
++] = S_0084FC_OFFSET_UPDATE_DONE(1); /* reference value */
717 cs
->buf
[cs
->cdw
++] = S_0084FC_OFFSET_UPDATE_DONE(1); /* mask */
718 cs
->buf
[cs
->cdw
++] = 4; /* poll interval */
721 void evergreen_set_streamout_enable(struct r600_context
*ctx
, unsigned buffer_enable_bit
)
723 struct radeon_winsys_cs
*cs
= ctx
->cs
;
725 if (buffer_enable_bit
) {
726 cs
->buf
[cs
->cdw
++] = PKT3(PKT3_SET_CONTEXT_REG
, 1, 0);
727 cs
->buf
[cs
->cdw
++] = (R_028B94_VGT_STRMOUT_CONFIG
- EVERGREEN_CONTEXT_REG_OFFSET
) >> 2;
728 cs
->buf
[cs
->cdw
++] = S_028B94_STREAMOUT_0_EN(1);
730 cs
->buf
[cs
->cdw
++] = PKT3(PKT3_SET_CONTEXT_REG
, 1, 0);
731 cs
->buf
[cs
->cdw
++] = (R_028B98_VGT_STRMOUT_BUFFER_CONFIG
- EVERGREEN_CONTEXT_REG_OFFSET
) >> 2;
732 cs
->buf
[cs
->cdw
++] = S_028B98_STREAM_0_BUFFER_EN(buffer_enable_bit
);
734 cs
->buf
[cs
->cdw
++] = PKT3(PKT3_SET_CONTEXT_REG
, 1, 0);
735 cs
->buf
[cs
->cdw
++] = (R_028B94_VGT_STRMOUT_CONFIG
- EVERGREEN_CONTEXT_REG_OFFSET
) >> 2;
736 cs
->buf
[cs
->cdw
++] = S_028B94_STREAMOUT_0_EN(0);