src/gallium/drivers/r600/evergreen_state.c

   1 /*
   2  * Copyright 2010 Jerome Glisse <glisse@freedesktop.org>
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * on the rights to use, copy, modify, merge, publish, distribute, sub
   8  * license, and/or sell copies of the Software, and to permit persons to whom
   9  * the Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice (including the next
  12  * paragraph) shall be included in all copies or substantial portions of the
  13  * Software.
  14  *
  15  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  16  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  17  * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
  18  * THE AUTHOR(S) AND/OR THEIR SUPPLIERS BE LIABLE FOR ANY CLAIM,
  19  * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
  20  * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
  21  * USE OR OTHER DEALINGS IN THE SOFTWARE.
  22  */
  23
  24 /* TODO:
  25  *      - fix mask for depth control & cull for query
  26  */
  27 #include <stdio.h>
  28 #include <errno.h>
  29 #include <pipe/p_defines.h>
  30 #include <pipe/p_state.h>
  31 #include <pipe/p_context.h>
  32 #include <tgsi/tgsi_scan.h>
  33 #include <tgsi/tgsi_parse.h>
  34 #include <tgsi/tgsi_util.h>
  35 #include <util/u_blitter.h>
  36 #include <util/u_double_list.h>
  37 #include <util/u_transfer.h>
  38 #include <util/u_surface.h>
  39 #include <util/u_pack_color.h>
  40 #include <util/u_memory.h>
  41 #include <util/u_inlines.h>
  42 #include <util/u_framebuffer.h>
  43 #include <pipebuffer/pb_buffer.h>
  44 #include "r600.h"
  45 #include "evergreend.h"
  46 #include "r600_resource.h"
  47 #include "r600_shader.h"
  48 #include "r600_pipe.h"
  49 #include "eg_state_inlines.h"
  50
  51 static void evergreen_set_blend_color(struct pipe_context *ctx,
  52                                         const struct pipe_blend_color *state)
  53 {
  54         struct r600_pipe_context *rctx = (struct r600_pipe_context *)ctx;
  55         struct r600_pipe_state *rstate = CALLOC_STRUCT(r600_pipe_state);
  56
  57         if (rstate == NULL)
  58                 return;
  59
  60         rstate->id = R600_PIPE_STATE_BLEND_COLOR;
  61         r600_pipe_state_add_reg(rstate, R_028414_CB_BLEND_RED, fui(state->color[0]), 0xFFFFFFFF, NULL);
  62         r600_pipe_state_add_reg(rstate, R_028418_CB_BLEND_GREEN, fui(state->color[1]), 0xFFFFFFFF, NULL);
  63         r600_pipe_state_add_reg(rstate, R_02841C_CB_BLEND_BLUE, fui(state->color[2]), 0xFFFFFFFF, NULL);
  64         r600_pipe_state_add_reg(rstate, R_028420_CB_BLEND_ALPHA, fui(state->color[3]), 0xFFFFFFFF, NULL);
  65
  66         free(rctx->states[R600_PIPE_STATE_BLEND_COLOR]);
  67         rctx->states[R600_PIPE_STATE_BLEND_COLOR] = rstate;
  68         r600_context_pipe_state_set(&rctx->ctx, rstate);
  69 }
  70
  71 static void *evergreen_create_blend_state(struct pipe_context *ctx,
  72                                         const struct pipe_blend_state *state)
  73 {
  74         struct r600_pipe_blend *blend = CALLOC_STRUCT(r600_pipe_blend);
  75         struct r600_pipe_state *rstate;
  76         u32 color_control, target_mask;
  77         /* FIXME there is more then 8 framebuffer */
  78         unsigned blend_cntl[8];
  79
  80         if (blend == NULL) {
  81                 return NULL;
  82         }
  83         rstate = &blend->rstate;
  84
  85         rstate->id = R600_PIPE_STATE_BLEND;
  86
  87         target_mask = 0;
  88         color_control = S_028808_MODE(1);
  89         if (state->logicop_enable) {
  90                 color_control |= (state->logicop_func << 16) | (state->logicop_func << 20);
  91         } else {
  92                 color_control |= (0xcc << 16);
  93         }
  94         /* we pretend 8 buffer are used, CB_SHADER_MASK will disable unused one */
  95         if (state->independent_blend_enable) {
  96                 for (int i = 0; i < 8; i++) {
  97                         target_mask |= (state->rt[i].colormask << (4 * i));
  98                 }
  99         } else {
 100                 for (int i = 0; i < 8; i++) {
 101                         target_mask |= (state->rt[0].colormask << (4 * i));
 102                 }
 103         }
 104         blend->cb_target_mask = target_mask;
 105         r600_pipe_state_add_reg(rstate, R_028808_CB_COLOR_CONTROL,
 106                                 color_control, 0xFFFFFFFD, NULL);
 107         r600_pipe_state_add_reg(rstate, R_028C3C_PA_SC_AA_MASK, 0xFFFFFFFF, 0xFFFFFFFF, NULL);
 108
 109         for (int i = 0; i < 8; i++) {
 110                 unsigned eqRGB = state->rt[i].rgb_func;
 111                 unsigned srcRGB = state->rt[i].rgb_src_factor;
 112                 unsigned dstRGB = state->rt[i].rgb_dst_factor;
 113                 unsigned eqA = state->rt[i].alpha_func;
 114                 unsigned srcA = state->rt[i].alpha_src_factor;
 115                 unsigned dstA = state->rt[i].alpha_dst_factor;
 116
 117                 blend_cntl[i] = 0;
 118                 if (!state->rt[i].blend_enable)
 119                         continue;
 120
 121                 blend_cntl[i] |= S_028780_BLEND_CONTROL_ENABLE(1);
 122                 blend_cntl[i] |= S_028780_COLOR_COMB_FCN(r600_translate_blend_function(eqRGB));
 123                 blend_cntl[i] |= S_028780_COLOR_SRCBLEND(r600_translate_blend_factor(srcRGB));
 124                 blend_cntl[i] |= S_028780_COLOR_DESTBLEND(r600_translate_blend_factor(dstRGB));
 125
 126                 if (srcA != srcRGB || dstA != dstRGB || eqA != eqRGB) {
 127                         blend_cntl[i] |= S_028780_SEPARATE_ALPHA_BLEND(1);
 128                         blend_cntl[i] |= S_028780_ALPHA_COMB_FCN(r600_translate_blend_function(eqA));
 129                         blend_cntl[i] |= S_028780_ALPHA_SRCBLEND(r600_translate_blend_factor(srcA));
 130                         blend_cntl[i] |= S_028780_ALPHA_DESTBLEND(r600_translate_blend_factor(dstA));
 131                 }
 132         }
 133         for (int i = 0; i < 8; i++) {
 134                 r600_pipe_state_add_reg(rstate, R_028780_CB_BLEND0_CONTROL + i * 4, blend_cntl[i], 0xFFFFFFFF, NULL);
 135         }
 136
 137         return rstate;
 138 }
 139
 140 static void *evergreen_create_dsa_state(struct pipe_context *ctx,
 141                                    const struct pipe_depth_stencil_alpha_state *state)
 142 {
 143         struct r600_pipe_state *rstate = CALLOC_STRUCT(r600_pipe_state);
 144         unsigned db_depth_control, alpha_test_control, alpha_ref, db_shader_control;
 145         unsigned stencil_ref_mask, stencil_ref_mask_bf, db_render_override, db_render_control;
 146
 147         if (rstate == NULL) {
 148                 return NULL;
 149         }
 150
 151         rstate->id = R600_PIPE_STATE_DSA;
 152         /* depth TODO some of those db_shader_control field depend on shader adjust mask & add it to shader */
 153         /* db_shader_control is 0xFFFFFFBE as Z_EXPORT_ENABLE (bit 0) will be
 154          * set by fragment shader if it export Z and KILL_ENABLE (bit 6) will
 155          * be set if shader use texkill instruction
 156          */
 157         db_shader_control = S_02880C_Z_ORDER(V_02880C_EARLY_Z_THEN_LATE_Z);
 158         stencil_ref_mask = 0;
 159         stencil_ref_mask_bf = 0;
 160         db_depth_control = S_028800_Z_ENABLE(state->depth.enabled) |
 161                 S_028800_Z_WRITE_ENABLE(state->depth.writemask) |
 162                 S_028800_ZFUNC(state->depth.func);
 163
 164         /* stencil */
 165         if (state->stencil[0].enabled) {
 166                 db_depth_control |= S_028800_STENCIL_ENABLE(1);
 167                 db_depth_control |= S_028800_STENCILFUNC(r600_translate_ds_func(state->stencil[0].func));
 168                 db_depth_control |= S_028800_STENCILFAIL(r600_translate_stencil_op(state->stencil[0].fail_op));
 169                 db_depth_control |= S_028800_STENCILZPASS(r600_translate_stencil_op(state->stencil[0].zpass_op));
 170                 db_depth_control |= S_028800_STENCILZFAIL(r600_translate_stencil_op(state->stencil[0].zfail_op));
 171
 172
 173                 stencil_ref_mask = S_028430_STENCILMASK(state->stencil[0].valuemask) |
 174                         S_028430_STENCILWRITEMASK(state->stencil[0].writemask);
 175                 if (state->stencil[1].enabled) {
 176                         db_depth_control |= S_028800_BACKFACE_ENABLE(1);
 177                         db_depth_control |= S_028800_STENCILFUNC_BF(r600_translate_ds_func(state->stencil[1].func));
 178                         db_depth_control |= S_028800_STENCILFAIL_BF(r600_translate_stencil_op(state->stencil[1].fail_op));
 179                         db_depth_control |= S_028800_STENCILZPASS_BF(r600_translate_stencil_op(state->stencil[1].zpass_op));
 180                         db_depth_control |= S_028800_STENCILZFAIL_BF(r600_translate_stencil_op(state->stencil[1].zfail_op));
 181                         stencil_ref_mask_bf = S_028434_STENCILMASK_BF(state->stencil[1].valuemask) |
 182                                 S_028434_STENCILWRITEMASK_BF(state->stencil[1].writemask);
 183                 }
 184         }
 185
 186         /* alpha */
 187         alpha_test_control = 0;
 188         alpha_ref = 0;
 189         if (state->alpha.enabled) {
 190                 alpha_test_control = S_028410_ALPHA_FUNC(state->alpha.func);
 191                 alpha_test_control |= S_028410_ALPHA_TEST_ENABLE(1);
 192                 alpha_ref = fui(state->alpha.ref_value);
 193         }
 194
 195         /* misc */
 196         db_render_control = 0;
 197         db_render_override = S_02800C_FORCE_HIZ_ENABLE(V_02800C_FORCE_DISABLE) |
 198                 S_02800C_FORCE_HIS_ENABLE0(V_02800C_FORCE_DISABLE) |
 199                 S_02800C_FORCE_HIS_ENABLE1(V_02800C_FORCE_DISABLE);
 200         /* TODO db_render_override depends on query */
 201         r600_pipe_state_add_reg(rstate, R_028028_DB_STENCIL_CLEAR, 0x00000000, 0xFFFFFFFF, NULL);
 202         r600_pipe_state_add_reg(rstate, R_02802C_DB_DEPTH_CLEAR, 0x3F800000, 0xFFFFFFFF, NULL);
 203         r600_pipe_state_add_reg(rstate, R_028410_SX_ALPHA_TEST_CONTROL, alpha_test_control, 0xFFFFFFFF, NULL);
 204         r600_pipe_state_add_reg(rstate,
 205                                 R_028430_DB_STENCILREFMASK, stencil_ref_mask,
 206                                 0xFFFFFFFF & C_028430_STENCILREF, NULL);
 207         r600_pipe_state_add_reg(rstate,
 208                                 R_028434_DB_STENCILREFMASK_BF, stencil_ref_mask_bf,
 209                                 0xFFFFFFFF & C_028434_STENCILREF_BF, NULL);
 210         r600_pipe_state_add_reg(rstate, R_028438_SX_ALPHA_REF, alpha_ref, 0xFFFFFFFF, NULL);
 211         r600_pipe_state_add_reg(rstate, R_0286DC_SPI_FOG_CNTL, 0x00000000, 0xFFFFFFFF, NULL);
 212         r600_pipe_state_add_reg(rstate, R_028800_DB_DEPTH_CONTROL, db_depth_control, 0xFFFFFFFF, NULL);
 213         r600_pipe_state_add_reg(rstate, R_02880C_DB_SHADER_CONTROL, db_shader_control, 0xFFFFFFBE, NULL);
 214         r600_pipe_state_add_reg(rstate, R_028000_DB_RENDER_CONTROL, db_render_control, 0xFFFFFFFF, NULL);
 215         r600_pipe_state_add_reg(rstate, R_02800C_DB_RENDER_OVERRIDE, db_render_override, 0xFFFFFFFF, NULL);
 216         r600_pipe_state_add_reg(rstate, R_028AC0_DB_SRESULTS_COMPARE_STATE0, 0x0, 0xFFFFFFFF, NULL);
 217         r600_pipe_state_add_reg(rstate, R_028AC4_DB_SRESULTS_COMPARE_STATE1, 0x0, 0xFFFFFFFF, NULL);
 218         r600_pipe_state_add_reg(rstate, R_028AC8_DB_PRELOAD_CONTROL, 0x0, 0xFFFFFFFF, NULL);
 219         r600_pipe_state_add_reg(rstate, R_028B70_DB_ALPHA_TO_MASK, 0x0000AA00, 0xFFFFFFFF, NULL);
 220
 221         return rstate;
 222 }
 223
 224 static void *evergreen_create_rs_state(struct pipe_context *ctx,
 225                                         const struct pipe_rasterizer_state *state)
 226 {
 227         struct r600_pipe_rasterizer *rs = CALLOC_STRUCT(r600_pipe_rasterizer);
 228         struct r600_pipe_state *rstate;
 229         unsigned tmp;
 230         unsigned prov_vtx = 1, polygon_dual_mode;
 231         unsigned clip_rule;
 232
 233         if (rs == NULL) {
 234                 return NULL;
 235         }
 236
 237         rstate = &rs->rstate;
 238         rs->flatshade = state->flatshade;
 239         rs->sprite_coord_enable = state->sprite_coord_enable;
 240
 241         clip_rule = state->scissor ? 0xAAAA : 0xFFFF;
 242
 243         /* offset */
 244         rs->offset_units = state->offset_units;
 245         rs->offset_scale = state->offset_scale * 12.0f;
 246
 247         rstate->id = R600_PIPE_STATE_RASTERIZER;
 248         if (state->flatshade_first)
 249                 prov_vtx = 0;
 250         tmp = S_0286D4_FLAT_SHADE_ENA(1);
 251         if (state->sprite_coord_enable) {
 252                 tmp |= S_0286D4_PNT_SPRITE_ENA(1) |
 253                         S_0286D4_PNT_SPRITE_OVRD_X(2) |
 254                         S_0286D4_PNT_SPRITE_OVRD_Y(3) |
 255                         S_0286D4_PNT_SPRITE_OVRD_Z(0) |
 256                         S_0286D4_PNT_SPRITE_OVRD_W(1);
 257                 if (state->sprite_coord_mode != PIPE_SPRITE_COORD_UPPER_LEFT) {
 258                         tmp |= S_0286D4_PNT_SPRITE_TOP_1(1);
 259                 }
 260         }
 261         r600_pipe_state_add_reg(rstate, R_0286D4_SPI_INTERP_CONTROL_0, tmp, 0xFFFFFFFF, NULL);
 262
 263         polygon_dual_mode = (state->fill_front != PIPE_POLYGON_MODE_FILL ||
 264                                 state->fill_back != PIPE_POLYGON_MODE_FILL);
 265         r600_pipe_state_add_reg(rstate, R_028814_PA_SU_SC_MODE_CNTL,
 266                 S_028814_PROVOKING_VTX_LAST(prov_vtx) |
 267                 S_028814_CULL_FRONT((state->cull_face & PIPE_FACE_FRONT) ? 1 : 0) |
 268                 S_028814_CULL_BACK((state->cull_face & PIPE_FACE_BACK) ? 1 : 0) |
 269                 S_028814_FACE(!state->front_ccw) |
 270                 S_028814_POLY_OFFSET_FRONT_ENABLE(state->offset_tri) |
 271                 S_028814_POLY_OFFSET_BACK_ENABLE(state->offset_tri) |
 272                 S_028814_POLY_OFFSET_PARA_ENABLE(state->offset_tri) |
 273                 S_028814_POLY_MODE(polygon_dual_mode) |
 274                 S_028814_POLYMODE_FRONT_PTYPE(r600_translate_fill(state->fill_front)) |
 275                 S_028814_POLYMODE_BACK_PTYPE(r600_translate_fill(state->fill_back)), 0xFFFFFFFF, NULL);
 276         r600_pipe_state_add_reg(rstate, R_02881C_PA_CL_VS_OUT_CNTL,
 277                         S_02881C_USE_VTX_POINT_SIZE(state->point_size_per_vertex) |
 278                         S_02881C_VS_OUT_MISC_VEC_ENA(state->point_size_per_vertex), 0xFFFFFFFF, NULL);
 279         r600_pipe_state_add_reg(rstate, R_028820_PA_CL_NANINF_CNTL, 0x00000000, 0xFFFFFFFF, NULL);
 280         /* point size 12.4 fixed point */
 281         tmp = (unsigned)(state->point_size * 8.0);
 282         r600_pipe_state_add_reg(rstate, R_028A00_PA_SU_POINT_SIZE, S_028A00_HEIGHT(tmp) | S_028A00_WIDTH(tmp), 0xFFFFFFFF, NULL);
 283         r600_pipe_state_add_reg(rstate, R_028A04_PA_SU_POINT_MINMAX, 0x80000000, 0xFFFFFFFF, NULL);
 284
 285         tmp = (unsigned)state->line_width * 8;
 286         r600_pipe_state_add_reg(rstate, R_028A08_PA_SU_LINE_CNTL, S_028A08_WIDTH(tmp), 0xFFFFFFFF, NULL);
 287
 288         r600_pipe_state_add_reg(rstate, R_028C00_PA_SC_LINE_CNTL, 0x00000400, 0xFFFFFFFF, NULL);
 289         r600_pipe_state_add_reg(rstate, R_028C0C_PA_CL_GB_VERT_CLIP_ADJ, 0x3F800000, 0xFFFFFFFF, NULL);
 290         r600_pipe_state_add_reg(rstate, R_028C10_PA_CL_GB_VERT_DISC_ADJ, 0x3F800000, 0xFFFFFFFF, NULL);
 291         r600_pipe_state_add_reg(rstate, R_028C14_PA_CL_GB_HORZ_CLIP_ADJ, 0x3F800000, 0xFFFFFFFF, NULL);
 292         r600_pipe_state_add_reg(rstate, R_028C18_PA_CL_GB_HORZ_DISC_ADJ, 0x3F800000, 0xFFFFFFFF, NULL);
 293         r600_pipe_state_add_reg(rstate, R_028B7C_PA_SU_POLY_OFFSET_CLAMP, 0x0, 0xFFFFFFFF, NULL);
 294
 295         r600_pipe_state_add_reg(rstate, R_028C08_PA_SU_VTX_CNTL,
 296                                 S_028C08_PIX_CENTER_HALF(state->gl_rasterization_rules),
 297                                 0xFFFFFFFF, NULL);
 298
 299         r600_pipe_state_add_reg(rstate, R_02820C_PA_SC_CLIPRECT_RULE, clip_rule, 0xFFFFFFFF, NULL);
 300         return rstate;
 301 }
 302
 303 static void *evergreen_create_sampler_state(struct pipe_context *ctx,
 304                                         const struct pipe_sampler_state *state)
 305 {
 306         struct r600_pipe_state *rstate = CALLOC_STRUCT(r600_pipe_state);
 307         union util_color uc;
 308
 309         if (rstate == NULL) {
 310                 return NULL;
 311         }
 312
 313         rstate->id = R600_PIPE_STATE_SAMPLER;
 314         util_pack_color(state->border_color, PIPE_FORMAT_B8G8R8A8_UNORM, &uc);
 315         r600_pipe_state_add_reg(rstate, R_03C000_SQ_TEX_SAMPLER_WORD0_0,
 316                         S_03C000_CLAMP_X(r600_tex_wrap(state->wrap_s)) |
 317                         S_03C000_CLAMP_Y(r600_tex_wrap(state->wrap_t)) |
 318                         S_03C000_CLAMP_Z(r600_tex_wrap(state->wrap_r)) |
 319                         S_03C000_XY_MAG_FILTER(r600_tex_filter(state->mag_img_filter)) |
 320                         S_03C000_XY_MIN_FILTER(r600_tex_filter(state->min_img_filter)) |
 321                         S_03C000_MIP_FILTER(r600_tex_mipfilter(state->min_mip_filter)) |
 322                         S_03C000_DEPTH_COMPARE_FUNCTION(r600_tex_compare(state->compare_func)) |
 323                         S_03C000_BORDER_COLOR_TYPE(uc.ui ? V_03C000_SQ_TEX_BORDER_COLOR_REGISTER : 0), 0xFFFFFFFF, NULL);
 324         /* FIXME LOD it depends on texture base level ... */
 325         r600_pipe_state_add_reg(rstate, R_03C004_SQ_TEX_SAMPLER_WORD1_0,
 326                         S_03C004_MIN_LOD(S_FIXED(CLAMP(state->min_lod, 0, 15), 8)) |
 327                         S_03C004_MAX_LOD(S_FIXED(CLAMP(state->max_lod, 0, 15), 8)),
 328                         0xFFFFFFFF, NULL);
 329         r600_pipe_state_add_reg(rstate, R_03C008_SQ_TEX_SAMPLER_WORD2_0,
 330                                 S_03C008_LOD_BIAS(S_FIXED(CLAMP(state->lod_bias, -16, 16), 8)) |
 331                                 S_03C008_TYPE(1),
 332                                 0xFFFFFFFF, NULL);
 333
 334         if (uc.ui) {
 335                 r600_pipe_state_add_reg(rstate, R_00A404_TD_PS_SAMPLER0_BORDER_RED, fui(state->border_color[0]), 0xFFFFFFFF, NULL);
 336                 r600_pipe_state_add_reg(rstate, R_00A408_TD_PS_SAMPLER0_BORDER_GREEN, fui(state->border_color[1]), 0xFFFFFFFF, NULL);
 337                 r600_pipe_state_add_reg(rstate, R_00A40C_TD_PS_SAMPLER0_BORDER_BLUE, fui(state->border_color[2]), 0xFFFFFFFF, NULL);
 338                 r600_pipe_state_add_reg(rstate, R_00A410_TD_PS_SAMPLER0_BORDER_ALPHA, fui(state->border_color[3]), 0xFFFFFFFF, NULL);
 339         }
 340         return rstate;
 341 }
 342
 343 static struct pipe_sampler_view *evergreen_create_sampler_view(struct pipe_context *ctx,
 344                                                         struct pipe_resource *texture,
 345                                                         const struct pipe_sampler_view *state)
 346 {
 347         struct r600_pipe_sampler_view *resource = CALLOC_STRUCT(r600_pipe_sampler_view);
 348         struct r600_pipe_state *rstate;
 349         const struct util_format_description *desc;
 350         struct r600_resource_texture *tmp;
 351         struct r600_resource *rbuffer;
 352         unsigned format;
 353         uint32_t word4 = 0, yuv_format = 0, pitch = 0;
 354         unsigned char swizzle[4], array_mode = 0, tile_type = 0;
 355         struct r600_bo *bo[2];
 356
 357         if (resource == NULL)
 358                 return NULL;
 359         rstate = &resource->state;
 360
 361         /* initialize base object */
 362         resource->base = *state;
 363         resource->base.texture = NULL;
 364         pipe_reference(NULL, &texture->reference);
 365         resource->base.texture = texture;
 366         resource->base.reference.count = 1;
 367         resource->base.context = ctx;
 368
 369         swizzle[0] = state->swizzle_r;
 370         swizzle[1] = state->swizzle_g;
 371         swizzle[2] = state->swizzle_b;
 372         swizzle[3] = state->swizzle_a;
 373         format = r600_translate_texformat(state->format,
 374                                           swizzle,
 375                                           &word4, &yuv_format);
 376         if (format == ~0) {
 377                 format = 0;
 378         }
 379         desc = util_format_description(state->format);
 380         if (desc == NULL) {
 381                 R600_ERR("unknow format %d\n", state->format);
 382         }
 383         tmp = (struct r600_resource_texture *)texture;
 384         if (tmp->depth && tmp->tile_type == 1) {
 385                 r600_texture_depth_flush(ctx, texture, TRUE);
 386                 tmp = tmp->flushed_depth_texture;
 387         }
 388         rbuffer = &tmp->resource;
 389         bo[0] = rbuffer->bo;
 390         bo[1] = rbuffer->bo;
 391
 392         pitch = align(tmp->pitch_in_pixels[0], 8);
 393         if (tmp->tiled) {
 394                 array_mode = tmp->array_mode[0];
 395                 tile_type = tmp->tile_type;
 396         }
 397
 398         /* FIXME properly handle first level != 0 */
 399         r600_pipe_state_add_reg(rstate, R_030000_RESOURCE0_WORD0,
 400                                 S_030000_DIM(r600_tex_dim(texture->target)) |
 401                                 S_030000_PITCH((pitch / 8) - 1) |
 402                                 S_030000_NON_DISP_TILING_ORDER(tile_type) |
 403                                 S_030000_TEX_WIDTH(texture->width0 - 1), 0xFFFFFFFF, NULL);
 404         r600_pipe_state_add_reg(rstate, R_030004_RESOURCE0_WORD1,
 405                                 S_030004_TEX_HEIGHT(texture->height0 - 1) |
 406                                 S_030004_TEX_DEPTH(texture->depth0 - 1) |
 407                                 S_030004_ARRAY_MODE(array_mode),
 408                                 0xFFFFFFFF, NULL);
 409         r600_pipe_state_add_reg(rstate, R_030008_RESOURCE0_WORD2,
 410                                 (tmp->offset[0] + r600_bo_offset(bo[0])) >> 8, 0xFFFFFFFF, bo[0]);
 411         r600_pipe_state_add_reg(rstate, R_03000C_RESOURCE0_WORD3,
 412                                 (tmp->offset[1] + r600_bo_offset(bo[1])) >> 8, 0xFFFFFFFF, bo[1]);
 413         r600_pipe_state_add_reg(rstate, R_030010_RESOURCE0_WORD4,
 414                                 word4 | S_030010_NUM_FORMAT_ALL(V_030010_SQ_NUM_FORMAT_NORM) |
 415                                 S_030010_SRF_MODE_ALL(V_030010_SRF_MODE_NO_ZERO) |
 416                                 S_030010_BASE_LEVEL(state->u.tex.first_level), 0xFFFFFFFF, NULL);
 417         r600_pipe_state_add_reg(rstate, R_030014_RESOURCE0_WORD5,
 418                                 S_030014_LAST_LEVEL(state->u.tex.last_level) |
 419                                 S_030014_BASE_ARRAY(0) |
 420                                 S_030014_LAST_ARRAY(0), 0xffffffff, NULL);
 421         r600_pipe_state_add_reg(rstate, R_030018_RESOURCE0_WORD6, 0x0, 0xFFFFFFFF, NULL);
 422         r600_pipe_state_add_reg(rstate, R_03001C_RESOURCE0_WORD7,
 423                                 S_03001C_DATA_FORMAT(format) |
 424                                 S_03001C_TYPE(V_03001C_SQ_TEX_VTX_VALID_TEXTURE), 0xFFFFFFFF, NULL);
 425
 426         return &resource->base;
 427 }
 428
 429 static void evergreen_set_vs_sampler_view(struct pipe_context *ctx, unsigned count,
 430                                         struct pipe_sampler_view **views)
 431 {
 432         struct r600_pipe_context *rctx = (struct r600_pipe_context *)ctx;
 433         struct r600_pipe_sampler_view **resource = (struct r600_pipe_sampler_view **)views;
 434
 435         for (int i = 0; i < count; i++) {
 436                 if (resource[i]) {
 437                         evergreen_context_pipe_state_set_vs_resource(&rctx->ctx, &resource[i]->state, i);
 438                 }
 439         }
 440 }
 441
 442 static void evergreen_set_ps_sampler_view(struct pipe_context *ctx, unsigned count,
 443                                         struct pipe_sampler_view **views)
 444 {
 445         struct r600_pipe_context *rctx = (struct r600_pipe_context *)ctx;
 446         struct r600_pipe_sampler_view **resource = (struct r600_pipe_sampler_view **)views;
 447         int i;
 448
 449         for (i = 0; i < count; i++) {
 450                 if (&rctx->ps_samplers.views[i]->base != views[i]) {
 451                         if (resource[i])
 452                                 evergreen_context_pipe_state_set_ps_resource(&rctx->ctx, &resource[i]->state, i);
 453                         else
 454                                 evergreen_context_pipe_state_set_ps_resource(&rctx->ctx, NULL, i);
 455
 456                         pipe_sampler_view_reference(
 457                                 (struct pipe_sampler_view **)&rctx->ps_samplers.views[i],
 458                                 views[i]);
 459                 }
 460         }
 461         for (i = count; i < NUM_TEX_UNITS; i++) {
 462                 if (rctx->ps_samplers.views[i]) {
 463                         evergreen_context_pipe_state_set_ps_resource(&rctx->ctx, NULL, i);
 464                         pipe_sampler_view_reference((struct pipe_sampler_view **)&rctx->ps_samplers.views[i], NULL);
 465                 }
 466         }
 467         rctx->ps_samplers.n_views = count;
 468 }
 469
 470 static void evergreen_bind_ps_sampler(struct pipe_context *ctx, unsigned count, void **states)
 471 {
 472         struct r600_pipe_context *rctx = (struct r600_pipe_context *)ctx;
 473         struct r600_pipe_state **rstates = (struct r600_pipe_state **)states;
 474
 475
 476         memcpy(rctx->ps_samplers.samplers, states, sizeof(void*) * count);
 477         rctx->ps_samplers.n_samplers = count;
 478
 479         for (int i = 0; i < count; i++) {
 480                 evergreen_context_pipe_state_set_ps_sampler(&rctx->ctx, rstates[i], i);
 481         }
 482 }
 483
 484 static void evergreen_bind_vs_sampler(struct pipe_context *ctx, unsigned count, void **states)
 485 {
 486         struct r600_pipe_context *rctx = (struct r600_pipe_context *)ctx;
 487         struct r600_pipe_state **rstates = (struct r600_pipe_state **)states;
 488
 489         for (int i = 0; i < count; i++) {
 490                 evergreen_context_pipe_state_set_vs_sampler(&rctx->ctx, rstates[i], i);
 491         }
 492 }
 493
 494 static void evergreen_set_clip_state(struct pipe_context *ctx,
 495                                 const struct pipe_clip_state *state)
 496 {
 497         struct r600_pipe_context *rctx = (struct r600_pipe_context *)ctx;
 498         struct r600_pipe_state *rstate = CALLOC_STRUCT(r600_pipe_state);
 499
 500         if (rstate == NULL)
 501                 return;
 502
 503         rctx->clip = *state;
 504         rstate->id = R600_PIPE_STATE_CLIP;
 505         for (int i = 0; i < state->nr; i++) {
 506                 r600_pipe_state_add_reg(rstate,
 507                                         R_0285BC_PA_CL_UCP0_X + i * 16,
 508                                         fui(state->ucp[i][0]), 0xFFFFFFFF, NULL);
 509                 r600_pipe_state_add_reg(rstate,
 510                                         R_0285C0_PA_CL_UCP0_Y + i * 16,
 511                                         fui(state->ucp[i][1]) , 0xFFFFFFFF, NULL);
 512                 r600_pipe_state_add_reg(rstate,
 513                                         R_0285C4_PA_CL_UCP0_Z + i * 16,
 514                                         fui(state->ucp[i][2]), 0xFFFFFFFF, NULL);
 515                 r600_pipe_state_add_reg(rstate,
 516                                         R_0285C8_PA_CL_UCP0_W + i * 16,
 517                                         fui(state->ucp[i][3]), 0xFFFFFFFF, NULL);
 518         }
 519         r600_pipe_state_add_reg(rstate, R_028810_PA_CL_CLIP_CNTL,
 520                         S_028810_PS_UCP_MODE(3) | ((1 << state->nr) - 1) |
 521                         S_028810_ZCLIP_NEAR_DISABLE(state->depth_clamp) |
 522                         S_028810_ZCLIP_FAR_DISABLE(state->depth_clamp), 0xFFFFFFFF, NULL);
 523
 524         free(rctx->states[R600_PIPE_STATE_CLIP]);
 525         rctx->states[R600_PIPE_STATE_CLIP] = rstate;
 526         r600_context_pipe_state_set(&rctx->ctx, rstate);
 527 }
 528
 529 static void evergreen_set_polygon_stipple(struct pipe_context *ctx,
 530                                          const struct pipe_poly_stipple *state)
 531 {
 532 }
 533
 534 static void evergreen_set_sample_mask(struct pipe_context *pipe, unsigned sample_mask)
 535 {
 536 }
 537
 538 static void evergreen_set_scissor_state(struct pipe_context *ctx,
 539                                         const struct pipe_scissor_state *state)
 540 {
 541         struct r600_pipe_context *rctx = (struct r600_pipe_context *)ctx;
 542         struct r600_pipe_state *rstate = CALLOC_STRUCT(r600_pipe_state);
 543         u32 tl, br;
 544
 545         if (rstate == NULL)
 546                 return;
 547
 548         rstate->id = R600_PIPE_STATE_SCISSOR;
 549         tl = S_028240_TL_X(state->minx) | S_028240_TL_Y(state->miny);
 550         br = S_028244_BR_X(state->maxx) | S_028244_BR_Y(state->maxy);
 551         r600_pipe_state_add_reg(rstate,
 552                                 R_028210_PA_SC_CLIPRECT_0_TL, tl,
 553                                 0xFFFFFFFF, NULL);
 554         r600_pipe_state_add_reg(rstate,
 555                                 R_028214_PA_SC_CLIPRECT_0_BR, br,
 556                                 0xFFFFFFFF, NULL);
 557         r600_pipe_state_add_reg(rstate,
 558                                 R_028218_PA_SC_CLIPRECT_1_TL, tl,
 559                                 0xFFFFFFFF, NULL);
 560         r600_pipe_state_add_reg(rstate,
 561                                 R_02821C_PA_SC_CLIPRECT_1_BR, br,
 562                                 0xFFFFFFFF, NULL);
 563         r600_pipe_state_add_reg(rstate,
 564                                 R_028220_PA_SC_CLIPRECT_2_TL, tl,
 565                                 0xFFFFFFFF, NULL);
 566         r600_pipe_state_add_reg(rstate,
 567                                 R_028224_PA_SC_CLIPRECT_2_BR, br,
 568                                 0xFFFFFFFF, NULL);
 569         r600_pipe_state_add_reg(rstate,
 570                                 R_028228_PA_SC_CLIPRECT_3_TL, tl,
 571                                 0xFFFFFFFF, NULL);
 572         r600_pipe_state_add_reg(rstate,
 573                                 R_02822C_PA_SC_CLIPRECT_3_BR, br,
 574                                 0xFFFFFFFF, NULL);
 575
 576         free(rctx->states[R600_PIPE_STATE_SCISSOR]);
 577         rctx->states[R600_PIPE_STATE_SCISSOR] = rstate;
 578         r600_context_pipe_state_set(&rctx->ctx, rstate);
 579 }
 580
 581 static void evergreen_set_stencil_ref(struct pipe_context *ctx,
 582                                 const struct pipe_stencil_ref *state)
 583 {
 584         struct r600_pipe_context *rctx = (struct r600_pipe_context *)ctx;
 585         struct r600_pipe_state *rstate = CALLOC_STRUCT(r600_pipe_state);
 586         u32 tmp;
 587
 588         if (rstate == NULL)
 589                 return;
 590
 591         rctx->stencil_ref = *state;
 592         rstate->id = R600_PIPE_STATE_STENCIL_REF;
 593         tmp = S_028430_STENCILREF(state->ref_value[0]);
 594         r600_pipe_state_add_reg(rstate,
 595                                 R_028430_DB_STENCILREFMASK, tmp,
 596                                 ~C_028430_STENCILREF, NULL);
 597         tmp = S_028434_STENCILREF_BF(state->ref_value[1]);
 598         r600_pipe_state_add_reg(rstate,
 599                                 R_028434_DB_STENCILREFMASK_BF, tmp,
 600                                 ~C_028434_STENCILREF_BF, NULL);
 601
 602         free(rctx->states[R600_PIPE_STATE_STENCIL_REF]);
 603         rctx->states[R600_PIPE_STATE_STENCIL_REF] = rstate;
 604         r600_context_pipe_state_set(&rctx->ctx, rstate);
 605 }
 606
 607 static void evergreen_set_viewport_state(struct pipe_context *ctx,
 608                                         const struct pipe_viewport_state *state)
 609 {
 610         struct r600_pipe_context *rctx = (struct r600_pipe_context *)ctx;
 611         struct r600_pipe_state *rstate = CALLOC_STRUCT(r600_pipe_state);
 612
 613         if (rstate == NULL)
 614                 return;
 615
 616         rctx->viewport = *state;
 617         rstate->id = R600_PIPE_STATE_VIEWPORT;
 618         r600_pipe_state_add_reg(rstate, R_0282D0_PA_SC_VPORT_ZMIN_0, 0x00000000, 0xFFFFFFFF, NULL);
 619         r600_pipe_state_add_reg(rstate, R_0282D4_PA_SC_VPORT_ZMAX_0, 0x3F800000, 0xFFFFFFFF, NULL);
 620         r600_pipe_state_add_reg(rstate, R_02843C_PA_CL_VPORT_XSCALE_0, fui(state->scale[0]), 0xFFFFFFFF, NULL);
 621         r600_pipe_state_add_reg(rstate, R_028444_PA_CL_VPORT_YSCALE_0, fui(state->scale[1]), 0xFFFFFFFF, NULL);
 622         r600_pipe_state_add_reg(rstate, R_02844C_PA_CL_VPORT_ZSCALE_0, fui(state->scale[2]), 0xFFFFFFFF, NULL);
 623         r600_pipe_state_add_reg(rstate, R_028440_PA_CL_VPORT_XOFFSET_0, fui(state->translate[0]), 0xFFFFFFFF, NULL);
 624         r600_pipe_state_add_reg(rstate, R_028448_PA_CL_VPORT_YOFFSET_0, fui(state->translate[1]), 0xFFFFFFFF, NULL);
 625         r600_pipe_state_add_reg(rstate, R_028450_PA_CL_VPORT_ZOFFSET_0, fui(state->translate[2]), 0xFFFFFFFF, NULL);
 626         r600_pipe_state_add_reg(rstate, R_028818_PA_CL_VTE_CNTL, 0x0000043F, 0xFFFFFFFF, NULL);
 627
 628         free(rctx->states[R600_PIPE_STATE_VIEWPORT]);
 629         rctx->states[R600_PIPE_STATE_VIEWPORT] = rstate;
 630         r600_context_pipe_state_set(&rctx->ctx, rstate);
 631 }
 632
 633 static void evergreen_cb(struct r600_pipe_context *rctx, struct r600_pipe_state *rstate,
 634                         const struct pipe_framebuffer_state *state, int cb)
 635 {
 636         struct r600_resource_texture *rtex;
 637         struct r600_resource *rbuffer;
 638         struct r600_surface *surf;
 639         unsigned level = state->cbufs[cb]->u.tex.level;
 640         unsigned pitch, slice;
 641         unsigned color_info;
 642         unsigned format, swap, ntype;
 643         unsigned offset;
 644         unsigned tile_type;
 645         const struct util_format_description *desc;
 646         struct r600_bo *bo[3];
 647
 648         surf = (struct r600_surface *)state->cbufs[cb];
 649         rtex = (struct r600_resource_texture*)state->cbufs[cb]->texture;
 650         rbuffer = &rtex->resource;
 651         bo[0] = rbuffer->bo;
 652         bo[1] = rbuffer->bo;
 653         bo[2] = rbuffer->bo;
 654
 655         /* XXX quite sure for dx10+ hw don't need any offset hacks */
 656         offset = r600_texture_get_offset((struct r600_resource_texture *)state->cbufs[cb]->texture,
 657                                          level, state->cbufs[cb]->u.tex.first_layer);
 658         pitch = rtex->pitch_in_pixels[level] / 8 - 1;
 659         slice = rtex->pitch_in_pixels[level] * surf->aligned_height / 64 - 1;
 660         ntype = 0;
 661         desc = util_format_description(rtex->resource.base.b.format);
 662         if (desc->colorspace == UTIL_FORMAT_COLORSPACE_SRGB)
 663                 ntype = V_028C70_NUMBER_SRGB;
 664
 665         format = r600_translate_colorformat(rtex->resource.base.b.format);
 666         swap = r600_translate_colorswap(rtex->resource.base.b.format);
 667         color_info = S_028C70_FORMAT(format) |
 668                 S_028C70_COMP_SWAP(swap) |
 669                 S_028C70_ARRAY_MODE(rtex->array_mode[level]) |
 670                 S_028C70_BLEND_CLAMP(1) |
 671                 S_028C70_NUMBER_TYPE(ntype);
 672         if (desc->colorspace != UTIL_FORMAT_COLORSPACE_ZS)
 673                 color_info |= S_028C70_SOURCE_FORMAT(1);
 674
 675         if (rtex->tiled) {
 676                 tile_type = rtex->tile_type;
 677         } else /* workaround for linear buffers */
 678                 tile_type = 1;
 679
 680         /* FIXME handle enabling of CB beyond BASE8 which has different offset */
 681         r600_pipe_state_add_reg(rstate,
 682                                 R_028C60_CB_COLOR0_BASE + cb * 0x3C,
 683                                 (offset +  r600_bo_offset(bo[0])) >> 8, 0xFFFFFFFF, bo[0]);
 684         r600_pipe_state_add_reg(rstate,
 685                                 R_028C78_CB_COLOR0_DIM + cb * 0x3C,
 686                                 0x0, 0xFFFFFFFF, NULL);
 687         r600_pipe_state_add_reg(rstate,
 688                                 R_028C70_CB_COLOR0_INFO + cb * 0x3C,
 689                                 color_info, 0xFFFFFFFF, bo[0]);
 690         r600_pipe_state_add_reg(rstate,
 691                                 R_028C64_CB_COLOR0_PITCH + cb * 0x3C,
 692                                 S_028C64_PITCH_TILE_MAX(pitch),
 693                                 0xFFFFFFFF, NULL);
 694         r600_pipe_state_add_reg(rstate,
 695                                 R_028C68_CB_COLOR0_SLICE + cb * 0x3C,
 696                                 S_028C68_SLICE_TILE_MAX(slice),
 697                                 0xFFFFFFFF, NULL);
 698         r600_pipe_state_add_reg(rstate,
 699                                 R_028C6C_CB_COLOR0_VIEW + cb * 0x3C,
 700                                 0x00000000, 0xFFFFFFFF, NULL);
 701         r600_pipe_state_add_reg(rstate,
 702                                 R_028C74_CB_COLOR0_ATTRIB + cb * 0x3C,
 703                                 S_028C74_NON_DISP_TILING_ORDER(tile_type),
 704                                 0xFFFFFFFF, bo[0]);
 705 }
 706
 707 static void evergreen_db(struct r600_pipe_context *rctx, struct r600_pipe_state *rstate,
 708                         const struct pipe_framebuffer_state *state)
 709 {
 710         struct r600_resource_texture *rtex;
 711         struct r600_resource *rbuffer;
 712         struct r600_surface *surf;
 713         unsigned level;
 714         unsigned pitch, slice, format, stencil_format;
 715         unsigned offset;
 716
 717         if (state->zsbuf == NULL)
 718                 return;
 719
 720         level = state->zsbuf->u.tex.level;
 721
 722         surf = (struct r600_surface *)state->zsbuf;
 723         rtex = (struct r600_resource_texture*)state->zsbuf->texture;
 724         rtex->tile_type = 1;
 725         rbuffer = &rtex->resource;
 726
 727         /* XXX quite sure for dx10+ hw don't need any offset hacks */
 728         offset = r600_texture_get_offset((struct r600_resource_texture *)state->zsbuf->texture,
 729                                          level, state->zsbuf->u.tex.first_layer);
 730         pitch = rtex->pitch_in_pixels[level] / 8 - 1;
 731         slice = rtex->pitch_in_pixels[level] * surf->aligned_height / 64 - 1;
 732         format = r600_translate_dbformat(state->zsbuf->texture->format);
 733         stencil_format = r600_translate_stencilformat(state->zsbuf->texture->format);
 734
 735         r600_pipe_state_add_reg(rstate, R_028048_DB_Z_READ_BASE,
 736                                 (offset + r600_bo_offset(rbuffer->bo)) >> 8, 0xFFFFFFFF, rbuffer->bo);
 737         r600_pipe_state_add_reg(rstate, R_028050_DB_Z_WRITE_BASE,
 738                                 (offset  + r600_bo_offset(rbuffer->bo)) >> 8, 0xFFFFFFFF, rbuffer->bo);
 739
 740         if (stencil_format) {
 741                 uint32_t stencil_offset;
 742
 743                 stencil_offset = ((surf->aligned_height * rtex->pitch_in_bytes[level]) + 255) & ~255;
 744                 r600_pipe_state_add_reg(rstate, R_02804C_DB_STENCIL_READ_BASE,
 745                                         (offset + stencil_offset + r600_bo_offset(rbuffer->bo)) >> 8, 0xFFFFFFFF, rbuffer->bo);
 746                 r600_pipe_state_add_reg(rstate, R_028054_DB_STENCIL_WRITE_BASE,
 747                                         (offset + stencil_offset + r600_bo_offset(rbuffer->bo)) >> 8, 0xFFFFFFFF, rbuffer->bo);
 748         }
 749
 750         r600_pipe_state_add_reg(rstate, R_028008_DB_DEPTH_VIEW, 0x00000000, 0xFFFFFFFF, NULL);
 751         r600_pipe_state_add_reg(rstate, R_028044_DB_STENCIL_INFO,
 752                                 S_028044_FORMAT(stencil_format), 0xFFFFFFFF, rbuffer->bo);
 753
 754         r600_pipe_state_add_reg(rstate, R_028040_DB_Z_INFO,
 755                                 S_028040_ARRAY_MODE(rtex->array_mode[level]) | S_028040_FORMAT(format),
 756                                 0xFFFFFFFF, rbuffer->bo);
 757         r600_pipe_state_add_reg(rstate, R_028058_DB_DEPTH_SIZE,
 758                                 S_028058_PITCH_TILE_MAX(pitch),
 759                                 0xFFFFFFFF, NULL);
 760         r600_pipe_state_add_reg(rstate, R_02805C_DB_DEPTH_SLICE,
 761                                 S_02805C_SLICE_TILE_MAX(slice),
 762                                 0xFFFFFFFF, NULL);
 763 }
 764
 765 static void evergreen_set_framebuffer_state(struct pipe_context *ctx,
 766                                         const struct pipe_framebuffer_state *state)
 767 {
 768         struct r600_pipe_context *rctx = (struct r600_pipe_context *)ctx;
 769         struct r600_pipe_state *rstate = CALLOC_STRUCT(r600_pipe_state);
 770         u32 shader_mask, tl, br, target_mask;
 771
 772         if (rstate == NULL)
 773                 return;
 774
 775         /* unreference old buffer and reference new one */
 776         rstate->id = R600_PIPE_STATE_FRAMEBUFFER;
 777
 778         util_copy_framebuffer_state(&rctx->framebuffer, state);
 779
 780         /* build states */
 781         for (int i = 0; i < state->nr_cbufs; i++) {
 782                 evergreen_cb(rctx, rstate, state, i);
 783         }
 784         if (state->zsbuf) {
 785                 evergreen_db(rctx, rstate, state);
 786         }
 787
 788         target_mask = 0x00000000;
 789         target_mask = 0xFFFFFFFF;
 790         shader_mask = 0;
 791         for (int i = 0; i < state->nr_cbufs; i++) {
 792                 target_mask ^= 0xf << (i * 4);
 793                 shader_mask |= 0xf << (i * 4);
 794         }
 795         tl = S_028240_TL_X(0) | S_028240_TL_Y(0);
 796         br = S_028244_BR_X(state->width) | S_028244_BR_Y(state->height);
 797
 798         r600_pipe_state_add_reg(rstate,
 799                                 R_028240_PA_SC_GENERIC_SCISSOR_TL, tl,
 800                                 0xFFFFFFFF, NULL);
 801         r600_pipe_state_add_reg(rstate,
 802                                 R_028244_PA_SC_GENERIC_SCISSOR_BR, br,
 803                                 0xFFFFFFFF, NULL);
 804         r600_pipe_state_add_reg(rstate,
 805                                 R_028250_PA_SC_VPORT_SCISSOR_0_TL, tl,
 806                                 0xFFFFFFFF, NULL);
 807         r600_pipe_state_add_reg(rstate,
 808                                 R_028254_PA_SC_VPORT_SCISSOR_0_BR, br,
 809                                 0xFFFFFFFF, NULL);
 810         r600_pipe_state_add_reg(rstate,
 811                                 R_028030_PA_SC_SCREEN_SCISSOR_TL, tl,
 812                                 0xFFFFFFFF, NULL);
 813         r600_pipe_state_add_reg(rstate,
 814                                 R_028034_PA_SC_SCREEN_SCISSOR_BR, br,
 815                                 0xFFFFFFFF, NULL);
 816         r600_pipe_state_add_reg(rstate,
 817                                 R_028204_PA_SC_WINDOW_SCISSOR_TL, tl,
 818                                 0xFFFFFFFF, NULL);
 819         r600_pipe_state_add_reg(rstate,
 820                                 R_028208_PA_SC_WINDOW_SCISSOR_BR, br,
 821                                 0xFFFFFFFF, NULL);
 822         r600_pipe_state_add_reg(rstate,
 823                                 R_028200_PA_SC_WINDOW_OFFSET, 0x00000000,
 824                                 0xFFFFFFFF, NULL);
 825         r600_pipe_state_add_reg(rstate,
 826                                 R_028230_PA_SC_EDGERULE, 0xAAAAAAAA,
 827                                 0xFFFFFFFF, NULL);
 828
 829         r600_pipe_state_add_reg(rstate, R_028238_CB_TARGET_MASK,
 830                                 0x00000000, target_mask, NULL);
 831         r600_pipe_state_add_reg(rstate, R_02823C_CB_SHADER_MASK,
 832                                 shader_mask, 0xFFFFFFFF, NULL);
 833         r600_pipe_state_add_reg(rstate, R_028C04_PA_SC_AA_CONFIG,
 834                                 0x00000000, 0xFFFFFFFF, NULL);
 835         r600_pipe_state_add_reg(rstate, R_028C1C_PA_SC_AA_SAMPLE_LOCS_MCTX,
 836                                 0x00000000, 0xFFFFFFFF, NULL);
 837
 838         free(rctx->states[R600_PIPE_STATE_FRAMEBUFFER]);
 839         rctx->states[R600_PIPE_STATE_FRAMEBUFFER] = rstate;
 840         r600_context_pipe_state_set(&rctx->ctx, rstate);
 841
 842         if (state->zsbuf) {
 843                 evergreen_polygon_offset_update(rctx);
 844         }
 845 }
 846
 847 void evergreen_init_state_functions(struct r600_pipe_context *rctx)
 848 {
 849         rctx->context.create_blend_state = evergreen_create_blend_state;
 850         rctx->context.create_depth_stencil_alpha_state = evergreen_create_dsa_state;
 851         rctx->context.create_fs_state = r600_create_shader_state;
 852         rctx->context.create_rasterizer_state = evergreen_create_rs_state;
 853         rctx->context.create_sampler_state = evergreen_create_sampler_state;
 854         rctx->context.create_sampler_view = evergreen_create_sampler_view;
 855         rctx->context.create_vertex_elements_state = r600_create_vertex_elements;
 856         rctx->context.create_vs_state = r600_create_shader_state;
 857         rctx->context.bind_blend_state = r600_bind_blend_state;
 858         rctx->context.bind_depth_stencil_alpha_state = r600_bind_state;
 859         rctx->context.bind_fragment_sampler_states = evergreen_bind_ps_sampler;
 860         rctx->context.bind_fs_state = r600_bind_ps_shader;
 861         rctx->context.bind_rasterizer_state = r600_bind_rs_state;
 862         rctx->context.bind_vertex_elements_state = r600_bind_vertex_elements;
 863         rctx->context.bind_vertex_sampler_states = evergreen_bind_vs_sampler;
 864         rctx->context.bind_vs_state = r600_bind_vs_shader;
 865         rctx->context.delete_blend_state = r600_delete_state;
 866         rctx->context.delete_depth_stencil_alpha_state = r600_delete_state;
 867         rctx->context.delete_fs_state = r600_delete_ps_shader;
 868         rctx->context.delete_rasterizer_state = r600_delete_rs_state;
 869         rctx->context.delete_sampler_state = r600_delete_state;
 870         rctx->context.delete_vertex_elements_state = r600_delete_vertex_element;
 871         rctx->context.delete_vs_state = r600_delete_vs_shader;
 872         rctx->context.set_blend_color = evergreen_set_blend_color;
 873         rctx->context.set_clip_state = evergreen_set_clip_state;
 874         rctx->context.set_constant_buffer = r600_set_constant_buffer;
 875         rctx->context.set_fragment_sampler_views = evergreen_set_ps_sampler_view;
 876         rctx->context.set_framebuffer_state = evergreen_set_framebuffer_state;
 877         rctx->context.set_polygon_stipple = evergreen_set_polygon_stipple;
 878         rctx->context.set_sample_mask = evergreen_set_sample_mask;
 879         rctx->context.set_scissor_state = evergreen_set_scissor_state;
 880         rctx->context.set_stencil_ref = evergreen_set_stencil_ref;
 881         rctx->context.set_vertex_buffers = r600_set_vertex_buffers;
 882         rctx->context.set_index_buffer = r600_set_index_buffer;
 883         rctx->context.set_vertex_sampler_views = evergreen_set_vs_sampler_view;
 884         rctx->context.set_viewport_state = evergreen_set_viewport_state;
 885         rctx->context.sampler_view_destroy = r600_sampler_view_destroy;
 886 }
 887
 888 void evergreen_init_config(struct r600_pipe_context *rctx)
 889 {
 890         struct r600_pipe_state *rstate = &rctx->config;
 891         int ps_prio;
 892         int vs_prio;
 893         int gs_prio;
 894         int es_prio;
 895         int hs_prio, cs_prio, ls_prio;
 896         int num_ps_gprs;
 897         int num_vs_gprs;
 898         int num_gs_gprs;
 899         int num_es_gprs;
 900         int num_hs_gprs;
 901         int num_ls_gprs;
 902         int num_temp_gprs;
 903         int num_ps_threads;
 904         int num_vs_threads;
 905         int num_gs_threads;
 906         int num_es_threads;
 907         int num_hs_threads;
 908         int num_ls_threads;
 909         int num_ps_stack_entries;
 910         int num_vs_stack_entries;
 911         int num_gs_stack_entries;
 912         int num_es_stack_entries;
 913         int num_hs_stack_entries;
 914         int num_ls_stack_entries;
 915         enum radeon_family family;
 916         unsigned tmp;
 917
 918         family = r600_get_family(rctx->radeon);
 919         ps_prio = 0;
 920         vs_prio = 1;
 921         gs_prio = 2;
 922         es_prio = 3;
 923         hs_prio = 0;
 924         ls_prio = 0;
 925         cs_prio = 0;
 926
 927         switch (family) {
 928         case CHIP_CEDAR:
 929         default:
 930                 num_ps_gprs = 93;
 931                 num_vs_gprs = 46;
 932                 num_temp_gprs = 4;
 933                 num_gs_gprs = 31;
 934                 num_es_gprs = 31;
 935                 num_hs_gprs = 23;
 936                 num_ls_gprs = 23;
 937                 num_ps_threads = 96;
 938                 num_vs_threads = 16;
 939                 num_gs_threads = 16;
 940                 num_es_threads = 16;
 941                 num_hs_threads = 16;
 942                 num_ls_threads = 16;
 943                 num_ps_stack_entries = 42;
 944                 num_vs_stack_entries = 42;
 945                 num_gs_stack_entries = 42;
 946                 num_es_stack_entries = 42;
 947                 num_hs_stack_entries = 42;
 948                 num_ls_stack_entries = 42;
 949                 break;
 950         case CHIP_REDWOOD:
 951                 num_ps_gprs = 93;
 952                 num_vs_gprs = 46;
 953                 num_temp_gprs = 4;
 954                 num_gs_gprs = 31;
 955                 num_es_gprs = 31;
 956                 num_hs_gprs = 23;
 957                 num_ls_gprs = 23;
 958                 num_ps_threads = 128;
 959                 num_vs_threads = 20;
 960                 num_gs_threads = 20;
 961                 num_es_threads = 20;
 962                 num_hs_threads = 20;
 963                 num_ls_threads = 20;
 964                 num_ps_stack_entries = 42;
 965                 num_vs_stack_entries = 42;
 966                 num_gs_stack_entries = 42;
 967                 num_es_stack_entries = 42;
 968                 num_hs_stack_entries = 42;
 969                 num_ls_stack_entries = 42;
 970                 break;
 971         case CHIP_JUNIPER:
 972                 num_ps_gprs = 93;
 973                 num_vs_gprs = 46;
 974                 num_temp_gprs = 4;
 975                 num_gs_gprs = 31;
 976                 num_es_gprs = 31;
 977                 num_hs_gprs = 23;
 978                 num_ls_gprs = 23;
 979                 num_ps_threads = 128;
 980                 num_vs_threads = 20;
 981                 num_gs_threads = 20;
 982                 num_es_threads = 20;
 983                 num_hs_threads = 20;
 984                 num_ls_threads = 20;
 985                 num_ps_stack_entries = 85;
 986                 num_vs_stack_entries = 85;
 987                 num_gs_stack_entries = 85;
 988                 num_es_stack_entries = 85;
 989                 num_hs_stack_entries = 85;
 990                 num_ls_stack_entries = 85;
 991                 break;
 992         case CHIP_CYPRESS:
 993         case CHIP_HEMLOCK:
 994                 num_ps_gprs = 93;
 995                 num_vs_gprs = 46;
 996                 num_temp_gprs = 4;
 997                 num_gs_gprs = 31;
 998                 num_es_gprs = 31;
 999                 num_hs_gprs = 23;
1000                 num_ls_gprs = 23;
1001                 num_ps_threads = 128;
1002                 num_vs_threads = 20;
1003                 num_gs_threads = 20;
1004                 num_es_threads = 20;
1005                 num_hs_threads = 20;
1006                 num_ls_threads = 20;
1007                 num_ps_stack_entries = 85;
1008                 num_vs_stack_entries = 85;
1009                 num_gs_stack_entries = 85;
1010                 num_es_stack_entries = 85;
1011                 num_hs_stack_entries = 85;
1012                 num_ls_stack_entries = 85;
1013                 break;
1014         case CHIP_PALM:
1015                 num_ps_gprs = 93;
1016                 num_vs_gprs = 46;
1017                 num_temp_gprs = 4;
1018                 num_gs_gprs = 31;
1019                 num_es_gprs = 31;
1020                 num_hs_gprs = 23;
1021                 num_ls_gprs = 23;
1022                 num_ps_threads = 96;
1023                 num_vs_threads = 16;
1024                 num_gs_threads = 16;
1025                 num_es_threads = 16;
1026                 num_hs_threads = 16;
1027                 num_ls_threads = 16;
1028                 num_ps_stack_entries = 42;
1029                 num_vs_stack_entries = 42;
1030                 num_gs_stack_entries = 42;
1031                 num_es_stack_entries = 42;
1032                 num_hs_stack_entries = 42;
1033                 num_ls_stack_entries = 42;
1034                 break;
1035         case CHIP_BARTS:
1036                 num_ps_gprs = 93;
1037                 num_vs_gprs = 46;
1038                 num_temp_gprs = 4;
1039                 num_gs_gprs = 31;
1040                 num_es_gprs = 31;
1041                 num_hs_gprs = 23;
1042                 num_ls_gprs = 23;
1043                 num_ps_threads = 128;
1044                 num_vs_threads = 20;
1045                 num_gs_threads = 20;
1046                 num_es_threads = 20;
1047                 num_hs_threads = 20;
1048                 num_ls_threads = 20;
1049                 num_ps_stack_entries = 85;
1050                 num_vs_stack_entries = 85;
1051                 num_gs_stack_entries = 85;
1052                 num_es_stack_entries = 85;
1053                 num_hs_stack_entries = 85;
1054                 num_ls_stack_entries = 85;
1055                 break;
1056         case CHIP_TURKS:
1057                 num_ps_gprs = 93;
1058                 num_vs_gprs = 46;
1059                 num_temp_gprs = 4;
1060                 num_gs_gprs = 31;
1061                 num_es_gprs = 31;
1062                 num_hs_gprs = 23;
1063                 num_ls_gprs = 23;
1064                 num_ps_threads = 128;
1065                 num_vs_threads = 20;
1066                 num_gs_threads = 20;
1067                 num_es_threads = 20;
1068                 num_hs_threads = 20;
1069                 num_ls_threads = 20;
1070                 num_ps_stack_entries = 42;
1071                 num_vs_stack_entries = 42;
1072                 num_gs_stack_entries = 42;
1073                 num_es_stack_entries = 42;
1074                 num_hs_stack_entries = 42;
1075                 num_ls_stack_entries = 42;
1076                 break;
1077         case CHIP_CAICOS:
1078                 num_ps_gprs = 93;
1079                 num_vs_gprs = 46;
1080                 num_temp_gprs = 4;
1081                 num_gs_gprs = 31;
1082                 num_es_gprs = 31;
1083                 num_hs_gprs = 23;
1084                 num_ls_gprs = 23;
1085                 num_ps_threads = 128;
1086                 num_vs_threads = 10;
1087                 num_gs_threads = 10;
1088                 num_es_threads = 10;
1089                 num_hs_threads = 10;
1090                 num_ls_threads = 10;
1091                 num_ps_stack_entries = 42;
1092                 num_vs_stack_entries = 42;
1093                 num_gs_stack_entries = 42;
1094                 num_es_stack_entries = 42;
1095                 num_hs_stack_entries = 42;
1096                 num_ls_stack_entries = 42;
1097                 break;
1098         }
1099
1100         tmp = 0x00000000;
1101         switch (family) {
1102         case CHIP_CEDAR:
1103         case CHIP_PALM:
1104         case CHIP_CAICOS:
1105                 break;
1106         default:
1107                 tmp |= S_008C00_VC_ENABLE(1);
1108                 break;
1109         }
1110         tmp |= S_008C00_EXPORT_SRC_C(1);
1111         tmp |= S_008C00_CS_PRIO(cs_prio);
1112         tmp |= S_008C00_LS_PRIO(ls_prio);
1113         tmp |= S_008C00_HS_PRIO(hs_prio);
1114         tmp |= S_008C00_PS_PRIO(ps_prio);
1115         tmp |= S_008C00_VS_PRIO(vs_prio);
1116         tmp |= S_008C00_GS_PRIO(gs_prio);
1117         tmp |= S_008C00_ES_PRIO(es_prio);
1118         r600_pipe_state_add_reg(rstate, R_008C00_SQ_CONFIG, tmp, 0xFFFFFFFF, NULL);
1119
1120         tmp = 0;
1121         tmp |= S_008C04_NUM_PS_GPRS(num_ps_gprs);
1122         tmp |= S_008C04_NUM_VS_GPRS(num_vs_gprs);
1123         tmp |= S_008C04_NUM_CLAUSE_TEMP_GPRS(num_temp_gprs);
1124         r600_pipe_state_add_reg(rstate, R_008C04_SQ_GPR_RESOURCE_MGMT_1, tmp, 0xFFFFFFFF, NULL);
1125
1126         tmp = 0;
1127         tmp |= S_008C08_NUM_GS_GPRS(num_gs_gprs);
1128         tmp |= S_008C08_NUM_ES_GPRS(num_es_gprs);
1129         r600_pipe_state_add_reg(rstate, R_008C08_SQ_GPR_RESOURCE_MGMT_2, tmp, 0xFFFFFFFF, NULL);
1130
1131         tmp = 0;
1132         tmp |= S_008C0C_NUM_HS_GPRS(num_hs_gprs);
1133         tmp |= S_008C0C_NUM_LS_GPRS(num_ls_gprs);
1134         r600_pipe_state_add_reg(rstate, R_008C0C_SQ_GPR_RESOURCE_MGMT_3, tmp, 0xFFFFFFFF, NULL);
1135
1136         tmp = 0;
1137         tmp |= S_008C18_NUM_PS_THREADS(num_ps_threads);
1138         tmp |= S_008C18_NUM_VS_THREADS(num_vs_threads);
1139         tmp |= S_008C18_NUM_GS_THREADS(num_gs_threads);
1140         tmp |= S_008C18_NUM_ES_THREADS(num_es_threads);
1141         r600_pipe_state_add_reg(rstate, R_008C18_SQ_THREAD_RESOURCE_MGMT_1, tmp, 0xFFFFFFFF, NULL);
1142
1143         tmp = 0;
1144         tmp |= S_008C1C_NUM_HS_THREADS(num_hs_threads);
1145         tmp |= S_008C1C_NUM_LS_THREADS(num_ls_threads);
1146         r600_pipe_state_add_reg(rstate, R_008C1C_SQ_THREAD_RESOURCE_MGMT_2, tmp, 0xFFFFFFFF, NULL);
1147
1148         tmp = 0;
1149         tmp |= S_008C20_NUM_PS_STACK_ENTRIES(num_ps_stack_entries);
1150         tmp |= S_008C20_NUM_VS_STACK_ENTRIES(num_vs_stack_entries);
1151         r600_pipe_state_add_reg(rstate, R_008C20_SQ_STACK_RESOURCE_MGMT_1, tmp, 0xFFFFFFFF, NULL);
1152
1153         tmp = 0;
1154         tmp |= S_008C24_NUM_GS_STACK_ENTRIES(num_gs_stack_entries);
1155         tmp |= S_008C24_NUM_ES_STACK_ENTRIES(num_es_stack_entries);
1156         r600_pipe_state_add_reg(rstate, R_008C24_SQ_STACK_RESOURCE_MGMT_2, tmp, 0xFFFFFFFF, NULL);
1157
1158         tmp = 0;
1159         tmp |= S_008C28_NUM_HS_STACK_ENTRIES(num_hs_stack_entries);
1160         tmp |= S_008C28_NUM_LS_STACK_ENTRIES(num_ls_stack_entries);
1161         r600_pipe_state_add_reg(rstate, R_008C28_SQ_STACK_RESOURCE_MGMT_3, tmp, 0xFFFFFFFF, NULL);
1162
1163         r600_pipe_state_add_reg(rstate, R_009100_SPI_CONFIG_CNTL, 0x0, 0xFFFFFFFF, NULL);
1164         r600_pipe_state_add_reg(rstate, R_00913C_SPI_CONFIG_CNTL_1, S_00913C_VTX_DONE_DELAY(4), 0xFFFFFFFF, NULL);
1165
1166 //      r600_pipe_state_add_reg(rstate, R_028350_SX_MISC, 0x0, 0xFFFFFFFF, NULL);
1167
1168 //      r600_pipe_state_add_reg(rstate, R_008D8C_SQ_DYN_GPR_CNTL_PS_FLUSH_REQ, 0x0, 0xFFFFFFFF, NULL);
1169         r600_pipe_state_add_reg(rstate, R_028A48_PA_SC_MODE_CNTL_0, 0x0, 0xFFFFFFFF, NULL);
1170         r600_pipe_state_add_reg(rstate, R_028A4C_PA_SC_MODE_CNTL_1, 0x0, 0xFFFFFFFF, NULL);
1171
1172         r600_pipe_state_add_reg(rstate, R_028900_SQ_ESGS_RING_ITEMSIZE, 0x0, 0xFFFFFFFF, NULL);
1173         r600_pipe_state_add_reg(rstate, R_028904_SQ_GSVS_RING_ITEMSIZE, 0x0, 0xFFFFFFFF, NULL);
1174         r600_pipe_state_add_reg(rstate, R_028908_SQ_ESTMP_RING_ITEMSIZE, 0x0, 0xFFFFFFFF, NULL);
1175         r600_pipe_state_add_reg(rstate, R_02890C_SQ_GSTMP_RING_ITEMSIZE, 0x0, 0xFFFFFFFF, NULL);
1176         r600_pipe_state_add_reg(rstate, R_028910_SQ_VSTMP_RING_ITEMSIZE, 0x0, 0xFFFFFFFF, NULL);
1177         r600_pipe_state_add_reg(rstate, R_028914_SQ_PSTMP_RING_ITEMSIZE, 0x0, 0xFFFFFFFF, NULL);
1178
1179         r600_pipe_state_add_reg(rstate, R_02891C_SQ_GS_VERT_ITEMSIZE, 0x0, 0xFFFFFFFF, NULL);
1180         r600_pipe_state_add_reg(rstate, R_028920_SQ_GS_VERT_ITEMSIZE_1, 0x0, 0xFFFFFFFF, NULL);
1181         r600_pipe_state_add_reg(rstate, R_028924_SQ_GS_VERT_ITEMSIZE_2, 0x0, 0xFFFFFFFF, NULL);
1182         r600_pipe_state_add_reg(rstate, R_028928_SQ_GS_VERT_ITEMSIZE_3, 0x0, 0xFFFFFFFF, NULL);
1183
1184         r600_pipe_state_add_reg(rstate, R_028A10_VGT_OUTPUT_PATH_CNTL, 0x0, 0xFFFFFFFF, NULL);
1185         r600_pipe_state_add_reg(rstate, R_028A14_VGT_HOS_CNTL, 0x0, 0xFFFFFFFF, NULL);
1186         r600_pipe_state_add_reg(rstate, R_028A18_VGT_HOS_MAX_TESS_LEVEL, 0x0, 0xFFFFFFFF, NULL);
1187         r600_pipe_state_add_reg(rstate, R_028A1C_VGT_HOS_MIN_TESS_LEVEL, 0x0, 0xFFFFFFFF, NULL);
1188         r600_pipe_state_add_reg(rstate, R_028A20_VGT_HOS_REUSE_DEPTH, 0x0, 0xFFFFFFFF, NULL);
1189         r600_pipe_state_add_reg(rstate, R_028A24_VGT_GROUP_PRIM_TYPE, 0x0, 0xFFFFFFFF, NULL);
1190         r600_pipe_state_add_reg(rstate, R_028A28_VGT_GROUP_FIRST_DECR, 0x0, 0xFFFFFFFF, NULL);
1191         r600_pipe_state_add_reg(rstate, R_028A2C_VGT_GROUP_DECR, 0x0, 0xFFFFFFFF, NULL);
1192         r600_pipe_state_add_reg(rstate, R_028A30_VGT_GROUP_VECT_0_CNTL, 0x0, 0xFFFFFFFF, NULL);
1193         r600_pipe_state_add_reg(rstate, R_028A34_VGT_GROUP_VECT_1_CNTL, 0x0, 0xFFFFFFFF, NULL);
1194         r600_pipe_state_add_reg(rstate, R_028A38_VGT_GROUP_VECT_0_FMT_CNTL, 0x0, 0xFFFFFFFF, NULL);
1195         r600_pipe_state_add_reg(rstate, R_028A3C_VGT_GROUP_VECT_1_FMT_CNTL, 0x0, 0xFFFFFFFF, NULL);
1196         r600_pipe_state_add_reg(rstate, R_028A40_VGT_GS_MODE, 0x0, 0xFFFFFFFF, NULL);
1197         r600_pipe_state_add_reg(rstate, R_028B94_VGT_STRMOUT_CONFIG, 0x0, 0xFFFFFFFF, NULL);
1198         r600_pipe_state_add_reg(rstate, R_028B98_VGT_STRMOUT_BUFFER_CONFIG, 0x0, 0xFFFFFFFF, NULL);
1199         r600_pipe_state_add_reg(rstate, R_028AB4_VGT_REUSE_OFF, 0x00000000, 0xFFFFFFFF, NULL);
1200         r600_pipe_state_add_reg(rstate, R_028AB8_VGT_VTX_CNT_EN, 0x0, 0xFFFFFFFF, NULL);
1201         r600_pipe_state_add_reg(rstate, R_008A14_PA_CL_ENHANCE, (3 << 1) | 1, 0xFFFFFFFF, NULL);
1202
1203         r600_pipe_state_add_reg(rstate, R_028380_SQ_VTX_SEMANTIC_0, 0x0, 0xFFFFFFFF, NULL);
1204         r600_pipe_state_add_reg(rstate, R_028384_SQ_VTX_SEMANTIC_1, 0x0, 0xFFFFFFFF, NULL);
1205         r600_pipe_state_add_reg(rstate, R_028388_SQ_VTX_SEMANTIC_2, 0x0, 0xFFFFFFFF, NULL);
1206         r600_pipe_state_add_reg(rstate, R_02838C_SQ_VTX_SEMANTIC_3, 0x0, 0xFFFFFFFF, NULL);
1207         r600_pipe_state_add_reg(rstate, R_028390_SQ_VTX_SEMANTIC_4, 0x0, 0xFFFFFFFF, NULL);
1208         r600_pipe_state_add_reg(rstate, R_028394_SQ_VTX_SEMANTIC_5, 0x0, 0xFFFFFFFF, NULL);
1209         r600_pipe_state_add_reg(rstate, R_028398_SQ_VTX_SEMANTIC_6, 0x0, 0xFFFFFFFF, NULL);
1210         r600_pipe_state_add_reg(rstate, R_02839C_SQ_VTX_SEMANTIC_7, 0x0, 0xFFFFFFFF, NULL);
1211         r600_pipe_state_add_reg(rstate, R_0283A0_SQ_VTX_SEMANTIC_8, 0x0, 0xFFFFFFFF, NULL);
1212         r600_pipe_state_add_reg(rstate, R_0283A4_SQ_VTX_SEMANTIC_9, 0x0, 0xFFFFFFFF, NULL);
1213         r600_pipe_state_add_reg(rstate, R_0283A8_SQ_VTX_SEMANTIC_10, 0x0, 0xFFFFFFFF, NULL);
1214         r600_pipe_state_add_reg(rstate, R_0283AC_SQ_VTX_SEMANTIC_11, 0x0, 0xFFFFFFFF, NULL);
1215         r600_pipe_state_add_reg(rstate, R_0283B0_SQ_VTX_SEMANTIC_12, 0x0, 0xFFFFFFFF, NULL);
1216         r600_pipe_state_add_reg(rstate, R_0283B4_SQ_VTX_SEMANTIC_13, 0x0, 0xFFFFFFFF, NULL);
1217         r600_pipe_state_add_reg(rstate, R_0283B8_SQ_VTX_SEMANTIC_14, 0x0, 0xFFFFFFFF, NULL);
1218         r600_pipe_state_add_reg(rstate, R_0283BC_SQ_VTX_SEMANTIC_15, 0x0, 0xFFFFFFFF, NULL);
1219         r600_pipe_state_add_reg(rstate, R_0283C0_SQ_VTX_SEMANTIC_16, 0x0, 0xFFFFFFFF, NULL);
1220         r600_pipe_state_add_reg(rstate, R_0283C4_SQ_VTX_SEMANTIC_17, 0x0, 0xFFFFFFFF, NULL);
1221         r600_pipe_state_add_reg(rstate, R_0283C8_SQ_VTX_SEMANTIC_18, 0x0, 0xFFFFFFFF, NULL);
1222         r600_pipe_state_add_reg(rstate, R_0283CC_SQ_VTX_SEMANTIC_19, 0x0, 0xFFFFFFFF, NULL);
1223         r600_pipe_state_add_reg(rstate, R_0283D0_SQ_VTX_SEMANTIC_20, 0x0, 0xFFFFFFFF, NULL);
1224         r600_pipe_state_add_reg(rstate, R_0283D4_SQ_VTX_SEMANTIC_21, 0x0, 0xFFFFFFFF, NULL);
1225         r600_pipe_state_add_reg(rstate, R_0283D8_SQ_VTX_SEMANTIC_22, 0x0, 0xFFFFFFFF, NULL);
1226         r600_pipe_state_add_reg(rstate, R_0283DC_SQ_VTX_SEMANTIC_23, 0x0, 0xFFFFFFFF, NULL);
1227         r600_pipe_state_add_reg(rstate, R_0283E0_SQ_VTX_SEMANTIC_24, 0x0, 0xFFFFFFFF, NULL);
1228         r600_pipe_state_add_reg(rstate, R_0283E4_SQ_VTX_SEMANTIC_25, 0x0, 0xFFFFFFFF, NULL);
1229         r600_pipe_state_add_reg(rstate, R_0283E8_SQ_VTX_SEMANTIC_26, 0x0, 0xFFFFFFFF, NULL);
1230         r600_pipe_state_add_reg(rstate, R_0283EC_SQ_VTX_SEMANTIC_27, 0x0, 0xFFFFFFFF, NULL);
1231         r600_pipe_state_add_reg(rstate, R_0283F0_SQ_VTX_SEMANTIC_28, 0x0, 0xFFFFFFFF, NULL);
1232         r600_pipe_state_add_reg(rstate, R_0283F4_SQ_VTX_SEMANTIC_29, 0x0, 0xFFFFFFFF, NULL);
1233         r600_pipe_state_add_reg(rstate, R_0283F8_SQ_VTX_SEMANTIC_30, 0x0, 0xFFFFFFFF, NULL);
1234         r600_pipe_state_add_reg(rstate, R_0283FC_SQ_VTX_SEMANTIC_31, 0x0, 0xFFFFFFFF, NULL);
1235
1236         r600_pipe_state_add_reg(rstate, R_028810_PA_CL_CLIP_CNTL, 0x0, 0xFFFFFFFF, NULL);
1237
1238         r600_context_pipe_state_set(&rctx->ctx, rstate);
1239 }
1240
1241 void evergreen_polygon_offset_update(struct r600_pipe_context *rctx)
1242 {
1243         struct r600_pipe_state state;
1244
1245         state.id = R600_PIPE_STATE_POLYGON_OFFSET;
1246         state.nregs = 0;
1247         if (rctx->rasterizer && rctx->framebuffer.zsbuf) {
1248                 float offset_units = rctx->rasterizer->offset_units;
1249                 unsigned offset_db_fmt_cntl = 0, depth;
1250
1251                 switch (rctx->framebuffer.zsbuf->texture->format) {
1252                 case PIPE_FORMAT_Z24X8_UNORM:
1253                 case PIPE_FORMAT_Z24_UNORM_S8_USCALED:
1254                         depth = -24;
1255                         offset_units *= 2.0f;
1256                         break;
1257                 case PIPE_FORMAT_Z32_FLOAT:
1258                         depth = -23;
1259                         offset_units *= 1.0f;
1260                         offset_db_fmt_cntl |= S_028B78_POLY_OFFSET_DB_IS_FLOAT_FMT(1);
1261                         break;
1262                 case PIPE_FORMAT_Z16_UNORM:
1263                         depth = -16;
1264                         offset_units *= 4.0f;
1265                         break;
1266                 default:
1267                         return;
1268                 }
1269                 /* FIXME some of those reg can be computed with cso */
1270                 offset_db_fmt_cntl |= S_028B78_POLY_OFFSET_NEG_NUM_DB_BITS(depth);
1271                 r600_pipe_state_add_reg(&state,
1272                                 R_028B80_PA_SU_POLY_OFFSET_FRONT_SCALE,
1273                                 fui(rctx->rasterizer->offset_scale), 0xFFFFFFFF, NULL);
1274                 r600_pipe_state_add_reg(&state,
1275                                 R_028B84_PA_SU_POLY_OFFSET_FRONT_OFFSET,
1276                                 fui(offset_units), 0xFFFFFFFF, NULL);
1277                 r600_pipe_state_add_reg(&state,
1278                                 R_028B88_PA_SU_POLY_OFFSET_BACK_SCALE,
1279                                 fui(rctx->rasterizer->offset_scale), 0xFFFFFFFF, NULL);
1280                 r600_pipe_state_add_reg(&state,
1281                                 R_028B8C_PA_SU_POLY_OFFSET_BACK_OFFSET,
1282                                 fui(offset_units), 0xFFFFFFFF, NULL);
1283                 r600_pipe_state_add_reg(&state,
1284                                 R_028B78_PA_SU_POLY_OFFSET_DB_FMT_CNTL,
1285                                 offset_db_fmt_cntl, 0xFFFFFFFF, NULL);
1286                 r600_context_pipe_state_set(&rctx->ctx, &state);
1287         }
1288 }
1289
1290 void evergreen_pipe_shader_ps(struct pipe_context *ctx, struct r600_pipe_shader *shader)
1291 {
1292         struct r600_pipe_state *rstate = &shader->rstate;
1293         struct r600_shader *rshader = &shader->shader;
1294         unsigned i, exports_ps, num_cout, spi_ps_in_control_0, spi_input_z, spi_ps_in_control_1;
1295         int pos_index = -1, face_index = -1;
1296         int ninterp = 0;
1297         boolean have_linear = FALSE, have_centroid = FALSE, have_perspective = FALSE;
1298         unsigned spi_baryc_cntl;
1299
1300         rstate->nregs = 0;
1301
1302         for (i = 0; i < rshader->ninput; i++) {
1303                 /* evergreen NUM_INTERP only contains values interpolated into the LDS,
1304                    POSITION goes via GPRs from the SC so isn't counted */
1305                 if (rshader->input[i].name == TGSI_SEMANTIC_POSITION)
1306                         pos_index = i;
1307                 else if (rshader->input[i].name == TGSI_SEMANTIC_FACE)
1308                         face_index = i;
1309                 else {
1310                         if (rshader->input[i].interpolate == TGSI_INTERPOLATE_LINEAR ||
1311                             rshader->input[i].interpolate == TGSI_INTERPOLATE_PERSPECTIVE)
1312                                 ninterp++;
1313                         if (rshader->input[i].interpolate == TGSI_INTERPOLATE_LINEAR)
1314                                 have_linear = TRUE;
1315                         if (rshader->input[i].interpolate == TGSI_INTERPOLATE_PERSPECTIVE)
1316                                 have_perspective = TRUE;
1317                         if (rshader->input[i].centroid)
1318                                 have_centroid = TRUE;
1319                 }
1320         }
1321         for (i = 0; i < rshader->noutput; i++) {
1322                 if (rshader->output[i].name == TGSI_SEMANTIC_POSITION)
1323                         r600_pipe_state_add_reg(rstate,
1324                                                 R_02880C_DB_SHADER_CONTROL,
1325                                                 S_02880C_Z_EXPORT_ENABLE(1),
1326                                                 S_02880C_Z_EXPORT_ENABLE(1), NULL);
1327                 if (rshader->output[i].name == TGSI_SEMANTIC_STENCIL)
1328                         r600_pipe_state_add_reg(rstate,
1329                                                 R_02880C_DB_SHADER_CONTROL,
1330                                                 S_02880C_STENCIL_EXPORT_ENABLE(1),
1331                                                 S_02880C_STENCIL_EXPORT_ENABLE(1), NULL);
1332         }
1333
1334         exports_ps = 0;
1335         num_cout = 0;
1336         for (i = 0; i < rshader->noutput; i++) {
1337                 if (rshader->output[i].name == TGSI_SEMANTIC_POSITION ||
1338                     rshader->output[i].name == TGSI_SEMANTIC_STENCIL)
1339                         exports_ps |= 1;
1340                 else if (rshader->output[i].name == TGSI_SEMANTIC_COLOR) {
1341                         num_cout++;
1342                 }
1343         }
1344         exports_ps |= S_02884C_EXPORT_COLORS(num_cout);
1345         if (!exports_ps) {
1346                 /* always at least export 1 component per pixel */
1347                 exports_ps = 2;
1348         }
1349
1350         if (ninterp == 0) {
1351                 ninterp = 1;
1352                 have_perspective = TRUE;
1353         }
1354
1355         spi_ps_in_control_0 = S_0286CC_NUM_INTERP(ninterp) |
1356                               S_0286CC_PERSP_GRADIENT_ENA(have_perspective) |
1357                               S_0286CC_LINEAR_GRADIENT_ENA(have_linear);
1358         spi_input_z = 0;
1359         if (pos_index != -1) {
1360                 spi_ps_in_control_0 |=  S_0286CC_POSITION_ENA(1) |
1361                         S_0286CC_POSITION_CENTROID(rshader->input[pos_index].centroid) |
1362                         S_0286CC_POSITION_ADDR(rshader->input[pos_index].gpr);
1363                 spi_input_z |= 1;
1364         }
1365
1366         spi_ps_in_control_1 = 0;
1367         if (face_index != -1) {
1368                 spi_ps_in_control_1 |= S_0286D0_FRONT_FACE_ENA(1) |
1369                         S_0286D0_FRONT_FACE_ADDR(rshader->input[face_index].gpr);
1370         }
1371
1372         spi_baryc_cntl = 0;
1373         if (have_perspective)
1374                 spi_baryc_cntl |= S_0286E0_PERSP_CENTER_ENA(1) |
1375                                   S_0286E0_PERSP_CENTROID_ENA(have_centroid);
1376         if (have_linear)
1377                 spi_baryc_cntl |= S_0286E0_LINEAR_CENTER_ENA(1) |
1378                                   S_0286E0_LINEAR_CENTROID_ENA(have_centroid);
1379
1380         r600_pipe_state_add_reg(rstate, R_0286CC_SPI_PS_IN_CONTROL_0,
1381                                 spi_ps_in_control_0, 0xFFFFFFFF, NULL);
1382         r600_pipe_state_add_reg(rstate, R_0286D0_SPI_PS_IN_CONTROL_1,
1383                                 spi_ps_in_control_1, 0xFFFFFFFF, NULL);
1384         r600_pipe_state_add_reg(rstate, R_0286E4_SPI_PS_IN_CONTROL_2,
1385                                 0, 0xFFFFFFFF, NULL);
1386         r600_pipe_state_add_reg(rstate, R_0286D8_SPI_INPUT_Z, spi_input_z, 0xFFFFFFFF, NULL);
1387         r600_pipe_state_add_reg(rstate,
1388                                 R_0286E0_SPI_BARYC_CNTL,
1389                                 spi_baryc_cntl,
1390                                 0xFFFFFFFF, NULL);
1391
1392         r600_pipe_state_add_reg(rstate,
1393                                 R_028840_SQ_PGM_START_PS,
1394                                 (r600_bo_offset(shader->bo)) >> 8, 0xFFFFFFFF, shader->bo);
1395         r600_pipe_state_add_reg(rstate,
1396                                 R_028844_SQ_PGM_RESOURCES_PS,
1397                                 S_028844_NUM_GPRS(rshader->bc.ngpr) |
1398                                 S_028844_PRIME_CACHE_ON_DRAW(1) |
1399                                 S_028844_STACK_SIZE(rshader->bc.nstack),
1400                                 0xFFFFFFFF, NULL);
1401         r600_pipe_state_add_reg(rstate,
1402                                 R_028848_SQ_PGM_RESOURCES_2_PS,
1403                                 0x0, 0xFFFFFFFF, NULL);
1404         r600_pipe_state_add_reg(rstate,
1405                                 R_02884C_SQ_PGM_EXPORTS_PS,
1406                                 exports_ps, 0xFFFFFFFF, NULL);
1407
1408         if (rshader->uses_kill) {
1409                 /* only set some bits here, the other bits are set in the dsa state */
1410                 r600_pipe_state_add_reg(rstate,
1411                                         R_02880C_DB_SHADER_CONTROL,
1412                                         S_02880C_KILL_ENABLE(1),
1413                                         S_02880C_KILL_ENABLE(1), NULL);
1414         }
1415
1416         r600_pipe_state_add_reg(rstate,
1417                                 R_03A200_SQ_LOOP_CONST_0, 0x01000FFF,
1418                                 0xFFFFFFFF, NULL);
1419 }
1420
1421 void evergreen_pipe_shader_vs(struct pipe_context *ctx, struct r600_pipe_shader *shader)
1422 {
1423         struct r600_pipe_state *rstate = &shader->rstate;
1424         struct r600_shader *rshader = &shader->shader;
1425         unsigned spi_vs_out_id[10];
1426         unsigned i, tmp;
1427
1428         /* clear previous register */
1429         rstate->nregs = 0;
1430
1431         /* so far never got proper semantic id from tgsi */
1432         for (i = 0; i < 10; i++) {
1433                 spi_vs_out_id[i] = 0;
1434         }
1435         for (i = 0; i < 32; i++) {
1436                 tmp = i << ((i & 3) * 8);
1437                 spi_vs_out_id[i / 4] |= tmp;
1438         }
1439         for (i = 0; i < 10; i++) {
1440                 r600_pipe_state_add_reg(rstate,
1441                                         R_02861C_SPI_VS_OUT_ID_0 + i * 4,
1442                                         spi_vs_out_id[i], 0xFFFFFFFF, NULL);
1443         }
1444
1445         r600_pipe_state_add_reg(rstate,
1446                         R_0286C4_SPI_VS_OUT_CONFIG,
1447                         S_0286C4_VS_EXPORT_COUNT(rshader->noutput - 2),
1448                         0xFFFFFFFF, NULL);
1449         r600_pipe_state_add_reg(rstate,
1450                         R_028860_SQ_PGM_RESOURCES_VS,
1451                         S_028860_NUM_GPRS(rshader->bc.ngpr) |
1452                         S_028860_STACK_SIZE(rshader->bc.nstack),
1453                         0xFFFFFFFF, NULL);
1454         r600_pipe_state_add_reg(rstate,
1455                                 R_028864_SQ_PGM_RESOURCES_2_VS,
1456                                 0x0, 0xFFFFFFFF, NULL);
1457         r600_pipe_state_add_reg(rstate,
1458                         R_02885C_SQ_PGM_START_VS,
1459                         (r600_bo_offset(shader->bo)) >> 8, 0xFFFFFFFF, shader->bo);
1460
1461         r600_pipe_state_add_reg(rstate,
1462                                 R_03A200_SQ_LOOP_CONST_0 + (32 * 4), 0x01000FFF,
1463                                 0xFFFFFFFF, NULL);
1464 }
1465
1466 void *evergreen_create_db_flush_dsa(struct r600_pipe_context *rctx)
1467 {
1468         struct pipe_depth_stencil_alpha_state dsa;
1469         struct r600_pipe_state *rstate;
1470
1471         memset(&dsa, 0, sizeof(dsa));
1472
1473         rstate = rctx->context.create_depth_stencil_alpha_state(&rctx->context, &dsa);
1474         r600_pipe_state_add_reg(rstate,
1475                                 R_02880C_DB_SHADER_CONTROL,
1476                                 0x0,
1477                                 S_02880C_DUAL_EXPORT_ENABLE(1), NULL);
1478         r600_pipe_state_add_reg(rstate,
1479                                 R_028000_DB_RENDER_CONTROL,
1480                                 S_028000_DEPTH_COPY_ENABLE(1) |
1481                                 S_028000_STENCIL_COPY_ENABLE(1) |
1482                                 S_028000_COPY_CENTROID(1),
1483                                 S_028000_DEPTH_COPY_ENABLE(1) |
1484                                 S_028000_STENCIL_COPY_ENABLE(1) |
1485                                 S_028000_COPY_CENTROID(1), NULL);
1486         return rstate;
1487 }
1488
1489 void evergreen_pipe_add_vertex_attrib(struct r600_pipe_context *rctx,
1490                                       struct r600_pipe_state *rstate,
1491                                       unsigned index,
1492                                       struct r600_resource *rbuffer,
1493                                       unsigned offset, unsigned stride)
1494 {
1495         r600_pipe_state_add_reg(rstate, R_030000_RESOURCE0_WORD0,
1496                                 offset, 0xFFFFFFFF, rbuffer->bo);
1497         r600_pipe_state_add_reg(rstate, R_030004_RESOURCE0_WORD1,
1498                                 rbuffer->bo_size - offset - 1, 0xFFFFFFFF, NULL);
1499         r600_pipe_state_add_reg(rstate, R_030008_RESOURCE0_WORD2,
1500                                 S_030008_STRIDE(stride),
1501                                 0xFFFFFFFF, NULL);
1502         r600_pipe_state_add_reg(rstate, R_03000C_RESOURCE0_WORD3,
1503                                 S_03000C_DST_SEL_X(V_03000C_SQ_SEL_X) |
1504                                 S_03000C_DST_SEL_Y(V_03000C_SQ_SEL_Y) |
1505                                 S_03000C_DST_SEL_Z(V_03000C_SQ_SEL_Z) |
1506                                 S_03000C_DST_SEL_W(V_03000C_SQ_SEL_W),
1507                                 0xFFFFFFFF, NULL);
1508         r600_pipe_state_add_reg(rstate, R_030010_RESOURCE0_WORD4,
1509                                 0x00000000, 0xFFFFFFFF, NULL);
1510         r600_pipe_state_add_reg(rstate, R_030014_RESOURCE0_WORD5,
1511                                 0x00000000, 0xFFFFFFFF, NULL);
1512         r600_pipe_state_add_reg(rstate, R_030018_RESOURCE0_WORD6,
1513                                 0x00000000, 0xFFFFFFFF, NULL);
1514         r600_pipe_state_add_reg(rstate, R_03001C_RESOURCE0_WORD7,
1515                                 0xC0000000, 0xFFFFFFFF, NULL);
1516         evergreen_context_pipe_state_set_fs_resource(&rctx->ctx, rstate, index);
1517 }