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r600g: enable instance cnt register with new enough kernel
[mesa.git] / src / gallium / drivers / r600 / evergreen_state.c
1 /*
2 * Copyright 2010 Jerome Glisse <glisse@freedesktop.org>
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * on the rights to use, copy, modify, merge, publish, distribute, sub
8 * license, and/or sell copies of the Software, and to permit persons to whom
9 * the Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
13 * Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHOR(S) AND/OR THEIR SUPPLIERS BE LIABLE FOR ANY CLAIM,
19 * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
20 * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
21 * USE OR OTHER DEALINGS IN THE SOFTWARE.
22 */
23 #include "r600_formats.h"
24 #include "r600_shader.h"
25 #include "evergreend.h"
26
27 #include "pipe/p_shader_tokens.h"
28 #include "util/u_pack_color.h"
29 #include "util/u_memory.h"
30 #include "util/u_framebuffer.h"
31 #include "util/u_dual_blend.h"
32 #include "evergreen_compute.h"
33 #include "util/u_math.h"
34
35 static INLINE unsigned evergreen_array_mode(unsigned mode)
36 {
37 switch (mode) {
38 case RADEON_SURF_MODE_LINEAR_ALIGNED: return V_028C70_ARRAY_LINEAR_ALIGNED;
39 break;
40 case RADEON_SURF_MODE_1D: return V_028C70_ARRAY_1D_TILED_THIN1;
41 break;
42 case RADEON_SURF_MODE_2D: return V_028C70_ARRAY_2D_TILED_THIN1;
43 default:
44 case RADEON_SURF_MODE_LINEAR: return V_028C70_ARRAY_LINEAR_GENERAL;
45 }
46 }
47
48 static uint32_t eg_num_banks(uint32_t nbanks)
49 {
50 switch (nbanks) {
51 case 2:
52 return 0;
53 case 4:
54 return 1;
55 case 8:
56 default:
57 return 2;
58 case 16:
59 return 3;
60 }
61 }
62
63
64 static unsigned eg_tile_split(unsigned tile_split)
65 {
66 switch (tile_split) {
67 case 64: tile_split = 0; break;
68 case 128: tile_split = 1; break;
69 case 256: tile_split = 2; break;
70 case 512: tile_split = 3; break;
71 default:
72 case 1024: tile_split = 4; break;
73 case 2048: tile_split = 5; break;
74 case 4096: tile_split = 6; break;
75 }
76 return tile_split;
77 }
78
79 static unsigned eg_macro_tile_aspect(unsigned macro_tile_aspect)
80 {
81 switch (macro_tile_aspect) {
82 default:
83 case 1: macro_tile_aspect = 0; break;
84 case 2: macro_tile_aspect = 1; break;
85 case 4: macro_tile_aspect = 2; break;
86 case 8: macro_tile_aspect = 3; break;
87 }
88 return macro_tile_aspect;
89 }
90
91 static unsigned eg_bank_wh(unsigned bankwh)
92 {
93 switch (bankwh) {
94 default:
95 case 1: bankwh = 0; break;
96 case 2: bankwh = 1; break;
97 case 4: bankwh = 2; break;
98 case 8: bankwh = 3; break;
99 }
100 return bankwh;
101 }
102
103 static uint32_t r600_translate_blend_function(int blend_func)
104 {
105 switch (blend_func) {
106 case PIPE_BLEND_ADD:
107 return V_028780_COMB_DST_PLUS_SRC;
108 case PIPE_BLEND_SUBTRACT:
109 return V_028780_COMB_SRC_MINUS_DST;
110 case PIPE_BLEND_REVERSE_SUBTRACT:
111 return V_028780_COMB_DST_MINUS_SRC;
112 case PIPE_BLEND_MIN:
113 return V_028780_COMB_MIN_DST_SRC;
114 case PIPE_BLEND_MAX:
115 return V_028780_COMB_MAX_DST_SRC;
116 default:
117 R600_ERR("Unknown blend function %d\n", blend_func);
118 assert(0);
119 break;
120 }
121 return 0;
122 }
123
124 static uint32_t r600_translate_blend_factor(int blend_fact)
125 {
126 switch (blend_fact) {
127 case PIPE_BLENDFACTOR_ONE:
128 return V_028780_BLEND_ONE;
129 case PIPE_BLENDFACTOR_SRC_COLOR:
130 return V_028780_BLEND_SRC_COLOR;
131 case PIPE_BLENDFACTOR_SRC_ALPHA:
132 return V_028780_BLEND_SRC_ALPHA;
133 case PIPE_BLENDFACTOR_DST_ALPHA:
134 return V_028780_BLEND_DST_ALPHA;
135 case PIPE_BLENDFACTOR_DST_COLOR:
136 return V_028780_BLEND_DST_COLOR;
137 case PIPE_BLENDFACTOR_SRC_ALPHA_SATURATE:
138 return V_028780_BLEND_SRC_ALPHA_SATURATE;
139 case PIPE_BLENDFACTOR_CONST_COLOR:
140 return V_028780_BLEND_CONST_COLOR;
141 case PIPE_BLENDFACTOR_CONST_ALPHA:
142 return V_028780_BLEND_CONST_ALPHA;
143 case PIPE_BLENDFACTOR_ZERO:
144 return V_028780_BLEND_ZERO;
145 case PIPE_BLENDFACTOR_INV_SRC_COLOR:
146 return V_028780_BLEND_ONE_MINUS_SRC_COLOR;
147 case PIPE_BLENDFACTOR_INV_SRC_ALPHA:
148 return V_028780_BLEND_ONE_MINUS_SRC_ALPHA;
149 case PIPE_BLENDFACTOR_INV_DST_ALPHA:
150 return V_028780_BLEND_ONE_MINUS_DST_ALPHA;
151 case PIPE_BLENDFACTOR_INV_DST_COLOR:
152 return V_028780_BLEND_ONE_MINUS_DST_COLOR;
153 case PIPE_BLENDFACTOR_INV_CONST_COLOR:
154 return V_028780_BLEND_ONE_MINUS_CONST_COLOR;
155 case PIPE_BLENDFACTOR_INV_CONST_ALPHA:
156 return V_028780_BLEND_ONE_MINUS_CONST_ALPHA;
157 case PIPE_BLENDFACTOR_SRC1_COLOR:
158 return V_028780_BLEND_SRC1_COLOR;
159 case PIPE_BLENDFACTOR_SRC1_ALPHA:
160 return V_028780_BLEND_SRC1_ALPHA;
161 case PIPE_BLENDFACTOR_INV_SRC1_COLOR:
162 return V_028780_BLEND_INV_SRC1_COLOR;
163 case PIPE_BLENDFACTOR_INV_SRC1_ALPHA:
164 return V_028780_BLEND_INV_SRC1_ALPHA;
165 default:
166 R600_ERR("Bad blend factor %d not supported!\n", blend_fact);
167 assert(0);
168 break;
169 }
170 return 0;
171 }
172
173 static unsigned r600_tex_dim(unsigned dim, unsigned nr_samples)
174 {
175 switch (dim) {
176 default:
177 case PIPE_TEXTURE_1D:
178 return V_030000_SQ_TEX_DIM_1D;
179 case PIPE_TEXTURE_1D_ARRAY:
180 return V_030000_SQ_TEX_DIM_1D_ARRAY;
181 case PIPE_TEXTURE_2D:
182 case PIPE_TEXTURE_RECT:
183 return nr_samples > 1 ? V_030000_SQ_TEX_DIM_2D_MSAA :
184 V_030000_SQ_TEX_DIM_2D;
185 case PIPE_TEXTURE_2D_ARRAY:
186 return nr_samples > 1 ? V_030000_SQ_TEX_DIM_2D_ARRAY_MSAA :
187 V_030000_SQ_TEX_DIM_2D_ARRAY;
188 case PIPE_TEXTURE_3D:
189 return V_030000_SQ_TEX_DIM_3D;
190 case PIPE_TEXTURE_CUBE:
191 case PIPE_TEXTURE_CUBE_ARRAY:
192 return V_030000_SQ_TEX_DIM_CUBEMAP;
193 }
194 }
195
196 static uint32_t r600_translate_dbformat(enum pipe_format format)
197 {
198 switch (format) {
199 case PIPE_FORMAT_Z16_UNORM:
200 return V_028040_Z_16;
201 case PIPE_FORMAT_Z24X8_UNORM:
202 case PIPE_FORMAT_Z24_UNORM_S8_UINT:
203 case PIPE_FORMAT_X8Z24_UNORM:
204 case PIPE_FORMAT_S8_UINT_Z24_UNORM:
205 return V_028040_Z_24;
206 case PIPE_FORMAT_Z32_FLOAT:
207 case PIPE_FORMAT_Z32_FLOAT_S8X24_UINT:
208 return V_028040_Z_32_FLOAT;
209 default:
210 return ~0U;
211 }
212 }
213
214 static uint32_t r600_translate_colorswap(enum pipe_format format)
215 {
216 switch (format) {
217 /* 8-bit buffers. */
218 case PIPE_FORMAT_L4A4_UNORM:
219 case PIPE_FORMAT_A4R4_UNORM:
220 return V_028C70_SWAP_ALT;
221
222 case PIPE_FORMAT_A8_UNORM:
223 case PIPE_FORMAT_A8_SNORM:
224 case PIPE_FORMAT_A8_UINT:
225 case PIPE_FORMAT_A8_SINT:
226 case PIPE_FORMAT_A16_UNORM:
227 case PIPE_FORMAT_A16_SNORM:
228 case PIPE_FORMAT_A16_UINT:
229 case PIPE_FORMAT_A16_SINT:
230 case PIPE_FORMAT_A16_FLOAT:
231 case PIPE_FORMAT_A32_UINT:
232 case PIPE_FORMAT_A32_SINT:
233 case PIPE_FORMAT_A32_FLOAT:
234 case PIPE_FORMAT_R4A4_UNORM:
235 return V_028C70_SWAP_ALT_REV;
236 case PIPE_FORMAT_I8_UNORM:
237 case PIPE_FORMAT_I8_SNORM:
238 case PIPE_FORMAT_I8_UINT:
239 case PIPE_FORMAT_I8_SINT:
240 case PIPE_FORMAT_I16_UNORM:
241 case PIPE_FORMAT_I16_SNORM:
242 case PIPE_FORMAT_I16_UINT:
243 case PIPE_FORMAT_I16_SINT:
244 case PIPE_FORMAT_I16_FLOAT:
245 case PIPE_FORMAT_I32_UINT:
246 case PIPE_FORMAT_I32_SINT:
247 case PIPE_FORMAT_I32_FLOAT:
248 case PIPE_FORMAT_L8_UNORM:
249 case PIPE_FORMAT_L8_SNORM:
250 case PIPE_FORMAT_L8_UINT:
251 case PIPE_FORMAT_L8_SINT:
252 case PIPE_FORMAT_L8_SRGB:
253 case PIPE_FORMAT_L16_UNORM:
254 case PIPE_FORMAT_L16_SNORM:
255 case PIPE_FORMAT_L16_UINT:
256 case PIPE_FORMAT_L16_SINT:
257 case PIPE_FORMAT_L16_FLOAT:
258 case PIPE_FORMAT_L32_UINT:
259 case PIPE_FORMAT_L32_SINT:
260 case PIPE_FORMAT_L32_FLOAT:
261 case PIPE_FORMAT_R8_UNORM:
262 case PIPE_FORMAT_R8_SNORM:
263 case PIPE_FORMAT_R8_UINT:
264 case PIPE_FORMAT_R8_SINT:
265 return V_028C70_SWAP_STD;
266
267 /* 16-bit buffers. */
268 case PIPE_FORMAT_B5G6R5_UNORM:
269 return V_028C70_SWAP_STD_REV;
270
271 case PIPE_FORMAT_B5G5R5A1_UNORM:
272 case PIPE_FORMAT_B5G5R5X1_UNORM:
273 return V_028C70_SWAP_ALT;
274
275 case PIPE_FORMAT_B4G4R4A4_UNORM:
276 case PIPE_FORMAT_B4G4R4X4_UNORM:
277 return V_028C70_SWAP_ALT;
278
279 case PIPE_FORMAT_Z16_UNORM:
280 return V_028C70_SWAP_STD;
281
282 case PIPE_FORMAT_L8A8_UNORM:
283 case PIPE_FORMAT_L8A8_SNORM:
284 case PIPE_FORMAT_L8A8_UINT:
285 case PIPE_FORMAT_L8A8_SINT:
286 case PIPE_FORMAT_L8A8_SRGB:
287 case PIPE_FORMAT_L16A16_UNORM:
288 case PIPE_FORMAT_L16A16_SNORM:
289 case PIPE_FORMAT_L16A16_UINT:
290 case PIPE_FORMAT_L16A16_SINT:
291 case PIPE_FORMAT_L16A16_FLOAT:
292 case PIPE_FORMAT_L32A32_UINT:
293 case PIPE_FORMAT_L32A32_SINT:
294 case PIPE_FORMAT_L32A32_FLOAT:
295 case PIPE_FORMAT_R8A8_UNORM:
296 case PIPE_FORMAT_R8A8_SNORM:
297 case PIPE_FORMAT_R8A8_UINT:
298 case PIPE_FORMAT_R8A8_SINT:
299 case PIPE_FORMAT_R16A16_UNORM:
300 case PIPE_FORMAT_R16A16_SNORM:
301 case PIPE_FORMAT_R16A16_UINT:
302 case PIPE_FORMAT_R16A16_SINT:
303 case PIPE_FORMAT_R16A16_FLOAT:
304 case PIPE_FORMAT_R32A32_UINT:
305 case PIPE_FORMAT_R32A32_SINT:
306 case PIPE_FORMAT_R32A32_FLOAT:
307 return V_028C70_SWAP_ALT;
308 case PIPE_FORMAT_R8G8_UNORM:
309 case PIPE_FORMAT_R8G8_SNORM:
310 case PIPE_FORMAT_R8G8_UINT:
311 case PIPE_FORMAT_R8G8_SINT:
312 return V_028C70_SWAP_STD;
313
314 case PIPE_FORMAT_R16_UNORM:
315 case PIPE_FORMAT_R16_SNORM:
316 case PIPE_FORMAT_R16_UINT:
317 case PIPE_FORMAT_R16_SINT:
318 case PIPE_FORMAT_R16_FLOAT:
319 return V_028C70_SWAP_STD;
320
321 /* 32-bit buffers. */
322 case PIPE_FORMAT_A8B8G8R8_SRGB:
323 return V_028C70_SWAP_STD_REV;
324 case PIPE_FORMAT_B8G8R8A8_SRGB:
325 return V_028C70_SWAP_ALT;
326
327 case PIPE_FORMAT_B8G8R8A8_UNORM:
328 case PIPE_FORMAT_B8G8R8X8_UNORM:
329 return V_028C70_SWAP_ALT;
330
331 case PIPE_FORMAT_A8R8G8B8_UNORM:
332 case PIPE_FORMAT_X8R8G8B8_UNORM:
333 return V_028C70_SWAP_ALT_REV;
334 case PIPE_FORMAT_R8G8B8A8_SNORM:
335 case PIPE_FORMAT_R8G8B8A8_UNORM:
336 case PIPE_FORMAT_R8G8B8A8_SINT:
337 case PIPE_FORMAT_R8G8B8A8_UINT:
338 case PIPE_FORMAT_R8G8B8X8_UNORM:
339 case PIPE_FORMAT_R8G8B8X8_SNORM:
340 case PIPE_FORMAT_R8G8B8X8_SRGB:
341 case PIPE_FORMAT_R8G8B8X8_UINT:
342 case PIPE_FORMAT_R8G8B8X8_SINT:
343 return V_028C70_SWAP_STD;
344
345 case PIPE_FORMAT_A8B8G8R8_UNORM:
346 case PIPE_FORMAT_X8B8G8R8_UNORM:
347 /* case PIPE_FORMAT_R8SG8SB8UX8U_NORM: */
348 return V_028C70_SWAP_STD_REV;
349
350 case PIPE_FORMAT_Z24X8_UNORM:
351 case PIPE_FORMAT_Z24_UNORM_S8_UINT:
352 return V_028C70_SWAP_STD;
353
354 case PIPE_FORMAT_X8Z24_UNORM:
355 case PIPE_FORMAT_S8_UINT_Z24_UNORM:
356 return V_028C70_SWAP_STD_REV;
357
358 case PIPE_FORMAT_R10G10B10A2_UNORM:
359 case PIPE_FORMAT_R10G10B10X2_SNORM:
360 case PIPE_FORMAT_R10SG10SB10SA2U_NORM:
361 return V_028C70_SWAP_STD;
362
363 case PIPE_FORMAT_B10G10R10A2_UNORM:
364 case PIPE_FORMAT_B10G10R10A2_UINT:
365 case PIPE_FORMAT_B10G10R10X2_UNORM:
366 return V_028C70_SWAP_ALT;
367
368 case PIPE_FORMAT_R11G11B10_FLOAT:
369 case PIPE_FORMAT_R32_FLOAT:
370 case PIPE_FORMAT_R32_UINT:
371 case PIPE_FORMAT_R32_SINT:
372 case PIPE_FORMAT_Z32_FLOAT:
373 case PIPE_FORMAT_R16G16_FLOAT:
374 case PIPE_FORMAT_R16G16_UNORM:
375 case PIPE_FORMAT_R16G16_SNORM:
376 case PIPE_FORMAT_R16G16_UINT:
377 case PIPE_FORMAT_R16G16_SINT:
378 return V_028C70_SWAP_STD;
379
380 /* 64-bit buffers. */
381 case PIPE_FORMAT_R32G32_FLOAT:
382 case PIPE_FORMAT_R32G32_UINT:
383 case PIPE_FORMAT_R32G32_SINT:
384 case PIPE_FORMAT_R16G16B16A16_UNORM:
385 case PIPE_FORMAT_R16G16B16A16_SNORM:
386 case PIPE_FORMAT_R16G16B16A16_UINT:
387 case PIPE_FORMAT_R16G16B16A16_SINT:
388 case PIPE_FORMAT_R16G16B16A16_FLOAT:
389 case PIPE_FORMAT_R16G16B16X16_UNORM:
390 case PIPE_FORMAT_R16G16B16X16_SNORM:
391 case PIPE_FORMAT_R16G16B16X16_FLOAT:
392 case PIPE_FORMAT_R16G16B16X16_UINT:
393 case PIPE_FORMAT_R16G16B16X16_SINT:
394 case PIPE_FORMAT_Z32_FLOAT_S8X24_UINT:
395
396 /* 128-bit buffers. */
397 case PIPE_FORMAT_R32G32B32A32_FLOAT:
398 case PIPE_FORMAT_R32G32B32A32_SNORM:
399 case PIPE_FORMAT_R32G32B32A32_UNORM:
400 case PIPE_FORMAT_R32G32B32A32_SINT:
401 case PIPE_FORMAT_R32G32B32A32_UINT:
402 case PIPE_FORMAT_R32G32B32X32_FLOAT:
403 case PIPE_FORMAT_R32G32B32X32_UINT:
404 case PIPE_FORMAT_R32G32B32X32_SINT:
405 return V_028C70_SWAP_STD;
406 default:
407 R600_ERR("unsupported colorswap format %d\n", format);
408 return ~0U;
409 }
410 return ~0U;
411 }
412
413 static uint32_t r600_translate_colorformat(enum pipe_format format)
414 {
415 switch (format) {
416 /* 8-bit buffers. */
417 case PIPE_FORMAT_A8_UNORM:
418 case PIPE_FORMAT_A8_SNORM:
419 case PIPE_FORMAT_A8_UINT:
420 case PIPE_FORMAT_A8_SINT:
421 case PIPE_FORMAT_I8_UNORM:
422 case PIPE_FORMAT_I8_SNORM:
423 case PIPE_FORMAT_I8_UINT:
424 case PIPE_FORMAT_I8_SINT:
425 case PIPE_FORMAT_L8_UNORM:
426 case PIPE_FORMAT_L8_SNORM:
427 case PIPE_FORMAT_L8_UINT:
428 case PIPE_FORMAT_L8_SINT:
429 case PIPE_FORMAT_L8_SRGB:
430 case PIPE_FORMAT_R8_UNORM:
431 case PIPE_FORMAT_R8_SNORM:
432 case PIPE_FORMAT_R8_UINT:
433 case PIPE_FORMAT_R8_SINT:
434 return V_028C70_COLOR_8;
435
436 /* 16-bit buffers. */
437 case PIPE_FORMAT_B5G6R5_UNORM:
438 return V_028C70_COLOR_5_6_5;
439
440 case PIPE_FORMAT_B5G5R5A1_UNORM:
441 case PIPE_FORMAT_B5G5R5X1_UNORM:
442 return V_028C70_COLOR_1_5_5_5;
443
444 case PIPE_FORMAT_B4G4R4A4_UNORM:
445 case PIPE_FORMAT_B4G4R4X4_UNORM:
446 return V_028C70_COLOR_4_4_4_4;
447
448 case PIPE_FORMAT_Z16_UNORM:
449 return V_028C70_COLOR_16;
450
451 case PIPE_FORMAT_L8A8_UNORM:
452 case PIPE_FORMAT_L8A8_SNORM:
453 case PIPE_FORMAT_L8A8_UINT:
454 case PIPE_FORMAT_L8A8_SINT:
455 case PIPE_FORMAT_L8A8_SRGB:
456 case PIPE_FORMAT_R8G8_UNORM:
457 case PIPE_FORMAT_R8G8_SNORM:
458 case PIPE_FORMAT_R8G8_UINT:
459 case PIPE_FORMAT_R8G8_SINT:
460 case PIPE_FORMAT_R8A8_UNORM:
461 case PIPE_FORMAT_R8A8_SNORM:
462 case PIPE_FORMAT_R8A8_UINT:
463 case PIPE_FORMAT_R8A8_SINT:
464 return V_028C70_COLOR_8_8;
465
466 case PIPE_FORMAT_R16_UNORM:
467 case PIPE_FORMAT_R16_SNORM:
468 case PIPE_FORMAT_R16_UINT:
469 case PIPE_FORMAT_R16_SINT:
470 case PIPE_FORMAT_A16_UNORM:
471 case PIPE_FORMAT_A16_SNORM:
472 case PIPE_FORMAT_A16_UINT:
473 case PIPE_FORMAT_A16_SINT:
474 case PIPE_FORMAT_L16_UNORM:
475 case PIPE_FORMAT_L16_SNORM:
476 case PIPE_FORMAT_L16_UINT:
477 case PIPE_FORMAT_L16_SINT:
478 case PIPE_FORMAT_I16_UNORM:
479 case PIPE_FORMAT_I16_SNORM:
480 case PIPE_FORMAT_I16_UINT:
481 case PIPE_FORMAT_I16_SINT:
482 return V_028C70_COLOR_16;
483
484 case PIPE_FORMAT_R16_FLOAT:
485 case PIPE_FORMAT_A16_FLOAT:
486 case PIPE_FORMAT_L16_FLOAT:
487 case PIPE_FORMAT_I16_FLOAT:
488 return V_028C70_COLOR_16_FLOAT;
489
490 /* 32-bit buffers. */
491 case PIPE_FORMAT_A8B8G8R8_SRGB:
492 case PIPE_FORMAT_A8B8G8R8_UNORM:
493 case PIPE_FORMAT_A8R8G8B8_UNORM:
494 case PIPE_FORMAT_B8G8R8A8_SRGB:
495 case PIPE_FORMAT_B8G8R8A8_UNORM:
496 case PIPE_FORMAT_B8G8R8X8_UNORM:
497 case PIPE_FORMAT_R8G8B8A8_SNORM:
498 case PIPE_FORMAT_R8G8B8A8_UNORM:
499 case PIPE_FORMAT_R8G8B8X8_UNORM:
500 case PIPE_FORMAT_R8G8B8X8_SNORM:
501 case PIPE_FORMAT_R8G8B8X8_SRGB:
502 case PIPE_FORMAT_R8G8B8X8_UINT:
503 case PIPE_FORMAT_R8G8B8X8_SINT:
504 case PIPE_FORMAT_R8SG8SB8UX8U_NORM:
505 case PIPE_FORMAT_X8B8G8R8_UNORM:
506 case PIPE_FORMAT_X8R8G8B8_UNORM:
507 case PIPE_FORMAT_R8G8B8_UNORM:
508 case PIPE_FORMAT_R8G8B8A8_SINT:
509 case PIPE_FORMAT_R8G8B8A8_UINT:
510 return V_028C70_COLOR_8_8_8_8;
511
512 case PIPE_FORMAT_R10G10B10A2_UNORM:
513 case PIPE_FORMAT_R10G10B10X2_SNORM:
514 case PIPE_FORMAT_B10G10R10A2_UNORM:
515 case PIPE_FORMAT_B10G10R10A2_UINT:
516 case PIPE_FORMAT_B10G10R10X2_UNORM:
517 case PIPE_FORMAT_R10SG10SB10SA2U_NORM:
518 return V_028C70_COLOR_2_10_10_10;
519
520 case PIPE_FORMAT_Z24X8_UNORM:
521 case PIPE_FORMAT_Z24_UNORM_S8_UINT:
522 return V_028C70_COLOR_8_24;
523
524 case PIPE_FORMAT_X8Z24_UNORM:
525 case PIPE_FORMAT_S8_UINT_Z24_UNORM:
526 return V_028C70_COLOR_24_8;
527
528 case PIPE_FORMAT_Z32_FLOAT_S8X24_UINT:
529 return V_028C70_COLOR_X24_8_32_FLOAT;
530
531 case PIPE_FORMAT_R32_UINT:
532 case PIPE_FORMAT_R32_SINT:
533 case PIPE_FORMAT_A32_UINT:
534 case PIPE_FORMAT_A32_SINT:
535 case PIPE_FORMAT_L32_UINT:
536 case PIPE_FORMAT_L32_SINT:
537 case PIPE_FORMAT_I32_UINT:
538 case PIPE_FORMAT_I32_SINT:
539 return V_028C70_COLOR_32;
540
541 case PIPE_FORMAT_R32_FLOAT:
542 case PIPE_FORMAT_A32_FLOAT:
543 case PIPE_FORMAT_L32_FLOAT:
544 case PIPE_FORMAT_I32_FLOAT:
545 case PIPE_FORMAT_Z32_FLOAT:
546 return V_028C70_COLOR_32_FLOAT;
547
548 case PIPE_FORMAT_R16G16_FLOAT:
549 case PIPE_FORMAT_L16A16_FLOAT:
550 case PIPE_FORMAT_R16A16_FLOAT:
551 return V_028C70_COLOR_16_16_FLOAT;
552
553 case PIPE_FORMAT_R16G16_UNORM:
554 case PIPE_FORMAT_R16G16_SNORM:
555 case PIPE_FORMAT_R16G16_UINT:
556 case PIPE_FORMAT_R16G16_SINT:
557 case PIPE_FORMAT_L16A16_UNORM:
558 case PIPE_FORMAT_L16A16_SNORM:
559 case PIPE_FORMAT_L16A16_UINT:
560 case PIPE_FORMAT_L16A16_SINT:
561 case PIPE_FORMAT_R16A16_UNORM:
562 case PIPE_FORMAT_R16A16_SNORM:
563 case PIPE_FORMAT_R16A16_UINT:
564 case PIPE_FORMAT_R16A16_SINT:
565 return V_028C70_COLOR_16_16;
566
567 case PIPE_FORMAT_R11G11B10_FLOAT:
568 return V_028C70_COLOR_10_11_11_FLOAT;
569
570 /* 64-bit buffers. */
571 case PIPE_FORMAT_R16G16B16A16_UINT:
572 case PIPE_FORMAT_R16G16B16A16_SINT:
573 case PIPE_FORMAT_R16G16B16A16_UNORM:
574 case PIPE_FORMAT_R16G16B16A16_SNORM:
575 case PIPE_FORMAT_R16G16B16X16_UNORM:
576 case PIPE_FORMAT_R16G16B16X16_SNORM:
577 case PIPE_FORMAT_R16G16B16X16_UINT:
578 case PIPE_FORMAT_R16G16B16X16_SINT:
579 return V_028C70_COLOR_16_16_16_16;
580
581 case PIPE_FORMAT_R16G16B16A16_FLOAT:
582 case PIPE_FORMAT_R16G16B16X16_FLOAT:
583 return V_028C70_COLOR_16_16_16_16_FLOAT;
584
585 case PIPE_FORMAT_R32G32_FLOAT:
586 case PIPE_FORMAT_L32A32_FLOAT:
587 case PIPE_FORMAT_R32A32_FLOAT:
588 return V_028C70_COLOR_32_32_FLOAT;
589
590 case PIPE_FORMAT_R32G32_SINT:
591 case PIPE_FORMAT_R32G32_UINT:
592 case PIPE_FORMAT_L32A32_UINT:
593 case PIPE_FORMAT_L32A32_SINT:
594 return V_028C70_COLOR_32_32;
595
596 /* 128-bit buffers. */
597 case PIPE_FORMAT_R32G32B32A32_SNORM:
598 case PIPE_FORMAT_R32G32B32A32_UNORM:
599 case PIPE_FORMAT_R32G32B32A32_SINT:
600 case PIPE_FORMAT_R32G32B32A32_UINT:
601 case PIPE_FORMAT_R32G32B32X32_UINT:
602 case PIPE_FORMAT_R32G32B32X32_SINT:
603 return V_028C70_COLOR_32_32_32_32;
604 case PIPE_FORMAT_R32G32B32A32_FLOAT:
605 case PIPE_FORMAT_R32G32B32X32_FLOAT:
606 return V_028C70_COLOR_32_32_32_32_FLOAT;
607
608 /* YUV buffers. */
609 case PIPE_FORMAT_UYVY:
610 case PIPE_FORMAT_YUYV:
611 default:
612 return ~0U; /* Unsupported. */
613 }
614 }
615
616 static uint32_t r600_colorformat_endian_swap(uint32_t colorformat)
617 {
618 if (R600_BIG_ENDIAN) {
619 switch(colorformat) {
620
621 /* 8-bit buffers. */
622 case V_028C70_COLOR_8:
623 return ENDIAN_NONE;
624
625 /* 16-bit buffers. */
626 case V_028C70_COLOR_5_6_5:
627 case V_028C70_COLOR_1_5_5_5:
628 case V_028C70_COLOR_4_4_4_4:
629 case V_028C70_COLOR_16:
630 case V_028C70_COLOR_8_8:
631 return ENDIAN_8IN16;
632
633 /* 32-bit buffers. */
634 case V_028C70_COLOR_8_8_8_8:
635 case V_028C70_COLOR_2_10_10_10:
636 case V_028C70_COLOR_8_24:
637 case V_028C70_COLOR_24_8:
638 case V_028C70_COLOR_32_FLOAT:
639 case V_028C70_COLOR_16_16_FLOAT:
640 case V_028C70_COLOR_16_16:
641 return ENDIAN_8IN32;
642
643 /* 64-bit buffers. */
644 case V_028C70_COLOR_16_16_16_16:
645 case V_028C70_COLOR_16_16_16_16_FLOAT:
646 return ENDIAN_8IN16;
647
648 case V_028C70_COLOR_32_32_FLOAT:
649 case V_028C70_COLOR_32_32:
650 case V_028C70_COLOR_X24_8_32_FLOAT:
651 return ENDIAN_8IN32;
652
653 /* 96-bit buffers. */
654 case V_028C70_COLOR_32_32_32_FLOAT:
655 /* 128-bit buffers. */
656 case V_028C70_COLOR_32_32_32_32_FLOAT:
657 case V_028C70_COLOR_32_32_32_32:
658 return ENDIAN_8IN32;
659 default:
660 return ENDIAN_NONE; /* Unsupported. */
661 }
662 } else {
663 return ENDIAN_NONE;
664 }
665 }
666
667 static bool r600_is_sampler_format_supported(struct pipe_screen *screen, enum pipe_format format)
668 {
669 return r600_translate_texformat(screen, format, NULL, NULL, NULL) != ~0U;
670 }
671
672 static bool r600_is_colorbuffer_format_supported(enum pipe_format format)
673 {
674 return r600_translate_colorformat(format) != ~0U &&
675 r600_translate_colorswap(format) != ~0U;
676 }
677
678 static bool r600_is_zs_format_supported(enum pipe_format format)
679 {
680 return r600_translate_dbformat(format) != ~0U;
681 }
682
683 boolean evergreen_is_format_supported(struct pipe_screen *screen,
684 enum pipe_format format,
685 enum pipe_texture_target target,
686 unsigned sample_count,
687 unsigned usage)
688 {
689 struct r600_screen *rscreen = (struct r600_screen*)screen;
690 unsigned retval = 0;
691
692 if (target >= PIPE_MAX_TEXTURE_TYPES) {
693 R600_ERR("r600: unsupported texture type %d\n", target);
694 return FALSE;
695 }
696
697 if (!util_format_is_supported(format, usage))
698 return FALSE;
699
700 if (sample_count > 1) {
701 if (!rscreen->has_msaa)
702 return FALSE;
703
704 switch (sample_count) {
705 case 2:
706 case 4:
707 case 8:
708 break;
709 default:
710 return FALSE;
711 }
712 }
713
714 if (usage & PIPE_BIND_SAMPLER_VIEW) {
715 if (target == PIPE_BUFFER) {
716 if (r600_is_vertex_format_supported(format))
717 retval |= PIPE_BIND_SAMPLER_VIEW;
718 } else {
719 if (r600_is_sampler_format_supported(screen, format))
720 retval |= PIPE_BIND_SAMPLER_VIEW;
721 }
722 }
723
724 if ((usage & (PIPE_BIND_RENDER_TARGET |
725 PIPE_BIND_DISPLAY_TARGET |
726 PIPE_BIND_SCANOUT |
727 PIPE_BIND_SHARED)) &&
728 r600_is_colorbuffer_format_supported(format)) {
729 retval |= usage &
730 (PIPE_BIND_RENDER_TARGET |
731 PIPE_BIND_DISPLAY_TARGET |
732 PIPE_BIND_SCANOUT |
733 PIPE_BIND_SHARED);
734 }
735
736 if ((usage & PIPE_BIND_DEPTH_STENCIL) &&
737 r600_is_zs_format_supported(format)) {
738 retval |= PIPE_BIND_DEPTH_STENCIL;
739 }
740
741 if ((usage & PIPE_BIND_VERTEX_BUFFER) &&
742 r600_is_vertex_format_supported(format)) {
743 retval |= PIPE_BIND_VERTEX_BUFFER;
744 }
745
746 if (usage & PIPE_BIND_TRANSFER_READ)
747 retval |= PIPE_BIND_TRANSFER_READ;
748 if (usage & PIPE_BIND_TRANSFER_WRITE)
749 retval |= PIPE_BIND_TRANSFER_WRITE;
750
751 return retval == usage;
752 }
753
754 static void *evergreen_create_blend_state_mode(struct pipe_context *ctx,
755 const struct pipe_blend_state *state, int mode)
756 {
757 uint32_t color_control = 0, target_mask = 0;
758 struct r600_blend_state *blend = CALLOC_STRUCT(r600_blend_state);
759
760 if (!blend) {
761 return NULL;
762 }
763
764 r600_init_command_buffer(&blend->buffer, 20);
765 r600_init_command_buffer(&blend->buffer_no_blend, 20);
766
767 if (state->logicop_enable) {
768 color_control |= (state->logicop_func << 16) | (state->logicop_func << 20);
769 } else {
770 color_control |= (0xcc << 16);
771 }
772 /* we pretend 8 buffer are used, CB_SHADER_MASK will disable unused one */
773 if (state->independent_blend_enable) {
774 for (int i = 0; i < 8; i++) {
775 target_mask |= (state->rt[i].colormask << (4 * i));
776 }
777 } else {
778 for (int i = 0; i < 8; i++) {
779 target_mask |= (state->rt[0].colormask << (4 * i));
780 }
781 }
782
783 /* only have dual source on MRT0 */
784 blend->dual_src_blend = util_blend_state_is_dual(state, 0);
785 blend->cb_target_mask = target_mask;
786 blend->alpha_to_one = state->alpha_to_one;
787
788 if (target_mask)
789 color_control |= S_028808_MODE(mode);
790 else
791 color_control |= S_028808_MODE(V_028808_CB_DISABLE);
792
793
794 r600_store_context_reg(&blend->buffer, R_028808_CB_COLOR_CONTROL, color_control);
795 r600_store_context_reg(&blend->buffer, R_028B70_DB_ALPHA_TO_MASK,
796 S_028B70_ALPHA_TO_MASK_ENABLE(state->alpha_to_coverage) |
797 S_028B70_ALPHA_TO_MASK_OFFSET0(2) |
798 S_028B70_ALPHA_TO_MASK_OFFSET1(2) |
799 S_028B70_ALPHA_TO_MASK_OFFSET2(2) |
800 S_028B70_ALPHA_TO_MASK_OFFSET3(2));
801 r600_store_context_reg_seq(&blend->buffer, R_028780_CB_BLEND0_CONTROL, 8);
802
803 /* Copy over the dwords set so far into buffer_no_blend.
804 * Only the CB_BLENDi_CONTROL registers must be set after this. */
805 memcpy(blend->buffer_no_blend.buf, blend->buffer.buf, blend->buffer.num_dw * 4);
806 blend->buffer_no_blend.num_dw = blend->buffer.num_dw;
807
808 for (int i = 0; i < 8; i++) {
809 /* state->rt entries > 0 only written if independent blending */
810 const int j = state->independent_blend_enable ? i : 0;
811
812 unsigned eqRGB = state->rt[j].rgb_func;
813 unsigned srcRGB = state->rt[j].rgb_src_factor;
814 unsigned dstRGB = state->rt[j].rgb_dst_factor;
815 unsigned eqA = state->rt[j].alpha_func;
816 unsigned srcA = state->rt[j].alpha_src_factor;
817 unsigned dstA = state->rt[j].alpha_dst_factor;
818 uint32_t bc = 0;
819
820 r600_store_value(&blend->buffer_no_blend, 0);
821
822 if (!state->rt[j].blend_enable) {
823 r600_store_value(&blend->buffer, 0);
824 continue;
825 }
826
827 bc |= S_028780_BLEND_CONTROL_ENABLE(1);
828 bc |= S_028780_COLOR_COMB_FCN(r600_translate_blend_function(eqRGB));
829 bc |= S_028780_COLOR_SRCBLEND(r600_translate_blend_factor(srcRGB));
830 bc |= S_028780_COLOR_DESTBLEND(r600_translate_blend_factor(dstRGB));
831
832 if (srcA != srcRGB || dstA != dstRGB || eqA != eqRGB) {
833 bc |= S_028780_SEPARATE_ALPHA_BLEND(1);
834 bc |= S_028780_ALPHA_COMB_FCN(r600_translate_blend_function(eqA));
835 bc |= S_028780_ALPHA_SRCBLEND(r600_translate_blend_factor(srcA));
836 bc |= S_028780_ALPHA_DESTBLEND(r600_translate_blend_factor(dstA));
837 }
838 r600_store_value(&blend->buffer, bc);
839 }
840 return blend;
841 }
842
843 static void *evergreen_create_blend_state(struct pipe_context *ctx,
844 const struct pipe_blend_state *state)
845 {
846
847 return evergreen_create_blend_state_mode(ctx, state, V_028808_CB_NORMAL);
848 }
849
850 static void *evergreen_create_dsa_state(struct pipe_context *ctx,
851 const struct pipe_depth_stencil_alpha_state *state)
852 {
853 unsigned db_depth_control, alpha_test_control, alpha_ref;
854 struct r600_dsa_state *dsa = CALLOC_STRUCT(r600_dsa_state);
855
856 if (dsa == NULL) {
857 return NULL;
858 }
859
860 r600_init_command_buffer(&dsa->buffer, 3);
861
862 dsa->valuemask[0] = state->stencil[0].valuemask;
863 dsa->valuemask[1] = state->stencil[1].valuemask;
864 dsa->writemask[0] = state->stencil[0].writemask;
865 dsa->writemask[1] = state->stencil[1].writemask;
866 dsa->zwritemask = state->depth.writemask;
867
868 db_depth_control = S_028800_Z_ENABLE(state->depth.enabled) |
869 S_028800_Z_WRITE_ENABLE(state->depth.writemask) |
870 S_028800_ZFUNC(state->depth.func);
871
872 /* stencil */
873 if (state->stencil[0].enabled) {
874 db_depth_control |= S_028800_STENCIL_ENABLE(1);
875 db_depth_control |= S_028800_STENCILFUNC(state->stencil[0].func); /* translates straight */
876 db_depth_control |= S_028800_STENCILFAIL(r600_translate_stencil_op(state->stencil[0].fail_op));
877 db_depth_control |= S_028800_STENCILZPASS(r600_translate_stencil_op(state->stencil[0].zpass_op));
878 db_depth_control |= S_028800_STENCILZFAIL(r600_translate_stencil_op(state->stencil[0].zfail_op));
879
880 if (state->stencil[1].enabled) {
881 db_depth_control |= S_028800_BACKFACE_ENABLE(1);
882 db_depth_control |= S_028800_STENCILFUNC_BF(state->stencil[1].func); /* translates straight */
883 db_depth_control |= S_028800_STENCILFAIL_BF(r600_translate_stencil_op(state->stencil[1].fail_op));
884 db_depth_control |= S_028800_STENCILZPASS_BF(r600_translate_stencil_op(state->stencil[1].zpass_op));
885 db_depth_control |= S_028800_STENCILZFAIL_BF(r600_translate_stencil_op(state->stencil[1].zfail_op));
886 }
887 }
888
889 /* alpha */
890 alpha_test_control = 0;
891 alpha_ref = 0;
892 if (state->alpha.enabled) {
893 alpha_test_control = S_028410_ALPHA_FUNC(state->alpha.func);
894 alpha_test_control |= S_028410_ALPHA_TEST_ENABLE(1);
895 alpha_ref = fui(state->alpha.ref_value);
896 }
897 dsa->sx_alpha_test_control = alpha_test_control & 0xff;
898 dsa->alpha_ref = alpha_ref;
899
900 /* misc */
901 r600_store_context_reg(&dsa->buffer, R_028800_DB_DEPTH_CONTROL, db_depth_control);
902 return dsa;
903 }
904
905 static void *evergreen_create_rs_state(struct pipe_context *ctx,
906 const struct pipe_rasterizer_state *state)
907 {
908 struct r600_context *rctx = (struct r600_context *)ctx;
909 unsigned tmp, spi_interp;
910 float psize_min, psize_max;
911 struct r600_rasterizer_state *rs = CALLOC_STRUCT(r600_rasterizer_state);
912
913 if (rs == NULL) {
914 return NULL;
915 }
916
917 r600_init_command_buffer(&rs->buffer, 30);
918
919 rs->flatshade = state->flatshade;
920 rs->sprite_coord_enable = state->sprite_coord_enable;
921 rs->two_side = state->light_twoside;
922 rs->clip_plane_enable = state->clip_plane_enable;
923 rs->pa_sc_line_stipple = state->line_stipple_enable ?
924 S_028A0C_LINE_PATTERN(state->line_stipple_pattern) |
925 S_028A0C_REPEAT_COUNT(state->line_stipple_factor) : 0;
926 rs->pa_cl_clip_cntl =
927 S_028810_PS_UCP_MODE(3) |
928 S_028810_ZCLIP_NEAR_DISABLE(!state->depth_clip) |
929 S_028810_ZCLIP_FAR_DISABLE(!state->depth_clip) |
930 S_028810_DX_LINEAR_ATTR_CLIP_ENA(1);
931 rs->multisample_enable = state->multisample;
932
933 /* offset */
934 rs->offset_units = state->offset_units;
935 rs->offset_scale = state->offset_scale * 12.0f;
936 rs->offset_enable = state->offset_point || state->offset_line || state->offset_tri;
937
938 if (state->point_size_per_vertex) {
939 psize_min = util_get_min_point_size(state);
940 psize_max = 8192;
941 } else {
942 /* Force the point size to be as if the vertex output was disabled. */
943 psize_min = state->point_size;
944 psize_max = state->point_size;
945 }
946
947 spi_interp = S_0286D4_FLAT_SHADE_ENA(1);
948 if (state->sprite_coord_enable) {
949 spi_interp |= S_0286D4_PNT_SPRITE_ENA(1) |
950 S_0286D4_PNT_SPRITE_OVRD_X(2) |
951 S_0286D4_PNT_SPRITE_OVRD_Y(3) |
952 S_0286D4_PNT_SPRITE_OVRD_Z(0) |
953 S_0286D4_PNT_SPRITE_OVRD_W(1);
954 if (state->sprite_coord_mode != PIPE_SPRITE_COORD_UPPER_LEFT) {
955 spi_interp |= S_0286D4_PNT_SPRITE_TOP_1(1);
956 }
957 }
958
959 r600_store_context_reg_seq(&rs->buffer, R_028A00_PA_SU_POINT_SIZE, 3);
960 /* point size 12.4 fixed point (divide by two, because 0.5 = 1 pixel) */
961 tmp = r600_pack_float_12p4(state->point_size/2);
962 r600_store_value(&rs->buffer, /* R_028A00_PA_SU_POINT_SIZE */
963 S_028A00_HEIGHT(tmp) | S_028A00_WIDTH(tmp));
964 r600_store_value(&rs->buffer, /* R_028A04_PA_SU_POINT_MINMAX */
965 S_028A04_MIN_SIZE(r600_pack_float_12p4(psize_min/2)) |
966 S_028A04_MAX_SIZE(r600_pack_float_12p4(psize_max/2)));
967 r600_store_value(&rs->buffer, /* R_028A08_PA_SU_LINE_CNTL */
968 S_028A08_WIDTH((unsigned)(state->line_width * 8)));
969
970 r600_store_context_reg(&rs->buffer, R_0286D4_SPI_INTERP_CONTROL_0, spi_interp);
971 r600_store_context_reg(&rs->buffer, R_028A48_PA_SC_MODE_CNTL_0,
972 S_028A48_MSAA_ENABLE(state->multisample) |
973 S_028A48_VPORT_SCISSOR_ENABLE(state->scissor) |
974 S_028A48_LINE_STIPPLE_ENABLE(state->line_stipple_enable));
975
976 if (rctx->b.chip_class == CAYMAN) {
977 r600_store_context_reg(&rs->buffer, CM_R_028BE4_PA_SU_VTX_CNTL,
978 S_028C08_PIX_CENTER_HALF(state->half_pixel_center) |
979 S_028C08_QUANT_MODE(V_028C08_X_1_256TH));
980 } else {
981 r600_store_context_reg(&rs->buffer, R_028C08_PA_SU_VTX_CNTL,
982 S_028C08_PIX_CENTER_HALF(state->half_pixel_center) |
983 S_028C08_QUANT_MODE(V_028C08_X_1_256TH));
984 }
985
986 r600_store_context_reg(&rs->buffer, R_028B7C_PA_SU_POLY_OFFSET_CLAMP, fui(state->offset_clamp));
987 r600_store_context_reg(&rs->buffer, R_028814_PA_SU_SC_MODE_CNTL,
988 S_028814_PROVOKING_VTX_LAST(!state->flatshade_first) |
989 S_028814_CULL_FRONT((state->cull_face & PIPE_FACE_FRONT) ? 1 : 0) |
990 S_028814_CULL_BACK((state->cull_face & PIPE_FACE_BACK) ? 1 : 0) |
991 S_028814_FACE(!state->front_ccw) |
992 S_028814_POLY_OFFSET_FRONT_ENABLE(state->offset_tri) |
993 S_028814_POLY_OFFSET_BACK_ENABLE(state->offset_tri) |
994 S_028814_POLY_OFFSET_PARA_ENABLE(state->offset_tri) |
995 S_028814_POLY_MODE(state->fill_front != PIPE_POLYGON_MODE_FILL ||
996 state->fill_back != PIPE_POLYGON_MODE_FILL) |
997 S_028814_POLYMODE_FRONT_PTYPE(r600_translate_fill(state->fill_front)) |
998 S_028814_POLYMODE_BACK_PTYPE(r600_translate_fill(state->fill_back)));
999 r600_store_context_reg(&rs->buffer, R_028350_SX_MISC, S_028350_MULTIPASS(state->rasterizer_discard));
1000 return rs;
1001 }
1002
1003 static void *evergreen_create_sampler_state(struct pipe_context *ctx,
1004 const struct pipe_sampler_state *state)
1005 {
1006 struct r600_pipe_sampler_state *ss = CALLOC_STRUCT(r600_pipe_sampler_state);
1007 unsigned aniso_flag_offset = state->max_anisotropy > 1 ? 2 : 0;
1008
1009 if (ss == NULL) {
1010 return NULL;
1011 }
1012
1013 ss->border_color_use = sampler_state_needs_border_color(state);
1014
1015 /* R_03C000_SQ_TEX_SAMPLER_WORD0_0 */
1016 ss->tex_sampler_words[0] =
1017 S_03C000_CLAMP_X(r600_tex_wrap(state->wrap_s)) |
1018 S_03C000_CLAMP_Y(r600_tex_wrap(state->wrap_t)) |
1019 S_03C000_CLAMP_Z(r600_tex_wrap(state->wrap_r)) |
1020 S_03C000_XY_MAG_FILTER(r600_tex_filter(state->mag_img_filter) | aniso_flag_offset) |
1021 S_03C000_XY_MIN_FILTER(r600_tex_filter(state->min_img_filter) | aniso_flag_offset) |
1022 S_03C000_MIP_FILTER(r600_tex_mipfilter(state->min_mip_filter)) |
1023 S_03C000_MAX_ANISO(r600_tex_aniso_filter(state->max_anisotropy)) |
1024 S_03C000_DEPTH_COMPARE_FUNCTION(r600_tex_compare(state->compare_func)) |
1025 S_03C000_BORDER_COLOR_TYPE(ss->border_color_use ? V_03C000_SQ_TEX_BORDER_COLOR_REGISTER : 0);
1026 /* R_03C004_SQ_TEX_SAMPLER_WORD1_0 */
1027 ss->tex_sampler_words[1] =
1028 S_03C004_MIN_LOD(S_FIXED(CLAMP(state->min_lod, 0, 15), 8)) |
1029 S_03C004_MAX_LOD(S_FIXED(CLAMP(state->max_lod, 0, 15), 8));
1030 /* R_03C008_SQ_TEX_SAMPLER_WORD2_0 */
1031 ss->tex_sampler_words[2] =
1032 S_03C008_LOD_BIAS(S_FIXED(CLAMP(state->lod_bias, -16, 16), 8)) |
1033 (state->seamless_cube_map ? 0 : S_03C008_DISABLE_CUBE_WRAP(1)) |
1034 S_03C008_TYPE(1);
1035
1036 if (ss->border_color_use) {
1037 memcpy(&ss->border_color, &state->border_color, sizeof(state->border_color));
1038 }
1039 return ss;
1040 }
1041
1042 static struct pipe_sampler_view *
1043 texture_buffer_sampler_view(struct r600_pipe_sampler_view *view,
1044 unsigned width0, unsigned height0)
1045
1046 {
1047 struct pipe_context *ctx = view->base.context;
1048 struct r600_texture *tmp = (struct r600_texture*)view->base.texture;
1049 uint64_t va;
1050 int stride = util_format_get_blocksize(view->base.format);
1051 unsigned format, num_format, format_comp, endian;
1052 unsigned swizzle_res;
1053 unsigned char swizzle[4];
1054 const struct util_format_description *desc;
1055 unsigned offset = view->base.u.buf.first_element * stride;
1056 unsigned size = (view->base.u.buf.last_element - view->base.u.buf.first_element + 1) * stride;
1057
1058 swizzle[0] = view->base.swizzle_r;
1059 swizzle[1] = view->base.swizzle_g;
1060 swizzle[2] = view->base.swizzle_b;
1061 swizzle[3] = view->base.swizzle_a;
1062
1063 r600_vertex_data_type(view->base.format,
1064 &format, &num_format, &format_comp,
1065 &endian);
1066
1067 desc = util_format_description(view->base.format);
1068
1069 swizzle_res = r600_get_swizzle_combined(desc->swizzle, swizzle, TRUE);
1070
1071 va = r600_resource_va(ctx->screen, view->base.texture) + offset;
1072 view->tex_resource = &tmp->resource;
1073
1074 view->skip_mip_address_reloc = true;
1075 view->tex_resource_words[0] = va;
1076 view->tex_resource_words[1] = size - 1;
1077 view->tex_resource_words[2] = S_030008_BASE_ADDRESS_HI(va >> 32UL) |
1078 S_030008_STRIDE(stride) |
1079 S_030008_DATA_FORMAT(format) |
1080 S_030008_NUM_FORMAT_ALL(num_format) |
1081 S_030008_FORMAT_COMP_ALL(format_comp) |
1082 S_030008_SRF_MODE_ALL(1) |
1083 S_030008_ENDIAN_SWAP(endian);
1084 view->tex_resource_words[3] = swizzle_res;
1085 /*
1086 * in theory dword 4 is for number of elements, for use with resinfo,
1087 * but it seems to utterly fail to work, the amd gpu shader analyser
1088 * uses a const buffer to store the element sizes for buffer txq
1089 */
1090 view->tex_resource_words[4] = 0;
1091 view->tex_resource_words[5] = view->tex_resource_words[6] = 0;
1092 view->tex_resource_words[7] = S_03001C_TYPE(V_03001C_SQ_TEX_VTX_VALID_BUFFER);
1093 return &view->base;
1094 }
1095
1096 struct pipe_sampler_view *
1097 evergreen_create_sampler_view_custom(struct pipe_context *ctx,
1098 struct pipe_resource *texture,
1099 const struct pipe_sampler_view *state,
1100 unsigned width0, unsigned height0)
1101 {
1102 struct r600_screen *rscreen = (struct r600_screen*)ctx->screen;
1103 struct r600_pipe_sampler_view *view = CALLOC_STRUCT(r600_pipe_sampler_view);
1104 struct r600_texture *tmp = (struct r600_texture*)texture;
1105 unsigned format, endian;
1106 uint32_t word4 = 0, yuv_format = 0, pitch = 0;
1107 unsigned char swizzle[4], array_mode = 0, non_disp_tiling = 0;
1108 unsigned height, depth, width;
1109 unsigned macro_aspect, tile_split, bankh, bankw, nbanks, fmask_bankh;
1110 enum pipe_format pipe_format = state->format;
1111 struct radeon_surface_level *surflevel;
1112
1113 if (view == NULL)
1114 return NULL;
1115
1116 /* initialize base object */
1117 view->base = *state;
1118 view->base.texture = NULL;
1119 pipe_reference(NULL, &texture->reference);
1120 view->base.texture = texture;
1121 view->base.reference.count = 1;
1122 view->base.context = ctx;
1123
1124 if (texture->target == PIPE_BUFFER)
1125 return texture_buffer_sampler_view(view, width0, height0);
1126
1127 swizzle[0] = state->swizzle_r;
1128 swizzle[1] = state->swizzle_g;
1129 swizzle[2] = state->swizzle_b;
1130 swizzle[3] = state->swizzle_a;
1131
1132 tile_split = tmp->surface.tile_split;
1133 surflevel = tmp->surface.level;
1134
1135 /* Texturing with separate depth and stencil. */
1136 if (tmp->is_depth && !tmp->is_flushing_texture) {
1137 switch (pipe_format) {
1138 case PIPE_FORMAT_Z32_FLOAT_S8X24_UINT:
1139 pipe_format = PIPE_FORMAT_Z32_FLOAT;
1140 break;
1141 case PIPE_FORMAT_X8Z24_UNORM:
1142 case PIPE_FORMAT_S8_UINT_Z24_UNORM:
1143 /* Z24 is always stored like this. */
1144 pipe_format = PIPE_FORMAT_Z24X8_UNORM;
1145 break;
1146 case PIPE_FORMAT_X24S8_UINT:
1147 case PIPE_FORMAT_S8X24_UINT:
1148 case PIPE_FORMAT_X32_S8X24_UINT:
1149 pipe_format = PIPE_FORMAT_S8_UINT;
1150 tile_split = tmp->surface.stencil_tile_split;
1151 surflevel = tmp->surface.stencil_level;
1152 break;
1153 default:;
1154 }
1155 }
1156
1157 format = r600_translate_texformat(ctx->screen, pipe_format,
1158 swizzle,
1159 &word4, &yuv_format);
1160 assert(format != ~0);
1161 if (format == ~0) {
1162 FREE(view);
1163 return NULL;
1164 }
1165
1166 endian = r600_colorformat_endian_swap(format);
1167
1168 width = width0;
1169 height = height0;
1170 depth = texture->depth0;
1171 pitch = surflevel[0].nblk_x * util_format_get_blockwidth(pipe_format);
1172 non_disp_tiling = tmp->non_disp_tiling;
1173
1174 switch (surflevel[0].mode) {
1175 case RADEON_SURF_MODE_LINEAR_ALIGNED:
1176 array_mode = V_028C70_ARRAY_LINEAR_ALIGNED;
1177 break;
1178 case RADEON_SURF_MODE_2D:
1179 array_mode = V_028C70_ARRAY_2D_TILED_THIN1;
1180 break;
1181 case RADEON_SURF_MODE_1D:
1182 array_mode = V_028C70_ARRAY_1D_TILED_THIN1;
1183 break;
1184 case RADEON_SURF_MODE_LINEAR:
1185 default:
1186 array_mode = V_028C70_ARRAY_LINEAR_GENERAL;
1187 break;
1188 }
1189 macro_aspect = tmp->surface.mtilea;
1190 bankw = tmp->surface.bankw;
1191 bankh = tmp->surface.bankh;
1192 tile_split = eg_tile_split(tile_split);
1193 macro_aspect = eg_macro_tile_aspect(macro_aspect);
1194 bankw = eg_bank_wh(bankw);
1195 bankh = eg_bank_wh(bankh);
1196 fmask_bankh = eg_bank_wh(tmp->fmask.bank_height);
1197
1198 /* 128 bit formats require tile type = 1 */
1199 if (rscreen->b.chip_class == CAYMAN) {
1200 if (util_format_get_blocksize(pipe_format) >= 16)
1201 non_disp_tiling = 1;
1202 }
1203 nbanks = eg_num_banks(rscreen->b.tiling_info.num_banks);
1204
1205 if (texture->target == PIPE_TEXTURE_1D_ARRAY) {
1206 height = 1;
1207 depth = texture->array_size;
1208 } else if (texture->target == PIPE_TEXTURE_2D_ARRAY) {
1209 depth = texture->array_size;
1210 } else if (texture->target == PIPE_TEXTURE_CUBE_ARRAY)
1211 depth = texture->array_size / 6;
1212
1213 view->tex_resource = &tmp->resource;
1214 view->tex_resource_words[0] = (S_030000_DIM(r600_tex_dim(texture->target, texture->nr_samples)) |
1215 S_030000_PITCH((pitch / 8) - 1) |
1216 S_030000_TEX_WIDTH(width - 1));
1217 if (rscreen->b.chip_class == CAYMAN)
1218 view->tex_resource_words[0] |= CM_S_030000_NON_DISP_TILING_ORDER(non_disp_tiling);
1219 else
1220 view->tex_resource_words[0] |= S_030000_NON_DISP_TILING_ORDER(non_disp_tiling);
1221 view->tex_resource_words[1] = (S_030004_TEX_HEIGHT(height - 1) |
1222 S_030004_TEX_DEPTH(depth - 1) |
1223 S_030004_ARRAY_MODE(array_mode));
1224 view->tex_resource_words[2] = (surflevel[0].offset + r600_resource_va(ctx->screen, texture)) >> 8;
1225
1226 /* TEX_RESOURCE_WORD3.MIP_ADDRESS */
1227 if (texture->nr_samples > 1 && rscreen->has_compressed_msaa_texturing) {
1228 if (tmp->is_depth) {
1229 /* disable FMASK (0 = disabled) */
1230 view->tex_resource_words[3] = 0;
1231 view->skip_mip_address_reloc = true;
1232 } else {
1233 /* FMASK should be in MIP_ADDRESS for multisample textures */
1234 view->tex_resource_words[3] = (tmp->fmask.offset + r600_resource_va(ctx->screen, texture)) >> 8;
1235 }
1236 } else if (state->u.tex.last_level && texture->nr_samples <= 1) {
1237 view->tex_resource_words[3] = (surflevel[1].offset + r600_resource_va(ctx->screen, texture)) >> 8;
1238 } else {
1239 view->tex_resource_words[3] = (surflevel[0].offset + r600_resource_va(ctx->screen, texture)) >> 8;
1240 }
1241
1242 view->tex_resource_words[4] = (word4 |
1243 S_030010_SRF_MODE_ALL(V_030010_SRF_MODE_ZERO_CLAMP_MINUS_ONE) |
1244 S_030010_ENDIAN_SWAP(endian));
1245 view->tex_resource_words[5] = S_030014_BASE_ARRAY(state->u.tex.first_layer) |
1246 S_030014_LAST_ARRAY(state->u.tex.last_layer);
1247 view->tex_resource_words[6] = S_030018_TILE_SPLIT(tile_split);
1248
1249 if (texture->nr_samples > 1) {
1250 unsigned log_samples = util_logbase2(texture->nr_samples);
1251 if (rscreen->b.chip_class == CAYMAN) {
1252 view->tex_resource_words[4] |= S_030010_LOG2_NUM_FRAGMENTS(log_samples);
1253 }
1254 /* LAST_LEVEL holds log2(nr_samples) for multisample textures */
1255 view->tex_resource_words[5] |= S_030014_LAST_LEVEL(log_samples);
1256 view->tex_resource_words[6] |= S_030018_FMASK_BANK_HEIGHT(fmask_bankh);
1257 } else {
1258 view->tex_resource_words[4] |= S_030010_BASE_LEVEL(state->u.tex.first_level);
1259 view->tex_resource_words[5] |= S_030014_LAST_LEVEL(state->u.tex.last_level);
1260 /* aniso max 16 samples */
1261 view->tex_resource_words[6] |= S_030018_MAX_ANISO(4);
1262 }
1263
1264 view->tex_resource_words[7] = S_03001C_DATA_FORMAT(format) |
1265 S_03001C_TYPE(V_03001C_SQ_TEX_VTX_VALID_TEXTURE) |
1266 S_03001C_BANK_WIDTH(bankw) |
1267 S_03001C_BANK_HEIGHT(bankh) |
1268 S_03001C_MACRO_TILE_ASPECT(macro_aspect) |
1269 S_03001C_NUM_BANKS(nbanks) |
1270 S_03001C_DEPTH_SAMPLE_ORDER(tmp->is_depth && !tmp->is_flushing_texture);
1271 return &view->base;
1272 }
1273
1274 static struct pipe_sampler_view *
1275 evergreen_create_sampler_view(struct pipe_context *ctx,
1276 struct pipe_resource *tex,
1277 const struct pipe_sampler_view *state)
1278 {
1279 return evergreen_create_sampler_view_custom(ctx, tex, state,
1280 tex->width0, tex->height0);
1281 }
1282
1283 static void evergreen_emit_clip_state(struct r600_context *rctx, struct r600_atom *atom)
1284 {
1285 struct radeon_winsys_cs *cs = rctx->b.rings.gfx.cs;
1286 struct pipe_clip_state *state = &rctx->clip_state.state;
1287
1288 r600_write_context_reg_seq(cs, R_0285BC_PA_CL_UCP0_X, 6*4);
1289 radeon_emit_array(cs, (unsigned*)state, 6*4);
1290 }
1291
1292 static void evergreen_set_polygon_stipple(struct pipe_context *ctx,
1293 const struct pipe_poly_stipple *state)
1294 {
1295 }
1296
1297 static void evergreen_get_scissor_rect(struct r600_context *rctx,
1298 unsigned tl_x, unsigned tl_y, unsigned br_x, unsigned br_y,
1299 uint32_t *tl, uint32_t *br)
1300 {
1301 /* EG hw workaround */
1302 if (br_x == 0)
1303 tl_x = 1;
1304 if (br_y == 0)
1305 tl_y = 1;
1306
1307 /* cayman hw workaround */
1308 if (rctx->b.chip_class == CAYMAN) {
1309 if (br_x == 1 && br_y == 1)
1310 br_x = 2;
1311 }
1312
1313 *tl = S_028240_TL_X(tl_x) | S_028240_TL_Y(tl_y);
1314 *br = S_028244_BR_X(br_x) | S_028244_BR_Y(br_y);
1315 }
1316
1317 static void evergreen_set_scissor_states(struct pipe_context *ctx,
1318 unsigned start_slot,
1319 unsigned num_scissors,
1320 const struct pipe_scissor_state *state)
1321 {
1322 struct r600_context *rctx = (struct r600_context *)ctx;
1323
1324 rctx->scissor.scissor = *state;
1325 rctx->scissor.atom.dirty = true;
1326 }
1327
1328 static void evergreen_emit_scissor_state(struct r600_context *rctx, struct r600_atom *atom)
1329 {
1330 struct radeon_winsys_cs *cs = rctx->b.rings.gfx.cs;
1331 struct pipe_scissor_state *state = &rctx->scissor.scissor;
1332 uint32_t tl, br;
1333
1334 evergreen_get_scissor_rect(rctx, state->minx, state->miny, state->maxx, state->maxy, &tl, &br);
1335
1336 r600_write_context_reg_seq(cs, R_028250_PA_SC_VPORT_SCISSOR_0_TL, 2);
1337 radeon_emit(cs, tl);
1338 radeon_emit(cs, br);
1339 }
1340
1341 /**
1342 * This function intializes the CB* register values for RATs. It is meant
1343 * to be used for 1D aligned buffers that do not have an associated
1344 * radeon_surface.
1345 */
1346 void evergreen_init_color_surface_rat(struct r600_context *rctx,
1347 struct r600_surface *surf)
1348 {
1349 struct pipe_resource *pipe_buffer = surf->base.texture;
1350 unsigned format = r600_translate_colorformat(surf->base.format);
1351 unsigned endian = r600_colorformat_endian_swap(format);
1352 unsigned swap = r600_translate_colorswap(surf->base.format);
1353 unsigned block_size =
1354 align(util_format_get_blocksize(pipe_buffer->format), 4);
1355 unsigned pitch_alignment =
1356 MAX2(64, rctx->screen->b.tiling_info.group_bytes / block_size);
1357 unsigned pitch = align(pipe_buffer->width0, pitch_alignment);
1358
1359 /* XXX: This is copied from evergreen_init_color_surface(). I don't
1360 * know why this is necessary.
1361 */
1362 if (pipe_buffer->usage == PIPE_USAGE_STAGING) {
1363 endian = ENDIAN_NONE;
1364 }
1365
1366 surf->cb_color_base =
1367 r600_resource_va(rctx->b.b.screen, pipe_buffer) >> 8;
1368
1369 surf->cb_color_pitch = (pitch / 8) - 1;
1370
1371 surf->cb_color_slice = 0;
1372
1373 surf->cb_color_view = 0;
1374
1375 surf->cb_color_info =
1376 S_028C70_ENDIAN(endian)
1377 | S_028C70_FORMAT(format)
1378 | S_028C70_ARRAY_MODE(V_028C70_ARRAY_LINEAR_ALIGNED)
1379 | S_028C70_NUMBER_TYPE(V_028C70_NUMBER_UINT)
1380 | S_028C70_COMP_SWAP(swap)
1381 | S_028C70_BLEND_BYPASS(1) /* We must set this bit because we
1382 * are using NUMBER_UINT */
1383 | S_028C70_RAT(1)
1384 ;
1385
1386 surf->cb_color_attrib = S_028C74_NON_DISP_TILING_ORDER(1);
1387
1388 /* For buffers, CB_COLOR0_DIM needs to be set to the number of
1389 * elements. */
1390 surf->cb_color_dim = pipe_buffer->width0;
1391
1392 /* Set the buffer range the GPU will have access to: */
1393 util_range_add(&r600_resource(pipe_buffer)->valid_buffer_range,
1394 0, pipe_buffer->width0);
1395
1396 surf->cb_color_cmask = surf->cb_color_base;
1397 surf->cb_color_cmask_slice = 0;
1398 surf->cb_color_fmask = surf->cb_color_base;
1399 surf->cb_color_fmask_slice = 0;
1400 }
1401
1402 void evergreen_init_color_surface(struct r600_context *rctx,
1403 struct r600_surface *surf)
1404 {
1405 struct r600_screen *rscreen = rctx->screen;
1406 struct r600_texture *rtex = (struct r600_texture*)surf->base.texture;
1407 struct pipe_resource *pipe_tex = surf->base.texture;
1408 unsigned level = surf->base.u.tex.level;
1409 unsigned pitch, slice;
1410 unsigned color_info, color_attrib, color_dim = 0;
1411 unsigned format, swap, ntype, endian;
1412 uint64_t offset, base_offset;
1413 unsigned non_disp_tiling, macro_aspect, tile_split, bankh, bankw, fmask_bankh, nbanks;
1414 const struct util_format_description *desc;
1415 int i;
1416 bool blend_clamp = 0, blend_bypass = 0;
1417
1418 offset = rtex->surface.level[level].offset;
1419 if (rtex->surface.level[level].mode < RADEON_SURF_MODE_1D) {
1420 offset += rtex->surface.level[level].slice_size *
1421 surf->base.u.tex.first_layer;
1422 }
1423 pitch = (rtex->surface.level[level].nblk_x) / 8 - 1;
1424 slice = (rtex->surface.level[level].nblk_x * rtex->surface.level[level].nblk_y) / 64;
1425 if (slice) {
1426 slice = slice - 1;
1427 }
1428 color_info = 0;
1429 switch (rtex->surface.level[level].mode) {
1430 case RADEON_SURF_MODE_LINEAR_ALIGNED:
1431 color_info = S_028C70_ARRAY_MODE(V_028C70_ARRAY_LINEAR_ALIGNED);
1432 non_disp_tiling = 1;
1433 break;
1434 case RADEON_SURF_MODE_1D:
1435 color_info = S_028C70_ARRAY_MODE(V_028C70_ARRAY_1D_TILED_THIN1);
1436 non_disp_tiling = rtex->non_disp_tiling;
1437 break;
1438 case RADEON_SURF_MODE_2D:
1439 color_info = S_028C70_ARRAY_MODE(V_028C70_ARRAY_2D_TILED_THIN1);
1440 non_disp_tiling = rtex->non_disp_tiling;
1441 break;
1442 case RADEON_SURF_MODE_LINEAR:
1443 default:
1444 color_info = S_028C70_ARRAY_MODE(V_028C70_ARRAY_LINEAR_GENERAL);
1445 non_disp_tiling = 1;
1446 break;
1447 }
1448 tile_split = rtex->surface.tile_split;
1449 macro_aspect = rtex->surface.mtilea;
1450 bankw = rtex->surface.bankw;
1451 bankh = rtex->surface.bankh;
1452 fmask_bankh = rtex->fmask.bank_height;
1453 tile_split = eg_tile_split(tile_split);
1454 macro_aspect = eg_macro_tile_aspect(macro_aspect);
1455 bankw = eg_bank_wh(bankw);
1456 bankh = eg_bank_wh(bankh);
1457 fmask_bankh = eg_bank_wh(fmask_bankh);
1458
1459 /* 128 bit formats require tile type = 1 */
1460 if (rscreen->b.chip_class == CAYMAN) {
1461 if (util_format_get_blocksize(surf->base.format) >= 16)
1462 non_disp_tiling = 1;
1463 }
1464 nbanks = eg_num_banks(rscreen->b.tiling_info.num_banks);
1465 desc = util_format_description(surf->base.format);
1466 for (i = 0; i < 4; i++) {
1467 if (desc->channel[i].type != UTIL_FORMAT_TYPE_VOID) {
1468 break;
1469 }
1470 }
1471
1472 color_attrib = S_028C74_TILE_SPLIT(tile_split)|
1473 S_028C74_NUM_BANKS(nbanks) |
1474 S_028C74_BANK_WIDTH(bankw) |
1475 S_028C74_BANK_HEIGHT(bankh) |
1476 S_028C74_MACRO_TILE_ASPECT(macro_aspect) |
1477 S_028C74_NON_DISP_TILING_ORDER(non_disp_tiling) |
1478 S_028C74_FMASK_BANK_HEIGHT(fmask_bankh);
1479
1480 if (rctx->b.chip_class == CAYMAN) {
1481 color_attrib |= S_028C74_FORCE_DST_ALPHA_1(desc->swizzle[3] ==
1482 UTIL_FORMAT_SWIZZLE_1);
1483
1484 if (rtex->resource.b.b.nr_samples > 1) {
1485 unsigned log_samples = util_logbase2(rtex->resource.b.b.nr_samples);
1486 color_attrib |= S_028C74_NUM_SAMPLES(log_samples) |
1487 S_028C74_NUM_FRAGMENTS(log_samples);
1488 }
1489 }
1490
1491 ntype = V_028C70_NUMBER_UNORM;
1492 if (desc->colorspace == UTIL_FORMAT_COLORSPACE_SRGB)
1493 ntype = V_028C70_NUMBER_SRGB;
1494 else if (desc->channel[i].type == UTIL_FORMAT_TYPE_SIGNED) {
1495 if (desc->channel[i].normalized)
1496 ntype = V_028C70_NUMBER_SNORM;
1497 else if (desc->channel[i].pure_integer)
1498 ntype = V_028C70_NUMBER_SINT;
1499 } else if (desc->channel[i].type == UTIL_FORMAT_TYPE_UNSIGNED) {
1500 if (desc->channel[i].normalized)
1501 ntype = V_028C70_NUMBER_UNORM;
1502 else if (desc->channel[i].pure_integer)
1503 ntype = V_028C70_NUMBER_UINT;
1504 }
1505
1506 format = r600_translate_colorformat(surf->base.format);
1507 assert(format != ~0);
1508
1509 swap = r600_translate_colorswap(surf->base.format);
1510 assert(swap != ~0);
1511
1512 if (rtex->resource.b.b.usage == PIPE_USAGE_STAGING) {
1513 endian = ENDIAN_NONE;
1514 } else {
1515 endian = r600_colorformat_endian_swap(format);
1516 }
1517
1518 /* blend clamp should be set for all NORM/SRGB types */
1519 if (ntype == V_028C70_NUMBER_UNORM || ntype == V_028C70_NUMBER_SNORM ||
1520 ntype == V_028C70_NUMBER_SRGB)
1521 blend_clamp = 1;
1522
1523 /* set blend bypass according to docs if SINT/UINT or
1524 8/24 COLOR variants */
1525 if (ntype == V_028C70_NUMBER_UINT || ntype == V_028C70_NUMBER_SINT ||
1526 format == V_028C70_COLOR_8_24 || format == V_028C70_COLOR_24_8 ||
1527 format == V_028C70_COLOR_X24_8_32_FLOAT) {
1528 blend_clamp = 0;
1529 blend_bypass = 1;
1530 }
1531
1532 surf->alphatest_bypass = ntype == V_028C70_NUMBER_UINT || ntype == V_028C70_NUMBER_SINT;
1533
1534 color_info |= S_028C70_FORMAT(format) |
1535 S_028C70_COMP_SWAP(swap) |
1536 S_028C70_BLEND_CLAMP(blend_clamp) |
1537 S_028C70_BLEND_BYPASS(blend_bypass) |
1538 S_028C70_NUMBER_TYPE(ntype) |
1539 S_028C70_ENDIAN(endian);
1540
1541 /* EXPORT_NORM is an optimzation that can be enabled for better
1542 * performance in certain cases.
1543 * EXPORT_NORM can be enabled if:
1544 * - 11-bit or smaller UNORM/SNORM/SRGB
1545 * - 16-bit or smaller FLOAT
1546 */
1547 if (desc->colorspace != UTIL_FORMAT_COLORSPACE_ZS &&
1548 ((desc->channel[i].size < 12 &&
1549 desc->channel[i].type != UTIL_FORMAT_TYPE_FLOAT &&
1550 ntype != V_028C70_NUMBER_UINT && ntype != V_028C70_NUMBER_SINT) ||
1551 (desc->channel[i].size < 17 &&
1552 desc->channel[i].type == UTIL_FORMAT_TYPE_FLOAT))) {
1553 color_info |= S_028C70_SOURCE_FORMAT(V_028C70_EXPORT_4C_16BPC);
1554 surf->export_16bpc = true;
1555 }
1556
1557 if (rtex->fmask.size) {
1558 color_info |= S_028C70_COMPRESSION(1);
1559 }
1560 if (rtex->cmask.size) {
1561 color_info |= S_028C70_FAST_CLEAR(1);
1562 }
1563
1564 base_offset = r600_resource_va(rctx->b.b.screen, pipe_tex);
1565
1566 /* XXX handle enabling of CB beyond BASE8 which has different offset */
1567 surf->cb_color_base = (base_offset + offset) >> 8;
1568 surf->cb_color_dim = color_dim;
1569 surf->cb_color_info = color_info;
1570 surf->cb_color_pitch = S_028C64_PITCH_TILE_MAX(pitch);
1571 surf->cb_color_slice = S_028C68_SLICE_TILE_MAX(slice);
1572 if (rtex->surface.level[level].mode < RADEON_SURF_MODE_1D) {
1573 surf->cb_color_view = 0;
1574 } else {
1575 surf->cb_color_view = S_028C6C_SLICE_START(surf->base.u.tex.first_layer) |
1576 S_028C6C_SLICE_MAX(surf->base.u.tex.last_layer);
1577 }
1578 surf->cb_color_attrib = color_attrib;
1579 if (rtex->fmask.size) {
1580 surf->cb_color_fmask = (base_offset + rtex->fmask.offset) >> 8;
1581 } else {
1582 surf->cb_color_fmask = surf->cb_color_base;
1583 }
1584 if (rtex->cmask.size) {
1585 uint64_t va = r600_resource_va(rctx->b.b.screen, &rtex->cmask_buffer->b.b);
1586 surf->cb_color_cmask = (va + rtex->cmask.offset) >> 8;
1587 } else {
1588 surf->cb_color_cmask = surf->cb_color_base;
1589 }
1590 surf->cb_color_fmask_slice = S_028C88_TILE_MAX(rtex->fmask.slice_tile_max);
1591 surf->cb_color_cmask_slice = S_028C80_TILE_MAX(rtex->cmask.slice_tile_max);
1592
1593 surf->color_initialized = true;
1594 }
1595
1596 static void evergreen_init_depth_surface(struct r600_context *rctx,
1597 struct r600_surface *surf)
1598 {
1599 struct r600_screen *rscreen = rctx->screen;
1600 struct pipe_screen *screen = &rscreen->b.b;
1601 struct r600_texture *rtex = (struct r600_texture*)surf->base.texture;
1602 uint64_t offset;
1603 unsigned level, pitch, slice, format, array_mode;
1604 unsigned macro_aspect, tile_split, bankh, bankw, nbanks;
1605
1606 level = surf->base.u.tex.level;
1607 format = r600_translate_dbformat(surf->base.format);
1608 assert(format != ~0);
1609
1610 offset = r600_resource_va(screen, surf->base.texture);
1611 offset += rtex->surface.level[level].offset;
1612 pitch = (rtex->surface.level[level].nblk_x / 8) - 1;
1613 slice = (rtex->surface.level[level].nblk_x * rtex->surface.level[level].nblk_y) / 64;
1614 if (slice) {
1615 slice = slice - 1;
1616 }
1617 switch (rtex->surface.level[level].mode) {
1618 case RADEON_SURF_MODE_2D:
1619 array_mode = V_028C70_ARRAY_2D_TILED_THIN1;
1620 break;
1621 case RADEON_SURF_MODE_1D:
1622 case RADEON_SURF_MODE_LINEAR_ALIGNED:
1623 case RADEON_SURF_MODE_LINEAR:
1624 default:
1625 array_mode = V_028C70_ARRAY_1D_TILED_THIN1;
1626 break;
1627 }
1628 tile_split = rtex->surface.tile_split;
1629 macro_aspect = rtex->surface.mtilea;
1630 bankw = rtex->surface.bankw;
1631 bankh = rtex->surface.bankh;
1632 tile_split = eg_tile_split(tile_split);
1633 macro_aspect = eg_macro_tile_aspect(macro_aspect);
1634 bankw = eg_bank_wh(bankw);
1635 bankh = eg_bank_wh(bankh);
1636 nbanks = eg_num_banks(rscreen->b.tiling_info.num_banks);
1637 offset >>= 8;
1638
1639 surf->db_depth_info = S_028040_ARRAY_MODE(array_mode) |
1640 S_028040_FORMAT(format) |
1641 S_028040_TILE_SPLIT(tile_split)|
1642 S_028040_NUM_BANKS(nbanks) |
1643 S_028040_BANK_WIDTH(bankw) |
1644 S_028040_BANK_HEIGHT(bankh) |
1645 S_028040_MACRO_TILE_ASPECT(macro_aspect);
1646 if (rscreen->b.chip_class == CAYMAN && rtex->resource.b.b.nr_samples > 1) {
1647 surf->db_depth_info |= S_028040_NUM_SAMPLES(util_logbase2(rtex->resource.b.b.nr_samples));
1648 }
1649 surf->db_depth_base = offset;
1650 surf->db_depth_view = S_028008_SLICE_START(surf->base.u.tex.first_layer) |
1651 S_028008_SLICE_MAX(surf->base.u.tex.last_layer);
1652 surf->db_depth_size = S_028058_PITCH_TILE_MAX(pitch);
1653 surf->db_depth_slice = S_02805C_SLICE_TILE_MAX(slice);
1654
1655 switch (surf->base.format) {
1656 case PIPE_FORMAT_Z24X8_UNORM:
1657 case PIPE_FORMAT_Z24_UNORM_S8_UINT:
1658 case PIPE_FORMAT_X8Z24_UNORM:
1659 case PIPE_FORMAT_S8_UINT_Z24_UNORM:
1660 surf->pa_su_poly_offset_db_fmt_cntl =
1661 S_028B78_POLY_OFFSET_NEG_NUM_DB_BITS((char)-24);
1662 break;
1663 case PIPE_FORMAT_Z32_FLOAT:
1664 case PIPE_FORMAT_Z32_FLOAT_S8X24_UINT:
1665 surf->pa_su_poly_offset_db_fmt_cntl =
1666 S_028B78_POLY_OFFSET_NEG_NUM_DB_BITS((char)-23) |
1667 S_028B78_POLY_OFFSET_DB_IS_FLOAT_FMT(1);
1668 break;
1669 case PIPE_FORMAT_Z16_UNORM:
1670 surf->pa_su_poly_offset_db_fmt_cntl =
1671 S_028B78_POLY_OFFSET_NEG_NUM_DB_BITS((char)-16);
1672 break;
1673 default:;
1674 }
1675
1676 if (rtex->surface.flags & RADEON_SURF_SBUFFER) {
1677 uint64_t stencil_offset;
1678 unsigned stile_split = rtex->surface.stencil_tile_split;
1679
1680 stile_split = eg_tile_split(stile_split);
1681
1682 stencil_offset = rtex->surface.stencil_level[level].offset;
1683 stencil_offset += r600_resource_va(screen, surf->base.texture);
1684
1685 surf->db_stencil_base = stencil_offset >> 8;
1686 surf->db_stencil_info = S_028044_FORMAT(V_028044_STENCIL_8) |
1687 S_028044_TILE_SPLIT(stile_split);
1688 } else {
1689 surf->db_stencil_base = offset;
1690 /* DRM 2.6.18 allows the INVALID format to disable stencil.
1691 * Older kernels are out of luck. */
1692 surf->db_stencil_info = rctx->screen->b.info.drm_minor >= 18 ?
1693 S_028044_FORMAT(V_028044_STENCIL_INVALID) :
1694 S_028044_FORMAT(V_028044_STENCIL_8);
1695 }
1696
1697 surf->htile_enabled = 0;
1698 /* use htile only for first level */
1699 if (rtex->htile_buffer && !level) {
1700 uint64_t va = r600_resource_va(&rctx->screen->b.b, &rtex->htile_buffer->b.b);
1701 surf->htile_enabled = 1;
1702 surf->db_htile_data_base = va >> 8;
1703 surf->db_htile_surface = S_028ABC_HTILE_WIDTH(1) |
1704 S_028ABC_HTILE_HEIGHT(1) |
1705 S_028ABC_FULL_CACHE(1) |
1706 S_028ABC_LINEAR(1);
1707 surf->db_depth_info |= S_028040_TILE_SURFACE_ENABLE(1);
1708 surf->db_preload_control = 0;
1709 }
1710
1711 surf->depth_initialized = true;
1712 }
1713
1714 static void evergreen_set_framebuffer_state(struct pipe_context *ctx,
1715 const struct pipe_framebuffer_state *state)
1716 {
1717 struct r600_context *rctx = (struct r600_context *)ctx;
1718 struct r600_surface *surf;
1719 struct r600_texture *rtex;
1720 uint32_t i, log_samples;
1721
1722 if (rctx->framebuffer.state.nr_cbufs) {
1723 rctx->b.flags |= R600_CONTEXT_WAIT_3D_IDLE | R600_CONTEXT_FLUSH_AND_INV;
1724 rctx->b.flags |= R600_CONTEXT_FLUSH_AND_INV_CB |
1725 R600_CONTEXT_FLUSH_AND_INV_CB_META;
1726 }
1727 if (rctx->framebuffer.state.zsbuf) {
1728 rctx->b.flags |= R600_CONTEXT_WAIT_3D_IDLE | R600_CONTEXT_FLUSH_AND_INV;
1729 rctx->b.flags |= R600_CONTEXT_FLUSH_AND_INV_DB;
1730
1731 rtex = (struct r600_texture*)rctx->framebuffer.state.zsbuf->texture;
1732 if (rtex->htile_buffer) {
1733 rctx->b.flags |= R600_CONTEXT_FLUSH_AND_INV_DB_META;
1734 }
1735 }
1736
1737 util_copy_framebuffer_state(&rctx->framebuffer.state, state);
1738
1739 /* Colorbuffers. */
1740 rctx->framebuffer.export_16bpc = state->nr_cbufs != 0;
1741 rctx->framebuffer.cb0_is_integer = state->nr_cbufs && state->cbufs[0] &&
1742 util_format_is_pure_integer(state->cbufs[0]->format);
1743 rctx->framebuffer.compressed_cb_mask = 0;
1744 rctx->framebuffer.nr_samples = util_framebuffer_get_num_samples(state);
1745
1746 for (i = 0; i < state->nr_cbufs; i++) {
1747 surf = (struct r600_surface*)state->cbufs[i];
1748 if (!surf)
1749 continue;
1750
1751 rtex = (struct r600_texture*)surf->base.texture;
1752
1753 r600_context_add_resource_size(ctx, state->cbufs[i]->texture);
1754
1755 if (!surf->color_initialized) {
1756 evergreen_init_color_surface(rctx, surf);
1757 }
1758
1759 if (!surf->export_16bpc) {
1760 rctx->framebuffer.export_16bpc = false;
1761 }
1762
1763 if (rtex->fmask.size && rtex->cmask.size) {
1764 rctx->framebuffer.compressed_cb_mask |= 1 << i;
1765 }
1766 }
1767
1768 /* Update alpha-test state dependencies.
1769 * Alpha-test is done on the first colorbuffer only. */
1770 if (state->nr_cbufs) {
1771 bool alphatest_bypass = false;
1772 bool export_16bpc = true;
1773
1774 surf = (struct r600_surface*)state->cbufs[0];
1775 if (surf) {
1776 alphatest_bypass = surf->alphatest_bypass;
1777 export_16bpc = surf->export_16bpc;
1778 }
1779
1780 if (rctx->alphatest_state.bypass != alphatest_bypass) {
1781 rctx->alphatest_state.bypass = alphatest_bypass;
1782 rctx->alphatest_state.atom.dirty = true;
1783 }
1784 if (rctx->alphatest_state.cb0_export_16bpc != export_16bpc) {
1785 rctx->alphatest_state.cb0_export_16bpc = export_16bpc;
1786 rctx->alphatest_state.atom.dirty = true;
1787 }
1788 }
1789
1790 /* ZS buffer. */
1791 if (state->zsbuf) {
1792 surf = (struct r600_surface*)state->zsbuf;
1793
1794 r600_context_add_resource_size(ctx, state->zsbuf->texture);
1795
1796 if (!surf->depth_initialized) {
1797 evergreen_init_depth_surface(rctx, surf);
1798 }
1799
1800 if (state->zsbuf->format != rctx->poly_offset_state.zs_format) {
1801 rctx->poly_offset_state.zs_format = state->zsbuf->format;
1802 rctx->poly_offset_state.atom.dirty = true;
1803 }
1804
1805 if (rctx->db_state.rsurf != surf) {
1806 rctx->db_state.rsurf = surf;
1807 rctx->db_state.atom.dirty = true;
1808 rctx->db_misc_state.atom.dirty = true;
1809 }
1810 } else if (rctx->db_state.rsurf) {
1811 rctx->db_state.rsurf = NULL;
1812 rctx->db_state.atom.dirty = true;
1813 rctx->db_misc_state.atom.dirty = true;
1814 }
1815
1816 if (rctx->cb_misc_state.nr_cbufs != state->nr_cbufs) {
1817 rctx->cb_misc_state.nr_cbufs = state->nr_cbufs;
1818 rctx->cb_misc_state.atom.dirty = true;
1819 }
1820
1821 if (state->nr_cbufs == 0 && rctx->alphatest_state.bypass) {
1822 rctx->alphatest_state.bypass = false;
1823 rctx->alphatest_state.atom.dirty = true;
1824 }
1825
1826 log_samples = util_logbase2(rctx->framebuffer.nr_samples);
1827 if (rctx->b.chip_class == CAYMAN && rctx->db_misc_state.log_samples != log_samples) {
1828 rctx->db_misc_state.log_samples = log_samples;
1829 rctx->db_misc_state.atom.dirty = true;
1830 }
1831
1832
1833 /* Calculate the CS size. */
1834 rctx->framebuffer.atom.num_dw = 4; /* SCISSOR */
1835
1836 /* MSAA. */
1837 if (rctx->b.chip_class == EVERGREEN) {
1838 switch (rctx->framebuffer.nr_samples) {
1839 case 2:
1840 case 4:
1841 rctx->framebuffer.atom.num_dw += 6;
1842 break;
1843 case 8:
1844 rctx->framebuffer.atom.num_dw += 10;
1845 break;
1846 }
1847 rctx->framebuffer.atom.num_dw += 4;
1848 } else {
1849 switch (rctx->framebuffer.nr_samples) {
1850 case 2:
1851 case 4:
1852 rctx->framebuffer.atom.num_dw += 12;
1853 break;
1854 case 8:
1855 rctx->framebuffer.atom.num_dw += 16;
1856 break;
1857 case 16:
1858 rctx->framebuffer.atom.num_dw += 18;
1859 break;
1860 }
1861 rctx->framebuffer.atom.num_dw += 7;
1862 }
1863
1864 /* Colorbuffers. */
1865 rctx->framebuffer.atom.num_dw += state->nr_cbufs * 23;
1866 if (rctx->keep_tiling_flags)
1867 rctx->framebuffer.atom.num_dw += state->nr_cbufs * 2;
1868 rctx->framebuffer.atom.num_dw += (12 - state->nr_cbufs) * 3;
1869
1870 /* ZS buffer. */
1871 if (state->zsbuf) {
1872 rctx->framebuffer.atom.num_dw += 24;
1873 if (rctx->keep_tiling_flags)
1874 rctx->framebuffer.atom.num_dw += 2;
1875 } else if (rctx->screen->b.info.drm_minor >= 18) {
1876 rctx->framebuffer.atom.num_dw += 4;
1877 }
1878
1879 rctx->framebuffer.atom.dirty = true;
1880 }
1881
1882 #define FILL_SREG(s0x, s0y, s1x, s1y, s2x, s2y, s3x, s3y) \
1883 (((s0x) & 0xf) | (((s0y) & 0xf) << 4) | \
1884 (((s1x) & 0xf) << 8) | (((s1y) & 0xf) << 12) | \
1885 (((s2x) & 0xf) << 16) | (((s2y) & 0xf) << 20) | \
1886 (((s3x) & 0xf) << 24) | (((s3y) & 0xf) << 28))
1887
1888 /* 2xMSAA
1889 * There are two locations (-4, 4), (4, -4). */
1890 static uint32_t sample_locs_2x[] = {
1891 FILL_SREG(-4, 4, 4, -4, -4, 4, 4, -4),
1892 FILL_SREG(-4, 4, 4, -4, -4, 4, 4, -4),
1893 FILL_SREG(-4, 4, 4, -4, -4, 4, 4, -4),
1894 FILL_SREG(-4, 4, 4, -4, -4, 4, 4, -4),
1895 };
1896 static unsigned max_dist_2x = 4;
1897 /* 4xMSAA
1898 * There are 4 locations: (-2, -2), (2, 2), (-6, 6), (6, -6). */
1899 static uint32_t sample_locs_4x[] = {
1900 FILL_SREG(-2, -2, 2, 2, -6, 6, 6, -6),
1901 FILL_SREG(-2, -2, 2, 2, -6, 6, 6, -6),
1902 FILL_SREG(-2, -2, 2, 2, -6, 6, 6, -6),
1903 FILL_SREG(-2, -2, 2, 2, -6, 6, 6, -6),
1904 };
1905 static unsigned max_dist_4x = 6;
1906 /* 8xMSAA */
1907 static uint32_t sample_locs_8x[] = {
1908 FILL_SREG(-1, 1, 1, 5, 3, -5, 5, 3),
1909 FILL_SREG(-7, -1, -3, -7, 7, -3, -5, 7),
1910 FILL_SREG(-1, 1, 1, 5, 3, -5, 5, 3),
1911 FILL_SREG(-7, -1, -3, -7, 7, -3, -5, 7),
1912 FILL_SREG(-1, 1, 1, 5, 3, -5, 5, 3),
1913 FILL_SREG(-7, -1, -3, -7, 7, -3, -5, 7),
1914 FILL_SREG(-1, 1, 1, 5, 3, -5, 5, 3),
1915 FILL_SREG(-7, -1, -3, -7, 7, -3, -5, 7),
1916 };
1917 static unsigned max_dist_8x = 7;
1918
1919 static void evergreen_get_sample_position(struct pipe_context *ctx,
1920 unsigned sample_count,
1921 unsigned sample_index,
1922 float *out_value)
1923 {
1924 int offset, index;
1925 struct {
1926 int idx:4;
1927 } val;
1928 switch (sample_count) {
1929 case 1:
1930 default:
1931 out_value[0] = out_value[1] = 0.5;
1932 break;
1933 case 2:
1934 offset = 4 * (sample_index * 2);
1935 val.idx = (sample_locs_2x[0] >> offset) & 0xf;
1936 out_value[0] = (float)(val.idx + 8) / 16.0f;
1937 val.idx = (sample_locs_2x[0] >> (offset + 4)) & 0xf;
1938 out_value[1] = (float)(val.idx + 8) / 16.0f;
1939 break;
1940 case 4:
1941 offset = 4 * (sample_index * 2);
1942 val.idx = (sample_locs_4x[0] >> offset) & 0xf;
1943 out_value[0] = (float)(val.idx + 8) / 16.0f;
1944 val.idx = (sample_locs_4x[0] >> (offset + 4)) & 0xf;
1945 out_value[1] = (float)(val.idx + 8) / 16.0f;
1946 break;
1947 case 8:
1948 offset = 4 * (sample_index % 4 * 2);
1949 index = (sample_index / 4);
1950 val.idx = (sample_locs_8x[index] >> offset) & 0xf;
1951 out_value[0] = (float)(val.idx + 8) / 16.0f;
1952 val.idx = (sample_locs_8x[index] >> (offset + 4)) & 0xf;
1953 out_value[1] = (float)(val.idx + 8) / 16.0f;
1954 break;
1955 }
1956 }
1957
1958 static void evergreen_emit_msaa_state(struct r600_context *rctx, int nr_samples)
1959 {
1960
1961 struct radeon_winsys_cs *cs = rctx->b.rings.gfx.cs;
1962 unsigned max_dist = 0;
1963
1964 switch (nr_samples) {
1965 default:
1966 nr_samples = 0;
1967 break;
1968 case 2:
1969 r600_write_context_reg_seq(cs, R_028C1C_PA_SC_AA_SAMPLE_LOCS_0, Elements(sample_locs_2x));
1970 radeon_emit_array(cs, sample_locs_2x, Elements(sample_locs_2x));
1971 max_dist = max_dist_2x;
1972 break;
1973 case 4:
1974 r600_write_context_reg_seq(cs, R_028C1C_PA_SC_AA_SAMPLE_LOCS_0, Elements(sample_locs_4x));
1975 radeon_emit_array(cs, sample_locs_4x, Elements(sample_locs_4x));
1976 max_dist = max_dist_4x;
1977 break;
1978 case 8:
1979 r600_write_context_reg_seq(cs, R_028C1C_PA_SC_AA_SAMPLE_LOCS_0, Elements(sample_locs_8x));
1980 radeon_emit_array(cs, sample_locs_8x, Elements(sample_locs_8x));
1981 max_dist = max_dist_8x;
1982 break;
1983 }
1984
1985 if (nr_samples > 1) {
1986 r600_write_context_reg_seq(cs, R_028C00_PA_SC_LINE_CNTL, 2);
1987 radeon_emit(cs, S_028C00_LAST_PIXEL(1) |
1988 S_028C00_EXPAND_LINE_WIDTH(1)); /* R_028C00_PA_SC_LINE_CNTL */
1989 radeon_emit(cs, S_028C04_MSAA_NUM_SAMPLES(util_logbase2(nr_samples)) |
1990 S_028C04_MAX_SAMPLE_DIST(max_dist)); /* R_028C04_PA_SC_AA_CONFIG */
1991 } else {
1992 r600_write_context_reg_seq(cs, R_028C00_PA_SC_LINE_CNTL, 2);
1993 radeon_emit(cs, S_028C00_LAST_PIXEL(1)); /* R_028C00_PA_SC_LINE_CNTL */
1994 radeon_emit(cs, 0); /* R_028C04_PA_SC_AA_CONFIG */
1995 }
1996 }
1997
1998 /* Cayman 8xMSAA */
1999 static uint32_t cm_sample_locs_8x[] = {
2000 FILL_SREG(-2, -5, 3, -4, -1, 5, -6, -2),
2001 FILL_SREG(-2, -5, 3, -4, -1, 5, -6, -2),
2002 FILL_SREG(-2, -5, 3, -4, -1, 5, -6, -2),
2003 FILL_SREG(-2, -5, 3, -4, -1, 5, -6, -2),
2004 FILL_SREG( 6, 0, 0, 0, -5, 3, 4, 4),
2005 FILL_SREG( 6, 0, 0, 0, -5, 3, 4, 4),
2006 FILL_SREG( 6, 0, 0, 0, -5, 3, 4, 4),
2007 FILL_SREG( 6, 0, 0, 0, -5, 3, 4, 4),
2008 };
2009 static unsigned cm_max_dist_8x = 8;
2010 /* Cayman 16xMSAA */
2011 static uint32_t cm_sample_locs_16x[] = {
2012 FILL_SREG(-7, -3, 7, 3, 1, -5, -5, 5),
2013 FILL_SREG(-7, -3, 7, 3, 1, -5, -5, 5),
2014 FILL_SREG(-7, -3, 7, 3, 1, -5, -5, 5),
2015 FILL_SREG(-7, -3, 7, 3, 1, -5, -5, 5),
2016 FILL_SREG(-3, -7, 3, 7, 5, -1, -1, 1),
2017 FILL_SREG(-3, -7, 3, 7, 5, -1, -1, 1),
2018 FILL_SREG(-3, -7, 3, 7, 5, -1, -1, 1),
2019 FILL_SREG(-3, -7, 3, 7, 5, -1, -1, 1),
2020 FILL_SREG(-8, -6, 4, 2, 2, -8, -2, 6),
2021 FILL_SREG(-8, -6, 4, 2, 2, -8, -2, 6),
2022 FILL_SREG(-8, -6, 4, 2, 2, -8, -2, 6),
2023 FILL_SREG(-8, -6, 4, 2, 2, -8, -2, 6),
2024 FILL_SREG(-4, -2, 0, 4, 6, -4, -6, 0),
2025 FILL_SREG(-4, -2, 0, 4, 6, -4, -6, 0),
2026 FILL_SREG(-4, -2, 0, 4, 6, -4, -6, 0),
2027 FILL_SREG(-4, -2, 0, 4, 6, -4, -6, 0),
2028 };
2029 static unsigned cm_max_dist_16x = 8;
2030 static void cayman_get_sample_position(struct pipe_context *ctx,
2031 unsigned sample_count,
2032 unsigned sample_index,
2033 float *out_value)
2034 {
2035 int offset, index;
2036 struct {
2037 int idx:4;
2038 } val;
2039 switch (sample_count) {
2040 case 1:
2041 default:
2042 out_value[0] = out_value[1] = 0.5;
2043 break;
2044 case 2:
2045 offset = 4 * (sample_index * 2);
2046 val.idx = (sample_locs_2x[0] >> offset) & 0xf;
2047 out_value[0] = (float)(val.idx + 8) / 16.0f;
2048 val.idx = (sample_locs_2x[0] >> (offset + 4)) & 0xf;
2049 out_value[1] = (float)(val.idx + 8) / 16.0f;
2050 break;
2051 case 4:
2052 offset = 4 * (sample_index * 2);
2053 val.idx = (sample_locs_4x[0] >> offset) & 0xf;
2054 out_value[0] = (float)(val.idx + 8) / 16.0f;
2055 val.idx = (sample_locs_4x[0] >> (offset + 4)) & 0xf;
2056 out_value[1] = (float)(val.idx + 8) / 16.0f;
2057 break;
2058 case 8:
2059 offset = 4 * (sample_index % 4 * 2);
2060 index = (sample_index / 4) * 4;
2061 val.idx = (cm_sample_locs_8x[index] >> offset) & 0xf;
2062 out_value[0] = (float)(val.idx + 8) / 16.0f;
2063 val.idx = (cm_sample_locs_8x[index] >> (offset + 4)) & 0xf;
2064 out_value[1] = (float)(val.idx + 8) / 16.0f;
2065 break;
2066 case 16:
2067 offset = 4 * (sample_index % 4 * 2);
2068 index = (sample_index / 4) * 4;
2069 val.idx = (cm_sample_locs_16x[index] >> offset) & 0xf;
2070 out_value[0] = (float)(val.idx + 8) / 16.0f;
2071 val.idx = (cm_sample_locs_16x[index] >> (offset + 4)) & 0xf;
2072 out_value[1] = (float)(val.idx + 8) / 16.0f;
2073 break;
2074 }
2075 }
2076
2077 static void cayman_emit_msaa_state(struct r600_context *rctx, int nr_samples)
2078 {
2079
2080
2081 struct radeon_winsys_cs *cs = rctx->b.rings.gfx.cs;
2082 unsigned max_dist = 0;
2083
2084 switch (nr_samples) {
2085 default:
2086 nr_samples = 0;
2087 break;
2088 case 2:
2089 r600_write_context_reg(cs, CM_R_028BF8_PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_0, sample_locs_2x[0]);
2090 r600_write_context_reg(cs, CM_R_028C08_PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_0, sample_locs_2x[1]);
2091 r600_write_context_reg(cs, CM_R_028C18_PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_0, sample_locs_2x[2]);
2092 r600_write_context_reg(cs, CM_R_028C28_PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_0, sample_locs_2x[3]);
2093 max_dist = max_dist_2x;
2094 break;
2095 case 4:
2096 r600_write_context_reg(cs, CM_R_028BF8_PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_0, sample_locs_4x[0]);
2097 r600_write_context_reg(cs, CM_R_028C08_PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_0, sample_locs_4x[1]);
2098 r600_write_context_reg(cs, CM_R_028C18_PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_0, sample_locs_4x[2]);
2099 r600_write_context_reg(cs, CM_R_028C28_PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_0, sample_locs_4x[3]);
2100 max_dist = max_dist_4x;
2101 break;
2102 case 8:
2103 r600_write_context_reg_seq(cs, CM_R_028BF8_PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_0, 14);
2104 radeon_emit(cs, cm_sample_locs_8x[0]);
2105 radeon_emit(cs, cm_sample_locs_8x[4]);
2106 radeon_emit(cs, 0);
2107 radeon_emit(cs, 0);
2108 radeon_emit(cs, cm_sample_locs_8x[1]);
2109 radeon_emit(cs, cm_sample_locs_8x[5]);
2110 radeon_emit(cs, 0);
2111 radeon_emit(cs, 0);
2112 radeon_emit(cs, cm_sample_locs_8x[2]);
2113 radeon_emit(cs, cm_sample_locs_8x[6]);
2114 radeon_emit(cs, 0);
2115 radeon_emit(cs, 0);
2116 radeon_emit(cs, cm_sample_locs_8x[3]);
2117 radeon_emit(cs, cm_sample_locs_8x[7]);
2118 max_dist = cm_max_dist_8x;
2119 break;
2120 case 16:
2121 r600_write_context_reg_seq(cs, CM_R_028BF8_PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_0, 16);
2122 radeon_emit(cs, cm_sample_locs_16x[0]);
2123 radeon_emit(cs, cm_sample_locs_16x[4]);
2124 radeon_emit(cs, cm_sample_locs_16x[8]);
2125 radeon_emit(cs, cm_sample_locs_16x[12]);
2126 radeon_emit(cs, cm_sample_locs_16x[1]);
2127 radeon_emit(cs, cm_sample_locs_16x[5]);
2128 radeon_emit(cs, cm_sample_locs_16x[9]);
2129 radeon_emit(cs, cm_sample_locs_16x[13]);
2130 radeon_emit(cs, cm_sample_locs_16x[2]);
2131 radeon_emit(cs, cm_sample_locs_16x[6]);
2132 radeon_emit(cs, cm_sample_locs_16x[10]);
2133 radeon_emit(cs, cm_sample_locs_16x[14]);
2134 radeon_emit(cs, cm_sample_locs_16x[3]);
2135 radeon_emit(cs, cm_sample_locs_16x[7]);
2136 radeon_emit(cs, cm_sample_locs_16x[11]);
2137 radeon_emit(cs, cm_sample_locs_16x[15]);
2138 max_dist = cm_max_dist_16x;
2139 break;
2140 }
2141
2142 if (nr_samples > 1) {
2143 unsigned log_samples = util_logbase2(nr_samples);
2144
2145 r600_write_context_reg_seq(cs, CM_R_028BDC_PA_SC_LINE_CNTL, 2);
2146 radeon_emit(cs, S_028C00_LAST_PIXEL(1) |
2147 S_028C00_EXPAND_LINE_WIDTH(1)); /* CM_R_028BDC_PA_SC_LINE_CNTL */
2148 radeon_emit(cs, S_028BE0_MSAA_NUM_SAMPLES(log_samples) |
2149 S_028BE0_MAX_SAMPLE_DIST(max_dist) |
2150 S_028BE0_MSAA_EXPOSED_SAMPLES(log_samples)); /* CM_R_028BE0_PA_SC_AA_CONFIG */
2151
2152 r600_write_context_reg(cs, CM_R_028804_DB_EQAA,
2153 S_028804_MAX_ANCHOR_SAMPLES(log_samples) |
2154 S_028804_PS_ITER_SAMPLES(log_samples) |
2155 S_028804_MASK_EXPORT_NUM_SAMPLES(log_samples) |
2156 S_028804_ALPHA_TO_MASK_NUM_SAMPLES(log_samples) |
2157 S_028804_HIGH_QUALITY_INTERSECTIONS(1) |
2158 S_028804_STATIC_ANCHOR_ASSOCIATIONS(1));
2159 } else {
2160 r600_write_context_reg_seq(cs, CM_R_028BDC_PA_SC_LINE_CNTL, 2);
2161 radeon_emit(cs, S_028C00_LAST_PIXEL(1)); /* CM_R_028BDC_PA_SC_LINE_CNTL */
2162 radeon_emit(cs, 0); /* CM_R_028BE0_PA_SC_AA_CONFIG */
2163
2164 r600_write_context_reg(cs, CM_R_028804_DB_EQAA,
2165 S_028804_HIGH_QUALITY_INTERSECTIONS(1) |
2166 S_028804_STATIC_ANCHOR_ASSOCIATIONS(1));
2167 }
2168 }
2169
2170 static void evergreen_emit_framebuffer_state(struct r600_context *rctx, struct r600_atom *atom)
2171 {
2172 struct radeon_winsys_cs *cs = rctx->b.rings.gfx.cs;
2173 struct pipe_framebuffer_state *state = &rctx->framebuffer.state;
2174 unsigned nr_cbufs = state->nr_cbufs;
2175 unsigned i, tl, br;
2176
2177 /* XXX support more colorbuffers once we need them */
2178 assert(nr_cbufs <= 8);
2179 if (nr_cbufs > 8)
2180 nr_cbufs = 8;
2181
2182 /* Colorbuffers. */
2183 for (i = 0; i < nr_cbufs; i++) {
2184 struct r600_surface *cb = (struct r600_surface*)state->cbufs[i];
2185 struct r600_texture *tex;
2186 unsigned reloc, cmask_reloc;
2187
2188 if (!cb) {
2189 r600_write_context_reg(cs, R_028C70_CB_COLOR0_INFO + i * 0x3C,
2190 S_028C70_FORMAT(V_028C70_COLOR_INVALID));
2191 continue;
2192 }
2193
2194 tex = (struct r600_texture *)cb->base.texture;
2195 reloc = r600_context_bo_reloc(&rctx->b,
2196 &rctx->b.rings.gfx,
2197 (struct r600_resource*)cb->base.texture,
2198 RADEON_USAGE_READWRITE);
2199
2200 if (tex->cmask_buffer && tex->cmask_buffer != &tex->resource) {
2201 cmask_reloc = r600_context_bo_reloc(&rctx->b, &rctx->b.rings.gfx,
2202 tex->cmask_buffer, RADEON_USAGE_READWRITE);
2203 } else {
2204 cmask_reloc = reloc;
2205 }
2206
2207 r600_write_context_reg_seq(cs, R_028C60_CB_COLOR0_BASE + i * 0x3C, 13);
2208 radeon_emit(cs, cb->cb_color_base); /* R_028C60_CB_COLOR0_BASE */
2209 radeon_emit(cs, cb->cb_color_pitch); /* R_028C64_CB_COLOR0_PITCH */
2210 radeon_emit(cs, cb->cb_color_slice); /* R_028C68_CB_COLOR0_SLICE */
2211 radeon_emit(cs, cb->cb_color_view); /* R_028C6C_CB_COLOR0_VIEW */
2212 radeon_emit(cs, cb->cb_color_info); /* R_028C70_CB_COLOR0_INFO */
2213 radeon_emit(cs, cb->cb_color_attrib); /* R_028C74_CB_COLOR0_ATTRIB */
2214 radeon_emit(cs, cb->cb_color_dim); /* R_028C78_CB_COLOR0_DIM */
2215 radeon_emit(cs, cb->cb_color_cmask); /* R_028C7C_CB_COLOR0_CMASK */
2216 radeon_emit(cs, cb->cb_color_cmask_slice); /* R_028C80_CB_COLOR0_CMASK_SLICE */
2217 radeon_emit(cs, cb->cb_color_fmask); /* R_028C84_CB_COLOR0_FMASK */
2218 radeon_emit(cs, cb->cb_color_fmask_slice); /* R_028C88_CB_COLOR0_FMASK_SLICE */
2219 radeon_emit(cs, tex->color_clear_value[0]); /* R_028C8C_CB_COLOR0_CLEAR_WORD0 */
2220 radeon_emit(cs, tex->color_clear_value[1]); /* R_028C90_CB_COLOR0_CLEAR_WORD1 */
2221
2222 radeon_emit(cs, PKT3(PKT3_NOP, 0, 0)); /* R_028C60_CB_COLOR0_BASE */
2223 radeon_emit(cs, reloc);
2224
2225 if (!rctx->keep_tiling_flags) {
2226 radeon_emit(cs, PKT3(PKT3_NOP, 0, 0)); /* R_028C70_CB_COLOR0_INFO */
2227 radeon_emit(cs, reloc);
2228 }
2229
2230 radeon_emit(cs, PKT3(PKT3_NOP, 0, 0)); /* R_028C74_CB_COLOR0_ATTRIB */
2231 radeon_emit(cs, reloc);
2232
2233 radeon_emit(cs, PKT3(PKT3_NOP, 0, 0)); /* R_028C7C_CB_COLOR0_CMASK */
2234 radeon_emit(cs, cmask_reloc);
2235
2236 radeon_emit(cs, PKT3(PKT3_NOP, 0, 0)); /* R_028C84_CB_COLOR0_FMASK */
2237 radeon_emit(cs, reloc);
2238 }
2239 /* set CB_COLOR1_INFO for possible dual-src blending */
2240 if (i == 1 && state->cbufs[0]) {
2241 r600_write_context_reg(cs, R_028C70_CB_COLOR0_INFO + 1 * 0x3C,
2242 ((struct r600_surface*)state->cbufs[0])->cb_color_info);
2243
2244 if (!rctx->keep_tiling_flags) {
2245 unsigned reloc = r600_context_bo_reloc(&rctx->b,
2246 &rctx->b.rings.gfx,
2247 (struct r600_resource*)state->cbufs[0]->texture,
2248 RADEON_USAGE_READWRITE);
2249
2250 radeon_emit(cs, PKT3(PKT3_NOP, 0, 0)); /* R_028C70_CB_COLOR0_INFO */
2251 radeon_emit(cs, reloc);
2252 }
2253 i++;
2254 }
2255 if (rctx->keep_tiling_flags) {
2256 for (; i < 8 ; i++) {
2257 r600_write_context_reg(cs, R_028C70_CB_COLOR0_INFO + i * 0x3C, 0);
2258 }
2259 for (; i < 12; i++) {
2260 r600_write_context_reg(cs, R_028E50_CB_COLOR8_INFO + (i - 8) * 0x1C, 0);
2261 }
2262 }
2263
2264 /* ZS buffer. */
2265 if (state->zsbuf) {
2266 struct r600_surface *zb = (struct r600_surface*)state->zsbuf;
2267 unsigned reloc = r600_context_bo_reloc(&rctx->b,
2268 &rctx->b.rings.gfx,
2269 (struct r600_resource*)state->zsbuf->texture,
2270 RADEON_USAGE_READWRITE);
2271
2272 r600_write_context_reg(cs, R_028B78_PA_SU_POLY_OFFSET_DB_FMT_CNTL,
2273 zb->pa_su_poly_offset_db_fmt_cntl);
2274 r600_write_context_reg(cs, R_028008_DB_DEPTH_VIEW, zb->db_depth_view);
2275
2276 r600_write_context_reg_seq(cs, R_028040_DB_Z_INFO, 8);
2277 radeon_emit(cs, zb->db_depth_info); /* R_028040_DB_Z_INFO */
2278 radeon_emit(cs, zb->db_stencil_info); /* R_028044_DB_STENCIL_INFO */
2279 radeon_emit(cs, zb->db_depth_base); /* R_028048_DB_Z_READ_BASE */
2280 radeon_emit(cs, zb->db_stencil_base); /* R_02804C_DB_STENCIL_READ_BASE */
2281 radeon_emit(cs, zb->db_depth_base); /* R_028050_DB_Z_WRITE_BASE */
2282 radeon_emit(cs, zb->db_stencil_base); /* R_028054_DB_STENCIL_WRITE_BASE */
2283 radeon_emit(cs, zb->db_depth_size); /* R_028058_DB_DEPTH_SIZE */
2284 radeon_emit(cs, zb->db_depth_slice); /* R_02805C_DB_DEPTH_SLICE */
2285
2286 if (!rctx->keep_tiling_flags) {
2287 radeon_emit(cs, PKT3(PKT3_NOP, 0, 0)); /* R_028040_DB_Z_INFO */
2288 radeon_emit(cs, reloc);
2289 }
2290
2291 radeon_emit(cs, PKT3(PKT3_NOP, 0, 0)); /* R_028048_DB_Z_READ_BASE */
2292 radeon_emit(cs, reloc);
2293
2294 radeon_emit(cs, PKT3(PKT3_NOP, 0, 0)); /* R_02804C_DB_STENCIL_READ_BASE */
2295 radeon_emit(cs, reloc);
2296
2297 radeon_emit(cs, PKT3(PKT3_NOP, 0, 0)); /* R_028050_DB_Z_WRITE_BASE */
2298 radeon_emit(cs, reloc);
2299
2300 radeon_emit(cs, PKT3(PKT3_NOP, 0, 0)); /* R_028054_DB_STENCIL_WRITE_BASE */
2301 radeon_emit(cs, reloc);
2302 } else if (rctx->screen->b.info.drm_minor >= 18) {
2303 /* DRM 2.6.18 allows the INVALID format to disable depth/stencil.
2304 * Older kernels are out of luck. */
2305 r600_write_context_reg_seq(cs, R_028040_DB_Z_INFO, 2);
2306 radeon_emit(cs, S_028040_FORMAT(V_028040_Z_INVALID)); /* R_028040_DB_Z_INFO */
2307 radeon_emit(cs, S_028044_FORMAT(V_028044_STENCIL_INVALID)); /* R_028044_DB_STENCIL_INFO */
2308 }
2309
2310 /* Framebuffer dimensions. */
2311 evergreen_get_scissor_rect(rctx, 0, 0, state->width, state->height, &tl, &br);
2312
2313 r600_write_context_reg_seq(cs, R_028204_PA_SC_WINDOW_SCISSOR_TL, 2);
2314 radeon_emit(cs, tl); /* R_028204_PA_SC_WINDOW_SCISSOR_TL */
2315 radeon_emit(cs, br); /* R_028208_PA_SC_WINDOW_SCISSOR_BR */
2316
2317 if (rctx->b.chip_class == EVERGREEN) {
2318 evergreen_emit_msaa_state(rctx, rctx->framebuffer.nr_samples);
2319 } else {
2320 cayman_emit_msaa_state(rctx, rctx->framebuffer.nr_samples);
2321 }
2322 }
2323
2324 static void evergreen_emit_polygon_offset(struct r600_context *rctx, struct r600_atom *a)
2325 {
2326 struct radeon_winsys_cs *cs = rctx->b.rings.gfx.cs;
2327 struct r600_poly_offset_state *state = (struct r600_poly_offset_state*)a;
2328 float offset_units = state->offset_units;
2329 float offset_scale = state->offset_scale;
2330
2331 switch (state->zs_format) {
2332 case PIPE_FORMAT_Z24X8_UNORM:
2333 case PIPE_FORMAT_Z24_UNORM_S8_UINT:
2334 case PIPE_FORMAT_X8Z24_UNORM:
2335 case PIPE_FORMAT_S8_UINT_Z24_UNORM:
2336 offset_units *= 2.0f;
2337 break;
2338 case PIPE_FORMAT_Z16_UNORM:
2339 offset_units *= 4.0f;
2340 break;
2341 default:;
2342 }
2343
2344 r600_write_context_reg_seq(cs, R_028B80_PA_SU_POLY_OFFSET_FRONT_SCALE, 4);
2345 radeon_emit(cs, fui(offset_scale));
2346 radeon_emit(cs, fui(offset_units));
2347 radeon_emit(cs, fui(offset_scale));
2348 radeon_emit(cs, fui(offset_units));
2349 }
2350
2351 static void evergreen_emit_cb_misc_state(struct r600_context *rctx, struct r600_atom *atom)
2352 {
2353 struct radeon_winsys_cs *cs = rctx->b.rings.gfx.cs;
2354 struct r600_cb_misc_state *a = (struct r600_cb_misc_state*)atom;
2355 unsigned fb_colormask = (1ULL << ((unsigned)a->nr_cbufs * 4)) - 1;
2356 unsigned ps_colormask = (1ULL << ((unsigned)a->nr_ps_color_outputs * 4)) - 1;
2357
2358 r600_write_context_reg_seq(cs, R_028238_CB_TARGET_MASK, 2);
2359 radeon_emit(cs, a->blend_colormask & fb_colormask); /* R_028238_CB_TARGET_MASK */
2360 /* Always enable the first colorbuffer in CB_SHADER_MASK. This
2361 * will assure that the alpha-test will work even if there is
2362 * no colorbuffer bound. */
2363 radeon_emit(cs, 0xf | (a->dual_src_blend ? ps_colormask : 0) | fb_colormask); /* R_02823C_CB_SHADER_MASK */
2364 }
2365
2366 static void evergreen_emit_db_state(struct r600_context *rctx, struct r600_atom *atom)
2367 {
2368 struct radeon_winsys_cs *cs = rctx->b.rings.gfx.cs;
2369 struct r600_db_state *a = (struct r600_db_state*)atom;
2370
2371 if (a->rsurf && a->rsurf->htile_enabled) {
2372 struct r600_texture *rtex = (struct r600_texture *)a->rsurf->base.texture;
2373 unsigned reloc_idx;
2374
2375 r600_write_context_reg(cs, R_02802C_DB_DEPTH_CLEAR, fui(rtex->depth_clear_value));
2376 r600_write_context_reg(cs, R_028ABC_DB_HTILE_SURFACE, a->rsurf->db_htile_surface);
2377 r600_write_context_reg(cs, R_028AC8_DB_PRELOAD_CONTROL, a->rsurf->db_preload_control);
2378 r600_write_context_reg(cs, R_028014_DB_HTILE_DATA_BASE, a->rsurf->db_htile_data_base);
2379 reloc_idx = r600_context_bo_reloc(&rctx->b, &rctx->b.rings.gfx, rtex->htile_buffer, RADEON_USAGE_READWRITE);
2380 cs->buf[cs->cdw++] = PKT3(PKT3_NOP, 0, 0);
2381 cs->buf[cs->cdw++] = reloc_idx;
2382 } else {
2383 r600_write_context_reg(cs, R_028ABC_DB_HTILE_SURFACE, 0);
2384 r600_write_context_reg(cs, R_028AC8_DB_PRELOAD_CONTROL, 0);
2385 }
2386 }
2387
2388 static void evergreen_emit_db_misc_state(struct r600_context *rctx, struct r600_atom *atom)
2389 {
2390 struct radeon_winsys_cs *cs = rctx->b.rings.gfx.cs;
2391 struct r600_db_misc_state *a = (struct r600_db_misc_state*)atom;
2392 unsigned db_render_control = 0;
2393 unsigned db_count_control = 0;
2394 unsigned db_render_override =
2395 S_02800C_FORCE_HIS_ENABLE0(V_02800C_FORCE_DISABLE) |
2396 S_02800C_FORCE_HIS_ENABLE1(V_02800C_FORCE_DISABLE);
2397
2398 if (a->occlusion_query_enabled) {
2399 db_count_control |= S_028004_PERFECT_ZPASS_COUNTS(1);
2400 if (rctx->b.chip_class == CAYMAN) {
2401 db_count_control |= S_028004_SAMPLE_RATE(a->log_samples);
2402 }
2403 db_render_override |= S_02800C_NOOP_CULL_DISABLE(1);
2404 }
2405 /* FIXME we should be able to use hyperz even if we are not writing to
2406 * zbuffer but somehow this trigger GPU lockup. See :
2407 *
2408 * https://bugs.freedesktop.org/show_bug.cgi?id=60848
2409 *
2410 * Disable hyperz for now if not writing to zbuffer.
2411 */
2412 if (rctx->db_state.rsurf && rctx->db_state.rsurf->htile_enabled && rctx->zwritemask) {
2413 /* FORCE_OFF means HiZ/HiS are determined by DB_SHADER_CONTROL */
2414 db_render_override |= S_02800C_FORCE_HIZ_ENABLE(V_02800C_FORCE_OFF);
2415 /* This is to fix a lockup when hyperz and alpha test are enabled at
2416 * the same time somehow GPU get confuse on which order to pick for
2417 * z test
2418 */
2419 if (rctx->alphatest_state.sx_alpha_test_control) {
2420 db_render_override |= S_02800C_FORCE_SHADER_Z_ORDER(1);
2421 }
2422 } else {
2423 db_render_override |= S_02800C_FORCE_HIZ_ENABLE(V_02800C_FORCE_DISABLE);
2424 }
2425 if (a->flush_depthstencil_through_cb) {
2426 assert(a->copy_depth || a->copy_stencil);
2427
2428 db_render_control |= S_028000_DEPTH_COPY_ENABLE(a->copy_depth) |
2429 S_028000_STENCIL_COPY_ENABLE(a->copy_stencil) |
2430 S_028000_COPY_CENTROID(1) |
2431 S_028000_COPY_SAMPLE(a->copy_sample);
2432 } else if (a->flush_depthstencil_in_place) {
2433 db_render_control |= S_028000_DEPTH_COMPRESS_DISABLE(1) |
2434 S_028000_STENCIL_COMPRESS_DISABLE(1);
2435 db_render_override |= S_02800C_DISABLE_PIXEL_RATE_TILES(1);
2436 }
2437 if (a->htile_clear) {
2438 /* FIXME we might want to disable cliprect here */
2439 db_render_control |= S_028000_DEPTH_CLEAR_ENABLE(1);
2440 }
2441
2442 r600_write_context_reg_seq(cs, R_028000_DB_RENDER_CONTROL, 2);
2443 radeon_emit(cs, db_render_control); /* R_028000_DB_RENDER_CONTROL */
2444 radeon_emit(cs, db_count_control); /* R_028004_DB_COUNT_CONTROL */
2445 r600_write_context_reg(cs, R_02800C_DB_RENDER_OVERRIDE, db_render_override);
2446 r600_write_context_reg(cs, R_02880C_DB_SHADER_CONTROL, a->db_shader_control);
2447 }
2448
2449 static void evergreen_emit_vertex_buffers(struct r600_context *rctx,
2450 struct r600_vertexbuf_state *state,
2451 unsigned resource_offset,
2452 unsigned pkt_flags)
2453 {
2454 struct radeon_winsys_cs *cs = rctx->b.rings.gfx.cs;
2455 uint32_t dirty_mask = state->dirty_mask;
2456
2457 while (dirty_mask) {
2458 struct pipe_vertex_buffer *vb;
2459 struct r600_resource *rbuffer;
2460 uint64_t va;
2461 unsigned buffer_index = u_bit_scan(&dirty_mask);
2462
2463 vb = &state->vb[buffer_index];
2464 rbuffer = (struct r600_resource*)vb->buffer;
2465 assert(rbuffer);
2466
2467 va = r600_resource_va(&rctx->screen->b.b, &rbuffer->b.b);
2468 va += vb->buffer_offset;
2469
2470 /* fetch resources start at index 992 */
2471 radeon_emit(cs, PKT3(PKT3_SET_RESOURCE, 8, 0) | pkt_flags);
2472 radeon_emit(cs, (resource_offset + buffer_index) * 8);
2473 radeon_emit(cs, va); /* RESOURCEi_WORD0 */
2474 radeon_emit(cs, rbuffer->buf->size - vb->buffer_offset - 1); /* RESOURCEi_WORD1 */
2475 radeon_emit(cs, /* RESOURCEi_WORD2 */
2476 S_030008_ENDIAN_SWAP(r600_endian_swap(32)) |
2477 S_030008_STRIDE(vb->stride) |
2478 S_030008_BASE_ADDRESS_HI(va >> 32UL));
2479 radeon_emit(cs, /* RESOURCEi_WORD3 */
2480 S_03000C_DST_SEL_X(V_03000C_SQ_SEL_X) |
2481 S_03000C_DST_SEL_Y(V_03000C_SQ_SEL_Y) |
2482 S_03000C_DST_SEL_Z(V_03000C_SQ_SEL_Z) |
2483 S_03000C_DST_SEL_W(V_03000C_SQ_SEL_W));
2484 radeon_emit(cs, 0); /* RESOURCEi_WORD4 */
2485 radeon_emit(cs, 0); /* RESOURCEi_WORD5 */
2486 radeon_emit(cs, 0); /* RESOURCEi_WORD6 */
2487 radeon_emit(cs, 0xc0000000); /* RESOURCEi_WORD7 */
2488
2489 radeon_emit(cs, PKT3(PKT3_NOP, 0, 0) | pkt_flags);
2490 radeon_emit(cs, r600_context_bo_reloc(&rctx->b, &rctx->b.rings.gfx, rbuffer, RADEON_USAGE_READ));
2491 }
2492 state->dirty_mask = 0;
2493 }
2494
2495 static void evergreen_fs_emit_vertex_buffers(struct r600_context *rctx, struct r600_atom * atom)
2496 {
2497 evergreen_emit_vertex_buffers(rctx, &rctx->vertex_buffer_state, 992, 0);
2498 }
2499
2500 static void evergreen_cs_emit_vertex_buffers(struct r600_context *rctx, struct r600_atom * atom)
2501 {
2502 evergreen_emit_vertex_buffers(rctx, &rctx->cs_vertex_buffer_state, 816,
2503 RADEON_CP_PACKET3_COMPUTE_MODE);
2504 }
2505
2506 static void evergreen_emit_constant_buffers(struct r600_context *rctx,
2507 struct r600_constbuf_state *state,
2508 unsigned buffer_id_base,
2509 unsigned reg_alu_constbuf_size,
2510 unsigned reg_alu_const_cache,
2511 unsigned pkt_flags)
2512 {
2513 struct radeon_winsys_cs *cs = rctx->b.rings.gfx.cs;
2514 uint32_t dirty_mask = state->dirty_mask;
2515
2516 while (dirty_mask) {
2517 struct pipe_constant_buffer *cb;
2518 struct r600_resource *rbuffer;
2519 uint64_t va;
2520 unsigned buffer_index = ffs(dirty_mask) - 1;
2521 unsigned gs_ring_buffer = (buffer_index == R600_GS_RING_CONST_BUFFER);
2522
2523 cb = &state->cb[buffer_index];
2524 rbuffer = (struct r600_resource*)cb->buffer;
2525 assert(rbuffer);
2526
2527 va = r600_resource_va(&rctx->screen->b.b, &rbuffer->b.b);
2528 va += cb->buffer_offset;
2529
2530 if (!gs_ring_buffer) {
2531 r600_write_context_reg_flag(cs, reg_alu_constbuf_size + buffer_index * 4,
2532 ALIGN_DIVUP(cb->buffer_size >> 4, 16), pkt_flags);
2533 r600_write_context_reg_flag(cs, reg_alu_const_cache + buffer_index * 4, va >> 8,
2534 pkt_flags);
2535 }
2536
2537 radeon_emit(cs, PKT3(PKT3_NOP, 0, 0) | pkt_flags);
2538 radeon_emit(cs, r600_context_bo_reloc(&rctx->b, &rctx->b.rings.gfx, rbuffer, RADEON_USAGE_READ));
2539
2540 radeon_emit(cs, PKT3(PKT3_SET_RESOURCE, 8, 0) | pkt_flags);
2541 radeon_emit(cs, (buffer_id_base + buffer_index) * 8);
2542 radeon_emit(cs, va); /* RESOURCEi_WORD0 */
2543 radeon_emit(cs, rbuffer->buf->size - cb->buffer_offset - 1); /* RESOURCEi_WORD1 */
2544 radeon_emit(cs, /* RESOURCEi_WORD2 */
2545 S_030008_ENDIAN_SWAP(gs_ring_buffer ? ENDIAN_NONE : r600_endian_swap(32)) |
2546 S_030008_STRIDE(gs_ring_buffer ? 4 : 16) |
2547 S_030008_BASE_ADDRESS_HI(va >> 32UL) |
2548 S_030008_DATA_FORMAT(FMT_32_32_32_32_FLOAT));
2549 radeon_emit(cs, /* RESOURCEi_WORD3 */
2550 S_03000C_UNCACHED(gs_ring_buffer ? 1 : 0) |
2551 S_03000C_DST_SEL_X(V_03000C_SQ_SEL_X) |
2552 S_03000C_DST_SEL_Y(V_03000C_SQ_SEL_Y) |
2553 S_03000C_DST_SEL_Z(V_03000C_SQ_SEL_Z) |
2554 S_03000C_DST_SEL_W(V_03000C_SQ_SEL_W));
2555 radeon_emit(cs, 0); /* RESOURCEi_WORD4 */
2556 radeon_emit(cs, 0); /* RESOURCEi_WORD5 */
2557 radeon_emit(cs, 0); /* RESOURCEi_WORD6 */
2558 radeon_emit(cs, /* RESOURCEi_WORD7 */
2559 S_03001C_TYPE(V_03001C_SQ_TEX_VTX_VALID_BUFFER));
2560
2561 radeon_emit(cs, PKT3(PKT3_NOP, 0, 0) | pkt_flags);
2562 radeon_emit(cs, r600_context_bo_reloc(&rctx->b, &rctx->b.rings.gfx, rbuffer, RADEON_USAGE_READ));
2563
2564 dirty_mask &= ~(1 << buffer_index);
2565 }
2566 state->dirty_mask = 0;
2567 }
2568
2569 static void evergreen_emit_vs_constant_buffers(struct r600_context *rctx, struct r600_atom *atom)
2570 {
2571 evergreen_emit_constant_buffers(rctx, &rctx->constbuf_state[PIPE_SHADER_VERTEX], 176,
2572 R_028180_ALU_CONST_BUFFER_SIZE_VS_0,
2573 R_028980_ALU_CONST_CACHE_VS_0,
2574 0 /* PKT3 flags */);
2575 }
2576
2577 static void evergreen_emit_gs_constant_buffers(struct r600_context *rctx, struct r600_atom *atom)
2578 {
2579 evergreen_emit_constant_buffers(rctx, &rctx->constbuf_state[PIPE_SHADER_GEOMETRY], 336,
2580 R_0281C0_ALU_CONST_BUFFER_SIZE_GS_0,
2581 R_0289C0_ALU_CONST_CACHE_GS_0,
2582 0 /* PKT3 flags */);
2583 }
2584
2585 static void evergreen_emit_ps_constant_buffers(struct r600_context *rctx, struct r600_atom *atom)
2586 {
2587 evergreen_emit_constant_buffers(rctx, &rctx->constbuf_state[PIPE_SHADER_FRAGMENT], 0,
2588 R_028140_ALU_CONST_BUFFER_SIZE_PS_0,
2589 R_028940_ALU_CONST_CACHE_PS_0,
2590 0 /* PKT3 flags */);
2591 }
2592
2593 static void evergreen_emit_cs_constant_buffers(struct r600_context *rctx, struct r600_atom *atom)
2594 {
2595 evergreen_emit_constant_buffers(rctx, &rctx->constbuf_state[PIPE_SHADER_COMPUTE], 816,
2596 R_028FC0_ALU_CONST_BUFFER_SIZE_LS_0,
2597 R_028F40_ALU_CONST_CACHE_LS_0,
2598 RADEON_CP_PACKET3_COMPUTE_MODE);
2599 }
2600
2601 static void evergreen_emit_sampler_views(struct r600_context *rctx,
2602 struct r600_samplerview_state *state,
2603 unsigned resource_id_base)
2604 {
2605 struct radeon_winsys_cs *cs = rctx->b.rings.gfx.cs;
2606 uint32_t dirty_mask = state->dirty_mask;
2607
2608 while (dirty_mask) {
2609 struct r600_pipe_sampler_view *rview;
2610 unsigned resource_index = u_bit_scan(&dirty_mask);
2611 unsigned reloc;
2612
2613 rview = state->views[resource_index];
2614 assert(rview);
2615
2616 radeon_emit(cs, PKT3(PKT3_SET_RESOURCE, 8, 0));
2617 radeon_emit(cs, (resource_id_base + resource_index) * 8);
2618 radeon_emit_array(cs, rview->tex_resource_words, 8);
2619
2620 reloc = r600_context_bo_reloc(&rctx->b, &rctx->b.rings.gfx, rview->tex_resource,
2621 RADEON_USAGE_READ);
2622 radeon_emit(cs, PKT3(PKT3_NOP, 0, 0));
2623 radeon_emit(cs, reloc);
2624
2625 if (!rview->skip_mip_address_reloc) {
2626 radeon_emit(cs, PKT3(PKT3_NOP, 0, 0));
2627 radeon_emit(cs, reloc);
2628 }
2629 }
2630 state->dirty_mask = 0;
2631 }
2632
2633 static void evergreen_emit_vs_sampler_views(struct r600_context *rctx, struct r600_atom *atom)
2634 {
2635 evergreen_emit_sampler_views(rctx, &rctx->samplers[PIPE_SHADER_VERTEX].views, 176 + R600_MAX_CONST_BUFFERS);
2636 }
2637
2638 static void evergreen_emit_gs_sampler_views(struct r600_context *rctx, struct r600_atom *atom)
2639 {
2640 evergreen_emit_sampler_views(rctx, &rctx->samplers[PIPE_SHADER_GEOMETRY].views, 336 + R600_MAX_CONST_BUFFERS);
2641 }
2642
2643 static void evergreen_emit_ps_sampler_views(struct r600_context *rctx, struct r600_atom *atom)
2644 {
2645 evergreen_emit_sampler_views(rctx, &rctx->samplers[PIPE_SHADER_FRAGMENT].views, R600_MAX_CONST_BUFFERS);
2646 }
2647
2648 static void evergreen_emit_sampler_states(struct r600_context *rctx,
2649 struct r600_textures_info *texinfo,
2650 unsigned resource_id_base,
2651 unsigned border_index_reg)
2652 {
2653 struct radeon_winsys_cs *cs = rctx->b.rings.gfx.cs;
2654 uint32_t dirty_mask = texinfo->states.dirty_mask;
2655
2656 while (dirty_mask) {
2657 struct r600_pipe_sampler_state *rstate;
2658 unsigned i = u_bit_scan(&dirty_mask);
2659
2660 rstate = texinfo->states.states[i];
2661 assert(rstate);
2662
2663 radeon_emit(cs, PKT3(PKT3_SET_SAMPLER, 3, 0));
2664 radeon_emit(cs, (resource_id_base + i) * 3);
2665 radeon_emit_array(cs, rstate->tex_sampler_words, 3);
2666
2667 if (rstate->border_color_use) {
2668 r600_write_config_reg_seq(cs, border_index_reg, 5);
2669 radeon_emit(cs, i);
2670 radeon_emit_array(cs, rstate->border_color.ui, 4);
2671 }
2672 }
2673 texinfo->states.dirty_mask = 0;
2674 }
2675
2676 static void evergreen_emit_vs_sampler_states(struct r600_context *rctx, struct r600_atom *atom)
2677 {
2678 evergreen_emit_sampler_states(rctx, &rctx->samplers[PIPE_SHADER_VERTEX], 18, R_00A414_TD_VS_SAMPLER0_BORDER_INDEX);
2679 }
2680
2681 static void evergreen_emit_gs_sampler_states(struct r600_context *rctx, struct r600_atom *atom)
2682 {
2683 evergreen_emit_sampler_states(rctx, &rctx->samplers[PIPE_SHADER_GEOMETRY], 36, R_00A428_TD_GS_SAMPLER0_BORDER_INDEX);
2684 }
2685
2686 static void evergreen_emit_ps_sampler_states(struct r600_context *rctx, struct r600_atom *atom)
2687 {
2688 evergreen_emit_sampler_states(rctx, &rctx->samplers[PIPE_SHADER_FRAGMENT], 0, R_00A400_TD_PS_SAMPLER0_BORDER_INDEX);
2689 }
2690
2691 static void evergreen_emit_sample_mask(struct r600_context *rctx, struct r600_atom *a)
2692 {
2693 struct r600_sample_mask *s = (struct r600_sample_mask*)a;
2694 uint8_t mask = s->sample_mask;
2695
2696 r600_write_context_reg(rctx->b.rings.gfx.cs, R_028C3C_PA_SC_AA_MASK,
2697 mask | (mask << 8) | (mask << 16) | (mask << 24));
2698 }
2699
2700 static void cayman_emit_sample_mask(struct r600_context *rctx, struct r600_atom *a)
2701 {
2702 struct r600_sample_mask *s = (struct r600_sample_mask*)a;
2703 struct radeon_winsys_cs *cs = rctx->b.rings.gfx.cs;
2704 uint16_t mask = s->sample_mask;
2705
2706 r600_write_context_reg_seq(cs, CM_R_028C38_PA_SC_AA_MASK_X0Y0_X1Y0, 2);
2707 radeon_emit(cs, mask | (mask << 16)); /* X0Y0_X1Y0 */
2708 radeon_emit(cs, mask | (mask << 16)); /* X0Y1_X1Y1 */
2709 }
2710
2711 static void evergreen_emit_vertex_fetch_shader(struct r600_context *rctx, struct r600_atom *a)
2712 {
2713 struct radeon_winsys_cs *cs = rctx->b.rings.gfx.cs;
2714 struct r600_cso_state *state = (struct r600_cso_state*)a;
2715 struct r600_fetch_shader *shader = (struct r600_fetch_shader*)state->cso;
2716
2717 r600_write_context_reg(cs, R_0288A4_SQ_PGM_START_FS,
2718 (r600_resource_va(rctx->b.b.screen, &shader->buffer->b.b) + shader->offset) >> 8);
2719 radeon_emit(cs, PKT3(PKT3_NOP, 0, 0));
2720 radeon_emit(cs, r600_context_bo_reloc(&rctx->b, &rctx->b.rings.gfx, shader->buffer, RADEON_USAGE_READ));
2721 }
2722
2723 static void evergreen_emit_shader_stages(struct r600_context *rctx, struct r600_atom *a)
2724 {
2725 struct radeon_winsys_cs *cs = rctx->b.rings.gfx.cs;
2726 struct r600_shader_stages_state *state = (struct r600_shader_stages_state*)a;
2727
2728 uint32_t v = 0, v2 = 0, primid = 0;
2729
2730 if (state->geom_enable) {
2731 v = S_028B54_ES_EN(V_028B54_ES_STAGE_REAL) |
2732 S_028B54_GS_EN(1) |
2733 S_028B54_VS_EN(V_028B54_VS_STAGE_COPY_SHADER);
2734
2735 v2 = S_028A40_MODE(V_028A40_GS_SCENARIO_G) |
2736 S_028A40_CUT_MODE(V_028A40_GS_CUT_128);
2737
2738 if (rctx->gs_shader->current->shader.gs_prim_id_input)
2739 primid = 1;
2740 }
2741
2742 r600_write_context_reg(cs, R_028B54_VGT_SHADER_STAGES_EN, v);
2743 r600_write_context_reg(cs, R_028A40_VGT_GS_MODE, v2);
2744 r600_write_context_reg(cs, R_028A84_VGT_PRIMITIVEID_EN, primid);
2745 }
2746
2747 static void evergreen_emit_gs_rings(struct r600_context *rctx, struct r600_atom *a)
2748 {
2749 struct pipe_screen *screen = rctx->b.b.screen;
2750 struct radeon_winsys_cs *cs = rctx->b.rings.gfx.cs;
2751 struct r600_gs_rings_state *state = (struct r600_gs_rings_state*)a;
2752 struct r600_resource *rbuffer;
2753
2754 r600_write_config_reg(cs, R_008040_WAIT_UNTIL, S_008040_WAIT_3D_IDLE(1));
2755 radeon_emit(cs, PKT3(PKT3_EVENT_WRITE, 0, 0));
2756 radeon_emit(cs, EVENT_TYPE(EVENT_TYPE_VGT_FLUSH));
2757
2758 if (state->enable) {
2759 rbuffer =(struct r600_resource*)state->esgs_ring.buffer;
2760 r600_write_config_reg(cs, R_008C40_SQ_ESGS_RING_BASE,
2761 (r600_resource_va(screen, &rbuffer->b.b)) >> 8);
2762 radeon_emit(cs, PKT3(PKT3_NOP, 0, 0));
2763 radeon_emit(cs, r600_context_bo_reloc(&rctx->b, &rctx->b.rings.gfx, rbuffer, RADEON_USAGE_READWRITE));
2764 r600_write_config_reg(cs, R_008C44_SQ_ESGS_RING_SIZE,
2765 state->esgs_ring.buffer_size >> 8);
2766
2767 rbuffer =(struct r600_resource*)state->gsvs_ring.buffer;
2768 r600_write_config_reg(cs, R_008C48_SQ_GSVS_RING_BASE,
2769 (r600_resource_va(screen, &rbuffer->b.b)) >> 8);
2770 radeon_emit(cs, PKT3(PKT3_NOP, 0, 0));
2771 radeon_emit(cs, r600_context_bo_reloc(&rctx->b, &rctx->b.rings.gfx, rbuffer, RADEON_USAGE_READWRITE));
2772 r600_write_config_reg(cs, R_008C4C_SQ_GSVS_RING_SIZE,
2773 state->gsvs_ring.buffer_size >> 8);
2774 } else {
2775 r600_write_config_reg(cs, R_008C44_SQ_ESGS_RING_SIZE, 0);
2776 r600_write_config_reg(cs, R_008C4C_SQ_GSVS_RING_SIZE, 0);
2777 }
2778
2779 r600_write_config_reg(cs, R_008040_WAIT_UNTIL, S_008040_WAIT_3D_IDLE(1));
2780 radeon_emit(cs, PKT3(PKT3_EVENT_WRITE, 0, 0));
2781 radeon_emit(cs, EVENT_TYPE(EVENT_TYPE_VGT_FLUSH));
2782 }
2783
2784 void cayman_init_common_regs(struct r600_command_buffer *cb,
2785 enum chip_class ctx_chip_class,
2786 enum radeon_family ctx_family,
2787 int ctx_drm_minor)
2788 {
2789 r600_store_config_reg_seq(cb, R_008C00_SQ_CONFIG, 2);
2790 r600_store_value(cb, S_008C00_EXPORT_SRC_C(1)); /* R_008C00_SQ_CONFIG */
2791 /* always set the temp clauses */
2792 r600_store_value(cb, S_008C04_NUM_CLAUSE_TEMP_GPRS(4)); /* R_008C04_SQ_GPR_RESOURCE_MGMT_1 */
2793
2794 r600_store_config_reg_seq(cb, R_008C10_SQ_GLOBAL_GPR_RESOURCE_MGMT_1, 2);
2795 r600_store_value(cb, 0); /* R_008C10_SQ_GLOBAL_GPR_RESOURCE_MGMT_1 */
2796 r600_store_value(cb, 0); /* R_008C14_SQ_GLOBAL_GPR_RESOURCE_MGMT_2 */
2797
2798 r600_store_config_reg(cb, R_008D8C_SQ_DYN_GPR_CNTL_PS_FLUSH_REQ, (1 << 8));
2799
2800 r600_store_context_reg(cb, R_028A4C_PA_SC_MODE_CNTL_1, 0);
2801
2802 r600_store_context_reg(cb, R_028354_SX_SURFACE_SYNC, S_028354_SURFACE_SYNC_MASK(0xf));
2803
2804 r600_store_context_reg(cb, R_028800_DB_DEPTH_CONTROL, 0);
2805 }
2806
2807 static void cayman_init_atom_start_cs(struct r600_context *rctx)
2808 {
2809 struct r600_command_buffer *cb = &rctx->start_cs_cmd;
2810
2811 r600_init_command_buffer(cb, 256);
2812
2813 /* This must be first. */
2814 r600_store_value(cb, PKT3(PKT3_CONTEXT_CONTROL, 1, 0));
2815 r600_store_value(cb, 0x80000000);
2816 r600_store_value(cb, 0x80000000);
2817
2818 /* We're setting config registers here. */
2819 r600_store_value(cb, PKT3(PKT3_EVENT_WRITE, 0, 0));
2820 r600_store_value(cb, EVENT_TYPE(EVENT_TYPE_PS_PARTIAL_FLUSH) | EVENT_INDEX(4));
2821
2822 cayman_init_common_regs(cb, rctx->b.chip_class,
2823 rctx->b.family, rctx->screen->b.info.drm_minor);
2824
2825 r600_store_config_reg(cb, R_009100_SPI_CONFIG_CNTL, 0);
2826 r600_store_config_reg(cb, R_00913C_SPI_CONFIG_CNTL_1, S_00913C_VTX_DONE_DELAY(4));
2827
2828 r600_store_context_reg_seq(cb, R_028900_SQ_ESGS_RING_ITEMSIZE, 6);
2829 r600_store_value(cb, 0); /* R_028900_SQ_ESGS_RING_ITEMSIZE */
2830 r600_store_value(cb, 0); /* R_028904_SQ_GSVS_RING_ITEMSIZE */
2831 r600_store_value(cb, 0); /* R_028908_SQ_ESTMP_RING_ITEMSIZE */
2832 r600_store_value(cb, 0); /* R_02890C_SQ_GSTMP_RING_ITEMSIZE */
2833 r600_store_value(cb, 0); /* R_028910_SQ_VSTMP_RING_ITEMSIZE */
2834 r600_store_value(cb, 0); /* R_028914_SQ_PSTMP_RING_ITEMSIZE */
2835
2836 r600_store_context_reg_seq(cb, R_02891C_SQ_GS_VERT_ITEMSIZE, 4);
2837 r600_store_value(cb, 0); /* R_02891C_SQ_GS_VERT_ITEMSIZE */
2838 r600_store_value(cb, 0); /* R_028920_SQ_GS_VERT_ITEMSIZE_1 */
2839 r600_store_value(cb, 0); /* R_028924_SQ_GS_VERT_ITEMSIZE_2 */
2840 r600_store_value(cb, 0); /* R_028928_SQ_GS_VERT_ITEMSIZE_3 */
2841
2842 r600_store_context_reg_seq(cb, R_028A10_VGT_OUTPUT_PATH_CNTL, 13);
2843 r600_store_value(cb, 0); /* R_028A10_VGT_OUTPUT_PATH_CNTL */
2844 r600_store_value(cb, 0); /* R_028A14_VGT_HOS_CNTL */
2845 r600_store_value(cb, 0); /* R_028A18_VGT_HOS_MAX_TESS_LEVEL */
2846 r600_store_value(cb, 0); /* R_028A1C_VGT_HOS_MIN_TESS_LEVEL */
2847 r600_store_value(cb, 0); /* R_028A20_VGT_HOS_REUSE_DEPTH */
2848 r600_store_value(cb, 0); /* R_028A24_VGT_GROUP_PRIM_TYPE */
2849 r600_store_value(cb, 0); /* R_028A28_VGT_GROUP_FIRST_DECR */
2850 r600_store_value(cb, 0); /* R_028A2C_VGT_GROUP_DECR */
2851 r600_store_value(cb, 0); /* R_028A30_VGT_GROUP_VECT_0_CNTL */
2852 r600_store_value(cb, 0); /* R_028A34_VGT_GROUP_VECT_1_CNTL */
2853 r600_store_value(cb, 0); /* R_028A38_VGT_GROUP_VECT_0_FMT_CNTL */
2854 r600_store_value(cb, 0); /* R_028A3C_VGT_GROUP_VECT_1_FMT_CNTL */
2855 r600_store_value(cb, 0); /* R_028A40_VGT_GS_MODE */
2856
2857 r600_store_context_reg_seq(cb, R_028B94_VGT_STRMOUT_CONFIG, 2);
2858 r600_store_value(cb, 0); /* R_028B94_VGT_STRMOUT_CONFIG */
2859 r600_store_value(cb, 0); /* R_028B98_VGT_STRMOUT_BUFFER_CONFIG */
2860
2861 r600_store_context_reg_seq(cb, R_028AB4_VGT_REUSE_OFF, 2);
2862 r600_store_value(cb, 0); /* R_028AB4_VGT_REUSE_OFF */
2863 r600_store_value(cb, 0); /* R_028AB8_VGT_VTX_CNT_EN */
2864
2865 r600_store_config_reg(cb, R_008A14_PA_CL_ENHANCE, (3 << 1) | 1);
2866
2867 r600_store_context_reg(cb, CM_R_028AA8_IA_MULTI_VGT_PARAM, S_028AA8_SWITCH_ON_EOP(1) | S_028AA8_PARTIAL_VS_WAVE_ON(1) | S_028AA8_PRIMGROUP_SIZE(63));
2868
2869 r600_store_context_reg_seq(cb, CM_R_028BD4_PA_SC_CENTROID_PRIORITY_0, 2);
2870 r600_store_value(cb, 0x76543210); /* CM_R_028BD4_PA_SC_CENTROID_PRIORITY_0 */
2871 r600_store_value(cb, 0xfedcba98); /* CM_R_028BD8_PA_SC_CENTROID_PRIORITY_1 */
2872
2873 r600_store_context_reg_seq(cb, CM_R_0288E8_SQ_LDS_ALLOC, 2);
2874 r600_store_value(cb, 0); /* CM_R_0288E8_SQ_LDS_ALLOC */
2875 r600_store_value(cb, 0); /* R_0288EC_SQ_LDS_ALLOC_PS */
2876
2877 r600_store_context_reg(cb, R_0288F0_SQ_VTX_SEMANTIC_CLEAR, ~0);
2878
2879 r600_store_context_reg_seq(cb, R_028400_VGT_MAX_VTX_INDX, 2);
2880 r600_store_value(cb, ~0); /* R_028400_VGT_MAX_VTX_INDX */
2881 r600_store_value(cb, 0); /* R_028404_VGT_MIN_VTX_INDX */
2882
2883 r600_store_ctl_const(cb, R_03CFF0_SQ_VTX_BASE_VTX_LOC, 0);
2884
2885 r600_store_context_reg(cb, R_028028_DB_STENCIL_CLEAR, 0);
2886
2887 r600_store_context_reg(cb, R_0286DC_SPI_FOG_CNTL, 0);
2888
2889 r600_store_context_reg_seq(cb, R_028AC0_DB_SRESULTS_COMPARE_STATE0, 3);
2890 r600_store_value(cb, 0); /* R_028AC0_DB_SRESULTS_COMPARE_STATE0 */
2891 r600_store_value(cb, 0); /* R_028AC4_DB_SRESULTS_COMPARE_STATE1 */
2892 r600_store_value(cb, 0); /* R_028AC8_DB_PRELOAD_CONTROL */
2893
2894 r600_store_context_reg(cb, R_028200_PA_SC_WINDOW_OFFSET, 0);
2895 r600_store_context_reg(cb, R_02820C_PA_SC_CLIPRECT_RULE, 0xFFFF);
2896
2897 r600_store_context_reg_seq(cb, R_0282D0_PA_SC_VPORT_ZMIN_0, 2);
2898 r600_store_value(cb, 0); /* R_0282D0_PA_SC_VPORT_ZMIN_0 */
2899 r600_store_value(cb, 0x3F800000); /* R_0282D4_PA_SC_VPORT_ZMAX_0 */
2900
2901 r600_store_context_reg(cb, R_028230_PA_SC_EDGERULE, 0xAAAAAAAA);
2902 r600_store_context_reg(cb, R_028818_PA_CL_VTE_CNTL, 0x0000043F);
2903 r600_store_context_reg(cb, R_028820_PA_CL_NANINF_CNTL, 0);
2904
2905 r600_store_context_reg_seq(cb, CM_R_028BE8_PA_CL_GB_VERT_CLIP_ADJ, 4);
2906 r600_store_value(cb, 0x3F800000); /* CM_R_028BE8_PA_CL_GB_VERT_CLIP_ADJ */
2907 r600_store_value(cb, 0x3F800000); /* CM_R_028BEC_PA_CL_GB_VERT_DISC_ADJ */
2908 r600_store_value(cb, 0x3F800000); /* CM_R_028BF0_PA_CL_GB_HORZ_CLIP_ADJ */
2909 r600_store_value(cb, 0x3F800000); /* CM_R_028BF4_PA_CL_GB_HORZ_DISC_ADJ */
2910
2911 r600_store_context_reg_seq(cb, R_028240_PA_SC_GENERIC_SCISSOR_TL, 2);
2912 r600_store_value(cb, 0); /* R_028240_PA_SC_GENERIC_SCISSOR_TL */
2913 r600_store_value(cb, S_028244_BR_X(16384) | S_028244_BR_Y(16384)); /* R_028244_PA_SC_GENERIC_SCISSOR_BR */
2914
2915 r600_store_context_reg_seq(cb, R_028030_PA_SC_SCREEN_SCISSOR_TL, 2);
2916 r600_store_value(cb, 0); /* R_028030_PA_SC_SCREEN_SCISSOR_TL */
2917 r600_store_value(cb, S_028034_BR_X(16384) | S_028034_BR_Y(16384)); /* R_028034_PA_SC_SCREEN_SCISSOR_BR */
2918
2919 r600_store_context_reg(cb, R_028848_SQ_PGM_RESOURCES_2_PS, S_028848_SINGLE_ROUND(V_SQ_ROUND_NEAREST_EVEN));
2920 r600_store_context_reg(cb, R_028864_SQ_PGM_RESOURCES_2_VS, S_028864_SINGLE_ROUND(V_SQ_ROUND_NEAREST_EVEN));
2921 r600_store_context_reg(cb, R_0288A8_SQ_PGM_RESOURCES_FS, 0);
2922
2923 /* to avoid GPU doing any preloading of constant from random address */
2924 r600_store_context_reg_seq(cb, R_028140_ALU_CONST_BUFFER_SIZE_PS_0, 16);
2925 r600_store_value(cb, 0); /* R_028140_ALU_CONST_BUFFER_SIZE_PS_0 */
2926 r600_store_value(cb, 0);
2927 r600_store_value(cb, 0);
2928 r600_store_value(cb, 0);
2929 r600_store_value(cb, 0);
2930 r600_store_value(cb, 0);
2931 r600_store_value(cb, 0);
2932 r600_store_value(cb, 0);
2933 r600_store_value(cb, 0);
2934 r600_store_value(cb, 0);
2935 r600_store_value(cb, 0);
2936 r600_store_value(cb, 0);
2937 r600_store_value(cb, 0);
2938 r600_store_value(cb, 0);
2939 r600_store_value(cb, 0);
2940 r600_store_value(cb, 0);
2941
2942 r600_store_context_reg_seq(cb, R_028180_ALU_CONST_BUFFER_SIZE_VS_0, 16);
2943 r600_store_value(cb, 0); /* R_028180_ALU_CONST_BUFFER_SIZE_VS_0 */
2944 r600_store_value(cb, 0);
2945 r600_store_value(cb, 0);
2946 r600_store_value(cb, 0);
2947 r600_store_value(cb, 0);
2948 r600_store_value(cb, 0);
2949 r600_store_value(cb, 0);
2950 r600_store_value(cb, 0);
2951 r600_store_value(cb, 0);
2952 r600_store_value(cb, 0);
2953 r600_store_value(cb, 0);
2954 r600_store_value(cb, 0);
2955 r600_store_value(cb, 0);
2956 r600_store_value(cb, 0);
2957 r600_store_value(cb, 0);
2958 r600_store_value(cb, 0);
2959
2960 if (rctx->screen->b.has_streamout) {
2961 r600_store_context_reg(cb, R_028B28_VGT_STRMOUT_DRAW_OPAQUE_OFFSET, 0);
2962 }
2963
2964 r600_store_context_reg(cb, R_028010_DB_RENDER_OVERRIDE2, 0);
2965 r600_store_context_reg(cb, R_028234_PA_SU_HARDWARE_SCREEN_OFFSET, 0);
2966 r600_store_context_reg(cb, R_0286C8_SPI_THREAD_GROUPING, 0);
2967 r600_store_context_reg_seq(cb, R_0286E4_SPI_PS_IN_CONTROL_2, 2);
2968 r600_store_value(cb, 0); /* R_0286E4_SPI_PS_IN_CONTROL_2 */
2969 r600_store_value(cb, 0); /* R_0286E8_SPI_COMPUTE_INPUT_CNTL */
2970 r600_store_context_reg(cb, R_028B54_VGT_SHADER_STAGES_EN, 0);
2971
2972 eg_store_loop_const(cb, R_03A200_SQ_LOOP_CONST_0, 0x01000FFF);
2973 eg_store_loop_const(cb, R_03A200_SQ_LOOP_CONST_0 + (32 * 4), 0x01000FFF);
2974 eg_store_loop_const(cb, R_03A200_SQ_LOOP_CONST_0 + (64 * 4), 0x01000FFF);
2975 }
2976
2977 void evergreen_init_common_regs(struct r600_command_buffer *cb,
2978 enum chip_class ctx_chip_class,
2979 enum radeon_family ctx_family,
2980 int ctx_drm_minor)
2981 {
2982 int ps_prio;
2983 int vs_prio;
2984 int gs_prio;
2985 int es_prio;
2986
2987 int hs_prio;
2988 int cs_prio;
2989 int ls_prio;
2990
2991 int num_ps_gprs;
2992 int num_vs_gprs;
2993 int num_gs_gprs;
2994 int num_es_gprs;
2995 int num_hs_gprs;
2996 int num_ls_gprs;
2997 int num_temp_gprs;
2998
2999 unsigned tmp;
3000
3001 ps_prio = 0;
3002 vs_prio = 1;
3003 gs_prio = 2;
3004 es_prio = 3;
3005 hs_prio = 0;
3006 ls_prio = 0;
3007 cs_prio = 0;
3008
3009 num_ps_gprs = 93;
3010 num_vs_gprs = 46;
3011 num_temp_gprs = 4;
3012 num_gs_gprs = 31;
3013 num_es_gprs = 31;
3014 num_hs_gprs = 23;
3015 num_ls_gprs = 23;
3016
3017 tmp = 0;
3018 switch (ctx_family) {
3019 case CHIP_CEDAR:
3020 case CHIP_PALM:
3021 case CHIP_SUMO:
3022 case CHIP_SUMO2:
3023 case CHIP_CAICOS:
3024 break;
3025 default:
3026 tmp |= S_008C00_VC_ENABLE(1);
3027 break;
3028 }
3029 tmp |= S_008C00_EXPORT_SRC_C(1);
3030 tmp |= S_008C00_CS_PRIO(cs_prio);
3031 tmp |= S_008C00_LS_PRIO(ls_prio);
3032 tmp |= S_008C00_HS_PRIO(hs_prio);
3033 tmp |= S_008C00_PS_PRIO(ps_prio);
3034 tmp |= S_008C00_VS_PRIO(vs_prio);
3035 tmp |= S_008C00_GS_PRIO(gs_prio);
3036 tmp |= S_008C00_ES_PRIO(es_prio);
3037
3038 /* enable dynamic GPR resource management */
3039 if (ctx_drm_minor >= 7) {
3040 r600_store_config_reg_seq(cb, R_008C00_SQ_CONFIG, 2);
3041 r600_store_value(cb, tmp); /* R_008C00_SQ_CONFIG */
3042 /* always set temp clauses */
3043 r600_store_value(cb, S_008C04_NUM_CLAUSE_TEMP_GPRS(num_temp_gprs)); /* R_008C04_SQ_GPR_RESOURCE_MGMT_1 */
3044 r600_store_config_reg_seq(cb, R_008C10_SQ_GLOBAL_GPR_RESOURCE_MGMT_1, 2);
3045 r600_store_value(cb, 0); /* R_008C10_SQ_GLOBAL_GPR_RESOURCE_MGMT_1 */
3046 r600_store_value(cb, 0); /* R_008C14_SQ_GLOBAL_GPR_RESOURCE_MGMT_2 */
3047 r600_store_config_reg(cb, R_008D8C_SQ_DYN_GPR_CNTL_PS_FLUSH_REQ, (1 << 8));
3048 r600_store_context_reg(cb, R_028838_SQ_DYN_GPR_RESOURCE_LIMIT_1,
3049 S_028838_PS_GPRS(0x1e) |
3050 S_028838_VS_GPRS(0x1e) |
3051 S_028838_GS_GPRS(0x1e) |
3052 S_028838_ES_GPRS(0x1e) |
3053 S_028838_HS_GPRS(0x1e) |
3054 S_028838_LS_GPRS(0x1e)); /* workaround for hw issues with dyn gpr - must set all limits to 240 instead of 0, 0x1e == 240 / 8*/
3055 } else {
3056 r600_store_config_reg_seq(cb, R_008C00_SQ_CONFIG, 4);
3057 r600_store_value(cb, tmp); /* R_008C00_SQ_CONFIG */
3058
3059 tmp = S_008C04_NUM_PS_GPRS(num_ps_gprs);
3060 tmp |= S_008C04_NUM_VS_GPRS(num_vs_gprs);
3061 tmp |= S_008C04_NUM_CLAUSE_TEMP_GPRS(num_temp_gprs);
3062 r600_store_value(cb, tmp); /* R_008C04_SQ_GPR_RESOURCE_MGMT_1 */
3063
3064 tmp = S_008C08_NUM_GS_GPRS(num_gs_gprs);
3065 tmp |= S_008C08_NUM_ES_GPRS(num_es_gprs);
3066 r600_store_value(cb, tmp); /* R_008C08_SQ_GPR_RESOURCE_MGMT_2 */
3067
3068 tmp = S_008C0C_NUM_HS_GPRS(num_hs_gprs);
3069 tmp |= S_008C0C_NUM_HS_GPRS(num_ls_gprs);
3070 r600_store_value(cb, tmp); /* R_008C0C_SQ_GPR_RESOURCE_MGMT_3 */
3071 }
3072
3073 r600_store_context_reg(cb, R_028A4C_PA_SC_MODE_CNTL_1, 0);
3074
3075 /* The cs checker requires this register to be set. */
3076 r600_store_context_reg(cb, R_028800_DB_DEPTH_CONTROL, 0);
3077
3078 r600_store_context_reg(cb, R_028354_SX_SURFACE_SYNC, S_028354_SURFACE_SYNC_MASK(0xf));
3079
3080 return;
3081 }
3082
3083 void evergreen_init_atom_start_cs(struct r600_context *rctx)
3084 {
3085 struct r600_command_buffer *cb = &rctx->start_cs_cmd;
3086 int num_ps_threads;
3087 int num_vs_threads;
3088 int num_gs_threads;
3089 int num_es_threads;
3090 int num_hs_threads;
3091 int num_ls_threads;
3092
3093 int num_ps_stack_entries;
3094 int num_vs_stack_entries;
3095 int num_gs_stack_entries;
3096 int num_es_stack_entries;
3097 int num_hs_stack_entries;
3098 int num_ls_stack_entries;
3099 enum radeon_family family;
3100 unsigned tmp;
3101
3102 if (rctx->b.chip_class == CAYMAN) {
3103 cayman_init_atom_start_cs(rctx);
3104 return;
3105 }
3106
3107 r600_init_command_buffer(cb, 256);
3108
3109 /* This must be first. */
3110 r600_store_value(cb, PKT3(PKT3_CONTEXT_CONTROL, 1, 0));
3111 r600_store_value(cb, 0x80000000);
3112 r600_store_value(cb, 0x80000000);
3113
3114 /* We're setting config registers here. */
3115 r600_store_value(cb, PKT3(PKT3_EVENT_WRITE, 0, 0));
3116 r600_store_value(cb, EVENT_TYPE(EVENT_TYPE_PS_PARTIAL_FLUSH) | EVENT_INDEX(4));
3117
3118 evergreen_init_common_regs(cb, rctx->b.chip_class,
3119 rctx->b.family, rctx->screen->b.info.drm_minor);
3120
3121 family = rctx->b.family;
3122 switch (family) {
3123 case CHIP_CEDAR:
3124 default:
3125 num_ps_threads = 96;
3126 num_vs_threads = 16;
3127 num_gs_threads = 16;
3128 num_es_threads = 16;
3129 num_hs_threads = 16;
3130 num_ls_threads = 16;
3131 num_ps_stack_entries = 42;
3132 num_vs_stack_entries = 42;
3133 num_gs_stack_entries = 42;
3134 num_es_stack_entries = 42;
3135 num_hs_stack_entries = 42;
3136 num_ls_stack_entries = 42;
3137 break;
3138 case CHIP_REDWOOD:
3139 num_ps_threads = 128;
3140 num_vs_threads = 20;
3141 num_gs_threads = 20;
3142 num_es_threads = 20;
3143 num_hs_threads = 20;
3144 num_ls_threads = 20;
3145 num_ps_stack_entries = 42;
3146 num_vs_stack_entries = 42;
3147 num_gs_stack_entries = 42;
3148 num_es_stack_entries = 42;
3149 num_hs_stack_entries = 42;
3150 num_ls_stack_entries = 42;
3151 break;
3152 case CHIP_JUNIPER:
3153 num_ps_threads = 128;
3154 num_vs_threads = 20;
3155 num_gs_threads = 20;
3156 num_es_threads = 20;
3157 num_hs_threads = 20;
3158 num_ls_threads = 20;
3159 num_ps_stack_entries = 85;
3160 num_vs_stack_entries = 85;
3161 num_gs_stack_entries = 85;
3162 num_es_stack_entries = 85;
3163 num_hs_stack_entries = 85;
3164 num_ls_stack_entries = 85;
3165 break;
3166 case CHIP_CYPRESS:
3167 case CHIP_HEMLOCK:
3168 num_ps_threads = 128;
3169 num_vs_threads = 20;
3170 num_gs_threads = 20;
3171 num_es_threads = 20;
3172 num_hs_threads = 20;
3173 num_ls_threads = 20;
3174 num_ps_stack_entries = 85;
3175 num_vs_stack_entries = 85;
3176 num_gs_stack_entries = 85;
3177 num_es_stack_entries = 85;
3178 num_hs_stack_entries = 85;
3179 num_ls_stack_entries = 85;
3180 break;
3181 case CHIP_PALM:
3182 num_ps_threads = 96;
3183 num_vs_threads = 16;
3184 num_gs_threads = 16;
3185 num_es_threads = 16;
3186 num_hs_threads = 16;
3187 num_ls_threads = 16;
3188 num_ps_stack_entries = 42;
3189 num_vs_stack_entries = 42;
3190 num_gs_stack_entries = 42;
3191 num_es_stack_entries = 42;
3192 num_hs_stack_entries = 42;
3193 num_ls_stack_entries = 42;
3194 break;
3195 case CHIP_SUMO:
3196 num_ps_threads = 96;
3197 num_vs_threads = 25;
3198 num_gs_threads = 25;
3199 num_es_threads = 25;
3200 num_hs_threads = 25;
3201 num_ls_threads = 25;
3202 num_ps_stack_entries = 42;
3203 num_vs_stack_entries = 42;
3204 num_gs_stack_entries = 42;
3205 num_es_stack_entries = 42;
3206 num_hs_stack_entries = 42;
3207 num_ls_stack_entries = 42;
3208 break;
3209 case CHIP_SUMO2:
3210 num_ps_threads = 96;
3211 num_vs_threads = 25;
3212 num_gs_threads = 25;
3213 num_es_threads = 25;
3214 num_hs_threads = 25;
3215 num_ls_threads = 25;
3216 num_ps_stack_entries = 85;
3217 num_vs_stack_entries = 85;
3218 num_gs_stack_entries = 85;
3219 num_es_stack_entries = 85;
3220 num_hs_stack_entries = 85;
3221 num_ls_stack_entries = 85;
3222 break;
3223 case CHIP_BARTS:
3224 num_ps_threads = 128;
3225 num_vs_threads = 20;
3226 num_gs_threads = 20;
3227 num_es_threads = 20;
3228 num_hs_threads = 20;
3229 num_ls_threads = 20;
3230 num_ps_stack_entries = 85;
3231 num_vs_stack_entries = 85;
3232 num_gs_stack_entries = 85;
3233 num_es_stack_entries = 85;
3234 num_hs_stack_entries = 85;
3235 num_ls_stack_entries = 85;
3236 break;
3237 case CHIP_TURKS:
3238 num_ps_threads = 128;
3239 num_vs_threads = 20;
3240 num_gs_threads = 20;
3241 num_es_threads = 20;
3242 num_hs_threads = 20;
3243 num_ls_threads = 20;
3244 num_ps_stack_entries = 42;
3245 num_vs_stack_entries = 42;
3246 num_gs_stack_entries = 42;
3247 num_es_stack_entries = 42;
3248 num_hs_stack_entries = 42;
3249 num_ls_stack_entries = 42;
3250 break;
3251 case CHIP_CAICOS:
3252 num_ps_threads = 128;
3253 num_vs_threads = 10;
3254 num_gs_threads = 10;
3255 num_es_threads = 10;
3256 num_hs_threads = 10;
3257 num_ls_threads = 10;
3258 num_ps_stack_entries = 42;
3259 num_vs_stack_entries = 42;
3260 num_gs_stack_entries = 42;
3261 num_es_stack_entries = 42;
3262 num_hs_stack_entries = 42;
3263 num_ls_stack_entries = 42;
3264 break;
3265 }
3266
3267 tmp = S_008C18_NUM_PS_THREADS(num_ps_threads);
3268 tmp |= S_008C18_NUM_VS_THREADS(num_vs_threads);
3269 tmp |= S_008C18_NUM_GS_THREADS(num_gs_threads);
3270 tmp |= S_008C18_NUM_ES_THREADS(num_es_threads);
3271
3272 r600_store_config_reg_seq(cb, R_008C18_SQ_THREAD_RESOURCE_MGMT_1, 5);
3273 r600_store_value(cb, tmp); /* R_008C18_SQ_THREAD_RESOURCE_MGMT_1 */
3274
3275 tmp = S_008C1C_NUM_HS_THREADS(num_hs_threads);
3276 tmp |= S_008C1C_NUM_LS_THREADS(num_ls_threads);
3277 r600_store_value(cb, tmp); /* R_008C1C_SQ_THREAD_RESOURCE_MGMT_2 */
3278
3279 tmp = S_008C20_NUM_PS_STACK_ENTRIES(num_ps_stack_entries);
3280 tmp |= S_008C20_NUM_VS_STACK_ENTRIES(num_vs_stack_entries);
3281 r600_store_value(cb, tmp); /* R_008C20_SQ_STACK_RESOURCE_MGMT_1 */
3282
3283 tmp = S_008C24_NUM_GS_STACK_ENTRIES(num_gs_stack_entries);
3284 tmp |= S_008C24_NUM_ES_STACK_ENTRIES(num_es_stack_entries);
3285 r600_store_value(cb, tmp); /* R_008C24_SQ_STACK_RESOURCE_MGMT_2 */
3286
3287 tmp = S_008C28_NUM_HS_STACK_ENTRIES(num_hs_stack_entries);
3288 tmp |= S_008C28_NUM_LS_STACK_ENTRIES(num_ls_stack_entries);
3289 r600_store_value(cb, tmp); /* R_008C28_SQ_STACK_RESOURCE_MGMT_3 */
3290
3291 r600_store_config_reg(cb, R_008E2C_SQ_LDS_RESOURCE_MGMT,
3292 S_008E2C_NUM_PS_LDS(0x1000) | S_008E2C_NUM_LS_LDS(0x1000));
3293
3294 r600_store_config_reg(cb, R_009100_SPI_CONFIG_CNTL, 0);
3295 r600_store_config_reg(cb, R_00913C_SPI_CONFIG_CNTL_1, S_00913C_VTX_DONE_DELAY(4));
3296
3297 r600_store_context_reg_seq(cb, R_028900_SQ_ESGS_RING_ITEMSIZE, 6);
3298 r600_store_value(cb, 0); /* R_028900_SQ_ESGS_RING_ITEMSIZE */
3299 r600_store_value(cb, 0); /* R_028904_SQ_GSVS_RING_ITEMSIZE */
3300 r600_store_value(cb, 0); /* R_028908_SQ_ESTMP_RING_ITEMSIZE */
3301 r600_store_value(cb, 0); /* R_02890C_SQ_GSTMP_RING_ITEMSIZE */
3302 r600_store_value(cb, 0); /* R_028910_SQ_VSTMP_RING_ITEMSIZE */
3303 r600_store_value(cb, 0); /* R_028914_SQ_PSTMP_RING_ITEMSIZE */
3304
3305 r600_store_context_reg_seq(cb, R_02891C_SQ_GS_VERT_ITEMSIZE, 4);
3306 r600_store_value(cb, 0); /* R_02891C_SQ_GS_VERT_ITEMSIZE */
3307 r600_store_value(cb, 0); /* R_028920_SQ_GS_VERT_ITEMSIZE_1 */
3308 r600_store_value(cb, 0); /* R_028924_SQ_GS_VERT_ITEMSIZE_2 */
3309 r600_store_value(cb, 0); /* R_028928_SQ_GS_VERT_ITEMSIZE_3 */
3310
3311 r600_store_context_reg_seq(cb, R_028A10_VGT_OUTPUT_PATH_CNTL, 13);
3312 r600_store_value(cb, 0); /* R_028A10_VGT_OUTPUT_PATH_CNTL */
3313 r600_store_value(cb, 0); /* R_028A14_VGT_HOS_CNTL */
3314 r600_store_value(cb, 0); /* R_028A18_VGT_HOS_MAX_TESS_LEVEL */
3315 r600_store_value(cb, 0); /* R_028A1C_VGT_HOS_MIN_TESS_LEVEL */
3316 r600_store_value(cb, 0); /* R_028A20_VGT_HOS_REUSE_DEPTH */
3317 r600_store_value(cb, 0); /* R_028A24_VGT_GROUP_PRIM_TYPE */
3318 r600_store_value(cb, 0); /* R_028A28_VGT_GROUP_FIRST_DECR */
3319 r600_store_value(cb, 0); /* R_028A2C_VGT_GROUP_DECR */
3320 r600_store_value(cb, 0); /* R_028A30_VGT_GROUP_VECT_0_CNTL */
3321 r600_store_value(cb, 0); /* R_028A34_VGT_GROUP_VECT_1_CNTL */
3322 r600_store_value(cb, 0); /* R_028A38_VGT_GROUP_VECT_0_FMT_CNTL */
3323 r600_store_value(cb, 0); /* R_028A3C_VGT_GROUP_VECT_1_FMT_CNTL */
3324 r600_store_value(cb, 0); /* R_028A40_VGT_GS_MODE */
3325
3326 r600_store_context_reg_seq(cb, R_028AB4_VGT_REUSE_OFF, 2);
3327 r600_store_value(cb, 0); /* R_028AB4_VGT_REUSE_OFF */
3328 r600_store_value(cb, 0); /* R_028AB8_VGT_VTX_CNT_EN */
3329
3330 r600_store_config_reg(cb, R_008A14_PA_CL_ENHANCE, (3 << 1) | 1);
3331
3332 r600_store_context_reg(cb, R_0288F0_SQ_VTX_SEMANTIC_CLEAR, ~0);
3333
3334 r600_store_context_reg_seq(cb, R_028400_VGT_MAX_VTX_INDX, 2);
3335 r600_store_value(cb, ~0); /* R_028400_VGT_MAX_VTX_INDX */
3336 r600_store_value(cb, 0); /* R_028404_VGT_MIN_VTX_INDX */
3337
3338 r600_store_ctl_const(cb, R_03CFF0_SQ_VTX_BASE_VTX_LOC, 0);
3339
3340 r600_store_context_reg(cb, R_028028_DB_STENCIL_CLEAR, 0);
3341
3342 r600_store_context_reg(cb, R_028200_PA_SC_WINDOW_OFFSET, 0);
3343 r600_store_context_reg(cb, R_02820C_PA_SC_CLIPRECT_RULE, 0xFFFF);
3344 r600_store_context_reg(cb, R_028230_PA_SC_EDGERULE, 0xAAAAAAAA);
3345
3346 r600_store_context_reg_seq(cb, R_0282D0_PA_SC_VPORT_ZMIN_0, 2);
3347 r600_store_value(cb, 0); /* R_0282D0_PA_SC_VPORT_ZMIN_0 */
3348 r600_store_value(cb, 0x3F800000); /* R_0282D4_PA_SC_VPORT_ZMAX_0 */
3349
3350 r600_store_context_reg(cb, R_0286DC_SPI_FOG_CNTL, 0);
3351 r600_store_context_reg(cb, R_028818_PA_CL_VTE_CNTL, 0x0000043F);
3352 r600_store_context_reg(cb, R_028820_PA_CL_NANINF_CNTL, 0);
3353
3354 r600_store_context_reg_seq(cb, R_028AC0_DB_SRESULTS_COMPARE_STATE0, 3);
3355 r600_store_value(cb, 0); /* R_028AC0_DB_SRESULTS_COMPARE_STATE0 */
3356 r600_store_value(cb, 0); /* R_028AC4_DB_SRESULTS_COMPARE_STATE1 */
3357 r600_store_value(cb, 0); /* R_028AC8_DB_PRELOAD_CONTROL */
3358
3359 r600_store_context_reg_seq(cb, R_028C0C_PA_CL_GB_VERT_CLIP_ADJ, 4);
3360 r600_store_value(cb, 0x3F800000); /* R_028C0C_PA_CL_GB_VERT_CLIP_ADJ */
3361 r600_store_value(cb, 0x3F800000); /* R_028C10_PA_CL_GB_VERT_DISC_ADJ */
3362 r600_store_value(cb, 0x3F800000); /* R_028C14_PA_CL_GB_HORZ_CLIP_ADJ */
3363 r600_store_value(cb, 0x3F800000); /* R_028C18_PA_CL_GB_HORZ_DISC_ADJ */
3364
3365 r600_store_context_reg_seq(cb, R_028240_PA_SC_GENERIC_SCISSOR_TL, 2);
3366 r600_store_value(cb, 0); /* R_028240_PA_SC_GENERIC_SCISSOR_TL */
3367 r600_store_value(cb, S_028244_BR_X(16384) | S_028244_BR_Y(16384)); /* R_028244_PA_SC_GENERIC_SCISSOR_BR */
3368
3369 r600_store_context_reg_seq(cb, R_028030_PA_SC_SCREEN_SCISSOR_TL, 2);
3370 r600_store_value(cb, 0); /* R_028030_PA_SC_SCREEN_SCISSOR_TL */
3371 r600_store_value(cb, S_028034_BR_X(16384) | S_028034_BR_Y(16384)); /* R_028034_PA_SC_SCREEN_SCISSOR_BR */
3372
3373 r600_store_context_reg(cb, R_028848_SQ_PGM_RESOURCES_2_PS, S_028848_SINGLE_ROUND(V_SQ_ROUND_NEAREST_EVEN));
3374 r600_store_context_reg(cb, R_028864_SQ_PGM_RESOURCES_2_VS, S_028864_SINGLE_ROUND(V_SQ_ROUND_NEAREST_EVEN));
3375 r600_store_context_reg(cb, R_0288A8_SQ_PGM_RESOURCES_FS, 0);
3376
3377 /* to avoid GPU doing any preloading of constant from random address */
3378 r600_store_context_reg_seq(cb, R_028140_ALU_CONST_BUFFER_SIZE_PS_0, 16);
3379 r600_store_value(cb, 0); /* R_028140_ALU_CONST_BUFFER_SIZE_PS_0 */
3380 r600_store_value(cb, 0);
3381 r600_store_value(cb, 0);
3382 r600_store_value(cb, 0);
3383 r600_store_value(cb, 0);
3384 r600_store_value(cb, 0);
3385 r600_store_value(cb, 0);
3386 r600_store_value(cb, 0);
3387 r600_store_value(cb, 0);
3388 r600_store_value(cb, 0);
3389 r600_store_value(cb, 0);
3390 r600_store_value(cb, 0);
3391 r600_store_value(cb, 0);
3392 r600_store_value(cb, 0);
3393 r600_store_value(cb, 0);
3394 r600_store_value(cb, 0);
3395
3396 r600_store_context_reg_seq(cb, R_028180_ALU_CONST_BUFFER_SIZE_VS_0, 16);
3397 r600_store_value(cb, 0); /* R_028180_ALU_CONST_BUFFER_SIZE_VS_0 */
3398 r600_store_value(cb, 0);
3399 r600_store_value(cb, 0);
3400 r600_store_value(cb, 0);
3401 r600_store_value(cb, 0);
3402 r600_store_value(cb, 0);
3403 r600_store_value(cb, 0);
3404 r600_store_value(cb, 0);
3405 r600_store_value(cb, 0);
3406 r600_store_value(cb, 0);
3407 r600_store_value(cb, 0);
3408 r600_store_value(cb, 0);
3409 r600_store_value(cb, 0);
3410 r600_store_value(cb, 0);
3411 r600_store_value(cb, 0);
3412 r600_store_value(cb, 0);
3413
3414 r600_store_context_reg_seq(cb, R_028B94_VGT_STRMOUT_CONFIG, 2);
3415 r600_store_value(cb, 0); /* R_028B94_VGT_STRMOUT_CONFIG */
3416 r600_store_value(cb, 0); /* R_028B98_VGT_STRMOUT_BUFFER_CONFIG */
3417
3418 if (rctx->screen->b.has_streamout) {
3419 r600_store_context_reg(cb, R_028B28_VGT_STRMOUT_DRAW_OPAQUE_OFFSET, 0);
3420 }
3421
3422 r600_store_context_reg(cb, R_028010_DB_RENDER_OVERRIDE2, 0);
3423 r600_store_context_reg(cb, R_028234_PA_SU_HARDWARE_SCREEN_OFFSET, 0);
3424 r600_store_context_reg(cb, R_0286C8_SPI_THREAD_GROUPING, 0);
3425 r600_store_context_reg_seq(cb, R_0286E4_SPI_PS_IN_CONTROL_2, 2);
3426 r600_store_value(cb, 0); /* R_0286E4_SPI_PS_IN_CONTROL_2 */
3427 r600_store_value(cb, 0); /* R_0286E8_SPI_COMPUTE_INPUT_CNTL */
3428 r600_store_context_reg(cb, R_0288EC_SQ_LDS_ALLOC_PS, 0);
3429 r600_store_context_reg(cb, R_028B54_VGT_SHADER_STAGES_EN, 0);
3430
3431 eg_store_loop_const(cb, R_03A200_SQ_LOOP_CONST_0, 0x01000FFF);
3432 eg_store_loop_const(cb, R_03A200_SQ_LOOP_CONST_0 + (32 * 4), 0x01000FFF);
3433 eg_store_loop_const(cb, R_03A200_SQ_LOOP_CONST_0 + (64 * 4), 0x01000FFF);
3434 }
3435
3436 void evergreen_update_ps_state(struct pipe_context *ctx, struct r600_pipe_shader *shader)
3437 {
3438 struct r600_context *rctx = (struct r600_context *)ctx;
3439 struct r600_command_buffer *cb = &shader->command_buffer;
3440 struct r600_shader *rshader = &shader->shader;
3441 unsigned i, exports_ps, num_cout, spi_ps_in_control_0, spi_input_z, spi_ps_in_control_1, db_shader_control = 0;
3442 int pos_index = -1, face_index = -1;
3443 int ninterp = 0;
3444 boolean have_linear = FALSE, have_centroid = FALSE, have_perspective = FALSE;
3445 unsigned spi_baryc_cntl, sid, tmp, num = 0;
3446 unsigned z_export = 0, stencil_export = 0;
3447 unsigned sprite_coord_enable = rctx->rasterizer ? rctx->rasterizer->sprite_coord_enable : 0;
3448 uint32_t spi_ps_input_cntl[32];
3449
3450 if (!cb->buf) {
3451 r600_init_command_buffer(cb, 64);
3452 } else {
3453 cb->num_dw = 0;
3454 }
3455
3456 for (i = 0; i < rshader->ninput; i++) {
3457 /* evergreen NUM_INTERP only contains values interpolated into the LDS,
3458 POSITION goes via GPRs from the SC so isn't counted */
3459 if (rshader->input[i].name == TGSI_SEMANTIC_POSITION)
3460 pos_index = i;
3461 else if (rshader->input[i].name == TGSI_SEMANTIC_FACE)
3462 face_index = i;
3463 else {
3464 ninterp++;
3465 if (rshader->input[i].interpolate == TGSI_INTERPOLATE_LINEAR)
3466 have_linear = TRUE;
3467 if (rshader->input[i].interpolate == TGSI_INTERPOLATE_PERSPECTIVE)
3468 have_perspective = TRUE;
3469 if (rshader->input[i].centroid)
3470 have_centroid = TRUE;
3471 }
3472
3473 sid = rshader->input[i].spi_sid;
3474
3475 if (sid) {
3476 tmp = S_028644_SEMANTIC(sid);
3477
3478 if (rshader->input[i].name == TGSI_SEMANTIC_POSITION ||
3479 rshader->input[i].interpolate == TGSI_INTERPOLATE_CONSTANT ||
3480 (rshader->input[i].interpolate == TGSI_INTERPOLATE_COLOR &&
3481 rctx->rasterizer && rctx->rasterizer->flatshade)) {
3482 tmp |= S_028644_FLAT_SHADE(1);
3483 }
3484
3485 if (rshader->input[i].name == TGSI_SEMANTIC_GENERIC &&
3486 (sprite_coord_enable & (1 << rshader->input[i].sid))) {
3487 tmp |= S_028644_PT_SPRITE_TEX(1);
3488 }
3489
3490 spi_ps_input_cntl[num++] = tmp;
3491 }
3492 }
3493
3494 r600_store_context_reg_seq(cb, R_028644_SPI_PS_INPUT_CNTL_0, num);
3495 r600_store_array(cb, num, spi_ps_input_cntl);
3496
3497 for (i = 0; i < rshader->noutput; i++) {
3498 if (rshader->output[i].name == TGSI_SEMANTIC_POSITION)
3499 z_export = 1;
3500 if (rshader->output[i].name == TGSI_SEMANTIC_STENCIL)
3501 stencil_export = 1;
3502 }
3503 if (rshader->uses_kill)
3504 db_shader_control |= S_02880C_KILL_ENABLE(1);
3505
3506 db_shader_control |= S_02880C_Z_EXPORT_ENABLE(z_export);
3507 db_shader_control |= S_02880C_STENCIL_EXPORT_ENABLE(stencil_export);
3508
3509 exports_ps = 0;
3510 for (i = 0; i < rshader->noutput; i++) {
3511 if (rshader->output[i].name == TGSI_SEMANTIC_POSITION ||
3512 rshader->output[i].name == TGSI_SEMANTIC_STENCIL)
3513 exports_ps |= 1;
3514 }
3515
3516 num_cout = rshader->nr_ps_color_exports;
3517
3518 exports_ps |= S_02884C_EXPORT_COLORS(num_cout);
3519 if (!exports_ps) {
3520 /* always at least export 1 component per pixel */
3521 exports_ps = 2;
3522 }
3523 shader->nr_ps_color_outputs = num_cout;
3524 if (ninterp == 0) {
3525 ninterp = 1;
3526 have_perspective = TRUE;
3527 }
3528
3529 if (!have_perspective && !have_linear)
3530 have_perspective = TRUE;
3531
3532 spi_ps_in_control_0 = S_0286CC_NUM_INTERP(ninterp) |
3533 S_0286CC_PERSP_GRADIENT_ENA(have_perspective) |
3534 S_0286CC_LINEAR_GRADIENT_ENA(have_linear);
3535 spi_input_z = 0;
3536 if (pos_index != -1) {
3537 spi_ps_in_control_0 |= S_0286CC_POSITION_ENA(1) |
3538 S_0286CC_POSITION_CENTROID(rshader->input[pos_index].centroid) |
3539 S_0286CC_POSITION_ADDR(rshader->input[pos_index].gpr);
3540 spi_input_z |= S_0286D8_PROVIDE_Z_TO_SPI(1);
3541 }
3542
3543 spi_ps_in_control_1 = 0;
3544 if (face_index != -1) {
3545 spi_ps_in_control_1 |= S_0286D0_FRONT_FACE_ENA(1) |
3546 S_0286D0_FRONT_FACE_ADDR(rshader->input[face_index].gpr);
3547 }
3548
3549 spi_baryc_cntl = 0;
3550 if (have_perspective)
3551 spi_baryc_cntl |= S_0286E0_PERSP_CENTER_ENA(1) |
3552 S_0286E0_PERSP_CENTROID_ENA(have_centroid);
3553 if (have_linear)
3554 spi_baryc_cntl |= S_0286E0_LINEAR_CENTER_ENA(1) |
3555 S_0286E0_LINEAR_CENTROID_ENA(have_centroid);
3556
3557 r600_store_context_reg_seq(cb, R_0286CC_SPI_PS_IN_CONTROL_0, 2);
3558 r600_store_value(cb, spi_ps_in_control_0); /* R_0286CC_SPI_PS_IN_CONTROL_0 */
3559 r600_store_value(cb, spi_ps_in_control_1); /* R_0286D0_SPI_PS_IN_CONTROL_1 */
3560
3561 r600_store_context_reg(cb, R_0286E0_SPI_BARYC_CNTL, spi_baryc_cntl);
3562 r600_store_context_reg(cb, R_0286D8_SPI_INPUT_Z, spi_input_z);
3563 r600_store_context_reg(cb, R_02884C_SQ_PGM_EXPORTS_PS, exports_ps);
3564
3565 r600_store_context_reg_seq(cb, R_028840_SQ_PGM_START_PS, 2);
3566 r600_store_value(cb, r600_resource_va(ctx->screen, (void *)shader->bo) >> 8);
3567 r600_store_value(cb, /* R_028844_SQ_PGM_RESOURCES_PS */
3568 S_028844_NUM_GPRS(rshader->bc.ngpr) |
3569 S_028844_PRIME_CACHE_ON_DRAW(1) |
3570 S_028844_STACK_SIZE(rshader->bc.nstack));
3571 /* After that, the NOP relocation packet must be emitted (shader->bo, RADEON_USAGE_READ). */
3572
3573 shader->db_shader_control = db_shader_control;
3574 shader->ps_depth_export = z_export | stencil_export;
3575
3576 shader->sprite_coord_enable = sprite_coord_enable;
3577 if (rctx->rasterizer)
3578 shader->flatshade = rctx->rasterizer->flatshade;
3579 }
3580
3581 void evergreen_update_es_state(struct pipe_context *ctx, struct r600_pipe_shader *shader)
3582 {
3583 struct r600_command_buffer *cb = &shader->command_buffer;
3584 struct r600_shader *rshader = &shader->shader;
3585
3586 r600_init_command_buffer(cb, 32);
3587
3588 r600_store_context_reg(cb, R_028890_SQ_PGM_RESOURCES_ES,
3589 S_028890_NUM_GPRS(rshader->bc.ngpr) |
3590 S_028890_STACK_SIZE(rshader->bc.nstack));
3591 r600_store_context_reg(cb, R_02888C_SQ_PGM_START_ES,
3592 r600_resource_va(ctx->screen, (void *)shader->bo) >> 8);
3593 /* After that, the NOP relocation packet must be emitted (shader->bo, RADEON_USAGE_READ). */
3594 }
3595
3596 void evergreen_update_gs_state(struct pipe_context *ctx, struct r600_pipe_shader *shader)
3597 {
3598 struct r600_context *rctx = (struct r600_context *)ctx;
3599 struct r600_command_buffer *cb = &shader->command_buffer;
3600 struct r600_shader *rshader = &shader->shader;
3601 struct r600_shader *cp_shader = &shader->gs_copy_shader->shader;
3602 unsigned gsvs_itemsize =
3603 (cp_shader->ring_item_size * rshader->gs_max_out_vertices) >> 2;
3604
3605 r600_init_command_buffer(cb, 64);
3606
3607 /* VGT_GS_OUT_PRIM_TYPE is written by r6000_draw_vbo */
3608 /* VGT_GS_MODE is written by evergreen_emit_shader_stages */
3609
3610 r600_store_context_reg(cb, R_028AB8_VGT_VTX_CNT_EN, 1);
3611
3612 r600_store_context_reg(cb, R_028B38_VGT_GS_MAX_VERT_OUT,
3613 S_028B38_MAX_VERT_OUT(rshader->gs_max_out_vertices));
3614
3615 if (rctx->screen->b.info.drm_minor >= 35) {
3616 r600_store_context_reg(cb, R_028B90_VGT_GS_INSTANCE_CNT,
3617 S_028B90_CNT(0) |
3618 S_028B90_ENABLE(0));
3619 }
3620 r600_store_context_reg_seq(cb, R_02891C_SQ_GS_VERT_ITEMSIZE, 4);
3621 r600_store_value(cb, cp_shader->ring_item_size >> 2);
3622 r600_store_value(cb, 0);
3623 r600_store_value(cb, 0);
3624 r600_store_value(cb, 0);
3625
3626 r600_store_context_reg(cb, R_028900_SQ_ESGS_RING_ITEMSIZE,
3627 (rshader->ring_item_size) >> 2);
3628
3629 r600_store_context_reg(cb, R_028904_SQ_GSVS_RING_ITEMSIZE,
3630 gsvs_itemsize);
3631
3632 r600_store_context_reg_seq(cb, R_02892C_SQ_GSVS_RING_OFFSET_1, 3);
3633 r600_store_value(cb, gsvs_itemsize);
3634 r600_store_value(cb, gsvs_itemsize);
3635 r600_store_value(cb, gsvs_itemsize);
3636
3637 /* FIXME calculate these values somehow ??? */
3638 r600_store_context_reg_seq(cb, R_028A54_GS_PER_ES, 3);
3639 r600_store_value(cb, 0x80); /* GS_PER_ES */
3640 r600_store_value(cb, 0x100); /* ES_PER_GS */
3641 r600_store_value(cb, 0x2); /* GS_PER_VS */
3642
3643 r600_store_context_reg(cb, R_028878_SQ_PGM_RESOURCES_GS,
3644 S_028878_NUM_GPRS(rshader->bc.ngpr) |
3645 S_028878_STACK_SIZE(rshader->bc.nstack));
3646 r600_store_context_reg(cb, R_028874_SQ_PGM_START_GS,
3647 r600_resource_va(ctx->screen, (void *)shader->bo) >> 8);
3648 /* After that, the NOP relocation packet must be emitted (shader->bo, RADEON_USAGE_READ). */
3649 }
3650
3651
3652 void evergreen_update_vs_state(struct pipe_context *ctx, struct r600_pipe_shader *shader)
3653 {
3654 struct r600_command_buffer *cb = &shader->command_buffer;
3655 struct r600_shader *rshader = &shader->shader;
3656 unsigned spi_vs_out_id[10] = {};
3657 unsigned i, tmp, nparams = 0;
3658
3659 for (i = 0; i < rshader->noutput; i++) {
3660 if (rshader->output[i].spi_sid) {
3661 tmp = rshader->output[i].spi_sid << ((nparams & 3) * 8);
3662 spi_vs_out_id[nparams / 4] |= tmp;
3663 nparams++;
3664 }
3665 }
3666
3667 r600_init_command_buffer(cb, 32);
3668
3669 r600_store_context_reg_seq(cb, R_02861C_SPI_VS_OUT_ID_0, 10);
3670 for (i = 0; i < 10; i++) {
3671 r600_store_value(cb, spi_vs_out_id[i]);
3672 }
3673
3674 /* Certain attributes (position, psize, etc.) don't count as params.
3675 * VS is required to export at least one param and r600_shader_from_tgsi()
3676 * takes care of adding a dummy export.
3677 */
3678 if (nparams < 1)
3679 nparams = 1;
3680
3681 r600_store_context_reg(cb, R_0286C4_SPI_VS_OUT_CONFIG,
3682 S_0286C4_VS_EXPORT_COUNT(nparams - 1));
3683 r600_store_context_reg(cb, R_028860_SQ_PGM_RESOURCES_VS,
3684 S_028860_NUM_GPRS(rshader->bc.ngpr) |
3685 S_028860_STACK_SIZE(rshader->bc.nstack));
3686 r600_store_context_reg(cb, R_02885C_SQ_PGM_START_VS,
3687 r600_resource_va(ctx->screen, (void *)shader->bo) >> 8);
3688 /* After that, the NOP relocation packet must be emitted (shader->bo, RADEON_USAGE_READ). */
3689
3690 shader->pa_cl_vs_out_cntl =
3691 S_02881C_VS_OUT_CCDIST0_VEC_ENA((rshader->clip_dist_write & 0x0F) != 0) |
3692 S_02881C_VS_OUT_CCDIST1_VEC_ENA((rshader->clip_dist_write & 0xF0) != 0) |
3693 S_02881C_VS_OUT_MISC_VEC_ENA(rshader->vs_out_misc_write) |
3694 S_02881C_USE_VTX_POINT_SIZE(rshader->vs_out_point_size);
3695 }
3696
3697 void *evergreen_create_resolve_blend(struct r600_context *rctx)
3698 {
3699 struct pipe_blend_state blend;
3700
3701 memset(&blend, 0, sizeof(blend));
3702 blend.independent_blend_enable = true;
3703 blend.rt[0].colormask = 0xf;
3704 return evergreen_create_blend_state_mode(&rctx->b.b, &blend, V_028808_CB_RESOLVE);
3705 }
3706
3707 void *evergreen_create_decompress_blend(struct r600_context *rctx)
3708 {
3709 struct pipe_blend_state blend;
3710 unsigned mode = rctx->screen->has_compressed_msaa_texturing ?
3711 V_028808_CB_FMASK_DECOMPRESS : V_028808_CB_DECOMPRESS;
3712
3713 memset(&blend, 0, sizeof(blend));
3714 blend.independent_blend_enable = true;
3715 blend.rt[0].colormask = 0xf;
3716 return evergreen_create_blend_state_mode(&rctx->b.b, &blend, mode);
3717 }
3718
3719 void *evergreen_create_fastclear_blend(struct r600_context *rctx)
3720 {
3721 struct pipe_blend_state blend;
3722 unsigned mode = V_028808_CB_ELIMINATE_FAST_CLEAR;
3723
3724 memset(&blend, 0, sizeof(blend));
3725 blend.independent_blend_enable = true;
3726 blend.rt[0].colormask = 0xf;
3727 return evergreen_create_blend_state_mode(&rctx->b.b, &blend, mode);
3728 }
3729
3730 void *evergreen_create_db_flush_dsa(struct r600_context *rctx)
3731 {
3732 struct pipe_depth_stencil_alpha_state dsa = {{0}};
3733
3734 return rctx->b.b.create_depth_stencil_alpha_state(&rctx->b.b, &dsa);
3735 }
3736
3737 void evergreen_update_db_shader_control(struct r600_context * rctx)
3738 {
3739 bool dual_export;
3740 unsigned db_shader_control;
3741
3742 if (!rctx->ps_shader) {
3743 return;
3744 }
3745
3746 dual_export = rctx->framebuffer.export_16bpc &&
3747 !rctx->ps_shader->current->ps_depth_export;
3748
3749 db_shader_control = rctx->ps_shader->current->db_shader_control |
3750 S_02880C_DUAL_EXPORT_ENABLE(dual_export) |
3751 S_02880C_DB_SOURCE_FORMAT(dual_export ? V_02880C_EXPORT_DB_TWO :
3752 V_02880C_EXPORT_DB_FULL) |
3753 S_02880C_ALPHA_TO_MASK_DISABLE(rctx->framebuffer.cb0_is_integer);
3754
3755 /* When alpha test is enabled we can't trust the hw to make the proper
3756 * decision on the order in which ztest should be run related to fragment
3757 * shader execution.
3758 *
3759 * If alpha test is enabled perform early z rejection (RE_Z) but don't early
3760 * write to the zbuffer. Write to zbuffer is delayed after fragment shader
3761 * execution and thus after alpha test so if discarded by the alpha test
3762 * the z value is not written.
3763 * If ReZ is enabled, and the zfunc/zenable/zwrite values change you can
3764 * get a hang unless you flush the DB in between. For now just use
3765 * LATE_Z.
3766 */
3767 if (rctx->alphatest_state.sx_alpha_test_control) {
3768 db_shader_control |= S_02880C_Z_ORDER(V_02880C_LATE_Z);
3769 } else {
3770 db_shader_control |= S_02880C_Z_ORDER(V_02880C_EARLY_Z_THEN_LATE_Z);
3771 }
3772
3773 if (db_shader_control != rctx->db_misc_state.db_shader_control) {
3774 rctx->db_misc_state.db_shader_control = db_shader_control;
3775 rctx->db_misc_state.atom.dirty = true;
3776 }
3777 }
3778
3779 static void evergreen_dma_copy_tile(struct r600_context *rctx,
3780 struct pipe_resource *dst,
3781 unsigned dst_level,
3782 unsigned dst_x,
3783 unsigned dst_y,
3784 unsigned dst_z,
3785 struct pipe_resource *src,
3786 unsigned src_level,
3787 unsigned src_x,
3788 unsigned src_y,
3789 unsigned src_z,
3790 unsigned copy_height,
3791 unsigned pitch,
3792 unsigned bpp)
3793 {
3794 struct radeon_winsys_cs *cs = rctx->b.rings.dma.cs;
3795 struct r600_texture *rsrc = (struct r600_texture*)src;
3796 struct r600_texture *rdst = (struct r600_texture*)dst;
3797 unsigned array_mode, lbpp, pitch_tile_max, slice_tile_max, size;
3798 unsigned ncopy, height, cheight, detile, i, x, y, z, src_mode, dst_mode;
3799 unsigned sub_cmd, bank_h, bank_w, mt_aspect, nbanks, tile_split, non_disp_tiling = 0;
3800 uint64_t base, addr;
3801
3802 /* make sure that the dma ring is only one active */
3803 rctx->b.rings.gfx.flush(rctx, RADEON_FLUSH_ASYNC);
3804
3805 dst_mode = rdst->surface.level[dst_level].mode;
3806 src_mode = rsrc->surface.level[src_level].mode;
3807 /* downcast linear aligned to linear to simplify test */
3808 src_mode = src_mode == RADEON_SURF_MODE_LINEAR_ALIGNED ? RADEON_SURF_MODE_LINEAR : src_mode;
3809 dst_mode = dst_mode == RADEON_SURF_MODE_LINEAR_ALIGNED ? RADEON_SURF_MODE_LINEAR : dst_mode;
3810 assert(dst_mode != src_mode);
3811
3812 /* non_disp_tiling bit needs to be set for depth, stencil, and fmask surfaces */
3813 if (util_format_has_depth(util_format_description(src->format)))
3814 non_disp_tiling = 1;
3815
3816 y = 0;
3817 sub_cmd = 0x8;
3818 lbpp = util_logbase2(bpp);
3819 pitch_tile_max = ((pitch / bpp) >> 3) - 1;
3820 nbanks = eg_num_banks(rctx->screen->b.tiling_info.num_banks);
3821
3822 if (dst_mode == RADEON_SURF_MODE_LINEAR) {
3823 /* T2L */
3824 array_mode = evergreen_array_mode(src_mode);
3825 slice_tile_max = (rsrc->surface.level[src_level].nblk_x * rsrc->surface.level[src_level].nblk_y) >> 6;
3826 slice_tile_max = slice_tile_max ? slice_tile_max - 1 : 0;
3827 /* linear height must be the same as the slice tile max height, it's ok even
3828 * if the linear destination/source have smaller heigh as the size of the
3829 * dma packet will be using the copy_height which is always smaller or equal
3830 * to the linear height
3831 */
3832 height = rsrc->surface.level[src_level].npix_y;
3833 detile = 1;
3834 x = src_x;
3835 y = src_y;
3836 z = src_z;
3837 base = rsrc->surface.level[src_level].offset;
3838 addr = rdst->surface.level[dst_level].offset;
3839 addr += rdst->surface.level[dst_level].slice_size * dst_z;
3840 addr += dst_y * pitch + dst_x * bpp;
3841 bank_h = eg_bank_wh(rsrc->surface.bankh);
3842 bank_w = eg_bank_wh(rsrc->surface.bankw);
3843 mt_aspect = eg_macro_tile_aspect(rsrc->surface.mtilea);
3844 tile_split = eg_tile_split(rsrc->surface.tile_split);
3845 base += r600_resource_va(&rctx->screen->b.b, src);
3846 addr += r600_resource_va(&rctx->screen->b.b, dst);
3847 } else {
3848 /* L2T */
3849 array_mode = evergreen_array_mode(dst_mode);
3850 slice_tile_max = (rdst->surface.level[dst_level].nblk_x * rdst->surface.level[dst_level].nblk_y) >> 6;
3851 slice_tile_max = slice_tile_max ? slice_tile_max - 1 : 0;
3852 /* linear height must be the same as the slice tile max height, it's ok even
3853 * if the linear destination/source have smaller heigh as the size of the
3854 * dma packet will be using the copy_height which is always smaller or equal
3855 * to the linear height
3856 */
3857 height = rdst->surface.level[dst_level].npix_y;
3858 detile = 0;
3859 x = dst_x;
3860 y = dst_y;
3861 z = dst_z;
3862 base = rdst->surface.level[dst_level].offset;
3863 addr = rsrc->surface.level[src_level].offset;
3864 addr += rsrc->surface.level[src_level].slice_size * src_z;
3865 addr += src_y * pitch + src_x * bpp;
3866 bank_h = eg_bank_wh(rdst->surface.bankh);
3867 bank_w = eg_bank_wh(rdst->surface.bankw);
3868 mt_aspect = eg_macro_tile_aspect(rdst->surface.mtilea);
3869 tile_split = eg_tile_split(rdst->surface.tile_split);
3870 base += r600_resource_va(&rctx->screen->b.b, dst);
3871 addr += r600_resource_va(&rctx->screen->b.b, src);
3872 }
3873
3874 size = (copy_height * pitch) >> 2;
3875 ncopy = (size / 0x000fffff) + !!(size % 0x000fffff);
3876 r600_need_dma_space(rctx, ncopy * 9);
3877
3878 for (i = 0; i < ncopy; i++) {
3879 cheight = copy_height;
3880 if (((cheight * pitch) >> 2) > 0x000fffff) {
3881 cheight = (0x000fffff << 2) / pitch;
3882 }
3883 size = (cheight * pitch) >> 2;
3884 /* emit reloc before writting cs so that cs is always in consistent state */
3885 r600_context_bo_reloc(&rctx->b, &rctx->b.rings.dma, &rsrc->resource, RADEON_USAGE_READ);
3886 r600_context_bo_reloc(&rctx->b, &rctx->b.rings.dma, &rdst->resource, RADEON_USAGE_WRITE);
3887 cs->buf[cs->cdw++] = DMA_PACKET(DMA_PACKET_COPY, sub_cmd, size);
3888 cs->buf[cs->cdw++] = base >> 8;
3889 cs->buf[cs->cdw++] = (detile << 31) | (array_mode << 27) |
3890 (lbpp << 24) | (bank_h << 21) |
3891 (bank_w << 18) | (mt_aspect << 16);
3892 cs->buf[cs->cdw++] = (pitch_tile_max << 0) | ((height - 1) << 16);
3893 cs->buf[cs->cdw++] = (slice_tile_max << 0);
3894 cs->buf[cs->cdw++] = (x << 0) | (z << 18);
3895 cs->buf[cs->cdw++] = (y << 0) | (tile_split << 21) | (nbanks << 25) | (non_disp_tiling << 28);
3896 cs->buf[cs->cdw++] = addr & 0xfffffffc;
3897 cs->buf[cs->cdw++] = (addr >> 32UL) & 0xff;
3898 copy_height -= cheight;
3899 addr += cheight * pitch;
3900 y += cheight;
3901 }
3902 }
3903
3904 static boolean evergreen_dma_blit(struct pipe_context *ctx,
3905 struct pipe_resource *dst,
3906 unsigned dst_level,
3907 unsigned dst_x, unsigned dst_y, unsigned dst_z,
3908 struct pipe_resource *src,
3909 unsigned src_level,
3910 const struct pipe_box *src_box)
3911 {
3912 struct r600_context *rctx = (struct r600_context *)ctx;
3913 struct r600_texture *rsrc = (struct r600_texture*)src;
3914 struct r600_texture *rdst = (struct r600_texture*)dst;
3915 unsigned dst_pitch, src_pitch, bpp, dst_mode, src_mode, copy_height;
3916 unsigned src_w, dst_w;
3917 unsigned src_x, src_y;
3918
3919 if (rctx->b.rings.dma.cs == NULL) {
3920 return FALSE;
3921 }
3922
3923 if (dst->target == PIPE_BUFFER && src->target == PIPE_BUFFER) {
3924 evergreen_dma_copy(rctx, dst, src, dst_x, src_box->x, src_box->width);
3925 return TRUE;
3926 }
3927
3928 if (src->format != dst->format) {
3929 return FALSE;
3930 }
3931 if (rdst->dirty_level_mask != 0) {
3932 return FALSE;
3933 }
3934 if (rsrc->dirty_level_mask) {
3935 ctx->flush_resource(ctx, src);
3936 }
3937
3938 src_x = util_format_get_nblocksx(src->format, src_box->x);
3939 dst_x = util_format_get_nblocksx(src->format, dst_x);
3940 src_y = util_format_get_nblocksy(src->format, src_box->y);
3941 dst_y = util_format_get_nblocksy(src->format, dst_y);
3942
3943 bpp = rdst->surface.bpe;
3944 dst_pitch = rdst->surface.level[dst_level].pitch_bytes;
3945 src_pitch = rsrc->surface.level[src_level].pitch_bytes;
3946 src_w = rsrc->surface.level[src_level].npix_x;
3947 dst_w = rdst->surface.level[dst_level].npix_x;
3948 copy_height = src_box->height / rsrc->surface.blk_h;
3949
3950 dst_mode = rdst->surface.level[dst_level].mode;
3951 src_mode = rsrc->surface.level[src_level].mode;
3952 /* downcast linear aligned to linear to simplify test */
3953 src_mode = src_mode == RADEON_SURF_MODE_LINEAR_ALIGNED ? RADEON_SURF_MODE_LINEAR : src_mode;
3954 dst_mode = dst_mode == RADEON_SURF_MODE_LINEAR_ALIGNED ? RADEON_SURF_MODE_LINEAR : dst_mode;
3955
3956 if (src_pitch != dst_pitch || src_box->x || dst_x || src_w != dst_w) {
3957 /* FIXME evergreen can do partial blit */
3958 return FALSE;
3959 }
3960 /* the x test here are currently useless (because we don't support partial blit)
3961 * but keep them around so we don't forget about those
3962 */
3963 if ((src_pitch & 0x7) || (src_box->x & 0x7) || (dst_x & 0x7) || (src_box->y & 0x7) || (dst_y & 0x7)) {
3964 return FALSE;
3965 }
3966
3967 /* 128 bpp surfaces require non_disp_tiling for both
3968 * tiled and linear buffers on cayman. However, async
3969 * DMA only supports it on the tiled side. As such
3970 * the tile order is backwards after a L2T/T2L packet.
3971 */
3972 if ((rctx->b.chip_class == CAYMAN) &&
3973 (src_mode != dst_mode) &&
3974 (util_format_get_blocksize(src->format) >= 16)) {
3975 return FALSE;
3976 }
3977
3978 if (src_mode == dst_mode) {
3979 uint64_t dst_offset, src_offset;
3980 /* simple dma blit would do NOTE code here assume :
3981 * src_box.x/y == 0
3982 * dst_x/y == 0
3983 * dst_pitch == src_pitch
3984 */
3985 src_offset= rsrc->surface.level[src_level].offset;
3986 src_offset += rsrc->surface.level[src_level].slice_size * src_box->z;
3987 src_offset += src_y * src_pitch + src_x * bpp;
3988 dst_offset = rdst->surface.level[dst_level].offset;
3989 dst_offset += rdst->surface.level[dst_level].slice_size * dst_z;
3990 dst_offset += dst_y * dst_pitch + dst_x * bpp;
3991 evergreen_dma_copy(rctx, dst, src, dst_offset, src_offset,
3992 src_box->height * src_pitch);
3993 } else {
3994 evergreen_dma_copy_tile(rctx, dst, dst_level, dst_x, dst_y, dst_z,
3995 src, src_level, src_x, src_y, src_box->z,
3996 copy_height, dst_pitch, bpp);
3997 }
3998 return TRUE;
3999 }
4000
4001 void evergreen_init_state_functions(struct r600_context *rctx)
4002 {
4003 unsigned id = 4;
4004
4005 /* !!!
4006 * To avoid GPU lockup registers must be emited in a specific order
4007 * (no kidding ...). The order below is important and have been
4008 * partialy infered from analyzing fglrx command stream.
4009 *
4010 * Don't reorder atom without carefully checking the effect (GPU lockup
4011 * or piglit regression).
4012 * !!!
4013 */
4014
4015 r600_init_atom(rctx, &rctx->framebuffer.atom, id++, evergreen_emit_framebuffer_state, 0);
4016 /* shader const */
4017 r600_init_atom(rctx, &rctx->constbuf_state[PIPE_SHADER_VERTEX].atom, id++, evergreen_emit_vs_constant_buffers, 0);
4018 r600_init_atom(rctx, &rctx->constbuf_state[PIPE_SHADER_GEOMETRY].atom, id++, evergreen_emit_gs_constant_buffers, 0);
4019 r600_init_atom(rctx, &rctx->constbuf_state[PIPE_SHADER_FRAGMENT].atom, id++, evergreen_emit_ps_constant_buffers, 0);
4020 r600_init_atom(rctx, &rctx->constbuf_state[PIPE_SHADER_COMPUTE].atom, id++, evergreen_emit_cs_constant_buffers, 0);
4021 /* shader program */
4022 r600_init_atom(rctx, &rctx->cs_shader_state.atom, id++, evergreen_emit_cs_shader, 0);
4023 /* sampler */
4024 r600_init_atom(rctx, &rctx->samplers[PIPE_SHADER_VERTEX].states.atom, id++, evergreen_emit_vs_sampler_states, 0);
4025 r600_init_atom(rctx, &rctx->samplers[PIPE_SHADER_GEOMETRY].states.atom, id++, evergreen_emit_gs_sampler_states, 0);
4026 r600_init_atom(rctx, &rctx->samplers[PIPE_SHADER_FRAGMENT].states.atom, id++, evergreen_emit_ps_sampler_states, 0);
4027 /* resources */
4028 r600_init_atom(rctx, &rctx->vertex_buffer_state.atom, id++, evergreen_fs_emit_vertex_buffers, 0);
4029 r600_init_atom(rctx, &rctx->cs_vertex_buffer_state.atom, id++, evergreen_cs_emit_vertex_buffers, 0);
4030 r600_init_atom(rctx, &rctx->samplers[PIPE_SHADER_VERTEX].views.atom, id++, evergreen_emit_vs_sampler_views, 0);
4031 r600_init_atom(rctx, &rctx->samplers[PIPE_SHADER_GEOMETRY].views.atom, id++, evergreen_emit_gs_sampler_views, 0);
4032 r600_init_atom(rctx, &rctx->samplers[PIPE_SHADER_FRAGMENT].views.atom, id++, evergreen_emit_ps_sampler_views, 0);
4033
4034 r600_init_atom(rctx, &rctx->vgt_state.atom, id++, r600_emit_vgt_state, 7);
4035
4036 if (rctx->b.chip_class == EVERGREEN) {
4037 r600_init_atom(rctx, &rctx->sample_mask.atom, id++, evergreen_emit_sample_mask, 3);
4038 } else {
4039 r600_init_atom(rctx, &rctx->sample_mask.atom, id++, cayman_emit_sample_mask, 4);
4040 }
4041 rctx->sample_mask.sample_mask = ~0;
4042
4043 r600_init_atom(rctx, &rctx->alphatest_state.atom, id++, r600_emit_alphatest_state, 6);
4044 r600_init_atom(rctx, &rctx->blend_color.atom, id++, r600_emit_blend_color, 6);
4045 r600_init_atom(rctx, &rctx->blend_state.atom, id++, r600_emit_cso_state, 0);
4046 r600_init_atom(rctx, &rctx->cb_misc_state.atom, id++, evergreen_emit_cb_misc_state, 4);
4047 r600_init_atom(rctx, &rctx->clip_misc_state.atom, id++, r600_emit_clip_misc_state, 6);
4048 r600_init_atom(rctx, &rctx->clip_state.atom, id++, evergreen_emit_clip_state, 26);
4049 r600_init_atom(rctx, &rctx->db_misc_state.atom, id++, evergreen_emit_db_misc_state, 10);
4050 r600_init_atom(rctx, &rctx->db_state.atom, id++, evergreen_emit_db_state, 14);
4051 r600_init_atom(rctx, &rctx->dsa_state.atom, id++, r600_emit_cso_state, 0);
4052 r600_init_atom(rctx, &rctx->poly_offset_state.atom, id++, evergreen_emit_polygon_offset, 6);
4053 r600_init_atom(rctx, &rctx->rasterizer_state.atom, id++, r600_emit_cso_state, 0);
4054 r600_init_atom(rctx, &rctx->scissor.atom, id++, evergreen_emit_scissor_state, 4);
4055 r600_init_atom(rctx, &rctx->stencil_ref.atom, id++, r600_emit_stencil_ref, 4);
4056 r600_init_atom(rctx, &rctx->viewport.atom, id++, r600_emit_viewport_state, 8);
4057 r600_init_atom(rctx, &rctx->vertex_fetch_shader.atom, id++, evergreen_emit_vertex_fetch_shader, 5);
4058 rctx->atoms[id++] = &rctx->b.streamout.begin_atom;
4059 r600_init_atom(rctx, &rctx->vertex_shader.atom, id++, r600_emit_shader, 23);
4060 r600_init_atom(rctx, &rctx->pixel_shader.atom, id++, r600_emit_shader, 0);
4061 r600_init_atom(rctx, &rctx->geometry_shader.atom, id++, r600_emit_shader, 0);
4062 r600_init_atom(rctx, &rctx->export_shader.atom, id++, r600_emit_shader, 0);
4063 r600_init_atom(rctx, &rctx->shader_stages.atom, id++, evergreen_emit_shader_stages, 6);
4064 r600_init_atom(rctx, &rctx->gs_rings.atom, id++, evergreen_emit_gs_rings, 26);
4065
4066 rctx->b.b.create_blend_state = evergreen_create_blend_state;
4067 rctx->b.b.create_depth_stencil_alpha_state = evergreen_create_dsa_state;
4068 rctx->b.b.create_rasterizer_state = evergreen_create_rs_state;
4069 rctx->b.b.create_sampler_state = evergreen_create_sampler_state;
4070 rctx->b.b.create_sampler_view = evergreen_create_sampler_view;
4071 rctx->b.b.set_framebuffer_state = evergreen_set_framebuffer_state;
4072 rctx->b.b.set_polygon_stipple = evergreen_set_polygon_stipple;
4073 rctx->b.b.set_scissor_states = evergreen_set_scissor_states;
4074
4075 if (rctx->b.chip_class == EVERGREEN)
4076 rctx->b.b.get_sample_position = evergreen_get_sample_position;
4077 else
4078 rctx->b.b.get_sample_position = cayman_get_sample_position;
4079 rctx->b.dma_copy = evergreen_dma_blit;
4080
4081 evergreen_init_compute_state_functions(rctx);
4082 }