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[mesa.git] / src / gallium / drivers / r600 / evergreen_state.c
1 /*
2 * Copyright 2010 Jerome Glisse <glisse@freedesktop.org>
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * on the rights to use, copy, modify, merge, publish, distribute, sub
8 * license, and/or sell copies of the Software, and to permit persons to whom
9 * the Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
13 * Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHOR(S) AND/OR THEIR SUPPLIERS BE LIABLE FOR ANY CLAIM,
19 * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
20 * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
21 * USE OR OTHER DEALINGS IN THE SOFTWARE.
22 */
23 #include "r600_formats.h"
24 #include "r600_shader.h"
25 #include "r600_query.h"
26 #include "evergreend.h"
27
28 #include "pipe/p_shader_tokens.h"
29 #include "util/u_pack_color.h"
30 #include "util/u_memory.h"
31 #include "util/u_framebuffer.h"
32 #include "util/u_dual_blend.h"
33 #include "evergreen_compute.h"
34 #include "util/u_math.h"
35
36 static inline unsigned evergreen_array_mode(unsigned mode)
37 {
38 switch (mode) {
39 default:
40 case RADEON_SURF_MODE_LINEAR_ALIGNED: return V_028C70_ARRAY_LINEAR_ALIGNED;
41 break;
42 case RADEON_SURF_MODE_1D: return V_028C70_ARRAY_1D_TILED_THIN1;
43 break;
44 case RADEON_SURF_MODE_2D: return V_028C70_ARRAY_2D_TILED_THIN1;
45 }
46 }
47
48 static uint32_t eg_num_banks(uint32_t nbanks)
49 {
50 switch (nbanks) {
51 case 2:
52 return 0;
53 case 4:
54 return 1;
55 case 8:
56 default:
57 return 2;
58 case 16:
59 return 3;
60 }
61 }
62
63
64 static unsigned eg_tile_split(unsigned tile_split)
65 {
66 switch (tile_split) {
67 case 64: tile_split = 0; break;
68 case 128: tile_split = 1; break;
69 case 256: tile_split = 2; break;
70 case 512: tile_split = 3; break;
71 default:
72 case 1024: tile_split = 4; break;
73 case 2048: tile_split = 5; break;
74 case 4096: tile_split = 6; break;
75 }
76 return tile_split;
77 }
78
79 static unsigned eg_macro_tile_aspect(unsigned macro_tile_aspect)
80 {
81 switch (macro_tile_aspect) {
82 default:
83 case 1: macro_tile_aspect = 0; break;
84 case 2: macro_tile_aspect = 1; break;
85 case 4: macro_tile_aspect = 2; break;
86 case 8: macro_tile_aspect = 3; break;
87 }
88 return macro_tile_aspect;
89 }
90
91 static unsigned eg_bank_wh(unsigned bankwh)
92 {
93 switch (bankwh) {
94 default:
95 case 1: bankwh = 0; break;
96 case 2: bankwh = 1; break;
97 case 4: bankwh = 2; break;
98 case 8: bankwh = 3; break;
99 }
100 return bankwh;
101 }
102
103 static uint32_t r600_translate_blend_function(int blend_func)
104 {
105 switch (blend_func) {
106 case PIPE_BLEND_ADD:
107 return V_028780_COMB_DST_PLUS_SRC;
108 case PIPE_BLEND_SUBTRACT:
109 return V_028780_COMB_SRC_MINUS_DST;
110 case PIPE_BLEND_REVERSE_SUBTRACT:
111 return V_028780_COMB_DST_MINUS_SRC;
112 case PIPE_BLEND_MIN:
113 return V_028780_COMB_MIN_DST_SRC;
114 case PIPE_BLEND_MAX:
115 return V_028780_COMB_MAX_DST_SRC;
116 default:
117 R600_ERR("Unknown blend function %d\n", blend_func);
118 assert(0);
119 break;
120 }
121 return 0;
122 }
123
124 static uint32_t r600_translate_blend_factor(int blend_fact)
125 {
126 switch (blend_fact) {
127 case PIPE_BLENDFACTOR_ONE:
128 return V_028780_BLEND_ONE;
129 case PIPE_BLENDFACTOR_SRC_COLOR:
130 return V_028780_BLEND_SRC_COLOR;
131 case PIPE_BLENDFACTOR_SRC_ALPHA:
132 return V_028780_BLEND_SRC_ALPHA;
133 case PIPE_BLENDFACTOR_DST_ALPHA:
134 return V_028780_BLEND_DST_ALPHA;
135 case PIPE_BLENDFACTOR_DST_COLOR:
136 return V_028780_BLEND_DST_COLOR;
137 case PIPE_BLENDFACTOR_SRC_ALPHA_SATURATE:
138 return V_028780_BLEND_SRC_ALPHA_SATURATE;
139 case PIPE_BLENDFACTOR_CONST_COLOR:
140 return V_028780_BLEND_CONST_COLOR;
141 case PIPE_BLENDFACTOR_CONST_ALPHA:
142 return V_028780_BLEND_CONST_ALPHA;
143 case PIPE_BLENDFACTOR_ZERO:
144 return V_028780_BLEND_ZERO;
145 case PIPE_BLENDFACTOR_INV_SRC_COLOR:
146 return V_028780_BLEND_ONE_MINUS_SRC_COLOR;
147 case PIPE_BLENDFACTOR_INV_SRC_ALPHA:
148 return V_028780_BLEND_ONE_MINUS_SRC_ALPHA;
149 case PIPE_BLENDFACTOR_INV_DST_ALPHA:
150 return V_028780_BLEND_ONE_MINUS_DST_ALPHA;
151 case PIPE_BLENDFACTOR_INV_DST_COLOR:
152 return V_028780_BLEND_ONE_MINUS_DST_COLOR;
153 case PIPE_BLENDFACTOR_INV_CONST_COLOR:
154 return V_028780_BLEND_ONE_MINUS_CONST_COLOR;
155 case PIPE_BLENDFACTOR_INV_CONST_ALPHA:
156 return V_028780_BLEND_ONE_MINUS_CONST_ALPHA;
157 case PIPE_BLENDFACTOR_SRC1_COLOR:
158 return V_028780_BLEND_SRC1_COLOR;
159 case PIPE_BLENDFACTOR_SRC1_ALPHA:
160 return V_028780_BLEND_SRC1_ALPHA;
161 case PIPE_BLENDFACTOR_INV_SRC1_COLOR:
162 return V_028780_BLEND_INV_SRC1_COLOR;
163 case PIPE_BLENDFACTOR_INV_SRC1_ALPHA:
164 return V_028780_BLEND_INV_SRC1_ALPHA;
165 default:
166 R600_ERR("Bad blend factor %d not supported!\n", blend_fact);
167 assert(0);
168 break;
169 }
170 return 0;
171 }
172
173 static unsigned r600_tex_dim(struct r600_texture *rtex,
174 unsigned view_target, unsigned nr_samples)
175 {
176 unsigned res_target = rtex->resource.b.b.target;
177
178 if (view_target == PIPE_TEXTURE_CUBE ||
179 view_target == PIPE_TEXTURE_CUBE_ARRAY)
180 res_target = view_target;
181 /* If interpreting cubemaps as something else, set 2D_ARRAY. */
182 else if (res_target == PIPE_TEXTURE_CUBE ||
183 res_target == PIPE_TEXTURE_CUBE_ARRAY)
184 res_target = PIPE_TEXTURE_2D_ARRAY;
185
186 switch (res_target) {
187 default:
188 case PIPE_TEXTURE_1D:
189 return V_030000_SQ_TEX_DIM_1D;
190 case PIPE_TEXTURE_1D_ARRAY:
191 return V_030000_SQ_TEX_DIM_1D_ARRAY;
192 case PIPE_TEXTURE_2D:
193 case PIPE_TEXTURE_RECT:
194 return nr_samples > 1 ? V_030000_SQ_TEX_DIM_2D_MSAA :
195 V_030000_SQ_TEX_DIM_2D;
196 case PIPE_TEXTURE_2D_ARRAY:
197 return nr_samples > 1 ? V_030000_SQ_TEX_DIM_2D_ARRAY_MSAA :
198 V_030000_SQ_TEX_DIM_2D_ARRAY;
199 case PIPE_TEXTURE_3D:
200 return V_030000_SQ_TEX_DIM_3D;
201 case PIPE_TEXTURE_CUBE:
202 case PIPE_TEXTURE_CUBE_ARRAY:
203 return V_030000_SQ_TEX_DIM_CUBEMAP;
204 }
205 }
206
207 static uint32_t r600_translate_dbformat(enum pipe_format format)
208 {
209 switch (format) {
210 case PIPE_FORMAT_Z16_UNORM:
211 return V_028040_Z_16;
212 case PIPE_FORMAT_Z24X8_UNORM:
213 case PIPE_FORMAT_Z24_UNORM_S8_UINT:
214 case PIPE_FORMAT_X8Z24_UNORM:
215 case PIPE_FORMAT_S8_UINT_Z24_UNORM:
216 return V_028040_Z_24;
217 case PIPE_FORMAT_Z32_FLOAT:
218 case PIPE_FORMAT_Z32_FLOAT_S8X24_UINT:
219 return V_028040_Z_32_FLOAT;
220 default:
221 return ~0U;
222 }
223 }
224
225 static bool r600_is_sampler_format_supported(struct pipe_screen *screen, enum pipe_format format)
226 {
227 return r600_translate_texformat(screen, format, NULL, NULL, NULL,
228 FALSE) != ~0U;
229 }
230
231 static bool r600_is_colorbuffer_format_supported(enum chip_class chip, enum pipe_format format)
232 {
233 return r600_translate_colorformat(chip, format, FALSE) != ~0U &&
234 r600_translate_colorswap(format, FALSE) != ~0U;
235 }
236
237 static bool r600_is_zs_format_supported(enum pipe_format format)
238 {
239 return r600_translate_dbformat(format) != ~0U;
240 }
241
242 boolean evergreen_is_format_supported(struct pipe_screen *screen,
243 enum pipe_format format,
244 enum pipe_texture_target target,
245 unsigned sample_count,
246 unsigned usage)
247 {
248 struct r600_screen *rscreen = (struct r600_screen*)screen;
249 unsigned retval = 0;
250
251 if (target >= PIPE_MAX_TEXTURE_TYPES) {
252 R600_ERR("r600: unsupported texture type %d\n", target);
253 return FALSE;
254 }
255
256 if (!util_format_is_supported(format, usage))
257 return FALSE;
258
259 if (sample_count > 1) {
260 if (!rscreen->has_msaa)
261 return FALSE;
262
263 switch (sample_count) {
264 case 2:
265 case 4:
266 case 8:
267 break;
268 default:
269 return FALSE;
270 }
271 }
272
273 if (usage & PIPE_BIND_SAMPLER_VIEW) {
274 if (target == PIPE_BUFFER) {
275 if (r600_is_vertex_format_supported(format))
276 retval |= PIPE_BIND_SAMPLER_VIEW;
277 } else {
278 if (r600_is_sampler_format_supported(screen, format))
279 retval |= PIPE_BIND_SAMPLER_VIEW;
280 }
281 }
282
283 if ((usage & (PIPE_BIND_RENDER_TARGET |
284 PIPE_BIND_DISPLAY_TARGET |
285 PIPE_BIND_SCANOUT |
286 PIPE_BIND_SHARED |
287 PIPE_BIND_BLENDABLE)) &&
288 r600_is_colorbuffer_format_supported(rscreen->b.chip_class, format)) {
289 retval |= usage &
290 (PIPE_BIND_RENDER_TARGET |
291 PIPE_BIND_DISPLAY_TARGET |
292 PIPE_BIND_SCANOUT |
293 PIPE_BIND_SHARED);
294 if (!util_format_is_pure_integer(format) &&
295 !util_format_is_depth_or_stencil(format))
296 retval |= usage & PIPE_BIND_BLENDABLE;
297 }
298
299 if ((usage & PIPE_BIND_DEPTH_STENCIL) &&
300 r600_is_zs_format_supported(format)) {
301 retval |= PIPE_BIND_DEPTH_STENCIL;
302 }
303
304 if ((usage & PIPE_BIND_VERTEX_BUFFER) &&
305 r600_is_vertex_format_supported(format)) {
306 retval |= PIPE_BIND_VERTEX_BUFFER;
307 }
308
309 if ((usage & PIPE_BIND_LINEAR) &&
310 !util_format_is_compressed(format) &&
311 !(usage & PIPE_BIND_DEPTH_STENCIL))
312 retval |= PIPE_BIND_LINEAR;
313
314 return retval == usage;
315 }
316
317 static void *evergreen_create_blend_state_mode(struct pipe_context *ctx,
318 const struct pipe_blend_state *state, int mode)
319 {
320 uint32_t color_control = 0, target_mask = 0;
321 struct r600_blend_state *blend = CALLOC_STRUCT(r600_blend_state);
322
323 if (!blend) {
324 return NULL;
325 }
326
327 r600_init_command_buffer(&blend->buffer, 20);
328 r600_init_command_buffer(&blend->buffer_no_blend, 20);
329
330 if (state->logicop_enable) {
331 color_control |= (state->logicop_func << 16) | (state->logicop_func << 20);
332 } else {
333 color_control |= (0xcc << 16);
334 }
335 /* we pretend 8 buffer are used, CB_SHADER_MASK will disable unused one */
336 if (state->independent_blend_enable) {
337 for (int i = 0; i < 8; i++) {
338 target_mask |= (state->rt[i].colormask << (4 * i));
339 }
340 } else {
341 for (int i = 0; i < 8; i++) {
342 target_mask |= (state->rt[0].colormask << (4 * i));
343 }
344 }
345
346 /* only have dual source on MRT0 */
347 blend->dual_src_blend = util_blend_state_is_dual(state, 0);
348 blend->cb_target_mask = target_mask;
349 blend->alpha_to_one = state->alpha_to_one;
350
351 if (target_mask)
352 color_control |= S_028808_MODE(mode);
353 else
354 color_control |= S_028808_MODE(V_028808_CB_DISABLE);
355
356
357 r600_store_context_reg(&blend->buffer, R_028808_CB_COLOR_CONTROL, color_control);
358 r600_store_context_reg(&blend->buffer, R_028B70_DB_ALPHA_TO_MASK,
359 S_028B70_ALPHA_TO_MASK_ENABLE(state->alpha_to_coverage) |
360 S_028B70_ALPHA_TO_MASK_OFFSET0(2) |
361 S_028B70_ALPHA_TO_MASK_OFFSET1(2) |
362 S_028B70_ALPHA_TO_MASK_OFFSET2(2) |
363 S_028B70_ALPHA_TO_MASK_OFFSET3(2));
364 r600_store_context_reg_seq(&blend->buffer, R_028780_CB_BLEND0_CONTROL, 8);
365
366 /* Copy over the dwords set so far into buffer_no_blend.
367 * Only the CB_BLENDi_CONTROL registers must be set after this. */
368 memcpy(blend->buffer_no_blend.buf, blend->buffer.buf, blend->buffer.num_dw * 4);
369 blend->buffer_no_blend.num_dw = blend->buffer.num_dw;
370
371 for (int i = 0; i < 8; i++) {
372 /* state->rt entries > 0 only written if independent blending */
373 const int j = state->independent_blend_enable ? i : 0;
374
375 unsigned eqRGB = state->rt[j].rgb_func;
376 unsigned srcRGB = state->rt[j].rgb_src_factor;
377 unsigned dstRGB = state->rt[j].rgb_dst_factor;
378 unsigned eqA = state->rt[j].alpha_func;
379 unsigned srcA = state->rt[j].alpha_src_factor;
380 unsigned dstA = state->rt[j].alpha_dst_factor;
381 uint32_t bc = 0;
382
383 r600_store_value(&blend->buffer_no_blend, 0);
384
385 if (!state->rt[j].blend_enable) {
386 r600_store_value(&blend->buffer, 0);
387 continue;
388 }
389
390 bc |= S_028780_BLEND_CONTROL_ENABLE(1);
391 bc |= S_028780_COLOR_COMB_FCN(r600_translate_blend_function(eqRGB));
392 bc |= S_028780_COLOR_SRCBLEND(r600_translate_blend_factor(srcRGB));
393 bc |= S_028780_COLOR_DESTBLEND(r600_translate_blend_factor(dstRGB));
394
395 if (srcA != srcRGB || dstA != dstRGB || eqA != eqRGB) {
396 bc |= S_028780_SEPARATE_ALPHA_BLEND(1);
397 bc |= S_028780_ALPHA_COMB_FCN(r600_translate_blend_function(eqA));
398 bc |= S_028780_ALPHA_SRCBLEND(r600_translate_blend_factor(srcA));
399 bc |= S_028780_ALPHA_DESTBLEND(r600_translate_blend_factor(dstA));
400 }
401 r600_store_value(&blend->buffer, bc);
402 }
403 return blend;
404 }
405
406 static void *evergreen_create_blend_state(struct pipe_context *ctx,
407 const struct pipe_blend_state *state)
408 {
409
410 return evergreen_create_blend_state_mode(ctx, state, V_028808_CB_NORMAL);
411 }
412
413 static void *evergreen_create_dsa_state(struct pipe_context *ctx,
414 const struct pipe_depth_stencil_alpha_state *state)
415 {
416 unsigned db_depth_control, alpha_test_control, alpha_ref;
417 struct r600_dsa_state *dsa = CALLOC_STRUCT(r600_dsa_state);
418
419 if (!dsa) {
420 return NULL;
421 }
422
423 r600_init_command_buffer(&dsa->buffer, 3);
424
425 dsa->valuemask[0] = state->stencil[0].valuemask;
426 dsa->valuemask[1] = state->stencil[1].valuemask;
427 dsa->writemask[0] = state->stencil[0].writemask;
428 dsa->writemask[1] = state->stencil[1].writemask;
429 dsa->zwritemask = state->depth.writemask;
430
431 db_depth_control = S_028800_Z_ENABLE(state->depth.enabled) |
432 S_028800_Z_WRITE_ENABLE(state->depth.writemask) |
433 S_028800_ZFUNC(state->depth.func);
434
435 /* stencil */
436 if (state->stencil[0].enabled) {
437 db_depth_control |= S_028800_STENCIL_ENABLE(1);
438 db_depth_control |= S_028800_STENCILFUNC(state->stencil[0].func); /* translates straight */
439 db_depth_control |= S_028800_STENCILFAIL(r600_translate_stencil_op(state->stencil[0].fail_op));
440 db_depth_control |= S_028800_STENCILZPASS(r600_translate_stencil_op(state->stencil[0].zpass_op));
441 db_depth_control |= S_028800_STENCILZFAIL(r600_translate_stencil_op(state->stencil[0].zfail_op));
442
443 if (state->stencil[1].enabled) {
444 db_depth_control |= S_028800_BACKFACE_ENABLE(1);
445 db_depth_control |= S_028800_STENCILFUNC_BF(state->stencil[1].func); /* translates straight */
446 db_depth_control |= S_028800_STENCILFAIL_BF(r600_translate_stencil_op(state->stencil[1].fail_op));
447 db_depth_control |= S_028800_STENCILZPASS_BF(r600_translate_stencil_op(state->stencil[1].zpass_op));
448 db_depth_control |= S_028800_STENCILZFAIL_BF(r600_translate_stencil_op(state->stencil[1].zfail_op));
449 }
450 }
451
452 /* alpha */
453 alpha_test_control = 0;
454 alpha_ref = 0;
455 if (state->alpha.enabled) {
456 alpha_test_control = S_028410_ALPHA_FUNC(state->alpha.func);
457 alpha_test_control |= S_028410_ALPHA_TEST_ENABLE(1);
458 alpha_ref = fui(state->alpha.ref_value);
459 }
460 dsa->sx_alpha_test_control = alpha_test_control & 0xff;
461 dsa->alpha_ref = alpha_ref;
462
463 /* misc */
464 r600_store_context_reg(&dsa->buffer, R_028800_DB_DEPTH_CONTROL, db_depth_control);
465 return dsa;
466 }
467
468 static void *evergreen_create_rs_state(struct pipe_context *ctx,
469 const struct pipe_rasterizer_state *state)
470 {
471 struct r600_context *rctx = (struct r600_context *)ctx;
472 unsigned tmp, spi_interp;
473 float psize_min, psize_max;
474 struct r600_rasterizer_state *rs = CALLOC_STRUCT(r600_rasterizer_state);
475
476 if (!rs) {
477 return NULL;
478 }
479
480 r600_init_command_buffer(&rs->buffer, 30);
481
482 rs->scissor_enable = state->scissor;
483 rs->clip_halfz = state->clip_halfz;
484 rs->flatshade = state->flatshade;
485 rs->sprite_coord_enable = state->sprite_coord_enable;
486 rs->rasterizer_discard = state->rasterizer_discard;
487 rs->two_side = state->light_twoside;
488 rs->clip_plane_enable = state->clip_plane_enable;
489 rs->pa_sc_line_stipple = state->line_stipple_enable ?
490 S_028A0C_LINE_PATTERN(state->line_stipple_pattern) |
491 S_028A0C_REPEAT_COUNT(state->line_stipple_factor) : 0;
492 rs->pa_cl_clip_cntl =
493 S_028810_DX_CLIP_SPACE_DEF(state->clip_halfz) |
494 S_028810_ZCLIP_NEAR_DISABLE(!state->depth_clip) |
495 S_028810_ZCLIP_FAR_DISABLE(!state->depth_clip) |
496 S_028810_DX_LINEAR_ATTR_CLIP_ENA(1) |
497 S_028810_DX_RASTERIZATION_KILL(state->rasterizer_discard);
498 rs->multisample_enable = state->multisample;
499
500 /* offset */
501 rs->offset_units = state->offset_units;
502 rs->offset_scale = state->offset_scale * 16.0f;
503 rs->offset_enable = state->offset_point || state->offset_line || state->offset_tri;
504 rs->offset_units_unscaled = state->offset_units_unscaled;
505
506 if (state->point_size_per_vertex) {
507 psize_min = util_get_min_point_size(state);
508 psize_max = 8192;
509 } else {
510 /* Force the point size to be as if the vertex output was disabled. */
511 psize_min = state->point_size;
512 psize_max = state->point_size;
513 }
514
515 spi_interp = S_0286D4_FLAT_SHADE_ENA(1);
516 if (state->sprite_coord_enable) {
517 spi_interp |= S_0286D4_PNT_SPRITE_ENA(1) |
518 S_0286D4_PNT_SPRITE_OVRD_X(2) |
519 S_0286D4_PNT_SPRITE_OVRD_Y(3) |
520 S_0286D4_PNT_SPRITE_OVRD_Z(0) |
521 S_0286D4_PNT_SPRITE_OVRD_W(1);
522 if (state->sprite_coord_mode != PIPE_SPRITE_COORD_UPPER_LEFT) {
523 spi_interp |= S_0286D4_PNT_SPRITE_TOP_1(1);
524 }
525 }
526
527 r600_store_context_reg_seq(&rs->buffer, R_028A00_PA_SU_POINT_SIZE, 3);
528 /* point size 12.4 fixed point (divide by two, because 0.5 = 1 pixel) */
529 tmp = r600_pack_float_12p4(state->point_size/2);
530 r600_store_value(&rs->buffer, /* R_028A00_PA_SU_POINT_SIZE */
531 S_028A00_HEIGHT(tmp) | S_028A00_WIDTH(tmp));
532 r600_store_value(&rs->buffer, /* R_028A04_PA_SU_POINT_MINMAX */
533 S_028A04_MIN_SIZE(r600_pack_float_12p4(psize_min/2)) |
534 S_028A04_MAX_SIZE(r600_pack_float_12p4(psize_max/2)));
535 r600_store_value(&rs->buffer, /* R_028A08_PA_SU_LINE_CNTL */
536 S_028A08_WIDTH((unsigned)(state->line_width * 8)));
537
538 r600_store_context_reg(&rs->buffer, R_0286D4_SPI_INTERP_CONTROL_0, spi_interp);
539 r600_store_context_reg(&rs->buffer, R_028A48_PA_SC_MODE_CNTL_0,
540 S_028A48_MSAA_ENABLE(state->multisample) |
541 S_028A48_VPORT_SCISSOR_ENABLE(1) |
542 S_028A48_LINE_STIPPLE_ENABLE(state->line_stipple_enable));
543
544 if (rctx->b.chip_class == CAYMAN) {
545 r600_store_context_reg(&rs->buffer, CM_R_028BE4_PA_SU_VTX_CNTL,
546 S_028C08_PIX_CENTER_HALF(state->half_pixel_center) |
547 S_028C08_QUANT_MODE(V_028C08_X_1_256TH));
548 } else {
549 r600_store_context_reg(&rs->buffer, R_028C08_PA_SU_VTX_CNTL,
550 S_028C08_PIX_CENTER_HALF(state->half_pixel_center) |
551 S_028C08_QUANT_MODE(V_028C08_X_1_256TH));
552 }
553
554 r600_store_context_reg(&rs->buffer, R_028B7C_PA_SU_POLY_OFFSET_CLAMP, fui(state->offset_clamp));
555 r600_store_context_reg(&rs->buffer, R_028814_PA_SU_SC_MODE_CNTL,
556 S_028814_PROVOKING_VTX_LAST(!state->flatshade_first) |
557 S_028814_CULL_FRONT((state->cull_face & PIPE_FACE_FRONT) ? 1 : 0) |
558 S_028814_CULL_BACK((state->cull_face & PIPE_FACE_BACK) ? 1 : 0) |
559 S_028814_FACE(!state->front_ccw) |
560 S_028814_POLY_OFFSET_FRONT_ENABLE(util_get_offset(state, state->fill_front)) |
561 S_028814_POLY_OFFSET_BACK_ENABLE(util_get_offset(state, state->fill_back)) |
562 S_028814_POLY_OFFSET_PARA_ENABLE(state->offset_point || state->offset_line) |
563 S_028814_POLY_MODE(state->fill_front != PIPE_POLYGON_MODE_FILL ||
564 state->fill_back != PIPE_POLYGON_MODE_FILL) |
565 S_028814_POLYMODE_FRONT_PTYPE(r600_translate_fill(state->fill_front)) |
566 S_028814_POLYMODE_BACK_PTYPE(r600_translate_fill(state->fill_back)));
567 return rs;
568 }
569
570 static void *evergreen_create_sampler_state(struct pipe_context *ctx,
571 const struct pipe_sampler_state *state)
572 {
573 struct r600_common_screen *rscreen = (struct r600_common_screen*)ctx->screen;
574 struct r600_pipe_sampler_state *ss = CALLOC_STRUCT(r600_pipe_sampler_state);
575 unsigned max_aniso = rscreen->force_aniso >= 0 ? rscreen->force_aniso
576 : state->max_anisotropy;
577 unsigned max_aniso_ratio = r600_tex_aniso_filter(max_aniso);
578
579 if (!ss) {
580 return NULL;
581 }
582
583 ss->border_color_use = sampler_state_needs_border_color(state);
584
585 /* R_03C000_SQ_TEX_SAMPLER_WORD0_0 */
586 ss->tex_sampler_words[0] =
587 S_03C000_CLAMP_X(r600_tex_wrap(state->wrap_s)) |
588 S_03C000_CLAMP_Y(r600_tex_wrap(state->wrap_t)) |
589 S_03C000_CLAMP_Z(r600_tex_wrap(state->wrap_r)) |
590 S_03C000_XY_MAG_FILTER(eg_tex_filter(state->mag_img_filter, max_aniso)) |
591 S_03C000_XY_MIN_FILTER(eg_tex_filter(state->min_img_filter, max_aniso)) |
592 S_03C000_MIP_FILTER(r600_tex_mipfilter(state->min_mip_filter)) |
593 S_03C000_MAX_ANISO_RATIO(max_aniso_ratio) |
594 S_03C000_DEPTH_COMPARE_FUNCTION(r600_tex_compare(state->compare_func)) |
595 S_03C000_BORDER_COLOR_TYPE(ss->border_color_use ? V_03C000_SQ_TEX_BORDER_COLOR_REGISTER : 0);
596 /* R_03C004_SQ_TEX_SAMPLER_WORD1_0 */
597 ss->tex_sampler_words[1] =
598 S_03C004_MIN_LOD(S_FIXED(CLAMP(state->min_lod, 0, 15), 8)) |
599 S_03C004_MAX_LOD(S_FIXED(CLAMP(state->max_lod, 0, 15), 8));
600 /* R_03C008_SQ_TEX_SAMPLER_WORD2_0 */
601 ss->tex_sampler_words[2] =
602 S_03C008_LOD_BIAS(S_FIXED(CLAMP(state->lod_bias, -16, 16), 8)) |
603 (state->seamless_cube_map ? 0 : S_03C008_DISABLE_CUBE_WRAP(1)) |
604 S_03C008_TYPE(1);
605
606 if (ss->border_color_use) {
607 memcpy(&ss->border_color, &state->border_color, sizeof(state->border_color));
608 }
609 return ss;
610 }
611
612 struct eg_buf_res_params {
613 enum pipe_format pipe_format;
614 unsigned offset;
615 unsigned size;
616 unsigned char swizzle[4];
617 bool uncached;
618 bool force_swizzle;
619 bool size_in_bytes;
620 };
621
622 static void evergreen_fill_buffer_resource_words(struct r600_context *rctx,
623 struct pipe_resource *buffer,
624 struct eg_buf_res_params *params,
625 bool *skip_mip_address_reloc,
626 unsigned tex_resource_words[8])
627 {
628 struct r600_texture *tmp = (struct r600_texture*)buffer;
629 uint64_t va;
630 int stride = util_format_get_blocksize(params->pipe_format);
631 unsigned format, num_format, format_comp, endian;
632 unsigned swizzle_res;
633 const struct util_format_description *desc;
634
635 r600_vertex_data_type(params->pipe_format,
636 &format, &num_format, &format_comp,
637 &endian);
638
639 desc = util_format_description(params->pipe_format);
640
641 if (params->force_swizzle)
642 swizzle_res = r600_get_swizzle_combined(params->swizzle, NULL, TRUE);
643 else
644 swizzle_res = r600_get_swizzle_combined(desc->swizzle, params->swizzle, TRUE);
645
646 va = tmp->resource.gpu_address + params->offset;
647 *skip_mip_address_reloc = true;
648 tex_resource_words[0] = va;
649 tex_resource_words[1] = params->size - 1;
650 tex_resource_words[2] = S_030008_BASE_ADDRESS_HI(va >> 32UL) |
651 S_030008_STRIDE(stride) |
652 S_030008_DATA_FORMAT(format) |
653 S_030008_NUM_FORMAT_ALL(num_format) |
654 S_030008_FORMAT_COMP_ALL(format_comp) |
655 S_030008_ENDIAN_SWAP(endian);
656 tex_resource_words[3] = swizzle_res | S_03000C_UNCACHED(params->uncached);
657 /*
658 * dword 4 is for number of elements, for use with resinfo,
659 * albeit the amd gpu shader analyser
660 * uses a const buffer to store the element sizes for buffer txq
661 */
662 tex_resource_words[4] = params->size_in_bytes ? params->size : (params->size / stride);
663
664 tex_resource_words[5] = tex_resource_words[6] = 0;
665 tex_resource_words[7] = S_03001C_TYPE(V_03001C_SQ_TEX_VTX_VALID_BUFFER);
666 }
667
668 static struct pipe_sampler_view *
669 texture_buffer_sampler_view(struct r600_context *rctx,
670 struct r600_pipe_sampler_view *view,
671 unsigned width0, unsigned height0)
672 {
673 struct r600_texture *tmp = (struct r600_texture*)view->base.texture;
674 struct eg_buf_res_params params;
675
676 memset(&params, 0, sizeof(params));
677
678 params.pipe_format = view->base.format;
679 params.offset = view->base.u.buf.offset;
680 params.size = view->base.u.buf.size;
681 params.swizzle[0] = view->base.swizzle_r;
682 params.swizzle[1] = view->base.swizzle_g;
683 params.swizzle[2] = view->base.swizzle_b;
684 params.swizzle[3] = view->base.swizzle_a;
685
686 evergreen_fill_buffer_resource_words(rctx, view->base.texture,
687 &params, &view->skip_mip_address_reloc,
688 view->tex_resource_words);
689 view->tex_resource = &tmp->resource;
690
691 if (tmp->resource.gpu_address)
692 LIST_ADDTAIL(&view->list, &rctx->texture_buffers);
693 return &view->base;
694 }
695
696 struct eg_tex_res_params {
697 enum pipe_format pipe_format;
698 int force_level;
699 unsigned width0;
700 unsigned height0;
701 unsigned first_level;
702 unsigned last_level;
703 unsigned first_layer;
704 unsigned last_layer;
705 unsigned target;
706 unsigned char swizzle[4];
707 };
708
709 static int evergreen_fill_tex_resource_words(struct r600_context *rctx,
710 struct pipe_resource *texture,
711 struct eg_tex_res_params *params,
712 bool *skip_mip_address_reloc,
713 unsigned tex_resource_words[8])
714 {
715 struct r600_screen *rscreen = (struct r600_screen*)rctx->b.b.screen;
716 struct r600_texture *tmp = (struct r600_texture*)texture;
717 unsigned format, endian;
718 uint32_t word4 = 0, yuv_format = 0, pitch = 0;
719 unsigned char array_mode = 0, non_disp_tiling = 0;
720 unsigned height, depth, width;
721 unsigned macro_aspect, tile_split, bankh, bankw, nbanks, fmask_bankh;
722 struct legacy_surf_level *surflevel;
723 unsigned base_level, first_level, last_level;
724 unsigned dim, last_layer;
725 uint64_t va;
726 bool do_endian_swap = FALSE;
727
728 tile_split = tmp->surface.u.legacy.tile_split;
729 surflevel = tmp->surface.u.legacy.level;
730
731 /* Texturing with separate depth and stencil. */
732 if (tmp->db_compatible) {
733 switch (params->pipe_format) {
734 case PIPE_FORMAT_Z32_FLOAT_S8X24_UINT:
735 params->pipe_format = PIPE_FORMAT_Z32_FLOAT;
736 break;
737 case PIPE_FORMAT_X8Z24_UNORM:
738 case PIPE_FORMAT_S8_UINT_Z24_UNORM:
739 /* Z24 is always stored like this for DB
740 * compatibility.
741 */
742 params->pipe_format = PIPE_FORMAT_Z24X8_UNORM;
743 break;
744 case PIPE_FORMAT_X24S8_UINT:
745 case PIPE_FORMAT_S8X24_UINT:
746 case PIPE_FORMAT_X32_S8X24_UINT:
747 params->pipe_format = PIPE_FORMAT_S8_UINT;
748 tile_split = tmp->surface.u.legacy.stencil_tile_split;
749 surflevel = tmp->surface.u.legacy.stencil_level;
750 break;
751 default:;
752 }
753 }
754
755 if (R600_BIG_ENDIAN)
756 do_endian_swap = !tmp->db_compatible;
757
758 format = r600_translate_texformat(rctx->b.b.screen, params->pipe_format,
759 params->swizzle,
760 &word4, &yuv_format, do_endian_swap);
761 assert(format != ~0);
762 if (format == ~0) {
763 return -1;
764 }
765
766 endian = r600_colorformat_endian_swap(format, do_endian_swap);
767
768 base_level = 0;
769 first_level = params->first_level;
770 last_level = params->last_level;
771 width = params->width0;
772 height = params->height0;
773 depth = texture->depth0;
774
775 if (params->force_level) {
776 base_level = params->force_level;
777 first_level = 0;
778 last_level = 0;
779 width = u_minify(width, params->force_level);
780 height = u_minify(height, params->force_level);
781 depth = u_minify(depth, params->force_level);
782 }
783
784 pitch = surflevel[base_level].nblk_x * util_format_get_blockwidth(params->pipe_format);
785 non_disp_tiling = tmp->non_disp_tiling;
786
787 switch (surflevel[base_level].mode) {
788 default:
789 case RADEON_SURF_MODE_LINEAR_ALIGNED:
790 array_mode = V_028C70_ARRAY_LINEAR_ALIGNED;
791 break;
792 case RADEON_SURF_MODE_2D:
793 array_mode = V_028C70_ARRAY_2D_TILED_THIN1;
794 break;
795 case RADEON_SURF_MODE_1D:
796 array_mode = V_028C70_ARRAY_1D_TILED_THIN1;
797 break;
798 }
799 macro_aspect = tmp->surface.u.legacy.mtilea;
800 bankw = tmp->surface.u.legacy.bankw;
801 bankh = tmp->surface.u.legacy.bankh;
802 tile_split = eg_tile_split(tile_split);
803 macro_aspect = eg_macro_tile_aspect(macro_aspect);
804 bankw = eg_bank_wh(bankw);
805 bankh = eg_bank_wh(bankh);
806 fmask_bankh = eg_bank_wh(tmp->fmask.bank_height);
807
808 /* 128 bit formats require tile type = 1 */
809 if (rscreen->b.chip_class == CAYMAN) {
810 if (util_format_get_blocksize(params->pipe_format) >= 16)
811 non_disp_tiling = 1;
812 }
813 nbanks = eg_num_banks(rscreen->b.info.r600_num_banks);
814
815
816 va = tmp->resource.gpu_address;
817
818 /* array type views and views into array types need to use layer offset */
819 dim = r600_tex_dim(tmp, params->target, texture->nr_samples);
820
821 if (dim == V_030000_SQ_TEX_DIM_1D_ARRAY) {
822 height = 1;
823 depth = texture->array_size;
824 } else if (dim == V_030000_SQ_TEX_DIM_2D_ARRAY ||
825 dim == V_030000_SQ_TEX_DIM_2D_ARRAY_MSAA) {
826 depth = texture->array_size;
827 } else if (dim == V_030000_SQ_TEX_DIM_CUBEMAP)
828 depth = texture->array_size / 6;
829
830 tex_resource_words[0] = (S_030000_DIM(dim) |
831 S_030000_PITCH((pitch / 8) - 1) |
832 S_030000_TEX_WIDTH(width - 1));
833 if (rscreen->b.chip_class == CAYMAN)
834 tex_resource_words[0] |= CM_S_030000_NON_DISP_TILING_ORDER(non_disp_tiling);
835 else
836 tex_resource_words[0] |= S_030000_NON_DISP_TILING_ORDER(non_disp_tiling);
837 tex_resource_words[1] = (S_030004_TEX_HEIGHT(height - 1) |
838 S_030004_TEX_DEPTH(depth - 1) |
839 S_030004_ARRAY_MODE(array_mode));
840 tex_resource_words[2] = (surflevel[base_level].offset + va) >> 8;
841
842 *skip_mip_address_reloc = false;
843 /* TEX_RESOURCE_WORD3.MIP_ADDRESS */
844 if (texture->nr_samples > 1 && rscreen->has_compressed_msaa_texturing) {
845 if (tmp->is_depth) {
846 /* disable FMASK (0 = disabled) */
847 tex_resource_words[3] = 0;
848 *skip_mip_address_reloc = true;
849 } else {
850 /* FMASK should be in MIP_ADDRESS for multisample textures */
851 tex_resource_words[3] = (tmp->fmask.offset + va) >> 8;
852 }
853 } else if (last_level && texture->nr_samples <= 1) {
854 tex_resource_words[3] = (surflevel[1].offset + va) >> 8;
855 } else {
856 tex_resource_words[3] = (surflevel[base_level].offset + va) >> 8;
857 }
858
859 last_layer = params->last_layer;
860 if (params->target != texture->target && depth == 1) {
861 last_layer = params->first_layer;
862 }
863 tex_resource_words[4] = (word4 |
864 S_030010_ENDIAN_SWAP(endian));
865 tex_resource_words[5] = S_030014_BASE_ARRAY(params->first_layer) |
866 S_030014_LAST_ARRAY(last_layer);
867 tex_resource_words[6] = S_030018_TILE_SPLIT(tile_split);
868
869 if (texture->nr_samples > 1) {
870 unsigned log_samples = util_logbase2(texture->nr_samples);
871 if (rscreen->b.chip_class == CAYMAN) {
872 tex_resource_words[4] |= S_030010_LOG2_NUM_FRAGMENTS(log_samples);
873 }
874 /* LAST_LEVEL holds log2(nr_samples) for multisample textures */
875 tex_resource_words[5] |= S_030014_LAST_LEVEL(log_samples);
876 tex_resource_words[6] |= S_030018_FMASK_BANK_HEIGHT(fmask_bankh);
877 } else {
878 bool no_mip = first_level == last_level;
879
880 tex_resource_words[4] |= S_030010_BASE_LEVEL(first_level);
881 tex_resource_words[5] |= S_030014_LAST_LEVEL(last_level);
882 /* aniso max 16 samples */
883 tex_resource_words[6] |= S_030018_MAX_ANISO_RATIO(no_mip ? 0 : 4);
884 }
885
886 tex_resource_words[7] = S_03001C_DATA_FORMAT(format) |
887 S_03001C_TYPE(V_03001C_SQ_TEX_VTX_VALID_TEXTURE) |
888 S_03001C_BANK_WIDTH(bankw) |
889 S_03001C_BANK_HEIGHT(bankh) |
890 S_03001C_MACRO_TILE_ASPECT(macro_aspect) |
891 S_03001C_NUM_BANKS(nbanks) |
892 S_03001C_DEPTH_SAMPLE_ORDER(tmp->db_compatible);
893 return 0;
894 }
895
896 struct pipe_sampler_view *
897 evergreen_create_sampler_view_custom(struct pipe_context *ctx,
898 struct pipe_resource *texture,
899 const struct pipe_sampler_view *state,
900 unsigned width0, unsigned height0,
901 unsigned force_level)
902 {
903 struct r600_context *rctx = (struct r600_context*)ctx;
904 struct r600_pipe_sampler_view *view = CALLOC_STRUCT(r600_pipe_sampler_view);
905 struct r600_texture *tmp = (struct r600_texture*)texture;
906 struct eg_tex_res_params params;
907 int ret;
908
909 if (!view)
910 return NULL;
911
912 /* initialize base object */
913 view->base = *state;
914 view->base.texture = NULL;
915 pipe_reference(NULL, &texture->reference);
916 view->base.texture = texture;
917 view->base.reference.count = 1;
918 view->base.context = ctx;
919
920 if (state->target == PIPE_BUFFER)
921 return texture_buffer_sampler_view(rctx, view, width0, height0);
922
923 memset(&params, 0, sizeof(params));
924 params.pipe_format = state->format;
925 params.force_level = force_level;
926 params.width0 = width0;
927 params.height0 = height0;
928 params.first_level = state->u.tex.first_level;
929 params.last_level = state->u.tex.last_level;
930 params.first_layer = state->u.tex.first_layer;
931 params.last_layer = state->u.tex.last_layer;
932 params.target = state->target;
933 params.swizzle[0] = state->swizzle_r;
934 params.swizzle[1] = state->swizzle_g;
935 params.swizzle[2] = state->swizzle_b;
936 params.swizzle[3] = state->swizzle_a;
937
938 ret = evergreen_fill_tex_resource_words(rctx, texture, &params,
939 &view->skip_mip_address_reloc,
940 view->tex_resource_words);
941 if (ret != 0) {
942 FREE(view);
943 return NULL;
944 }
945
946 if (state->format == PIPE_FORMAT_X24S8_UINT ||
947 state->format == PIPE_FORMAT_S8X24_UINT ||
948 state->format == PIPE_FORMAT_X32_S8X24_UINT ||
949 state->format == PIPE_FORMAT_S8_UINT)
950 view->is_stencil_sampler = true;
951
952 view->tex_resource = &tmp->resource;
953
954 return &view->base;
955 }
956
957 static struct pipe_sampler_view *
958 evergreen_create_sampler_view(struct pipe_context *ctx,
959 struct pipe_resource *tex,
960 const struct pipe_sampler_view *state)
961 {
962 return evergreen_create_sampler_view_custom(ctx, tex, state,
963 tex->width0, tex->height0, 0);
964 }
965
966 static void evergreen_emit_config_state(struct r600_context *rctx, struct r600_atom *atom)
967 {
968 struct radeon_winsys_cs *cs = rctx->b.gfx.cs;
969 struct r600_config_state *a = (struct r600_config_state*)atom;
970
971 radeon_set_config_reg_seq(cs, R_008C04_SQ_GPR_RESOURCE_MGMT_1, 3);
972 if (a->dyn_gpr_enabled) {
973 radeon_emit(cs, S_008C04_NUM_CLAUSE_TEMP_GPRS(rctx->r6xx_num_clause_temp_gprs));
974 radeon_emit(cs, 0);
975 radeon_emit(cs, 0);
976 } else {
977 radeon_emit(cs, a->sq_gpr_resource_mgmt_1);
978 radeon_emit(cs, a->sq_gpr_resource_mgmt_2);
979 radeon_emit(cs, a->sq_gpr_resource_mgmt_3);
980 }
981 radeon_set_config_reg(cs, R_008D8C_SQ_DYN_GPR_CNTL_PS_FLUSH_REQ, (a->dyn_gpr_enabled << 8));
982 if (a->dyn_gpr_enabled) {
983 radeon_set_context_reg(cs, R_028838_SQ_DYN_GPR_RESOURCE_LIMIT_1,
984 S_028838_PS_GPRS(0x1e) |
985 S_028838_VS_GPRS(0x1e) |
986 S_028838_GS_GPRS(0x1e) |
987 S_028838_ES_GPRS(0x1e) |
988 S_028838_HS_GPRS(0x1e) |
989 S_028838_LS_GPRS(0x1e)); /* workaround for hw issues with dyn gpr - must set all limits to 240 instead of 0, 0x1e == 240 / 8*/
990 }
991 }
992
993 static void evergreen_emit_clip_state(struct r600_context *rctx, struct r600_atom *atom)
994 {
995 struct radeon_winsys_cs *cs = rctx->b.gfx.cs;
996 struct pipe_clip_state *state = &rctx->clip_state.state;
997
998 radeon_set_context_reg_seq(cs, R_0285BC_PA_CL_UCP0_X, 6*4);
999 radeon_emit_array(cs, (unsigned*)state, 6*4);
1000 }
1001
1002 static void evergreen_set_polygon_stipple(struct pipe_context *ctx,
1003 const struct pipe_poly_stipple *state)
1004 {
1005 }
1006
1007 static void evergreen_get_scissor_rect(struct r600_context *rctx,
1008 unsigned tl_x, unsigned tl_y, unsigned br_x, unsigned br_y,
1009 uint32_t *tl, uint32_t *br)
1010 {
1011 struct pipe_scissor_state scissor = {tl_x, tl_y, br_x, br_y};
1012
1013 evergreen_apply_scissor_bug_workaround(&rctx->b, &scissor);
1014
1015 *tl = S_028240_TL_X(scissor.minx) | S_028240_TL_Y(scissor.miny);
1016 *br = S_028244_BR_X(scissor.maxx) | S_028244_BR_Y(scissor.maxy);
1017 }
1018
1019 struct r600_tex_color_info {
1020 unsigned info;
1021 unsigned view;
1022 unsigned dim;
1023 unsigned pitch;
1024 unsigned slice;
1025 unsigned attrib;
1026 unsigned ntype;
1027 unsigned fmask;
1028 unsigned fmask_slice;
1029 uint64_t offset;
1030 boolean export_16bpc;
1031 };
1032
1033 static void evergreen_set_color_surface_buffer(struct r600_context *rctx,
1034 struct r600_resource *res,
1035 enum pipe_format pformat,
1036 unsigned first_element,
1037 unsigned last_element,
1038 struct r600_tex_color_info *color)
1039 {
1040 unsigned format, swap, ntype, endian;
1041 const struct util_format_description *desc;
1042 unsigned block_size = util_format_get_blocksize(res->b.b.format);
1043 unsigned pitch_alignment =
1044 MAX2(64, rctx->screen->b.info.pipe_interleave_bytes / block_size);
1045 unsigned pitch = align(res->b.b.width0, pitch_alignment);
1046 int i;
1047 unsigned width_elements;
1048
1049 width_elements = last_element - first_element + 1;
1050
1051 format = r600_translate_colorformat(rctx->b.chip_class, pformat, FALSE);
1052 swap = r600_translate_colorswap(pformat, FALSE);
1053
1054 endian = r600_colorformat_endian_swap(format, FALSE);
1055
1056 desc = util_format_description(pformat);
1057 for (i = 0; i < 4; i++) {
1058 if (desc->channel[i].type != UTIL_FORMAT_TYPE_VOID) {
1059 break;
1060 }
1061 }
1062 ntype = V_028C70_NUMBER_UNORM;
1063 if (desc->colorspace == UTIL_FORMAT_COLORSPACE_SRGB)
1064 ntype = V_028C70_NUMBER_SRGB;
1065 else if (desc->channel[i].type == UTIL_FORMAT_TYPE_SIGNED) {
1066 if (desc->channel[i].normalized)
1067 ntype = V_028C70_NUMBER_SNORM;
1068 else if (desc->channel[i].pure_integer)
1069 ntype = V_028C70_NUMBER_SINT;
1070 } else if (desc->channel[i].type == UTIL_FORMAT_TYPE_UNSIGNED) {
1071 if (desc->channel[i].normalized)
1072 ntype = V_028C70_NUMBER_UNORM;
1073 else if (desc->channel[i].pure_integer)
1074 ntype = V_028C70_NUMBER_UINT;
1075 } else if (desc->channel[i].type == UTIL_FORMAT_TYPE_FLOAT) {
1076 ntype = V_028C70_NUMBER_FLOAT;
1077 }
1078
1079 pitch = (pitch / 8) - 1;
1080 color->pitch = S_028C64_PITCH_TILE_MAX(pitch);
1081
1082 color->info = S_028C70_ARRAY_MODE(V_028C70_ARRAY_LINEAR_ALIGNED);
1083 color->info |= S_028C70_FORMAT(format) |
1084 S_028C70_COMP_SWAP(swap) |
1085 S_028C70_BLEND_CLAMP(0) |
1086 S_028C70_BLEND_BYPASS(1) |
1087 S_028C70_NUMBER_TYPE(ntype) |
1088 S_028C70_ENDIAN(endian);
1089 color->attrib = S_028C74_NON_DISP_TILING_ORDER(1);
1090 color->ntype = ntype;
1091 color->export_16bpc = false;
1092 color->dim = width_elements - 1;
1093 color->slice = 0; /* (width_elements / 64) - 1;*/
1094 color->view = 0;
1095 color->offset = (res->gpu_address + first_element) >> 8;
1096
1097 color->fmask = color->offset;
1098 color->fmask_slice = 0;
1099 }
1100
1101 static void evergreen_set_color_surface_common(struct r600_context *rctx,
1102 struct r600_texture *rtex,
1103 unsigned level,
1104 unsigned first_layer,
1105 unsigned last_layer,
1106 enum pipe_format pformat,
1107 struct r600_tex_color_info *color)
1108 {
1109 struct r600_screen *rscreen = rctx->screen;
1110 unsigned pitch, slice;
1111 unsigned non_disp_tiling, macro_aspect, tile_split, bankh, bankw, fmask_bankh, nbanks;
1112 unsigned format, swap, ntype, endian;
1113 const struct util_format_description *desc;
1114 bool blend_clamp = 0, blend_bypass = 0, do_endian_swap = FALSE;
1115 int i;
1116
1117 color->offset = rtex->surface.u.legacy.level[level].offset;
1118 color->view = S_028C6C_SLICE_START(first_layer) |
1119 S_028C6C_SLICE_MAX(last_layer);
1120
1121 color->offset += rtex->resource.gpu_address;
1122 color->offset >>= 8;
1123
1124 color->dim = 0;
1125 pitch = (rtex->surface.u.legacy.level[level].nblk_x) / 8 - 1;
1126 slice = (rtex->surface.u.legacy.level[level].nblk_x * rtex->surface.u.legacy.level[level].nblk_y) / 64;
1127 if (slice) {
1128 slice = slice - 1;
1129 }
1130
1131 color->info = 0;
1132 switch (rtex->surface.u.legacy.level[level].mode) {
1133 default:
1134 case RADEON_SURF_MODE_LINEAR_ALIGNED:
1135 color->info = S_028C70_ARRAY_MODE(V_028C70_ARRAY_LINEAR_ALIGNED);
1136 non_disp_tiling = 1;
1137 break;
1138 case RADEON_SURF_MODE_1D:
1139 color->info = S_028C70_ARRAY_MODE(V_028C70_ARRAY_1D_TILED_THIN1);
1140 non_disp_tiling = rtex->non_disp_tiling;
1141 break;
1142 case RADEON_SURF_MODE_2D:
1143 color->info = S_028C70_ARRAY_MODE(V_028C70_ARRAY_2D_TILED_THIN1);
1144 non_disp_tiling = rtex->non_disp_tiling;
1145 break;
1146 }
1147 tile_split = rtex->surface.u.legacy.tile_split;
1148 macro_aspect = rtex->surface.u.legacy.mtilea;
1149 bankw = rtex->surface.u.legacy.bankw;
1150 bankh = rtex->surface.u.legacy.bankh;
1151 if (rtex->fmask.size)
1152 fmask_bankh = rtex->fmask.bank_height;
1153 else
1154 fmask_bankh = rtex->surface.u.legacy.bankh;
1155 tile_split = eg_tile_split(tile_split);
1156 macro_aspect = eg_macro_tile_aspect(macro_aspect);
1157 bankw = eg_bank_wh(bankw);
1158 bankh = eg_bank_wh(bankh);
1159 fmask_bankh = eg_bank_wh(fmask_bankh);
1160
1161 if (rscreen->b.chip_class == CAYMAN) {
1162 if (util_format_get_blocksize(pformat) >= 16)
1163 non_disp_tiling = 1;
1164 }
1165 nbanks = eg_num_banks(rscreen->b.info.r600_num_banks);
1166 desc = util_format_description(pformat);
1167 for (i = 0; i < 4; i++) {
1168 if (desc->channel[i].type != UTIL_FORMAT_TYPE_VOID) {
1169 break;
1170 }
1171 }
1172 color->attrib = S_028C74_TILE_SPLIT(tile_split)|
1173 S_028C74_NUM_BANKS(nbanks) |
1174 S_028C74_BANK_WIDTH(bankw) |
1175 S_028C74_BANK_HEIGHT(bankh) |
1176 S_028C74_MACRO_TILE_ASPECT(macro_aspect) |
1177 S_028C74_NON_DISP_TILING_ORDER(non_disp_tiling) |
1178 S_028C74_FMASK_BANK_HEIGHT(fmask_bankh);
1179
1180 if (rctx->b.chip_class == CAYMAN) {
1181 color->attrib |= S_028C74_FORCE_DST_ALPHA_1(desc->swizzle[3] ==
1182 PIPE_SWIZZLE_1);
1183
1184 if (rtex->resource.b.b.nr_samples > 1) {
1185 unsigned log_samples = util_logbase2(rtex->resource.b.b.nr_samples);
1186 color->attrib |= S_028C74_NUM_SAMPLES(log_samples) |
1187 S_028C74_NUM_FRAGMENTS(log_samples);
1188 }
1189 }
1190
1191 ntype = V_028C70_NUMBER_UNORM;
1192 if (desc->colorspace == UTIL_FORMAT_COLORSPACE_SRGB)
1193 ntype = V_028C70_NUMBER_SRGB;
1194 else if (desc->channel[i].type == UTIL_FORMAT_TYPE_SIGNED) {
1195 if (desc->channel[i].normalized)
1196 ntype = V_028C70_NUMBER_SNORM;
1197 else if (desc->channel[i].pure_integer)
1198 ntype = V_028C70_NUMBER_SINT;
1199 } else if (desc->channel[i].type == UTIL_FORMAT_TYPE_UNSIGNED) {
1200 if (desc->channel[i].normalized)
1201 ntype = V_028C70_NUMBER_UNORM;
1202 else if (desc->channel[i].pure_integer)
1203 ntype = V_028C70_NUMBER_UINT;
1204 } else if (desc->channel[i].type == UTIL_FORMAT_TYPE_FLOAT) {
1205 ntype = V_028C70_NUMBER_FLOAT;
1206 }
1207
1208 if (R600_BIG_ENDIAN)
1209 do_endian_swap = !rtex->db_compatible;
1210
1211 format = r600_translate_colorformat(rctx->b.chip_class, pformat, do_endian_swap);
1212 assert(format != ~0);
1213 swap = r600_translate_colorswap(pformat, do_endian_swap);
1214 assert(swap != ~0);
1215
1216 endian = r600_colorformat_endian_swap(format, do_endian_swap);
1217
1218 /* blend clamp should be set for all NORM/SRGB types */
1219 if (ntype == V_028C70_NUMBER_UNORM || ntype == V_028C70_NUMBER_SNORM ||
1220 ntype == V_028C70_NUMBER_SRGB)
1221 blend_clamp = 1;
1222
1223 /* set blend bypass according to docs if SINT/UINT or
1224 8/24 COLOR variants */
1225 if (ntype == V_028C70_NUMBER_UINT || ntype == V_028C70_NUMBER_SINT ||
1226 format == V_028C70_COLOR_8_24 || format == V_028C70_COLOR_24_8 ||
1227 format == V_028C70_COLOR_X24_8_32_FLOAT) {
1228 blend_clamp = 0;
1229 blend_bypass = 1;
1230 }
1231
1232 color->ntype = ntype;
1233 color->info |= S_028C70_FORMAT(format) |
1234 S_028C70_COMP_SWAP(swap) |
1235 S_028C70_BLEND_CLAMP(blend_clamp) |
1236 S_028C70_BLEND_BYPASS(blend_bypass) |
1237 S_028C70_SIMPLE_FLOAT(1) |
1238 S_028C70_NUMBER_TYPE(ntype) |
1239 S_028C70_ENDIAN(endian);
1240
1241 if (rtex->fmask.size) {
1242 color->info |= S_028C70_COMPRESSION(1);
1243 }
1244
1245 /* EXPORT_NORM is an optimzation that can be enabled for better
1246 * performance in certain cases.
1247 * EXPORT_NORM can be enabled if:
1248 * - 11-bit or smaller UNORM/SNORM/SRGB
1249 * - 16-bit or smaller FLOAT
1250 */
1251 color->export_16bpc = false;
1252 if (desc->colorspace != UTIL_FORMAT_COLORSPACE_ZS &&
1253 ((desc->channel[i].size < 12 &&
1254 desc->channel[i].type != UTIL_FORMAT_TYPE_FLOAT &&
1255 ntype != V_028C70_NUMBER_UINT && ntype != V_028C70_NUMBER_SINT) ||
1256 (desc->channel[i].size < 17 &&
1257 desc->channel[i].type == UTIL_FORMAT_TYPE_FLOAT))) {
1258 color->info |= S_028C70_SOURCE_FORMAT(V_028C70_EXPORT_4C_16BPC);
1259 color->export_16bpc = true;
1260 }
1261
1262 color->pitch = S_028C64_PITCH_TILE_MAX(pitch);
1263 color->slice = S_028C68_SLICE_TILE_MAX(slice);
1264
1265 if (rtex->fmask.size) {
1266 color->fmask = (rtex->resource.gpu_address + rtex->fmask.offset) >> 8;
1267 color->fmask_slice = S_028C88_TILE_MAX(rtex->fmask.slice_tile_max);
1268 } else {
1269 color->fmask = color->offset;
1270 color->fmask_slice = S_028C88_TILE_MAX(slice);
1271 }
1272 }
1273
1274 /**
1275 * This function intializes the CB* register values for RATs. It is meant
1276 * to be used for 1D aligned buffers that do not have an associated
1277 * radeon_surf.
1278 */
1279 void evergreen_init_color_surface_rat(struct r600_context *rctx,
1280 struct r600_surface *surf)
1281 {
1282 struct pipe_resource *pipe_buffer = surf->base.texture;
1283 struct r600_tex_color_info color;
1284
1285 evergreen_set_color_surface_buffer(rctx, (struct r600_resource *)surf->base.texture,
1286 surf->base.format, 0, pipe_buffer->width0,
1287 &color);
1288
1289 surf->cb_color_base = color.offset;
1290 surf->cb_color_dim = color.dim;
1291 surf->cb_color_info = color.info | S_028C70_RAT(1);
1292 surf->cb_color_pitch = color.pitch;
1293 surf->cb_color_slice = color.slice;
1294 surf->cb_color_view = color.view;
1295 surf->cb_color_attrib = color.attrib;
1296 surf->cb_color_fmask = color.fmask;
1297 surf->cb_color_fmask_slice = color.fmask_slice;
1298
1299 surf->cb_color_view = 0;
1300
1301 /* Set the buffer range the GPU will have access to: */
1302 util_range_add(&r600_resource(pipe_buffer)->valid_buffer_range,
1303 0, pipe_buffer->width0);
1304 }
1305
1306
1307 void evergreen_init_color_surface(struct r600_context *rctx,
1308 struct r600_surface *surf)
1309 {
1310 struct r600_texture *rtex = (struct r600_texture*)surf->base.texture;
1311 unsigned level = surf->base.u.tex.level;
1312 struct r600_tex_color_info color;
1313
1314 evergreen_set_color_surface_common(rctx, rtex, level,
1315 surf->base.u.tex.first_layer,
1316 surf->base.u.tex.last_layer,
1317 surf->base.format,
1318 &color);
1319
1320 surf->alphatest_bypass = color.ntype == V_028C70_NUMBER_UINT ||
1321 color.ntype == V_028C70_NUMBER_SINT;
1322 surf->export_16bpc = color.export_16bpc;
1323
1324 /* XXX handle enabling of CB beyond BASE8 which has different offset */
1325 surf->cb_color_base = color.offset;
1326 surf->cb_color_dim = color.dim;
1327 surf->cb_color_info = color.info;
1328 surf->cb_color_pitch = color.pitch;
1329 surf->cb_color_slice = color.slice;
1330 surf->cb_color_view = color.view;
1331 surf->cb_color_attrib = color.attrib;
1332 surf->cb_color_fmask = color.fmask;
1333 surf->cb_color_fmask_slice = color.fmask_slice;
1334
1335 surf->color_initialized = true;
1336 }
1337
1338 static void evergreen_init_depth_surface(struct r600_context *rctx,
1339 struct r600_surface *surf)
1340 {
1341 struct r600_screen *rscreen = rctx->screen;
1342 struct r600_texture *rtex = (struct r600_texture*)surf->base.texture;
1343 unsigned level = surf->base.u.tex.level;
1344 struct legacy_surf_level *levelinfo = &rtex->surface.u.legacy.level[level];
1345 uint64_t offset;
1346 unsigned format, array_mode;
1347 unsigned macro_aspect, tile_split, bankh, bankw, nbanks;
1348
1349
1350 format = r600_translate_dbformat(surf->base.format);
1351 assert(format != ~0);
1352
1353 offset = rtex->resource.gpu_address;
1354 offset += rtex->surface.u.legacy.level[level].offset;
1355
1356 switch (rtex->surface.u.legacy.level[level].mode) {
1357 case RADEON_SURF_MODE_2D:
1358 array_mode = V_028C70_ARRAY_2D_TILED_THIN1;
1359 break;
1360 case RADEON_SURF_MODE_1D:
1361 case RADEON_SURF_MODE_LINEAR_ALIGNED:
1362 default:
1363 array_mode = V_028C70_ARRAY_1D_TILED_THIN1;
1364 break;
1365 }
1366 tile_split = rtex->surface.u.legacy.tile_split;
1367 macro_aspect = rtex->surface.u.legacy.mtilea;
1368 bankw = rtex->surface.u.legacy.bankw;
1369 bankh = rtex->surface.u.legacy.bankh;
1370 tile_split = eg_tile_split(tile_split);
1371 macro_aspect = eg_macro_tile_aspect(macro_aspect);
1372 bankw = eg_bank_wh(bankw);
1373 bankh = eg_bank_wh(bankh);
1374 nbanks = eg_num_banks(rscreen->b.info.r600_num_banks);
1375 offset >>= 8;
1376
1377 surf->db_z_info = S_028040_ARRAY_MODE(array_mode) |
1378 S_028040_FORMAT(format) |
1379 S_028040_TILE_SPLIT(tile_split)|
1380 S_028040_NUM_BANKS(nbanks) |
1381 S_028040_BANK_WIDTH(bankw) |
1382 S_028040_BANK_HEIGHT(bankh) |
1383 S_028040_MACRO_TILE_ASPECT(macro_aspect);
1384 if (rscreen->b.chip_class == CAYMAN && rtex->resource.b.b.nr_samples > 1) {
1385 surf->db_z_info |= S_028040_NUM_SAMPLES(util_logbase2(rtex->resource.b.b.nr_samples));
1386 }
1387
1388 assert(levelinfo->nblk_x % 8 == 0 && levelinfo->nblk_y % 8 == 0);
1389
1390 surf->db_depth_base = offset;
1391 surf->db_depth_view = S_028008_SLICE_START(surf->base.u.tex.first_layer) |
1392 S_028008_SLICE_MAX(surf->base.u.tex.last_layer);
1393 surf->db_depth_size = S_028058_PITCH_TILE_MAX(levelinfo->nblk_x / 8 - 1) |
1394 S_028058_HEIGHT_TILE_MAX(levelinfo->nblk_y / 8 - 1);
1395 surf->db_depth_slice = S_02805C_SLICE_TILE_MAX(levelinfo->nblk_x *
1396 levelinfo->nblk_y / 64 - 1);
1397
1398 if (rtex->surface.has_stencil) {
1399 uint64_t stencil_offset;
1400 unsigned stile_split = rtex->surface.u.legacy.stencil_tile_split;
1401
1402 stile_split = eg_tile_split(stile_split);
1403
1404 stencil_offset = rtex->surface.u.legacy.stencil_level[level].offset;
1405 stencil_offset += rtex->resource.gpu_address;
1406
1407 surf->db_stencil_base = stencil_offset >> 8;
1408 surf->db_stencil_info = S_028044_FORMAT(V_028044_STENCIL_8) |
1409 S_028044_TILE_SPLIT(stile_split);
1410 } else {
1411 surf->db_stencil_base = offset;
1412 /* DRM 2.6.18 allows the INVALID format to disable stencil.
1413 * Older kernels are out of luck. */
1414 surf->db_stencil_info = rctx->screen->b.info.drm_minor >= 18 ?
1415 S_028044_FORMAT(V_028044_STENCIL_INVALID) :
1416 S_028044_FORMAT(V_028044_STENCIL_8);
1417 }
1418
1419 if (r600_htile_enabled(rtex, level)) {
1420 uint64_t va = rtex->resource.gpu_address + rtex->htile_offset;
1421 surf->db_htile_data_base = va >> 8;
1422 surf->db_htile_surface = S_028ABC_HTILE_WIDTH(1) |
1423 S_028ABC_HTILE_HEIGHT(1) |
1424 S_028ABC_FULL_CACHE(1);
1425 surf->db_z_info |= S_028040_TILE_SURFACE_ENABLE(1);
1426 surf->db_preload_control = 0;
1427 }
1428
1429 surf->depth_initialized = true;
1430 }
1431
1432 static void evergreen_set_framebuffer_state(struct pipe_context *ctx,
1433 const struct pipe_framebuffer_state *state)
1434 {
1435 struct r600_context *rctx = (struct r600_context *)ctx;
1436 struct r600_surface *surf;
1437 struct r600_texture *rtex;
1438 uint32_t i, log_samples;
1439 uint32_t target_mask = 0;
1440 /* Flush TC when changing the framebuffer state, because the only
1441 * client not using TC that can change textures is the framebuffer.
1442 * Other places don't typically have to flush TC.
1443 */
1444 rctx->b.flags |= R600_CONTEXT_WAIT_3D_IDLE |
1445 R600_CONTEXT_FLUSH_AND_INV |
1446 R600_CONTEXT_FLUSH_AND_INV_CB |
1447 R600_CONTEXT_FLUSH_AND_INV_CB_META |
1448 R600_CONTEXT_FLUSH_AND_INV_DB |
1449 R600_CONTEXT_FLUSH_AND_INV_DB_META |
1450 R600_CONTEXT_INV_TEX_CACHE;
1451
1452 util_copy_framebuffer_state(&rctx->framebuffer.state, state);
1453
1454 /* Colorbuffers. */
1455 rctx->framebuffer.export_16bpc = state->nr_cbufs != 0;
1456 rctx->framebuffer.cb0_is_integer = state->nr_cbufs && state->cbufs[0] &&
1457 util_format_is_pure_integer(state->cbufs[0]->format);
1458 rctx->framebuffer.compressed_cb_mask = 0;
1459 rctx->framebuffer.nr_samples = util_framebuffer_get_num_samples(state);
1460
1461 for (i = 0; i < state->nr_cbufs; i++) {
1462 surf = (struct r600_surface*)state->cbufs[i];
1463 if (!surf)
1464 continue;
1465
1466 target_mask |= (0xf << (i * 4));
1467
1468 rtex = (struct r600_texture*)surf->base.texture;
1469
1470 r600_context_add_resource_size(ctx, state->cbufs[i]->texture);
1471
1472 if (!surf->color_initialized) {
1473 evergreen_init_color_surface(rctx, surf);
1474 }
1475
1476 if (!surf->export_16bpc) {
1477 rctx->framebuffer.export_16bpc = false;
1478 }
1479
1480 if (rtex->fmask.size) {
1481 rctx->framebuffer.compressed_cb_mask |= 1 << i;
1482 }
1483 }
1484
1485 /* Update alpha-test state dependencies.
1486 * Alpha-test is done on the first colorbuffer only. */
1487 if (state->nr_cbufs) {
1488 bool alphatest_bypass = false;
1489 bool export_16bpc = true;
1490
1491 surf = (struct r600_surface*)state->cbufs[0];
1492 if (surf) {
1493 alphatest_bypass = surf->alphatest_bypass;
1494 export_16bpc = surf->export_16bpc;
1495 }
1496
1497 if (rctx->alphatest_state.bypass != alphatest_bypass) {
1498 rctx->alphatest_state.bypass = alphatest_bypass;
1499 r600_mark_atom_dirty(rctx, &rctx->alphatest_state.atom);
1500 }
1501 if (rctx->alphatest_state.cb0_export_16bpc != export_16bpc) {
1502 rctx->alphatest_state.cb0_export_16bpc = export_16bpc;
1503 r600_mark_atom_dirty(rctx, &rctx->alphatest_state.atom);
1504 }
1505 }
1506
1507 /* ZS buffer. */
1508 if (state->zsbuf) {
1509 surf = (struct r600_surface*)state->zsbuf;
1510
1511 r600_context_add_resource_size(ctx, state->zsbuf->texture);
1512
1513 if (!surf->depth_initialized) {
1514 evergreen_init_depth_surface(rctx, surf);
1515 }
1516
1517 if (state->zsbuf->format != rctx->poly_offset_state.zs_format) {
1518 rctx->poly_offset_state.zs_format = state->zsbuf->format;
1519 r600_mark_atom_dirty(rctx, &rctx->poly_offset_state.atom);
1520 }
1521
1522 if (rctx->db_state.rsurf != surf) {
1523 rctx->db_state.rsurf = surf;
1524 r600_mark_atom_dirty(rctx, &rctx->db_state.atom);
1525 r600_mark_atom_dirty(rctx, &rctx->db_misc_state.atom);
1526 }
1527 } else if (rctx->db_state.rsurf) {
1528 rctx->db_state.rsurf = NULL;
1529 r600_mark_atom_dirty(rctx, &rctx->db_state.atom);
1530 r600_mark_atom_dirty(rctx, &rctx->db_misc_state.atom);
1531 }
1532
1533 if (rctx->cb_misc_state.nr_cbufs != state->nr_cbufs ||
1534 rctx->cb_misc_state.bound_cbufs_target_mask != target_mask) {
1535 rctx->cb_misc_state.bound_cbufs_target_mask = target_mask;
1536 rctx->cb_misc_state.nr_cbufs = state->nr_cbufs;
1537 r600_mark_atom_dirty(rctx, &rctx->cb_misc_state.atom);
1538 }
1539
1540 if (state->nr_cbufs == 0 && rctx->alphatest_state.bypass) {
1541 rctx->alphatest_state.bypass = false;
1542 r600_mark_atom_dirty(rctx, &rctx->alphatest_state.atom);
1543 }
1544
1545 log_samples = util_logbase2(rctx->framebuffer.nr_samples);
1546 /* This is for Cayman to program SAMPLE_RATE, and for RV770 to fix a hw bug. */
1547 if ((rctx->b.chip_class == CAYMAN ||
1548 rctx->b.family == CHIP_RV770) &&
1549 rctx->db_misc_state.log_samples != log_samples) {
1550 rctx->db_misc_state.log_samples = log_samples;
1551 r600_mark_atom_dirty(rctx, &rctx->db_misc_state.atom);
1552 }
1553
1554
1555 /* Calculate the CS size. */
1556 rctx->framebuffer.atom.num_dw = 4; /* SCISSOR */
1557
1558 /* MSAA. */
1559 if (rctx->b.chip_class == EVERGREEN)
1560 rctx->framebuffer.atom.num_dw += 17; /* Evergreen */
1561 else
1562 rctx->framebuffer.atom.num_dw += 28; /* Cayman */
1563
1564 /* Colorbuffers. */
1565 rctx->framebuffer.atom.num_dw += state->nr_cbufs * 23;
1566 rctx->framebuffer.atom.num_dw += state->nr_cbufs * 2;
1567 rctx->framebuffer.atom.num_dw += (12 - state->nr_cbufs) * 3;
1568
1569 /* ZS buffer. */
1570 if (state->zsbuf) {
1571 rctx->framebuffer.atom.num_dw += 24;
1572 rctx->framebuffer.atom.num_dw += 2;
1573 } else if (rctx->screen->b.info.drm_minor >= 18) {
1574 rctx->framebuffer.atom.num_dw += 4;
1575 }
1576
1577 r600_mark_atom_dirty(rctx, &rctx->framebuffer.atom);
1578
1579 r600_set_sample_locations_constant_buffer(rctx);
1580 rctx->framebuffer.do_update_surf_dirtiness = true;
1581 }
1582
1583 static void evergreen_set_min_samples(struct pipe_context *ctx, unsigned min_samples)
1584 {
1585 struct r600_context *rctx = (struct r600_context *)ctx;
1586
1587 if (rctx->ps_iter_samples == min_samples)
1588 return;
1589
1590 rctx->ps_iter_samples = min_samples;
1591 if (rctx->framebuffer.nr_samples > 1) {
1592 r600_mark_atom_dirty(rctx, &rctx->framebuffer.atom);
1593 }
1594 }
1595
1596 /* 8xMSAA */
1597 static uint32_t sample_locs_8x[] = {
1598 FILL_SREG(-1, 1, 1, 5, 3, -5, 5, 3),
1599 FILL_SREG(-7, -1, -3, -7, 7, -3, -5, 7),
1600 FILL_SREG(-1, 1, 1, 5, 3, -5, 5, 3),
1601 FILL_SREG(-7, -1, -3, -7, 7, -3, -5, 7),
1602 FILL_SREG(-1, 1, 1, 5, 3, -5, 5, 3),
1603 FILL_SREG(-7, -1, -3, -7, 7, -3, -5, 7),
1604 FILL_SREG(-1, 1, 1, 5, 3, -5, 5, 3),
1605 FILL_SREG(-7, -1, -3, -7, 7, -3, -5, 7),
1606 };
1607 static unsigned max_dist_8x = 7;
1608
1609 static void evergreen_get_sample_position(struct pipe_context *ctx,
1610 unsigned sample_count,
1611 unsigned sample_index,
1612 float *out_value)
1613 {
1614 int offset, index;
1615 struct {
1616 int idx:4;
1617 } val;
1618 switch (sample_count) {
1619 case 1:
1620 default:
1621 out_value[0] = out_value[1] = 0.5;
1622 break;
1623 case 2:
1624 offset = 4 * (sample_index * 2);
1625 val.idx = (eg_sample_locs_2x[0] >> offset) & 0xf;
1626 out_value[0] = (float)(val.idx + 8) / 16.0f;
1627 val.idx = (eg_sample_locs_2x[0] >> (offset + 4)) & 0xf;
1628 out_value[1] = (float)(val.idx + 8) / 16.0f;
1629 break;
1630 case 4:
1631 offset = 4 * (sample_index * 2);
1632 val.idx = (eg_sample_locs_4x[0] >> offset) & 0xf;
1633 out_value[0] = (float)(val.idx + 8) / 16.0f;
1634 val.idx = (eg_sample_locs_4x[0] >> (offset + 4)) & 0xf;
1635 out_value[1] = (float)(val.idx + 8) / 16.0f;
1636 break;
1637 case 8:
1638 offset = 4 * (sample_index % 4 * 2);
1639 index = (sample_index / 4);
1640 val.idx = (sample_locs_8x[index] >> offset) & 0xf;
1641 out_value[0] = (float)(val.idx + 8) / 16.0f;
1642 val.idx = (sample_locs_8x[index] >> (offset + 4)) & 0xf;
1643 out_value[1] = (float)(val.idx + 8) / 16.0f;
1644 break;
1645 }
1646 }
1647
1648 static void evergreen_emit_msaa_state(struct r600_context *rctx, int nr_samples, int ps_iter_samples)
1649 {
1650
1651 struct radeon_winsys_cs *cs = rctx->b.gfx.cs;
1652 unsigned max_dist = 0;
1653
1654 switch (nr_samples) {
1655 default:
1656 nr_samples = 0;
1657 break;
1658 case 2:
1659 radeon_set_context_reg_seq(cs, R_028C1C_PA_SC_AA_SAMPLE_LOCS_0, ARRAY_SIZE(eg_sample_locs_2x));
1660 radeon_emit_array(cs, eg_sample_locs_2x, ARRAY_SIZE(eg_sample_locs_2x));
1661 max_dist = eg_max_dist_2x;
1662 break;
1663 case 4:
1664 radeon_set_context_reg_seq(cs, R_028C1C_PA_SC_AA_SAMPLE_LOCS_0, ARRAY_SIZE(eg_sample_locs_4x));
1665 radeon_emit_array(cs, eg_sample_locs_4x, ARRAY_SIZE(eg_sample_locs_4x));
1666 max_dist = eg_max_dist_4x;
1667 break;
1668 case 8:
1669 radeon_set_context_reg_seq(cs, R_028C1C_PA_SC_AA_SAMPLE_LOCS_0, ARRAY_SIZE(sample_locs_8x));
1670 radeon_emit_array(cs, sample_locs_8x, ARRAY_SIZE(sample_locs_8x));
1671 max_dist = max_dist_8x;
1672 break;
1673 }
1674
1675 if (nr_samples > 1) {
1676 radeon_set_context_reg_seq(cs, R_028C00_PA_SC_LINE_CNTL, 2);
1677 radeon_emit(cs, S_028C00_LAST_PIXEL(1) |
1678 S_028C00_EXPAND_LINE_WIDTH(1)); /* R_028C00_PA_SC_LINE_CNTL */
1679 radeon_emit(cs, S_028C04_MSAA_NUM_SAMPLES(util_logbase2(nr_samples)) |
1680 S_028C04_MAX_SAMPLE_DIST(max_dist)); /* R_028C04_PA_SC_AA_CONFIG */
1681 radeon_set_context_reg(cs, R_028A4C_PA_SC_MODE_CNTL_1,
1682 EG_S_028A4C_PS_ITER_SAMPLE(ps_iter_samples > 1) |
1683 EG_S_028A4C_FORCE_EOV_CNTDWN_ENABLE(1) |
1684 EG_S_028A4C_FORCE_EOV_REZ_ENABLE(1));
1685 } else {
1686 radeon_set_context_reg_seq(cs, R_028C00_PA_SC_LINE_CNTL, 2);
1687 radeon_emit(cs, S_028C00_LAST_PIXEL(1)); /* R_028C00_PA_SC_LINE_CNTL */
1688 radeon_emit(cs, 0); /* R_028C04_PA_SC_AA_CONFIG */
1689 radeon_set_context_reg(cs, R_028A4C_PA_SC_MODE_CNTL_1,
1690 EG_S_028A4C_FORCE_EOV_CNTDWN_ENABLE(1) |
1691 EG_S_028A4C_FORCE_EOV_REZ_ENABLE(1));
1692 }
1693 }
1694
1695 static void evergreen_emit_image_state(struct r600_context *rctx, struct r600_atom *atom,
1696 int immed_id_base, int res_id_base, int offset, uint32_t pkt_flags)
1697 {
1698 struct r600_image_state *state = (struct r600_image_state *)atom;
1699 struct pipe_framebuffer_state *fb_state = &rctx->framebuffer.state;
1700 struct radeon_winsys_cs *cs = rctx->b.gfx.cs;
1701 struct r600_texture *rtex;
1702 struct r600_resource *resource;
1703 int i;
1704
1705 for (i = 0; i < R600_MAX_IMAGES; i++) {
1706 struct r600_image_view *image = &state->views[i];
1707 unsigned reloc, immed_reloc;
1708 int idx = i + offset;
1709
1710 if (!pkt_flags)
1711 idx += fb_state->nr_cbufs + (rctx->dual_src_blend ? 1 : 0);
1712 if (!image->base.resource)
1713 continue;
1714
1715 resource = (struct r600_resource *)image->base.resource;
1716 if (resource->b.b.target != PIPE_BUFFER)
1717 rtex = (struct r600_texture *)image->base.resource;
1718 else
1719 rtex = NULL;
1720
1721 reloc = radeon_add_to_buffer_list(&rctx->b,
1722 &rctx->b.gfx,
1723 resource,
1724 RADEON_USAGE_READWRITE,
1725 RADEON_PRIO_SHADER_RW_BUFFER);
1726
1727 immed_reloc = radeon_add_to_buffer_list(&rctx->b,
1728 &rctx->b.gfx,
1729 resource->immed_buffer,
1730 RADEON_USAGE_READWRITE,
1731 RADEON_PRIO_SHADER_RW_BUFFER);
1732
1733 if (pkt_flags)
1734 radeon_compute_set_context_reg_seq(cs, R_028C60_CB_COLOR0_BASE + idx * 0x3C, 13);
1735 else
1736 radeon_set_context_reg_seq(cs, R_028C60_CB_COLOR0_BASE + idx * 0x3C, 13);
1737
1738 radeon_emit(cs, image->cb_color_base); /* R_028C60_CB_COLOR0_BASE */
1739 radeon_emit(cs, image->cb_color_pitch); /* R_028C64_CB_COLOR0_PITCH */
1740 radeon_emit(cs, image->cb_color_slice); /* R_028C68_CB_COLOR0_SLICE */
1741 radeon_emit(cs, image->cb_color_view); /* R_028C6C_CB_COLOR0_VIEW */
1742 radeon_emit(cs, image->cb_color_info); /* R_028C70_CB_COLOR0_INFO */
1743 radeon_emit(cs, image->cb_color_attrib); /* R_028C74_CB_COLOR0_ATTRIB */
1744 radeon_emit(cs, image->cb_color_dim); /* R_028C78_CB_COLOR0_DIM */
1745 radeon_emit(cs, rtex ? rtex->cmask.base_address_reg : image->cb_color_base); /* R_028C7C_CB_COLOR0_CMASK */
1746 radeon_emit(cs, rtex ? rtex->cmask.slice_tile_max : 0); /* R_028C80_CB_COLOR0_CMASK_SLICE */
1747 radeon_emit(cs, image->cb_color_fmask); /* R_028C84_CB_COLOR0_FMASK */
1748 radeon_emit(cs, image->cb_color_fmask_slice); /* R_028C88_CB_COLOR0_FMASK_SLICE */
1749 radeon_emit(cs, rtex ? rtex->color_clear_value[0] : 0); /* R_028C8C_CB_COLOR0_CLEAR_WORD0 */
1750 radeon_emit(cs, rtex ? rtex->color_clear_value[1] : 0); /* R_028C90_CB_COLOR0_CLEAR_WORD1 */
1751
1752 radeon_emit(cs, PKT3(PKT3_NOP, 0, 0)); /* R_028C60_CB_COLOR0_BASE */
1753 radeon_emit(cs, reloc);
1754
1755 radeon_emit(cs, PKT3(PKT3_NOP, 0, 0)); /* R_028C74_CB_COLOR0_ATTRIB */
1756 radeon_emit(cs, reloc);
1757
1758 radeon_emit(cs, PKT3(PKT3_NOP, 0, 0)); /* R_028C7C_CB_COLOR0_CMASK */
1759 radeon_emit(cs, reloc);
1760
1761 radeon_emit(cs, PKT3(PKT3_NOP, 0, 0)); /* R_028C84_CB_COLOR0_FMASK */
1762 radeon_emit(cs, reloc);
1763
1764 if (pkt_flags)
1765 radeon_compute_set_context_reg(cs, R_028B9C_CB_IMMED0_BASE + (idx * 4), resource->immed_buffer->gpu_address >> 8);
1766 else
1767 radeon_set_context_reg(cs, R_028B9C_CB_IMMED0_BASE + (idx * 4), resource->immed_buffer->gpu_address >> 8);
1768
1769 radeon_emit(cs, PKT3(PKT3_NOP, 0, 0)); /**/
1770 radeon_emit(cs, immed_reloc);
1771
1772 radeon_emit(cs, PKT3(PKT3_SET_RESOURCE, 8, 0) | pkt_flags);
1773 radeon_emit(cs, (immed_id_base + i + offset) * 8);
1774 radeon_emit_array(cs, image->immed_resource_words, 8);
1775
1776 radeon_emit(cs, PKT3(PKT3_NOP, 0, 0) | pkt_flags);
1777 radeon_emit(cs, immed_reloc);
1778
1779 radeon_emit(cs, PKT3(PKT3_SET_RESOURCE, 8, 0) | pkt_flags);
1780 radeon_emit(cs, (res_id_base + i + offset) * 8);
1781 radeon_emit_array(cs, image->resource_words, 8);
1782
1783 radeon_emit(cs, PKT3(PKT3_NOP, 0, 0) | pkt_flags);
1784 radeon_emit(cs, reloc);
1785
1786 if (!image->skip_mip_address_reloc) {
1787 radeon_emit(cs, PKT3(PKT3_NOP, 0, 0) | pkt_flags);
1788 radeon_emit(cs, reloc);
1789 }
1790 }
1791 }
1792
1793 static void evergreen_emit_fragment_image_state(struct r600_context *rctx, struct r600_atom *atom)
1794 {
1795 evergreen_emit_image_state(rctx, atom,
1796 R600_IMAGE_IMMED_RESOURCE_OFFSET,
1797 R600_IMAGE_REAL_RESOURCE_OFFSET, 0, 0);
1798 }
1799
1800 static void evergreen_emit_compute_image_state(struct r600_context *rctx, struct r600_atom *atom)
1801 {
1802 evergreen_emit_image_state(rctx, atom,
1803 EG_FETCH_CONSTANTS_OFFSET_CS + R600_IMAGE_IMMED_RESOURCE_OFFSET,
1804 EG_FETCH_CONSTANTS_OFFSET_CS + R600_IMAGE_REAL_RESOURCE_OFFSET,
1805 0, RADEON_CP_PACKET3_COMPUTE_MODE);
1806 }
1807
1808 static void evergreen_emit_fragment_buffer_state(struct r600_context *rctx, struct r600_atom *atom)
1809 {
1810 int offset = util_bitcount(rctx->fragment_images.enabled_mask);
1811 evergreen_emit_image_state(rctx, atom,
1812 R600_IMAGE_IMMED_RESOURCE_OFFSET,
1813 R600_IMAGE_REAL_RESOURCE_OFFSET, offset, 0);
1814 }
1815
1816 static void evergreen_emit_compute_buffer_state(struct r600_context *rctx, struct r600_atom *atom)
1817 {
1818 int offset = util_bitcount(rctx->compute_images.enabled_mask);
1819 evergreen_emit_image_state(rctx, atom,
1820 EG_FETCH_CONSTANTS_OFFSET_CS + R600_IMAGE_IMMED_RESOURCE_OFFSET,
1821 EG_FETCH_CONSTANTS_OFFSET_CS + R600_IMAGE_REAL_RESOURCE_OFFSET,
1822 offset, RADEON_CP_PACKET3_COMPUTE_MODE);
1823 }
1824
1825 static void evergreen_emit_framebuffer_state(struct r600_context *rctx, struct r600_atom *atom)
1826 {
1827 struct radeon_winsys_cs *cs = rctx->b.gfx.cs;
1828 struct pipe_framebuffer_state *state = &rctx->framebuffer.state;
1829 unsigned nr_cbufs = state->nr_cbufs;
1830 unsigned i, tl, br;
1831 struct r600_texture *tex = NULL;
1832 struct r600_surface *cb = NULL;
1833
1834 /* XXX support more colorbuffers once we need them */
1835 assert(nr_cbufs <= 8);
1836 if (nr_cbufs > 8)
1837 nr_cbufs = 8;
1838
1839 /* Colorbuffers. */
1840 for (i = 0; i < nr_cbufs; i++) {
1841 unsigned reloc, cmask_reloc;
1842
1843 cb = (struct r600_surface*)state->cbufs[i];
1844 if (!cb) {
1845 radeon_set_context_reg(cs, R_028C70_CB_COLOR0_INFO + i * 0x3C,
1846 S_028C70_FORMAT(V_028C70_COLOR_INVALID));
1847 continue;
1848 }
1849
1850 tex = (struct r600_texture *)cb->base.texture;
1851 reloc = radeon_add_to_buffer_list(&rctx->b,
1852 &rctx->b.gfx,
1853 (struct r600_resource*)cb->base.texture,
1854 RADEON_USAGE_READWRITE,
1855 tex->resource.b.b.nr_samples > 1 ?
1856 RADEON_PRIO_COLOR_BUFFER_MSAA :
1857 RADEON_PRIO_COLOR_BUFFER);
1858
1859 if (tex->cmask_buffer && tex->cmask_buffer != &tex->resource) {
1860 cmask_reloc = radeon_add_to_buffer_list(&rctx->b, &rctx->b.gfx,
1861 tex->cmask_buffer, RADEON_USAGE_READWRITE,
1862 RADEON_PRIO_CMASK);
1863 } else {
1864 cmask_reloc = reloc;
1865 }
1866
1867 radeon_set_context_reg_seq(cs, R_028C60_CB_COLOR0_BASE + i * 0x3C, 13);
1868 radeon_emit(cs, cb->cb_color_base); /* R_028C60_CB_COLOR0_BASE */
1869 radeon_emit(cs, cb->cb_color_pitch); /* R_028C64_CB_COLOR0_PITCH */
1870 radeon_emit(cs, cb->cb_color_slice); /* R_028C68_CB_COLOR0_SLICE */
1871 radeon_emit(cs, cb->cb_color_view); /* R_028C6C_CB_COLOR0_VIEW */
1872 radeon_emit(cs, cb->cb_color_info | tex->cb_color_info); /* R_028C70_CB_COLOR0_INFO */
1873 radeon_emit(cs, cb->cb_color_attrib); /* R_028C74_CB_COLOR0_ATTRIB */
1874 radeon_emit(cs, cb->cb_color_dim); /* R_028C78_CB_COLOR0_DIM */
1875 radeon_emit(cs, tex->cmask.base_address_reg); /* R_028C7C_CB_COLOR0_CMASK */
1876 radeon_emit(cs, tex->cmask.slice_tile_max); /* R_028C80_CB_COLOR0_CMASK_SLICE */
1877 radeon_emit(cs, cb->cb_color_fmask); /* R_028C84_CB_COLOR0_FMASK */
1878 radeon_emit(cs, cb->cb_color_fmask_slice); /* R_028C88_CB_COLOR0_FMASK_SLICE */
1879 radeon_emit(cs, tex->color_clear_value[0]); /* R_028C8C_CB_COLOR0_CLEAR_WORD0 */
1880 radeon_emit(cs, tex->color_clear_value[1]); /* R_028C90_CB_COLOR0_CLEAR_WORD1 */
1881
1882 radeon_emit(cs, PKT3(PKT3_NOP, 0, 0)); /* R_028C60_CB_COLOR0_BASE */
1883 radeon_emit(cs, reloc);
1884
1885 radeon_emit(cs, PKT3(PKT3_NOP, 0, 0)); /* R_028C74_CB_COLOR0_ATTRIB */
1886 radeon_emit(cs, reloc);
1887
1888 radeon_emit(cs, PKT3(PKT3_NOP, 0, 0)); /* R_028C7C_CB_COLOR0_CMASK */
1889 radeon_emit(cs, cmask_reloc);
1890
1891 radeon_emit(cs, PKT3(PKT3_NOP, 0, 0)); /* R_028C84_CB_COLOR0_FMASK */
1892 radeon_emit(cs, reloc);
1893 }
1894 /* set CB_COLOR1_INFO for possible dual-src blending */
1895 if (rctx->framebuffer.dual_src_blend && i == 1 && state->cbufs[0]) {
1896 radeon_set_context_reg(cs, R_028C70_CB_COLOR0_INFO + 1 * 0x3C,
1897 cb->cb_color_info | tex->cb_color_info);
1898 i++;
1899 }
1900 i += util_bitcount(rctx->fragment_images.enabled_mask);
1901 i += util_bitcount(rctx->fragment_buffers.enabled_mask);
1902 for (; i < 8 ; i++)
1903 radeon_set_context_reg(cs, R_028C70_CB_COLOR0_INFO + i * 0x3C, 0);
1904 for (; i < 12; i++)
1905 radeon_set_context_reg(cs, R_028E50_CB_COLOR8_INFO + (i - 8) * 0x1C, 0);
1906
1907 /* ZS buffer. */
1908 if (state->zsbuf) {
1909 struct r600_surface *zb = (struct r600_surface*)state->zsbuf;
1910 unsigned reloc = radeon_add_to_buffer_list(&rctx->b,
1911 &rctx->b.gfx,
1912 (struct r600_resource*)state->zsbuf->texture,
1913 RADEON_USAGE_READWRITE,
1914 zb->base.texture->nr_samples > 1 ?
1915 RADEON_PRIO_DEPTH_BUFFER_MSAA :
1916 RADEON_PRIO_DEPTH_BUFFER);
1917
1918 radeon_set_context_reg(cs, R_028008_DB_DEPTH_VIEW, zb->db_depth_view);
1919
1920 radeon_set_context_reg_seq(cs, R_028040_DB_Z_INFO, 8);
1921 radeon_emit(cs, zb->db_z_info); /* R_028040_DB_Z_INFO */
1922 radeon_emit(cs, zb->db_stencil_info); /* R_028044_DB_STENCIL_INFO */
1923 radeon_emit(cs, zb->db_depth_base); /* R_028048_DB_Z_READ_BASE */
1924 radeon_emit(cs, zb->db_stencil_base); /* R_02804C_DB_STENCIL_READ_BASE */
1925 radeon_emit(cs, zb->db_depth_base); /* R_028050_DB_Z_WRITE_BASE */
1926 radeon_emit(cs, zb->db_stencil_base); /* R_028054_DB_STENCIL_WRITE_BASE */
1927 radeon_emit(cs, zb->db_depth_size); /* R_028058_DB_DEPTH_SIZE */
1928 radeon_emit(cs, zb->db_depth_slice); /* R_02805C_DB_DEPTH_SLICE */
1929
1930 radeon_emit(cs, PKT3(PKT3_NOP, 0, 0)); /* R_028048_DB_Z_READ_BASE */
1931 radeon_emit(cs, reloc);
1932
1933 radeon_emit(cs, PKT3(PKT3_NOP, 0, 0)); /* R_02804C_DB_STENCIL_READ_BASE */
1934 radeon_emit(cs, reloc);
1935
1936 radeon_emit(cs, PKT3(PKT3_NOP, 0, 0)); /* R_028050_DB_Z_WRITE_BASE */
1937 radeon_emit(cs, reloc);
1938
1939 radeon_emit(cs, PKT3(PKT3_NOP, 0, 0)); /* R_028054_DB_STENCIL_WRITE_BASE */
1940 radeon_emit(cs, reloc);
1941 } else if (rctx->screen->b.info.drm_minor >= 18) {
1942 /* DRM 2.6.18 allows the INVALID format to disable depth/stencil.
1943 * Older kernels are out of luck. */
1944 radeon_set_context_reg_seq(cs, R_028040_DB_Z_INFO, 2);
1945 radeon_emit(cs, S_028040_FORMAT(V_028040_Z_INVALID)); /* R_028040_DB_Z_INFO */
1946 radeon_emit(cs, S_028044_FORMAT(V_028044_STENCIL_INVALID)); /* R_028044_DB_STENCIL_INFO */
1947 }
1948
1949 /* Framebuffer dimensions. */
1950 evergreen_get_scissor_rect(rctx, 0, 0, state->width, state->height, &tl, &br);
1951
1952 radeon_set_context_reg_seq(cs, R_028204_PA_SC_WINDOW_SCISSOR_TL, 2);
1953 radeon_emit(cs, tl); /* R_028204_PA_SC_WINDOW_SCISSOR_TL */
1954 radeon_emit(cs, br); /* R_028208_PA_SC_WINDOW_SCISSOR_BR */
1955
1956 if (rctx->b.chip_class == EVERGREEN) {
1957 evergreen_emit_msaa_state(rctx, rctx->framebuffer.nr_samples, rctx->ps_iter_samples);
1958 } else {
1959 cayman_emit_msaa_state(cs, rctx->framebuffer.nr_samples,
1960 rctx->ps_iter_samples, 0);
1961 }
1962 }
1963
1964 static void evergreen_emit_polygon_offset(struct r600_context *rctx, struct r600_atom *a)
1965 {
1966 struct radeon_winsys_cs *cs = rctx->b.gfx.cs;
1967 struct r600_poly_offset_state *state = (struct r600_poly_offset_state*)a;
1968 float offset_units = state->offset_units;
1969 float offset_scale = state->offset_scale;
1970 uint32_t pa_su_poly_offset_db_fmt_cntl = 0;
1971
1972 if (!state->offset_units_unscaled) {
1973 switch (state->zs_format) {
1974 case PIPE_FORMAT_Z24X8_UNORM:
1975 case PIPE_FORMAT_Z24_UNORM_S8_UINT:
1976 case PIPE_FORMAT_X8Z24_UNORM:
1977 case PIPE_FORMAT_S8_UINT_Z24_UNORM:
1978 offset_units *= 2.0f;
1979 pa_su_poly_offset_db_fmt_cntl =
1980 S_028B78_POLY_OFFSET_NEG_NUM_DB_BITS((char)-24);
1981 break;
1982 case PIPE_FORMAT_Z16_UNORM:
1983 offset_units *= 4.0f;
1984 pa_su_poly_offset_db_fmt_cntl =
1985 S_028B78_POLY_OFFSET_NEG_NUM_DB_BITS((char)-16);
1986 break;
1987 default:
1988 pa_su_poly_offset_db_fmt_cntl =
1989 S_028B78_POLY_OFFSET_NEG_NUM_DB_BITS((char)-23) |
1990 S_028B78_POLY_OFFSET_DB_IS_FLOAT_FMT(1);
1991 }
1992 }
1993
1994 radeon_set_context_reg_seq(cs, R_028B80_PA_SU_POLY_OFFSET_FRONT_SCALE, 4);
1995 radeon_emit(cs, fui(offset_scale));
1996 radeon_emit(cs, fui(offset_units));
1997 radeon_emit(cs, fui(offset_scale));
1998 radeon_emit(cs, fui(offset_units));
1999
2000 radeon_set_context_reg(cs, R_028B78_PA_SU_POLY_OFFSET_DB_FMT_CNTL,
2001 pa_su_poly_offset_db_fmt_cntl);
2002 }
2003
2004 uint32_t evergreen_construct_rat_mask(struct r600_context *rctx, struct r600_cb_misc_state *a,
2005 unsigned nr_cbufs)
2006 {
2007 unsigned base_mask = 0;
2008 unsigned dirty_mask = a->image_rat_enabled_mask;
2009 while (dirty_mask) {
2010 unsigned idx = u_bit_scan(&dirty_mask);
2011 base_mask |= (0xf << (idx * 4));
2012 }
2013 unsigned offset = util_last_bit(a->image_rat_enabled_mask);
2014 dirty_mask = a->buffer_rat_enabled_mask;
2015 while (dirty_mask) {
2016 unsigned idx = u_bit_scan(&dirty_mask);
2017 base_mask |= (0xf << (idx + offset) * 4);
2018 }
2019 return base_mask << (nr_cbufs * 4);
2020 }
2021
2022 static void evergreen_emit_cb_misc_state(struct r600_context *rctx, struct r600_atom *atom)
2023 {
2024 struct radeon_winsys_cs *cs = rctx->b.gfx.cs;
2025 struct r600_cb_misc_state *a = (struct r600_cb_misc_state*)atom;
2026 unsigned fb_colormask = a->bound_cbufs_target_mask;
2027 unsigned ps_colormask = a->ps_color_export_mask;
2028 unsigned rat_colormask = evergreen_construct_rat_mask(rctx, a, a->nr_cbufs);
2029 radeon_set_context_reg_seq(cs, R_028238_CB_TARGET_MASK, 2);
2030 radeon_emit(cs, (a->blend_colormask & fb_colormask) | rat_colormask); /* R_028238_CB_TARGET_MASK */
2031 /* This must match the used export instructions exactly.
2032 * Other values may lead to undefined behavior and hangs.
2033 */
2034 radeon_emit(cs, ps_colormask); /* R_02823C_CB_SHADER_MASK */
2035 }
2036
2037 static void evergreen_emit_db_state(struct r600_context *rctx, struct r600_atom *atom)
2038 {
2039 struct radeon_winsys_cs *cs = rctx->b.gfx.cs;
2040 struct r600_db_state *a = (struct r600_db_state*)atom;
2041
2042 if (a->rsurf && a->rsurf->db_htile_surface) {
2043 struct r600_texture *rtex = (struct r600_texture *)a->rsurf->base.texture;
2044 unsigned reloc_idx;
2045
2046 radeon_set_context_reg(cs, R_02802C_DB_DEPTH_CLEAR, fui(rtex->depth_clear_value));
2047 radeon_set_context_reg(cs, R_028ABC_DB_HTILE_SURFACE, a->rsurf->db_htile_surface);
2048 radeon_set_context_reg(cs, R_028AC8_DB_PRELOAD_CONTROL, a->rsurf->db_preload_control);
2049 radeon_set_context_reg(cs, R_028014_DB_HTILE_DATA_BASE, a->rsurf->db_htile_data_base);
2050 reloc_idx = radeon_add_to_buffer_list(&rctx->b, &rctx->b.gfx, &rtex->resource,
2051 RADEON_USAGE_READWRITE, RADEON_PRIO_HTILE);
2052 radeon_emit(cs, PKT3(PKT3_NOP, 0, 0));
2053 radeon_emit(cs, reloc_idx);
2054 } else {
2055 radeon_set_context_reg(cs, R_028ABC_DB_HTILE_SURFACE, 0);
2056 radeon_set_context_reg(cs, R_028AC8_DB_PRELOAD_CONTROL, 0);
2057 }
2058 }
2059
2060 static void evergreen_emit_db_misc_state(struct r600_context *rctx, struct r600_atom *atom)
2061 {
2062 struct radeon_winsys_cs *cs = rctx->b.gfx.cs;
2063 struct r600_db_misc_state *a = (struct r600_db_misc_state*)atom;
2064 unsigned db_render_control = 0;
2065 unsigned db_count_control = 0;
2066 unsigned db_render_override =
2067 S_02800C_FORCE_HIS_ENABLE0(V_02800C_FORCE_DISABLE) |
2068 S_02800C_FORCE_HIS_ENABLE1(V_02800C_FORCE_DISABLE);
2069
2070 if (rctx->b.num_occlusion_queries > 0 &&
2071 !a->occlusion_queries_disabled) {
2072 db_count_control |= S_028004_PERFECT_ZPASS_COUNTS(1);
2073 if (rctx->b.chip_class == CAYMAN) {
2074 db_count_control |= S_028004_SAMPLE_RATE(a->log_samples);
2075 }
2076 db_render_override |= S_02800C_NOOP_CULL_DISABLE(1);
2077 } else {
2078 db_count_control |= S_028004_ZPASS_INCREMENT_DISABLE(1);
2079 }
2080
2081 /* This is to fix a lockup when hyperz and alpha test are enabled at
2082 * the same time somehow GPU get confuse on which order to pick for
2083 * z test
2084 */
2085 if (rctx->alphatest_state.sx_alpha_test_control)
2086 db_render_override |= S_02800C_FORCE_SHADER_Z_ORDER(1);
2087
2088 if (a->flush_depthstencil_through_cb) {
2089 assert(a->copy_depth || a->copy_stencil);
2090
2091 db_render_control |= S_028000_DEPTH_COPY_ENABLE(a->copy_depth) |
2092 S_028000_STENCIL_COPY_ENABLE(a->copy_stencil) |
2093 S_028000_COPY_CENTROID(1) |
2094 S_028000_COPY_SAMPLE(a->copy_sample);
2095 } else if (a->flush_depth_inplace || a->flush_stencil_inplace) {
2096 db_render_control |= S_028000_DEPTH_COMPRESS_DISABLE(a->flush_depth_inplace) |
2097 S_028000_STENCIL_COMPRESS_DISABLE(a->flush_stencil_inplace);
2098 db_render_override |= S_02800C_DISABLE_PIXEL_RATE_TILES(1);
2099 }
2100 if (a->htile_clear) {
2101 /* FIXME we might want to disable cliprect here */
2102 db_render_control |= S_028000_DEPTH_CLEAR_ENABLE(1);
2103 }
2104
2105 radeon_set_context_reg_seq(cs, R_028000_DB_RENDER_CONTROL, 2);
2106 radeon_emit(cs, db_render_control); /* R_028000_DB_RENDER_CONTROL */
2107 radeon_emit(cs, db_count_control); /* R_028004_DB_COUNT_CONTROL */
2108 radeon_set_context_reg(cs, R_02800C_DB_RENDER_OVERRIDE, db_render_override);
2109 radeon_set_context_reg(cs, R_02880C_DB_SHADER_CONTROL, a->db_shader_control);
2110 }
2111
2112 static void evergreen_emit_vertex_buffers(struct r600_context *rctx,
2113 struct r600_vertexbuf_state *state,
2114 unsigned resource_offset,
2115 unsigned pkt_flags)
2116 {
2117 struct radeon_winsys_cs *cs = rctx->b.gfx.cs;
2118 uint32_t dirty_mask = state->dirty_mask;
2119
2120 while (dirty_mask) {
2121 struct pipe_vertex_buffer *vb;
2122 struct r600_resource *rbuffer;
2123 uint64_t va;
2124 unsigned buffer_index = u_bit_scan(&dirty_mask);
2125
2126 vb = &state->vb[buffer_index];
2127 rbuffer = (struct r600_resource*)vb->buffer.resource;
2128 assert(rbuffer);
2129
2130 va = rbuffer->gpu_address + vb->buffer_offset;
2131
2132 /* fetch resources start at index 992 */
2133 radeon_emit(cs, PKT3(PKT3_SET_RESOURCE, 8, 0) | pkt_flags);
2134 radeon_emit(cs, (resource_offset + buffer_index) * 8);
2135 radeon_emit(cs, va); /* RESOURCEi_WORD0 */
2136 radeon_emit(cs, rbuffer->b.b.width0 - vb->buffer_offset - 1); /* RESOURCEi_WORD1 */
2137 radeon_emit(cs, /* RESOURCEi_WORD2 */
2138 S_030008_ENDIAN_SWAP(r600_endian_swap(32)) |
2139 S_030008_STRIDE(vb->stride) |
2140 S_030008_BASE_ADDRESS_HI(va >> 32UL));
2141 radeon_emit(cs, /* RESOURCEi_WORD3 */
2142 S_03000C_DST_SEL_X(V_03000C_SQ_SEL_X) |
2143 S_03000C_DST_SEL_Y(V_03000C_SQ_SEL_Y) |
2144 S_03000C_DST_SEL_Z(V_03000C_SQ_SEL_Z) |
2145 S_03000C_DST_SEL_W(V_03000C_SQ_SEL_W));
2146 radeon_emit(cs, 0); /* RESOURCEi_WORD4 */
2147 radeon_emit(cs, 0); /* RESOURCEi_WORD5 */
2148 radeon_emit(cs, 0); /* RESOURCEi_WORD6 */
2149 radeon_emit(cs, 0xc0000000); /* RESOURCEi_WORD7 */
2150
2151 radeon_emit(cs, PKT3(PKT3_NOP, 0, 0) | pkt_flags);
2152 radeon_emit(cs, radeon_add_to_buffer_list(&rctx->b, &rctx->b.gfx, rbuffer,
2153 RADEON_USAGE_READ, RADEON_PRIO_VERTEX_BUFFER));
2154 }
2155 state->dirty_mask = 0;
2156 }
2157
2158 static void evergreen_fs_emit_vertex_buffers(struct r600_context *rctx, struct r600_atom * atom)
2159 {
2160 evergreen_emit_vertex_buffers(rctx, &rctx->vertex_buffer_state, EG_FETCH_CONSTANTS_OFFSET_FS, 0);
2161 }
2162
2163 static void evergreen_cs_emit_vertex_buffers(struct r600_context *rctx, struct r600_atom * atom)
2164 {
2165 evergreen_emit_vertex_buffers(rctx, &rctx->cs_vertex_buffer_state, EG_FETCH_CONSTANTS_OFFSET_CS,
2166 RADEON_CP_PACKET3_COMPUTE_MODE);
2167 }
2168
2169 static void evergreen_emit_constant_buffers(struct r600_context *rctx,
2170 struct r600_constbuf_state *state,
2171 unsigned buffer_id_base,
2172 unsigned reg_alu_constbuf_size,
2173 unsigned reg_alu_const_cache,
2174 unsigned pkt_flags)
2175 {
2176 struct radeon_winsys_cs *cs = rctx->b.gfx.cs;
2177 uint32_t dirty_mask = state->dirty_mask;
2178
2179 while (dirty_mask) {
2180 struct pipe_constant_buffer *cb;
2181 struct r600_resource *rbuffer;
2182 uint64_t va;
2183 unsigned buffer_index = ffs(dirty_mask) - 1;
2184 unsigned gs_ring_buffer = (buffer_index == R600_GS_RING_CONST_BUFFER);
2185
2186 cb = &state->cb[buffer_index];
2187 rbuffer = (struct r600_resource*)cb->buffer;
2188 assert(rbuffer);
2189
2190 va = rbuffer->gpu_address + cb->buffer_offset;
2191
2192 if (buffer_index < R600_MAX_HW_CONST_BUFFERS) {
2193 radeon_set_context_reg_flag(cs, reg_alu_constbuf_size + buffer_index * 4,
2194 DIV_ROUND_UP(cb->buffer_size, 256), pkt_flags);
2195 radeon_set_context_reg_flag(cs, reg_alu_const_cache + buffer_index * 4, va >> 8,
2196 pkt_flags);
2197 radeon_emit(cs, PKT3(PKT3_NOP, 0, 0) | pkt_flags);
2198 radeon_emit(cs, radeon_add_to_buffer_list(&rctx->b, &rctx->b.gfx, rbuffer,
2199 RADEON_USAGE_READ, RADEON_PRIO_CONST_BUFFER));
2200 }
2201
2202 radeon_emit(cs, PKT3(PKT3_SET_RESOURCE, 8, 0) | pkt_flags);
2203 radeon_emit(cs, (buffer_id_base + buffer_index) * 8);
2204 radeon_emit(cs, va); /* RESOURCEi_WORD0 */
2205 radeon_emit(cs, cb->buffer_size -1); /* RESOURCEi_WORD1 */
2206 radeon_emit(cs, /* RESOURCEi_WORD2 */
2207 S_030008_ENDIAN_SWAP(gs_ring_buffer ? ENDIAN_NONE : r600_endian_swap(32)) |
2208 S_030008_STRIDE(gs_ring_buffer ? 4 : 16) |
2209 S_030008_BASE_ADDRESS_HI(va >> 32UL) |
2210 S_030008_DATA_FORMAT(FMT_32_32_32_32_FLOAT));
2211 radeon_emit(cs, /* RESOURCEi_WORD3 */
2212 S_03000C_UNCACHED(gs_ring_buffer ? 1 : 0) |
2213 S_03000C_DST_SEL_X(V_03000C_SQ_SEL_X) |
2214 S_03000C_DST_SEL_Y(V_03000C_SQ_SEL_Y) |
2215 S_03000C_DST_SEL_Z(V_03000C_SQ_SEL_Z) |
2216 S_03000C_DST_SEL_W(V_03000C_SQ_SEL_W));
2217 radeon_emit(cs, 0); /* RESOURCEi_WORD4 */
2218 radeon_emit(cs, 0); /* RESOURCEi_WORD5 */
2219 radeon_emit(cs, 0); /* RESOURCEi_WORD6 */
2220 radeon_emit(cs, /* RESOURCEi_WORD7 */
2221 S_03001C_TYPE(V_03001C_SQ_TEX_VTX_VALID_BUFFER));
2222
2223 radeon_emit(cs, PKT3(PKT3_NOP, 0, 0) | pkt_flags);
2224 radeon_emit(cs, radeon_add_to_buffer_list(&rctx->b, &rctx->b.gfx, rbuffer,
2225 RADEON_USAGE_READ, RADEON_PRIO_CONST_BUFFER));
2226
2227 dirty_mask &= ~(1 << buffer_index);
2228 }
2229 state->dirty_mask = 0;
2230 }
2231
2232 /* VS constants can be in VS/ES (same space) or LS if tess is enabled */
2233 static void evergreen_emit_vs_constant_buffers(struct r600_context *rctx, struct r600_atom *atom)
2234 {
2235 if (rctx->vs_shader->current->shader.vs_as_ls) {
2236 evergreen_emit_constant_buffers(rctx, &rctx->constbuf_state[PIPE_SHADER_VERTEX],
2237 EG_FETCH_CONSTANTS_OFFSET_LS,
2238 R_028FC0_ALU_CONST_BUFFER_SIZE_LS_0,
2239 R_028F40_ALU_CONST_CACHE_LS_0,
2240 0 /* PKT3 flags */);
2241 } else {
2242 evergreen_emit_constant_buffers(rctx, &rctx->constbuf_state[PIPE_SHADER_VERTEX],
2243 EG_FETCH_CONSTANTS_OFFSET_VS,
2244 R_028180_ALU_CONST_BUFFER_SIZE_VS_0,
2245 R_028980_ALU_CONST_CACHE_VS_0,
2246 0 /* PKT3 flags */);
2247 }
2248 }
2249
2250 static void evergreen_emit_gs_constant_buffers(struct r600_context *rctx, struct r600_atom *atom)
2251 {
2252 evergreen_emit_constant_buffers(rctx, &rctx->constbuf_state[PIPE_SHADER_GEOMETRY],
2253 EG_FETCH_CONSTANTS_OFFSET_GS,
2254 R_0281C0_ALU_CONST_BUFFER_SIZE_GS_0,
2255 R_0289C0_ALU_CONST_CACHE_GS_0,
2256 0 /* PKT3 flags */);
2257 }
2258
2259 static void evergreen_emit_ps_constant_buffers(struct r600_context *rctx, struct r600_atom *atom)
2260 {
2261 evergreen_emit_constant_buffers(rctx, &rctx->constbuf_state[PIPE_SHADER_FRAGMENT],
2262 EG_FETCH_CONSTANTS_OFFSET_PS,
2263 R_028140_ALU_CONST_BUFFER_SIZE_PS_0,
2264 R_028940_ALU_CONST_CACHE_PS_0,
2265 0 /* PKT3 flags */);
2266 }
2267
2268 static void evergreen_emit_cs_constant_buffers(struct r600_context *rctx, struct r600_atom *atom)
2269 {
2270 evergreen_emit_constant_buffers(rctx, &rctx->constbuf_state[PIPE_SHADER_COMPUTE],
2271 EG_FETCH_CONSTANTS_OFFSET_CS,
2272 R_028FC0_ALU_CONST_BUFFER_SIZE_LS_0,
2273 R_028F40_ALU_CONST_CACHE_LS_0,
2274 RADEON_CP_PACKET3_COMPUTE_MODE);
2275 }
2276
2277 /* tes constants can be emitted to VS or ES - which are common */
2278 static void evergreen_emit_tes_constant_buffers(struct r600_context *rctx, struct r600_atom *atom)
2279 {
2280 if (!rctx->tes_shader)
2281 return;
2282 evergreen_emit_constant_buffers(rctx, &rctx->constbuf_state[PIPE_SHADER_TESS_EVAL],
2283 EG_FETCH_CONSTANTS_OFFSET_VS,
2284 R_028180_ALU_CONST_BUFFER_SIZE_VS_0,
2285 R_028980_ALU_CONST_CACHE_VS_0,
2286 0);
2287 }
2288
2289 static void evergreen_emit_tcs_constant_buffers(struct r600_context *rctx, struct r600_atom *atom)
2290 {
2291 if (!rctx->tes_shader)
2292 return;
2293 evergreen_emit_constant_buffers(rctx, &rctx->constbuf_state[PIPE_SHADER_TESS_CTRL],
2294 EG_FETCH_CONSTANTS_OFFSET_HS,
2295 R_028F80_ALU_CONST_BUFFER_SIZE_HS_0,
2296 R_028F00_ALU_CONST_CACHE_HS_0,
2297 0);
2298 }
2299
2300 void evergreen_setup_scratch_buffers(struct r600_context *rctx) {
2301 static const struct {
2302 unsigned ring_base;
2303 unsigned item_size;
2304 unsigned ring_size;
2305 } regs[EG_NUM_HW_STAGES] = {
2306 [R600_HW_STAGE_PS] = { R_008C68_SQ_PSTMP_RING_BASE, R_028914_SQ_PSTMP_RING_ITEMSIZE, R_008C6C_SQ_PSTMP_RING_SIZE },
2307 [R600_HW_STAGE_VS] = { R_008C60_SQ_VSTMP_RING_BASE, R_028910_SQ_VSTMP_RING_ITEMSIZE, R_008C64_SQ_VSTMP_RING_SIZE },
2308 [R600_HW_STAGE_GS] = { R_008C58_SQ_GSTMP_RING_BASE, R_02890C_SQ_GSTMP_RING_ITEMSIZE, R_008C5C_SQ_GSTMP_RING_SIZE },
2309 [R600_HW_STAGE_ES] = { R_008C50_SQ_ESTMP_RING_BASE, R_028908_SQ_ESTMP_RING_ITEMSIZE, R_008C54_SQ_ESTMP_RING_SIZE },
2310 [EG_HW_STAGE_LS] = { R_008E10_SQ_LSTMP_RING_BASE, R_028830_SQ_LSTMP_RING_ITEMSIZE, R_008E14_SQ_LSTMP_RING_SIZE },
2311 [EG_HW_STAGE_HS] = { R_008E18_SQ_HSTMP_RING_BASE, R_028834_SQ_HSTMP_RING_ITEMSIZE, R_008E1C_SQ_HSTMP_RING_SIZE }
2312 };
2313
2314 for (unsigned i = 0; i < EG_NUM_HW_STAGES; i++) {
2315 struct r600_pipe_shader *stage = rctx->hw_shader_stages[i].shader;
2316
2317 if (stage && unlikely(stage->scratch_space_needed)) {
2318 r600_setup_scratch_area_for_shader(rctx, stage,
2319 &rctx->scratch_buffers[i], regs[i].ring_base, regs[i].item_size, regs[i].ring_size);
2320 }
2321 }
2322 }
2323
2324 static void evergreen_emit_sampler_views(struct r600_context *rctx,
2325 struct r600_samplerview_state *state,
2326 unsigned resource_id_base, unsigned pkt_flags)
2327 {
2328 struct radeon_winsys_cs *cs = rctx->b.gfx.cs;
2329 uint32_t dirty_mask = state->dirty_mask;
2330
2331 while (dirty_mask) {
2332 struct r600_pipe_sampler_view *rview;
2333 unsigned resource_index = u_bit_scan(&dirty_mask);
2334 unsigned reloc;
2335
2336 rview = state->views[resource_index];
2337 assert(rview);
2338
2339 radeon_emit(cs, PKT3(PKT3_SET_RESOURCE, 8, 0) | pkt_flags);
2340 radeon_emit(cs, (resource_id_base + resource_index) * 8);
2341 radeon_emit_array(cs, rview->tex_resource_words, 8);
2342
2343 reloc = radeon_add_to_buffer_list(&rctx->b, &rctx->b.gfx, rview->tex_resource,
2344 RADEON_USAGE_READ,
2345 r600_get_sampler_view_priority(rview->tex_resource));
2346 radeon_emit(cs, PKT3(PKT3_NOP, 0, 0) | pkt_flags);
2347 radeon_emit(cs, reloc);
2348
2349 if (!rview->skip_mip_address_reloc) {
2350 radeon_emit(cs, PKT3(PKT3_NOP, 0, 0) | pkt_flags);
2351 radeon_emit(cs, reloc);
2352 }
2353 }
2354 state->dirty_mask = 0;
2355 }
2356
2357 static void evergreen_emit_vs_sampler_views(struct r600_context *rctx, struct r600_atom *atom)
2358 {
2359 if (rctx->vs_shader->current->shader.vs_as_ls) {
2360 evergreen_emit_sampler_views(rctx, &rctx->samplers[PIPE_SHADER_VERTEX].views,
2361 EG_FETCH_CONSTANTS_OFFSET_LS + R600_MAX_CONST_BUFFERS, 0);
2362 } else {
2363 evergreen_emit_sampler_views(rctx, &rctx->samplers[PIPE_SHADER_VERTEX].views,
2364 EG_FETCH_CONSTANTS_OFFSET_VS + R600_MAX_CONST_BUFFERS, 0);
2365 }
2366 }
2367
2368 static void evergreen_emit_gs_sampler_views(struct r600_context *rctx, struct r600_atom *atom)
2369 {
2370 evergreen_emit_sampler_views(rctx, &rctx->samplers[PIPE_SHADER_GEOMETRY].views,
2371 EG_FETCH_CONSTANTS_OFFSET_GS + R600_MAX_CONST_BUFFERS, 0);
2372 }
2373
2374 static void evergreen_emit_tcs_sampler_views(struct r600_context *rctx, struct r600_atom *atom)
2375 {
2376 evergreen_emit_sampler_views(rctx, &rctx->samplers[PIPE_SHADER_TESS_CTRL].views,
2377 EG_FETCH_CONSTANTS_OFFSET_HS + R600_MAX_CONST_BUFFERS, 0);
2378 }
2379
2380 static void evergreen_emit_tes_sampler_views(struct r600_context *rctx, struct r600_atom *atom)
2381 {
2382 if (!rctx->tes_shader)
2383 return;
2384 evergreen_emit_sampler_views(rctx, &rctx->samplers[PIPE_SHADER_TESS_EVAL].views,
2385 EG_FETCH_CONSTANTS_OFFSET_VS + R600_MAX_CONST_BUFFERS, 0);
2386 }
2387
2388 static void evergreen_emit_ps_sampler_views(struct r600_context *rctx, struct r600_atom *atom)
2389 {
2390 evergreen_emit_sampler_views(rctx, &rctx->samplers[PIPE_SHADER_FRAGMENT].views,
2391 EG_FETCH_CONSTANTS_OFFSET_PS + R600_MAX_CONST_BUFFERS, 0);
2392 }
2393
2394 static void evergreen_emit_cs_sampler_views(struct r600_context *rctx, struct r600_atom *atom)
2395 {
2396 evergreen_emit_sampler_views(rctx, &rctx->samplers[PIPE_SHADER_COMPUTE].views,
2397 EG_FETCH_CONSTANTS_OFFSET_CS + R600_MAX_CONST_BUFFERS, RADEON_CP_PACKET3_COMPUTE_MODE);
2398 }
2399
2400 static void evergreen_emit_sampler_states(struct r600_context *rctx,
2401 struct r600_textures_info *texinfo,
2402 unsigned resource_id_base,
2403 unsigned border_index_reg,
2404 unsigned pkt_flags)
2405 {
2406 struct radeon_winsys_cs *cs = rctx->b.gfx.cs;
2407 uint32_t dirty_mask = texinfo->states.dirty_mask;
2408
2409 while (dirty_mask) {
2410 struct r600_pipe_sampler_state *rstate;
2411 unsigned i = u_bit_scan(&dirty_mask);
2412
2413 rstate = texinfo->states.states[i];
2414 assert(rstate);
2415
2416 radeon_emit(cs, PKT3(PKT3_SET_SAMPLER, 3, 0) | pkt_flags);
2417 radeon_emit(cs, (resource_id_base + i) * 3);
2418 radeon_emit_array(cs, rstate->tex_sampler_words, 3);
2419
2420 if (rstate->border_color_use) {
2421 radeon_set_config_reg_seq(cs, border_index_reg, 5);
2422 radeon_emit(cs, i);
2423 radeon_emit_array(cs, rstate->border_color.ui, 4);
2424 }
2425 }
2426 texinfo->states.dirty_mask = 0;
2427 }
2428
2429 static void evergreen_emit_vs_sampler_states(struct r600_context *rctx, struct r600_atom *atom)
2430 {
2431 if (rctx->vs_shader->current->shader.vs_as_ls) {
2432 evergreen_emit_sampler_states(rctx, &rctx->samplers[PIPE_SHADER_VERTEX], 72,
2433 R_00A450_TD_LS_SAMPLER0_BORDER_COLOR_INDEX, 0);
2434 } else {
2435 evergreen_emit_sampler_states(rctx, &rctx->samplers[PIPE_SHADER_VERTEX], 18,
2436 R_00A414_TD_VS_SAMPLER0_BORDER_INDEX, 0);
2437 }
2438 }
2439
2440 static void evergreen_emit_gs_sampler_states(struct r600_context *rctx, struct r600_atom *atom)
2441 {
2442 evergreen_emit_sampler_states(rctx, &rctx->samplers[PIPE_SHADER_GEOMETRY], 36,
2443 R_00A428_TD_GS_SAMPLER0_BORDER_INDEX, 0);
2444 }
2445
2446 static void evergreen_emit_tcs_sampler_states(struct r600_context *rctx, struct r600_atom *atom)
2447 {
2448 evergreen_emit_sampler_states(rctx, &rctx->samplers[PIPE_SHADER_TESS_CTRL], 54,
2449 R_00A43C_TD_HS_SAMPLER0_BORDER_COLOR_INDEX, 0);
2450 }
2451
2452 static void evergreen_emit_tes_sampler_states(struct r600_context *rctx, struct r600_atom *atom)
2453 {
2454 if (!rctx->tes_shader)
2455 return;
2456 evergreen_emit_sampler_states(rctx, &rctx->samplers[PIPE_SHADER_TESS_EVAL], 18,
2457 R_00A414_TD_VS_SAMPLER0_BORDER_INDEX, 0);
2458 }
2459
2460 static void evergreen_emit_ps_sampler_states(struct r600_context *rctx, struct r600_atom *atom)
2461 {
2462 evergreen_emit_sampler_states(rctx, &rctx->samplers[PIPE_SHADER_FRAGMENT], 0,
2463 R_00A400_TD_PS_SAMPLER0_BORDER_INDEX, 0);
2464 }
2465
2466 static void evergreen_emit_cs_sampler_states(struct r600_context *rctx, struct r600_atom *atom)
2467 {
2468 evergreen_emit_sampler_states(rctx, &rctx->samplers[PIPE_SHADER_COMPUTE], 90,
2469 R_00A464_TD_CS_SAMPLER0_BORDER_INDEX,
2470 RADEON_CP_PACKET3_COMPUTE_MODE);
2471 }
2472
2473 static void evergreen_emit_sample_mask(struct r600_context *rctx, struct r600_atom *a)
2474 {
2475 struct r600_sample_mask *s = (struct r600_sample_mask*)a;
2476 uint8_t mask = s->sample_mask;
2477
2478 radeon_set_context_reg(rctx->b.gfx.cs, R_028C3C_PA_SC_AA_MASK,
2479 mask | (mask << 8) | (mask << 16) | (mask << 24));
2480 }
2481
2482 static void cayman_emit_sample_mask(struct r600_context *rctx, struct r600_atom *a)
2483 {
2484 struct r600_sample_mask *s = (struct r600_sample_mask*)a;
2485 struct radeon_winsys_cs *cs = rctx->b.gfx.cs;
2486 uint16_t mask = s->sample_mask;
2487
2488 radeon_set_context_reg_seq(cs, CM_R_028C38_PA_SC_AA_MASK_X0Y0_X1Y0, 2);
2489 radeon_emit(cs, mask | (mask << 16)); /* X0Y0_X1Y0 */
2490 radeon_emit(cs, mask | (mask << 16)); /* X0Y1_X1Y1 */
2491 }
2492
2493 static void evergreen_emit_vertex_fetch_shader(struct r600_context *rctx, struct r600_atom *a)
2494 {
2495 struct radeon_winsys_cs *cs = rctx->b.gfx.cs;
2496 struct r600_cso_state *state = (struct r600_cso_state*)a;
2497 struct r600_fetch_shader *shader = (struct r600_fetch_shader*)state->cso;
2498
2499 if (!shader)
2500 return;
2501
2502 radeon_set_context_reg(cs, R_0288A4_SQ_PGM_START_FS,
2503 (shader->buffer->gpu_address + shader->offset) >> 8);
2504 radeon_emit(cs, PKT3(PKT3_NOP, 0, 0));
2505 radeon_emit(cs, radeon_add_to_buffer_list(&rctx->b, &rctx->b.gfx, shader->buffer,
2506 RADEON_USAGE_READ,
2507 RADEON_PRIO_SHADER_BINARY));
2508 }
2509
2510 static void evergreen_emit_shader_stages(struct r600_context *rctx, struct r600_atom *a)
2511 {
2512 struct radeon_winsys_cs *cs = rctx->b.gfx.cs;
2513 struct r600_shader_stages_state *state = (struct r600_shader_stages_state*)a;
2514
2515 uint32_t v = 0, v2 = 0, primid = 0, tf_param = 0;
2516
2517 if (rctx->vs_shader->current->shader.vs_as_gs_a) {
2518 v2 = S_028A40_MODE(V_028A40_GS_SCENARIO_A);
2519 primid = 1;
2520 }
2521
2522 if (state->geom_enable) {
2523 uint32_t cut_val;
2524
2525 if (rctx->gs_shader->gs_max_out_vertices <= 128)
2526 cut_val = V_028A40_GS_CUT_128;
2527 else if (rctx->gs_shader->gs_max_out_vertices <= 256)
2528 cut_val = V_028A40_GS_CUT_256;
2529 else if (rctx->gs_shader->gs_max_out_vertices <= 512)
2530 cut_val = V_028A40_GS_CUT_512;
2531 else
2532 cut_val = V_028A40_GS_CUT_1024;
2533
2534 v = S_028B54_GS_EN(1) |
2535 S_028B54_VS_EN(V_028B54_VS_STAGE_COPY_SHADER);
2536 if (!rctx->tes_shader)
2537 v |= S_028B54_ES_EN(V_028B54_ES_STAGE_REAL);
2538
2539 v2 = S_028A40_MODE(V_028A40_GS_SCENARIO_G) |
2540 S_028A40_CUT_MODE(cut_val);
2541
2542 if (rctx->gs_shader->current->shader.gs_prim_id_input)
2543 primid = 1;
2544 }
2545
2546 if (rctx->tes_shader) {
2547 uint32_t type, partitioning, topology;
2548 struct tgsi_shader_info *info = &rctx->tes_shader->current->selector->info;
2549 unsigned tes_prim_mode = info->properties[TGSI_PROPERTY_TES_PRIM_MODE];
2550 unsigned tes_spacing = info->properties[TGSI_PROPERTY_TES_SPACING];
2551 bool tes_vertex_order_cw = info->properties[TGSI_PROPERTY_TES_VERTEX_ORDER_CW];
2552 bool tes_point_mode = info->properties[TGSI_PROPERTY_TES_POINT_MODE];
2553 switch (tes_prim_mode) {
2554 case PIPE_PRIM_LINES:
2555 type = V_028B6C_TESS_ISOLINE;
2556 break;
2557 case PIPE_PRIM_TRIANGLES:
2558 type = V_028B6C_TESS_TRIANGLE;
2559 break;
2560 case PIPE_PRIM_QUADS:
2561 type = V_028B6C_TESS_QUAD;
2562 break;
2563 default:
2564 assert(0);
2565 return;
2566 }
2567
2568 switch (tes_spacing) {
2569 case PIPE_TESS_SPACING_FRACTIONAL_ODD:
2570 partitioning = V_028B6C_PART_FRAC_ODD;
2571 break;
2572 case PIPE_TESS_SPACING_FRACTIONAL_EVEN:
2573 partitioning = V_028B6C_PART_FRAC_EVEN;
2574 break;
2575 case PIPE_TESS_SPACING_EQUAL:
2576 partitioning = V_028B6C_PART_INTEGER;
2577 break;
2578 default:
2579 assert(0);
2580 return;
2581 }
2582
2583 if (tes_point_mode)
2584 topology = V_028B6C_OUTPUT_POINT;
2585 else if (tes_prim_mode == PIPE_PRIM_LINES)
2586 topology = V_028B6C_OUTPUT_LINE;
2587 else if (tes_vertex_order_cw)
2588 /* XXX follow radeonsi and invert */
2589 topology = V_028B6C_OUTPUT_TRIANGLE_CCW;
2590 else
2591 topology = V_028B6C_OUTPUT_TRIANGLE_CW;
2592
2593 tf_param = S_028B6C_TYPE(type) |
2594 S_028B6C_PARTITIONING(partitioning) |
2595 S_028B6C_TOPOLOGY(topology);
2596 }
2597
2598 if (rctx->tes_shader) {
2599 v |= S_028B54_LS_EN(V_028B54_LS_STAGE_ON) |
2600 S_028B54_HS_EN(1);
2601 if (!state->geom_enable)
2602 v |= S_028B54_VS_EN(V_028B54_VS_STAGE_DS);
2603 else
2604 v |= S_028B54_ES_EN(V_028B54_ES_STAGE_DS);
2605 }
2606
2607 radeon_set_context_reg(cs, R_028AB8_VGT_VTX_CNT_EN, v ? 1 : 0 );
2608 radeon_set_context_reg(cs, R_028B54_VGT_SHADER_STAGES_EN, v);
2609 radeon_set_context_reg(cs, R_028A40_VGT_GS_MODE, v2);
2610 radeon_set_context_reg(cs, R_028A84_VGT_PRIMITIVEID_EN, primid);
2611 radeon_set_context_reg(cs, R_028B6C_VGT_TF_PARAM, tf_param);
2612 }
2613
2614 static void evergreen_emit_gs_rings(struct r600_context *rctx, struct r600_atom *a)
2615 {
2616 struct radeon_winsys_cs *cs = rctx->b.gfx.cs;
2617 struct r600_gs_rings_state *state = (struct r600_gs_rings_state*)a;
2618 struct r600_resource *rbuffer;
2619
2620 radeon_set_config_reg(cs, R_008040_WAIT_UNTIL, S_008040_WAIT_3D_IDLE(1));
2621 radeon_emit(cs, PKT3(PKT3_EVENT_WRITE, 0, 0));
2622 radeon_emit(cs, EVENT_TYPE(EVENT_TYPE_VGT_FLUSH));
2623
2624 if (state->enable) {
2625 rbuffer =(struct r600_resource*)state->esgs_ring.buffer;
2626 radeon_set_config_reg(cs, R_008C40_SQ_ESGS_RING_BASE,
2627 rbuffer->gpu_address >> 8);
2628 radeon_emit(cs, PKT3(PKT3_NOP, 0, 0));
2629 radeon_emit(cs, radeon_add_to_buffer_list(&rctx->b, &rctx->b.gfx, rbuffer,
2630 RADEON_USAGE_READWRITE,
2631 RADEON_PRIO_SHADER_RINGS));
2632 radeon_set_config_reg(cs, R_008C44_SQ_ESGS_RING_SIZE,
2633 state->esgs_ring.buffer_size >> 8);
2634
2635 rbuffer =(struct r600_resource*)state->gsvs_ring.buffer;
2636 radeon_set_config_reg(cs, R_008C48_SQ_GSVS_RING_BASE,
2637 rbuffer->gpu_address >> 8);
2638 radeon_emit(cs, PKT3(PKT3_NOP, 0, 0));
2639 radeon_emit(cs, radeon_add_to_buffer_list(&rctx->b, &rctx->b.gfx, rbuffer,
2640 RADEON_USAGE_READWRITE,
2641 RADEON_PRIO_SHADER_RINGS));
2642 radeon_set_config_reg(cs, R_008C4C_SQ_GSVS_RING_SIZE,
2643 state->gsvs_ring.buffer_size >> 8);
2644 } else {
2645 radeon_set_config_reg(cs, R_008C44_SQ_ESGS_RING_SIZE, 0);
2646 radeon_set_config_reg(cs, R_008C4C_SQ_GSVS_RING_SIZE, 0);
2647 }
2648
2649 radeon_set_config_reg(cs, R_008040_WAIT_UNTIL, S_008040_WAIT_3D_IDLE(1));
2650 radeon_emit(cs, PKT3(PKT3_EVENT_WRITE, 0, 0));
2651 radeon_emit(cs, EVENT_TYPE(EVENT_TYPE_VGT_FLUSH));
2652 }
2653
2654 void cayman_init_common_regs(struct r600_command_buffer *cb,
2655 enum chip_class ctx_chip_class,
2656 enum radeon_family ctx_family,
2657 int ctx_drm_minor)
2658 {
2659 r600_store_config_reg_seq(cb, R_008C00_SQ_CONFIG, 2);
2660 r600_store_value(cb, S_008C00_EXPORT_SRC_C(1)); /* R_008C00_SQ_CONFIG */
2661 /* always set the temp clauses */
2662 r600_store_value(cb, S_008C04_NUM_CLAUSE_TEMP_GPRS(4)); /* R_008C04_SQ_GPR_RESOURCE_MGMT_1 */
2663
2664 r600_store_config_reg_seq(cb, R_008C10_SQ_GLOBAL_GPR_RESOURCE_MGMT_1, 2);
2665 r600_store_value(cb, 0); /* R_008C10_SQ_GLOBAL_GPR_RESOURCE_MGMT_1 */
2666 r600_store_value(cb, 0); /* R_008C14_SQ_GLOBAL_GPR_RESOURCE_MGMT_2 */
2667
2668 r600_store_config_reg(cb, R_008D8C_SQ_DYN_GPR_CNTL_PS_FLUSH_REQ, (1 << 8));
2669
2670 r600_store_context_reg_seq(cb, R_028350_SX_MISC, 2);
2671 r600_store_value(cb, 0);
2672 r600_store_value(cb, S_028354_SURFACE_SYNC_MASK(0xf));
2673
2674 r600_store_context_reg(cb, R_028800_DB_DEPTH_CONTROL, 0);
2675 }
2676
2677 static void cayman_init_atom_start_cs(struct r600_context *rctx)
2678 {
2679 struct r600_command_buffer *cb = &rctx->start_cs_cmd;
2680 int i;
2681
2682 r600_init_command_buffer(cb, 338);
2683
2684 /* This must be first. */
2685 r600_store_value(cb, PKT3(PKT3_CONTEXT_CONTROL, 1, 0));
2686 r600_store_value(cb, 0x80000000);
2687 r600_store_value(cb, 0x80000000);
2688
2689 /* We're setting config registers here. */
2690 r600_store_value(cb, PKT3(PKT3_EVENT_WRITE, 0, 0));
2691 r600_store_value(cb, EVENT_TYPE(EVENT_TYPE_PS_PARTIAL_FLUSH) | EVENT_INDEX(4));
2692
2693 /* This enables pipeline stat & streamout queries.
2694 * They are only disabled by blits.
2695 */
2696 r600_store_value(cb, PKT3(PKT3_EVENT_WRITE, 0, 0));
2697 r600_store_value(cb, EVENT_TYPE(EVENT_TYPE_PIPELINESTAT_START) | EVENT_INDEX(0));
2698
2699 cayman_init_common_regs(cb, rctx->b.chip_class,
2700 rctx->b.family, rctx->screen->b.info.drm_minor);
2701
2702 r600_store_config_reg(cb, R_009100_SPI_CONFIG_CNTL, 0);
2703 r600_store_config_reg(cb, R_00913C_SPI_CONFIG_CNTL_1, S_00913C_VTX_DONE_DELAY(4));
2704
2705 /* remove LS/HS from one SIMD for hw workaround */
2706 r600_store_config_reg_seq(cb, R_008E20_SQ_STATIC_THREAD_MGMT1, 3);
2707 r600_store_value(cb, 0xffffffff);
2708 r600_store_value(cb, 0xffffffff);
2709 r600_store_value(cb, 0xfffffffe);
2710
2711 r600_store_context_reg_seq(cb, R_028900_SQ_ESGS_RING_ITEMSIZE, 6);
2712 r600_store_value(cb, 0); /* R_028900_SQ_ESGS_RING_ITEMSIZE */
2713 r600_store_value(cb, 0); /* R_028904_SQ_GSVS_RING_ITEMSIZE */
2714 r600_store_value(cb, 0); /* R_028908_SQ_ESTMP_RING_ITEMSIZE */
2715 r600_store_value(cb, 0); /* R_02890C_SQ_GSTMP_RING_ITEMSIZE */
2716 r600_store_value(cb, 0); /* R_028910_SQ_VSTMP_RING_ITEMSIZE */
2717 r600_store_value(cb, 0); /* R_028914_SQ_PSTMP_RING_ITEMSIZE */
2718
2719 r600_store_context_reg_seq(cb, R_02891C_SQ_GS_VERT_ITEMSIZE, 4);
2720 r600_store_value(cb, 0); /* R_02891C_SQ_GS_VERT_ITEMSIZE */
2721 r600_store_value(cb, 0); /* R_028920_SQ_GS_VERT_ITEMSIZE_1 */
2722 r600_store_value(cb, 0); /* R_028924_SQ_GS_VERT_ITEMSIZE_2 */
2723 r600_store_value(cb, 0); /* R_028928_SQ_GS_VERT_ITEMSIZE_3 */
2724
2725 r600_store_context_reg_seq(cb, R_028A10_VGT_OUTPUT_PATH_CNTL, 13);
2726 r600_store_value(cb, 0); /* R_028A10_VGT_OUTPUT_PATH_CNTL */
2727 r600_store_value(cb, 0); /* R_028A14_VGT_HOS_CNTL */
2728 r600_store_value(cb, fui(64)); /* R_028A18_VGT_HOS_MAX_TESS_LEVEL */
2729 r600_store_value(cb, fui(0)); /* R_028A1C_VGT_HOS_MIN_TESS_LEVEL */
2730 r600_store_value(cb, 16); /* R_028A20_VGT_HOS_REUSE_DEPTH */
2731 r600_store_value(cb, 0); /* R_028A24_VGT_GROUP_PRIM_TYPE */
2732 r600_store_value(cb, 0); /* R_028A28_VGT_GROUP_FIRST_DECR */
2733 r600_store_value(cb, 0); /* R_028A2C_VGT_GROUP_DECR */
2734 r600_store_value(cb, 0); /* R_028A30_VGT_GROUP_VECT_0_CNTL */
2735 r600_store_value(cb, 0); /* R_028A34_VGT_GROUP_VECT_1_CNTL */
2736 r600_store_value(cb, 0); /* R_028A38_VGT_GROUP_VECT_0_FMT_CNTL */
2737 r600_store_value(cb, 0); /* R_028A3C_VGT_GROUP_VECT_1_FMT_CNTL */
2738 r600_store_value(cb, 0); /* R_028A40_VGT_GS_MODE */
2739
2740 r600_store_context_reg(cb, R_028B98_VGT_STRMOUT_BUFFER_CONFIG, 0);
2741
2742 r600_store_config_reg(cb, R_008A14_PA_CL_ENHANCE, (3 << 1) | 1);
2743
2744 r600_store_context_reg_seq(cb, CM_R_028BD4_PA_SC_CENTROID_PRIORITY_0, 2);
2745 r600_store_value(cb, 0x76543210); /* CM_R_028BD4_PA_SC_CENTROID_PRIORITY_0 */
2746 r600_store_value(cb, 0xfedcba98); /* CM_R_028BD8_PA_SC_CENTROID_PRIORITY_1 */
2747
2748 r600_store_context_reg(cb, R_028724_GDS_ADDR_SIZE, 0x3fff);
2749 r600_store_context_reg_seq(cb, R_0288E8_SQ_LDS_ALLOC, 2);
2750 r600_store_value(cb, 0); /* R_0288E8_SQ_LDS_ALLOC */
2751 r600_store_value(cb, 0); /* R_0288EC_SQ_LDS_ALLOC_PS */
2752
2753 r600_store_context_reg(cb, R_0288F0_SQ_VTX_SEMANTIC_CLEAR, ~0);
2754
2755 r600_store_context_reg_seq(cb, R_028400_VGT_MAX_VTX_INDX, 2);
2756 r600_store_value(cb, ~0); /* R_028400_VGT_MAX_VTX_INDX */
2757 r600_store_value(cb, 0); /* R_028404_VGT_MIN_VTX_INDX */
2758
2759 r600_store_ctl_const(cb, R_03CFF0_SQ_VTX_BASE_VTX_LOC, 0);
2760
2761 r600_store_context_reg(cb, R_028028_DB_STENCIL_CLEAR, 0);
2762
2763 r600_store_context_reg(cb, R_0286DC_SPI_FOG_CNTL, 0);
2764
2765 r600_store_context_reg_seq(cb, R_028AC0_DB_SRESULTS_COMPARE_STATE0, 3);
2766 r600_store_value(cb, 0); /* R_028AC0_DB_SRESULTS_COMPARE_STATE0 */
2767 r600_store_value(cb, 0); /* R_028AC4_DB_SRESULTS_COMPARE_STATE1 */
2768 r600_store_value(cb, 0); /* R_028AC8_DB_PRELOAD_CONTROL */
2769
2770 r600_store_context_reg(cb, R_028200_PA_SC_WINDOW_OFFSET, 0);
2771 r600_store_context_reg(cb, R_02820C_PA_SC_CLIPRECT_RULE, 0xFFFF);
2772
2773 r600_store_context_reg(cb, R_028230_PA_SC_EDGERULE, 0xAAAAAAAA);
2774 r600_store_context_reg(cb, R_028820_PA_CL_NANINF_CNTL, 0);
2775
2776 r600_store_context_reg_seq(cb, R_028240_PA_SC_GENERIC_SCISSOR_TL, 2);
2777 r600_store_value(cb, 0); /* R_028240_PA_SC_GENERIC_SCISSOR_TL */
2778 r600_store_value(cb, S_028244_BR_X(16384) | S_028244_BR_Y(16384)); /* R_028244_PA_SC_GENERIC_SCISSOR_BR */
2779
2780 r600_store_context_reg_seq(cb, R_028030_PA_SC_SCREEN_SCISSOR_TL, 2);
2781 r600_store_value(cb, 0); /* R_028030_PA_SC_SCREEN_SCISSOR_TL */
2782 r600_store_value(cb, S_028034_BR_X(16384) | S_028034_BR_Y(16384)); /* R_028034_PA_SC_SCREEN_SCISSOR_BR */
2783
2784 r600_store_context_reg(cb, R_028848_SQ_PGM_RESOURCES_2_PS, S_028848_SINGLE_ROUND(V_SQ_ROUND_NEAREST_EVEN));
2785 r600_store_context_reg(cb, R_028864_SQ_PGM_RESOURCES_2_VS, S_028864_SINGLE_ROUND(V_SQ_ROUND_NEAREST_EVEN));
2786 r600_store_context_reg(cb, R_02887C_SQ_PGM_RESOURCES_2_GS, S_028848_SINGLE_ROUND(V_SQ_ROUND_NEAREST_EVEN));
2787 r600_store_context_reg(cb, R_028894_SQ_PGM_RESOURCES_2_ES, S_028848_SINGLE_ROUND(V_SQ_ROUND_NEAREST_EVEN));
2788 r600_store_context_reg(cb, R_0288C0_SQ_PGM_RESOURCES_2_HS, S_028848_SINGLE_ROUND(V_SQ_ROUND_NEAREST_EVEN));
2789 r600_store_context_reg(cb, R_0288D8_SQ_PGM_RESOURCES_2_LS, S_028848_SINGLE_ROUND(V_SQ_ROUND_NEAREST_EVEN));
2790
2791 r600_store_context_reg(cb, R_0288A8_SQ_PGM_RESOURCES_FS, 0);
2792
2793 /* to avoid GPU doing any preloading of constant from random address */
2794 r600_store_context_reg_seq(cb, R_028140_ALU_CONST_BUFFER_SIZE_PS_0, 16);
2795 for (i = 0; i < 16; i++)
2796 r600_store_value(cb, 0);
2797
2798 r600_store_context_reg_seq(cb, R_028180_ALU_CONST_BUFFER_SIZE_VS_0, 16);
2799 for (i = 0; i < 16; i++)
2800 r600_store_value(cb, 0);
2801
2802 r600_store_context_reg_seq(cb, R_0281C0_ALU_CONST_BUFFER_SIZE_GS_0, 16);
2803 for (i = 0; i < 16; i++)
2804 r600_store_value(cb, 0);
2805
2806 r600_store_context_reg_seq(cb, R_028FC0_ALU_CONST_BUFFER_SIZE_LS_0, 16);
2807 for (i = 0; i < 16; i++)
2808 r600_store_value(cb, 0);
2809
2810 r600_store_context_reg_seq(cb, R_028F80_ALU_CONST_BUFFER_SIZE_HS_0, 16);
2811 for (i = 0; i < 16; i++)
2812 r600_store_value(cb, 0);
2813
2814 if (rctx->screen->b.has_streamout) {
2815 r600_store_context_reg(cb, R_028B28_VGT_STRMOUT_DRAW_OPAQUE_OFFSET, 0);
2816 }
2817
2818 r600_store_context_reg(cb, R_028010_DB_RENDER_OVERRIDE2, 0);
2819 r600_store_context_reg(cb, R_028234_PA_SU_HARDWARE_SCREEN_OFFSET, 0);
2820 r600_store_context_reg(cb, R_0286C8_SPI_THREAD_GROUPING, 0);
2821 r600_store_context_reg_seq(cb, R_0286E4_SPI_PS_IN_CONTROL_2, 2);
2822 r600_store_value(cb, 0); /* R_0286E4_SPI_PS_IN_CONTROL_2 */
2823 r600_store_value(cb, 0); /* R_0286E8_SPI_COMPUTE_INPUT_CNTL */
2824
2825 r600_store_context_reg_seq(cb, R_028B54_VGT_SHADER_STAGES_EN, 2);
2826 r600_store_value(cb, 0); /* R028B54_VGT_SHADER_STAGES_EN */
2827 r600_store_value(cb, 0); /* R028B58_VGT_LS_HS_CONFIG */
2828 r600_store_context_reg(cb, R_028B6C_VGT_TF_PARAM, 0);
2829 eg_store_loop_const(cb, R_03A200_SQ_LOOP_CONST_0, 0x01000FFF);
2830 eg_store_loop_const(cb, R_03A200_SQ_LOOP_CONST_0 + (32 * 4), 0x01000FFF);
2831 eg_store_loop_const(cb, R_03A200_SQ_LOOP_CONST_0 + (64 * 4), 0x01000FFF);
2832 eg_store_loop_const(cb, R_03A200_SQ_LOOP_CONST_0 + (96 * 4), 0x01000FFF);
2833 eg_store_loop_const(cb, R_03A200_SQ_LOOP_CONST_0 + (128 * 4), 0x01000FFF);
2834 }
2835
2836 void evergreen_init_common_regs(struct r600_context *rctx, struct r600_command_buffer *cb,
2837 enum chip_class ctx_chip_class,
2838 enum radeon_family ctx_family,
2839 int ctx_drm_minor)
2840 {
2841 int ps_prio;
2842 int vs_prio;
2843 int gs_prio;
2844 int es_prio;
2845
2846 int hs_prio;
2847 int cs_prio;
2848 int ls_prio;
2849
2850 unsigned tmp;
2851
2852 ps_prio = 0;
2853 vs_prio = 1;
2854 gs_prio = 2;
2855 es_prio = 3;
2856 hs_prio = 3;
2857 ls_prio = 3;
2858 cs_prio = 0;
2859
2860 rctx->default_gprs[R600_HW_STAGE_PS] = 93;
2861 rctx->default_gprs[R600_HW_STAGE_VS] = 46;
2862 rctx->r6xx_num_clause_temp_gprs = 4;
2863 rctx->default_gprs[R600_HW_STAGE_GS] = 31;
2864 rctx->default_gprs[R600_HW_STAGE_ES] = 31;
2865 rctx->default_gprs[EG_HW_STAGE_HS] = 23;
2866 rctx->default_gprs[EG_HW_STAGE_LS] = 23;
2867
2868 tmp = 0;
2869 switch (ctx_family) {
2870 case CHIP_CEDAR:
2871 case CHIP_PALM:
2872 case CHIP_SUMO:
2873 case CHIP_SUMO2:
2874 case CHIP_CAICOS:
2875 break;
2876 default:
2877 tmp |= S_008C00_VC_ENABLE(1);
2878 break;
2879 }
2880 tmp |= S_008C00_EXPORT_SRC_C(1);
2881 tmp |= S_008C00_CS_PRIO(cs_prio);
2882 tmp |= S_008C00_LS_PRIO(ls_prio);
2883 tmp |= S_008C00_HS_PRIO(hs_prio);
2884 tmp |= S_008C00_PS_PRIO(ps_prio);
2885 tmp |= S_008C00_VS_PRIO(vs_prio);
2886 tmp |= S_008C00_GS_PRIO(gs_prio);
2887 tmp |= S_008C00_ES_PRIO(es_prio);
2888
2889 r600_store_config_reg_seq(cb, R_008C00_SQ_CONFIG, 1);
2890 r600_store_value(cb, tmp); /* R_008C00_SQ_CONFIG */
2891
2892 r600_store_config_reg_seq(cb, R_008C10_SQ_GLOBAL_GPR_RESOURCE_MGMT_1, 2);
2893 r600_store_value(cb, 0); /* R_008C10_SQ_GLOBAL_GPR_RESOURCE_MGMT_1 */
2894 r600_store_value(cb, 0); /* R_008C14_SQ_GLOBAL_GPR_RESOURCE_MGMT_2 */
2895
2896 /* The cs checker requires this register to be set. */
2897 r600_store_context_reg(cb, R_028800_DB_DEPTH_CONTROL, 0);
2898
2899 r600_store_context_reg_seq(cb, R_028350_SX_MISC, 2);
2900 r600_store_value(cb, 0);
2901 r600_store_value(cb, S_028354_SURFACE_SYNC_MASK(0xf));
2902
2903 return;
2904 }
2905
2906 void evergreen_init_atom_start_cs(struct r600_context *rctx)
2907 {
2908 struct r600_command_buffer *cb = &rctx->start_cs_cmd;
2909 int num_ps_threads;
2910 int num_vs_threads;
2911 int num_gs_threads;
2912 int num_es_threads;
2913 int num_hs_threads;
2914 int num_ls_threads;
2915
2916 int num_ps_stack_entries;
2917 int num_vs_stack_entries;
2918 int num_gs_stack_entries;
2919 int num_es_stack_entries;
2920 int num_hs_stack_entries;
2921 int num_ls_stack_entries;
2922 enum radeon_family family;
2923 unsigned tmp, i;
2924
2925 if (rctx->b.chip_class == CAYMAN) {
2926 cayman_init_atom_start_cs(rctx);
2927 return;
2928 }
2929
2930 r600_init_command_buffer(cb, 338);
2931
2932 /* This must be first. */
2933 r600_store_value(cb, PKT3(PKT3_CONTEXT_CONTROL, 1, 0));
2934 r600_store_value(cb, 0x80000000);
2935 r600_store_value(cb, 0x80000000);
2936
2937 /* We're setting config registers here. */
2938 r600_store_value(cb, PKT3(PKT3_EVENT_WRITE, 0, 0));
2939 r600_store_value(cb, EVENT_TYPE(EVENT_TYPE_PS_PARTIAL_FLUSH) | EVENT_INDEX(4));
2940
2941 /* This enables pipeline stat & streamout queries.
2942 * They are only disabled by blits.
2943 */
2944 r600_store_value(cb, PKT3(PKT3_EVENT_WRITE, 0, 0));
2945 r600_store_value(cb, EVENT_TYPE(EVENT_TYPE_PIPELINESTAT_START) | EVENT_INDEX(0));
2946
2947 evergreen_init_common_regs(rctx, cb, rctx->b.chip_class,
2948 rctx->b.family, rctx->screen->b.info.drm_minor);
2949
2950 family = rctx->b.family;
2951 switch (family) {
2952 case CHIP_CEDAR:
2953 default:
2954 num_ps_threads = 96;
2955 num_vs_threads = 16;
2956 num_gs_threads = 16;
2957 num_es_threads = 16;
2958 num_hs_threads = 16;
2959 num_ls_threads = 16;
2960 num_ps_stack_entries = 42;
2961 num_vs_stack_entries = 42;
2962 num_gs_stack_entries = 42;
2963 num_es_stack_entries = 42;
2964 num_hs_stack_entries = 42;
2965 num_ls_stack_entries = 42;
2966 break;
2967 case CHIP_REDWOOD:
2968 num_ps_threads = 128;
2969 num_vs_threads = 20;
2970 num_gs_threads = 20;
2971 num_es_threads = 20;
2972 num_hs_threads = 20;
2973 num_ls_threads = 20;
2974 num_ps_stack_entries = 42;
2975 num_vs_stack_entries = 42;
2976 num_gs_stack_entries = 42;
2977 num_es_stack_entries = 42;
2978 num_hs_stack_entries = 42;
2979 num_ls_stack_entries = 42;
2980 break;
2981 case CHIP_JUNIPER:
2982 num_ps_threads = 128;
2983 num_vs_threads = 20;
2984 num_gs_threads = 20;
2985 num_es_threads = 20;
2986 num_hs_threads = 20;
2987 num_ls_threads = 20;
2988 num_ps_stack_entries = 85;
2989 num_vs_stack_entries = 85;
2990 num_gs_stack_entries = 85;
2991 num_es_stack_entries = 85;
2992 num_hs_stack_entries = 85;
2993 num_ls_stack_entries = 85;
2994 break;
2995 case CHIP_CYPRESS:
2996 case CHIP_HEMLOCK:
2997 num_ps_threads = 128;
2998 num_vs_threads = 20;
2999 num_gs_threads = 20;
3000 num_es_threads = 20;
3001 num_hs_threads = 20;
3002 num_ls_threads = 20;
3003 num_ps_stack_entries = 85;
3004 num_vs_stack_entries = 85;
3005 num_gs_stack_entries = 85;
3006 num_es_stack_entries = 85;
3007 num_hs_stack_entries = 85;
3008 num_ls_stack_entries = 85;
3009 break;
3010 case CHIP_PALM:
3011 num_ps_threads = 96;
3012 num_vs_threads = 16;
3013 num_gs_threads = 16;
3014 num_es_threads = 16;
3015 num_hs_threads = 16;
3016 num_ls_threads = 16;
3017 num_ps_stack_entries = 42;
3018 num_vs_stack_entries = 42;
3019 num_gs_stack_entries = 42;
3020 num_es_stack_entries = 42;
3021 num_hs_stack_entries = 42;
3022 num_ls_stack_entries = 42;
3023 break;
3024 case CHIP_SUMO:
3025 num_ps_threads = 96;
3026 num_vs_threads = 25;
3027 num_gs_threads = 25;
3028 num_es_threads = 25;
3029 num_hs_threads = 16;
3030 num_ls_threads = 16;
3031 num_ps_stack_entries = 42;
3032 num_vs_stack_entries = 42;
3033 num_gs_stack_entries = 42;
3034 num_es_stack_entries = 42;
3035 num_hs_stack_entries = 42;
3036 num_ls_stack_entries = 42;
3037 break;
3038 case CHIP_SUMO2:
3039 num_ps_threads = 96;
3040 num_vs_threads = 25;
3041 num_gs_threads = 25;
3042 num_es_threads = 25;
3043 num_hs_threads = 16;
3044 num_ls_threads = 16;
3045 num_ps_stack_entries = 85;
3046 num_vs_stack_entries = 85;
3047 num_gs_stack_entries = 85;
3048 num_es_stack_entries = 85;
3049 num_hs_stack_entries = 85;
3050 num_ls_stack_entries = 85;
3051 break;
3052 case CHIP_BARTS:
3053 num_ps_threads = 128;
3054 num_vs_threads = 20;
3055 num_gs_threads = 20;
3056 num_es_threads = 20;
3057 num_hs_threads = 20;
3058 num_ls_threads = 20;
3059 num_ps_stack_entries = 85;
3060 num_vs_stack_entries = 85;
3061 num_gs_stack_entries = 85;
3062 num_es_stack_entries = 85;
3063 num_hs_stack_entries = 85;
3064 num_ls_stack_entries = 85;
3065 break;
3066 case CHIP_TURKS:
3067 num_ps_threads = 128;
3068 num_vs_threads = 20;
3069 num_gs_threads = 20;
3070 num_es_threads = 20;
3071 num_hs_threads = 20;
3072 num_ls_threads = 20;
3073 num_ps_stack_entries = 42;
3074 num_vs_stack_entries = 42;
3075 num_gs_stack_entries = 42;
3076 num_es_stack_entries = 42;
3077 num_hs_stack_entries = 42;
3078 num_ls_stack_entries = 42;
3079 break;
3080 case CHIP_CAICOS:
3081 num_ps_threads = 96;
3082 num_vs_threads = 10;
3083 num_gs_threads = 10;
3084 num_es_threads = 10;
3085 num_hs_threads = 10;
3086 num_ls_threads = 10;
3087 num_ps_stack_entries = 42;
3088 num_vs_stack_entries = 42;
3089 num_gs_stack_entries = 42;
3090 num_es_stack_entries = 42;
3091 num_hs_stack_entries = 42;
3092 num_ls_stack_entries = 42;
3093 break;
3094 }
3095
3096 tmp = S_008C18_NUM_PS_THREADS(num_ps_threads);
3097 tmp |= S_008C18_NUM_VS_THREADS(num_vs_threads);
3098 tmp |= S_008C18_NUM_GS_THREADS(num_gs_threads);
3099 tmp |= S_008C18_NUM_ES_THREADS(num_es_threads);
3100
3101 r600_store_config_reg_seq(cb, R_008C18_SQ_THREAD_RESOURCE_MGMT_1, 5);
3102 r600_store_value(cb, tmp); /* R_008C18_SQ_THREAD_RESOURCE_MGMT_1 */
3103
3104 tmp = S_008C1C_NUM_HS_THREADS(num_hs_threads);
3105 tmp |= S_008C1C_NUM_LS_THREADS(num_ls_threads);
3106 r600_store_value(cb, tmp); /* R_008C1C_SQ_THREAD_RESOURCE_MGMT_2 */
3107
3108 tmp = S_008C20_NUM_PS_STACK_ENTRIES(num_ps_stack_entries);
3109 tmp |= S_008C20_NUM_VS_STACK_ENTRIES(num_vs_stack_entries);
3110 r600_store_value(cb, tmp); /* R_008C20_SQ_STACK_RESOURCE_MGMT_1 */
3111
3112 tmp = S_008C24_NUM_GS_STACK_ENTRIES(num_gs_stack_entries);
3113 tmp |= S_008C24_NUM_ES_STACK_ENTRIES(num_es_stack_entries);
3114 r600_store_value(cb, tmp); /* R_008C24_SQ_STACK_RESOURCE_MGMT_2 */
3115
3116 tmp = S_008C28_NUM_HS_STACK_ENTRIES(num_hs_stack_entries);
3117 tmp |= S_008C28_NUM_LS_STACK_ENTRIES(num_ls_stack_entries);
3118 r600_store_value(cb, tmp); /* R_008C28_SQ_STACK_RESOURCE_MGMT_3 */
3119
3120 r600_store_config_reg(cb, R_008E2C_SQ_LDS_RESOURCE_MGMT,
3121 S_008E2C_NUM_PS_LDS(0x1000) | S_008E2C_NUM_LS_LDS(0x1000));
3122
3123 /* remove LS/HS from one SIMD for hw workaround */
3124 r600_store_config_reg_seq(cb, R_008E20_SQ_STATIC_THREAD_MGMT1, 3);
3125 r600_store_value(cb, 0xffffffff);
3126 r600_store_value(cb, 0xffffffff);
3127 r600_store_value(cb, 0xfffffffe);
3128
3129 r600_store_config_reg(cb, R_009100_SPI_CONFIG_CNTL, 0);
3130 r600_store_config_reg(cb, R_00913C_SPI_CONFIG_CNTL_1, S_00913C_VTX_DONE_DELAY(4));
3131
3132 r600_store_context_reg_seq(cb, R_028900_SQ_ESGS_RING_ITEMSIZE, 6);
3133 r600_store_value(cb, 0); /* R_028900_SQ_ESGS_RING_ITEMSIZE */
3134 r600_store_value(cb, 0); /* R_028904_SQ_GSVS_RING_ITEMSIZE */
3135 r600_store_value(cb, 0); /* R_028908_SQ_ESTMP_RING_ITEMSIZE */
3136 r600_store_value(cb, 0); /* R_02890C_SQ_GSTMP_RING_ITEMSIZE */
3137 r600_store_value(cb, 0); /* R_028910_SQ_VSTMP_RING_ITEMSIZE */
3138 r600_store_value(cb, 0); /* R_028914_SQ_PSTMP_RING_ITEMSIZE */
3139
3140 r600_store_context_reg_seq(cb, R_02891C_SQ_GS_VERT_ITEMSIZE, 4);
3141 r600_store_value(cb, 0); /* R_02891C_SQ_GS_VERT_ITEMSIZE */
3142 r600_store_value(cb, 0); /* R_028920_SQ_GS_VERT_ITEMSIZE_1 */
3143 r600_store_value(cb, 0); /* R_028924_SQ_GS_VERT_ITEMSIZE_2 */
3144 r600_store_value(cb, 0); /* R_028928_SQ_GS_VERT_ITEMSIZE_3 */
3145
3146 r600_store_context_reg_seq(cb, R_028A10_VGT_OUTPUT_PATH_CNTL, 13);
3147 r600_store_value(cb, 0); /* R_028A10_VGT_OUTPUT_PATH_CNTL */
3148 r600_store_value(cb, 0); /* R_028A14_VGT_HOS_CNTL */
3149 r600_store_value(cb, fui(64)); /* R_028A18_VGT_HOS_MAX_TESS_LEVEL */
3150 r600_store_value(cb, fui(1.0)); /* R_028A1C_VGT_HOS_MIN_TESS_LEVEL */
3151 r600_store_value(cb, 16); /* R_028A20_VGT_HOS_REUSE_DEPTH */
3152 r600_store_value(cb, 0); /* R_028A24_VGT_GROUP_PRIM_TYPE */
3153 r600_store_value(cb, 0); /* R_028A28_VGT_GROUP_FIRST_DECR */
3154 r600_store_value(cb, 0); /* R_028A2C_VGT_GROUP_DECR */
3155 r600_store_value(cb, 0); /* R_028A30_VGT_GROUP_VECT_0_CNTL */
3156 r600_store_value(cb, 0); /* R_028A34_VGT_GROUP_VECT_1_CNTL */
3157 r600_store_value(cb, 0); /* R_028A38_VGT_GROUP_VECT_0_FMT_CNTL */
3158 r600_store_value(cb, 0); /* R_028A3C_VGT_GROUP_VECT_1_FMT_CNTL */
3159 r600_store_value(cb, 0); /* R_028A40_VGT_GS_MODE */
3160
3161 r600_store_config_reg(cb, R_008A14_PA_CL_ENHANCE, (3 << 1) | 1);
3162
3163 r600_store_context_reg(cb, R_0288F0_SQ_VTX_SEMANTIC_CLEAR, ~0);
3164
3165 r600_store_context_reg_seq(cb, R_028400_VGT_MAX_VTX_INDX, 2);
3166 r600_store_value(cb, ~0); /* R_028400_VGT_MAX_VTX_INDX */
3167 r600_store_value(cb, 0); /* R_028404_VGT_MIN_VTX_INDX */
3168
3169 r600_store_ctl_const(cb, R_03CFF0_SQ_VTX_BASE_VTX_LOC, 0);
3170
3171 r600_store_context_reg(cb, R_028028_DB_STENCIL_CLEAR, 0);
3172
3173 r600_store_context_reg(cb, R_028200_PA_SC_WINDOW_OFFSET, 0);
3174 r600_store_context_reg(cb, R_02820C_PA_SC_CLIPRECT_RULE, 0xFFFF);
3175 r600_store_context_reg(cb, R_028230_PA_SC_EDGERULE, 0xAAAAAAAA);
3176
3177 r600_store_context_reg(cb, R_0286DC_SPI_FOG_CNTL, 0);
3178 r600_store_context_reg(cb, R_028820_PA_CL_NANINF_CNTL, 0);
3179
3180 r600_store_context_reg_seq(cb, R_028AC0_DB_SRESULTS_COMPARE_STATE0, 3);
3181 r600_store_value(cb, 0); /* R_028AC0_DB_SRESULTS_COMPARE_STATE0 */
3182 r600_store_value(cb, 0); /* R_028AC4_DB_SRESULTS_COMPARE_STATE1 */
3183 r600_store_value(cb, 0); /* R_028AC8_DB_PRELOAD_CONTROL */
3184
3185 r600_store_context_reg_seq(cb, R_028240_PA_SC_GENERIC_SCISSOR_TL, 2);
3186 r600_store_value(cb, 0); /* R_028240_PA_SC_GENERIC_SCISSOR_TL */
3187 r600_store_value(cb, S_028244_BR_X(16384) | S_028244_BR_Y(16384)); /* R_028244_PA_SC_GENERIC_SCISSOR_BR */
3188
3189 r600_store_context_reg_seq(cb, R_028030_PA_SC_SCREEN_SCISSOR_TL, 2);
3190 r600_store_value(cb, 0); /* R_028030_PA_SC_SCREEN_SCISSOR_TL */
3191 r600_store_value(cb, S_028034_BR_X(16384) | S_028034_BR_Y(16384)); /* R_028034_PA_SC_SCREEN_SCISSOR_BR */
3192
3193 r600_store_context_reg(cb, R_028848_SQ_PGM_RESOURCES_2_PS, S_028848_SINGLE_ROUND(V_SQ_ROUND_NEAREST_EVEN));
3194 r600_store_context_reg(cb, R_028864_SQ_PGM_RESOURCES_2_VS, S_028864_SINGLE_ROUND(V_SQ_ROUND_NEAREST_EVEN));
3195 r600_store_context_reg(cb, R_02887C_SQ_PGM_RESOURCES_2_GS, S_028848_SINGLE_ROUND(V_SQ_ROUND_NEAREST_EVEN));
3196 r600_store_context_reg(cb, R_028894_SQ_PGM_RESOURCES_2_ES, S_028848_SINGLE_ROUND(V_SQ_ROUND_NEAREST_EVEN));
3197 r600_store_context_reg(cb, R_0288A8_SQ_PGM_RESOURCES_FS, 0);
3198 r600_store_context_reg(cb, R_0288C0_SQ_PGM_RESOURCES_2_HS, S_028848_SINGLE_ROUND(V_SQ_ROUND_NEAREST_EVEN));
3199 r600_store_context_reg(cb, R_0288D8_SQ_PGM_RESOURCES_2_LS, S_028848_SINGLE_ROUND(V_SQ_ROUND_NEAREST_EVEN));
3200
3201 /* to avoid GPU doing any preloading of constant from random address */
3202 r600_store_context_reg_seq(cb, R_028140_ALU_CONST_BUFFER_SIZE_PS_0, 16);
3203 for (i = 0; i < 16; i++)
3204 r600_store_value(cb, 0);
3205
3206 r600_store_context_reg_seq(cb, R_028180_ALU_CONST_BUFFER_SIZE_VS_0, 16);
3207 for (i = 0; i < 16; i++)
3208 r600_store_value(cb, 0);
3209
3210 r600_store_context_reg_seq(cb, R_0281C0_ALU_CONST_BUFFER_SIZE_GS_0, 16);
3211 for (i = 0; i < 16; i++)
3212 r600_store_value(cb, 0);
3213
3214 r600_store_context_reg_seq(cb, R_028FC0_ALU_CONST_BUFFER_SIZE_LS_0, 16);
3215 for (i = 0; i < 16; i++)
3216 r600_store_value(cb, 0);
3217
3218 r600_store_context_reg_seq(cb, R_028F80_ALU_CONST_BUFFER_SIZE_HS_0, 16);
3219 for (i = 0; i < 16; i++)
3220 r600_store_value(cb, 0);
3221
3222 r600_store_context_reg(cb, R_028B98_VGT_STRMOUT_BUFFER_CONFIG, 0);
3223
3224 if (rctx->screen->b.has_streamout) {
3225 r600_store_context_reg(cb, R_028B28_VGT_STRMOUT_DRAW_OPAQUE_OFFSET, 0);
3226 }
3227
3228 r600_store_context_reg(cb, R_028010_DB_RENDER_OVERRIDE2, 0);
3229 r600_store_context_reg(cb, R_028234_PA_SU_HARDWARE_SCREEN_OFFSET, 0);
3230 r600_store_context_reg(cb, R_0286C8_SPI_THREAD_GROUPING, 0);
3231 r600_store_context_reg_seq(cb, R_0286E4_SPI_PS_IN_CONTROL_2, 2);
3232 r600_store_value(cb, 0); /* R_0286E4_SPI_PS_IN_CONTROL_2 */
3233 r600_store_value(cb, 0); /* R_0286E8_SPI_COMPUTE_INPUT_CNTL */
3234
3235 r600_store_context_reg_seq(cb, R_0288E8_SQ_LDS_ALLOC, 2);
3236 r600_store_value(cb, 0); /* R_0288E8_SQ_LDS_ALLOC */
3237 r600_store_value(cb, 0); /* R_0288EC_SQ_LDS_ALLOC_PS */
3238
3239 if (rctx->b.family == CHIP_CAICOS) {
3240 r600_store_context_reg_seq(cb, R_028B54_VGT_SHADER_STAGES_EN, 2);
3241 r600_store_value(cb, 0); /* R028B54_VGT_SHADER_STAGES_EN */
3242 r600_store_value(cb, 0); /* R028B58_VGT_LS_HS_CONFIG */
3243 r600_store_context_reg(cb, R_028B6C_VGT_TF_PARAM, 0);
3244 } else {
3245 r600_store_context_reg_seq(cb, R_028B54_VGT_SHADER_STAGES_EN, 7);
3246 r600_store_value(cb, 0); /* R028B54_VGT_SHADER_STAGES_EN */
3247 r600_store_value(cb, 0); /* R028B58_VGT_LS_HS_CONFIG */
3248 r600_store_value(cb, 0); /* R028B5C_VGT_LS_SIZE */
3249 r600_store_value(cb, 0); /* R028B60_VGT_HS_SIZE */
3250 r600_store_value(cb, 0); /* R028B64_VGT_LS_HS_ALLOC */
3251 r600_store_value(cb, 0); /* R028B68_VGT_HS_PATCH_CONST */
3252 r600_store_value(cb, 0); /* R028B68_VGT_TF_PARAM */
3253 }
3254
3255 eg_store_loop_const(cb, R_03A200_SQ_LOOP_CONST_0, 0x01000FFF);
3256 eg_store_loop_const(cb, R_03A200_SQ_LOOP_CONST_0 + (32 * 4), 0x01000FFF);
3257 eg_store_loop_const(cb, R_03A200_SQ_LOOP_CONST_0 + (64 * 4), 0x01000FFF);
3258 eg_store_loop_const(cb, R_03A200_SQ_LOOP_CONST_0 + (96 * 4), 0x01000FFF);
3259 eg_store_loop_const(cb, R_03A200_SQ_LOOP_CONST_0 + (128 * 4), 0x01000FFF);
3260 }
3261
3262 void evergreen_update_ps_state(struct pipe_context *ctx, struct r600_pipe_shader *shader)
3263 {
3264 struct r600_context *rctx = (struct r600_context *)ctx;
3265 struct r600_command_buffer *cb = &shader->command_buffer;
3266 struct r600_shader *rshader = &shader->shader;
3267 unsigned i, exports_ps, num_cout, spi_ps_in_control_0, spi_input_z, spi_ps_in_control_1, db_shader_control = 0;
3268 int pos_index = -1, face_index = -1, fixed_pt_position_index = -1;
3269 int ninterp = 0;
3270 boolean have_perspective = FALSE, have_linear = FALSE;
3271 static const unsigned spi_baryc_enable_bit[6] = {
3272 S_0286E0_PERSP_SAMPLE_ENA(1),
3273 S_0286E0_PERSP_CENTER_ENA(1),
3274 S_0286E0_PERSP_CENTROID_ENA(1),
3275 S_0286E0_LINEAR_SAMPLE_ENA(1),
3276 S_0286E0_LINEAR_CENTER_ENA(1),
3277 S_0286E0_LINEAR_CENTROID_ENA(1)
3278 };
3279 unsigned spi_baryc_cntl = 0, sid, tmp, num = 0;
3280 unsigned z_export = 0, stencil_export = 0, mask_export = 0;
3281 unsigned sprite_coord_enable = rctx->rasterizer ? rctx->rasterizer->sprite_coord_enable : 0;
3282 uint32_t spi_ps_input_cntl[32];
3283
3284 if (!cb->buf) {
3285 r600_init_command_buffer(cb, 64);
3286 } else {
3287 cb->num_dw = 0;
3288 }
3289
3290 for (i = 0; i < rshader->ninput; i++) {
3291 /* evergreen NUM_INTERP only contains values interpolated into the LDS,
3292 POSITION goes via GPRs from the SC so isn't counted */
3293 if (rshader->input[i].name == TGSI_SEMANTIC_POSITION)
3294 pos_index = i;
3295 else if (rshader->input[i].name == TGSI_SEMANTIC_FACE) {
3296 if (face_index == -1)
3297 face_index = i;
3298 }
3299 else if (rshader->input[i].name == TGSI_SEMANTIC_SAMPLEMASK) {
3300 if (face_index == -1)
3301 face_index = i; /* lives in same register, same enable bit */
3302 }
3303 else if (rshader->input[i].name == TGSI_SEMANTIC_SAMPLEID) {
3304 fixed_pt_position_index = i;
3305 }
3306 else {
3307 ninterp++;
3308 int k = eg_get_interpolator_index(
3309 rshader->input[i].interpolate,
3310 rshader->input[i].interpolate_location);
3311 if (k >= 0) {
3312 spi_baryc_cntl |= spi_baryc_enable_bit[k];
3313 have_perspective |= k < 3;
3314 have_linear |= !(k < 3);
3315 }
3316 }
3317
3318 sid = rshader->input[i].spi_sid;
3319
3320 if (sid) {
3321 tmp = S_028644_SEMANTIC(sid);
3322
3323 /* D3D 9 behaviour. GL is undefined */
3324 if (rshader->input[i].name == TGSI_SEMANTIC_COLOR && rshader->input[i].sid == 0)
3325 tmp |= S_028644_DEFAULT_VAL(3);
3326
3327 if (rshader->input[i].name == TGSI_SEMANTIC_POSITION ||
3328 rshader->input[i].interpolate == TGSI_INTERPOLATE_CONSTANT ||
3329 (rshader->input[i].interpolate == TGSI_INTERPOLATE_COLOR &&
3330 rctx->rasterizer && rctx->rasterizer->flatshade)) {
3331 tmp |= S_028644_FLAT_SHADE(1);
3332 }
3333
3334 if (rshader->input[i].name == TGSI_SEMANTIC_GENERIC &&
3335 (sprite_coord_enable & (1 << rshader->input[i].sid))) {
3336 tmp |= S_028644_PT_SPRITE_TEX(1);
3337 }
3338
3339 spi_ps_input_cntl[num++] = tmp;
3340 }
3341 }
3342
3343 r600_store_context_reg_seq(cb, R_028644_SPI_PS_INPUT_CNTL_0, num);
3344 r600_store_array(cb, num, spi_ps_input_cntl);
3345
3346 for (i = 0; i < rshader->noutput; i++) {
3347 if (rshader->output[i].name == TGSI_SEMANTIC_POSITION)
3348 z_export = 1;
3349 if (rshader->output[i].name == TGSI_SEMANTIC_STENCIL)
3350 stencil_export = 1;
3351 if (rshader->output[i].name == TGSI_SEMANTIC_SAMPLEMASK &&
3352 rctx->framebuffer.nr_samples > 1 && rctx->ps_iter_samples > 0)
3353 mask_export = 1;
3354 }
3355 if (rshader->uses_kill)
3356 db_shader_control |= S_02880C_KILL_ENABLE(1);
3357
3358 db_shader_control |= S_02880C_Z_EXPORT_ENABLE(z_export);
3359 db_shader_control |= S_02880C_STENCIL_EXPORT_ENABLE(stencil_export);
3360 db_shader_control |= S_02880C_MASK_EXPORT_ENABLE(mask_export);
3361
3362 if (shader->selector->info.properties[TGSI_PROPERTY_FS_EARLY_DEPTH_STENCIL]) {
3363 db_shader_control |= S_02880C_DEPTH_BEFORE_SHADER(1) |
3364 S_02880C_EXEC_ON_NOOP(shader->selector->info.writes_memory);
3365 } else if (shader->selector->info.writes_memory) {
3366 db_shader_control |= S_02880C_EXEC_ON_HIER_FAIL(1);
3367 }
3368
3369 switch (rshader->ps_conservative_z) {
3370 default: /* fall through */
3371 case TGSI_FS_DEPTH_LAYOUT_ANY:
3372 db_shader_control |= S_02880C_CONSERVATIVE_Z_EXPORT(V_02880C_EXPORT_ANY_Z);
3373 break;
3374 case TGSI_FS_DEPTH_LAYOUT_GREATER:
3375 db_shader_control |= S_02880C_CONSERVATIVE_Z_EXPORT(V_02880C_EXPORT_GREATER_THAN_Z);
3376 break;
3377 case TGSI_FS_DEPTH_LAYOUT_LESS:
3378 db_shader_control |= S_02880C_CONSERVATIVE_Z_EXPORT(V_02880C_EXPORT_LESS_THAN_Z);
3379 break;
3380 }
3381
3382 exports_ps = 0;
3383 for (i = 0; i < rshader->noutput; i++) {
3384 if (rshader->output[i].name == TGSI_SEMANTIC_POSITION ||
3385 rshader->output[i].name == TGSI_SEMANTIC_STENCIL ||
3386 rshader->output[i].name == TGSI_SEMANTIC_SAMPLEMASK)
3387 exports_ps |= 1;
3388 }
3389
3390 num_cout = rshader->ps_export_highest + 1;
3391
3392 exports_ps |= S_02884C_EXPORT_COLORS(num_cout);
3393 if (!exports_ps) {
3394 /* always at least export 1 component per pixel */
3395 exports_ps = 2;
3396 }
3397 shader->nr_ps_color_outputs = num_cout;
3398 shader->ps_color_export_mask = rshader->ps_color_export_mask;
3399 if (ninterp == 0) {
3400 ninterp = 1;
3401 have_perspective = TRUE;
3402 }
3403 if (!spi_baryc_cntl)
3404 spi_baryc_cntl |= spi_baryc_enable_bit[0];
3405
3406 if (!have_perspective && !have_linear)
3407 have_perspective = TRUE;
3408
3409 spi_ps_in_control_0 = S_0286CC_NUM_INTERP(ninterp) |
3410 S_0286CC_PERSP_GRADIENT_ENA(have_perspective) |
3411 S_0286CC_LINEAR_GRADIENT_ENA(have_linear);
3412 spi_input_z = 0;
3413 if (pos_index != -1) {
3414 spi_ps_in_control_0 |= S_0286CC_POSITION_ENA(1) |
3415 S_0286CC_POSITION_CENTROID(rshader->input[pos_index].interpolate_location == TGSI_INTERPOLATE_LOC_CENTROID) |
3416 S_0286CC_POSITION_ADDR(rshader->input[pos_index].gpr);
3417 spi_input_z |= S_0286D8_PROVIDE_Z_TO_SPI(1);
3418 }
3419
3420 spi_ps_in_control_1 = 0;
3421 if (face_index != -1) {
3422 spi_ps_in_control_1 |= S_0286D0_FRONT_FACE_ENA(1) |
3423 S_0286D0_FRONT_FACE_ADDR(rshader->input[face_index].gpr);
3424 }
3425 if (fixed_pt_position_index != -1) {
3426 spi_ps_in_control_1 |= S_0286D0_FIXED_PT_POSITION_ENA(1) |
3427 S_0286D0_FIXED_PT_POSITION_ADDR(rshader->input[fixed_pt_position_index].gpr);
3428 }
3429
3430 r600_store_context_reg_seq(cb, R_0286CC_SPI_PS_IN_CONTROL_0, 2);
3431 r600_store_value(cb, spi_ps_in_control_0); /* R_0286CC_SPI_PS_IN_CONTROL_0 */
3432 r600_store_value(cb, spi_ps_in_control_1); /* R_0286D0_SPI_PS_IN_CONTROL_1 */
3433
3434 r600_store_context_reg(cb, R_0286E0_SPI_BARYC_CNTL, spi_baryc_cntl);
3435 r600_store_context_reg(cb, R_0286D8_SPI_INPUT_Z, spi_input_z);
3436 r600_store_context_reg(cb, R_02884C_SQ_PGM_EXPORTS_PS, exports_ps);
3437
3438 r600_store_context_reg_seq(cb, R_028840_SQ_PGM_START_PS, 2);
3439 r600_store_value(cb, shader->bo->gpu_address >> 8);
3440 r600_store_value(cb, /* R_028844_SQ_PGM_RESOURCES_PS */
3441 S_028844_NUM_GPRS(rshader->bc.ngpr) |
3442 S_028844_PRIME_CACHE_ON_DRAW(1) |
3443 S_028844_DX10_CLAMP(1) |
3444 S_028844_STACK_SIZE(rshader->bc.nstack));
3445 /* After that, the NOP relocation packet must be emitted (shader->bo, RADEON_USAGE_READ). */
3446
3447 shader->db_shader_control = db_shader_control;
3448 shader->ps_depth_export = z_export | stencil_export | mask_export;
3449
3450 shader->sprite_coord_enable = sprite_coord_enable;
3451 if (rctx->rasterizer)
3452 shader->flatshade = rctx->rasterizer->flatshade;
3453 }
3454
3455 void evergreen_update_es_state(struct pipe_context *ctx, struct r600_pipe_shader *shader)
3456 {
3457 struct r600_command_buffer *cb = &shader->command_buffer;
3458 struct r600_shader *rshader = &shader->shader;
3459
3460 r600_init_command_buffer(cb, 32);
3461
3462 r600_store_context_reg(cb, R_028890_SQ_PGM_RESOURCES_ES,
3463 S_028890_NUM_GPRS(rshader->bc.ngpr) |
3464 S_028890_DX10_CLAMP(1) |
3465 S_028890_STACK_SIZE(rshader->bc.nstack));
3466 r600_store_context_reg(cb, R_02888C_SQ_PGM_START_ES,
3467 shader->bo->gpu_address >> 8);
3468 /* After that, the NOP relocation packet must be emitted (shader->bo, RADEON_USAGE_READ). */
3469 }
3470
3471 void evergreen_update_gs_state(struct pipe_context *ctx, struct r600_pipe_shader *shader)
3472 {
3473 struct r600_context *rctx = (struct r600_context *)ctx;
3474 struct r600_command_buffer *cb = &shader->command_buffer;
3475 struct r600_shader *rshader = &shader->shader;
3476 struct r600_shader *cp_shader = &shader->gs_copy_shader->shader;
3477 unsigned gsvs_itemsizes[4] = {
3478 (cp_shader->ring_item_sizes[0] * shader->selector->gs_max_out_vertices) >> 2,
3479 (cp_shader->ring_item_sizes[1] * shader->selector->gs_max_out_vertices) >> 2,
3480 (cp_shader->ring_item_sizes[2] * shader->selector->gs_max_out_vertices) >> 2,
3481 (cp_shader->ring_item_sizes[3] * shader->selector->gs_max_out_vertices) >> 2
3482 };
3483
3484 r600_init_command_buffer(cb, 64);
3485
3486 /* VGT_GS_MODE is written by evergreen_emit_shader_stages */
3487
3488
3489 r600_store_context_reg(cb, R_028B38_VGT_GS_MAX_VERT_OUT,
3490 S_028B38_MAX_VERT_OUT(shader->selector->gs_max_out_vertices));
3491 r600_store_context_reg(cb, R_028A6C_VGT_GS_OUT_PRIM_TYPE,
3492 r600_conv_prim_to_gs_out(shader->selector->gs_output_prim));
3493
3494 if (rctx->screen->b.info.drm_minor >= 35) {
3495 r600_store_context_reg(cb, R_028B90_VGT_GS_INSTANCE_CNT,
3496 S_028B90_CNT(MIN2(shader->selector->gs_num_invocations, 127)) |
3497 S_028B90_ENABLE(shader->selector->gs_num_invocations > 0));
3498 }
3499 r600_store_context_reg_seq(cb, R_02891C_SQ_GS_VERT_ITEMSIZE, 4);
3500 r600_store_value(cb, cp_shader->ring_item_sizes[0] >> 2);
3501 r600_store_value(cb, cp_shader->ring_item_sizes[1] >> 2);
3502 r600_store_value(cb, cp_shader->ring_item_sizes[2] >> 2);
3503 r600_store_value(cb, cp_shader->ring_item_sizes[3] >> 2);
3504
3505 r600_store_context_reg(cb, R_028900_SQ_ESGS_RING_ITEMSIZE,
3506 (rshader->ring_item_sizes[0]) >> 2);
3507
3508 r600_store_context_reg(cb, R_028904_SQ_GSVS_RING_ITEMSIZE,
3509 gsvs_itemsizes[0] +
3510 gsvs_itemsizes[1] +
3511 gsvs_itemsizes[2] +
3512 gsvs_itemsizes[3]);
3513
3514 r600_store_context_reg_seq(cb, R_02892C_SQ_GSVS_RING_OFFSET_1, 3);
3515 r600_store_value(cb, gsvs_itemsizes[0]);
3516 r600_store_value(cb, gsvs_itemsizes[0] + gsvs_itemsizes[1]);
3517 r600_store_value(cb, gsvs_itemsizes[0] + gsvs_itemsizes[1] + gsvs_itemsizes[2]);
3518
3519 /* FIXME calculate these values somehow ??? */
3520 r600_store_context_reg_seq(cb, R_028A54_GS_PER_ES, 3);
3521 r600_store_value(cb, 0x80); /* GS_PER_ES */
3522 r600_store_value(cb, 0x100); /* ES_PER_GS */
3523 r600_store_value(cb, 0x2); /* GS_PER_VS */
3524
3525 r600_store_context_reg(cb, R_028878_SQ_PGM_RESOURCES_GS,
3526 S_028878_NUM_GPRS(rshader->bc.ngpr) |
3527 S_028878_DX10_CLAMP(1) |
3528 S_028878_STACK_SIZE(rshader->bc.nstack));
3529 r600_store_context_reg(cb, R_028874_SQ_PGM_START_GS,
3530 shader->bo->gpu_address >> 8);
3531 /* After that, the NOP relocation packet must be emitted (shader->bo, RADEON_USAGE_READ). */
3532 }
3533
3534
3535 void evergreen_update_vs_state(struct pipe_context *ctx, struct r600_pipe_shader *shader)
3536 {
3537 struct r600_command_buffer *cb = &shader->command_buffer;
3538 struct r600_shader *rshader = &shader->shader;
3539 unsigned spi_vs_out_id[10] = {};
3540 unsigned i, tmp, nparams = 0;
3541
3542 for (i = 0; i < rshader->noutput; i++) {
3543 if (rshader->output[i].spi_sid) {
3544 tmp = rshader->output[i].spi_sid << ((nparams & 3) * 8);
3545 spi_vs_out_id[nparams / 4] |= tmp;
3546 nparams++;
3547 }
3548 }
3549
3550 r600_init_command_buffer(cb, 32);
3551
3552 r600_store_context_reg_seq(cb, R_02861C_SPI_VS_OUT_ID_0, 10);
3553 for (i = 0; i < 10; i++) {
3554 r600_store_value(cb, spi_vs_out_id[i]);
3555 }
3556
3557 /* Certain attributes (position, psize, etc.) don't count as params.
3558 * VS is required to export at least one param and r600_shader_from_tgsi()
3559 * takes care of adding a dummy export.
3560 */
3561 if (nparams < 1)
3562 nparams = 1;
3563
3564 r600_store_context_reg(cb, R_0286C4_SPI_VS_OUT_CONFIG,
3565 S_0286C4_VS_EXPORT_COUNT(nparams - 1));
3566 r600_store_context_reg(cb, R_028860_SQ_PGM_RESOURCES_VS,
3567 S_028860_NUM_GPRS(rshader->bc.ngpr) |
3568 S_028860_DX10_CLAMP(1) |
3569 S_028860_STACK_SIZE(rshader->bc.nstack));
3570 if (rshader->vs_position_window_space) {
3571 r600_store_context_reg(cb, R_028818_PA_CL_VTE_CNTL,
3572 S_028818_VTX_XY_FMT(1) | S_028818_VTX_Z_FMT(1));
3573 } else {
3574 r600_store_context_reg(cb, R_028818_PA_CL_VTE_CNTL,
3575 S_028818_VTX_W0_FMT(1) |
3576 S_028818_VPORT_X_SCALE_ENA(1) | S_028818_VPORT_X_OFFSET_ENA(1) |
3577 S_028818_VPORT_Y_SCALE_ENA(1) | S_028818_VPORT_Y_OFFSET_ENA(1) |
3578 S_028818_VPORT_Z_SCALE_ENA(1) | S_028818_VPORT_Z_OFFSET_ENA(1));
3579
3580 }
3581 r600_store_context_reg(cb, R_02885C_SQ_PGM_START_VS,
3582 shader->bo->gpu_address >> 8);
3583 /* After that, the NOP relocation packet must be emitted (shader->bo, RADEON_USAGE_READ). */
3584
3585 shader->pa_cl_vs_out_cntl =
3586 S_02881C_VS_OUT_CCDIST0_VEC_ENA((rshader->cc_dist_mask & 0x0F) != 0) |
3587 S_02881C_VS_OUT_CCDIST1_VEC_ENA((rshader->cc_dist_mask & 0xF0) != 0) |
3588 S_02881C_VS_OUT_MISC_VEC_ENA(rshader->vs_out_misc_write) |
3589 S_02881C_USE_VTX_POINT_SIZE(rshader->vs_out_point_size) |
3590 S_02881C_USE_VTX_EDGE_FLAG(rshader->vs_out_edgeflag) |
3591 S_02881C_USE_VTX_VIEWPORT_INDX(rshader->vs_out_viewport) |
3592 S_02881C_USE_VTX_RENDER_TARGET_INDX(rshader->vs_out_layer);
3593 }
3594
3595 void evergreen_update_hs_state(struct pipe_context *ctx, struct r600_pipe_shader *shader)
3596 {
3597 struct r600_command_buffer *cb = &shader->command_buffer;
3598 struct r600_shader *rshader = &shader->shader;
3599
3600 r600_init_command_buffer(cb, 32);
3601 r600_store_context_reg(cb, R_0288BC_SQ_PGM_RESOURCES_HS,
3602 S_0288BC_NUM_GPRS(rshader->bc.ngpr) |
3603 S_0288BC_DX10_CLAMP(1) |
3604 S_0288BC_STACK_SIZE(rshader->bc.nstack));
3605 r600_store_context_reg(cb, R_0288B8_SQ_PGM_START_HS,
3606 shader->bo->gpu_address >> 8);
3607 }
3608
3609 void evergreen_update_ls_state(struct pipe_context *ctx, struct r600_pipe_shader *shader)
3610 {
3611 struct r600_command_buffer *cb = &shader->command_buffer;
3612 struct r600_shader *rshader = &shader->shader;
3613
3614 r600_init_command_buffer(cb, 32);
3615 r600_store_context_reg(cb, R_0288D4_SQ_PGM_RESOURCES_LS,
3616 S_0288D4_NUM_GPRS(rshader->bc.ngpr) |
3617 S_0288D4_DX10_CLAMP(1) |
3618 S_0288D4_STACK_SIZE(rshader->bc.nstack));
3619 r600_store_context_reg(cb, R_0288D0_SQ_PGM_START_LS,
3620 shader->bo->gpu_address >> 8);
3621 }
3622 void *evergreen_create_resolve_blend(struct r600_context *rctx)
3623 {
3624 struct pipe_blend_state blend;
3625
3626 memset(&blend, 0, sizeof(blend));
3627 blend.independent_blend_enable = true;
3628 blend.rt[0].colormask = 0xf;
3629 return evergreen_create_blend_state_mode(&rctx->b.b, &blend, V_028808_CB_RESOLVE);
3630 }
3631
3632 void *evergreen_create_decompress_blend(struct r600_context *rctx)
3633 {
3634 struct pipe_blend_state blend;
3635 unsigned mode = rctx->screen->has_compressed_msaa_texturing ?
3636 V_028808_CB_FMASK_DECOMPRESS : V_028808_CB_DECOMPRESS;
3637
3638 memset(&blend, 0, sizeof(blend));
3639 blend.independent_blend_enable = true;
3640 blend.rt[0].colormask = 0xf;
3641 return evergreen_create_blend_state_mode(&rctx->b.b, &blend, mode);
3642 }
3643
3644 void *evergreen_create_fastclear_blend(struct r600_context *rctx)
3645 {
3646 struct pipe_blend_state blend;
3647 unsigned mode = V_028808_CB_ELIMINATE_FAST_CLEAR;
3648
3649 memset(&blend, 0, sizeof(blend));
3650 blend.independent_blend_enable = true;
3651 blend.rt[0].colormask = 0xf;
3652 return evergreen_create_blend_state_mode(&rctx->b.b, &blend, mode);
3653 }
3654
3655 void *evergreen_create_db_flush_dsa(struct r600_context *rctx)
3656 {
3657 struct pipe_depth_stencil_alpha_state dsa = {{0}};
3658
3659 return rctx->b.b.create_depth_stencil_alpha_state(&rctx->b.b, &dsa);
3660 }
3661
3662 void evergreen_update_db_shader_control(struct r600_context * rctx)
3663 {
3664 bool dual_export;
3665 unsigned db_shader_control;
3666
3667 if (!rctx->ps_shader) {
3668 return;
3669 }
3670
3671 dual_export = rctx->framebuffer.export_16bpc &&
3672 !rctx->ps_shader->current->ps_depth_export;
3673
3674 db_shader_control = rctx->ps_shader->current->db_shader_control |
3675 S_02880C_DUAL_EXPORT_ENABLE(dual_export) |
3676 S_02880C_DB_SOURCE_FORMAT(dual_export ? V_02880C_EXPORT_DB_TWO :
3677 V_02880C_EXPORT_DB_FULL) |
3678 S_02880C_ALPHA_TO_MASK_DISABLE(rctx->framebuffer.cb0_is_integer);
3679
3680 /* When alpha test is enabled we can't trust the hw to make the proper
3681 * decision on the order in which ztest should be run related to fragment
3682 * shader execution.
3683 *
3684 * If alpha test is enabled perform early z rejection (RE_Z) but don't early
3685 * write to the zbuffer. Write to zbuffer is delayed after fragment shader
3686 * execution and thus after alpha test so if discarded by the alpha test
3687 * the z value is not written.
3688 * If ReZ is enabled, and the zfunc/zenable/zwrite values change you can
3689 * get a hang unless you flush the DB in between. For now just use
3690 * LATE_Z.
3691 */
3692 if (rctx->alphatest_state.sx_alpha_test_control || rctx->ps_shader->info.writes_memory) {
3693 db_shader_control |= S_02880C_Z_ORDER(V_02880C_LATE_Z);
3694 } else {
3695 db_shader_control |= S_02880C_Z_ORDER(V_02880C_EARLY_Z_THEN_LATE_Z);
3696 }
3697
3698 if (db_shader_control != rctx->db_misc_state.db_shader_control) {
3699 rctx->db_misc_state.db_shader_control = db_shader_control;
3700 r600_mark_atom_dirty(rctx, &rctx->db_misc_state.atom);
3701 }
3702 }
3703
3704 static void evergreen_dma_copy_tile(struct r600_context *rctx,
3705 struct pipe_resource *dst,
3706 unsigned dst_level,
3707 unsigned dst_x,
3708 unsigned dst_y,
3709 unsigned dst_z,
3710 struct pipe_resource *src,
3711 unsigned src_level,
3712 unsigned src_x,
3713 unsigned src_y,
3714 unsigned src_z,
3715 unsigned copy_height,
3716 unsigned pitch,
3717 unsigned bpp)
3718 {
3719 struct radeon_winsys_cs *cs = rctx->b.dma.cs;
3720 struct r600_texture *rsrc = (struct r600_texture*)src;
3721 struct r600_texture *rdst = (struct r600_texture*)dst;
3722 unsigned array_mode, lbpp, pitch_tile_max, slice_tile_max, size;
3723 unsigned ncopy, height, cheight, detile, i, x, y, z, src_mode, dst_mode;
3724 unsigned sub_cmd, bank_h, bank_w, mt_aspect, nbanks, tile_split, non_disp_tiling = 0;
3725 uint64_t base, addr;
3726
3727 dst_mode = rdst->surface.u.legacy.level[dst_level].mode;
3728 src_mode = rsrc->surface.u.legacy.level[src_level].mode;
3729 assert(dst_mode != src_mode);
3730
3731 /* non_disp_tiling bit needs to be set for depth, stencil, and fmask surfaces */
3732 if (util_format_has_depth(util_format_description(src->format)))
3733 non_disp_tiling = 1;
3734
3735 y = 0;
3736 sub_cmd = EG_DMA_COPY_TILED;
3737 lbpp = util_logbase2(bpp);
3738 pitch_tile_max = ((pitch / bpp) / 8) - 1;
3739 nbanks = eg_num_banks(rctx->screen->b.info.r600_num_banks);
3740
3741 if (dst_mode == RADEON_SURF_MODE_LINEAR_ALIGNED) {
3742 /* T2L */
3743 array_mode = evergreen_array_mode(src_mode);
3744 slice_tile_max = (rsrc->surface.u.legacy.level[src_level].nblk_x * rsrc->surface.u.legacy.level[src_level].nblk_y) / (8*8);
3745 slice_tile_max = slice_tile_max ? slice_tile_max - 1 : 0;
3746 /* linear height must be the same as the slice tile max height, it's ok even
3747 * if the linear destination/source have smaller heigh as the size of the
3748 * dma packet will be using the copy_height which is always smaller or equal
3749 * to the linear height
3750 */
3751 height = u_minify(rsrc->resource.b.b.height0, src_level);
3752 detile = 1;
3753 x = src_x;
3754 y = src_y;
3755 z = src_z;
3756 base = rsrc->surface.u.legacy.level[src_level].offset;
3757 addr = rdst->surface.u.legacy.level[dst_level].offset;
3758 addr += (uint64_t)rdst->surface.u.legacy.level[dst_level].slice_size_dw * 4 * dst_z;
3759 addr += dst_y * pitch + dst_x * bpp;
3760 bank_h = eg_bank_wh(rsrc->surface.u.legacy.bankh);
3761 bank_w = eg_bank_wh(rsrc->surface.u.legacy.bankw);
3762 mt_aspect = eg_macro_tile_aspect(rsrc->surface.u.legacy.mtilea);
3763 tile_split = eg_tile_split(rsrc->surface.u.legacy.tile_split);
3764 base += rsrc->resource.gpu_address;
3765 addr += rdst->resource.gpu_address;
3766 } else {
3767 /* L2T */
3768 array_mode = evergreen_array_mode(dst_mode);
3769 slice_tile_max = (rdst->surface.u.legacy.level[dst_level].nblk_x * rdst->surface.u.legacy.level[dst_level].nblk_y) / (8*8);
3770 slice_tile_max = slice_tile_max ? slice_tile_max - 1 : 0;
3771 /* linear height must be the same as the slice tile max height, it's ok even
3772 * if the linear destination/source have smaller heigh as the size of the
3773 * dma packet will be using the copy_height which is always smaller or equal
3774 * to the linear height
3775 */
3776 height = u_minify(rdst->resource.b.b.height0, dst_level);
3777 detile = 0;
3778 x = dst_x;
3779 y = dst_y;
3780 z = dst_z;
3781 base = rdst->surface.u.legacy.level[dst_level].offset;
3782 addr = rsrc->surface.u.legacy.level[src_level].offset;
3783 addr += (uint64_t)rsrc->surface.u.legacy.level[src_level].slice_size_dw * 4 * src_z;
3784 addr += src_y * pitch + src_x * bpp;
3785 bank_h = eg_bank_wh(rdst->surface.u.legacy.bankh);
3786 bank_w = eg_bank_wh(rdst->surface.u.legacy.bankw);
3787 mt_aspect = eg_macro_tile_aspect(rdst->surface.u.legacy.mtilea);
3788 tile_split = eg_tile_split(rdst->surface.u.legacy.tile_split);
3789 base += rdst->resource.gpu_address;
3790 addr += rsrc->resource.gpu_address;
3791 }
3792
3793 size = (copy_height * pitch) / 4;
3794 ncopy = (size / EG_DMA_COPY_MAX_SIZE) + !!(size % EG_DMA_COPY_MAX_SIZE);
3795 r600_need_dma_space(&rctx->b, ncopy * 9, &rdst->resource, &rsrc->resource);
3796
3797 for (i = 0; i < ncopy; i++) {
3798 cheight = copy_height;
3799 if (((cheight * pitch) / 4) > EG_DMA_COPY_MAX_SIZE) {
3800 cheight = (EG_DMA_COPY_MAX_SIZE * 4) / pitch;
3801 }
3802 size = (cheight * pitch) / 4;
3803 /* emit reloc before writing cs so that cs is always in consistent state */
3804 radeon_add_to_buffer_list(&rctx->b, &rctx->b.dma, &rsrc->resource,
3805 RADEON_USAGE_READ, RADEON_PRIO_SDMA_TEXTURE);
3806 radeon_add_to_buffer_list(&rctx->b, &rctx->b.dma, &rdst->resource,
3807 RADEON_USAGE_WRITE, RADEON_PRIO_SDMA_TEXTURE);
3808 radeon_emit(cs, DMA_PACKET(DMA_PACKET_COPY, sub_cmd, size));
3809 radeon_emit(cs, base >> 8);
3810 radeon_emit(cs, (detile << 31) | (array_mode << 27) |
3811 (lbpp << 24) | (bank_h << 21) |
3812 (bank_w << 18) | (mt_aspect << 16));
3813 radeon_emit(cs, (pitch_tile_max << 0) | ((height - 1) << 16));
3814 radeon_emit(cs, (slice_tile_max << 0));
3815 radeon_emit(cs, (x << 0) | (z << 18));
3816 radeon_emit(cs, (y << 0) | (tile_split << 21) | (nbanks << 25) | (non_disp_tiling << 28));
3817 radeon_emit(cs, addr & 0xfffffffc);
3818 radeon_emit(cs, (addr >> 32UL) & 0xff);
3819 copy_height -= cheight;
3820 addr += cheight * pitch;
3821 y += cheight;
3822 }
3823 }
3824
3825 static void evergreen_dma_copy(struct pipe_context *ctx,
3826 struct pipe_resource *dst,
3827 unsigned dst_level,
3828 unsigned dstx, unsigned dsty, unsigned dstz,
3829 struct pipe_resource *src,
3830 unsigned src_level,
3831 const struct pipe_box *src_box)
3832 {
3833 struct r600_context *rctx = (struct r600_context *)ctx;
3834 struct r600_texture *rsrc = (struct r600_texture*)src;
3835 struct r600_texture *rdst = (struct r600_texture*)dst;
3836 unsigned dst_pitch, src_pitch, bpp, dst_mode, src_mode, copy_height;
3837 unsigned src_w, dst_w;
3838 unsigned src_x, src_y;
3839 unsigned dst_x = dstx, dst_y = dsty, dst_z = dstz;
3840
3841 if (rctx->b.dma.cs == NULL) {
3842 goto fallback;
3843 }
3844
3845 if (rctx->cmd_buf_is_compute) {
3846 rctx->b.gfx.flush(rctx, PIPE_FLUSH_ASYNC, NULL);
3847 rctx->cmd_buf_is_compute = false;
3848 }
3849
3850 if (dst->target == PIPE_BUFFER && src->target == PIPE_BUFFER) {
3851 evergreen_dma_copy_buffer(rctx, dst, src, dst_x, src_box->x, src_box->width);
3852 return;
3853 }
3854
3855 if (src_box->depth > 1 ||
3856 !r600_prepare_for_dma_blit(&rctx->b, rdst, dst_level, dstx, dsty,
3857 dstz, rsrc, src_level, src_box))
3858 goto fallback;
3859
3860 src_x = util_format_get_nblocksx(src->format, src_box->x);
3861 dst_x = util_format_get_nblocksx(src->format, dst_x);
3862 src_y = util_format_get_nblocksy(src->format, src_box->y);
3863 dst_y = util_format_get_nblocksy(src->format, dst_y);
3864
3865 bpp = rdst->surface.bpe;
3866 dst_pitch = rdst->surface.u.legacy.level[dst_level].nblk_x * rdst->surface.bpe;
3867 src_pitch = rsrc->surface.u.legacy.level[src_level].nblk_x * rsrc->surface.bpe;
3868 src_w = u_minify(rsrc->resource.b.b.width0, src_level);
3869 dst_w = u_minify(rdst->resource.b.b.width0, dst_level);
3870 copy_height = src_box->height / rsrc->surface.blk_h;
3871
3872 dst_mode = rdst->surface.u.legacy.level[dst_level].mode;
3873 src_mode = rsrc->surface.u.legacy.level[src_level].mode;
3874
3875 if (src_pitch != dst_pitch || src_box->x || dst_x || src_w != dst_w) {
3876 /* FIXME evergreen can do partial blit */
3877 goto fallback;
3878 }
3879 /* the x test here are currently useless (because we don't support partial blit)
3880 * but keep them around so we don't forget about those
3881 */
3882 if (src_pitch % 8 || src_box->x % 8 || dst_x % 8 || src_box->y % 8 || dst_y % 8) {
3883 goto fallback;
3884 }
3885
3886 /* 128 bpp surfaces require non_disp_tiling for both
3887 * tiled and linear buffers on cayman. However, async
3888 * DMA only supports it on the tiled side. As such
3889 * the tile order is backwards after a L2T/T2L packet.
3890 */
3891 if ((rctx->b.chip_class == CAYMAN) &&
3892 (src_mode != dst_mode) &&
3893 (util_format_get_blocksize(src->format) >= 16)) {
3894 goto fallback;
3895 }
3896
3897 if (src_mode == dst_mode) {
3898 uint64_t dst_offset, src_offset;
3899 /* simple dma blit would do NOTE code here assume :
3900 * src_box.x/y == 0
3901 * dst_x/y == 0
3902 * dst_pitch == src_pitch
3903 */
3904 src_offset= rsrc->surface.u.legacy.level[src_level].offset;
3905 src_offset += (uint64_t)rsrc->surface.u.legacy.level[src_level].slice_size_dw * 4 * src_box->z;
3906 src_offset += src_y * src_pitch + src_x * bpp;
3907 dst_offset = rdst->surface.u.legacy.level[dst_level].offset;
3908 dst_offset += (uint64_t)rdst->surface.u.legacy.level[dst_level].slice_size_dw * 4 * dst_z;
3909 dst_offset += dst_y * dst_pitch + dst_x * bpp;
3910 evergreen_dma_copy_buffer(rctx, dst, src, dst_offset, src_offset,
3911 src_box->height * src_pitch);
3912 } else {
3913 evergreen_dma_copy_tile(rctx, dst, dst_level, dst_x, dst_y, dst_z,
3914 src, src_level, src_x, src_y, src_box->z,
3915 copy_height, dst_pitch, bpp);
3916 }
3917 return;
3918
3919 fallback:
3920 r600_resource_copy_region(ctx, dst, dst_level, dstx, dsty, dstz,
3921 src, src_level, src_box);
3922 }
3923
3924 static void evergreen_set_tess_state(struct pipe_context *ctx,
3925 const float default_outer_level[4],
3926 const float default_inner_level[2])
3927 {
3928 struct r600_context *rctx = (struct r600_context *)ctx;
3929
3930 memcpy(rctx->tess_state, default_outer_level, sizeof(float) * 4);
3931 memcpy(rctx->tess_state+4, default_inner_level, sizeof(float) * 2);
3932 rctx->driver_consts[PIPE_SHADER_TESS_CTRL].tcs_default_levels_dirty = true;
3933 }
3934
3935 static void evergreen_setup_immed_buffer(struct r600_context *rctx,
3936 struct r600_image_view *rview,
3937 enum pipe_format pformat)
3938 {
3939 struct r600_screen *rscreen = (struct r600_screen *)rctx->b.b.screen;
3940 uint32_t immed_size = rscreen->b.info.max_se * 256 * 64 * util_format_get_blocksize(pformat);
3941 struct eg_buf_res_params buf_params;
3942 bool skip_reloc = false;
3943 struct r600_resource *resource = (struct r600_resource *)rview->base.resource;
3944 if (!resource->immed_buffer) {
3945 eg_resource_alloc_immed(&rscreen->b, resource, immed_size);
3946 }
3947
3948 memset(&buf_params, 0, sizeof(buf_params));
3949 buf_params.pipe_format = pformat;
3950 buf_params.size = resource->immed_buffer->b.b.width0;
3951 buf_params.swizzle[0] = PIPE_SWIZZLE_X;
3952 buf_params.swizzle[1] = PIPE_SWIZZLE_Y;
3953 buf_params.swizzle[2] = PIPE_SWIZZLE_Z;
3954 buf_params.swizzle[3] = PIPE_SWIZZLE_W;
3955 buf_params.uncached = 1;
3956 evergreen_fill_buffer_resource_words(rctx, &resource->immed_buffer->b.b,
3957 &buf_params, &skip_reloc,
3958 rview->immed_resource_words);
3959 }
3960
3961 static void evergreen_set_hw_atomic_buffers(struct pipe_context *ctx,
3962 unsigned start_slot,
3963 unsigned count,
3964 const struct pipe_shader_buffer *buffers)
3965 {
3966 struct r600_context *rctx = (struct r600_context *)ctx;
3967 struct r600_atomic_buffer_state *astate;
3968 int i, idx;
3969
3970 astate = &rctx->atomic_buffer_state;
3971
3972 /* we'd probably like to expand this to 8 later so put the logic in */
3973 for (i = start_slot, idx = 0; i < start_slot + count; i++, idx++) {
3974 const struct pipe_shader_buffer *buf;
3975 struct pipe_shader_buffer *abuf;
3976
3977 abuf = &astate->buffer[i];
3978
3979 if (!buffers || !buffers[idx].buffer) {
3980 pipe_resource_reference(&abuf->buffer, NULL);
3981 astate->enabled_mask &= ~(1 << i);
3982 continue;
3983 }
3984 buf = &buffers[idx];
3985
3986 pipe_resource_reference(&abuf->buffer, buf->buffer);
3987 abuf->buffer_offset = buf->buffer_offset;
3988 abuf->buffer_size = buf->buffer_size;
3989 astate->enabled_mask |= (1 << i);
3990 }
3991 }
3992
3993 static void evergreen_set_shader_buffers(struct pipe_context *ctx,
3994 enum pipe_shader_type shader, unsigned start_slot,
3995 unsigned count,
3996 const struct pipe_shader_buffer *buffers)
3997 {
3998 struct r600_context *rctx = (struct r600_context *)ctx;
3999 struct r600_image_state *istate = NULL;
4000 struct r600_image_view *rview;
4001 struct r600_tex_color_info color;
4002 struct eg_buf_res_params buf_params;
4003 struct r600_resource *resource;
4004 int i, idx;
4005 unsigned old_mask;
4006
4007 if (shader != PIPE_SHADER_FRAGMENT &&
4008 shader != PIPE_SHADER_COMPUTE && count == 0)
4009 return;
4010
4011 if (shader == PIPE_SHADER_FRAGMENT)
4012 istate = &rctx->fragment_buffers;
4013 else if (shader == PIPE_SHADER_COMPUTE)
4014 istate = &rctx->compute_buffers;
4015
4016 old_mask = istate->enabled_mask;
4017 for (i = start_slot, idx = 0; i < start_slot + count; i++, idx++) {
4018 const struct pipe_shader_buffer *buf;
4019 unsigned res_type;
4020
4021 rview = &istate->views[i];
4022
4023 if (!buffers || !buffers[idx].buffer) {
4024 pipe_resource_reference((struct pipe_resource **)&rview->base.resource, NULL);
4025 istate->enabled_mask &= ~(1 << i);
4026 continue;
4027 }
4028
4029 buf = &buffers[idx];
4030 pipe_resource_reference((struct pipe_resource **)&rview->base.resource, buf->buffer);
4031
4032 resource = (struct r600_resource *)rview->base.resource;
4033
4034 evergreen_setup_immed_buffer(rctx, rview, PIPE_FORMAT_R32_UINT);
4035
4036 color.offset = 0;
4037 color.view = 0;
4038 evergreen_set_color_surface_buffer(rctx, resource,
4039 PIPE_FORMAT_R32_UINT,
4040 buf->buffer_offset,
4041 buf->buffer_offset + buf->buffer_size,
4042 &color);
4043
4044 res_type = V_028C70_BUFFER;
4045
4046 rview->cb_color_base = color.offset;
4047 rview->cb_color_dim = color.dim;
4048 rview->cb_color_info = color.info |
4049 S_028C70_RAT(1) |
4050 S_028C70_RESOURCE_TYPE(res_type);
4051 rview->cb_color_pitch = color.pitch;
4052 rview->cb_color_slice = color.slice;
4053 rview->cb_color_view = color.view;
4054 rview->cb_color_attrib = color.attrib;
4055 rview->cb_color_fmask = color.fmask;
4056 rview->cb_color_fmask_slice = color.fmask_slice;
4057
4058 memset(&buf_params, 0, sizeof(buf_params));
4059 buf_params.pipe_format = PIPE_FORMAT_R32_UINT;
4060 buf_params.offset = buf->buffer_offset;
4061 buf_params.size = buf->buffer_size;
4062 buf_params.swizzle[0] = PIPE_SWIZZLE_X;
4063 buf_params.swizzle[1] = PIPE_SWIZZLE_Y;
4064 buf_params.swizzle[2] = PIPE_SWIZZLE_Z;
4065 buf_params.swizzle[3] = PIPE_SWIZZLE_W;
4066 buf_params.force_swizzle = true;
4067 buf_params.uncached = 1;
4068 buf_params.size_in_bytes = true;
4069 evergreen_fill_buffer_resource_words(rctx, &resource->b.b,
4070 &buf_params,
4071 &rview->skip_mip_address_reloc,
4072 rview->resource_words);
4073
4074 istate->enabled_mask |= (1 << i);
4075 }
4076
4077 istate->atom.num_dw = util_bitcount(istate->enabled_mask) * 46;
4078
4079 if (old_mask != istate->enabled_mask)
4080 r600_mark_atom_dirty(rctx, &rctx->framebuffer.atom);
4081
4082 /* construct the target mask */
4083 if (rctx->cb_misc_state.buffer_rat_enabled_mask != istate->enabled_mask) {
4084 rctx->cb_misc_state.buffer_rat_enabled_mask = istate->enabled_mask;
4085 r600_mark_atom_dirty(rctx, &rctx->cb_misc_state.atom);
4086 }
4087
4088 if (shader == PIPE_SHADER_FRAGMENT)
4089 r600_mark_atom_dirty(rctx, &istate->atom);
4090 }
4091
4092 static void evergreen_set_shader_images(struct pipe_context *ctx,
4093 enum pipe_shader_type shader, unsigned start_slot,
4094 unsigned count,
4095 const struct pipe_image_view *images)
4096 {
4097 struct r600_context *rctx = (struct r600_context *)ctx;
4098 int i;
4099 struct r600_image_view *rview;
4100 struct pipe_resource *image;
4101 struct r600_resource *resource;
4102 struct r600_tex_color_info color;
4103 struct eg_buf_res_params buf_params;
4104 struct eg_tex_res_params tex_params;
4105 unsigned old_mask;
4106 struct r600_image_state *istate = NULL;
4107 int idx;
4108 if (shader != PIPE_SHADER_FRAGMENT && shader != PIPE_SHADER_COMPUTE && count == 0)
4109 return;
4110
4111 if (shader == PIPE_SHADER_FRAGMENT)
4112 istate = &rctx->fragment_images;
4113 else if (shader == PIPE_SHADER_COMPUTE)
4114 istate = &rctx->compute_images;
4115
4116 assert (shader == PIPE_SHADER_FRAGMENT || shader == PIPE_SHADER_COMPUTE);
4117
4118 old_mask = istate->enabled_mask;
4119 for (i = start_slot, idx = 0; i < start_slot + count; i++, idx++) {
4120 unsigned res_type;
4121 const struct pipe_image_view *iview;
4122 rview = &istate->views[i];
4123
4124 if (!images || !images[idx].resource) {
4125 pipe_resource_reference((struct pipe_resource **)&rview->base.resource, NULL);
4126 istate->enabled_mask &= ~(1 << i);
4127 istate->compressed_colortex_mask &= ~(1 << i);
4128 istate->compressed_depthtex_mask &= ~(1 << i);
4129 continue;
4130 }
4131
4132 iview = &images[idx];
4133 image = iview->resource;
4134 resource = (struct r600_resource *)image;
4135
4136 r600_context_add_resource_size(ctx, image);
4137
4138 rview->base = *iview;
4139 rview->base.resource = NULL;
4140 pipe_resource_reference((struct pipe_resource **)&rview->base.resource, image);
4141
4142 evergreen_setup_immed_buffer(rctx, rview, iview->format);
4143
4144 bool is_buffer = image->target == PIPE_BUFFER;
4145 struct r600_texture *rtex = (struct r600_texture *)image;
4146 if (!is_buffer & rtex->db_compatible)
4147 istate->compressed_depthtex_mask |= 1 << i;
4148 else
4149 istate->compressed_depthtex_mask &= ~(1 << i);
4150
4151 if (!is_buffer && rtex->cmask.size)
4152 istate->compressed_colortex_mask |= 1 << i;
4153 else
4154 istate->compressed_colortex_mask &= ~(1 << i);
4155 if (!is_buffer) {
4156
4157 evergreen_set_color_surface_common(rctx, rtex,
4158 iview->u.tex.level,
4159 iview->u.tex.first_layer,
4160 iview->u.tex.last_layer,
4161 iview->format,
4162 &color);
4163 color.dim = S_028C78_WIDTH_MAX(u_minify(image->width0, iview->u.tex.level) - 1) |
4164 S_028C78_HEIGHT_MAX(u_minify(image->height0, iview->u.tex.level) - 1);
4165 } else {
4166 color.offset = 0;
4167 color.view = 0;
4168 evergreen_set_color_surface_buffer(rctx, resource,
4169 iview->format,
4170 iview->u.buf.offset,
4171 iview->u.buf.size,
4172 &color);
4173 }
4174
4175 switch (image->target) {
4176 case PIPE_BUFFER:
4177 res_type = V_028C70_BUFFER;
4178 break;
4179 case PIPE_TEXTURE_1D:
4180 res_type = V_028C70_TEXTURE1D;
4181 break;
4182 case PIPE_TEXTURE_1D_ARRAY:
4183 res_type = V_028C70_TEXTURE1DARRAY;
4184 break;
4185 case PIPE_TEXTURE_2D:
4186 case PIPE_TEXTURE_RECT:
4187 res_type = V_028C70_TEXTURE2D;
4188 break;
4189 case PIPE_TEXTURE_3D:
4190 res_type = V_028C70_TEXTURE3D;
4191 break;
4192 case PIPE_TEXTURE_2D_ARRAY:
4193 case PIPE_TEXTURE_CUBE:
4194 case PIPE_TEXTURE_CUBE_ARRAY:
4195 res_type = V_028C70_TEXTURE2DARRAY;
4196 break;
4197 default:
4198 assert(0);
4199 res_type = 0;
4200 break;
4201 }
4202
4203 rview->cb_color_base = color.offset;
4204 rview->cb_color_dim = color.dim;
4205 rview->cb_color_info = color.info |
4206 S_028C70_RAT(1) |
4207 S_028C70_RESOURCE_TYPE(res_type);
4208 rview->cb_color_pitch = color.pitch;
4209 rview->cb_color_slice = color.slice;
4210 rview->cb_color_view = color.view;
4211 rview->cb_color_attrib = color.attrib;
4212 rview->cb_color_fmask = color.fmask;
4213 rview->cb_color_fmask_slice = color.fmask_slice;
4214
4215 if (image->target != PIPE_BUFFER) {
4216 memset(&tex_params, 0, sizeof(tex_params));
4217 tex_params.pipe_format = iview->format;
4218 tex_params.force_level = 0;
4219 tex_params.width0 = image->width0;
4220 tex_params.height0 = image->height0;
4221 tex_params.first_level = iview->u.tex.level;
4222 tex_params.last_level = iview->u.tex.level;
4223 tex_params.first_layer = iview->u.tex.first_layer;
4224 tex_params.last_layer = iview->u.tex.last_layer;
4225 tex_params.target = image->target;
4226 tex_params.swizzle[0] = PIPE_SWIZZLE_X;
4227 tex_params.swizzle[1] = PIPE_SWIZZLE_Y;
4228 tex_params.swizzle[2] = PIPE_SWIZZLE_Z;
4229 tex_params.swizzle[3] = PIPE_SWIZZLE_W;
4230 evergreen_fill_tex_resource_words(rctx, &resource->b.b, &tex_params,
4231 &rview->skip_mip_address_reloc,
4232 rview->resource_words);
4233
4234 } else {
4235 memset(&buf_params, 0, sizeof(buf_params));
4236 buf_params.pipe_format = iview->format;
4237 buf_params.size = iview->u.buf.size;
4238 buf_params.offset = iview->u.buf.offset;
4239 buf_params.swizzle[0] = PIPE_SWIZZLE_X;
4240 buf_params.swizzle[1] = PIPE_SWIZZLE_Y;
4241 buf_params.swizzle[2] = PIPE_SWIZZLE_Z;
4242 buf_params.swizzle[3] = PIPE_SWIZZLE_W;
4243 evergreen_fill_buffer_resource_words(rctx, &resource->b.b,
4244 &buf_params,
4245 &rview->skip_mip_address_reloc,
4246 rview->resource_words);
4247 }
4248 istate->enabled_mask |= (1 << i);
4249 }
4250
4251 istate->atom.num_dw = util_bitcount(istate->enabled_mask) * 46;
4252 istate->dirty_buffer_constants = TRUE;
4253 rctx->b.flags |= R600_CONTEXT_WAIT_3D_IDLE | R600_CONTEXT_FLUSH_AND_INV;
4254 rctx->b.flags |= R600_CONTEXT_FLUSH_AND_INV_CB |
4255 R600_CONTEXT_FLUSH_AND_INV_CB_META;
4256
4257 if (old_mask != istate->enabled_mask)
4258 r600_mark_atom_dirty(rctx, &rctx->framebuffer.atom);
4259
4260 if (rctx->cb_misc_state.image_rat_enabled_mask != istate->enabled_mask) {
4261 rctx->cb_misc_state.image_rat_enabled_mask = istate->enabled_mask;
4262 r600_mark_atom_dirty(rctx, &rctx->cb_misc_state.atom);
4263 }
4264
4265 if (shader == PIPE_SHADER_FRAGMENT)
4266 r600_mark_atom_dirty(rctx, &istate->atom);
4267 }
4268
4269 static void evergreen_get_pipe_constant_buffer(struct r600_context *rctx,
4270 enum pipe_shader_type shader, uint slot,
4271 struct pipe_constant_buffer *cbuf)
4272 {
4273 struct r600_constbuf_state *state = &rctx->constbuf_state[shader];
4274 struct pipe_constant_buffer *cb;
4275 cbuf->user_buffer = NULL;
4276
4277 cb = &state->cb[slot];
4278
4279 cbuf->buffer_size = cb->buffer_size;
4280 pipe_resource_reference(&cbuf->buffer, cb->buffer);
4281 }
4282
4283 static void evergreen_get_shader_buffers(struct r600_context *rctx,
4284 enum pipe_shader_type shader,
4285 uint start_slot, uint count,
4286 struct pipe_shader_buffer *sbuf)
4287 {
4288 assert(shader == PIPE_SHADER_COMPUTE);
4289 int idx, i;
4290 struct r600_image_state *istate = &rctx->compute_buffers;
4291 struct r600_image_view *rview;
4292
4293 for (i = start_slot, idx = 0; i < start_slot + count; i++, idx++) {
4294
4295 rview = &istate->views[i];
4296
4297 pipe_resource_reference(&sbuf[idx].buffer, rview->base.resource);
4298 if (rview->base.resource) {
4299 uint64_t rview_va = ((struct r600_resource *)rview->base.resource)->gpu_address;
4300
4301 uint64_t prog_va = rview->resource_words[0];
4302
4303 prog_va += ((uint64_t)G_030008_BASE_ADDRESS_HI(rview->resource_words[2])) << 32;
4304 prog_va -= rview_va;
4305
4306 sbuf[idx].buffer_offset = prog_va & 0xffffffff;
4307 sbuf[idx].buffer_size = rview->resource_words[1] + 1;;
4308 } else {
4309 sbuf[idx].buffer_offset = 0;
4310 sbuf[idx].buffer_size = 0;
4311 }
4312 }
4313 }
4314
4315 static void evergreen_save_qbo_state(struct pipe_context *ctx, struct r600_qbo_state *st)
4316 {
4317 struct r600_context *rctx = (struct r600_context *)ctx;
4318 st->saved_compute = rctx->cs_shader_state.shader;
4319
4320 /* save constant buffer 0 */
4321 evergreen_get_pipe_constant_buffer(rctx, PIPE_SHADER_COMPUTE, 0, &st->saved_const0);
4322 /* save ssbo 0 */
4323 evergreen_get_shader_buffers(rctx, PIPE_SHADER_COMPUTE, 0, 3, st->saved_ssbo);
4324 }
4325
4326
4327 void evergreen_init_state_functions(struct r600_context *rctx)
4328 {
4329 unsigned id = 1;
4330 unsigned i;
4331 /* !!!
4332 * To avoid GPU lockup registers must be emitted in a specific order
4333 * (no kidding ...). The order below is important and have been
4334 * partially inferred from analyzing fglrx command stream.
4335 *
4336 * Don't reorder atom without carefully checking the effect (GPU lockup
4337 * or piglit regression).
4338 * !!!
4339 */
4340 if (rctx->b.chip_class == EVERGREEN) {
4341 r600_init_atom(rctx, &rctx->config_state.atom, id++, evergreen_emit_config_state, 11);
4342 rctx->config_state.dyn_gpr_enabled = true;
4343 }
4344 r600_init_atom(rctx, &rctx->framebuffer.atom, id++, evergreen_emit_framebuffer_state, 0);
4345 r600_init_atom(rctx, &rctx->fragment_images.atom, id++, evergreen_emit_fragment_image_state, 0);
4346 r600_init_atom(rctx, &rctx->compute_images.atom, id++, evergreen_emit_compute_image_state, 0);
4347 r600_init_atom(rctx, &rctx->fragment_buffers.atom, id++, evergreen_emit_fragment_buffer_state, 0);
4348 r600_init_atom(rctx, &rctx->compute_buffers.atom, id++, evergreen_emit_compute_buffer_state, 0);
4349 /* shader const */
4350 r600_init_atom(rctx, &rctx->constbuf_state[PIPE_SHADER_VERTEX].atom, id++, evergreen_emit_vs_constant_buffers, 0);
4351 r600_init_atom(rctx, &rctx->constbuf_state[PIPE_SHADER_GEOMETRY].atom, id++, evergreen_emit_gs_constant_buffers, 0);
4352 r600_init_atom(rctx, &rctx->constbuf_state[PIPE_SHADER_FRAGMENT].atom, id++, evergreen_emit_ps_constant_buffers, 0);
4353 r600_init_atom(rctx, &rctx->constbuf_state[PIPE_SHADER_TESS_CTRL].atom, id++, evergreen_emit_tcs_constant_buffers, 0);
4354 r600_init_atom(rctx, &rctx->constbuf_state[PIPE_SHADER_TESS_EVAL].atom, id++, evergreen_emit_tes_constant_buffers, 0);
4355 r600_init_atom(rctx, &rctx->constbuf_state[PIPE_SHADER_COMPUTE].atom, id++, evergreen_emit_cs_constant_buffers, 0);
4356 /* shader program */
4357 r600_init_atom(rctx, &rctx->cs_shader_state.atom, id++, evergreen_emit_cs_shader, 0);
4358 /* sampler */
4359 r600_init_atom(rctx, &rctx->samplers[PIPE_SHADER_VERTEX].states.atom, id++, evergreen_emit_vs_sampler_states, 0);
4360 r600_init_atom(rctx, &rctx->samplers[PIPE_SHADER_GEOMETRY].states.atom, id++, evergreen_emit_gs_sampler_states, 0);
4361 r600_init_atom(rctx, &rctx->samplers[PIPE_SHADER_TESS_CTRL].states.atom, id++, evergreen_emit_tcs_sampler_states, 0);
4362 r600_init_atom(rctx, &rctx->samplers[PIPE_SHADER_TESS_EVAL].states.atom, id++, evergreen_emit_tes_sampler_states, 0);
4363 r600_init_atom(rctx, &rctx->samplers[PIPE_SHADER_FRAGMENT].states.atom, id++, evergreen_emit_ps_sampler_states, 0);
4364 r600_init_atom(rctx, &rctx->samplers[PIPE_SHADER_COMPUTE].states.atom, id++, evergreen_emit_cs_sampler_states, 0);
4365 /* resources */
4366 r600_init_atom(rctx, &rctx->vertex_buffer_state.atom, id++, evergreen_fs_emit_vertex_buffers, 0);
4367 r600_init_atom(rctx, &rctx->cs_vertex_buffer_state.atom, id++, evergreen_cs_emit_vertex_buffers, 0);
4368 r600_init_atom(rctx, &rctx->samplers[PIPE_SHADER_VERTEX].views.atom, id++, evergreen_emit_vs_sampler_views, 0);
4369 r600_init_atom(rctx, &rctx->samplers[PIPE_SHADER_GEOMETRY].views.atom, id++, evergreen_emit_gs_sampler_views, 0);
4370 r600_init_atom(rctx, &rctx->samplers[PIPE_SHADER_TESS_CTRL].views.atom, id++, evergreen_emit_tcs_sampler_views, 0);
4371 r600_init_atom(rctx, &rctx->samplers[PIPE_SHADER_TESS_EVAL].views.atom, id++, evergreen_emit_tes_sampler_views, 0);
4372 r600_init_atom(rctx, &rctx->samplers[PIPE_SHADER_FRAGMENT].views.atom, id++, evergreen_emit_ps_sampler_views, 0);
4373 r600_init_atom(rctx, &rctx->samplers[PIPE_SHADER_COMPUTE].views.atom, id++, evergreen_emit_cs_sampler_views, 0);
4374
4375 r600_init_atom(rctx, &rctx->vgt_state.atom, id++, r600_emit_vgt_state, 10);
4376
4377 if (rctx->b.chip_class == EVERGREEN) {
4378 r600_init_atom(rctx, &rctx->sample_mask.atom, id++, evergreen_emit_sample_mask, 3);
4379 } else {
4380 r600_init_atom(rctx, &rctx->sample_mask.atom, id++, cayman_emit_sample_mask, 4);
4381 }
4382 rctx->sample_mask.sample_mask = ~0;
4383
4384 r600_init_atom(rctx, &rctx->alphatest_state.atom, id++, r600_emit_alphatest_state, 6);
4385 r600_init_atom(rctx, &rctx->blend_color.atom, id++, r600_emit_blend_color, 6);
4386 r600_init_atom(rctx, &rctx->blend_state.atom, id++, r600_emit_cso_state, 0);
4387 r600_init_atom(rctx, &rctx->cb_misc_state.atom, id++, evergreen_emit_cb_misc_state, 4);
4388 r600_init_atom(rctx, &rctx->clip_misc_state.atom, id++, r600_emit_clip_misc_state, 9);
4389 r600_init_atom(rctx, &rctx->clip_state.atom, id++, evergreen_emit_clip_state, 26);
4390 r600_init_atom(rctx, &rctx->db_misc_state.atom, id++, evergreen_emit_db_misc_state, 10);
4391 r600_init_atom(rctx, &rctx->db_state.atom, id++, evergreen_emit_db_state, 14);
4392 r600_init_atom(rctx, &rctx->dsa_state.atom, id++, r600_emit_cso_state, 0);
4393 r600_init_atom(rctx, &rctx->poly_offset_state.atom, id++, evergreen_emit_polygon_offset, 9);
4394 r600_init_atom(rctx, &rctx->rasterizer_state.atom, id++, r600_emit_cso_state, 0);
4395 r600_add_atom(rctx, &rctx->b.scissors.atom, id++);
4396 r600_add_atom(rctx, &rctx->b.viewports.atom, id++);
4397 r600_init_atom(rctx, &rctx->stencil_ref.atom, id++, r600_emit_stencil_ref, 4);
4398 r600_init_atom(rctx, &rctx->vertex_fetch_shader.atom, id++, evergreen_emit_vertex_fetch_shader, 5);
4399 r600_add_atom(rctx, &rctx->b.render_cond_atom, id++);
4400 r600_add_atom(rctx, &rctx->b.streamout.begin_atom, id++);
4401 r600_add_atom(rctx, &rctx->b.streamout.enable_atom, id++);
4402 for (i = 0; i < EG_NUM_HW_STAGES; i++)
4403 r600_init_atom(rctx, &rctx->hw_shader_stages[i].atom, id++, r600_emit_shader, 0);
4404 r600_init_atom(rctx, &rctx->shader_stages.atom, id++, evergreen_emit_shader_stages, 15);
4405 r600_init_atom(rctx, &rctx->gs_rings.atom, id++, evergreen_emit_gs_rings, 26);
4406
4407 rctx->b.b.create_blend_state = evergreen_create_blend_state;
4408 rctx->b.b.create_depth_stencil_alpha_state = evergreen_create_dsa_state;
4409 rctx->b.b.create_rasterizer_state = evergreen_create_rs_state;
4410 rctx->b.b.create_sampler_state = evergreen_create_sampler_state;
4411 rctx->b.b.create_sampler_view = evergreen_create_sampler_view;
4412 rctx->b.b.set_framebuffer_state = evergreen_set_framebuffer_state;
4413 rctx->b.b.set_polygon_stipple = evergreen_set_polygon_stipple;
4414 rctx->b.b.set_min_samples = evergreen_set_min_samples;
4415 rctx->b.b.set_tess_state = evergreen_set_tess_state;
4416 rctx->b.b.set_hw_atomic_buffers = evergreen_set_hw_atomic_buffers;
4417 rctx->b.b.set_shader_images = evergreen_set_shader_images;
4418 rctx->b.b.set_shader_buffers = evergreen_set_shader_buffers;
4419 if (rctx->b.chip_class == EVERGREEN)
4420 rctx->b.b.get_sample_position = evergreen_get_sample_position;
4421 else
4422 rctx->b.b.get_sample_position = cayman_get_sample_position;
4423 rctx->b.dma_copy = evergreen_dma_copy;
4424 rctx->b.save_qbo_state = evergreen_save_qbo_state;
4425
4426 evergreen_init_compute_state_functions(rctx);
4427 }
4428
4429 /**
4430 * This calculates the LDS size for tessellation shaders (VS, TCS, TES).
4431 *
4432 * The information about LDS and other non-compile-time parameters is then
4433 * written to the const buffer.
4434
4435 * const buffer contains -
4436 * uint32_t input_patch_size
4437 * uint32_t input_vertex_size
4438 * uint32_t num_tcs_input_cp
4439 * uint32_t num_tcs_output_cp;
4440 * uint32_t output_patch_size
4441 * uint32_t output_vertex_size
4442 * uint32_t output_patch0_offset
4443 * uint32_t perpatch_output_offset
4444 * and the same constbuf is bound to LS/HS/VS(ES).
4445 */
4446 void evergreen_setup_tess_constants(struct r600_context *rctx, const struct pipe_draw_info *info, unsigned *num_patches)
4447 {
4448 struct pipe_constant_buffer constbuf = {0};
4449 struct r600_pipe_shader_selector *tcs = rctx->tcs_shader ? rctx->tcs_shader : rctx->tes_shader;
4450 struct r600_pipe_shader_selector *ls = rctx->vs_shader;
4451 unsigned num_tcs_input_cp = info->vertices_per_patch;
4452 unsigned num_tcs_outputs;
4453 unsigned num_tcs_output_cp;
4454 unsigned num_tcs_patch_outputs;
4455 unsigned num_tcs_inputs;
4456 unsigned input_vertex_size, output_vertex_size;
4457 unsigned input_patch_size, pervertex_output_patch_size, output_patch_size;
4458 unsigned output_patch0_offset, perpatch_output_offset, lds_size;
4459 uint32_t values[8];
4460 unsigned num_waves;
4461 unsigned num_pipes = rctx->screen->b.info.r600_max_quad_pipes;
4462 unsigned wave_divisor = (16 * num_pipes);
4463
4464 *num_patches = 1;
4465
4466 if (!rctx->tes_shader) {
4467 rctx->lds_alloc = 0;
4468 rctx->b.b.set_constant_buffer(&rctx->b.b, PIPE_SHADER_VERTEX,
4469 R600_LDS_INFO_CONST_BUFFER, NULL);
4470 rctx->b.b.set_constant_buffer(&rctx->b.b, PIPE_SHADER_TESS_CTRL,
4471 R600_LDS_INFO_CONST_BUFFER, NULL);
4472 rctx->b.b.set_constant_buffer(&rctx->b.b, PIPE_SHADER_TESS_EVAL,
4473 R600_LDS_INFO_CONST_BUFFER, NULL);
4474 return;
4475 }
4476
4477 if (rctx->lds_alloc != 0 &&
4478 rctx->last_ls == ls &&
4479 rctx->last_num_tcs_input_cp == num_tcs_input_cp &&
4480 rctx->last_tcs == tcs)
4481 return;
4482
4483 num_tcs_inputs = util_last_bit64(ls->lds_outputs_written_mask);
4484
4485 if (rctx->tcs_shader) {
4486 num_tcs_outputs = util_last_bit64(tcs->lds_outputs_written_mask);
4487 num_tcs_output_cp = tcs->info.properties[TGSI_PROPERTY_TCS_VERTICES_OUT];
4488 num_tcs_patch_outputs = util_last_bit64(tcs->lds_patch_outputs_written_mask);
4489 } else {
4490 num_tcs_outputs = num_tcs_inputs;
4491 num_tcs_output_cp = num_tcs_input_cp;
4492 num_tcs_patch_outputs = 2; /* TESSINNER + TESSOUTER */
4493 }
4494
4495 /* size in bytes */
4496 input_vertex_size = num_tcs_inputs * 16;
4497 output_vertex_size = num_tcs_outputs * 16;
4498
4499 input_patch_size = num_tcs_input_cp * input_vertex_size;
4500
4501 pervertex_output_patch_size = num_tcs_output_cp * output_vertex_size;
4502 output_patch_size = pervertex_output_patch_size + num_tcs_patch_outputs * 16;
4503
4504 output_patch0_offset = rctx->tcs_shader ? input_patch_size * *num_patches : 0;
4505 perpatch_output_offset = output_patch0_offset + pervertex_output_patch_size;
4506
4507 lds_size = output_patch0_offset + output_patch_size * *num_patches;
4508
4509 values[0] = input_patch_size;
4510 values[1] = input_vertex_size;
4511 values[2] = num_tcs_input_cp;
4512 values[3] = num_tcs_output_cp;
4513
4514 values[4] = output_patch_size;
4515 values[5] = output_vertex_size;
4516 values[6] = output_patch0_offset;
4517 values[7] = perpatch_output_offset;
4518
4519 /* docs say HS_NUM_WAVES - CEIL((LS_HS_CONFIG.NUM_PATCHES *
4520 LS_HS_CONFIG.HS_NUM_OUTPUT_CP) / (NUM_GOOD_PIPES * 16)) */
4521 num_waves = ceilf((float)(*num_patches * num_tcs_output_cp) / (float)wave_divisor);
4522
4523 rctx->lds_alloc = (lds_size | (num_waves << 14));
4524
4525 rctx->last_ls = ls;
4526 rctx->last_tcs = tcs;
4527 rctx->last_num_tcs_input_cp = num_tcs_input_cp;
4528
4529 constbuf.user_buffer = values;
4530 constbuf.buffer_size = 8 * 4;
4531
4532 rctx->b.b.set_constant_buffer(&rctx->b.b, PIPE_SHADER_VERTEX,
4533 R600_LDS_INFO_CONST_BUFFER, &constbuf);
4534 rctx->b.b.set_constant_buffer(&rctx->b.b, PIPE_SHADER_TESS_CTRL,
4535 R600_LDS_INFO_CONST_BUFFER, &constbuf);
4536 rctx->b.b.set_constant_buffer(&rctx->b.b, PIPE_SHADER_TESS_EVAL,
4537 R600_LDS_INFO_CONST_BUFFER, &constbuf);
4538 pipe_resource_reference(&constbuf.buffer, NULL);
4539 }
4540
4541 uint32_t evergreen_get_ls_hs_config(struct r600_context *rctx,
4542 const struct pipe_draw_info *info,
4543 unsigned num_patches)
4544 {
4545 unsigned num_output_cp;
4546
4547 if (!rctx->tes_shader)
4548 return 0;
4549
4550 num_output_cp = rctx->tcs_shader ?
4551 rctx->tcs_shader->info.properties[TGSI_PROPERTY_TCS_VERTICES_OUT] :
4552 info->vertices_per_patch;
4553
4554 return S_028B58_NUM_PATCHES(num_patches) |
4555 S_028B58_HS_NUM_INPUT_CP(info->vertices_per_patch) |
4556 S_028B58_HS_NUM_OUTPUT_CP(num_output_cp);
4557 }
4558
4559 void evergreen_set_ls_hs_config(struct r600_context *rctx,
4560 struct radeon_winsys_cs *cs,
4561 uint32_t ls_hs_config)
4562 {
4563 radeon_set_context_reg(cs, R_028B58_VGT_LS_HS_CONFIG, ls_hs_config);
4564 }
4565
4566 void evergreen_set_lds_alloc(struct r600_context *rctx,
4567 struct radeon_winsys_cs *cs,
4568 uint32_t lds_alloc)
4569 {
4570 radeon_set_context_reg(cs, R_0288E8_SQ_LDS_ALLOC, lds_alloc);
4571 }
4572
4573 /* on evergreen if you are running tessellation you need to disable dynamic
4574 GPRs to workaround a hardware bug.*/
4575 bool evergreen_adjust_gprs(struct r600_context *rctx)
4576 {
4577 unsigned num_gprs[EG_NUM_HW_STAGES];
4578 unsigned def_gprs[EG_NUM_HW_STAGES];
4579 unsigned cur_gprs[EG_NUM_HW_STAGES];
4580 unsigned new_gprs[EG_NUM_HW_STAGES];
4581 unsigned def_num_clause_temp_gprs = rctx->r6xx_num_clause_temp_gprs;
4582 unsigned max_gprs;
4583 unsigned i;
4584 unsigned total_gprs;
4585 unsigned tmp[3];
4586 bool rework = false, set_default = false, set_dirty = false;
4587 max_gprs = 0;
4588 for (i = 0; i < EG_NUM_HW_STAGES; i++) {
4589 def_gprs[i] = rctx->default_gprs[i];
4590 max_gprs += def_gprs[i];
4591 }
4592 max_gprs += def_num_clause_temp_gprs * 2;
4593
4594 /* if we have no TESS and dyn gpr is enabled then do nothing. */
4595 if (!rctx->hw_shader_stages[EG_HW_STAGE_HS].shader) {
4596 if (rctx->config_state.dyn_gpr_enabled)
4597 return true;
4598
4599 /* transition back to dyn gpr enabled state */
4600 rctx->config_state.dyn_gpr_enabled = true;
4601 r600_mark_atom_dirty(rctx, &rctx->config_state.atom);
4602 rctx->b.flags |= R600_CONTEXT_WAIT_3D_IDLE;
4603 return true;
4604 }
4605
4606
4607 /* gather required shader gprs */
4608 for (i = 0; i < EG_NUM_HW_STAGES; i++) {
4609 if (rctx->hw_shader_stages[i].shader)
4610 num_gprs[i] = rctx->hw_shader_stages[i].shader->shader.bc.ngpr;
4611 else
4612 num_gprs[i] = 0;
4613 }
4614
4615 cur_gprs[R600_HW_STAGE_PS] = G_008C04_NUM_PS_GPRS(rctx->config_state.sq_gpr_resource_mgmt_1);
4616 cur_gprs[R600_HW_STAGE_VS] = G_008C04_NUM_VS_GPRS(rctx->config_state.sq_gpr_resource_mgmt_1);
4617 cur_gprs[R600_HW_STAGE_GS] = G_008C08_NUM_GS_GPRS(rctx->config_state.sq_gpr_resource_mgmt_2);
4618 cur_gprs[R600_HW_STAGE_ES] = G_008C08_NUM_ES_GPRS(rctx->config_state.sq_gpr_resource_mgmt_2);
4619 cur_gprs[EG_HW_STAGE_LS] = G_008C0C_NUM_LS_GPRS(rctx->config_state.sq_gpr_resource_mgmt_3);
4620 cur_gprs[EG_HW_STAGE_HS] = G_008C0C_NUM_HS_GPRS(rctx->config_state.sq_gpr_resource_mgmt_3);
4621
4622 total_gprs = 0;
4623 for (i = 0; i < EG_NUM_HW_STAGES; i++) {
4624 new_gprs[i] = num_gprs[i];
4625 total_gprs += num_gprs[i];
4626 }
4627
4628 if (total_gprs > (max_gprs - (2 * def_num_clause_temp_gprs)))
4629 return false;
4630
4631 for (i = 0; i < EG_NUM_HW_STAGES; i++) {
4632 if (new_gprs[i] > cur_gprs[i]) {
4633 rework = true;
4634 break;
4635 }
4636 }
4637
4638 if (rctx->config_state.dyn_gpr_enabled) {
4639 set_dirty = true;
4640 rctx->config_state.dyn_gpr_enabled = false;
4641 }
4642
4643 if (rework) {
4644 set_default = true;
4645 for (i = 0; i < EG_NUM_HW_STAGES; i++) {
4646 if (new_gprs[i] > def_gprs[i])
4647 set_default = false;
4648 }
4649
4650 if (set_default) {
4651 for (i = 0; i < EG_NUM_HW_STAGES; i++) {
4652 new_gprs[i] = def_gprs[i];
4653 }
4654 } else {
4655 unsigned ps_value = max_gprs;
4656
4657 ps_value -= (def_num_clause_temp_gprs * 2);
4658 for (i = R600_HW_STAGE_VS; i < EG_NUM_HW_STAGES; i++)
4659 ps_value -= new_gprs[i];
4660
4661 new_gprs[R600_HW_STAGE_PS] = ps_value;
4662 }
4663
4664 tmp[0] = S_008C04_NUM_PS_GPRS(new_gprs[R600_HW_STAGE_PS]) |
4665 S_008C04_NUM_VS_GPRS(new_gprs[R600_HW_STAGE_VS]) |
4666 S_008C04_NUM_CLAUSE_TEMP_GPRS(def_num_clause_temp_gprs);
4667
4668 tmp[1] = S_008C08_NUM_ES_GPRS(new_gprs[R600_HW_STAGE_ES]) |
4669 S_008C08_NUM_GS_GPRS(new_gprs[R600_HW_STAGE_GS]);
4670
4671 tmp[2] = S_008C0C_NUM_HS_GPRS(new_gprs[EG_HW_STAGE_HS]) |
4672 S_008C0C_NUM_LS_GPRS(new_gprs[EG_HW_STAGE_LS]);
4673
4674 if (rctx->config_state.sq_gpr_resource_mgmt_1 != tmp[0] ||
4675 rctx->config_state.sq_gpr_resource_mgmt_2 != tmp[1] ||
4676 rctx->config_state.sq_gpr_resource_mgmt_3 != tmp[2]) {
4677 rctx->config_state.sq_gpr_resource_mgmt_1 = tmp[0];
4678 rctx->config_state.sq_gpr_resource_mgmt_2 = tmp[1];
4679 rctx->config_state.sq_gpr_resource_mgmt_3 = tmp[2];
4680 set_dirty = true;
4681 }
4682 }
4683
4684
4685 if (set_dirty) {
4686 r600_mark_atom_dirty(rctx, &rctx->config_state.atom);
4687 rctx->b.flags |= R600_CONTEXT_WAIT_3D_IDLE;
4688 }
4689 return true;
4690 }
4691
4692 #define AC_ENCODE_TRACE_POINT(id) (0xcafe0000 | ((id) & 0xffff))
4693
4694 void eg_trace_emit(struct r600_context *rctx)
4695 {
4696 struct radeon_winsys_cs *cs = rctx->b.gfx.cs;
4697 unsigned reloc;
4698
4699 if (rctx->b.chip_class < EVERGREEN)
4700 return;
4701
4702 /* This must be done after r600_need_cs_space. */
4703 reloc = radeon_add_to_buffer_list(&rctx->b, &rctx->b.gfx,
4704 (struct r600_resource*)rctx->trace_buf, RADEON_USAGE_WRITE,
4705 RADEON_PRIO_CP_DMA);
4706
4707 rctx->trace_id++;
4708 radeon_add_to_buffer_list(&rctx->b, &rctx->b.gfx, rctx->trace_buf,
4709 RADEON_USAGE_READWRITE, RADEON_PRIO_TRACE);
4710 radeon_emit(cs, PKT3(PKT3_MEM_WRITE, 3, 0));
4711 radeon_emit(cs, rctx->trace_buf->gpu_address);
4712 radeon_emit(cs, rctx->trace_buf->gpu_address >> 32 | MEM_WRITE_32_BITS | MEM_WRITE_CONFIRM);
4713 radeon_emit(cs, rctx->trace_id);
4714 radeon_emit(cs, 0);
4715 radeon_emit(cs, PKT3(PKT3_NOP, 0, 0));
4716 radeon_emit(cs, reloc);
4717 radeon_emit(cs, PKT3(PKT3_NOP, 0, 0));
4718 radeon_emit(cs, AC_ENCODE_TRACE_POINT(rctx->trace_id));
4719 }
4720
4721 static void evergreen_emit_set_append_cnt(struct r600_context *rctx,
4722 struct r600_shader_atomic *atomic,
4723 struct r600_resource *resource,
4724 uint32_t pkt_flags)
4725 {
4726 struct radeon_winsys_cs *cs = rctx->b.gfx.cs;
4727 unsigned reloc = radeon_add_to_buffer_list(&rctx->b, &rctx->b.gfx,
4728 resource,
4729 RADEON_USAGE_READ,
4730 RADEON_PRIO_SHADER_RW_BUFFER);
4731 uint64_t dst_offset = resource->gpu_address + (atomic->start * 4);
4732 uint32_t base_reg_0 = R_02872C_GDS_APPEND_COUNT_0;
4733
4734 uint32_t reg_val = (base_reg_0 + atomic->hw_idx * 4 - EVERGREEN_CONTEXT_REG_OFFSET) >> 2;
4735
4736 radeon_emit(cs, PKT3(PKT3_SET_APPEND_CNT, 2, 0) | pkt_flags);
4737 radeon_emit(cs, (reg_val << 16) | 0x3);
4738 radeon_emit(cs, dst_offset & 0xfffffffc);
4739 radeon_emit(cs, (dst_offset >> 32) & 0xff);
4740 radeon_emit(cs, PKT3(PKT3_NOP, 0, 0));
4741 radeon_emit(cs, reloc);
4742 }
4743
4744 static void evergreen_emit_event_write_eos(struct r600_context *rctx,
4745 struct r600_shader_atomic *atomic,
4746 struct r600_resource *resource,
4747 uint32_t pkt_flags)
4748 {
4749 struct radeon_winsys_cs *cs = rctx->b.gfx.cs;
4750 uint32_t event = EVENT_TYPE_PS_DONE;
4751 uint32_t base_reg_0 = R_02872C_GDS_APPEND_COUNT_0;
4752 uint32_t reloc = radeon_add_to_buffer_list(&rctx->b, &rctx->b.gfx,
4753 resource,
4754 RADEON_USAGE_WRITE,
4755 RADEON_PRIO_SHADER_RW_BUFFER);
4756 uint64_t dst_offset = resource->gpu_address + (atomic->start * 4);
4757 uint32_t reg_val = (base_reg_0 + atomic->hw_idx * 4) >> 2;
4758
4759 if (pkt_flags == RADEON_CP_PACKET3_COMPUTE_MODE)
4760 event = EVENT_TYPE_CS_DONE;
4761
4762 radeon_emit(cs, PKT3(PKT3_EVENT_WRITE_EOS, 3, 0) | pkt_flags);
4763 radeon_emit(cs, EVENT_TYPE(event) | EVENT_INDEX(6));
4764 radeon_emit(cs, (dst_offset) & 0xffffffff);
4765 radeon_emit(cs, (0 << 29) | ((dst_offset >> 32) & 0xff));
4766 radeon_emit(cs, reg_val);
4767 radeon_emit(cs, PKT3(PKT3_NOP, 0, 0));
4768 radeon_emit(cs, reloc);
4769 }
4770
4771 static void cayman_emit_event_write_eos(struct r600_context *rctx,
4772 struct r600_shader_atomic *atomic,
4773 struct r600_resource *resource,
4774 uint32_t pkt_flags)
4775 {
4776 struct radeon_winsys_cs *cs = rctx->b.gfx.cs;
4777 uint32_t event = EVENT_TYPE_PS_DONE;
4778 uint32_t reloc = radeon_add_to_buffer_list(&rctx->b, &rctx->b.gfx,
4779 resource,
4780 RADEON_USAGE_WRITE,
4781 RADEON_PRIO_SHADER_RW_BUFFER);
4782 uint64_t dst_offset = resource->gpu_address + (atomic->start * 4);
4783
4784 if (pkt_flags == RADEON_CP_PACKET3_COMPUTE_MODE)
4785 event = EVENT_TYPE_CS_DONE;
4786
4787 radeon_emit(cs, PKT3(PKT3_EVENT_WRITE_EOS, 3, 0) | pkt_flags);
4788 radeon_emit(cs, EVENT_TYPE(event) | EVENT_INDEX(6));
4789 radeon_emit(cs, (dst_offset) & 0xffffffff);
4790 radeon_emit(cs, (1 << 29) | ((dst_offset >> 32) & 0xff));
4791 radeon_emit(cs, (atomic->hw_idx) | (1 << 16));
4792 radeon_emit(cs, PKT3(PKT3_NOP, 0, 0));
4793 radeon_emit(cs, reloc);
4794 }
4795
4796 /* writes count from a buffer into GDS */
4797 static void cayman_write_count_to_gds(struct r600_context *rctx,
4798 struct r600_shader_atomic *atomic,
4799 struct r600_resource *resource,
4800 uint32_t pkt_flags)
4801 {
4802 struct radeon_winsys_cs *cs = rctx->b.gfx.cs;
4803 unsigned reloc = radeon_add_to_buffer_list(&rctx->b, &rctx->b.gfx,
4804 resource,
4805 RADEON_USAGE_READ,
4806 RADEON_PRIO_SHADER_RW_BUFFER);
4807 uint64_t dst_offset = resource->gpu_address + (atomic->start * 4);
4808
4809 radeon_emit(cs, PKT3(PKT3_CP_DMA, 4, 0) | pkt_flags);
4810 radeon_emit(cs, dst_offset & 0xffffffff);
4811 radeon_emit(cs, PKT3_CP_DMA_CP_SYNC | PKT3_CP_DMA_DST_SEL(1) | ((dst_offset >> 32) & 0xff));// GDS
4812 radeon_emit(cs, atomic->hw_idx * 4);
4813 radeon_emit(cs, 0);
4814 radeon_emit(cs, PKT3_CP_DMA_CMD_DAS | 4);
4815 radeon_emit(cs, PKT3(PKT3_NOP, 0, 0));
4816 radeon_emit(cs, reloc);
4817 }
4818
4819 bool evergreen_emit_atomic_buffer_setup(struct r600_context *rctx,
4820 struct r600_pipe_shader *cs_shader,
4821 struct r600_shader_atomic *combined_atomics,
4822 uint8_t *atomic_used_mask_p)
4823 {
4824 struct r600_atomic_buffer_state *astate = &rctx->atomic_buffer_state;
4825 unsigned pkt_flags = 0;
4826 uint8_t atomic_used_mask = 0;
4827 int i, j, k;
4828 bool is_compute = cs_shader ? true : false;
4829
4830 if (is_compute)
4831 pkt_flags = RADEON_CP_PACKET3_COMPUTE_MODE;
4832
4833 for (i = 0; i < (is_compute ? 1 : EG_NUM_HW_STAGES); i++) {
4834 uint8_t num_atomic_stage;
4835 struct r600_pipe_shader *pshader;
4836
4837 if (is_compute)
4838 pshader = cs_shader;
4839 else
4840 pshader = rctx->hw_shader_stages[i].shader;
4841 if (!pshader)
4842 continue;
4843
4844 num_atomic_stage = pshader->shader.nhwatomic_ranges;
4845 if (!num_atomic_stage)
4846 continue;
4847
4848 for (j = 0; j < num_atomic_stage; j++) {
4849 struct r600_shader_atomic *atomic = &pshader->shader.atomics[j];
4850 int natomics = atomic->end - atomic->start + 1;
4851
4852 for (k = 0; k < natomics; k++) {
4853 /* seen this in a previous stage */
4854 if (atomic_used_mask & (1u << (atomic->hw_idx + k)))
4855 continue;
4856
4857 combined_atomics[atomic->hw_idx + k].hw_idx = atomic->hw_idx + k;
4858 combined_atomics[atomic->hw_idx + k].buffer_id = atomic->buffer_id;
4859 combined_atomics[atomic->hw_idx + k].start = atomic->start + k;
4860 combined_atomics[atomic->hw_idx + k].end = combined_atomics[atomic->hw_idx + k].start + 1;
4861 atomic_used_mask |= (1u << (atomic->hw_idx + k));
4862 }
4863 }
4864 }
4865
4866 uint32_t mask = atomic_used_mask;
4867 while (mask) {
4868 unsigned atomic_index = u_bit_scan(&mask);
4869 struct r600_shader_atomic *atomic = &combined_atomics[atomic_index];
4870 struct r600_resource *resource = r600_resource(astate->buffer[atomic->buffer_id].buffer);
4871 assert(resource);
4872
4873 if (rctx->b.chip_class == CAYMAN)
4874 cayman_write_count_to_gds(rctx, atomic, resource, pkt_flags);
4875 else
4876 evergreen_emit_set_append_cnt(rctx, atomic, resource, pkt_flags);
4877 }
4878 *atomic_used_mask_p = atomic_used_mask;
4879 return true;
4880 }
4881
4882 void evergreen_emit_atomic_buffer_save(struct r600_context *rctx,
4883 bool is_compute,
4884 struct r600_shader_atomic *combined_atomics,
4885 uint8_t *atomic_used_mask_p)
4886 {
4887 struct radeon_winsys_cs *cs = rctx->b.gfx.cs;
4888 struct r600_atomic_buffer_state *astate = &rctx->atomic_buffer_state;
4889 uint32_t pkt_flags = 0;
4890 uint32_t event = EVENT_TYPE_PS_DONE;
4891 uint32_t mask = astate->enabled_mask;
4892 uint64_t dst_offset;
4893 unsigned reloc;
4894
4895 if (is_compute)
4896 pkt_flags = RADEON_CP_PACKET3_COMPUTE_MODE;
4897
4898 mask = *atomic_used_mask_p;
4899 if (!mask)
4900 return;
4901
4902 while (mask) {
4903 unsigned atomic_index = u_bit_scan(&mask);
4904 struct r600_shader_atomic *atomic = &combined_atomics[atomic_index];
4905 struct r600_resource *resource = r600_resource(astate->buffer[atomic->buffer_id].buffer);
4906 assert(resource);
4907
4908 if (rctx->b.chip_class == CAYMAN)
4909 cayman_emit_event_write_eos(rctx, atomic, resource, pkt_flags);
4910 else
4911 evergreen_emit_event_write_eos(rctx, atomic, resource, pkt_flags);
4912 }
4913
4914 if (pkt_flags == RADEON_CP_PACKET3_COMPUTE_MODE)
4915 event = EVENT_TYPE_CS_DONE;
4916
4917 ++rctx->append_fence_id;
4918 reloc = radeon_add_to_buffer_list(&rctx->b, &rctx->b.gfx,
4919 r600_resource(rctx->append_fence),
4920 RADEON_USAGE_READWRITE,
4921 RADEON_PRIO_SHADER_RW_BUFFER);
4922 dst_offset = r600_resource(rctx->append_fence)->gpu_address;
4923 radeon_emit(cs, PKT3(PKT3_EVENT_WRITE_EOS, 3, 0) | pkt_flags);
4924 radeon_emit(cs, EVENT_TYPE(event) | EVENT_INDEX(6));
4925 radeon_emit(cs, dst_offset & 0xffffffff);
4926 radeon_emit(cs, (2 << 29) | ((dst_offset >> 32) & 0xff));
4927 radeon_emit(cs, rctx->append_fence_id);
4928 radeon_emit(cs, PKT3(PKT3_NOP, 0, 0));
4929 radeon_emit(cs, reloc);
4930
4931 radeon_emit(cs, PKT3(PKT3_WAIT_REG_MEM, 5, 0) | pkt_flags);
4932 radeon_emit(cs, WAIT_REG_MEM_GEQUAL | WAIT_REG_MEM_MEMORY | (1 << 8));
4933 radeon_emit(cs, dst_offset & 0xffffffff);
4934 radeon_emit(cs, ((dst_offset >> 32) & 0xff));
4935 radeon_emit(cs, rctx->append_fence_id);
4936 radeon_emit(cs, 0xffffffff);
4937 radeon_emit(cs, 0xa);
4938 radeon_emit(cs, PKT3(PKT3_NOP, 0, 0));
4939 radeon_emit(cs, reloc);
4940 }