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r600g: disable aniso filtering for non-mipmap textures on EG
[mesa.git] / src / gallium / drivers / r600 / evergreen_state.c
1 /*
2 * Copyright 2010 Jerome Glisse <glisse@freedesktop.org>
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * on the rights to use, copy, modify, merge, publish, distribute, sub
8 * license, and/or sell copies of the Software, and to permit persons to whom
9 * the Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
13 * Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHOR(S) AND/OR THEIR SUPPLIERS BE LIABLE FOR ANY CLAIM,
19 * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
20 * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
21 * USE OR OTHER DEALINGS IN THE SOFTWARE.
22 */
23 #include "r600_formats.h"
24 #include "r600_shader.h"
25 #include "evergreend.h"
26
27 #include "pipe/p_shader_tokens.h"
28 #include "util/u_pack_color.h"
29 #include "util/u_memory.h"
30 #include "util/u_framebuffer.h"
31 #include "util/u_dual_blend.h"
32 #include "evergreen_compute.h"
33 #include "util/u_math.h"
34
35 static inline unsigned evergreen_array_mode(unsigned mode)
36 {
37 switch (mode) {
38 case RADEON_SURF_MODE_LINEAR_ALIGNED: return V_028C70_ARRAY_LINEAR_ALIGNED;
39 break;
40 case RADEON_SURF_MODE_1D: return V_028C70_ARRAY_1D_TILED_THIN1;
41 break;
42 case RADEON_SURF_MODE_2D: return V_028C70_ARRAY_2D_TILED_THIN1;
43 default:
44 case RADEON_SURF_MODE_LINEAR: return V_028C70_ARRAY_LINEAR_GENERAL;
45 }
46 }
47
48 static uint32_t eg_num_banks(uint32_t nbanks)
49 {
50 switch (nbanks) {
51 case 2:
52 return 0;
53 case 4:
54 return 1;
55 case 8:
56 default:
57 return 2;
58 case 16:
59 return 3;
60 }
61 }
62
63
64 static unsigned eg_tile_split(unsigned tile_split)
65 {
66 switch (tile_split) {
67 case 64: tile_split = 0; break;
68 case 128: tile_split = 1; break;
69 case 256: tile_split = 2; break;
70 case 512: tile_split = 3; break;
71 default:
72 case 1024: tile_split = 4; break;
73 case 2048: tile_split = 5; break;
74 case 4096: tile_split = 6; break;
75 }
76 return tile_split;
77 }
78
79 static unsigned eg_macro_tile_aspect(unsigned macro_tile_aspect)
80 {
81 switch (macro_tile_aspect) {
82 default:
83 case 1: macro_tile_aspect = 0; break;
84 case 2: macro_tile_aspect = 1; break;
85 case 4: macro_tile_aspect = 2; break;
86 case 8: macro_tile_aspect = 3; break;
87 }
88 return macro_tile_aspect;
89 }
90
91 static unsigned eg_bank_wh(unsigned bankwh)
92 {
93 switch (bankwh) {
94 default:
95 case 1: bankwh = 0; break;
96 case 2: bankwh = 1; break;
97 case 4: bankwh = 2; break;
98 case 8: bankwh = 3; break;
99 }
100 return bankwh;
101 }
102
103 static uint32_t r600_translate_blend_function(int blend_func)
104 {
105 switch (blend_func) {
106 case PIPE_BLEND_ADD:
107 return V_028780_COMB_DST_PLUS_SRC;
108 case PIPE_BLEND_SUBTRACT:
109 return V_028780_COMB_SRC_MINUS_DST;
110 case PIPE_BLEND_REVERSE_SUBTRACT:
111 return V_028780_COMB_DST_MINUS_SRC;
112 case PIPE_BLEND_MIN:
113 return V_028780_COMB_MIN_DST_SRC;
114 case PIPE_BLEND_MAX:
115 return V_028780_COMB_MAX_DST_SRC;
116 default:
117 R600_ERR("Unknown blend function %d\n", blend_func);
118 assert(0);
119 break;
120 }
121 return 0;
122 }
123
124 static uint32_t r600_translate_blend_factor(int blend_fact)
125 {
126 switch (blend_fact) {
127 case PIPE_BLENDFACTOR_ONE:
128 return V_028780_BLEND_ONE;
129 case PIPE_BLENDFACTOR_SRC_COLOR:
130 return V_028780_BLEND_SRC_COLOR;
131 case PIPE_BLENDFACTOR_SRC_ALPHA:
132 return V_028780_BLEND_SRC_ALPHA;
133 case PIPE_BLENDFACTOR_DST_ALPHA:
134 return V_028780_BLEND_DST_ALPHA;
135 case PIPE_BLENDFACTOR_DST_COLOR:
136 return V_028780_BLEND_DST_COLOR;
137 case PIPE_BLENDFACTOR_SRC_ALPHA_SATURATE:
138 return V_028780_BLEND_SRC_ALPHA_SATURATE;
139 case PIPE_BLENDFACTOR_CONST_COLOR:
140 return V_028780_BLEND_CONST_COLOR;
141 case PIPE_BLENDFACTOR_CONST_ALPHA:
142 return V_028780_BLEND_CONST_ALPHA;
143 case PIPE_BLENDFACTOR_ZERO:
144 return V_028780_BLEND_ZERO;
145 case PIPE_BLENDFACTOR_INV_SRC_COLOR:
146 return V_028780_BLEND_ONE_MINUS_SRC_COLOR;
147 case PIPE_BLENDFACTOR_INV_SRC_ALPHA:
148 return V_028780_BLEND_ONE_MINUS_SRC_ALPHA;
149 case PIPE_BLENDFACTOR_INV_DST_ALPHA:
150 return V_028780_BLEND_ONE_MINUS_DST_ALPHA;
151 case PIPE_BLENDFACTOR_INV_DST_COLOR:
152 return V_028780_BLEND_ONE_MINUS_DST_COLOR;
153 case PIPE_BLENDFACTOR_INV_CONST_COLOR:
154 return V_028780_BLEND_ONE_MINUS_CONST_COLOR;
155 case PIPE_BLENDFACTOR_INV_CONST_ALPHA:
156 return V_028780_BLEND_ONE_MINUS_CONST_ALPHA;
157 case PIPE_BLENDFACTOR_SRC1_COLOR:
158 return V_028780_BLEND_SRC1_COLOR;
159 case PIPE_BLENDFACTOR_SRC1_ALPHA:
160 return V_028780_BLEND_SRC1_ALPHA;
161 case PIPE_BLENDFACTOR_INV_SRC1_COLOR:
162 return V_028780_BLEND_INV_SRC1_COLOR;
163 case PIPE_BLENDFACTOR_INV_SRC1_ALPHA:
164 return V_028780_BLEND_INV_SRC1_ALPHA;
165 default:
166 R600_ERR("Bad blend factor %d not supported!\n", blend_fact);
167 assert(0);
168 break;
169 }
170 return 0;
171 }
172
173 static unsigned r600_tex_dim(unsigned dim, unsigned nr_samples)
174 {
175 switch (dim) {
176 default:
177 case PIPE_TEXTURE_1D:
178 return V_030000_SQ_TEX_DIM_1D;
179 case PIPE_TEXTURE_1D_ARRAY:
180 return V_030000_SQ_TEX_DIM_1D_ARRAY;
181 case PIPE_TEXTURE_2D:
182 case PIPE_TEXTURE_RECT:
183 return nr_samples > 1 ? V_030000_SQ_TEX_DIM_2D_MSAA :
184 V_030000_SQ_TEX_DIM_2D;
185 case PIPE_TEXTURE_2D_ARRAY:
186 return nr_samples > 1 ? V_030000_SQ_TEX_DIM_2D_ARRAY_MSAA :
187 V_030000_SQ_TEX_DIM_2D_ARRAY;
188 case PIPE_TEXTURE_3D:
189 return V_030000_SQ_TEX_DIM_3D;
190 case PIPE_TEXTURE_CUBE:
191 case PIPE_TEXTURE_CUBE_ARRAY:
192 return V_030000_SQ_TEX_DIM_CUBEMAP;
193 }
194 }
195
196 static uint32_t r600_translate_dbformat(enum pipe_format format)
197 {
198 switch (format) {
199 case PIPE_FORMAT_Z16_UNORM:
200 return V_028040_Z_16;
201 case PIPE_FORMAT_Z24X8_UNORM:
202 case PIPE_FORMAT_Z24_UNORM_S8_UINT:
203 case PIPE_FORMAT_X8Z24_UNORM:
204 case PIPE_FORMAT_S8_UINT_Z24_UNORM:
205 return V_028040_Z_24;
206 case PIPE_FORMAT_Z32_FLOAT:
207 case PIPE_FORMAT_Z32_FLOAT_S8X24_UINT:
208 return V_028040_Z_32_FLOAT;
209 default:
210 return ~0U;
211 }
212 }
213
214 static bool r600_is_sampler_format_supported(struct pipe_screen *screen, enum pipe_format format)
215 {
216 return r600_translate_texformat(screen, format, NULL, NULL, NULL) != ~0U;
217 }
218
219 static bool r600_is_colorbuffer_format_supported(enum chip_class chip, enum pipe_format format)
220 {
221 return r600_translate_colorformat(chip, format) != ~0U &&
222 r600_translate_colorswap(format) != ~0U;
223 }
224
225 static bool r600_is_zs_format_supported(enum pipe_format format)
226 {
227 return r600_translate_dbformat(format) != ~0U;
228 }
229
230 boolean evergreen_is_format_supported(struct pipe_screen *screen,
231 enum pipe_format format,
232 enum pipe_texture_target target,
233 unsigned sample_count,
234 unsigned usage)
235 {
236 struct r600_screen *rscreen = (struct r600_screen*)screen;
237 unsigned retval = 0;
238
239 if (target >= PIPE_MAX_TEXTURE_TYPES) {
240 R600_ERR("r600: unsupported texture type %d\n", target);
241 return FALSE;
242 }
243
244 if (!util_format_is_supported(format, usage))
245 return FALSE;
246
247 if (sample_count > 1) {
248 if (!rscreen->has_msaa)
249 return FALSE;
250
251 switch (sample_count) {
252 case 2:
253 case 4:
254 case 8:
255 break;
256 default:
257 return FALSE;
258 }
259 }
260
261 if (usage & PIPE_BIND_SAMPLER_VIEW) {
262 if (target == PIPE_BUFFER) {
263 if (r600_is_vertex_format_supported(format))
264 retval |= PIPE_BIND_SAMPLER_VIEW;
265 } else {
266 if (r600_is_sampler_format_supported(screen, format))
267 retval |= PIPE_BIND_SAMPLER_VIEW;
268 }
269 }
270
271 if ((usage & (PIPE_BIND_RENDER_TARGET |
272 PIPE_BIND_DISPLAY_TARGET |
273 PIPE_BIND_SCANOUT |
274 PIPE_BIND_SHARED |
275 PIPE_BIND_BLENDABLE)) &&
276 r600_is_colorbuffer_format_supported(rscreen->b.chip_class, format)) {
277 retval |= usage &
278 (PIPE_BIND_RENDER_TARGET |
279 PIPE_BIND_DISPLAY_TARGET |
280 PIPE_BIND_SCANOUT |
281 PIPE_BIND_SHARED);
282 if (!util_format_is_pure_integer(format) &&
283 !util_format_is_depth_or_stencil(format))
284 retval |= usage & PIPE_BIND_BLENDABLE;
285 }
286
287 if ((usage & PIPE_BIND_DEPTH_STENCIL) &&
288 r600_is_zs_format_supported(format)) {
289 retval |= PIPE_BIND_DEPTH_STENCIL;
290 }
291
292 if ((usage & PIPE_BIND_VERTEX_BUFFER) &&
293 r600_is_vertex_format_supported(format)) {
294 retval |= PIPE_BIND_VERTEX_BUFFER;
295 }
296
297 if (usage & PIPE_BIND_TRANSFER_READ)
298 retval |= PIPE_BIND_TRANSFER_READ;
299 if (usage & PIPE_BIND_TRANSFER_WRITE)
300 retval |= PIPE_BIND_TRANSFER_WRITE;
301
302 if ((usage & PIPE_BIND_LINEAR) &&
303 !util_format_is_compressed(format) &&
304 !(usage & PIPE_BIND_DEPTH_STENCIL))
305 retval |= PIPE_BIND_LINEAR;
306
307 return retval == usage;
308 }
309
310 static void *evergreen_create_blend_state_mode(struct pipe_context *ctx,
311 const struct pipe_blend_state *state, int mode)
312 {
313 uint32_t color_control = 0, target_mask = 0;
314 struct r600_blend_state *blend = CALLOC_STRUCT(r600_blend_state);
315
316 if (!blend) {
317 return NULL;
318 }
319
320 r600_init_command_buffer(&blend->buffer, 20);
321 r600_init_command_buffer(&blend->buffer_no_blend, 20);
322
323 if (state->logicop_enable) {
324 color_control |= (state->logicop_func << 16) | (state->logicop_func << 20);
325 } else {
326 color_control |= (0xcc << 16);
327 }
328 /* we pretend 8 buffer are used, CB_SHADER_MASK will disable unused one */
329 if (state->independent_blend_enable) {
330 for (int i = 0; i < 8; i++) {
331 target_mask |= (state->rt[i].colormask << (4 * i));
332 }
333 } else {
334 for (int i = 0; i < 8; i++) {
335 target_mask |= (state->rt[0].colormask << (4 * i));
336 }
337 }
338
339 /* only have dual source on MRT0 */
340 blend->dual_src_blend = util_blend_state_is_dual(state, 0);
341 blend->cb_target_mask = target_mask;
342 blend->alpha_to_one = state->alpha_to_one;
343
344 if (target_mask)
345 color_control |= S_028808_MODE(mode);
346 else
347 color_control |= S_028808_MODE(V_028808_CB_DISABLE);
348
349
350 r600_store_context_reg(&blend->buffer, R_028808_CB_COLOR_CONTROL, color_control);
351 r600_store_context_reg(&blend->buffer, R_028B70_DB_ALPHA_TO_MASK,
352 S_028B70_ALPHA_TO_MASK_ENABLE(state->alpha_to_coverage) |
353 S_028B70_ALPHA_TO_MASK_OFFSET0(2) |
354 S_028B70_ALPHA_TO_MASK_OFFSET1(2) |
355 S_028B70_ALPHA_TO_MASK_OFFSET2(2) |
356 S_028B70_ALPHA_TO_MASK_OFFSET3(2));
357 r600_store_context_reg_seq(&blend->buffer, R_028780_CB_BLEND0_CONTROL, 8);
358
359 /* Copy over the dwords set so far into buffer_no_blend.
360 * Only the CB_BLENDi_CONTROL registers must be set after this. */
361 memcpy(blend->buffer_no_blend.buf, blend->buffer.buf, blend->buffer.num_dw * 4);
362 blend->buffer_no_blend.num_dw = blend->buffer.num_dw;
363
364 for (int i = 0; i < 8; i++) {
365 /* state->rt entries > 0 only written if independent blending */
366 const int j = state->independent_blend_enable ? i : 0;
367
368 unsigned eqRGB = state->rt[j].rgb_func;
369 unsigned srcRGB = state->rt[j].rgb_src_factor;
370 unsigned dstRGB = state->rt[j].rgb_dst_factor;
371 unsigned eqA = state->rt[j].alpha_func;
372 unsigned srcA = state->rt[j].alpha_src_factor;
373 unsigned dstA = state->rt[j].alpha_dst_factor;
374 uint32_t bc = 0;
375
376 r600_store_value(&blend->buffer_no_blend, 0);
377
378 if (!state->rt[j].blend_enable) {
379 r600_store_value(&blend->buffer, 0);
380 continue;
381 }
382
383 bc |= S_028780_BLEND_CONTROL_ENABLE(1);
384 bc |= S_028780_COLOR_COMB_FCN(r600_translate_blend_function(eqRGB));
385 bc |= S_028780_COLOR_SRCBLEND(r600_translate_blend_factor(srcRGB));
386 bc |= S_028780_COLOR_DESTBLEND(r600_translate_blend_factor(dstRGB));
387
388 if (srcA != srcRGB || dstA != dstRGB || eqA != eqRGB) {
389 bc |= S_028780_SEPARATE_ALPHA_BLEND(1);
390 bc |= S_028780_ALPHA_COMB_FCN(r600_translate_blend_function(eqA));
391 bc |= S_028780_ALPHA_SRCBLEND(r600_translate_blend_factor(srcA));
392 bc |= S_028780_ALPHA_DESTBLEND(r600_translate_blend_factor(dstA));
393 }
394 r600_store_value(&blend->buffer, bc);
395 }
396 return blend;
397 }
398
399 static void *evergreen_create_blend_state(struct pipe_context *ctx,
400 const struct pipe_blend_state *state)
401 {
402
403 return evergreen_create_blend_state_mode(ctx, state, V_028808_CB_NORMAL);
404 }
405
406 static void *evergreen_create_dsa_state(struct pipe_context *ctx,
407 const struct pipe_depth_stencil_alpha_state *state)
408 {
409 unsigned db_depth_control, alpha_test_control, alpha_ref;
410 struct r600_dsa_state *dsa = CALLOC_STRUCT(r600_dsa_state);
411
412 if (!dsa) {
413 return NULL;
414 }
415
416 r600_init_command_buffer(&dsa->buffer, 3);
417
418 dsa->valuemask[0] = state->stencil[0].valuemask;
419 dsa->valuemask[1] = state->stencil[1].valuemask;
420 dsa->writemask[0] = state->stencil[0].writemask;
421 dsa->writemask[1] = state->stencil[1].writemask;
422 dsa->zwritemask = state->depth.writemask;
423
424 db_depth_control = S_028800_Z_ENABLE(state->depth.enabled) |
425 S_028800_Z_WRITE_ENABLE(state->depth.writemask) |
426 S_028800_ZFUNC(state->depth.func);
427
428 /* stencil */
429 if (state->stencil[0].enabled) {
430 db_depth_control |= S_028800_STENCIL_ENABLE(1);
431 db_depth_control |= S_028800_STENCILFUNC(state->stencil[0].func); /* translates straight */
432 db_depth_control |= S_028800_STENCILFAIL(r600_translate_stencil_op(state->stencil[0].fail_op));
433 db_depth_control |= S_028800_STENCILZPASS(r600_translate_stencil_op(state->stencil[0].zpass_op));
434 db_depth_control |= S_028800_STENCILZFAIL(r600_translate_stencil_op(state->stencil[0].zfail_op));
435
436 if (state->stencil[1].enabled) {
437 db_depth_control |= S_028800_BACKFACE_ENABLE(1);
438 db_depth_control |= S_028800_STENCILFUNC_BF(state->stencil[1].func); /* translates straight */
439 db_depth_control |= S_028800_STENCILFAIL_BF(r600_translate_stencil_op(state->stencil[1].fail_op));
440 db_depth_control |= S_028800_STENCILZPASS_BF(r600_translate_stencil_op(state->stencil[1].zpass_op));
441 db_depth_control |= S_028800_STENCILZFAIL_BF(r600_translate_stencil_op(state->stencil[1].zfail_op));
442 }
443 }
444
445 /* alpha */
446 alpha_test_control = 0;
447 alpha_ref = 0;
448 if (state->alpha.enabled) {
449 alpha_test_control = S_028410_ALPHA_FUNC(state->alpha.func);
450 alpha_test_control |= S_028410_ALPHA_TEST_ENABLE(1);
451 alpha_ref = fui(state->alpha.ref_value);
452 }
453 dsa->sx_alpha_test_control = alpha_test_control & 0xff;
454 dsa->alpha_ref = alpha_ref;
455
456 /* misc */
457 r600_store_context_reg(&dsa->buffer, R_028800_DB_DEPTH_CONTROL, db_depth_control);
458 return dsa;
459 }
460
461 static void *evergreen_create_rs_state(struct pipe_context *ctx,
462 const struct pipe_rasterizer_state *state)
463 {
464 struct r600_context *rctx = (struct r600_context *)ctx;
465 unsigned tmp, spi_interp;
466 float psize_min, psize_max;
467 struct r600_rasterizer_state *rs = CALLOC_STRUCT(r600_rasterizer_state);
468
469 if (!rs) {
470 return NULL;
471 }
472
473 r600_init_command_buffer(&rs->buffer, 30);
474
475 rs->flatshade = state->flatshade;
476 rs->sprite_coord_enable = state->sprite_coord_enable;
477 rs->two_side = state->light_twoside;
478 rs->clip_plane_enable = state->clip_plane_enable;
479 rs->pa_sc_line_stipple = state->line_stipple_enable ?
480 S_028A0C_LINE_PATTERN(state->line_stipple_pattern) |
481 S_028A0C_REPEAT_COUNT(state->line_stipple_factor) : 0;
482 rs->pa_cl_clip_cntl =
483 S_028810_PS_UCP_MODE(3) |
484 S_028810_DX_CLIP_SPACE_DEF(state->clip_halfz) |
485 S_028810_ZCLIP_NEAR_DISABLE(!state->depth_clip) |
486 S_028810_ZCLIP_FAR_DISABLE(!state->depth_clip) |
487 S_028810_DX_LINEAR_ATTR_CLIP_ENA(1) |
488 S_028810_DX_RASTERIZATION_KILL(state->rasterizer_discard);
489 rs->multisample_enable = state->multisample;
490
491 /* offset */
492 rs->offset_units = state->offset_units;
493 rs->offset_scale = state->offset_scale * 16.0f;
494 rs->offset_enable = state->offset_point || state->offset_line || state->offset_tri;
495
496 if (state->point_size_per_vertex) {
497 psize_min = util_get_min_point_size(state);
498 psize_max = 8192;
499 } else {
500 /* Force the point size to be as if the vertex output was disabled. */
501 psize_min = state->point_size;
502 psize_max = state->point_size;
503 }
504
505 spi_interp = S_0286D4_FLAT_SHADE_ENA(1);
506 if (state->sprite_coord_enable) {
507 spi_interp |= S_0286D4_PNT_SPRITE_ENA(1) |
508 S_0286D4_PNT_SPRITE_OVRD_X(2) |
509 S_0286D4_PNT_SPRITE_OVRD_Y(3) |
510 S_0286D4_PNT_SPRITE_OVRD_Z(0) |
511 S_0286D4_PNT_SPRITE_OVRD_W(1);
512 if (state->sprite_coord_mode != PIPE_SPRITE_COORD_UPPER_LEFT) {
513 spi_interp |= S_0286D4_PNT_SPRITE_TOP_1(1);
514 }
515 }
516
517 r600_store_context_reg_seq(&rs->buffer, R_028A00_PA_SU_POINT_SIZE, 3);
518 /* point size 12.4 fixed point (divide by two, because 0.5 = 1 pixel) */
519 tmp = r600_pack_float_12p4(state->point_size/2);
520 r600_store_value(&rs->buffer, /* R_028A00_PA_SU_POINT_SIZE */
521 S_028A00_HEIGHT(tmp) | S_028A00_WIDTH(tmp));
522 r600_store_value(&rs->buffer, /* R_028A04_PA_SU_POINT_MINMAX */
523 S_028A04_MIN_SIZE(r600_pack_float_12p4(psize_min/2)) |
524 S_028A04_MAX_SIZE(r600_pack_float_12p4(psize_max/2)));
525 r600_store_value(&rs->buffer, /* R_028A08_PA_SU_LINE_CNTL */
526 S_028A08_WIDTH((unsigned)(state->line_width * 8)));
527
528 r600_store_context_reg(&rs->buffer, R_0286D4_SPI_INTERP_CONTROL_0, spi_interp);
529 r600_store_context_reg(&rs->buffer, R_028A48_PA_SC_MODE_CNTL_0,
530 S_028A48_MSAA_ENABLE(state->multisample) |
531 S_028A48_VPORT_SCISSOR_ENABLE(state->scissor) |
532 S_028A48_LINE_STIPPLE_ENABLE(state->line_stipple_enable));
533
534 if (rctx->b.chip_class == CAYMAN) {
535 r600_store_context_reg(&rs->buffer, CM_R_028BE4_PA_SU_VTX_CNTL,
536 S_028C08_PIX_CENTER_HALF(state->half_pixel_center) |
537 S_028C08_QUANT_MODE(V_028C08_X_1_256TH));
538 } else {
539 r600_store_context_reg(&rs->buffer, R_028C08_PA_SU_VTX_CNTL,
540 S_028C08_PIX_CENTER_HALF(state->half_pixel_center) |
541 S_028C08_QUANT_MODE(V_028C08_X_1_256TH));
542 }
543
544 r600_store_context_reg(&rs->buffer, R_028B7C_PA_SU_POLY_OFFSET_CLAMP, fui(state->offset_clamp));
545 r600_store_context_reg(&rs->buffer, R_028814_PA_SU_SC_MODE_CNTL,
546 S_028814_PROVOKING_VTX_LAST(!state->flatshade_first) |
547 S_028814_CULL_FRONT((state->cull_face & PIPE_FACE_FRONT) ? 1 : 0) |
548 S_028814_CULL_BACK((state->cull_face & PIPE_FACE_BACK) ? 1 : 0) |
549 S_028814_FACE(!state->front_ccw) |
550 S_028814_POLY_OFFSET_FRONT_ENABLE(util_get_offset(state, state->fill_front)) |
551 S_028814_POLY_OFFSET_BACK_ENABLE(util_get_offset(state, state->fill_back)) |
552 S_028814_POLY_OFFSET_PARA_ENABLE(state->offset_point || state->offset_line) |
553 S_028814_POLY_MODE(state->fill_front != PIPE_POLYGON_MODE_FILL ||
554 state->fill_back != PIPE_POLYGON_MODE_FILL) |
555 S_028814_POLYMODE_FRONT_PTYPE(r600_translate_fill(state->fill_front)) |
556 S_028814_POLYMODE_BACK_PTYPE(r600_translate_fill(state->fill_back)));
557 return rs;
558 }
559
560 static void *evergreen_create_sampler_state(struct pipe_context *ctx,
561 const struct pipe_sampler_state *state)
562 {
563 struct r600_pipe_sampler_state *ss = CALLOC_STRUCT(r600_pipe_sampler_state);
564
565 if (!ss) {
566 return NULL;
567 }
568
569 ss->border_color_use = sampler_state_needs_border_color(state);
570
571 /* R_03C000_SQ_TEX_SAMPLER_WORD0_0 */
572 ss->tex_sampler_words[0] =
573 S_03C000_CLAMP_X(r600_tex_wrap(state->wrap_s)) |
574 S_03C000_CLAMP_Y(r600_tex_wrap(state->wrap_t)) |
575 S_03C000_CLAMP_Z(r600_tex_wrap(state->wrap_r)) |
576 S_03C000_XY_MAG_FILTER(eg_tex_filter(state->mag_img_filter, state->max_anisotropy)) |
577 S_03C000_XY_MIN_FILTER(eg_tex_filter(state->min_img_filter, state->max_anisotropy)) |
578 S_03C000_MIP_FILTER(r600_tex_mipfilter(state->min_mip_filter)) |
579 S_03C000_MAX_ANISO_RATIO(r600_tex_aniso_filter(state->max_anisotropy)) |
580 S_03C000_DEPTH_COMPARE_FUNCTION(r600_tex_compare(state->compare_func)) |
581 S_03C000_BORDER_COLOR_TYPE(ss->border_color_use ? V_03C000_SQ_TEX_BORDER_COLOR_REGISTER : 0);
582 /* R_03C004_SQ_TEX_SAMPLER_WORD1_0 */
583 ss->tex_sampler_words[1] =
584 S_03C004_MIN_LOD(S_FIXED(CLAMP(state->min_lod, 0, 15), 8)) |
585 S_03C004_MAX_LOD(S_FIXED(CLAMP(state->max_lod, 0, 15), 8));
586 /* R_03C008_SQ_TEX_SAMPLER_WORD2_0 */
587 ss->tex_sampler_words[2] =
588 S_03C008_LOD_BIAS(S_FIXED(CLAMP(state->lod_bias, -16, 16), 8)) |
589 (state->seamless_cube_map ? 0 : S_03C008_DISABLE_CUBE_WRAP(1)) |
590 S_03C008_TYPE(1);
591
592 if (ss->border_color_use) {
593 memcpy(&ss->border_color, &state->border_color, sizeof(state->border_color));
594 }
595 return ss;
596 }
597
598 static struct pipe_sampler_view *
599 texture_buffer_sampler_view(struct r600_context *rctx,
600 struct r600_pipe_sampler_view *view,
601 unsigned width0, unsigned height0)
602
603 {
604 struct r600_texture *tmp = (struct r600_texture*)view->base.texture;
605 uint64_t va;
606 int stride = util_format_get_blocksize(view->base.format);
607 unsigned format, num_format, format_comp, endian;
608 unsigned swizzle_res;
609 unsigned char swizzle[4];
610 const struct util_format_description *desc;
611 unsigned offset = view->base.u.buf.first_element * stride;
612 unsigned size = (view->base.u.buf.last_element - view->base.u.buf.first_element + 1) * stride;
613
614 swizzle[0] = view->base.swizzle_r;
615 swizzle[1] = view->base.swizzle_g;
616 swizzle[2] = view->base.swizzle_b;
617 swizzle[3] = view->base.swizzle_a;
618
619 r600_vertex_data_type(view->base.format,
620 &format, &num_format, &format_comp,
621 &endian);
622
623 desc = util_format_description(view->base.format);
624
625 swizzle_res = r600_get_swizzle_combined(desc->swizzle, swizzle, TRUE);
626
627 va = tmp->resource.gpu_address + offset;
628 view->tex_resource = &tmp->resource;
629
630 view->skip_mip_address_reloc = true;
631 view->tex_resource_words[0] = va;
632 view->tex_resource_words[1] = size - 1;
633 view->tex_resource_words[2] = S_030008_BASE_ADDRESS_HI(va >> 32UL) |
634 S_030008_STRIDE(stride) |
635 S_030008_DATA_FORMAT(format) |
636 S_030008_NUM_FORMAT_ALL(num_format) |
637 S_030008_FORMAT_COMP_ALL(format_comp) |
638 S_030008_ENDIAN_SWAP(endian);
639 view->tex_resource_words[3] = swizzle_res;
640 /*
641 * in theory dword 4 is for number of elements, for use with resinfo,
642 * but it seems to utterly fail to work, the amd gpu shader analyser
643 * uses a const buffer to store the element sizes for buffer txq
644 */
645 view->tex_resource_words[4] = 0;
646 view->tex_resource_words[5] = view->tex_resource_words[6] = 0;
647 view->tex_resource_words[7] = S_03001C_TYPE(V_03001C_SQ_TEX_VTX_VALID_BUFFER);
648
649 if (tmp->resource.gpu_address)
650 LIST_ADDTAIL(&view->list, &rctx->b.texture_buffers);
651 return &view->base;
652 }
653
654 struct pipe_sampler_view *
655 evergreen_create_sampler_view_custom(struct pipe_context *ctx,
656 struct pipe_resource *texture,
657 const struct pipe_sampler_view *state,
658 unsigned width0, unsigned height0,
659 unsigned force_level)
660 {
661 struct r600_context *rctx = (struct r600_context*)ctx;
662 struct r600_screen *rscreen = (struct r600_screen*)ctx->screen;
663 struct r600_pipe_sampler_view *view = CALLOC_STRUCT(r600_pipe_sampler_view);
664 struct r600_texture *tmp = (struct r600_texture*)texture;
665 unsigned format, endian;
666 uint32_t word4 = 0, yuv_format = 0, pitch = 0;
667 unsigned char swizzle[4], array_mode = 0, non_disp_tiling = 0;
668 unsigned height, depth, width;
669 unsigned macro_aspect, tile_split, bankh, bankw, nbanks, fmask_bankh;
670 enum pipe_format pipe_format = state->format;
671 struct radeon_surf_level *surflevel;
672 unsigned base_level, first_level, last_level;
673 unsigned dim, last_layer;
674 uint64_t va;
675
676 if (!view)
677 return NULL;
678
679 /* initialize base object */
680 view->base = *state;
681 view->base.texture = NULL;
682 pipe_reference(NULL, &texture->reference);
683 view->base.texture = texture;
684 view->base.reference.count = 1;
685 view->base.context = ctx;
686
687 if (state->target == PIPE_BUFFER)
688 return texture_buffer_sampler_view(rctx, view, width0, height0);
689
690 swizzle[0] = state->swizzle_r;
691 swizzle[1] = state->swizzle_g;
692 swizzle[2] = state->swizzle_b;
693 swizzle[3] = state->swizzle_a;
694
695 tile_split = tmp->surface.tile_split;
696 surflevel = tmp->surface.level;
697
698 /* Texturing with separate depth and stencil. */
699 if (tmp->is_depth && !tmp->is_flushing_texture) {
700 switch (pipe_format) {
701 case PIPE_FORMAT_Z32_FLOAT_S8X24_UINT:
702 pipe_format = PIPE_FORMAT_Z32_FLOAT;
703 break;
704 case PIPE_FORMAT_X8Z24_UNORM:
705 case PIPE_FORMAT_S8_UINT_Z24_UNORM:
706 /* Z24 is always stored like this. */
707 pipe_format = PIPE_FORMAT_Z24X8_UNORM;
708 break;
709 case PIPE_FORMAT_X24S8_UINT:
710 case PIPE_FORMAT_S8X24_UINT:
711 case PIPE_FORMAT_X32_S8X24_UINT:
712 pipe_format = PIPE_FORMAT_S8_UINT;
713 tile_split = tmp->surface.stencil_tile_split;
714 surflevel = tmp->surface.stencil_level;
715 break;
716 default:;
717 }
718 }
719
720 format = r600_translate_texformat(ctx->screen, pipe_format,
721 swizzle,
722 &word4, &yuv_format);
723 assert(format != ~0);
724 if (format == ~0) {
725 FREE(view);
726 return NULL;
727 }
728
729 endian = r600_colorformat_endian_swap(format);
730
731 base_level = 0;
732 first_level = state->u.tex.first_level;
733 last_level = state->u.tex.last_level;
734 width = width0;
735 height = height0;
736 depth = texture->depth0;
737
738 if (force_level) {
739 base_level = force_level;
740 first_level = 0;
741 last_level = 0;
742 width = u_minify(width, force_level);
743 height = u_minify(height, force_level);
744 depth = u_minify(depth, force_level);
745 }
746
747 pitch = surflevel[base_level].nblk_x * util_format_get_blockwidth(pipe_format);
748 non_disp_tiling = tmp->non_disp_tiling;
749
750 switch (surflevel[base_level].mode) {
751 case RADEON_SURF_MODE_LINEAR_ALIGNED:
752 array_mode = V_028C70_ARRAY_LINEAR_ALIGNED;
753 break;
754 case RADEON_SURF_MODE_2D:
755 array_mode = V_028C70_ARRAY_2D_TILED_THIN1;
756 break;
757 case RADEON_SURF_MODE_1D:
758 array_mode = V_028C70_ARRAY_1D_TILED_THIN1;
759 break;
760 case RADEON_SURF_MODE_LINEAR:
761 default:
762 array_mode = V_028C70_ARRAY_LINEAR_GENERAL;
763 break;
764 }
765 macro_aspect = tmp->surface.mtilea;
766 bankw = tmp->surface.bankw;
767 bankh = tmp->surface.bankh;
768 tile_split = eg_tile_split(tile_split);
769 macro_aspect = eg_macro_tile_aspect(macro_aspect);
770 bankw = eg_bank_wh(bankw);
771 bankh = eg_bank_wh(bankh);
772 fmask_bankh = eg_bank_wh(tmp->fmask.bank_height);
773
774 /* 128 bit formats require tile type = 1 */
775 if (rscreen->b.chip_class == CAYMAN) {
776 if (util_format_get_blocksize(pipe_format) >= 16)
777 non_disp_tiling = 1;
778 }
779 nbanks = eg_num_banks(rscreen->b.info.r600_num_banks);
780
781 if (state->target == PIPE_TEXTURE_1D_ARRAY) {
782 height = 1;
783 depth = texture->array_size;
784 } else if (state->target == PIPE_TEXTURE_2D_ARRAY) {
785 depth = texture->array_size;
786 } else if (state->target == PIPE_TEXTURE_CUBE_ARRAY)
787 depth = texture->array_size / 6;
788
789 va = tmp->resource.gpu_address;
790
791 if (state->format == PIPE_FORMAT_X24S8_UINT ||
792 state->format == PIPE_FORMAT_S8X24_UINT ||
793 state->format == PIPE_FORMAT_X32_S8X24_UINT ||
794 state->format == PIPE_FORMAT_S8_UINT)
795 view->is_stencil_sampler = true;
796
797 view->tex_resource = &tmp->resource;
798
799 /* array type views and views into array types need to use layer offset */
800 dim = state->target;
801 if (state->target != PIPE_TEXTURE_CUBE)
802 dim = MAX2(state->target, texture->target);
803
804 view->tex_resource_words[0] = (S_030000_DIM(r600_tex_dim(dim, texture->nr_samples)) |
805 S_030000_PITCH((pitch / 8) - 1) |
806 S_030000_TEX_WIDTH(width - 1));
807 if (rscreen->b.chip_class == CAYMAN)
808 view->tex_resource_words[0] |= CM_S_030000_NON_DISP_TILING_ORDER(non_disp_tiling);
809 else
810 view->tex_resource_words[0] |= S_030000_NON_DISP_TILING_ORDER(non_disp_tiling);
811 view->tex_resource_words[1] = (S_030004_TEX_HEIGHT(height - 1) |
812 S_030004_TEX_DEPTH(depth - 1) |
813 S_030004_ARRAY_MODE(array_mode));
814 view->tex_resource_words[2] = (surflevel[base_level].offset + va) >> 8;
815
816 /* TEX_RESOURCE_WORD3.MIP_ADDRESS */
817 if (texture->nr_samples > 1 && rscreen->has_compressed_msaa_texturing) {
818 if (tmp->is_depth) {
819 /* disable FMASK (0 = disabled) */
820 view->tex_resource_words[3] = 0;
821 view->skip_mip_address_reloc = true;
822 } else {
823 /* FMASK should be in MIP_ADDRESS for multisample textures */
824 view->tex_resource_words[3] = (tmp->fmask.offset + va) >> 8;
825 }
826 } else if (last_level && texture->nr_samples <= 1) {
827 view->tex_resource_words[3] = (surflevel[1].offset + va) >> 8;
828 } else {
829 view->tex_resource_words[3] = (surflevel[base_level].offset + va) >> 8;
830 }
831
832 last_layer = state->u.tex.last_layer;
833 if (state->target != texture->target && depth == 1) {
834 last_layer = state->u.tex.first_layer;
835 }
836 view->tex_resource_words[4] = (word4 |
837 S_030010_ENDIAN_SWAP(endian));
838 view->tex_resource_words[5] = S_030014_BASE_ARRAY(state->u.tex.first_layer) |
839 S_030014_LAST_ARRAY(last_layer);
840 view->tex_resource_words[6] = S_030018_TILE_SPLIT(tile_split);
841
842 if (texture->nr_samples > 1) {
843 unsigned log_samples = util_logbase2(texture->nr_samples);
844 if (rscreen->b.chip_class == CAYMAN) {
845 view->tex_resource_words[4] |= S_030010_LOG2_NUM_FRAGMENTS(log_samples);
846 }
847 /* LAST_LEVEL holds log2(nr_samples) for multisample textures */
848 view->tex_resource_words[5] |= S_030014_LAST_LEVEL(log_samples);
849 view->tex_resource_words[6] |= S_030018_FMASK_BANK_HEIGHT(fmask_bankh);
850 } else {
851 bool no_mip = first_level == last_level;
852
853 view->tex_resource_words[4] |= S_030010_BASE_LEVEL(first_level);
854 view->tex_resource_words[5] |= S_030014_LAST_LEVEL(last_level);
855 /* aniso max 16 samples */
856 view->tex_resource_words[6] |= S_030018_MAX_ANISO_RATIO(no_mip ? 0 : 4);
857 }
858
859 view->tex_resource_words[7] = S_03001C_DATA_FORMAT(format) |
860 S_03001C_TYPE(V_03001C_SQ_TEX_VTX_VALID_TEXTURE) |
861 S_03001C_BANK_WIDTH(bankw) |
862 S_03001C_BANK_HEIGHT(bankh) |
863 S_03001C_MACRO_TILE_ASPECT(macro_aspect) |
864 S_03001C_NUM_BANKS(nbanks) |
865 S_03001C_DEPTH_SAMPLE_ORDER(tmp->is_depth && !tmp->is_flushing_texture);
866 return &view->base;
867 }
868
869 static struct pipe_sampler_view *
870 evergreen_create_sampler_view(struct pipe_context *ctx,
871 struct pipe_resource *tex,
872 const struct pipe_sampler_view *state)
873 {
874 return evergreen_create_sampler_view_custom(ctx, tex, state,
875 tex->width0, tex->height0, 0);
876 }
877
878 static void evergreen_emit_config_state(struct r600_context *rctx, struct r600_atom *atom)
879 {
880 struct radeon_winsys_cs *cs = rctx->b.gfx.cs;
881 struct r600_config_state *a = (struct r600_config_state*)atom;
882
883 radeon_set_config_reg_seq(cs, R_008C04_SQ_GPR_RESOURCE_MGMT_1, 3);
884 if (a->dyn_gpr_enabled) {
885 radeon_emit(cs, S_008C04_NUM_CLAUSE_TEMP_GPRS(rctx->r6xx_num_clause_temp_gprs));
886 radeon_emit(cs, 0);
887 radeon_emit(cs, 0);
888 } else {
889 radeon_emit(cs, a->sq_gpr_resource_mgmt_1);
890 radeon_emit(cs, a->sq_gpr_resource_mgmt_2);
891 radeon_emit(cs, a->sq_gpr_resource_mgmt_3);
892 }
893 radeon_set_config_reg(cs, R_008D8C_SQ_DYN_GPR_CNTL_PS_FLUSH_REQ, (a->dyn_gpr_enabled << 8));
894 if (a->dyn_gpr_enabled) {
895 radeon_set_context_reg(cs, R_028838_SQ_DYN_GPR_RESOURCE_LIMIT_1,
896 S_028838_PS_GPRS(0x1e) |
897 S_028838_VS_GPRS(0x1e) |
898 S_028838_GS_GPRS(0x1e) |
899 S_028838_ES_GPRS(0x1e) |
900 S_028838_HS_GPRS(0x1e) |
901 S_028838_LS_GPRS(0x1e)); /* workaround for hw issues with dyn gpr - must set all limits to 240 instead of 0, 0x1e == 240 / 8*/
902 }
903 }
904
905 static void evergreen_emit_clip_state(struct r600_context *rctx, struct r600_atom *atom)
906 {
907 struct radeon_winsys_cs *cs = rctx->b.gfx.cs;
908 struct pipe_clip_state *state = &rctx->clip_state.state;
909
910 radeon_set_context_reg_seq(cs, R_0285BC_PA_CL_UCP0_X, 6*4);
911 radeon_emit_array(cs, (unsigned*)state, 6*4);
912 }
913
914 static void evergreen_set_polygon_stipple(struct pipe_context *ctx,
915 const struct pipe_poly_stipple *state)
916 {
917 }
918
919 static void evergreen_get_scissor_rect(struct r600_context *rctx,
920 unsigned tl_x, unsigned tl_y, unsigned br_x, unsigned br_y,
921 uint32_t *tl, uint32_t *br)
922 {
923 /* EG hw workaround */
924 if (br_x == 0)
925 tl_x = 1;
926 if (br_y == 0)
927 tl_y = 1;
928
929 /* cayman hw workaround */
930 if (rctx->b.chip_class == CAYMAN) {
931 if (br_x == 1 && br_y == 1)
932 br_x = 2;
933 }
934
935 *tl = S_028240_TL_X(tl_x) | S_028240_TL_Y(tl_y);
936 *br = S_028244_BR_X(br_x) | S_028244_BR_Y(br_y);
937 }
938
939 static void evergreen_set_scissor_states(struct pipe_context *ctx,
940 unsigned start_slot,
941 unsigned num_scissors,
942 const struct pipe_scissor_state *state)
943 {
944 struct r600_context *rctx = (struct r600_context *)ctx;
945 struct r600_scissor_state *rstate = &rctx->scissor;
946 int i;
947
948 for (i = start_slot; i < start_slot + num_scissors; i++)
949 rstate->scissor[i] = state[i - start_slot];
950 rstate->dirty_mask |= ((1 << num_scissors) - 1) << start_slot;
951 rstate->atom.num_dw = util_bitcount(rstate->dirty_mask) * 4;
952 r600_mark_atom_dirty(rctx, &rstate->atom);
953 }
954
955 static void evergreen_emit_scissor_state(struct r600_context *rctx, struct r600_atom *atom)
956 {
957 struct radeon_winsys_cs *cs = rctx->b.gfx.cs;
958 struct r600_scissor_state *rstate = &rctx->scissor;
959 struct pipe_scissor_state *state;
960 uint32_t dirty_mask;
961 unsigned i, offset;
962 uint32_t tl, br;
963
964 dirty_mask = rstate->dirty_mask;
965 while (dirty_mask != 0) {
966 i = u_bit_scan(&dirty_mask);
967 state = &rstate->scissor[i];
968 evergreen_get_scissor_rect(rctx, state->minx, state->miny, state->maxx, state->maxy, &tl, &br);
969
970 offset = i * 4 * 2;
971 radeon_set_context_reg_seq(cs, R_028250_PA_SC_VPORT_SCISSOR_0_TL + offset, 2);
972 radeon_emit(cs, tl);
973 radeon_emit(cs, br);
974 }
975 rstate->dirty_mask = 0;
976 rstate->atom.num_dw = 0;
977 }
978
979 /**
980 * This function intializes the CB* register values for RATs. It is meant
981 * to be used for 1D aligned buffers that do not have an associated
982 * radeon_surf.
983 */
984 void evergreen_init_color_surface_rat(struct r600_context *rctx,
985 struct r600_surface *surf)
986 {
987 struct pipe_resource *pipe_buffer = surf->base.texture;
988 unsigned format = r600_translate_colorformat(rctx->b.chip_class,
989 surf->base.format);
990 unsigned endian = r600_colorformat_endian_swap(format);
991 unsigned swap = r600_translate_colorswap(surf->base.format);
992 unsigned block_size =
993 align(util_format_get_blocksize(pipe_buffer->format), 4);
994 unsigned pitch_alignment =
995 MAX2(64, rctx->screen->b.info.pipe_interleave_bytes / block_size);
996 unsigned pitch = align(pipe_buffer->width0, pitch_alignment);
997
998 surf->cb_color_base = r600_resource(pipe_buffer)->gpu_address >> 8;
999
1000 surf->cb_color_pitch = (pitch / 8) - 1;
1001
1002 surf->cb_color_slice = 0;
1003
1004 surf->cb_color_view = 0;
1005
1006 surf->cb_color_info =
1007 S_028C70_ENDIAN(endian)
1008 | S_028C70_FORMAT(format)
1009 | S_028C70_ARRAY_MODE(V_028C70_ARRAY_LINEAR_ALIGNED)
1010 | S_028C70_NUMBER_TYPE(V_028C70_NUMBER_UINT)
1011 | S_028C70_COMP_SWAP(swap)
1012 | S_028C70_BLEND_BYPASS(1) /* We must set this bit because we
1013 * are using NUMBER_UINT */
1014 | S_028C70_RAT(1)
1015 ;
1016
1017 surf->cb_color_attrib = S_028C74_NON_DISP_TILING_ORDER(1);
1018
1019 /* For buffers, CB_COLOR0_DIM needs to be set to the number of
1020 * elements. */
1021 surf->cb_color_dim = pipe_buffer->width0;
1022
1023 /* Set the buffer range the GPU will have access to: */
1024 util_range_add(&r600_resource(pipe_buffer)->valid_buffer_range,
1025 0, pipe_buffer->width0);
1026
1027 surf->cb_color_fmask = surf->cb_color_base;
1028 surf->cb_color_fmask_slice = 0;
1029 }
1030
1031 void evergreen_init_color_surface(struct r600_context *rctx,
1032 struct r600_surface *surf)
1033 {
1034 struct r600_screen *rscreen = rctx->screen;
1035 struct r600_texture *rtex = (struct r600_texture*)surf->base.texture;
1036 unsigned level = surf->base.u.tex.level;
1037 unsigned pitch, slice;
1038 unsigned color_info, color_attrib, color_dim = 0, color_view;
1039 unsigned format, swap, ntype, endian;
1040 uint64_t offset, base_offset;
1041 unsigned non_disp_tiling, macro_aspect, tile_split, bankh, bankw, fmask_bankh, nbanks;
1042 const struct util_format_description *desc;
1043 int i;
1044 bool blend_clamp = 0, blend_bypass = 0;
1045
1046 offset = rtex->surface.level[level].offset;
1047 if (rtex->surface.level[level].mode == RADEON_SURF_MODE_LINEAR) {
1048 assert(surf->base.u.tex.first_layer == surf->base.u.tex.last_layer);
1049 offset += rtex->surface.level[level].slice_size *
1050 surf->base.u.tex.first_layer;
1051 color_view = 0;
1052 } else
1053 color_view = S_028C6C_SLICE_START(surf->base.u.tex.first_layer) |
1054 S_028C6C_SLICE_MAX(surf->base.u.tex.last_layer);
1055
1056 pitch = (rtex->surface.level[level].nblk_x) / 8 - 1;
1057 slice = (rtex->surface.level[level].nblk_x * rtex->surface.level[level].nblk_y) / 64;
1058 if (slice) {
1059 slice = slice - 1;
1060 }
1061 color_info = 0;
1062 switch (rtex->surface.level[level].mode) {
1063 case RADEON_SURF_MODE_LINEAR_ALIGNED:
1064 color_info = S_028C70_ARRAY_MODE(V_028C70_ARRAY_LINEAR_ALIGNED);
1065 non_disp_tiling = 1;
1066 break;
1067 case RADEON_SURF_MODE_1D:
1068 color_info = S_028C70_ARRAY_MODE(V_028C70_ARRAY_1D_TILED_THIN1);
1069 non_disp_tiling = rtex->non_disp_tiling;
1070 break;
1071 case RADEON_SURF_MODE_2D:
1072 color_info = S_028C70_ARRAY_MODE(V_028C70_ARRAY_2D_TILED_THIN1);
1073 non_disp_tiling = rtex->non_disp_tiling;
1074 break;
1075 case RADEON_SURF_MODE_LINEAR:
1076 default:
1077 color_info = S_028C70_ARRAY_MODE(V_028C70_ARRAY_LINEAR_GENERAL);
1078 non_disp_tiling = 1;
1079 break;
1080 }
1081 tile_split = rtex->surface.tile_split;
1082 macro_aspect = rtex->surface.mtilea;
1083 bankw = rtex->surface.bankw;
1084 bankh = rtex->surface.bankh;
1085 if (rtex->fmask.size)
1086 fmask_bankh = rtex->fmask.bank_height;
1087 else
1088 fmask_bankh = rtex->surface.bankh;
1089 tile_split = eg_tile_split(tile_split);
1090 macro_aspect = eg_macro_tile_aspect(macro_aspect);
1091 bankw = eg_bank_wh(bankw);
1092 bankh = eg_bank_wh(bankh);
1093 fmask_bankh = eg_bank_wh(fmask_bankh);
1094
1095 /* 128 bit formats require tile type = 1 */
1096 if (rscreen->b.chip_class == CAYMAN) {
1097 if (util_format_get_blocksize(surf->base.format) >= 16)
1098 non_disp_tiling = 1;
1099 }
1100 nbanks = eg_num_banks(rscreen->b.info.r600_num_banks);
1101 desc = util_format_description(surf->base.format);
1102 for (i = 0; i < 4; i++) {
1103 if (desc->channel[i].type != UTIL_FORMAT_TYPE_VOID) {
1104 break;
1105 }
1106 }
1107
1108 color_attrib = S_028C74_TILE_SPLIT(tile_split)|
1109 S_028C74_NUM_BANKS(nbanks) |
1110 S_028C74_BANK_WIDTH(bankw) |
1111 S_028C74_BANK_HEIGHT(bankh) |
1112 S_028C74_MACRO_TILE_ASPECT(macro_aspect) |
1113 S_028C74_NON_DISP_TILING_ORDER(non_disp_tiling) |
1114 S_028C74_FMASK_BANK_HEIGHT(fmask_bankh);
1115
1116 if (rctx->b.chip_class == CAYMAN) {
1117 color_attrib |= S_028C74_FORCE_DST_ALPHA_1(desc->swizzle[3] ==
1118 UTIL_FORMAT_SWIZZLE_1);
1119
1120 if (rtex->resource.b.b.nr_samples > 1) {
1121 unsigned log_samples = util_logbase2(rtex->resource.b.b.nr_samples);
1122 color_attrib |= S_028C74_NUM_SAMPLES(log_samples) |
1123 S_028C74_NUM_FRAGMENTS(log_samples);
1124 }
1125 }
1126
1127 ntype = V_028C70_NUMBER_UNORM;
1128 if (desc->colorspace == UTIL_FORMAT_COLORSPACE_SRGB)
1129 ntype = V_028C70_NUMBER_SRGB;
1130 else if (desc->channel[i].type == UTIL_FORMAT_TYPE_SIGNED) {
1131 if (desc->channel[i].normalized)
1132 ntype = V_028C70_NUMBER_SNORM;
1133 else if (desc->channel[i].pure_integer)
1134 ntype = V_028C70_NUMBER_SINT;
1135 } else if (desc->channel[i].type == UTIL_FORMAT_TYPE_UNSIGNED) {
1136 if (desc->channel[i].normalized)
1137 ntype = V_028C70_NUMBER_UNORM;
1138 else if (desc->channel[i].pure_integer)
1139 ntype = V_028C70_NUMBER_UINT;
1140 }
1141
1142 format = r600_translate_colorformat(rctx->b.chip_class, surf->base.format);
1143 assert(format != ~0);
1144
1145 swap = r600_translate_colorswap(surf->base.format);
1146 assert(swap != ~0);
1147
1148 endian = r600_colorformat_endian_swap(format);
1149
1150 /* blend clamp should be set for all NORM/SRGB types */
1151 if (ntype == V_028C70_NUMBER_UNORM || ntype == V_028C70_NUMBER_SNORM ||
1152 ntype == V_028C70_NUMBER_SRGB)
1153 blend_clamp = 1;
1154
1155 /* set blend bypass according to docs if SINT/UINT or
1156 8/24 COLOR variants */
1157 if (ntype == V_028C70_NUMBER_UINT || ntype == V_028C70_NUMBER_SINT ||
1158 format == V_028C70_COLOR_8_24 || format == V_028C70_COLOR_24_8 ||
1159 format == V_028C70_COLOR_X24_8_32_FLOAT) {
1160 blend_clamp = 0;
1161 blend_bypass = 1;
1162 }
1163
1164 surf->alphatest_bypass = ntype == V_028C70_NUMBER_UINT || ntype == V_028C70_NUMBER_SINT;
1165
1166 color_info |= S_028C70_FORMAT(format) |
1167 S_028C70_COMP_SWAP(swap) |
1168 S_028C70_BLEND_CLAMP(blend_clamp) |
1169 S_028C70_BLEND_BYPASS(blend_bypass) |
1170 S_028C70_NUMBER_TYPE(ntype) |
1171 S_028C70_ENDIAN(endian);
1172
1173 /* EXPORT_NORM is an optimzation that can be enabled for better
1174 * performance in certain cases.
1175 * EXPORT_NORM can be enabled if:
1176 * - 11-bit or smaller UNORM/SNORM/SRGB
1177 * - 16-bit or smaller FLOAT
1178 */
1179 if (desc->colorspace != UTIL_FORMAT_COLORSPACE_ZS &&
1180 ((desc->channel[i].size < 12 &&
1181 desc->channel[i].type != UTIL_FORMAT_TYPE_FLOAT &&
1182 ntype != V_028C70_NUMBER_UINT && ntype != V_028C70_NUMBER_SINT) ||
1183 (desc->channel[i].size < 17 &&
1184 desc->channel[i].type == UTIL_FORMAT_TYPE_FLOAT))) {
1185 color_info |= S_028C70_SOURCE_FORMAT(V_028C70_EXPORT_4C_16BPC);
1186 surf->export_16bpc = true;
1187 }
1188
1189 if (rtex->fmask.size) {
1190 color_info |= S_028C70_COMPRESSION(1);
1191 }
1192
1193 base_offset = rtex->resource.gpu_address;
1194
1195 /* XXX handle enabling of CB beyond BASE8 which has different offset */
1196 surf->cb_color_base = (base_offset + offset) >> 8;
1197 surf->cb_color_dim = color_dim;
1198 surf->cb_color_info = color_info;
1199 surf->cb_color_pitch = S_028C64_PITCH_TILE_MAX(pitch);
1200 surf->cb_color_slice = S_028C68_SLICE_TILE_MAX(slice);
1201 surf->cb_color_view = color_view;
1202 surf->cb_color_attrib = color_attrib;
1203 if (rtex->fmask.size) {
1204 surf->cb_color_fmask = (base_offset + rtex->fmask.offset) >> 8;
1205 surf->cb_color_fmask_slice = S_028C88_TILE_MAX(rtex->fmask.slice_tile_max);
1206 } else {
1207 surf->cb_color_fmask = surf->cb_color_base;
1208 surf->cb_color_fmask_slice = S_028C88_TILE_MAX(slice);
1209 }
1210
1211 surf->color_initialized = true;
1212 }
1213
1214 static void evergreen_init_depth_surface(struct r600_context *rctx,
1215 struct r600_surface *surf)
1216 {
1217 struct r600_screen *rscreen = rctx->screen;
1218 struct r600_texture *rtex = (struct r600_texture*)surf->base.texture;
1219 unsigned level = surf->base.u.tex.level;
1220 struct radeon_surf_level *levelinfo = &rtex->surface.level[level];
1221 uint64_t offset;
1222 unsigned format, array_mode;
1223 unsigned macro_aspect, tile_split, bankh, bankw, nbanks;
1224
1225
1226 format = r600_translate_dbformat(surf->base.format);
1227 assert(format != ~0);
1228
1229 offset = rtex->resource.gpu_address;
1230 offset += rtex->surface.level[level].offset;
1231
1232 switch (rtex->surface.level[level].mode) {
1233 case RADEON_SURF_MODE_2D:
1234 array_mode = V_028C70_ARRAY_2D_TILED_THIN1;
1235 break;
1236 case RADEON_SURF_MODE_1D:
1237 case RADEON_SURF_MODE_LINEAR_ALIGNED:
1238 case RADEON_SURF_MODE_LINEAR:
1239 default:
1240 array_mode = V_028C70_ARRAY_1D_TILED_THIN1;
1241 break;
1242 }
1243 tile_split = rtex->surface.tile_split;
1244 macro_aspect = rtex->surface.mtilea;
1245 bankw = rtex->surface.bankw;
1246 bankh = rtex->surface.bankh;
1247 tile_split = eg_tile_split(tile_split);
1248 macro_aspect = eg_macro_tile_aspect(macro_aspect);
1249 bankw = eg_bank_wh(bankw);
1250 bankh = eg_bank_wh(bankh);
1251 nbanks = eg_num_banks(rscreen->b.info.r600_num_banks);
1252 offset >>= 8;
1253
1254 surf->db_z_info = S_028040_ARRAY_MODE(array_mode) |
1255 S_028040_FORMAT(format) |
1256 S_028040_TILE_SPLIT(tile_split)|
1257 S_028040_NUM_BANKS(nbanks) |
1258 S_028040_BANK_WIDTH(bankw) |
1259 S_028040_BANK_HEIGHT(bankh) |
1260 S_028040_MACRO_TILE_ASPECT(macro_aspect);
1261 if (rscreen->b.chip_class == CAYMAN && rtex->resource.b.b.nr_samples > 1) {
1262 surf->db_z_info |= S_028040_NUM_SAMPLES(util_logbase2(rtex->resource.b.b.nr_samples));
1263 }
1264
1265 assert(levelinfo->nblk_x % 8 == 0 && levelinfo->nblk_y % 8 == 0);
1266
1267 surf->db_depth_base = offset;
1268 surf->db_depth_view = S_028008_SLICE_START(surf->base.u.tex.first_layer) |
1269 S_028008_SLICE_MAX(surf->base.u.tex.last_layer);
1270 surf->db_depth_size = S_028058_PITCH_TILE_MAX(levelinfo->nblk_x / 8 - 1) |
1271 S_028058_HEIGHT_TILE_MAX(levelinfo->nblk_y / 8 - 1);
1272 surf->db_depth_slice = S_02805C_SLICE_TILE_MAX(levelinfo->nblk_x *
1273 levelinfo->nblk_y / 64 - 1);
1274
1275 switch (surf->base.format) {
1276 case PIPE_FORMAT_Z24X8_UNORM:
1277 case PIPE_FORMAT_Z24_UNORM_S8_UINT:
1278 case PIPE_FORMAT_X8Z24_UNORM:
1279 case PIPE_FORMAT_S8_UINT_Z24_UNORM:
1280 surf->pa_su_poly_offset_db_fmt_cntl =
1281 S_028B78_POLY_OFFSET_NEG_NUM_DB_BITS((char)-24);
1282 break;
1283 case PIPE_FORMAT_Z32_FLOAT:
1284 case PIPE_FORMAT_Z32_FLOAT_S8X24_UINT:
1285 surf->pa_su_poly_offset_db_fmt_cntl =
1286 S_028B78_POLY_OFFSET_NEG_NUM_DB_BITS((char)-23) |
1287 S_028B78_POLY_OFFSET_DB_IS_FLOAT_FMT(1);
1288 break;
1289 case PIPE_FORMAT_Z16_UNORM:
1290 surf->pa_su_poly_offset_db_fmt_cntl =
1291 S_028B78_POLY_OFFSET_NEG_NUM_DB_BITS((char)-16);
1292 break;
1293 default:;
1294 }
1295
1296 if (rtex->surface.flags & RADEON_SURF_SBUFFER) {
1297 uint64_t stencil_offset;
1298 unsigned stile_split = rtex->surface.stencil_tile_split;
1299
1300 stile_split = eg_tile_split(stile_split);
1301
1302 stencil_offset = rtex->surface.stencil_level[level].offset;
1303 stencil_offset += rtex->resource.gpu_address;
1304
1305 surf->db_stencil_base = stencil_offset >> 8;
1306 surf->db_stencil_info = S_028044_FORMAT(V_028044_STENCIL_8) |
1307 S_028044_TILE_SPLIT(stile_split);
1308 } else {
1309 surf->db_stencil_base = offset;
1310 /* DRM 2.6.18 allows the INVALID format to disable stencil.
1311 * Older kernels are out of luck. */
1312 surf->db_stencil_info = rctx->screen->b.info.drm_minor >= 18 ?
1313 S_028044_FORMAT(V_028044_STENCIL_INVALID) :
1314 S_028044_FORMAT(V_028044_STENCIL_8);
1315 }
1316
1317 /* use htile only for first level */
1318 if (rtex->htile_buffer && !level) {
1319 uint64_t va = rtex->htile_buffer->gpu_address;
1320 surf->db_htile_data_base = va >> 8;
1321 surf->db_htile_surface = S_028ABC_HTILE_WIDTH(1) |
1322 S_028ABC_HTILE_HEIGHT(1) |
1323 S_028ABC_FULL_CACHE(1);
1324 surf->db_z_info |= S_028040_TILE_SURFACE_ENABLE(1);
1325 surf->db_preload_control = 0;
1326 }
1327
1328 surf->depth_initialized = true;
1329 }
1330
1331 static void evergreen_set_framebuffer_state(struct pipe_context *ctx,
1332 const struct pipe_framebuffer_state *state)
1333 {
1334 struct r600_context *rctx = (struct r600_context *)ctx;
1335 struct r600_surface *surf;
1336 struct r600_texture *rtex;
1337 uint32_t i, log_samples;
1338
1339 if (rctx->framebuffer.state.nr_cbufs) {
1340 rctx->b.flags |= R600_CONTEXT_WAIT_3D_IDLE | R600_CONTEXT_FLUSH_AND_INV;
1341 rctx->b.flags |= R600_CONTEXT_FLUSH_AND_INV_CB |
1342 R600_CONTEXT_FLUSH_AND_INV_CB_META;
1343 }
1344 if (rctx->framebuffer.state.zsbuf) {
1345 rctx->b.flags |= R600_CONTEXT_WAIT_3D_IDLE | R600_CONTEXT_FLUSH_AND_INV;
1346 rctx->b.flags |= R600_CONTEXT_FLUSH_AND_INV_DB;
1347
1348 rtex = (struct r600_texture*)rctx->framebuffer.state.zsbuf->texture;
1349 if (rtex->htile_buffer) {
1350 rctx->b.flags |= R600_CONTEXT_FLUSH_AND_INV_DB_META;
1351 }
1352 }
1353
1354 util_copy_framebuffer_state(&rctx->framebuffer.state, state);
1355
1356 /* Colorbuffers. */
1357 rctx->framebuffer.export_16bpc = state->nr_cbufs != 0;
1358 rctx->framebuffer.cb0_is_integer = state->nr_cbufs && state->cbufs[0] &&
1359 util_format_is_pure_integer(state->cbufs[0]->format);
1360 rctx->framebuffer.compressed_cb_mask = 0;
1361 rctx->framebuffer.nr_samples = util_framebuffer_get_num_samples(state);
1362
1363 for (i = 0; i < state->nr_cbufs; i++) {
1364 surf = (struct r600_surface*)state->cbufs[i];
1365 if (!surf)
1366 continue;
1367
1368 rtex = (struct r600_texture*)surf->base.texture;
1369
1370 r600_context_add_resource_size(ctx, state->cbufs[i]->texture);
1371
1372 if (!surf->color_initialized) {
1373 evergreen_init_color_surface(rctx, surf);
1374 }
1375
1376 if (!surf->export_16bpc) {
1377 rctx->framebuffer.export_16bpc = false;
1378 }
1379
1380 if (rtex->fmask.size && rtex->cmask.size) {
1381 rctx->framebuffer.compressed_cb_mask |= 1 << i;
1382 }
1383 }
1384
1385 /* Update alpha-test state dependencies.
1386 * Alpha-test is done on the first colorbuffer only. */
1387 if (state->nr_cbufs) {
1388 bool alphatest_bypass = false;
1389 bool export_16bpc = true;
1390
1391 surf = (struct r600_surface*)state->cbufs[0];
1392 if (surf) {
1393 alphatest_bypass = surf->alphatest_bypass;
1394 export_16bpc = surf->export_16bpc;
1395 }
1396
1397 if (rctx->alphatest_state.bypass != alphatest_bypass) {
1398 rctx->alphatest_state.bypass = alphatest_bypass;
1399 r600_mark_atom_dirty(rctx, &rctx->alphatest_state.atom);
1400 }
1401 if (rctx->alphatest_state.cb0_export_16bpc != export_16bpc) {
1402 rctx->alphatest_state.cb0_export_16bpc = export_16bpc;
1403 r600_mark_atom_dirty(rctx, &rctx->alphatest_state.atom);
1404 }
1405 }
1406
1407 /* ZS buffer. */
1408 if (state->zsbuf) {
1409 surf = (struct r600_surface*)state->zsbuf;
1410
1411 r600_context_add_resource_size(ctx, state->zsbuf->texture);
1412
1413 if (!surf->depth_initialized) {
1414 evergreen_init_depth_surface(rctx, surf);
1415 }
1416
1417 if (state->zsbuf->format != rctx->poly_offset_state.zs_format) {
1418 rctx->poly_offset_state.zs_format = state->zsbuf->format;
1419 r600_mark_atom_dirty(rctx, &rctx->poly_offset_state.atom);
1420 }
1421
1422 if (rctx->db_state.rsurf != surf) {
1423 rctx->db_state.rsurf = surf;
1424 r600_mark_atom_dirty(rctx, &rctx->db_state.atom);
1425 r600_mark_atom_dirty(rctx, &rctx->db_misc_state.atom);
1426 }
1427 } else if (rctx->db_state.rsurf) {
1428 rctx->db_state.rsurf = NULL;
1429 r600_mark_atom_dirty(rctx, &rctx->db_state.atom);
1430 r600_mark_atom_dirty(rctx, &rctx->db_misc_state.atom);
1431 }
1432
1433 if (rctx->cb_misc_state.nr_cbufs != state->nr_cbufs) {
1434 rctx->cb_misc_state.nr_cbufs = state->nr_cbufs;
1435 r600_mark_atom_dirty(rctx, &rctx->cb_misc_state.atom);
1436 }
1437
1438 if (state->nr_cbufs == 0 && rctx->alphatest_state.bypass) {
1439 rctx->alphatest_state.bypass = false;
1440 r600_mark_atom_dirty(rctx, &rctx->alphatest_state.atom);
1441 }
1442
1443 log_samples = util_logbase2(rctx->framebuffer.nr_samples);
1444 /* This is for Cayman to program SAMPLE_RATE, and for RV770 to fix a hw bug. */
1445 if ((rctx->b.chip_class == CAYMAN ||
1446 rctx->b.family == CHIP_RV770) &&
1447 rctx->db_misc_state.log_samples != log_samples) {
1448 rctx->db_misc_state.log_samples = log_samples;
1449 r600_mark_atom_dirty(rctx, &rctx->db_misc_state.atom);
1450 }
1451
1452
1453 /* Calculate the CS size. */
1454 rctx->framebuffer.atom.num_dw = 4; /* SCISSOR */
1455
1456 /* MSAA. */
1457 if (rctx->b.chip_class == EVERGREEN)
1458 rctx->framebuffer.atom.num_dw += 17; /* Evergreen */
1459 else
1460 rctx->framebuffer.atom.num_dw += 28; /* Cayman */
1461
1462 /* Colorbuffers. */
1463 rctx->framebuffer.atom.num_dw += state->nr_cbufs * 23;
1464 rctx->framebuffer.atom.num_dw += state->nr_cbufs * 2;
1465 rctx->framebuffer.atom.num_dw += (12 - state->nr_cbufs) * 3;
1466
1467 /* ZS buffer. */
1468 if (state->zsbuf) {
1469 rctx->framebuffer.atom.num_dw += 24;
1470 rctx->framebuffer.atom.num_dw += 2;
1471 } else if (rctx->screen->b.info.drm_minor >= 18) {
1472 rctx->framebuffer.atom.num_dw += 4;
1473 }
1474
1475 r600_mark_atom_dirty(rctx, &rctx->framebuffer.atom);
1476
1477 r600_set_sample_locations_constant_buffer(rctx);
1478 }
1479
1480 static void evergreen_set_min_samples(struct pipe_context *ctx, unsigned min_samples)
1481 {
1482 struct r600_context *rctx = (struct r600_context *)ctx;
1483
1484 if (rctx->ps_iter_samples == min_samples)
1485 return;
1486
1487 rctx->ps_iter_samples = min_samples;
1488 if (rctx->framebuffer.nr_samples > 1) {
1489 r600_mark_atom_dirty(rctx, &rctx->framebuffer.atom);
1490 }
1491 }
1492
1493 /* 8xMSAA */
1494 static uint32_t sample_locs_8x[] = {
1495 FILL_SREG(-1, 1, 1, 5, 3, -5, 5, 3),
1496 FILL_SREG(-7, -1, -3, -7, 7, -3, -5, 7),
1497 FILL_SREG(-1, 1, 1, 5, 3, -5, 5, 3),
1498 FILL_SREG(-7, -1, -3, -7, 7, -3, -5, 7),
1499 FILL_SREG(-1, 1, 1, 5, 3, -5, 5, 3),
1500 FILL_SREG(-7, -1, -3, -7, 7, -3, -5, 7),
1501 FILL_SREG(-1, 1, 1, 5, 3, -5, 5, 3),
1502 FILL_SREG(-7, -1, -3, -7, 7, -3, -5, 7),
1503 };
1504 static unsigned max_dist_8x = 7;
1505
1506 static void evergreen_get_sample_position(struct pipe_context *ctx,
1507 unsigned sample_count,
1508 unsigned sample_index,
1509 float *out_value)
1510 {
1511 int offset, index;
1512 struct {
1513 int idx:4;
1514 } val;
1515 switch (sample_count) {
1516 case 1:
1517 default:
1518 out_value[0] = out_value[1] = 0.5;
1519 break;
1520 case 2:
1521 offset = 4 * (sample_index * 2);
1522 val.idx = (eg_sample_locs_2x[0] >> offset) & 0xf;
1523 out_value[0] = (float)(val.idx + 8) / 16.0f;
1524 val.idx = (eg_sample_locs_2x[0] >> (offset + 4)) & 0xf;
1525 out_value[1] = (float)(val.idx + 8) / 16.0f;
1526 break;
1527 case 4:
1528 offset = 4 * (sample_index * 2);
1529 val.idx = (eg_sample_locs_4x[0] >> offset) & 0xf;
1530 out_value[0] = (float)(val.idx + 8) / 16.0f;
1531 val.idx = (eg_sample_locs_4x[0] >> (offset + 4)) & 0xf;
1532 out_value[1] = (float)(val.idx + 8) / 16.0f;
1533 break;
1534 case 8:
1535 offset = 4 * (sample_index % 4 * 2);
1536 index = (sample_index / 4);
1537 val.idx = (sample_locs_8x[index] >> offset) & 0xf;
1538 out_value[0] = (float)(val.idx + 8) / 16.0f;
1539 val.idx = (sample_locs_8x[index] >> (offset + 4)) & 0xf;
1540 out_value[1] = (float)(val.idx + 8) / 16.0f;
1541 break;
1542 }
1543 }
1544
1545 static void evergreen_emit_msaa_state(struct r600_context *rctx, int nr_samples, int ps_iter_samples)
1546 {
1547
1548 struct radeon_winsys_cs *cs = rctx->b.gfx.cs;
1549 unsigned max_dist = 0;
1550
1551 switch (nr_samples) {
1552 default:
1553 nr_samples = 0;
1554 break;
1555 case 2:
1556 radeon_set_context_reg_seq(cs, R_028C1C_PA_SC_AA_SAMPLE_LOCS_0, Elements(eg_sample_locs_2x));
1557 radeon_emit_array(cs, eg_sample_locs_2x, Elements(eg_sample_locs_2x));
1558 max_dist = eg_max_dist_2x;
1559 break;
1560 case 4:
1561 radeon_set_context_reg_seq(cs, R_028C1C_PA_SC_AA_SAMPLE_LOCS_0, Elements(eg_sample_locs_4x));
1562 radeon_emit_array(cs, eg_sample_locs_4x, Elements(eg_sample_locs_4x));
1563 max_dist = eg_max_dist_4x;
1564 break;
1565 case 8:
1566 radeon_set_context_reg_seq(cs, R_028C1C_PA_SC_AA_SAMPLE_LOCS_0, Elements(sample_locs_8x));
1567 radeon_emit_array(cs, sample_locs_8x, Elements(sample_locs_8x));
1568 max_dist = max_dist_8x;
1569 break;
1570 }
1571
1572 if (nr_samples > 1) {
1573 radeon_set_context_reg_seq(cs, R_028C00_PA_SC_LINE_CNTL, 2);
1574 radeon_emit(cs, S_028C00_LAST_PIXEL(1) |
1575 S_028C00_EXPAND_LINE_WIDTH(1)); /* R_028C00_PA_SC_LINE_CNTL */
1576 radeon_emit(cs, S_028C04_MSAA_NUM_SAMPLES(util_logbase2(nr_samples)) |
1577 S_028C04_MAX_SAMPLE_DIST(max_dist)); /* R_028C04_PA_SC_AA_CONFIG */
1578 radeon_set_context_reg(cs, EG_R_028A4C_PA_SC_MODE_CNTL_1,
1579 EG_S_028A4C_PS_ITER_SAMPLE(ps_iter_samples > 1) |
1580 EG_S_028A4C_FORCE_EOV_CNTDWN_ENABLE(1) |
1581 EG_S_028A4C_FORCE_EOV_REZ_ENABLE(1));
1582 } else {
1583 radeon_set_context_reg_seq(cs, R_028C00_PA_SC_LINE_CNTL, 2);
1584 radeon_emit(cs, S_028C00_LAST_PIXEL(1)); /* R_028C00_PA_SC_LINE_CNTL */
1585 radeon_emit(cs, 0); /* R_028C04_PA_SC_AA_CONFIG */
1586 radeon_set_context_reg(cs, EG_R_028A4C_PA_SC_MODE_CNTL_1,
1587 EG_S_028A4C_FORCE_EOV_CNTDWN_ENABLE(1) |
1588 EG_S_028A4C_FORCE_EOV_REZ_ENABLE(1));
1589 }
1590 }
1591
1592 static void evergreen_emit_framebuffer_state(struct r600_context *rctx, struct r600_atom *atom)
1593 {
1594 struct radeon_winsys_cs *cs = rctx->b.gfx.cs;
1595 struct pipe_framebuffer_state *state = &rctx->framebuffer.state;
1596 unsigned nr_cbufs = state->nr_cbufs;
1597 unsigned i, tl, br;
1598 struct r600_texture *tex = NULL;
1599 struct r600_surface *cb = NULL;
1600
1601 /* XXX support more colorbuffers once we need them */
1602 assert(nr_cbufs <= 8);
1603 if (nr_cbufs > 8)
1604 nr_cbufs = 8;
1605
1606 /* Colorbuffers. */
1607 for (i = 0; i < nr_cbufs; i++) {
1608 unsigned reloc, cmask_reloc;
1609
1610 cb = (struct r600_surface*)state->cbufs[i];
1611 if (!cb) {
1612 radeon_set_context_reg(cs, R_028C70_CB_COLOR0_INFO + i * 0x3C,
1613 S_028C70_FORMAT(V_028C70_COLOR_INVALID));
1614 continue;
1615 }
1616
1617 tex = (struct r600_texture *)cb->base.texture;
1618 reloc = radeon_add_to_buffer_list(&rctx->b,
1619 &rctx->b.gfx,
1620 (struct r600_resource*)cb->base.texture,
1621 RADEON_USAGE_READWRITE,
1622 tex->surface.nsamples > 1 ?
1623 RADEON_PRIO_COLOR_BUFFER_MSAA :
1624 RADEON_PRIO_COLOR_BUFFER);
1625
1626 if (tex->cmask_buffer && tex->cmask_buffer != &tex->resource) {
1627 cmask_reloc = radeon_add_to_buffer_list(&rctx->b, &rctx->b.gfx,
1628 tex->cmask_buffer, RADEON_USAGE_READWRITE,
1629 RADEON_PRIO_CMASK);
1630 } else {
1631 cmask_reloc = reloc;
1632 }
1633
1634 radeon_set_context_reg_seq(cs, R_028C60_CB_COLOR0_BASE + i * 0x3C, 13);
1635 radeon_emit(cs, cb->cb_color_base); /* R_028C60_CB_COLOR0_BASE */
1636 radeon_emit(cs, cb->cb_color_pitch); /* R_028C64_CB_COLOR0_PITCH */
1637 radeon_emit(cs, cb->cb_color_slice); /* R_028C68_CB_COLOR0_SLICE */
1638 radeon_emit(cs, cb->cb_color_view); /* R_028C6C_CB_COLOR0_VIEW */
1639 radeon_emit(cs, cb->cb_color_info | tex->cb_color_info); /* R_028C70_CB_COLOR0_INFO */
1640 radeon_emit(cs, cb->cb_color_attrib); /* R_028C74_CB_COLOR0_ATTRIB */
1641 radeon_emit(cs, cb->cb_color_dim); /* R_028C78_CB_COLOR0_DIM */
1642 radeon_emit(cs, tex->cmask.base_address_reg); /* R_028C7C_CB_COLOR0_CMASK */
1643 radeon_emit(cs, tex->cmask.slice_tile_max); /* R_028C80_CB_COLOR0_CMASK_SLICE */
1644 radeon_emit(cs, cb->cb_color_fmask); /* R_028C84_CB_COLOR0_FMASK */
1645 radeon_emit(cs, cb->cb_color_fmask_slice); /* R_028C88_CB_COLOR0_FMASK_SLICE */
1646 radeon_emit(cs, tex->color_clear_value[0]); /* R_028C8C_CB_COLOR0_CLEAR_WORD0 */
1647 radeon_emit(cs, tex->color_clear_value[1]); /* R_028C90_CB_COLOR0_CLEAR_WORD1 */
1648
1649 radeon_emit(cs, PKT3(PKT3_NOP, 0, 0)); /* R_028C60_CB_COLOR0_BASE */
1650 radeon_emit(cs, reloc);
1651
1652 radeon_emit(cs, PKT3(PKT3_NOP, 0, 0)); /* R_028C74_CB_COLOR0_ATTRIB */
1653 radeon_emit(cs, reloc);
1654
1655 radeon_emit(cs, PKT3(PKT3_NOP, 0, 0)); /* R_028C7C_CB_COLOR0_CMASK */
1656 radeon_emit(cs, cmask_reloc);
1657
1658 radeon_emit(cs, PKT3(PKT3_NOP, 0, 0)); /* R_028C84_CB_COLOR0_FMASK */
1659 radeon_emit(cs, reloc);
1660 }
1661 /* set CB_COLOR1_INFO for possible dual-src blending */
1662 if (i == 1 && state->cbufs[0]) {
1663 radeon_set_context_reg(cs, R_028C70_CB_COLOR0_INFO + 1 * 0x3C,
1664 cb->cb_color_info | tex->cb_color_info);
1665 i++;
1666 }
1667 for (; i < 8 ; i++)
1668 radeon_set_context_reg(cs, R_028C70_CB_COLOR0_INFO + i * 0x3C, 0);
1669 for (; i < 12; i++)
1670 radeon_set_context_reg(cs, R_028E50_CB_COLOR8_INFO + (i - 8) * 0x1C, 0);
1671
1672 /* ZS buffer. */
1673 if (state->zsbuf) {
1674 struct r600_surface *zb = (struct r600_surface*)state->zsbuf;
1675 unsigned reloc = radeon_add_to_buffer_list(&rctx->b,
1676 &rctx->b.gfx,
1677 (struct r600_resource*)state->zsbuf->texture,
1678 RADEON_USAGE_READWRITE,
1679 zb->base.texture->nr_samples > 1 ?
1680 RADEON_PRIO_DEPTH_BUFFER_MSAA :
1681 RADEON_PRIO_DEPTH_BUFFER);
1682
1683 radeon_set_context_reg(cs, R_028B78_PA_SU_POLY_OFFSET_DB_FMT_CNTL,
1684 zb->pa_su_poly_offset_db_fmt_cntl);
1685 radeon_set_context_reg(cs, R_028008_DB_DEPTH_VIEW, zb->db_depth_view);
1686
1687 radeon_set_context_reg_seq(cs, R_028040_DB_Z_INFO, 8);
1688 radeon_emit(cs, zb->db_z_info); /* R_028040_DB_Z_INFO */
1689 radeon_emit(cs, zb->db_stencil_info); /* R_028044_DB_STENCIL_INFO */
1690 radeon_emit(cs, zb->db_depth_base); /* R_028048_DB_Z_READ_BASE */
1691 radeon_emit(cs, zb->db_stencil_base); /* R_02804C_DB_STENCIL_READ_BASE */
1692 radeon_emit(cs, zb->db_depth_base); /* R_028050_DB_Z_WRITE_BASE */
1693 radeon_emit(cs, zb->db_stencil_base); /* R_028054_DB_STENCIL_WRITE_BASE */
1694 radeon_emit(cs, zb->db_depth_size); /* R_028058_DB_DEPTH_SIZE */
1695 radeon_emit(cs, zb->db_depth_slice); /* R_02805C_DB_DEPTH_SLICE */
1696
1697 radeon_emit(cs, PKT3(PKT3_NOP, 0, 0)); /* R_028048_DB_Z_READ_BASE */
1698 radeon_emit(cs, reloc);
1699
1700 radeon_emit(cs, PKT3(PKT3_NOP, 0, 0)); /* R_02804C_DB_STENCIL_READ_BASE */
1701 radeon_emit(cs, reloc);
1702
1703 radeon_emit(cs, PKT3(PKT3_NOP, 0, 0)); /* R_028050_DB_Z_WRITE_BASE */
1704 radeon_emit(cs, reloc);
1705
1706 radeon_emit(cs, PKT3(PKT3_NOP, 0, 0)); /* R_028054_DB_STENCIL_WRITE_BASE */
1707 radeon_emit(cs, reloc);
1708 } else if (rctx->screen->b.info.drm_minor >= 18) {
1709 /* DRM 2.6.18 allows the INVALID format to disable depth/stencil.
1710 * Older kernels are out of luck. */
1711 radeon_set_context_reg_seq(cs, R_028040_DB_Z_INFO, 2);
1712 radeon_emit(cs, S_028040_FORMAT(V_028040_Z_INVALID)); /* R_028040_DB_Z_INFO */
1713 radeon_emit(cs, S_028044_FORMAT(V_028044_STENCIL_INVALID)); /* R_028044_DB_STENCIL_INFO */
1714 }
1715
1716 /* Framebuffer dimensions. */
1717 evergreen_get_scissor_rect(rctx, 0, 0, state->width, state->height, &tl, &br);
1718
1719 radeon_set_context_reg_seq(cs, R_028204_PA_SC_WINDOW_SCISSOR_TL, 2);
1720 radeon_emit(cs, tl); /* R_028204_PA_SC_WINDOW_SCISSOR_TL */
1721 radeon_emit(cs, br); /* R_028208_PA_SC_WINDOW_SCISSOR_BR */
1722
1723 if (rctx->b.chip_class == EVERGREEN) {
1724 evergreen_emit_msaa_state(rctx, rctx->framebuffer.nr_samples, rctx->ps_iter_samples);
1725 } else {
1726 cayman_emit_msaa_sample_locs(cs, rctx->framebuffer.nr_samples);
1727 cayman_emit_msaa_config(cs, rctx->framebuffer.nr_samples, rctx->ps_iter_samples, 0);
1728 }
1729 }
1730
1731 static void evergreen_emit_polygon_offset(struct r600_context *rctx, struct r600_atom *a)
1732 {
1733 struct radeon_winsys_cs *cs = rctx->b.gfx.cs;
1734 struct r600_poly_offset_state *state = (struct r600_poly_offset_state*)a;
1735 float offset_units = state->offset_units;
1736 float offset_scale = state->offset_scale;
1737
1738 switch (state->zs_format) {
1739 case PIPE_FORMAT_Z24X8_UNORM:
1740 case PIPE_FORMAT_Z24_UNORM_S8_UINT:
1741 case PIPE_FORMAT_X8Z24_UNORM:
1742 case PIPE_FORMAT_S8_UINT_Z24_UNORM:
1743 offset_units *= 2.0f;
1744 break;
1745 case PIPE_FORMAT_Z16_UNORM:
1746 offset_units *= 4.0f;
1747 break;
1748 default:;
1749 }
1750
1751 radeon_set_context_reg_seq(cs, R_028B80_PA_SU_POLY_OFFSET_FRONT_SCALE, 4);
1752 radeon_emit(cs, fui(offset_scale));
1753 radeon_emit(cs, fui(offset_units));
1754 radeon_emit(cs, fui(offset_scale));
1755 radeon_emit(cs, fui(offset_units));
1756 }
1757
1758 static void evergreen_emit_cb_misc_state(struct r600_context *rctx, struct r600_atom *atom)
1759 {
1760 struct radeon_winsys_cs *cs = rctx->b.gfx.cs;
1761 struct r600_cb_misc_state *a = (struct r600_cb_misc_state*)atom;
1762 unsigned fb_colormask = (1ULL << ((unsigned)a->nr_cbufs * 4)) - 1;
1763 unsigned ps_colormask = (1ULL << ((unsigned)a->nr_ps_color_outputs * 4)) - 1;
1764
1765 radeon_set_context_reg_seq(cs, R_028238_CB_TARGET_MASK, 2);
1766 radeon_emit(cs, a->blend_colormask & fb_colormask); /* R_028238_CB_TARGET_MASK */
1767 /* This must match the used export instructions exactly.
1768 * Other values may lead to undefined behavior and hangs.
1769 */
1770 radeon_emit(cs, ps_colormask); /* R_02823C_CB_SHADER_MASK */
1771 }
1772
1773 static void evergreen_emit_db_state(struct r600_context *rctx, struct r600_atom *atom)
1774 {
1775 struct radeon_winsys_cs *cs = rctx->b.gfx.cs;
1776 struct r600_db_state *a = (struct r600_db_state*)atom;
1777
1778 if (a->rsurf && a->rsurf->db_htile_surface) {
1779 struct r600_texture *rtex = (struct r600_texture *)a->rsurf->base.texture;
1780 unsigned reloc_idx;
1781
1782 radeon_set_context_reg(cs, R_02802C_DB_DEPTH_CLEAR, fui(rtex->depth_clear_value));
1783 radeon_set_context_reg(cs, R_028ABC_DB_HTILE_SURFACE, a->rsurf->db_htile_surface);
1784 radeon_set_context_reg(cs, R_028AC8_DB_PRELOAD_CONTROL, a->rsurf->db_preload_control);
1785 radeon_set_context_reg(cs, R_028014_DB_HTILE_DATA_BASE, a->rsurf->db_htile_data_base);
1786 reloc_idx = radeon_add_to_buffer_list(&rctx->b, &rctx->b.gfx, rtex->htile_buffer,
1787 RADEON_USAGE_READWRITE, RADEON_PRIO_HTILE);
1788 cs->buf[cs->cdw++] = PKT3(PKT3_NOP, 0, 0);
1789 cs->buf[cs->cdw++] = reloc_idx;
1790 } else {
1791 radeon_set_context_reg(cs, R_028ABC_DB_HTILE_SURFACE, 0);
1792 radeon_set_context_reg(cs, R_028AC8_DB_PRELOAD_CONTROL, 0);
1793 }
1794 }
1795
1796 static void evergreen_emit_db_misc_state(struct r600_context *rctx, struct r600_atom *atom)
1797 {
1798 struct radeon_winsys_cs *cs = rctx->b.gfx.cs;
1799 struct r600_db_misc_state *a = (struct r600_db_misc_state*)atom;
1800 unsigned db_render_control = 0;
1801 unsigned db_count_control = 0;
1802 unsigned db_render_override =
1803 S_02800C_FORCE_HIS_ENABLE0(V_02800C_FORCE_DISABLE) |
1804 S_02800C_FORCE_HIS_ENABLE1(V_02800C_FORCE_DISABLE);
1805
1806 if (rctx->b.num_occlusion_queries > 0 &&
1807 !a->occlusion_queries_disabled) {
1808 db_count_control |= S_028004_PERFECT_ZPASS_COUNTS(1);
1809 if (rctx->b.chip_class == CAYMAN) {
1810 db_count_control |= S_028004_SAMPLE_RATE(a->log_samples);
1811 }
1812 db_render_override |= S_02800C_NOOP_CULL_DISABLE(1);
1813 } else {
1814 db_count_control |= S_028004_ZPASS_INCREMENT_DISABLE(1);
1815 }
1816
1817 /* This is to fix a lockup when hyperz and alpha test are enabled at
1818 * the same time somehow GPU get confuse on which order to pick for
1819 * z test
1820 */
1821 if (rctx->alphatest_state.sx_alpha_test_control)
1822 db_render_override |= S_02800C_FORCE_SHADER_Z_ORDER(1);
1823
1824 if (a->flush_depthstencil_through_cb) {
1825 assert(a->copy_depth || a->copy_stencil);
1826
1827 db_render_control |= S_028000_DEPTH_COPY_ENABLE(a->copy_depth) |
1828 S_028000_STENCIL_COPY_ENABLE(a->copy_stencil) |
1829 S_028000_COPY_CENTROID(1) |
1830 S_028000_COPY_SAMPLE(a->copy_sample);
1831 } else if (a->flush_depth_inplace || a->flush_stencil_inplace) {
1832 db_render_control |= S_028000_DEPTH_COMPRESS_DISABLE(a->flush_depth_inplace) |
1833 S_028000_STENCIL_COMPRESS_DISABLE(a->flush_stencil_inplace);
1834 db_render_override |= S_02800C_DISABLE_PIXEL_RATE_TILES(1);
1835 }
1836 if (a->htile_clear) {
1837 /* FIXME we might want to disable cliprect here */
1838 db_render_control |= S_028000_DEPTH_CLEAR_ENABLE(1);
1839 }
1840
1841 radeon_set_context_reg_seq(cs, R_028000_DB_RENDER_CONTROL, 2);
1842 radeon_emit(cs, db_render_control); /* R_028000_DB_RENDER_CONTROL */
1843 radeon_emit(cs, db_count_control); /* R_028004_DB_COUNT_CONTROL */
1844 radeon_set_context_reg(cs, R_02800C_DB_RENDER_OVERRIDE, db_render_override);
1845 radeon_set_context_reg(cs, R_02880C_DB_SHADER_CONTROL, a->db_shader_control);
1846 }
1847
1848 static void evergreen_emit_vertex_buffers(struct r600_context *rctx,
1849 struct r600_vertexbuf_state *state,
1850 unsigned resource_offset,
1851 unsigned pkt_flags)
1852 {
1853 struct radeon_winsys_cs *cs = rctx->b.gfx.cs;
1854 uint32_t dirty_mask = state->dirty_mask;
1855
1856 while (dirty_mask) {
1857 struct pipe_vertex_buffer *vb;
1858 struct r600_resource *rbuffer;
1859 uint64_t va;
1860 unsigned buffer_index = u_bit_scan(&dirty_mask);
1861
1862 vb = &state->vb[buffer_index];
1863 rbuffer = (struct r600_resource*)vb->buffer;
1864 assert(rbuffer);
1865
1866 va = rbuffer->gpu_address + vb->buffer_offset;
1867
1868 /* fetch resources start at index 992 */
1869 radeon_emit(cs, PKT3(PKT3_SET_RESOURCE, 8, 0) | pkt_flags);
1870 radeon_emit(cs, (resource_offset + buffer_index) * 8);
1871 radeon_emit(cs, va); /* RESOURCEi_WORD0 */
1872 radeon_emit(cs, rbuffer->b.b.width0 - vb->buffer_offset - 1); /* RESOURCEi_WORD1 */
1873 radeon_emit(cs, /* RESOURCEi_WORD2 */
1874 S_030008_ENDIAN_SWAP(r600_endian_swap(32)) |
1875 S_030008_STRIDE(vb->stride) |
1876 S_030008_BASE_ADDRESS_HI(va >> 32UL));
1877 radeon_emit(cs, /* RESOURCEi_WORD3 */
1878 S_03000C_DST_SEL_X(V_03000C_SQ_SEL_X) |
1879 S_03000C_DST_SEL_Y(V_03000C_SQ_SEL_Y) |
1880 S_03000C_DST_SEL_Z(V_03000C_SQ_SEL_Z) |
1881 S_03000C_DST_SEL_W(V_03000C_SQ_SEL_W));
1882 radeon_emit(cs, 0); /* RESOURCEi_WORD4 */
1883 radeon_emit(cs, 0); /* RESOURCEi_WORD5 */
1884 radeon_emit(cs, 0); /* RESOURCEi_WORD6 */
1885 radeon_emit(cs, 0xc0000000); /* RESOURCEi_WORD7 */
1886
1887 radeon_emit(cs, PKT3(PKT3_NOP, 0, 0) | pkt_flags);
1888 radeon_emit(cs, radeon_add_to_buffer_list(&rctx->b, &rctx->b.gfx, rbuffer,
1889 RADEON_USAGE_READ, RADEON_PRIO_VERTEX_BUFFER));
1890 }
1891 state->dirty_mask = 0;
1892 }
1893
1894 static void evergreen_fs_emit_vertex_buffers(struct r600_context *rctx, struct r600_atom * atom)
1895 {
1896 evergreen_emit_vertex_buffers(rctx, &rctx->vertex_buffer_state, EG_FETCH_CONSTANTS_OFFSET_FS, 0);
1897 }
1898
1899 static void evergreen_cs_emit_vertex_buffers(struct r600_context *rctx, struct r600_atom * atom)
1900 {
1901 evergreen_emit_vertex_buffers(rctx, &rctx->cs_vertex_buffer_state, EG_FETCH_CONSTANTS_OFFSET_CS,
1902 RADEON_CP_PACKET3_COMPUTE_MODE);
1903 }
1904
1905 static void evergreen_emit_constant_buffers(struct r600_context *rctx,
1906 struct r600_constbuf_state *state,
1907 unsigned buffer_id_base,
1908 unsigned reg_alu_constbuf_size,
1909 unsigned reg_alu_const_cache,
1910 unsigned pkt_flags)
1911 {
1912 struct radeon_winsys_cs *cs = rctx->b.gfx.cs;
1913 uint32_t dirty_mask = state->dirty_mask;
1914
1915 while (dirty_mask) {
1916 struct pipe_constant_buffer *cb;
1917 struct r600_resource *rbuffer;
1918 uint64_t va;
1919 unsigned buffer_index = ffs(dirty_mask) - 1;
1920 unsigned gs_ring_buffer = (buffer_index == R600_GS_RING_CONST_BUFFER);
1921
1922 cb = &state->cb[buffer_index];
1923 rbuffer = (struct r600_resource*)cb->buffer;
1924 assert(rbuffer);
1925
1926 va = rbuffer->gpu_address + cb->buffer_offset;
1927
1928 if (!gs_ring_buffer) {
1929 radeon_set_context_reg_flag(cs, reg_alu_constbuf_size + buffer_index * 4,
1930 DIV_ROUND_UP(cb->buffer_size, 256), pkt_flags);
1931 radeon_set_context_reg_flag(cs, reg_alu_const_cache + buffer_index * 4, va >> 8,
1932 pkt_flags);
1933 }
1934
1935 radeon_emit(cs, PKT3(PKT3_NOP, 0, 0) | pkt_flags);
1936 radeon_emit(cs, radeon_add_to_buffer_list(&rctx->b, &rctx->b.gfx, rbuffer,
1937 RADEON_USAGE_READ, RADEON_PRIO_CONST_BUFFER));
1938
1939 radeon_emit(cs, PKT3(PKT3_SET_RESOURCE, 8, 0) | pkt_flags);
1940 radeon_emit(cs, (buffer_id_base + buffer_index) * 8);
1941 radeon_emit(cs, va); /* RESOURCEi_WORD0 */
1942 radeon_emit(cs, rbuffer->b.b.width0 - cb->buffer_offset - 1); /* RESOURCEi_WORD1 */
1943 radeon_emit(cs, /* RESOURCEi_WORD2 */
1944 S_030008_ENDIAN_SWAP(gs_ring_buffer ? ENDIAN_NONE : r600_endian_swap(32)) |
1945 S_030008_STRIDE(gs_ring_buffer ? 4 : 16) |
1946 S_030008_BASE_ADDRESS_HI(va >> 32UL) |
1947 S_030008_DATA_FORMAT(FMT_32_32_32_32_FLOAT));
1948 radeon_emit(cs, /* RESOURCEi_WORD3 */
1949 S_03000C_UNCACHED(gs_ring_buffer ? 1 : 0) |
1950 S_03000C_DST_SEL_X(V_03000C_SQ_SEL_X) |
1951 S_03000C_DST_SEL_Y(V_03000C_SQ_SEL_Y) |
1952 S_03000C_DST_SEL_Z(V_03000C_SQ_SEL_Z) |
1953 S_03000C_DST_SEL_W(V_03000C_SQ_SEL_W));
1954 radeon_emit(cs, 0); /* RESOURCEi_WORD4 */
1955 radeon_emit(cs, 0); /* RESOURCEi_WORD5 */
1956 radeon_emit(cs, 0); /* RESOURCEi_WORD6 */
1957 radeon_emit(cs, /* RESOURCEi_WORD7 */
1958 S_03001C_TYPE(V_03001C_SQ_TEX_VTX_VALID_BUFFER));
1959
1960 radeon_emit(cs, PKT3(PKT3_NOP, 0, 0) | pkt_flags);
1961 radeon_emit(cs, radeon_add_to_buffer_list(&rctx->b, &rctx->b.gfx, rbuffer,
1962 RADEON_USAGE_READ, RADEON_PRIO_CONST_BUFFER));
1963
1964 dirty_mask &= ~(1 << buffer_index);
1965 }
1966 state->dirty_mask = 0;
1967 }
1968
1969 /* VS constants can be in VS/ES (same space) or LS if tess is enabled */
1970 static void evergreen_emit_vs_constant_buffers(struct r600_context *rctx, struct r600_atom *atom)
1971 {
1972 if (rctx->vs_shader->current->shader.vs_as_ls) {
1973 evergreen_emit_constant_buffers(rctx, &rctx->constbuf_state[PIPE_SHADER_VERTEX],
1974 EG_FETCH_CONSTANTS_OFFSET_LS,
1975 R_028FC0_ALU_CONST_BUFFER_SIZE_LS_0,
1976 R_028F40_ALU_CONST_CACHE_LS_0,
1977 0 /* PKT3 flags */);
1978 } else {
1979 evergreen_emit_constant_buffers(rctx, &rctx->constbuf_state[PIPE_SHADER_VERTEX],
1980 EG_FETCH_CONSTANTS_OFFSET_VS,
1981 R_028180_ALU_CONST_BUFFER_SIZE_VS_0,
1982 R_028980_ALU_CONST_CACHE_VS_0,
1983 0 /* PKT3 flags */);
1984 }
1985 }
1986
1987 static void evergreen_emit_gs_constant_buffers(struct r600_context *rctx, struct r600_atom *atom)
1988 {
1989 evergreen_emit_constant_buffers(rctx, &rctx->constbuf_state[PIPE_SHADER_GEOMETRY],
1990 EG_FETCH_CONSTANTS_OFFSET_GS,
1991 R_0281C0_ALU_CONST_BUFFER_SIZE_GS_0,
1992 R_0289C0_ALU_CONST_CACHE_GS_0,
1993 0 /* PKT3 flags */);
1994 }
1995
1996 static void evergreen_emit_ps_constant_buffers(struct r600_context *rctx, struct r600_atom *atom)
1997 {
1998 evergreen_emit_constant_buffers(rctx, &rctx->constbuf_state[PIPE_SHADER_FRAGMENT],
1999 EG_FETCH_CONSTANTS_OFFSET_PS,
2000 R_028140_ALU_CONST_BUFFER_SIZE_PS_0,
2001 R_028940_ALU_CONST_CACHE_PS_0,
2002 0 /* PKT3 flags */);
2003 }
2004
2005 static void evergreen_emit_cs_constant_buffers(struct r600_context *rctx, struct r600_atom *atom)
2006 {
2007 evergreen_emit_constant_buffers(rctx, &rctx->constbuf_state[PIPE_SHADER_COMPUTE],
2008 EG_FETCH_CONSTANTS_OFFSET_CS,
2009 R_028FC0_ALU_CONST_BUFFER_SIZE_LS_0,
2010 R_028F40_ALU_CONST_CACHE_LS_0,
2011 RADEON_CP_PACKET3_COMPUTE_MODE);
2012 }
2013
2014 /* tes constants can be emitted to VS or ES - which are common */
2015 static void evergreen_emit_tes_constant_buffers(struct r600_context *rctx, struct r600_atom *atom)
2016 {
2017 if (!rctx->tes_shader)
2018 return;
2019 evergreen_emit_constant_buffers(rctx, &rctx->constbuf_state[PIPE_SHADER_TESS_EVAL],
2020 EG_FETCH_CONSTANTS_OFFSET_VS,
2021 R_028180_ALU_CONST_BUFFER_SIZE_VS_0,
2022 R_028980_ALU_CONST_CACHE_VS_0,
2023 0);
2024 }
2025
2026 static void evergreen_emit_tcs_constant_buffers(struct r600_context *rctx, struct r600_atom *atom)
2027 {
2028 if (!rctx->tes_shader)
2029 return;
2030 evergreen_emit_constant_buffers(rctx, &rctx->constbuf_state[PIPE_SHADER_TESS_CTRL],
2031 EG_FETCH_CONSTANTS_OFFSET_HS,
2032 R_028F80_ALU_CONST_BUFFER_SIZE_HS_0,
2033 R_028F00_ALU_CONST_CACHE_HS_0,
2034 0);
2035 }
2036
2037 static void evergreen_emit_sampler_views(struct r600_context *rctx,
2038 struct r600_samplerview_state *state,
2039 unsigned resource_id_base, unsigned pkt_flags)
2040 {
2041 struct radeon_winsys_cs *cs = rctx->b.gfx.cs;
2042 uint32_t dirty_mask = state->dirty_mask;
2043
2044 while (dirty_mask) {
2045 struct r600_pipe_sampler_view *rview;
2046 unsigned resource_index = u_bit_scan(&dirty_mask);
2047 unsigned reloc;
2048
2049 rview = state->views[resource_index];
2050 assert(rview);
2051
2052 radeon_emit(cs, PKT3(PKT3_SET_RESOURCE, 8, 0) | pkt_flags);
2053 radeon_emit(cs, (resource_id_base + resource_index) * 8);
2054 radeon_emit_array(cs, rview->tex_resource_words, 8);
2055
2056 reloc = radeon_add_to_buffer_list(&rctx->b, &rctx->b.gfx, rview->tex_resource,
2057 RADEON_USAGE_READ,
2058 r600_get_sampler_view_priority(rview->tex_resource));
2059 radeon_emit(cs, PKT3(PKT3_NOP, 0, 0) | pkt_flags);
2060 radeon_emit(cs, reloc);
2061
2062 if (!rview->skip_mip_address_reloc) {
2063 radeon_emit(cs, PKT3(PKT3_NOP, 0, 0) | pkt_flags);
2064 radeon_emit(cs, reloc);
2065 }
2066 }
2067 state->dirty_mask = 0;
2068 }
2069
2070 static void evergreen_emit_vs_sampler_views(struct r600_context *rctx, struct r600_atom *atom)
2071 {
2072 if (rctx->vs_shader->current->shader.vs_as_ls) {
2073 evergreen_emit_sampler_views(rctx, &rctx->samplers[PIPE_SHADER_VERTEX].views,
2074 EG_FETCH_CONSTANTS_OFFSET_LS + R600_MAX_CONST_BUFFERS, 0);
2075 } else {
2076 evergreen_emit_sampler_views(rctx, &rctx->samplers[PIPE_SHADER_VERTEX].views,
2077 EG_FETCH_CONSTANTS_OFFSET_VS + R600_MAX_CONST_BUFFERS, 0);
2078 }
2079 }
2080
2081 static void evergreen_emit_gs_sampler_views(struct r600_context *rctx, struct r600_atom *atom)
2082 {
2083 evergreen_emit_sampler_views(rctx, &rctx->samplers[PIPE_SHADER_GEOMETRY].views,
2084 EG_FETCH_CONSTANTS_OFFSET_GS + R600_MAX_CONST_BUFFERS, 0);
2085 }
2086
2087 static void evergreen_emit_tcs_sampler_views(struct r600_context *rctx, struct r600_atom *atom)
2088 {
2089 evergreen_emit_sampler_views(rctx, &rctx->samplers[PIPE_SHADER_TESS_CTRL].views,
2090 EG_FETCH_CONSTANTS_OFFSET_HS + R600_MAX_CONST_BUFFERS, 0);
2091 }
2092
2093 static void evergreen_emit_tes_sampler_views(struct r600_context *rctx, struct r600_atom *atom)
2094 {
2095 evergreen_emit_sampler_views(rctx, &rctx->samplers[PIPE_SHADER_TESS_EVAL].views,
2096 EG_FETCH_CONSTANTS_OFFSET_VS + R600_MAX_CONST_BUFFERS, 0);
2097 }
2098
2099 static void evergreen_emit_ps_sampler_views(struct r600_context *rctx, struct r600_atom *atom)
2100 {
2101 evergreen_emit_sampler_views(rctx, &rctx->samplers[PIPE_SHADER_FRAGMENT].views,
2102 EG_FETCH_CONSTANTS_OFFSET_PS + R600_MAX_CONST_BUFFERS, 0);
2103 }
2104
2105 static void evergreen_emit_cs_sampler_views(struct r600_context *rctx, struct r600_atom *atom)
2106 {
2107 evergreen_emit_sampler_views(rctx, &rctx->samplers[PIPE_SHADER_COMPUTE].views,
2108 EG_FETCH_CONSTANTS_OFFSET_CS + 2, RADEON_CP_PACKET3_COMPUTE_MODE);
2109 }
2110
2111 static void evergreen_emit_sampler_states(struct r600_context *rctx,
2112 struct r600_textures_info *texinfo,
2113 unsigned resource_id_base,
2114 unsigned border_index_reg,
2115 unsigned pkt_flags)
2116 {
2117 struct radeon_winsys_cs *cs = rctx->b.gfx.cs;
2118 uint32_t dirty_mask = texinfo->states.dirty_mask;
2119
2120 while (dirty_mask) {
2121 struct r600_pipe_sampler_state *rstate;
2122 unsigned i = u_bit_scan(&dirty_mask);
2123
2124 rstate = texinfo->states.states[i];
2125 assert(rstate);
2126
2127 radeon_emit(cs, PKT3(PKT3_SET_SAMPLER, 3, 0) | pkt_flags);
2128 radeon_emit(cs, (resource_id_base + i) * 3);
2129 radeon_emit_array(cs, rstate->tex_sampler_words, 3);
2130
2131 if (rstate->border_color_use) {
2132 radeon_set_config_reg_seq(cs, border_index_reg, 5);
2133 radeon_emit(cs, i);
2134 radeon_emit_array(cs, rstate->border_color.ui, 4);
2135 }
2136 }
2137 texinfo->states.dirty_mask = 0;
2138 }
2139
2140 static void evergreen_emit_vs_sampler_states(struct r600_context *rctx, struct r600_atom *atom)
2141 {
2142 if (rctx->vs_shader->current->shader.vs_as_ls) {
2143 evergreen_emit_sampler_states(rctx, &rctx->samplers[PIPE_SHADER_VERTEX], 72,
2144 R_00A450_TD_LS_SAMPLER0_BORDER_COLOR_INDEX, 0);
2145 } else {
2146 evergreen_emit_sampler_states(rctx, &rctx->samplers[PIPE_SHADER_VERTEX], 18,
2147 R_00A414_TD_VS_SAMPLER0_BORDER_INDEX, 0);
2148 }
2149 }
2150
2151 static void evergreen_emit_gs_sampler_states(struct r600_context *rctx, struct r600_atom *atom)
2152 {
2153 evergreen_emit_sampler_states(rctx, &rctx->samplers[PIPE_SHADER_GEOMETRY], 36,
2154 R_00A428_TD_GS_SAMPLER0_BORDER_INDEX, 0);
2155 }
2156
2157 static void evergreen_emit_tcs_sampler_states(struct r600_context *rctx, struct r600_atom *atom)
2158 {
2159 evergreen_emit_sampler_states(rctx, &rctx->samplers[PIPE_SHADER_TESS_CTRL], 54,
2160 R_00A43C_TD_HS_SAMPLER0_BORDER_COLOR_INDEX, 0);
2161 }
2162
2163 static void evergreen_emit_tes_sampler_states(struct r600_context *rctx, struct r600_atom *atom)
2164 {
2165 evergreen_emit_sampler_states(rctx, &rctx->samplers[PIPE_SHADER_TESS_EVAL], 18,
2166 R_00A414_TD_VS_SAMPLER0_BORDER_INDEX, 0);
2167 }
2168
2169 static void evergreen_emit_ps_sampler_states(struct r600_context *rctx, struct r600_atom *atom)
2170 {
2171 evergreen_emit_sampler_states(rctx, &rctx->samplers[PIPE_SHADER_FRAGMENT], 0,
2172 R_00A400_TD_PS_SAMPLER0_BORDER_INDEX, 0);
2173 }
2174
2175 static void evergreen_emit_cs_sampler_states(struct r600_context *rctx, struct r600_atom *atom)
2176 {
2177 evergreen_emit_sampler_states(rctx, &rctx->samplers[PIPE_SHADER_COMPUTE], 90,
2178 R_00A464_TD_CS_SAMPLER0_BORDER_INDEX,
2179 RADEON_CP_PACKET3_COMPUTE_MODE);
2180 }
2181
2182 static void evergreen_emit_sample_mask(struct r600_context *rctx, struct r600_atom *a)
2183 {
2184 struct r600_sample_mask *s = (struct r600_sample_mask*)a;
2185 uint8_t mask = s->sample_mask;
2186
2187 radeon_set_context_reg(rctx->b.gfx.cs, R_028C3C_PA_SC_AA_MASK,
2188 mask | (mask << 8) | (mask << 16) | (mask << 24));
2189 }
2190
2191 static void cayman_emit_sample_mask(struct r600_context *rctx, struct r600_atom *a)
2192 {
2193 struct r600_sample_mask *s = (struct r600_sample_mask*)a;
2194 struct radeon_winsys_cs *cs = rctx->b.gfx.cs;
2195 uint16_t mask = s->sample_mask;
2196
2197 radeon_set_context_reg_seq(cs, CM_R_028C38_PA_SC_AA_MASK_X0Y0_X1Y0, 2);
2198 radeon_emit(cs, mask | (mask << 16)); /* X0Y0_X1Y0 */
2199 radeon_emit(cs, mask | (mask << 16)); /* X0Y1_X1Y1 */
2200 }
2201
2202 static void evergreen_emit_vertex_fetch_shader(struct r600_context *rctx, struct r600_atom *a)
2203 {
2204 struct radeon_winsys_cs *cs = rctx->b.gfx.cs;
2205 struct r600_cso_state *state = (struct r600_cso_state*)a;
2206 struct r600_fetch_shader *shader = (struct r600_fetch_shader*)state->cso;
2207
2208 radeon_set_context_reg(cs, R_0288A4_SQ_PGM_START_FS,
2209 (shader->buffer->gpu_address + shader->offset) >> 8);
2210 radeon_emit(cs, PKT3(PKT3_NOP, 0, 0));
2211 radeon_emit(cs, radeon_add_to_buffer_list(&rctx->b, &rctx->b.gfx, shader->buffer,
2212 RADEON_USAGE_READ,
2213 RADEON_PRIO_INTERNAL_SHADER));
2214 }
2215
2216 static void evergreen_emit_shader_stages(struct r600_context *rctx, struct r600_atom *a)
2217 {
2218 struct radeon_winsys_cs *cs = rctx->b.gfx.cs;
2219 struct r600_shader_stages_state *state = (struct r600_shader_stages_state*)a;
2220
2221 uint32_t v = 0, v2 = 0, primid = 0, tf_param = 0;
2222
2223 if (rctx->vs_shader->current->shader.vs_as_gs_a) {
2224 v2 = S_028A40_MODE(V_028A40_GS_SCENARIO_A);
2225 primid = 1;
2226 }
2227
2228 if (state->geom_enable) {
2229 uint32_t cut_val;
2230
2231 if (rctx->gs_shader->gs_max_out_vertices <= 128)
2232 cut_val = V_028A40_GS_CUT_128;
2233 else if (rctx->gs_shader->gs_max_out_vertices <= 256)
2234 cut_val = V_028A40_GS_CUT_256;
2235 else if (rctx->gs_shader->gs_max_out_vertices <= 512)
2236 cut_val = V_028A40_GS_CUT_512;
2237 else
2238 cut_val = V_028A40_GS_CUT_1024;
2239
2240 v = S_028B54_GS_EN(1) |
2241 S_028B54_VS_EN(V_028B54_VS_STAGE_COPY_SHADER);
2242 if (!rctx->tes_shader)
2243 v |= S_028B54_ES_EN(V_028B54_ES_STAGE_REAL);
2244
2245 v2 = S_028A40_MODE(V_028A40_GS_SCENARIO_G) |
2246 S_028A40_CUT_MODE(cut_val);
2247
2248 if (rctx->gs_shader->current->shader.gs_prim_id_input)
2249 primid = 1;
2250 }
2251
2252 if (rctx->tes_shader) {
2253 uint32_t type, partitioning, topology;
2254 struct tgsi_shader_info *info = &rctx->tes_shader->current->selector->info;
2255 unsigned tes_prim_mode = info->properties[TGSI_PROPERTY_TES_PRIM_MODE];
2256 unsigned tes_spacing = info->properties[TGSI_PROPERTY_TES_SPACING];
2257 bool tes_vertex_order_cw = info->properties[TGSI_PROPERTY_TES_VERTEX_ORDER_CW];
2258 bool tes_point_mode = info->properties[TGSI_PROPERTY_TES_POINT_MODE];
2259 switch (tes_prim_mode) {
2260 case PIPE_PRIM_LINES:
2261 type = V_028B6C_TESS_ISOLINE;
2262 break;
2263 case PIPE_PRIM_TRIANGLES:
2264 type = V_028B6C_TESS_TRIANGLE;
2265 break;
2266 case PIPE_PRIM_QUADS:
2267 type = V_028B6C_TESS_QUAD;
2268 break;
2269 default:
2270 assert(0);
2271 return;
2272 }
2273
2274 switch (tes_spacing) {
2275 case PIPE_TESS_SPACING_FRACTIONAL_ODD:
2276 partitioning = V_028B6C_PART_FRAC_ODD;
2277 break;
2278 case PIPE_TESS_SPACING_FRACTIONAL_EVEN:
2279 partitioning = V_028B6C_PART_FRAC_EVEN;
2280 break;
2281 case PIPE_TESS_SPACING_EQUAL:
2282 partitioning = V_028B6C_PART_INTEGER;
2283 break;
2284 default:
2285 assert(0);
2286 return;
2287 }
2288
2289 if (tes_point_mode)
2290 topology = V_028B6C_OUTPUT_POINT;
2291 else if (tes_prim_mode == PIPE_PRIM_LINES)
2292 topology = V_028B6C_OUTPUT_LINE;
2293 else if (tes_vertex_order_cw)
2294 /* XXX follow radeonsi and invert */
2295 topology = V_028B6C_OUTPUT_TRIANGLE_CCW;
2296 else
2297 topology = V_028B6C_OUTPUT_TRIANGLE_CW;
2298
2299 tf_param = S_028B6C_TYPE(type) |
2300 S_028B6C_PARTITIONING(partitioning) |
2301 S_028B6C_TOPOLOGY(topology);
2302 }
2303
2304 if (rctx->tes_shader) {
2305 v |= S_028B54_LS_EN(V_028B54_LS_STAGE_ON) |
2306 S_028B54_HS_EN(1);
2307 if (!state->geom_enable)
2308 v |= S_028B54_VS_EN(V_028B54_VS_STAGE_DS);
2309 else
2310 v |= S_028B54_ES_EN(V_028B54_ES_STAGE_DS);
2311 }
2312
2313 radeon_set_context_reg(cs, R_028AB8_VGT_VTX_CNT_EN, v ? 1 : 0 );
2314 radeon_set_context_reg(cs, R_028B54_VGT_SHADER_STAGES_EN, v);
2315 radeon_set_context_reg(cs, R_028A40_VGT_GS_MODE, v2);
2316 radeon_set_context_reg(cs, R_028A84_VGT_PRIMITIVEID_EN, primid);
2317 radeon_set_context_reg(cs, R_028B6C_VGT_TF_PARAM, tf_param);
2318 }
2319
2320 static void evergreen_emit_gs_rings(struct r600_context *rctx, struct r600_atom *a)
2321 {
2322 struct radeon_winsys_cs *cs = rctx->b.gfx.cs;
2323 struct r600_gs_rings_state *state = (struct r600_gs_rings_state*)a;
2324 struct r600_resource *rbuffer;
2325
2326 radeon_set_config_reg(cs, R_008040_WAIT_UNTIL, S_008040_WAIT_3D_IDLE(1));
2327 radeon_emit(cs, PKT3(PKT3_EVENT_WRITE, 0, 0));
2328 radeon_emit(cs, EVENT_TYPE(EVENT_TYPE_VGT_FLUSH));
2329
2330 if (state->enable) {
2331 rbuffer =(struct r600_resource*)state->esgs_ring.buffer;
2332 radeon_set_config_reg(cs, R_008C40_SQ_ESGS_RING_BASE,
2333 rbuffer->gpu_address >> 8);
2334 radeon_emit(cs, PKT3(PKT3_NOP, 0, 0));
2335 radeon_emit(cs, radeon_add_to_buffer_list(&rctx->b, &rctx->b.gfx, rbuffer,
2336 RADEON_USAGE_READWRITE,
2337 RADEON_PRIO_RINGS_STREAMOUT));
2338 radeon_set_config_reg(cs, R_008C44_SQ_ESGS_RING_SIZE,
2339 state->esgs_ring.buffer_size >> 8);
2340
2341 rbuffer =(struct r600_resource*)state->gsvs_ring.buffer;
2342 radeon_set_config_reg(cs, R_008C48_SQ_GSVS_RING_BASE,
2343 rbuffer->gpu_address >> 8);
2344 radeon_emit(cs, PKT3(PKT3_NOP, 0, 0));
2345 radeon_emit(cs, radeon_add_to_buffer_list(&rctx->b, &rctx->b.gfx, rbuffer,
2346 RADEON_USAGE_READWRITE,
2347 RADEON_PRIO_RINGS_STREAMOUT));
2348 radeon_set_config_reg(cs, R_008C4C_SQ_GSVS_RING_SIZE,
2349 state->gsvs_ring.buffer_size >> 8);
2350 } else {
2351 radeon_set_config_reg(cs, R_008C44_SQ_ESGS_RING_SIZE, 0);
2352 radeon_set_config_reg(cs, R_008C4C_SQ_GSVS_RING_SIZE, 0);
2353 }
2354
2355 radeon_set_config_reg(cs, R_008040_WAIT_UNTIL, S_008040_WAIT_3D_IDLE(1));
2356 radeon_emit(cs, PKT3(PKT3_EVENT_WRITE, 0, 0));
2357 radeon_emit(cs, EVENT_TYPE(EVENT_TYPE_VGT_FLUSH));
2358 }
2359
2360 void cayman_init_common_regs(struct r600_command_buffer *cb,
2361 enum chip_class ctx_chip_class,
2362 enum radeon_family ctx_family,
2363 int ctx_drm_minor)
2364 {
2365 r600_store_config_reg_seq(cb, R_008C00_SQ_CONFIG, 2);
2366 r600_store_value(cb, S_008C00_EXPORT_SRC_C(1)); /* R_008C00_SQ_CONFIG */
2367 /* always set the temp clauses */
2368 r600_store_value(cb, S_008C04_NUM_CLAUSE_TEMP_GPRS(4)); /* R_008C04_SQ_GPR_RESOURCE_MGMT_1 */
2369
2370 r600_store_config_reg_seq(cb, R_008C10_SQ_GLOBAL_GPR_RESOURCE_MGMT_1, 2);
2371 r600_store_value(cb, 0); /* R_008C10_SQ_GLOBAL_GPR_RESOURCE_MGMT_1 */
2372 r600_store_value(cb, 0); /* R_008C14_SQ_GLOBAL_GPR_RESOURCE_MGMT_2 */
2373
2374 r600_store_config_reg(cb, R_008D8C_SQ_DYN_GPR_CNTL_PS_FLUSH_REQ, (1 << 8));
2375
2376 r600_store_context_reg_seq(cb, R_028350_SX_MISC, 2);
2377 r600_store_value(cb, 0);
2378 r600_store_value(cb, S_028354_SURFACE_SYNC_MASK(0xf));
2379
2380 r600_store_context_reg(cb, R_028800_DB_DEPTH_CONTROL, 0);
2381 }
2382
2383 static void cayman_init_atom_start_cs(struct r600_context *rctx)
2384 {
2385 struct r600_command_buffer *cb = &rctx->start_cs_cmd;
2386 int tmp, i;
2387
2388 r600_init_command_buffer(cb, 338);
2389
2390 /* This must be first. */
2391 r600_store_value(cb, PKT3(PKT3_CONTEXT_CONTROL, 1, 0));
2392 r600_store_value(cb, 0x80000000);
2393 r600_store_value(cb, 0x80000000);
2394
2395 /* We're setting config registers here. */
2396 r600_store_value(cb, PKT3(PKT3_EVENT_WRITE, 0, 0));
2397 r600_store_value(cb, EVENT_TYPE(EVENT_TYPE_PS_PARTIAL_FLUSH) | EVENT_INDEX(4));
2398
2399 /* This enables pipeline stat & streamout queries.
2400 * They are only disabled by blits.
2401 */
2402 r600_store_value(cb, PKT3(PKT3_EVENT_WRITE, 0, 0));
2403 r600_store_value(cb, EVENT_TYPE(EVENT_TYPE_PIPELINESTAT_START) | EVENT_INDEX(0));
2404
2405 cayman_init_common_regs(cb, rctx->b.chip_class,
2406 rctx->b.family, rctx->screen->b.info.drm_minor);
2407
2408 r600_store_config_reg(cb, R_009100_SPI_CONFIG_CNTL, 0);
2409 r600_store_config_reg(cb, R_00913C_SPI_CONFIG_CNTL_1, S_00913C_VTX_DONE_DELAY(4));
2410
2411 /* remove LS/HS from one SIMD for hw workaround */
2412 r600_store_config_reg_seq(cb, R_008E20_SQ_STATIC_THREAD_MGMT1, 3);
2413 r600_store_value(cb, 0xffffffff);
2414 r600_store_value(cb, 0xffffffff);
2415 r600_store_value(cb, 0xfffffffe);
2416
2417 r600_store_context_reg_seq(cb, R_028900_SQ_ESGS_RING_ITEMSIZE, 6);
2418 r600_store_value(cb, 0); /* R_028900_SQ_ESGS_RING_ITEMSIZE */
2419 r600_store_value(cb, 0); /* R_028904_SQ_GSVS_RING_ITEMSIZE */
2420 r600_store_value(cb, 0); /* R_028908_SQ_ESTMP_RING_ITEMSIZE */
2421 r600_store_value(cb, 0); /* R_02890C_SQ_GSTMP_RING_ITEMSIZE */
2422 r600_store_value(cb, 0); /* R_028910_SQ_VSTMP_RING_ITEMSIZE */
2423 r600_store_value(cb, 0); /* R_028914_SQ_PSTMP_RING_ITEMSIZE */
2424
2425 r600_store_context_reg_seq(cb, R_02891C_SQ_GS_VERT_ITEMSIZE, 4);
2426 r600_store_value(cb, 0); /* R_02891C_SQ_GS_VERT_ITEMSIZE */
2427 r600_store_value(cb, 0); /* R_028920_SQ_GS_VERT_ITEMSIZE_1 */
2428 r600_store_value(cb, 0); /* R_028924_SQ_GS_VERT_ITEMSIZE_2 */
2429 r600_store_value(cb, 0); /* R_028928_SQ_GS_VERT_ITEMSIZE_3 */
2430
2431 r600_store_context_reg_seq(cb, R_028A10_VGT_OUTPUT_PATH_CNTL, 13);
2432 r600_store_value(cb, 0); /* R_028A10_VGT_OUTPUT_PATH_CNTL */
2433 r600_store_value(cb, 0); /* R_028A14_VGT_HOS_CNTL */
2434 r600_store_value(cb, fui(64)); /* R_028A18_VGT_HOS_MAX_TESS_LEVEL */
2435 r600_store_value(cb, fui(0)); /* R_028A1C_VGT_HOS_MIN_TESS_LEVEL */
2436 r600_store_value(cb, 16); /* R_028A20_VGT_HOS_REUSE_DEPTH */
2437 r600_store_value(cb, 0); /* R_028A24_VGT_GROUP_PRIM_TYPE */
2438 r600_store_value(cb, 0); /* R_028A28_VGT_GROUP_FIRST_DECR */
2439 r600_store_value(cb, 0); /* R_028A2C_VGT_GROUP_DECR */
2440 r600_store_value(cb, 0); /* R_028A30_VGT_GROUP_VECT_0_CNTL */
2441 r600_store_value(cb, 0); /* R_028A34_VGT_GROUP_VECT_1_CNTL */
2442 r600_store_value(cb, 0); /* R_028A38_VGT_GROUP_VECT_0_FMT_CNTL */
2443 r600_store_value(cb, 0); /* R_028A3C_VGT_GROUP_VECT_1_FMT_CNTL */
2444 r600_store_value(cb, 0); /* R_028A40_VGT_GS_MODE */
2445
2446 r600_store_context_reg(cb, R_028B98_VGT_STRMOUT_BUFFER_CONFIG, 0);
2447
2448 r600_store_config_reg(cb, R_008A14_PA_CL_ENHANCE, (3 << 1) | 1);
2449
2450 r600_store_context_reg_seq(cb, CM_R_028BD4_PA_SC_CENTROID_PRIORITY_0, 2);
2451 r600_store_value(cb, 0x76543210); /* CM_R_028BD4_PA_SC_CENTROID_PRIORITY_0 */
2452 r600_store_value(cb, 0xfedcba98); /* CM_R_028BD8_PA_SC_CENTROID_PRIORITY_1 */
2453
2454 r600_store_context_reg_seq(cb, R_0288E8_SQ_LDS_ALLOC, 2);
2455 r600_store_value(cb, 0); /* R_0288E8_SQ_LDS_ALLOC */
2456 r600_store_value(cb, 0); /* R_0288EC_SQ_LDS_ALLOC_PS */
2457
2458 r600_store_context_reg(cb, R_0288F0_SQ_VTX_SEMANTIC_CLEAR, ~0);
2459
2460 r600_store_context_reg_seq(cb, R_028400_VGT_MAX_VTX_INDX, 2);
2461 r600_store_value(cb, ~0); /* R_028400_VGT_MAX_VTX_INDX */
2462 r600_store_value(cb, 0); /* R_028404_VGT_MIN_VTX_INDX */
2463
2464 r600_store_ctl_const(cb, R_03CFF0_SQ_VTX_BASE_VTX_LOC, 0);
2465
2466 r600_store_context_reg(cb, R_028028_DB_STENCIL_CLEAR, 0);
2467
2468 r600_store_context_reg(cb, R_0286DC_SPI_FOG_CNTL, 0);
2469
2470 r600_store_context_reg_seq(cb, R_028AC0_DB_SRESULTS_COMPARE_STATE0, 3);
2471 r600_store_value(cb, 0); /* R_028AC0_DB_SRESULTS_COMPARE_STATE0 */
2472 r600_store_value(cb, 0); /* R_028AC4_DB_SRESULTS_COMPARE_STATE1 */
2473 r600_store_value(cb, 0); /* R_028AC8_DB_PRELOAD_CONTROL */
2474
2475 r600_store_context_reg(cb, R_028200_PA_SC_WINDOW_OFFSET, 0);
2476 r600_store_context_reg(cb, R_02820C_PA_SC_CLIPRECT_RULE, 0xFFFF);
2477
2478 r600_store_context_reg_seq(cb, R_0282D0_PA_SC_VPORT_ZMIN_0, 2 * R600_MAX_VIEWPORTS);
2479 for (tmp = 0; tmp < R600_MAX_VIEWPORTS; tmp++) {
2480 r600_store_value(cb, 0); /* R_0282D0_PA_SC_VPORT_ZMIN_0 */
2481 r600_store_value(cb, fui(1.0)); /* R_0282D4_PA_SC_VPORT_ZMAX_0 */
2482 }
2483
2484 r600_store_context_reg(cb, R_028230_PA_SC_EDGERULE, 0xAAAAAAAA);
2485 r600_store_context_reg(cb, R_028820_PA_CL_NANINF_CNTL, 0);
2486
2487 r600_store_context_reg_seq(cb, CM_R_028BE8_PA_CL_GB_VERT_CLIP_ADJ, 4);
2488 r600_store_value(cb, fui(1.0)); /* CM_R_028BE8_PA_CL_GB_VERT_CLIP_ADJ */
2489 r600_store_value(cb, fui(1.0)); /* CM_R_028BEC_PA_CL_GB_VERT_DISC_ADJ */
2490 r600_store_value(cb, fui(1.0)); /* CM_R_028BF0_PA_CL_GB_HORZ_CLIP_ADJ */
2491 r600_store_value(cb, fui(1.0)); /* CM_R_028BF4_PA_CL_GB_HORZ_DISC_ADJ */
2492
2493 r600_store_context_reg_seq(cb, R_028240_PA_SC_GENERIC_SCISSOR_TL, 2);
2494 r600_store_value(cb, 0); /* R_028240_PA_SC_GENERIC_SCISSOR_TL */
2495 r600_store_value(cb, S_028244_BR_X(16384) | S_028244_BR_Y(16384)); /* R_028244_PA_SC_GENERIC_SCISSOR_BR */
2496
2497 r600_store_context_reg_seq(cb, R_028030_PA_SC_SCREEN_SCISSOR_TL, 2);
2498 r600_store_value(cb, 0); /* R_028030_PA_SC_SCREEN_SCISSOR_TL */
2499 r600_store_value(cb, S_028034_BR_X(16384) | S_028034_BR_Y(16384)); /* R_028034_PA_SC_SCREEN_SCISSOR_BR */
2500
2501 r600_store_context_reg(cb, R_028848_SQ_PGM_RESOURCES_2_PS, S_028848_SINGLE_ROUND(V_SQ_ROUND_NEAREST_EVEN));
2502 r600_store_context_reg(cb, R_028864_SQ_PGM_RESOURCES_2_VS, S_028864_SINGLE_ROUND(V_SQ_ROUND_NEAREST_EVEN));
2503 r600_store_context_reg(cb, R_02887C_SQ_PGM_RESOURCES_2_GS, S_028848_SINGLE_ROUND(V_SQ_ROUND_NEAREST_EVEN));
2504 r600_store_context_reg(cb, R_028894_SQ_PGM_RESOURCES_2_ES, S_028848_SINGLE_ROUND(V_SQ_ROUND_NEAREST_EVEN));
2505 r600_store_context_reg(cb, R_0288C0_SQ_PGM_RESOURCES_2_HS, S_028848_SINGLE_ROUND(V_SQ_ROUND_NEAREST_EVEN));
2506 r600_store_context_reg(cb, R_0288D8_SQ_PGM_RESOURCES_2_LS, S_028848_SINGLE_ROUND(V_SQ_ROUND_NEAREST_EVEN));
2507
2508 r600_store_context_reg(cb, R_0288A8_SQ_PGM_RESOURCES_FS, 0);
2509
2510 /* to avoid GPU doing any preloading of constant from random address */
2511 r600_store_context_reg_seq(cb, R_028140_ALU_CONST_BUFFER_SIZE_PS_0, 16);
2512 for (i = 0; i < 16; i++)
2513 r600_store_value(cb, 0);
2514
2515 r600_store_context_reg_seq(cb, R_028180_ALU_CONST_BUFFER_SIZE_VS_0, 16);
2516 for (i = 0; i < 16; i++)
2517 r600_store_value(cb, 0);
2518
2519 r600_store_context_reg_seq(cb, R_0281C0_ALU_CONST_BUFFER_SIZE_GS_0, 16);
2520 for (i = 0; i < 16; i++)
2521 r600_store_value(cb, 0);
2522
2523 r600_store_context_reg_seq(cb, R_028FC0_ALU_CONST_BUFFER_SIZE_LS_0, 16);
2524 for (i = 0; i < 16; i++)
2525 r600_store_value(cb, 0);
2526
2527 r600_store_context_reg_seq(cb, R_028F80_ALU_CONST_BUFFER_SIZE_HS_0, 16);
2528 for (i = 0; i < 16; i++)
2529 r600_store_value(cb, 0);
2530
2531 if (rctx->screen->b.has_streamout) {
2532 r600_store_context_reg(cb, R_028B28_VGT_STRMOUT_DRAW_OPAQUE_OFFSET, 0);
2533 }
2534
2535 r600_store_context_reg(cb, R_028010_DB_RENDER_OVERRIDE2, 0);
2536 r600_store_context_reg(cb, R_028234_PA_SU_HARDWARE_SCREEN_OFFSET, 0);
2537 r600_store_context_reg(cb, R_0286C8_SPI_THREAD_GROUPING, 0);
2538 r600_store_context_reg_seq(cb, R_0286E4_SPI_PS_IN_CONTROL_2, 2);
2539 r600_store_value(cb, 0); /* R_0286E4_SPI_PS_IN_CONTROL_2 */
2540 r600_store_value(cb, 0); /* R_0286E8_SPI_COMPUTE_INPUT_CNTL */
2541
2542 r600_store_context_reg_seq(cb, R_028B54_VGT_SHADER_STAGES_EN, 2);
2543 r600_store_value(cb, 0); /* R028B54_VGT_SHADER_STAGES_EN */
2544 r600_store_value(cb, 0); /* R028B58_VGT_LS_HS_CONFIG */
2545 r600_store_context_reg(cb, R_028B6C_VGT_TF_PARAM, 0);
2546 eg_store_loop_const(cb, R_03A200_SQ_LOOP_CONST_0, 0x01000FFF);
2547 eg_store_loop_const(cb, R_03A200_SQ_LOOP_CONST_0 + (32 * 4), 0x01000FFF);
2548 eg_store_loop_const(cb, R_03A200_SQ_LOOP_CONST_0 + (64 * 4), 0x01000FFF);
2549 eg_store_loop_const(cb, R_03A200_SQ_LOOP_CONST_0 + (96 * 4), 0x01000FFF);
2550 eg_store_loop_const(cb, R_03A200_SQ_LOOP_CONST_0 + (128 * 4), 0x01000FFF);
2551 }
2552
2553 void evergreen_init_common_regs(struct r600_context *rctx, struct r600_command_buffer *cb,
2554 enum chip_class ctx_chip_class,
2555 enum radeon_family ctx_family,
2556 int ctx_drm_minor)
2557 {
2558 int ps_prio;
2559 int vs_prio;
2560 int gs_prio;
2561 int es_prio;
2562
2563 int hs_prio;
2564 int cs_prio;
2565 int ls_prio;
2566
2567 unsigned tmp;
2568
2569 ps_prio = 0;
2570 vs_prio = 1;
2571 gs_prio = 2;
2572 es_prio = 3;
2573 hs_prio = 3;
2574 ls_prio = 3;
2575 cs_prio = 0;
2576
2577 rctx->default_gprs[R600_HW_STAGE_PS] = 93;
2578 rctx->default_gprs[R600_HW_STAGE_VS] = 46;
2579 rctx->r6xx_num_clause_temp_gprs = 4;
2580 rctx->default_gprs[R600_HW_STAGE_GS] = 31;
2581 rctx->default_gprs[R600_HW_STAGE_ES] = 31;
2582 rctx->default_gprs[EG_HW_STAGE_HS] = 23;
2583 rctx->default_gprs[EG_HW_STAGE_LS] = 23;
2584
2585 tmp = 0;
2586 switch (ctx_family) {
2587 case CHIP_CEDAR:
2588 case CHIP_PALM:
2589 case CHIP_SUMO:
2590 case CHIP_SUMO2:
2591 case CHIP_CAICOS:
2592 break;
2593 default:
2594 tmp |= S_008C00_VC_ENABLE(1);
2595 break;
2596 }
2597 tmp |= S_008C00_EXPORT_SRC_C(1);
2598 tmp |= S_008C00_CS_PRIO(cs_prio);
2599 tmp |= S_008C00_LS_PRIO(ls_prio);
2600 tmp |= S_008C00_HS_PRIO(hs_prio);
2601 tmp |= S_008C00_PS_PRIO(ps_prio);
2602 tmp |= S_008C00_VS_PRIO(vs_prio);
2603 tmp |= S_008C00_GS_PRIO(gs_prio);
2604 tmp |= S_008C00_ES_PRIO(es_prio);
2605
2606 r600_store_config_reg_seq(cb, R_008C00_SQ_CONFIG, 1);
2607 r600_store_value(cb, tmp); /* R_008C00_SQ_CONFIG */
2608
2609 r600_store_config_reg_seq(cb, R_008C10_SQ_GLOBAL_GPR_RESOURCE_MGMT_1, 2);
2610 r600_store_value(cb, 0); /* R_008C10_SQ_GLOBAL_GPR_RESOURCE_MGMT_1 */
2611 r600_store_value(cb, 0); /* R_008C14_SQ_GLOBAL_GPR_RESOURCE_MGMT_2 */
2612
2613 /* The cs checker requires this register to be set. */
2614 r600_store_context_reg(cb, R_028800_DB_DEPTH_CONTROL, 0);
2615
2616 r600_store_context_reg_seq(cb, R_028350_SX_MISC, 2);
2617 r600_store_value(cb, 0);
2618 r600_store_value(cb, S_028354_SURFACE_SYNC_MASK(0xf));
2619
2620 return;
2621 }
2622
2623 void evergreen_init_atom_start_cs(struct r600_context *rctx)
2624 {
2625 struct r600_command_buffer *cb = &rctx->start_cs_cmd;
2626 int num_ps_threads;
2627 int num_vs_threads;
2628 int num_gs_threads;
2629 int num_es_threads;
2630 int num_hs_threads;
2631 int num_ls_threads;
2632
2633 int num_ps_stack_entries;
2634 int num_vs_stack_entries;
2635 int num_gs_stack_entries;
2636 int num_es_stack_entries;
2637 int num_hs_stack_entries;
2638 int num_ls_stack_entries;
2639 enum radeon_family family;
2640 unsigned tmp, i;
2641
2642 if (rctx->b.chip_class == CAYMAN) {
2643 cayman_init_atom_start_cs(rctx);
2644 return;
2645 }
2646
2647 r600_init_command_buffer(cb, 338);
2648
2649 /* This must be first. */
2650 r600_store_value(cb, PKT3(PKT3_CONTEXT_CONTROL, 1, 0));
2651 r600_store_value(cb, 0x80000000);
2652 r600_store_value(cb, 0x80000000);
2653
2654 /* We're setting config registers here. */
2655 r600_store_value(cb, PKT3(PKT3_EVENT_WRITE, 0, 0));
2656 r600_store_value(cb, EVENT_TYPE(EVENT_TYPE_PS_PARTIAL_FLUSH) | EVENT_INDEX(4));
2657
2658 /* This enables pipeline stat & streamout queries.
2659 * They are only disabled by blits.
2660 */
2661 r600_store_value(cb, PKT3(PKT3_EVENT_WRITE, 0, 0));
2662 r600_store_value(cb, EVENT_TYPE(EVENT_TYPE_PIPELINESTAT_START) | EVENT_INDEX(0));
2663
2664 evergreen_init_common_regs(rctx, cb, rctx->b.chip_class,
2665 rctx->b.family, rctx->screen->b.info.drm_minor);
2666
2667 family = rctx->b.family;
2668 switch (family) {
2669 case CHIP_CEDAR:
2670 default:
2671 num_ps_threads = 96;
2672 num_vs_threads = 16;
2673 num_gs_threads = 16;
2674 num_es_threads = 16;
2675 num_hs_threads = 16;
2676 num_ls_threads = 16;
2677 num_ps_stack_entries = 42;
2678 num_vs_stack_entries = 42;
2679 num_gs_stack_entries = 42;
2680 num_es_stack_entries = 42;
2681 num_hs_stack_entries = 42;
2682 num_ls_stack_entries = 42;
2683 break;
2684 case CHIP_REDWOOD:
2685 num_ps_threads = 128;
2686 num_vs_threads = 20;
2687 num_gs_threads = 20;
2688 num_es_threads = 20;
2689 num_hs_threads = 20;
2690 num_ls_threads = 20;
2691 num_ps_stack_entries = 42;
2692 num_vs_stack_entries = 42;
2693 num_gs_stack_entries = 42;
2694 num_es_stack_entries = 42;
2695 num_hs_stack_entries = 42;
2696 num_ls_stack_entries = 42;
2697 break;
2698 case CHIP_JUNIPER:
2699 num_ps_threads = 128;
2700 num_vs_threads = 20;
2701 num_gs_threads = 20;
2702 num_es_threads = 20;
2703 num_hs_threads = 20;
2704 num_ls_threads = 20;
2705 num_ps_stack_entries = 85;
2706 num_vs_stack_entries = 85;
2707 num_gs_stack_entries = 85;
2708 num_es_stack_entries = 85;
2709 num_hs_stack_entries = 85;
2710 num_ls_stack_entries = 85;
2711 break;
2712 case CHIP_CYPRESS:
2713 case CHIP_HEMLOCK:
2714 num_ps_threads = 128;
2715 num_vs_threads = 20;
2716 num_gs_threads = 20;
2717 num_es_threads = 20;
2718 num_hs_threads = 20;
2719 num_ls_threads = 20;
2720 num_ps_stack_entries = 85;
2721 num_vs_stack_entries = 85;
2722 num_gs_stack_entries = 85;
2723 num_es_stack_entries = 85;
2724 num_hs_stack_entries = 85;
2725 num_ls_stack_entries = 85;
2726 break;
2727 case CHIP_PALM:
2728 num_ps_threads = 96;
2729 num_vs_threads = 16;
2730 num_gs_threads = 16;
2731 num_es_threads = 16;
2732 num_hs_threads = 16;
2733 num_ls_threads = 16;
2734 num_ps_stack_entries = 42;
2735 num_vs_stack_entries = 42;
2736 num_gs_stack_entries = 42;
2737 num_es_stack_entries = 42;
2738 num_hs_stack_entries = 42;
2739 num_ls_stack_entries = 42;
2740 break;
2741 case CHIP_SUMO:
2742 num_ps_threads = 96;
2743 num_vs_threads = 25;
2744 num_gs_threads = 25;
2745 num_es_threads = 25;
2746 num_hs_threads = 16;
2747 num_ls_threads = 16;
2748 num_ps_stack_entries = 42;
2749 num_vs_stack_entries = 42;
2750 num_gs_stack_entries = 42;
2751 num_es_stack_entries = 42;
2752 num_hs_stack_entries = 42;
2753 num_ls_stack_entries = 42;
2754 break;
2755 case CHIP_SUMO2:
2756 num_ps_threads = 96;
2757 num_vs_threads = 25;
2758 num_gs_threads = 25;
2759 num_es_threads = 25;
2760 num_hs_threads = 16;
2761 num_ls_threads = 16;
2762 num_ps_stack_entries = 85;
2763 num_vs_stack_entries = 85;
2764 num_gs_stack_entries = 85;
2765 num_es_stack_entries = 85;
2766 num_hs_stack_entries = 85;
2767 num_ls_stack_entries = 85;
2768 break;
2769 case CHIP_BARTS:
2770 num_ps_threads = 128;
2771 num_vs_threads = 20;
2772 num_gs_threads = 20;
2773 num_es_threads = 20;
2774 num_hs_threads = 20;
2775 num_ls_threads = 20;
2776 num_ps_stack_entries = 85;
2777 num_vs_stack_entries = 85;
2778 num_gs_stack_entries = 85;
2779 num_es_stack_entries = 85;
2780 num_hs_stack_entries = 85;
2781 num_ls_stack_entries = 85;
2782 break;
2783 case CHIP_TURKS:
2784 num_ps_threads = 128;
2785 num_vs_threads = 20;
2786 num_gs_threads = 20;
2787 num_es_threads = 20;
2788 num_hs_threads = 20;
2789 num_ls_threads = 20;
2790 num_ps_stack_entries = 42;
2791 num_vs_stack_entries = 42;
2792 num_gs_stack_entries = 42;
2793 num_es_stack_entries = 42;
2794 num_hs_stack_entries = 42;
2795 num_ls_stack_entries = 42;
2796 break;
2797 case CHIP_CAICOS:
2798 num_ps_threads = 96;
2799 num_vs_threads = 10;
2800 num_gs_threads = 10;
2801 num_es_threads = 10;
2802 num_hs_threads = 10;
2803 num_ls_threads = 10;
2804 num_ps_stack_entries = 42;
2805 num_vs_stack_entries = 42;
2806 num_gs_stack_entries = 42;
2807 num_es_stack_entries = 42;
2808 num_hs_stack_entries = 42;
2809 num_ls_stack_entries = 42;
2810 break;
2811 }
2812
2813 tmp = S_008C18_NUM_PS_THREADS(num_ps_threads);
2814 tmp |= S_008C18_NUM_VS_THREADS(num_vs_threads);
2815 tmp |= S_008C18_NUM_GS_THREADS(num_gs_threads);
2816 tmp |= S_008C18_NUM_ES_THREADS(num_es_threads);
2817
2818 r600_store_config_reg_seq(cb, R_008C18_SQ_THREAD_RESOURCE_MGMT_1, 5);
2819 r600_store_value(cb, tmp); /* R_008C18_SQ_THREAD_RESOURCE_MGMT_1 */
2820
2821 tmp = S_008C1C_NUM_HS_THREADS(num_hs_threads);
2822 tmp |= S_008C1C_NUM_LS_THREADS(num_ls_threads);
2823 r600_store_value(cb, tmp); /* R_008C1C_SQ_THREAD_RESOURCE_MGMT_2 */
2824
2825 tmp = S_008C20_NUM_PS_STACK_ENTRIES(num_ps_stack_entries);
2826 tmp |= S_008C20_NUM_VS_STACK_ENTRIES(num_vs_stack_entries);
2827 r600_store_value(cb, tmp); /* R_008C20_SQ_STACK_RESOURCE_MGMT_1 */
2828
2829 tmp = S_008C24_NUM_GS_STACK_ENTRIES(num_gs_stack_entries);
2830 tmp |= S_008C24_NUM_ES_STACK_ENTRIES(num_es_stack_entries);
2831 r600_store_value(cb, tmp); /* R_008C24_SQ_STACK_RESOURCE_MGMT_2 */
2832
2833 tmp = S_008C28_NUM_HS_STACK_ENTRIES(num_hs_stack_entries);
2834 tmp |= S_008C28_NUM_LS_STACK_ENTRIES(num_ls_stack_entries);
2835 r600_store_value(cb, tmp); /* R_008C28_SQ_STACK_RESOURCE_MGMT_3 */
2836
2837 r600_store_config_reg(cb, R_008E2C_SQ_LDS_RESOURCE_MGMT,
2838 S_008E2C_NUM_PS_LDS(0x1000) | S_008E2C_NUM_LS_LDS(0x1000));
2839
2840 /* remove LS/HS from one SIMD for hw workaround */
2841 r600_store_config_reg_seq(cb, R_008E20_SQ_STATIC_THREAD_MGMT1, 3);
2842 r600_store_value(cb, 0xffffffff);
2843 r600_store_value(cb, 0xffffffff);
2844 r600_store_value(cb, 0xfffffffe);
2845
2846 r600_store_config_reg(cb, R_009100_SPI_CONFIG_CNTL, 0);
2847 r600_store_config_reg(cb, R_00913C_SPI_CONFIG_CNTL_1, S_00913C_VTX_DONE_DELAY(4));
2848
2849 r600_store_context_reg_seq(cb, R_028900_SQ_ESGS_RING_ITEMSIZE, 6);
2850 r600_store_value(cb, 0); /* R_028900_SQ_ESGS_RING_ITEMSIZE */
2851 r600_store_value(cb, 0); /* R_028904_SQ_GSVS_RING_ITEMSIZE */
2852 r600_store_value(cb, 0); /* R_028908_SQ_ESTMP_RING_ITEMSIZE */
2853 r600_store_value(cb, 0); /* R_02890C_SQ_GSTMP_RING_ITEMSIZE */
2854 r600_store_value(cb, 0); /* R_028910_SQ_VSTMP_RING_ITEMSIZE */
2855 r600_store_value(cb, 0); /* R_028914_SQ_PSTMP_RING_ITEMSIZE */
2856
2857 r600_store_context_reg_seq(cb, R_02891C_SQ_GS_VERT_ITEMSIZE, 4);
2858 r600_store_value(cb, 0); /* R_02891C_SQ_GS_VERT_ITEMSIZE */
2859 r600_store_value(cb, 0); /* R_028920_SQ_GS_VERT_ITEMSIZE_1 */
2860 r600_store_value(cb, 0); /* R_028924_SQ_GS_VERT_ITEMSIZE_2 */
2861 r600_store_value(cb, 0); /* R_028928_SQ_GS_VERT_ITEMSIZE_3 */
2862
2863 r600_store_context_reg_seq(cb, R_028A10_VGT_OUTPUT_PATH_CNTL, 13);
2864 r600_store_value(cb, 0); /* R_028A10_VGT_OUTPUT_PATH_CNTL */
2865 r600_store_value(cb, 0); /* R_028A14_VGT_HOS_CNTL */
2866 r600_store_value(cb, fui(64)); /* R_028A18_VGT_HOS_MAX_TESS_LEVEL */
2867 r600_store_value(cb, fui(1.0)); /* R_028A1C_VGT_HOS_MIN_TESS_LEVEL */
2868 r600_store_value(cb, 16); /* R_028A20_VGT_HOS_REUSE_DEPTH */
2869 r600_store_value(cb, 0); /* R_028A24_VGT_GROUP_PRIM_TYPE */
2870 r600_store_value(cb, 0); /* R_028A28_VGT_GROUP_FIRST_DECR */
2871 r600_store_value(cb, 0); /* R_028A2C_VGT_GROUP_DECR */
2872 r600_store_value(cb, 0); /* R_028A30_VGT_GROUP_VECT_0_CNTL */
2873 r600_store_value(cb, 0); /* R_028A34_VGT_GROUP_VECT_1_CNTL */
2874 r600_store_value(cb, 0); /* R_028A38_VGT_GROUP_VECT_0_FMT_CNTL */
2875 r600_store_value(cb, 0); /* R_028A3C_VGT_GROUP_VECT_1_FMT_CNTL */
2876 r600_store_value(cb, 0); /* R_028A40_VGT_GS_MODE */
2877
2878 r600_store_config_reg(cb, R_008A14_PA_CL_ENHANCE, (3 << 1) | 1);
2879
2880 r600_store_context_reg(cb, R_0288F0_SQ_VTX_SEMANTIC_CLEAR, ~0);
2881
2882 r600_store_context_reg_seq(cb, R_028400_VGT_MAX_VTX_INDX, 2);
2883 r600_store_value(cb, ~0); /* R_028400_VGT_MAX_VTX_INDX */
2884 r600_store_value(cb, 0); /* R_028404_VGT_MIN_VTX_INDX */
2885
2886 r600_store_ctl_const(cb, R_03CFF0_SQ_VTX_BASE_VTX_LOC, 0);
2887
2888 r600_store_context_reg(cb, R_028028_DB_STENCIL_CLEAR, 0);
2889
2890 r600_store_context_reg(cb, R_028200_PA_SC_WINDOW_OFFSET, 0);
2891 r600_store_context_reg(cb, R_02820C_PA_SC_CLIPRECT_RULE, 0xFFFF);
2892 r600_store_context_reg(cb, R_028230_PA_SC_EDGERULE, 0xAAAAAAAA);
2893
2894 r600_store_context_reg_seq(cb, R_0282D0_PA_SC_VPORT_ZMIN_0, 2 * R600_MAX_VIEWPORTS);
2895 for (tmp = 0; tmp < R600_MAX_VIEWPORTS; tmp++) {
2896 r600_store_value(cb, 0); /* R_0282D0_PA_SC_VPORT_ZMIN_0 */
2897 r600_store_value(cb, fui(1.0)); /* R_0282D4_PA_SC_VPORT_ZMAX_0 */
2898 }
2899
2900 r600_store_context_reg(cb, R_0286DC_SPI_FOG_CNTL, 0);
2901 r600_store_context_reg(cb, R_028820_PA_CL_NANINF_CNTL, 0);
2902
2903 r600_store_context_reg_seq(cb, R_028AC0_DB_SRESULTS_COMPARE_STATE0, 3);
2904 r600_store_value(cb, 0); /* R_028AC0_DB_SRESULTS_COMPARE_STATE0 */
2905 r600_store_value(cb, 0); /* R_028AC4_DB_SRESULTS_COMPARE_STATE1 */
2906 r600_store_value(cb, 0); /* R_028AC8_DB_PRELOAD_CONTROL */
2907
2908 r600_store_context_reg_seq(cb, R_028C0C_PA_CL_GB_VERT_CLIP_ADJ, 4);
2909 r600_store_value(cb, fui(1.0)); /* R_028C0C_PA_CL_GB_VERT_CLIP_ADJ */
2910 r600_store_value(cb, fui(1.0)); /* R_028C10_PA_CL_GB_VERT_DISC_ADJ */
2911 r600_store_value(cb, fui(1.0)); /* R_028C14_PA_CL_GB_HORZ_CLIP_ADJ */
2912 r600_store_value(cb, fui(1.0)); /* R_028C18_PA_CL_GB_HORZ_DISC_ADJ */
2913
2914 r600_store_context_reg_seq(cb, R_028240_PA_SC_GENERIC_SCISSOR_TL, 2);
2915 r600_store_value(cb, 0); /* R_028240_PA_SC_GENERIC_SCISSOR_TL */
2916 r600_store_value(cb, S_028244_BR_X(16384) | S_028244_BR_Y(16384)); /* R_028244_PA_SC_GENERIC_SCISSOR_BR */
2917
2918 r600_store_context_reg_seq(cb, R_028030_PA_SC_SCREEN_SCISSOR_TL, 2);
2919 r600_store_value(cb, 0); /* R_028030_PA_SC_SCREEN_SCISSOR_TL */
2920 r600_store_value(cb, S_028034_BR_X(16384) | S_028034_BR_Y(16384)); /* R_028034_PA_SC_SCREEN_SCISSOR_BR */
2921
2922 r600_store_context_reg(cb, R_028848_SQ_PGM_RESOURCES_2_PS, S_028848_SINGLE_ROUND(V_SQ_ROUND_NEAREST_EVEN));
2923 r600_store_context_reg(cb, R_028864_SQ_PGM_RESOURCES_2_VS, S_028864_SINGLE_ROUND(V_SQ_ROUND_NEAREST_EVEN));
2924 r600_store_context_reg(cb, R_02887C_SQ_PGM_RESOURCES_2_GS, S_028848_SINGLE_ROUND(V_SQ_ROUND_NEAREST_EVEN));
2925 r600_store_context_reg(cb, R_028894_SQ_PGM_RESOURCES_2_ES, S_028848_SINGLE_ROUND(V_SQ_ROUND_NEAREST_EVEN));
2926 r600_store_context_reg(cb, R_0288A8_SQ_PGM_RESOURCES_FS, 0);
2927 r600_store_context_reg(cb, R_0288C0_SQ_PGM_RESOURCES_2_HS, S_028848_SINGLE_ROUND(V_SQ_ROUND_NEAREST_EVEN));
2928 r600_store_context_reg(cb, R_0288D8_SQ_PGM_RESOURCES_2_LS, S_028848_SINGLE_ROUND(V_SQ_ROUND_NEAREST_EVEN));
2929
2930 /* to avoid GPU doing any preloading of constant from random address */
2931 r600_store_context_reg_seq(cb, R_028140_ALU_CONST_BUFFER_SIZE_PS_0, 16);
2932 for (i = 0; i < 16; i++)
2933 r600_store_value(cb, 0);
2934
2935 r600_store_context_reg_seq(cb, R_028180_ALU_CONST_BUFFER_SIZE_VS_0, 16);
2936 for (i = 0; i < 16; i++)
2937 r600_store_value(cb, 0);
2938
2939 r600_store_context_reg_seq(cb, R_0281C0_ALU_CONST_BUFFER_SIZE_GS_0, 16);
2940 for (i = 0; i < 16; i++)
2941 r600_store_value(cb, 0);
2942
2943 r600_store_context_reg_seq(cb, R_028FC0_ALU_CONST_BUFFER_SIZE_LS_0, 16);
2944 for (i = 0; i < 16; i++)
2945 r600_store_value(cb, 0);
2946
2947 r600_store_context_reg_seq(cb, R_028F80_ALU_CONST_BUFFER_SIZE_HS_0, 16);
2948 for (i = 0; i < 16; i++)
2949 r600_store_value(cb, 0);
2950
2951 r600_store_context_reg(cb, R_028B98_VGT_STRMOUT_BUFFER_CONFIG, 0);
2952
2953 if (rctx->screen->b.has_streamout) {
2954 r600_store_context_reg(cb, R_028B28_VGT_STRMOUT_DRAW_OPAQUE_OFFSET, 0);
2955 }
2956
2957 r600_store_context_reg(cb, R_028010_DB_RENDER_OVERRIDE2, 0);
2958 r600_store_context_reg(cb, R_028234_PA_SU_HARDWARE_SCREEN_OFFSET, 0);
2959 r600_store_context_reg(cb, R_0286C8_SPI_THREAD_GROUPING, 0);
2960 r600_store_context_reg_seq(cb, R_0286E4_SPI_PS_IN_CONTROL_2, 2);
2961 r600_store_value(cb, 0); /* R_0286E4_SPI_PS_IN_CONTROL_2 */
2962 r600_store_value(cb, 0); /* R_0286E8_SPI_COMPUTE_INPUT_CNTL */
2963
2964 r600_store_context_reg_seq(cb, R_0288E8_SQ_LDS_ALLOC, 2);
2965 r600_store_value(cb, 0); /* R_0288E8_SQ_LDS_ALLOC */
2966 r600_store_value(cb, 0); /* R_0288EC_SQ_LDS_ALLOC_PS */
2967
2968 if (rctx->b.family == CHIP_CAICOS) {
2969 r600_store_context_reg_seq(cb, R_028B54_VGT_SHADER_STAGES_EN, 2);
2970 r600_store_value(cb, 0); /* R028B54_VGT_SHADER_STAGES_EN */
2971 r600_store_value(cb, 0); /* R028B58_VGT_LS_HS_CONFIG */
2972 r600_store_context_reg(cb, R_028B6C_VGT_TF_PARAM, 0);
2973 } else {
2974 r600_store_context_reg_seq(cb, R_028B54_VGT_SHADER_STAGES_EN, 7);
2975 r600_store_value(cb, 0); /* R028B54_VGT_SHADER_STAGES_EN */
2976 r600_store_value(cb, 0); /* R028B58_VGT_LS_HS_CONFIG */
2977 r600_store_value(cb, 0); /* R028B5C_VGT_LS_SIZE */
2978 r600_store_value(cb, 0); /* R028B60_VGT_HS_SIZE */
2979 r600_store_value(cb, 0); /* R028B64_VGT_LS_HS_ALLOC */
2980 r600_store_value(cb, 0); /* R028B68_VGT_HS_PATCH_CONST */
2981 r600_store_value(cb, 0); /* R028B68_VGT_TF_PARAM */
2982 }
2983
2984 eg_store_loop_const(cb, R_03A200_SQ_LOOP_CONST_0, 0x01000FFF);
2985 eg_store_loop_const(cb, R_03A200_SQ_LOOP_CONST_0 + (32 * 4), 0x01000FFF);
2986 eg_store_loop_const(cb, R_03A200_SQ_LOOP_CONST_0 + (64 * 4), 0x01000FFF);
2987 eg_store_loop_const(cb, R_03A200_SQ_LOOP_CONST_0 + (96 * 4), 0x01000FFF);
2988 eg_store_loop_const(cb, R_03A200_SQ_LOOP_CONST_0 + (128 * 4), 0x01000FFF);
2989 }
2990
2991 void evergreen_update_ps_state(struct pipe_context *ctx, struct r600_pipe_shader *shader)
2992 {
2993 struct r600_context *rctx = (struct r600_context *)ctx;
2994 struct r600_command_buffer *cb = &shader->command_buffer;
2995 struct r600_shader *rshader = &shader->shader;
2996 unsigned i, exports_ps, num_cout, spi_ps_in_control_0, spi_input_z, spi_ps_in_control_1, db_shader_control = 0;
2997 int pos_index = -1, face_index = -1, fixed_pt_position_index = -1;
2998 int ninterp = 0;
2999 boolean have_perspective = FALSE, have_linear = FALSE;
3000 static const unsigned spi_baryc_enable_bit[6] = {
3001 S_0286E0_PERSP_SAMPLE_ENA(1),
3002 S_0286E0_PERSP_CENTER_ENA(1),
3003 S_0286E0_PERSP_CENTROID_ENA(1),
3004 S_0286E0_LINEAR_SAMPLE_ENA(1),
3005 S_0286E0_LINEAR_CENTER_ENA(1),
3006 S_0286E0_LINEAR_CENTROID_ENA(1)
3007 };
3008 unsigned spi_baryc_cntl = 0, sid, tmp, num = 0;
3009 unsigned z_export = 0, stencil_export = 0, mask_export = 0;
3010 unsigned sprite_coord_enable = rctx->rasterizer ? rctx->rasterizer->sprite_coord_enable : 0;
3011 uint32_t spi_ps_input_cntl[32];
3012
3013 if (!cb->buf) {
3014 r600_init_command_buffer(cb, 64);
3015 } else {
3016 cb->num_dw = 0;
3017 }
3018
3019 for (i = 0; i < rshader->ninput; i++) {
3020 /* evergreen NUM_INTERP only contains values interpolated into the LDS,
3021 POSITION goes via GPRs from the SC so isn't counted */
3022 if (rshader->input[i].name == TGSI_SEMANTIC_POSITION)
3023 pos_index = i;
3024 else if (rshader->input[i].name == TGSI_SEMANTIC_FACE) {
3025 if (face_index == -1)
3026 face_index = i;
3027 }
3028 else if (rshader->input[i].name == TGSI_SEMANTIC_SAMPLEMASK) {
3029 if (face_index == -1)
3030 face_index = i; /* lives in same register, same enable bit */
3031 }
3032 else if (rshader->input[i].name == TGSI_SEMANTIC_SAMPLEID) {
3033 fixed_pt_position_index = i;
3034 }
3035 else {
3036 ninterp++;
3037 int k = eg_get_interpolator_index(
3038 rshader->input[i].interpolate,
3039 rshader->input[i].interpolate_location);
3040 if (k >= 0) {
3041 spi_baryc_cntl |= spi_baryc_enable_bit[k];
3042 have_perspective |= k < 3;
3043 have_linear |= !(k < 3);
3044 }
3045 }
3046
3047 sid = rshader->input[i].spi_sid;
3048
3049 if (sid) {
3050 tmp = S_028644_SEMANTIC(sid);
3051
3052 if (rshader->input[i].name == TGSI_SEMANTIC_POSITION ||
3053 rshader->input[i].interpolate == TGSI_INTERPOLATE_CONSTANT ||
3054 (rshader->input[i].interpolate == TGSI_INTERPOLATE_COLOR &&
3055 rctx->rasterizer && rctx->rasterizer->flatshade)) {
3056 tmp |= S_028644_FLAT_SHADE(1);
3057 }
3058
3059 if (rshader->input[i].name == TGSI_SEMANTIC_GENERIC &&
3060 (sprite_coord_enable & (1 << rshader->input[i].sid))) {
3061 tmp |= S_028644_PT_SPRITE_TEX(1);
3062 }
3063
3064 spi_ps_input_cntl[num++] = tmp;
3065 }
3066 }
3067
3068 r600_store_context_reg_seq(cb, R_028644_SPI_PS_INPUT_CNTL_0, num);
3069 r600_store_array(cb, num, spi_ps_input_cntl);
3070
3071 for (i = 0; i < rshader->noutput; i++) {
3072 if (rshader->output[i].name == TGSI_SEMANTIC_POSITION)
3073 z_export = 1;
3074 if (rshader->output[i].name == TGSI_SEMANTIC_STENCIL)
3075 stencil_export = 1;
3076 if (rshader->output[i].name == TGSI_SEMANTIC_SAMPLEMASK &&
3077 rctx->framebuffer.nr_samples > 1 && rctx->ps_iter_samples > 0)
3078 mask_export = 1;
3079 }
3080 if (rshader->uses_kill)
3081 db_shader_control |= S_02880C_KILL_ENABLE(1);
3082
3083 db_shader_control |= S_02880C_Z_EXPORT_ENABLE(z_export);
3084 db_shader_control |= S_02880C_STENCIL_EXPORT_ENABLE(stencil_export);
3085 db_shader_control |= S_02880C_MASK_EXPORT_ENABLE(mask_export);
3086
3087 switch (rshader->ps_conservative_z) {
3088 default: /* fall through */
3089 case TGSI_FS_DEPTH_LAYOUT_ANY:
3090 db_shader_control |= S_02880C_CONSERVATIVE_Z_EXPORT(V_02880C_EXPORT_ANY_Z);
3091 break;
3092 case TGSI_FS_DEPTH_LAYOUT_GREATER:
3093 db_shader_control |= S_02880C_CONSERVATIVE_Z_EXPORT(V_02880C_EXPORT_GREATER_THAN_Z);
3094 break;
3095 case TGSI_FS_DEPTH_LAYOUT_LESS:
3096 db_shader_control |= S_02880C_CONSERVATIVE_Z_EXPORT(V_02880C_EXPORT_LESS_THAN_Z);
3097 break;
3098 }
3099
3100 exports_ps = 0;
3101 for (i = 0; i < rshader->noutput; i++) {
3102 if (rshader->output[i].name == TGSI_SEMANTIC_POSITION ||
3103 rshader->output[i].name == TGSI_SEMANTIC_STENCIL ||
3104 rshader->output[i].name == TGSI_SEMANTIC_SAMPLEMASK)
3105 exports_ps |= 1;
3106 }
3107
3108 num_cout = rshader->nr_ps_color_exports;
3109
3110 exports_ps |= S_02884C_EXPORT_COLORS(num_cout);
3111 if (!exports_ps) {
3112 /* always at least export 1 component per pixel */
3113 exports_ps = 2;
3114 }
3115 shader->nr_ps_color_outputs = num_cout;
3116 if (ninterp == 0) {
3117 ninterp = 1;
3118 have_perspective = TRUE;
3119 }
3120 if (!spi_baryc_cntl)
3121 spi_baryc_cntl |= spi_baryc_enable_bit[0];
3122
3123 if (!have_perspective && !have_linear)
3124 have_perspective = TRUE;
3125
3126 spi_ps_in_control_0 = S_0286CC_NUM_INTERP(ninterp) |
3127 S_0286CC_PERSP_GRADIENT_ENA(have_perspective) |
3128 S_0286CC_LINEAR_GRADIENT_ENA(have_linear);
3129 spi_input_z = 0;
3130 if (pos_index != -1) {
3131 spi_ps_in_control_0 |= S_0286CC_POSITION_ENA(1) |
3132 S_0286CC_POSITION_CENTROID(rshader->input[pos_index].interpolate_location == TGSI_INTERPOLATE_LOC_CENTROID) |
3133 S_0286CC_POSITION_ADDR(rshader->input[pos_index].gpr);
3134 spi_input_z |= S_0286D8_PROVIDE_Z_TO_SPI(1);
3135 }
3136
3137 spi_ps_in_control_1 = 0;
3138 if (face_index != -1) {
3139 spi_ps_in_control_1 |= S_0286D0_FRONT_FACE_ENA(1) |
3140 S_0286D0_FRONT_FACE_ADDR(rshader->input[face_index].gpr);
3141 }
3142 if (fixed_pt_position_index != -1) {
3143 spi_ps_in_control_1 |= S_0286D0_FIXED_PT_POSITION_ENA(1) |
3144 S_0286D0_FIXED_PT_POSITION_ADDR(rshader->input[fixed_pt_position_index].gpr);
3145 }
3146
3147 r600_store_context_reg_seq(cb, R_0286CC_SPI_PS_IN_CONTROL_0, 2);
3148 r600_store_value(cb, spi_ps_in_control_0); /* R_0286CC_SPI_PS_IN_CONTROL_0 */
3149 r600_store_value(cb, spi_ps_in_control_1); /* R_0286D0_SPI_PS_IN_CONTROL_1 */
3150
3151 r600_store_context_reg(cb, R_0286E0_SPI_BARYC_CNTL, spi_baryc_cntl);
3152 r600_store_context_reg(cb, R_0286D8_SPI_INPUT_Z, spi_input_z);
3153 r600_store_context_reg(cb, R_02884C_SQ_PGM_EXPORTS_PS, exports_ps);
3154
3155 r600_store_context_reg_seq(cb, R_028840_SQ_PGM_START_PS, 2);
3156 r600_store_value(cb, shader->bo->gpu_address >> 8);
3157 r600_store_value(cb, /* R_028844_SQ_PGM_RESOURCES_PS */
3158 S_028844_NUM_GPRS(rshader->bc.ngpr) |
3159 S_028844_PRIME_CACHE_ON_DRAW(1) |
3160 S_028844_STACK_SIZE(rshader->bc.nstack));
3161 /* After that, the NOP relocation packet must be emitted (shader->bo, RADEON_USAGE_READ). */
3162
3163 shader->db_shader_control = db_shader_control;
3164 shader->ps_depth_export = z_export | stencil_export | mask_export;
3165
3166 shader->sprite_coord_enable = sprite_coord_enable;
3167 if (rctx->rasterizer)
3168 shader->flatshade = rctx->rasterizer->flatshade;
3169 }
3170
3171 void evergreen_update_es_state(struct pipe_context *ctx, struct r600_pipe_shader *shader)
3172 {
3173 struct r600_command_buffer *cb = &shader->command_buffer;
3174 struct r600_shader *rshader = &shader->shader;
3175
3176 r600_init_command_buffer(cb, 32);
3177
3178 r600_store_context_reg(cb, R_028890_SQ_PGM_RESOURCES_ES,
3179 S_028890_NUM_GPRS(rshader->bc.ngpr) |
3180 S_028890_STACK_SIZE(rshader->bc.nstack));
3181 r600_store_context_reg(cb, R_02888C_SQ_PGM_START_ES,
3182 shader->bo->gpu_address >> 8);
3183 /* After that, the NOP relocation packet must be emitted (shader->bo, RADEON_USAGE_READ). */
3184 }
3185
3186 void evergreen_update_gs_state(struct pipe_context *ctx, struct r600_pipe_shader *shader)
3187 {
3188 struct r600_context *rctx = (struct r600_context *)ctx;
3189 struct r600_command_buffer *cb = &shader->command_buffer;
3190 struct r600_shader *rshader = &shader->shader;
3191 struct r600_shader *cp_shader = &shader->gs_copy_shader->shader;
3192 unsigned gsvs_itemsizes[4] = {
3193 (cp_shader->ring_item_sizes[0] * shader->selector->gs_max_out_vertices) >> 2,
3194 (cp_shader->ring_item_sizes[1] * shader->selector->gs_max_out_vertices) >> 2,
3195 (cp_shader->ring_item_sizes[2] * shader->selector->gs_max_out_vertices) >> 2,
3196 (cp_shader->ring_item_sizes[3] * shader->selector->gs_max_out_vertices) >> 2
3197 };
3198
3199 r600_init_command_buffer(cb, 64);
3200
3201 /* VGT_GS_MODE is written by evergreen_emit_shader_stages */
3202
3203
3204 r600_store_context_reg(cb, R_028B38_VGT_GS_MAX_VERT_OUT,
3205 S_028B38_MAX_VERT_OUT(shader->selector->gs_max_out_vertices));
3206 r600_store_context_reg(cb, R_028A6C_VGT_GS_OUT_PRIM_TYPE,
3207 r600_conv_prim_to_gs_out(shader->selector->gs_output_prim));
3208
3209 if (rctx->screen->b.info.drm_minor >= 35) {
3210 r600_store_context_reg(cb, R_028B90_VGT_GS_INSTANCE_CNT,
3211 S_028B90_CNT(MIN2(shader->selector->gs_num_invocations, 127)) |
3212 S_028B90_ENABLE(shader->selector->gs_num_invocations > 0));
3213 }
3214 r600_store_context_reg_seq(cb, R_02891C_SQ_GS_VERT_ITEMSIZE, 4);
3215 r600_store_value(cb, cp_shader->ring_item_sizes[0] >> 2);
3216 r600_store_value(cb, cp_shader->ring_item_sizes[1] >> 2);
3217 r600_store_value(cb, cp_shader->ring_item_sizes[2] >> 2);
3218 r600_store_value(cb, cp_shader->ring_item_sizes[3] >> 2);
3219
3220 r600_store_context_reg(cb, R_028900_SQ_ESGS_RING_ITEMSIZE,
3221 (rshader->ring_item_sizes[0]) >> 2);
3222
3223 r600_store_context_reg(cb, R_028904_SQ_GSVS_RING_ITEMSIZE,
3224 gsvs_itemsizes[0] +
3225 gsvs_itemsizes[1] +
3226 gsvs_itemsizes[2] +
3227 gsvs_itemsizes[3]);
3228
3229 r600_store_context_reg_seq(cb, R_02892C_SQ_GSVS_RING_OFFSET_1, 3);
3230 r600_store_value(cb, gsvs_itemsizes[0]);
3231 r600_store_value(cb, gsvs_itemsizes[0] + gsvs_itemsizes[1]);
3232 r600_store_value(cb, gsvs_itemsizes[0] + gsvs_itemsizes[1] + gsvs_itemsizes[2]);
3233
3234 /* FIXME calculate these values somehow ??? */
3235 r600_store_context_reg_seq(cb, R_028A54_GS_PER_ES, 3);
3236 r600_store_value(cb, 0x80); /* GS_PER_ES */
3237 r600_store_value(cb, 0x100); /* ES_PER_GS */
3238 r600_store_value(cb, 0x2); /* GS_PER_VS */
3239
3240 r600_store_context_reg(cb, R_028878_SQ_PGM_RESOURCES_GS,
3241 S_028878_NUM_GPRS(rshader->bc.ngpr) |
3242 S_028878_STACK_SIZE(rshader->bc.nstack));
3243 r600_store_context_reg(cb, R_028874_SQ_PGM_START_GS,
3244 shader->bo->gpu_address >> 8);
3245 /* After that, the NOP relocation packet must be emitted (shader->bo, RADEON_USAGE_READ). */
3246 }
3247
3248
3249 void evergreen_update_vs_state(struct pipe_context *ctx, struct r600_pipe_shader *shader)
3250 {
3251 struct r600_command_buffer *cb = &shader->command_buffer;
3252 struct r600_shader *rshader = &shader->shader;
3253 unsigned spi_vs_out_id[10] = {};
3254 unsigned i, tmp, nparams = 0;
3255
3256 for (i = 0; i < rshader->noutput; i++) {
3257 if (rshader->output[i].spi_sid) {
3258 tmp = rshader->output[i].spi_sid << ((nparams & 3) * 8);
3259 spi_vs_out_id[nparams / 4] |= tmp;
3260 nparams++;
3261 }
3262 }
3263
3264 r600_init_command_buffer(cb, 32);
3265
3266 r600_store_context_reg_seq(cb, R_02861C_SPI_VS_OUT_ID_0, 10);
3267 for (i = 0; i < 10; i++) {
3268 r600_store_value(cb, spi_vs_out_id[i]);
3269 }
3270
3271 /* Certain attributes (position, psize, etc.) don't count as params.
3272 * VS is required to export at least one param and r600_shader_from_tgsi()
3273 * takes care of adding a dummy export.
3274 */
3275 if (nparams < 1)
3276 nparams = 1;
3277
3278 r600_store_context_reg(cb, R_0286C4_SPI_VS_OUT_CONFIG,
3279 S_0286C4_VS_EXPORT_COUNT(nparams - 1));
3280 r600_store_context_reg(cb, R_028860_SQ_PGM_RESOURCES_VS,
3281 S_028860_NUM_GPRS(rshader->bc.ngpr) |
3282 S_028860_STACK_SIZE(rshader->bc.nstack));
3283 if (rshader->vs_position_window_space) {
3284 r600_store_context_reg(cb, R_028818_PA_CL_VTE_CNTL,
3285 S_028818_VTX_XY_FMT(1) | S_028818_VTX_Z_FMT(1));
3286 } else {
3287 r600_store_context_reg(cb, R_028818_PA_CL_VTE_CNTL,
3288 S_028818_VTX_W0_FMT(1) |
3289 S_028818_VPORT_X_SCALE_ENA(1) | S_028818_VPORT_X_OFFSET_ENA(1) |
3290 S_028818_VPORT_Y_SCALE_ENA(1) | S_028818_VPORT_Y_OFFSET_ENA(1) |
3291 S_028818_VPORT_Z_SCALE_ENA(1) | S_028818_VPORT_Z_OFFSET_ENA(1));
3292
3293 }
3294 r600_store_context_reg(cb, R_02885C_SQ_PGM_START_VS,
3295 shader->bo->gpu_address >> 8);
3296 /* After that, the NOP relocation packet must be emitted (shader->bo, RADEON_USAGE_READ). */
3297
3298 shader->pa_cl_vs_out_cntl =
3299 S_02881C_VS_OUT_CCDIST0_VEC_ENA((rshader->clip_dist_write & 0x0F) != 0) |
3300 S_02881C_VS_OUT_CCDIST1_VEC_ENA((rshader->clip_dist_write & 0xF0) != 0) |
3301 S_02881C_VS_OUT_MISC_VEC_ENA(rshader->vs_out_misc_write) |
3302 S_02881C_USE_VTX_POINT_SIZE(rshader->vs_out_point_size) |
3303 S_02881C_USE_VTX_EDGE_FLAG(rshader->vs_out_edgeflag) |
3304 S_02881C_USE_VTX_VIEWPORT_INDX(rshader->vs_out_viewport) |
3305 S_02881C_USE_VTX_RENDER_TARGET_INDX(rshader->vs_out_layer);
3306 }
3307
3308 void evergreen_update_hs_state(struct pipe_context *ctx, struct r600_pipe_shader *shader)
3309 {
3310 struct r600_command_buffer *cb = &shader->command_buffer;
3311 struct r600_shader *rshader = &shader->shader;
3312
3313 r600_init_command_buffer(cb, 32);
3314 r600_store_context_reg(cb, R_0288BC_SQ_PGM_RESOURCES_HS,
3315 S_0288BC_NUM_GPRS(rshader->bc.ngpr) |
3316 S_0288BC_STACK_SIZE(rshader->bc.nstack));
3317 r600_store_context_reg(cb, R_0288B8_SQ_PGM_START_HS,
3318 shader->bo->gpu_address >> 8);
3319 }
3320
3321 void evergreen_update_ls_state(struct pipe_context *ctx, struct r600_pipe_shader *shader)
3322 {
3323 struct r600_command_buffer *cb = &shader->command_buffer;
3324 struct r600_shader *rshader = &shader->shader;
3325
3326 r600_init_command_buffer(cb, 32);
3327 r600_store_context_reg(cb, R_0288D4_SQ_PGM_RESOURCES_LS,
3328 S_0288D4_NUM_GPRS(rshader->bc.ngpr) |
3329 S_0288D4_STACK_SIZE(rshader->bc.nstack));
3330 r600_store_context_reg(cb, R_0288D0_SQ_PGM_START_LS,
3331 shader->bo->gpu_address >> 8);
3332 }
3333 void *evergreen_create_resolve_blend(struct r600_context *rctx)
3334 {
3335 struct pipe_blend_state blend;
3336
3337 memset(&blend, 0, sizeof(blend));
3338 blend.independent_blend_enable = true;
3339 blend.rt[0].colormask = 0xf;
3340 return evergreen_create_blend_state_mode(&rctx->b.b, &blend, V_028808_CB_RESOLVE);
3341 }
3342
3343 void *evergreen_create_decompress_blend(struct r600_context *rctx)
3344 {
3345 struct pipe_blend_state blend;
3346 unsigned mode = rctx->screen->has_compressed_msaa_texturing ?
3347 V_028808_CB_FMASK_DECOMPRESS : V_028808_CB_DECOMPRESS;
3348
3349 memset(&blend, 0, sizeof(blend));
3350 blend.independent_blend_enable = true;
3351 blend.rt[0].colormask = 0xf;
3352 return evergreen_create_blend_state_mode(&rctx->b.b, &blend, mode);
3353 }
3354
3355 void *evergreen_create_fastclear_blend(struct r600_context *rctx)
3356 {
3357 struct pipe_blend_state blend;
3358 unsigned mode = V_028808_CB_ELIMINATE_FAST_CLEAR;
3359
3360 memset(&blend, 0, sizeof(blend));
3361 blend.independent_blend_enable = true;
3362 blend.rt[0].colormask = 0xf;
3363 return evergreen_create_blend_state_mode(&rctx->b.b, &blend, mode);
3364 }
3365
3366 void *evergreen_create_db_flush_dsa(struct r600_context *rctx)
3367 {
3368 struct pipe_depth_stencil_alpha_state dsa = {{0}};
3369
3370 return rctx->b.b.create_depth_stencil_alpha_state(&rctx->b.b, &dsa);
3371 }
3372
3373 void evergreen_update_db_shader_control(struct r600_context * rctx)
3374 {
3375 bool dual_export;
3376 unsigned db_shader_control;
3377
3378 if (!rctx->ps_shader) {
3379 return;
3380 }
3381
3382 dual_export = rctx->framebuffer.export_16bpc &&
3383 !rctx->ps_shader->current->ps_depth_export;
3384
3385 db_shader_control = rctx->ps_shader->current->db_shader_control |
3386 S_02880C_DUAL_EXPORT_ENABLE(dual_export) |
3387 S_02880C_DB_SOURCE_FORMAT(dual_export ? V_02880C_EXPORT_DB_TWO :
3388 V_02880C_EXPORT_DB_FULL) |
3389 S_02880C_ALPHA_TO_MASK_DISABLE(rctx->framebuffer.cb0_is_integer);
3390
3391 /* When alpha test is enabled we can't trust the hw to make the proper
3392 * decision on the order in which ztest should be run related to fragment
3393 * shader execution.
3394 *
3395 * If alpha test is enabled perform early z rejection (RE_Z) but don't early
3396 * write to the zbuffer. Write to zbuffer is delayed after fragment shader
3397 * execution and thus after alpha test so if discarded by the alpha test
3398 * the z value is not written.
3399 * If ReZ is enabled, and the zfunc/zenable/zwrite values change you can
3400 * get a hang unless you flush the DB in between. For now just use
3401 * LATE_Z.
3402 */
3403 if (rctx->alphatest_state.sx_alpha_test_control) {
3404 db_shader_control |= S_02880C_Z_ORDER(V_02880C_LATE_Z);
3405 } else {
3406 db_shader_control |= S_02880C_Z_ORDER(V_02880C_EARLY_Z_THEN_LATE_Z);
3407 }
3408
3409 if (db_shader_control != rctx->db_misc_state.db_shader_control) {
3410 rctx->db_misc_state.db_shader_control = db_shader_control;
3411 r600_mark_atom_dirty(rctx, &rctx->db_misc_state.atom);
3412 }
3413 }
3414
3415 static void evergreen_dma_copy_tile(struct r600_context *rctx,
3416 struct pipe_resource *dst,
3417 unsigned dst_level,
3418 unsigned dst_x,
3419 unsigned dst_y,
3420 unsigned dst_z,
3421 struct pipe_resource *src,
3422 unsigned src_level,
3423 unsigned src_x,
3424 unsigned src_y,
3425 unsigned src_z,
3426 unsigned copy_height,
3427 unsigned pitch,
3428 unsigned bpp)
3429 {
3430 struct radeon_winsys_cs *cs = rctx->b.dma.cs;
3431 struct r600_texture *rsrc = (struct r600_texture*)src;
3432 struct r600_texture *rdst = (struct r600_texture*)dst;
3433 unsigned array_mode, lbpp, pitch_tile_max, slice_tile_max, size;
3434 unsigned ncopy, height, cheight, detile, i, x, y, z, src_mode, dst_mode;
3435 unsigned sub_cmd, bank_h, bank_w, mt_aspect, nbanks, tile_split, non_disp_tiling = 0;
3436 uint64_t base, addr;
3437
3438 dst_mode = rdst->surface.level[dst_level].mode;
3439 src_mode = rsrc->surface.level[src_level].mode;
3440 /* downcast linear aligned to linear to simplify test */
3441 src_mode = src_mode == RADEON_SURF_MODE_LINEAR_ALIGNED ? RADEON_SURF_MODE_LINEAR : src_mode;
3442 dst_mode = dst_mode == RADEON_SURF_MODE_LINEAR_ALIGNED ? RADEON_SURF_MODE_LINEAR : dst_mode;
3443 assert(dst_mode != src_mode);
3444
3445 /* non_disp_tiling bit needs to be set for depth, stencil, and fmask surfaces */
3446 if (util_format_has_depth(util_format_description(src->format)))
3447 non_disp_tiling = 1;
3448
3449 y = 0;
3450 sub_cmd = EG_DMA_COPY_TILED;
3451 lbpp = util_logbase2(bpp);
3452 pitch_tile_max = ((pitch / bpp) / 8) - 1;
3453 nbanks = eg_num_banks(rctx->screen->b.info.r600_num_banks);
3454
3455 if (dst_mode == RADEON_SURF_MODE_LINEAR) {
3456 /* T2L */
3457 array_mode = evergreen_array_mode(src_mode);
3458 slice_tile_max = (rsrc->surface.level[src_level].nblk_x * rsrc->surface.level[src_level].nblk_y) / (8*8);
3459 slice_tile_max = slice_tile_max ? slice_tile_max - 1 : 0;
3460 /* linear height must be the same as the slice tile max height, it's ok even
3461 * if the linear destination/source have smaller heigh as the size of the
3462 * dma packet will be using the copy_height which is always smaller or equal
3463 * to the linear height
3464 */
3465 height = rsrc->surface.level[src_level].npix_y;
3466 detile = 1;
3467 x = src_x;
3468 y = src_y;
3469 z = src_z;
3470 base = rsrc->surface.level[src_level].offset;
3471 addr = rdst->surface.level[dst_level].offset;
3472 addr += rdst->surface.level[dst_level].slice_size * dst_z;
3473 addr += dst_y * pitch + dst_x * bpp;
3474 bank_h = eg_bank_wh(rsrc->surface.bankh);
3475 bank_w = eg_bank_wh(rsrc->surface.bankw);
3476 mt_aspect = eg_macro_tile_aspect(rsrc->surface.mtilea);
3477 tile_split = eg_tile_split(rsrc->surface.tile_split);
3478 base += rsrc->resource.gpu_address;
3479 addr += rdst->resource.gpu_address;
3480 } else {
3481 /* L2T */
3482 array_mode = evergreen_array_mode(dst_mode);
3483 slice_tile_max = (rdst->surface.level[dst_level].nblk_x * rdst->surface.level[dst_level].nblk_y) / (8*8);
3484 slice_tile_max = slice_tile_max ? slice_tile_max - 1 : 0;
3485 /* linear height must be the same as the slice tile max height, it's ok even
3486 * if the linear destination/source have smaller heigh as the size of the
3487 * dma packet will be using the copy_height which is always smaller or equal
3488 * to the linear height
3489 */
3490 height = rdst->surface.level[dst_level].npix_y;
3491 detile = 0;
3492 x = dst_x;
3493 y = dst_y;
3494 z = dst_z;
3495 base = rdst->surface.level[dst_level].offset;
3496 addr = rsrc->surface.level[src_level].offset;
3497 addr += rsrc->surface.level[src_level].slice_size * src_z;
3498 addr += src_y * pitch + src_x * bpp;
3499 bank_h = eg_bank_wh(rdst->surface.bankh);
3500 bank_w = eg_bank_wh(rdst->surface.bankw);
3501 mt_aspect = eg_macro_tile_aspect(rdst->surface.mtilea);
3502 tile_split = eg_tile_split(rdst->surface.tile_split);
3503 base += rdst->resource.gpu_address;
3504 addr += rsrc->resource.gpu_address;
3505 }
3506
3507 size = (copy_height * pitch) / 4;
3508 ncopy = (size / EG_DMA_COPY_MAX_SIZE) + !!(size % EG_DMA_COPY_MAX_SIZE);
3509 r600_need_dma_space(&rctx->b, ncopy * 9);
3510
3511 for (i = 0; i < ncopy; i++) {
3512 cheight = copy_height;
3513 if (((cheight * pitch) / 4) > EG_DMA_COPY_MAX_SIZE) {
3514 cheight = (EG_DMA_COPY_MAX_SIZE * 4) / pitch;
3515 }
3516 size = (cheight * pitch) / 4;
3517 /* emit reloc before writing cs so that cs is always in consistent state */
3518 radeon_add_to_buffer_list(&rctx->b, &rctx->b.dma, &rsrc->resource,
3519 RADEON_USAGE_READ, RADEON_PRIO_SDMA_TEXTURE);
3520 radeon_add_to_buffer_list(&rctx->b, &rctx->b.dma, &rdst->resource,
3521 RADEON_USAGE_WRITE, RADEON_PRIO_SDMA_TEXTURE);
3522 cs->buf[cs->cdw++] = DMA_PACKET(DMA_PACKET_COPY, sub_cmd, size);
3523 cs->buf[cs->cdw++] = base >> 8;
3524 cs->buf[cs->cdw++] = (detile << 31) | (array_mode << 27) |
3525 (lbpp << 24) | (bank_h << 21) |
3526 (bank_w << 18) | (mt_aspect << 16);
3527 cs->buf[cs->cdw++] = (pitch_tile_max << 0) | ((height - 1) << 16);
3528 cs->buf[cs->cdw++] = (slice_tile_max << 0);
3529 cs->buf[cs->cdw++] = (x << 0) | (z << 18);
3530 cs->buf[cs->cdw++] = (y << 0) | (tile_split << 21) | (nbanks << 25) | (non_disp_tiling << 28);
3531 cs->buf[cs->cdw++] = addr & 0xfffffffc;
3532 cs->buf[cs->cdw++] = (addr >> 32UL) & 0xff;
3533 copy_height -= cheight;
3534 addr += cheight * pitch;
3535 y += cheight;
3536 }
3537 }
3538
3539 static void evergreen_dma_copy(struct pipe_context *ctx,
3540 struct pipe_resource *dst,
3541 unsigned dst_level,
3542 unsigned dstx, unsigned dsty, unsigned dstz,
3543 struct pipe_resource *src,
3544 unsigned src_level,
3545 const struct pipe_box *src_box)
3546 {
3547 struct r600_context *rctx = (struct r600_context *)ctx;
3548 struct r600_texture *rsrc = (struct r600_texture*)src;
3549 struct r600_texture *rdst = (struct r600_texture*)dst;
3550 unsigned dst_pitch, src_pitch, bpp, dst_mode, src_mode, copy_height;
3551 unsigned src_w, dst_w;
3552 unsigned src_x, src_y;
3553 unsigned dst_x = dstx, dst_y = dsty, dst_z = dstz;
3554
3555 if (rctx->b.dma.cs == NULL) {
3556 goto fallback;
3557 }
3558
3559 if (dst->target == PIPE_BUFFER && src->target == PIPE_BUFFER) {
3560 evergreen_dma_copy_buffer(rctx, dst, src, dst_x, src_box->x, src_box->width);
3561 return;
3562 }
3563
3564 if (src->format != dst->format || src_box->depth > 1 ||
3565 (rdst->dirty_level_mask | rdst->stencil_dirty_level_mask) & (1 << dst_level)) {
3566 goto fallback;
3567 }
3568
3569 if (rsrc->dirty_level_mask & (1 << src_level)) {
3570 ctx->flush_resource(ctx, src);
3571 }
3572
3573 src_x = util_format_get_nblocksx(src->format, src_box->x);
3574 dst_x = util_format_get_nblocksx(src->format, dst_x);
3575 src_y = util_format_get_nblocksy(src->format, src_box->y);
3576 dst_y = util_format_get_nblocksy(src->format, dst_y);
3577
3578 bpp = rdst->surface.bpe;
3579 dst_pitch = rdst->surface.level[dst_level].pitch_bytes;
3580 src_pitch = rsrc->surface.level[src_level].pitch_bytes;
3581 src_w = rsrc->surface.level[src_level].npix_x;
3582 dst_w = rdst->surface.level[dst_level].npix_x;
3583 copy_height = src_box->height / rsrc->surface.blk_h;
3584
3585 dst_mode = rdst->surface.level[dst_level].mode;
3586 src_mode = rsrc->surface.level[src_level].mode;
3587 /* downcast linear aligned to linear to simplify test */
3588 src_mode = src_mode == RADEON_SURF_MODE_LINEAR_ALIGNED ? RADEON_SURF_MODE_LINEAR : src_mode;
3589 dst_mode = dst_mode == RADEON_SURF_MODE_LINEAR_ALIGNED ? RADEON_SURF_MODE_LINEAR : dst_mode;
3590
3591 if (src_pitch != dst_pitch || src_box->x || dst_x || src_w != dst_w) {
3592 /* FIXME evergreen can do partial blit */
3593 goto fallback;
3594 }
3595 /* the x test here are currently useless (because we don't support partial blit)
3596 * but keep them around so we don't forget about those
3597 */
3598 if (src_pitch % 8 || src_box->x % 8 || dst_x % 8 || src_box->y % 8 || dst_y % 8) {
3599 goto fallback;
3600 }
3601
3602 /* 128 bpp surfaces require non_disp_tiling for both
3603 * tiled and linear buffers on cayman. However, async
3604 * DMA only supports it on the tiled side. As such
3605 * the tile order is backwards after a L2T/T2L packet.
3606 */
3607 if ((rctx->b.chip_class == CAYMAN) &&
3608 (src_mode != dst_mode) &&
3609 (util_format_get_blocksize(src->format) >= 16)) {
3610 goto fallback;
3611 }
3612
3613 if (src_mode == dst_mode) {
3614 uint64_t dst_offset, src_offset;
3615 /* simple dma blit would do NOTE code here assume :
3616 * src_box.x/y == 0
3617 * dst_x/y == 0
3618 * dst_pitch == src_pitch
3619 */
3620 src_offset= rsrc->surface.level[src_level].offset;
3621 src_offset += rsrc->surface.level[src_level].slice_size * src_box->z;
3622 src_offset += src_y * src_pitch + src_x * bpp;
3623 dst_offset = rdst->surface.level[dst_level].offset;
3624 dst_offset += rdst->surface.level[dst_level].slice_size * dst_z;
3625 dst_offset += dst_y * dst_pitch + dst_x * bpp;
3626 evergreen_dma_copy_buffer(rctx, dst, src, dst_offset, src_offset,
3627 src_box->height * src_pitch);
3628 } else {
3629 evergreen_dma_copy_tile(rctx, dst, dst_level, dst_x, dst_y, dst_z,
3630 src, src_level, src_x, src_y, src_box->z,
3631 copy_height, dst_pitch, bpp);
3632 }
3633 return;
3634
3635 fallback:
3636 r600_resource_copy_region(ctx, dst, dst_level, dstx, dsty, dstz,
3637 src, src_level, src_box);
3638 }
3639
3640 static void evergreen_set_tess_state(struct pipe_context *ctx,
3641 const float default_outer_level[4],
3642 const float default_inner_level[2])
3643 {
3644 struct r600_context *rctx = (struct r600_context *)ctx;
3645
3646 memcpy(rctx->tess_state, default_outer_level, sizeof(float) * 4);
3647 memcpy(rctx->tess_state+4, default_inner_level, sizeof(float) * 2);
3648 rctx->tess_state_dirty = true;
3649 }
3650
3651 void evergreen_init_state_functions(struct r600_context *rctx)
3652 {
3653 unsigned id = 1;
3654 unsigned i;
3655 /* !!!
3656 * To avoid GPU lockup registers must be emitted in a specific order
3657 * (no kidding ...). The order below is important and have been
3658 * partially inferred from analyzing fglrx command stream.
3659 *
3660 * Don't reorder atom without carefully checking the effect (GPU lockup
3661 * or piglit regression).
3662 * !!!
3663 */
3664 if (rctx->b.chip_class == EVERGREEN) {
3665 r600_init_atom(rctx, &rctx->config_state.atom, id++, evergreen_emit_config_state, 11);
3666 rctx->config_state.dyn_gpr_enabled = true;
3667 }
3668 r600_init_atom(rctx, &rctx->framebuffer.atom, id++, evergreen_emit_framebuffer_state, 0);
3669 /* shader const */
3670 r600_init_atom(rctx, &rctx->constbuf_state[PIPE_SHADER_VERTEX].atom, id++, evergreen_emit_vs_constant_buffers, 0);
3671 r600_init_atom(rctx, &rctx->constbuf_state[PIPE_SHADER_GEOMETRY].atom, id++, evergreen_emit_gs_constant_buffers, 0);
3672 r600_init_atom(rctx, &rctx->constbuf_state[PIPE_SHADER_FRAGMENT].atom, id++, evergreen_emit_ps_constant_buffers, 0);
3673 r600_init_atom(rctx, &rctx->constbuf_state[PIPE_SHADER_TESS_CTRL].atom, id++, evergreen_emit_tcs_constant_buffers, 0);
3674 r600_init_atom(rctx, &rctx->constbuf_state[PIPE_SHADER_TESS_EVAL].atom, id++, evergreen_emit_tes_constant_buffers, 0);
3675 r600_init_atom(rctx, &rctx->constbuf_state[PIPE_SHADER_COMPUTE].atom, id++, evergreen_emit_cs_constant_buffers, 0);
3676 /* shader program */
3677 r600_init_atom(rctx, &rctx->cs_shader_state.atom, id++, evergreen_emit_cs_shader, 0);
3678 /* sampler */
3679 r600_init_atom(rctx, &rctx->samplers[PIPE_SHADER_VERTEX].states.atom, id++, evergreen_emit_vs_sampler_states, 0);
3680 r600_init_atom(rctx, &rctx->samplers[PIPE_SHADER_GEOMETRY].states.atom, id++, evergreen_emit_gs_sampler_states, 0);
3681 r600_init_atom(rctx, &rctx->samplers[PIPE_SHADER_TESS_CTRL].states.atom, id++, evergreen_emit_tcs_sampler_states, 0);
3682 r600_init_atom(rctx, &rctx->samplers[PIPE_SHADER_TESS_EVAL].states.atom, id++, evergreen_emit_tes_sampler_states, 0);
3683 r600_init_atom(rctx, &rctx->samplers[PIPE_SHADER_FRAGMENT].states.atom, id++, evergreen_emit_ps_sampler_states, 0);
3684 r600_init_atom(rctx, &rctx->samplers[PIPE_SHADER_COMPUTE].states.atom, id++, evergreen_emit_cs_sampler_states, 0);
3685 /* resources */
3686 r600_init_atom(rctx, &rctx->vertex_buffer_state.atom, id++, evergreen_fs_emit_vertex_buffers, 0);
3687 r600_init_atom(rctx, &rctx->cs_vertex_buffer_state.atom, id++, evergreen_cs_emit_vertex_buffers, 0);
3688 r600_init_atom(rctx, &rctx->samplers[PIPE_SHADER_VERTEX].views.atom, id++, evergreen_emit_vs_sampler_views, 0);
3689 r600_init_atom(rctx, &rctx->samplers[PIPE_SHADER_GEOMETRY].views.atom, id++, evergreen_emit_gs_sampler_views, 0);
3690 r600_init_atom(rctx, &rctx->samplers[PIPE_SHADER_TESS_CTRL].views.atom, id++, evergreen_emit_tcs_sampler_views, 0);
3691 r600_init_atom(rctx, &rctx->samplers[PIPE_SHADER_TESS_EVAL].views.atom, id++, evergreen_emit_tes_sampler_views, 0);
3692 r600_init_atom(rctx, &rctx->samplers[PIPE_SHADER_FRAGMENT].views.atom, id++, evergreen_emit_ps_sampler_views, 0);
3693 r600_init_atom(rctx, &rctx->samplers[PIPE_SHADER_COMPUTE].views.atom, id++, evergreen_emit_cs_sampler_views, 0);
3694
3695 r600_init_atom(rctx, &rctx->vgt_state.atom, id++, r600_emit_vgt_state, 10);
3696
3697 if (rctx->b.chip_class == EVERGREEN) {
3698 r600_init_atom(rctx, &rctx->sample_mask.atom, id++, evergreen_emit_sample_mask, 3);
3699 } else {
3700 r600_init_atom(rctx, &rctx->sample_mask.atom, id++, cayman_emit_sample_mask, 4);
3701 }
3702 rctx->sample_mask.sample_mask = ~0;
3703
3704 r600_init_atom(rctx, &rctx->alphatest_state.atom, id++, r600_emit_alphatest_state, 6);
3705 r600_init_atom(rctx, &rctx->blend_color.atom, id++, r600_emit_blend_color, 6);
3706 r600_init_atom(rctx, &rctx->blend_state.atom, id++, r600_emit_cso_state, 0);
3707 r600_init_atom(rctx, &rctx->cb_misc_state.atom, id++, evergreen_emit_cb_misc_state, 4);
3708 r600_init_atom(rctx, &rctx->clip_misc_state.atom, id++, r600_emit_clip_misc_state, 9);
3709 r600_init_atom(rctx, &rctx->clip_state.atom, id++, evergreen_emit_clip_state, 26);
3710 r600_init_atom(rctx, &rctx->db_misc_state.atom, id++, evergreen_emit_db_misc_state, 10);
3711 r600_init_atom(rctx, &rctx->db_state.atom, id++, evergreen_emit_db_state, 14);
3712 r600_init_atom(rctx, &rctx->dsa_state.atom, id++, r600_emit_cso_state, 0);
3713 r600_init_atom(rctx, &rctx->poly_offset_state.atom, id++, evergreen_emit_polygon_offset, 6);
3714 r600_init_atom(rctx, &rctx->rasterizer_state.atom, id++, r600_emit_cso_state, 0);
3715 r600_init_atom(rctx, &rctx->scissor.atom, id++, evergreen_emit_scissor_state, 0);
3716 r600_init_atom(rctx, &rctx->viewport.atom, id++, r600_emit_viewport_state, 0);
3717 r600_init_atom(rctx, &rctx->stencil_ref.atom, id++, r600_emit_stencil_ref, 4);
3718 r600_init_atom(rctx, &rctx->vertex_fetch_shader.atom, id++, evergreen_emit_vertex_fetch_shader, 5);
3719 r600_add_atom(rctx, &rctx->b.render_cond_atom, id++);
3720 r600_add_atom(rctx, &rctx->b.streamout.begin_atom, id++);
3721 r600_add_atom(rctx, &rctx->b.streamout.enable_atom, id++);
3722 for (i = 0; i < EG_NUM_HW_STAGES; i++)
3723 r600_init_atom(rctx, &rctx->hw_shader_stages[i].atom, id++, r600_emit_shader, 0);
3724 r600_init_atom(rctx, &rctx->shader_stages.atom, id++, evergreen_emit_shader_stages, 15);
3725 r600_init_atom(rctx, &rctx->gs_rings.atom, id++, evergreen_emit_gs_rings, 26);
3726
3727 rctx->b.b.create_blend_state = evergreen_create_blend_state;
3728 rctx->b.b.create_depth_stencil_alpha_state = evergreen_create_dsa_state;
3729 rctx->b.b.create_rasterizer_state = evergreen_create_rs_state;
3730 rctx->b.b.create_sampler_state = evergreen_create_sampler_state;
3731 rctx->b.b.create_sampler_view = evergreen_create_sampler_view;
3732 rctx->b.b.set_framebuffer_state = evergreen_set_framebuffer_state;
3733 rctx->b.b.set_polygon_stipple = evergreen_set_polygon_stipple;
3734 rctx->b.b.set_min_samples = evergreen_set_min_samples;
3735 rctx->b.b.set_scissor_states = evergreen_set_scissor_states;
3736 rctx->b.b.set_tess_state = evergreen_set_tess_state;
3737 if (rctx->b.chip_class == EVERGREEN)
3738 rctx->b.b.get_sample_position = evergreen_get_sample_position;
3739 else
3740 rctx->b.b.get_sample_position = cayman_get_sample_position;
3741 rctx->b.dma_copy = evergreen_dma_copy;
3742
3743 evergreen_init_compute_state_functions(rctx);
3744 }
3745
3746 /**
3747 * This calculates the LDS size for tessellation shaders (VS, TCS, TES).
3748 *
3749 * The information about LDS and other non-compile-time parameters is then
3750 * written to the const buffer.
3751
3752 * const buffer contains -
3753 * uint32_t input_patch_size
3754 * uint32_t input_vertex_size
3755 * uint32_t num_tcs_input_cp
3756 * uint32_t num_tcs_output_cp;
3757 * uint32_t output_patch_size
3758 * uint32_t output_vertex_size
3759 * uint32_t output_patch0_offset
3760 * uint32_t perpatch_output_offset
3761 * and the same constbuf is bound to LS/HS/VS(ES).
3762 */
3763 void evergreen_setup_tess_constants(struct r600_context *rctx, const struct pipe_draw_info *info, unsigned *num_patches)
3764 {
3765 struct pipe_constant_buffer constbuf = {0};
3766 struct r600_pipe_shader_selector *tcs = rctx->tcs_shader ? rctx->tcs_shader : rctx->tes_shader;
3767 struct r600_pipe_shader_selector *ls = rctx->vs_shader;
3768 unsigned num_tcs_input_cp = info->vertices_per_patch;
3769 unsigned num_tcs_outputs;
3770 unsigned num_tcs_output_cp;
3771 unsigned num_tcs_patch_outputs;
3772 unsigned num_tcs_inputs;
3773 unsigned input_vertex_size, output_vertex_size;
3774 unsigned input_patch_size, pervertex_output_patch_size, output_patch_size;
3775 unsigned output_patch0_offset, perpatch_output_offset, lds_size;
3776 uint32_t values[16];
3777 unsigned num_waves;
3778 unsigned num_pipes = rctx->screen->b.info.r600_max_quad_pipes;
3779 unsigned wave_divisor = (16 * num_pipes);
3780
3781 *num_patches = 1;
3782
3783 if (!rctx->tes_shader) {
3784 rctx->lds_alloc = 0;
3785 rctx->b.b.set_constant_buffer(&rctx->b.b, PIPE_SHADER_VERTEX,
3786 R600_LDS_INFO_CONST_BUFFER, NULL);
3787 rctx->b.b.set_constant_buffer(&rctx->b.b, PIPE_SHADER_TESS_CTRL,
3788 R600_LDS_INFO_CONST_BUFFER, NULL);
3789 rctx->b.b.set_constant_buffer(&rctx->b.b, PIPE_SHADER_TESS_EVAL,
3790 R600_LDS_INFO_CONST_BUFFER, NULL);
3791 return;
3792 }
3793
3794 if (rctx->lds_alloc != 0 &&
3795 rctx->last_ls == ls &&
3796 !rctx->tess_state_dirty &&
3797 rctx->last_num_tcs_input_cp == num_tcs_input_cp &&
3798 rctx->last_tcs == tcs)
3799 return;
3800
3801 num_tcs_inputs = util_last_bit64(ls->lds_outputs_written_mask);
3802
3803 if (rctx->tcs_shader) {
3804 num_tcs_outputs = util_last_bit64(tcs->lds_outputs_written_mask);
3805 num_tcs_output_cp = tcs->info.properties[TGSI_PROPERTY_TCS_VERTICES_OUT];
3806 num_tcs_patch_outputs = util_last_bit64(tcs->lds_patch_outputs_written_mask);
3807 } else {
3808 num_tcs_outputs = num_tcs_inputs;
3809 num_tcs_output_cp = num_tcs_input_cp;
3810 num_tcs_patch_outputs = 2; /* TESSINNER + TESSOUTER */
3811 }
3812
3813 /* size in bytes */
3814 input_vertex_size = num_tcs_inputs * 16;
3815 output_vertex_size = num_tcs_outputs * 16;
3816
3817 input_patch_size = num_tcs_input_cp * input_vertex_size;
3818
3819 pervertex_output_patch_size = num_tcs_output_cp * output_vertex_size;
3820 output_patch_size = pervertex_output_patch_size + num_tcs_patch_outputs * 16;
3821
3822 output_patch0_offset = rctx->tcs_shader ? input_patch_size * *num_patches : 0;
3823 perpatch_output_offset = output_patch0_offset + pervertex_output_patch_size;
3824
3825 lds_size = output_patch0_offset + output_patch_size * *num_patches;
3826
3827 values[0] = input_patch_size;
3828 values[1] = input_vertex_size;
3829 values[2] = num_tcs_input_cp;
3830 values[3] = num_tcs_output_cp;
3831
3832 values[4] = output_patch_size;
3833 values[5] = output_vertex_size;
3834 values[6] = output_patch0_offset;
3835 values[7] = perpatch_output_offset;
3836
3837 /* docs say HS_NUM_WAVES - CEIL((LS_HS_CONFIG.NUM_PATCHES *
3838 LS_HS_CONFIG.HS_NUM_OUTPUT_CP) / (NUM_GOOD_PIPES * 16)) */
3839 num_waves = ceilf((float)(*num_patches * num_tcs_output_cp) / (float)wave_divisor);
3840
3841 rctx->lds_alloc = (lds_size | (num_waves << 14));
3842
3843 memcpy(&values[8], rctx->tess_state, 6 * sizeof(float));
3844 values[14] = 0;
3845 values[15] = 0;
3846
3847 rctx->tess_state_dirty = false;
3848 rctx->last_ls = ls;
3849 rctx->last_tcs = tcs;
3850 rctx->last_num_tcs_input_cp = num_tcs_input_cp;
3851
3852 constbuf.user_buffer = values;
3853 constbuf.buffer_size = 16 * 4;
3854
3855 rctx->b.b.set_constant_buffer(&rctx->b.b, PIPE_SHADER_VERTEX,
3856 R600_LDS_INFO_CONST_BUFFER, &constbuf);
3857 rctx->b.b.set_constant_buffer(&rctx->b.b, PIPE_SHADER_TESS_CTRL,
3858 R600_LDS_INFO_CONST_BUFFER, &constbuf);
3859 rctx->b.b.set_constant_buffer(&rctx->b.b, PIPE_SHADER_TESS_EVAL,
3860 R600_LDS_INFO_CONST_BUFFER, &constbuf);
3861 pipe_resource_reference(&constbuf.buffer, NULL);
3862 }
3863
3864 uint32_t evergreen_get_ls_hs_config(struct r600_context *rctx,
3865 const struct pipe_draw_info *info,
3866 unsigned num_patches)
3867 {
3868 unsigned num_output_cp;
3869
3870 if (!rctx->tes_shader)
3871 return 0;
3872
3873 num_output_cp = rctx->tcs_shader ?
3874 rctx->tcs_shader->info.properties[TGSI_PROPERTY_TCS_VERTICES_OUT] :
3875 info->vertices_per_patch;
3876
3877 return S_028B58_NUM_PATCHES(num_patches) |
3878 S_028B58_HS_NUM_INPUT_CP(info->vertices_per_patch) |
3879 S_028B58_HS_NUM_OUTPUT_CP(num_output_cp);
3880 }
3881
3882 void evergreen_set_ls_hs_config(struct r600_context *rctx,
3883 struct radeon_winsys_cs *cs,
3884 uint32_t ls_hs_config)
3885 {
3886 radeon_set_context_reg(cs, R_028B58_VGT_LS_HS_CONFIG, ls_hs_config);
3887 }
3888
3889 void evergreen_set_lds_alloc(struct r600_context *rctx,
3890 struct radeon_winsys_cs *cs,
3891 uint32_t lds_alloc)
3892 {
3893 radeon_set_context_reg(cs, R_0288E8_SQ_LDS_ALLOC, lds_alloc);
3894 }
3895
3896 /* on evergreen if you are running tessellation you need to disable dynamic
3897 GPRs to workaround a hardware bug.*/
3898 bool evergreen_adjust_gprs(struct r600_context *rctx)
3899 {
3900 unsigned num_gprs[EG_NUM_HW_STAGES];
3901 unsigned def_gprs[EG_NUM_HW_STAGES];
3902 unsigned cur_gprs[EG_NUM_HW_STAGES];
3903 unsigned new_gprs[EG_NUM_HW_STAGES];
3904 unsigned def_num_clause_temp_gprs = rctx->r6xx_num_clause_temp_gprs;
3905 unsigned max_gprs;
3906 unsigned i;
3907 unsigned total_gprs;
3908 unsigned tmp[3];
3909 bool rework = false, set_default = false, set_dirty = false;
3910 max_gprs = 0;
3911 for (i = 0; i < EG_NUM_HW_STAGES; i++) {
3912 def_gprs[i] = rctx->default_gprs[i];
3913 max_gprs += def_gprs[i];
3914 }
3915 max_gprs += def_num_clause_temp_gprs * 2;
3916
3917 /* if we have no TESS and dyn gpr is enabled then do nothing. */
3918 if (!rctx->hw_shader_stages[EG_HW_STAGE_HS].shader) {
3919 if (rctx->config_state.dyn_gpr_enabled)
3920 return true;
3921
3922 /* transition back to dyn gpr enabled state */
3923 rctx->config_state.dyn_gpr_enabled = true;
3924 r600_mark_atom_dirty(rctx, &rctx->config_state.atom);
3925 rctx->b.flags |= R600_CONTEXT_WAIT_3D_IDLE;
3926 return true;
3927 }
3928
3929
3930 /* gather required shader gprs */
3931 for (i = 0; i < EG_NUM_HW_STAGES; i++) {
3932 if (rctx->hw_shader_stages[i].shader)
3933 num_gprs[i] = rctx->hw_shader_stages[i].shader->shader.bc.ngpr;
3934 else
3935 num_gprs[i] = 0;
3936 }
3937
3938 cur_gprs[R600_HW_STAGE_PS] = G_008C04_NUM_PS_GPRS(rctx->config_state.sq_gpr_resource_mgmt_1);
3939 cur_gprs[R600_HW_STAGE_VS] = G_008C04_NUM_VS_GPRS(rctx->config_state.sq_gpr_resource_mgmt_1);
3940 cur_gprs[R600_HW_STAGE_GS] = G_008C08_NUM_GS_GPRS(rctx->config_state.sq_gpr_resource_mgmt_2);
3941 cur_gprs[R600_HW_STAGE_ES] = G_008C08_NUM_ES_GPRS(rctx->config_state.sq_gpr_resource_mgmt_2);
3942 cur_gprs[EG_HW_STAGE_LS] = G_008C0C_NUM_LS_GPRS(rctx->config_state.sq_gpr_resource_mgmt_3);
3943 cur_gprs[EG_HW_STAGE_HS] = G_008C0C_NUM_HS_GPRS(rctx->config_state.sq_gpr_resource_mgmt_3);
3944
3945 total_gprs = 0;
3946 for (i = 0; i < EG_NUM_HW_STAGES; i++) {
3947 new_gprs[i] = num_gprs[i];
3948 total_gprs += num_gprs[i];
3949 }
3950
3951 if (total_gprs > (max_gprs - (2 * def_num_clause_temp_gprs)))
3952 return false;
3953
3954 for (i = 0; i < EG_NUM_HW_STAGES; i++) {
3955 if (new_gprs[i] > cur_gprs[i]) {
3956 rework = true;
3957 break;
3958 }
3959 }
3960
3961 if (rctx->config_state.dyn_gpr_enabled) {
3962 set_dirty = true;
3963 rctx->config_state.dyn_gpr_enabled = false;
3964 }
3965
3966 if (rework) {
3967 set_default = true;
3968 for (i = 0; i < EG_NUM_HW_STAGES; i++) {
3969 if (new_gprs[i] > def_gprs[i])
3970 set_default = false;
3971 }
3972
3973 if (set_default) {
3974 for (i = 0; i < EG_NUM_HW_STAGES; i++) {
3975 new_gprs[i] = def_gprs[i];
3976 }
3977 } else {
3978 unsigned ps_value = max_gprs;
3979
3980 ps_value -= (def_num_clause_temp_gprs * 2);
3981 for (i = R600_HW_STAGE_VS; i < EG_NUM_HW_STAGES; i++)
3982 ps_value -= new_gprs[i];
3983
3984 new_gprs[R600_HW_STAGE_PS] = ps_value;
3985 }
3986
3987 tmp[0] = S_008C04_NUM_PS_GPRS(new_gprs[R600_HW_STAGE_PS]) |
3988 S_008C04_NUM_VS_GPRS(new_gprs[R600_HW_STAGE_VS]) |
3989 S_008C04_NUM_CLAUSE_TEMP_GPRS(def_num_clause_temp_gprs);
3990
3991 tmp[1] = S_008C08_NUM_ES_GPRS(new_gprs[R600_HW_STAGE_ES]) |
3992 S_008C08_NUM_GS_GPRS(new_gprs[R600_HW_STAGE_GS]);
3993
3994 tmp[2] = S_008C0C_NUM_HS_GPRS(new_gprs[EG_HW_STAGE_HS]) |
3995 S_008C0C_NUM_LS_GPRS(new_gprs[EG_HW_STAGE_LS]);
3996
3997 if (rctx->config_state.sq_gpr_resource_mgmt_1 != tmp[0] ||
3998 rctx->config_state.sq_gpr_resource_mgmt_2 != tmp[1] ||
3999 rctx->config_state.sq_gpr_resource_mgmt_3 != tmp[2]) {
4000 rctx->config_state.sq_gpr_resource_mgmt_1 = tmp[0];
4001 rctx->config_state.sq_gpr_resource_mgmt_2 = tmp[1];
4002 rctx->config_state.sq_gpr_resource_mgmt_3 = tmp[2];
4003 set_dirty = true;
4004 }
4005 }
4006
4007
4008 if (set_dirty) {
4009 r600_mark_atom_dirty(rctx, &rctx->config_state.atom);
4010 rctx->b.flags |= R600_CONTEXT_WAIT_3D_IDLE;
4011 }
4012 return true;
4013 }