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r600g: fix eg/cayman scissor workaround
[mesa.git] / src / gallium / drivers / r600 / evergreen_state.c
1 /*
2 * Copyright 2010 Jerome Glisse <glisse@freedesktop.org>
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * on the rights to use, copy, modify, merge, publish, distribute, sub
8 * license, and/or sell copies of the Software, and to permit persons to whom
9 * the Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
13 * Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHOR(S) AND/OR THEIR SUPPLIERS BE LIABLE FOR ANY CLAIM,
19 * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
20 * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
21 * USE OR OTHER DEALINGS IN THE SOFTWARE.
22 */
23
24 /* TODO:
25 * - fix mask for depth control & cull for query
26 */
27 #include <stdio.h>
28 #include <errno.h>
29 #include <pipe/p_defines.h>
30 #include <pipe/p_state.h>
31 #include <pipe/p_context.h>
32 #include <tgsi/tgsi_scan.h>
33 #include <tgsi/tgsi_parse.h>
34 #include <tgsi/tgsi_util.h>
35 #include <util/u_blitter.h>
36 #include <util/u_double_list.h>
37 #include <util/u_transfer.h>
38 #include <util/u_surface.h>
39 #include <util/u_pack_color.h>
40 #include <util/u_memory.h>
41 #include <util/u_inlines.h>
42 #include <util/u_framebuffer.h>
43 #include <pipebuffer/pb_buffer.h>
44 #include "r600.h"
45 #include "evergreend.h"
46 #include "r600_resource.h"
47 #include "r600_shader.h"
48 #include "r600_pipe.h"
49 #include "eg_state_inlines.h"
50
51 static void evergreen_set_blend_color(struct pipe_context *ctx,
52 const struct pipe_blend_color *state)
53 {
54 struct r600_pipe_context *rctx = (struct r600_pipe_context *)ctx;
55 struct r600_pipe_state *rstate = CALLOC_STRUCT(r600_pipe_state);
56
57 if (rstate == NULL)
58 return;
59
60 rstate->id = R600_PIPE_STATE_BLEND_COLOR;
61 r600_pipe_state_add_reg(rstate, R_028414_CB_BLEND_RED, fui(state->color[0]), 0xFFFFFFFF, NULL);
62 r600_pipe_state_add_reg(rstate, R_028418_CB_BLEND_GREEN, fui(state->color[1]), 0xFFFFFFFF, NULL);
63 r600_pipe_state_add_reg(rstate, R_02841C_CB_BLEND_BLUE, fui(state->color[2]), 0xFFFFFFFF, NULL);
64 r600_pipe_state_add_reg(rstate, R_028420_CB_BLEND_ALPHA, fui(state->color[3]), 0xFFFFFFFF, NULL);
65
66 free(rctx->states[R600_PIPE_STATE_BLEND_COLOR]);
67 rctx->states[R600_PIPE_STATE_BLEND_COLOR] = rstate;
68 r600_context_pipe_state_set(&rctx->ctx, rstate);
69 }
70
71 static void *evergreen_create_blend_state(struct pipe_context *ctx,
72 const struct pipe_blend_state *state)
73 {
74 struct r600_pipe_context *rctx = (struct r600_pipe_context *)ctx;
75 struct r600_pipe_blend *blend = CALLOC_STRUCT(r600_pipe_blend);
76 struct r600_pipe_state *rstate;
77 u32 color_control, target_mask;
78 /* FIXME there is more then 8 framebuffer */
79 unsigned blend_cntl[8];
80 enum radeon_family family;
81
82 if (blend == NULL) {
83 return NULL;
84 }
85
86 family = r600_get_family(rctx->radeon);
87 rstate = &blend->rstate;
88
89 rstate->id = R600_PIPE_STATE_BLEND;
90
91 target_mask = 0;
92 color_control = S_028808_MODE(1);
93 if (state->logicop_enable) {
94 color_control |= (state->logicop_func << 16) | (state->logicop_func << 20);
95 } else {
96 color_control |= (0xcc << 16);
97 }
98 /* we pretend 8 buffer are used, CB_SHADER_MASK will disable unused one */
99 if (state->independent_blend_enable) {
100 for (int i = 0; i < 8; i++) {
101 target_mask |= (state->rt[i].colormask << (4 * i));
102 }
103 } else {
104 for (int i = 0; i < 8; i++) {
105 target_mask |= (state->rt[0].colormask << (4 * i));
106 }
107 }
108 blend->cb_target_mask = target_mask;
109
110 r600_pipe_state_add_reg(rstate, R_028808_CB_COLOR_CONTROL,
111 color_control, 0xFFFFFFFD, NULL);
112
113 if (family != CHIP_CAYMAN)
114 r600_pipe_state_add_reg(rstate, R_028C3C_PA_SC_AA_MASK, 0xFFFFFFFF, 0xFFFFFFFF, NULL);
115 else {
116 r600_pipe_state_add_reg(rstate, CM_R_028C38_PA_SC_AA_MASK_X0Y0_X1Y0, 0xFFFFFFFF, 0xFFFFFFFF, NULL);
117 r600_pipe_state_add_reg(rstate, CM_R_028C3C_PA_SC_AA_MASK_X0Y1_X1Y1, 0xFFFFFFFF, 0xFFFFFFFF, NULL);
118 }
119
120 for (int i = 0; i < 8; i++) {
121 /* state->rt entries > 0 only written if independent blending */
122 const int j = state->independent_blend_enable ? i : 0;
123
124 unsigned eqRGB = state->rt[j].rgb_func;
125 unsigned srcRGB = state->rt[j].rgb_src_factor;
126 unsigned dstRGB = state->rt[j].rgb_dst_factor;
127 unsigned eqA = state->rt[j].alpha_func;
128 unsigned srcA = state->rt[j].alpha_src_factor;
129 unsigned dstA = state->rt[j].alpha_dst_factor;
130
131 blend_cntl[i] = 0;
132 if (!state->rt[j].blend_enable)
133 continue;
134
135 blend_cntl[i] |= S_028780_BLEND_CONTROL_ENABLE(1);
136 blend_cntl[i] |= S_028780_COLOR_COMB_FCN(r600_translate_blend_function(eqRGB));
137 blend_cntl[i] |= S_028780_COLOR_SRCBLEND(r600_translate_blend_factor(srcRGB));
138 blend_cntl[i] |= S_028780_COLOR_DESTBLEND(r600_translate_blend_factor(dstRGB));
139
140 if (srcA != srcRGB || dstA != dstRGB || eqA != eqRGB) {
141 blend_cntl[i] |= S_028780_SEPARATE_ALPHA_BLEND(1);
142 blend_cntl[i] |= S_028780_ALPHA_COMB_FCN(r600_translate_blend_function(eqA));
143 blend_cntl[i] |= S_028780_ALPHA_SRCBLEND(r600_translate_blend_factor(srcA));
144 blend_cntl[i] |= S_028780_ALPHA_DESTBLEND(r600_translate_blend_factor(dstA));
145 }
146 }
147 for (int i = 0; i < 8; i++) {
148 r600_pipe_state_add_reg(rstate, R_028780_CB_BLEND0_CONTROL + i * 4, blend_cntl[i], 0xFFFFFFFF, NULL);
149 }
150
151 return rstate;
152 }
153
154 static void *evergreen_create_dsa_state(struct pipe_context *ctx,
155 const struct pipe_depth_stencil_alpha_state *state)
156 {
157 struct r600_pipe_dsa *dsa = CALLOC_STRUCT(r600_pipe_dsa);
158 unsigned db_depth_control, alpha_test_control, alpha_ref, db_shader_control;
159 unsigned stencil_ref_mask, stencil_ref_mask_bf, db_render_override, db_render_control;
160 struct r600_pipe_state *rstate;
161
162 if (dsa == NULL) {
163 return NULL;
164 }
165
166 rstate = &dsa->rstate;
167
168 rstate->id = R600_PIPE_STATE_DSA;
169 /* depth TODO some of those db_shader_control field depend on shader adjust mask & add it to shader */
170 db_shader_control = S_02880C_Z_ORDER(V_02880C_EARLY_Z_THEN_LATE_Z);
171 stencil_ref_mask = 0;
172 stencil_ref_mask_bf = 0;
173 db_depth_control = S_028800_Z_ENABLE(state->depth.enabled) |
174 S_028800_Z_WRITE_ENABLE(state->depth.writemask) |
175 S_028800_ZFUNC(state->depth.func);
176
177 /* stencil */
178 if (state->stencil[0].enabled) {
179 db_depth_control |= S_028800_STENCIL_ENABLE(1);
180 db_depth_control |= S_028800_STENCILFUNC(r600_translate_ds_func(state->stencil[0].func));
181 db_depth_control |= S_028800_STENCILFAIL(r600_translate_stencil_op(state->stencil[0].fail_op));
182 db_depth_control |= S_028800_STENCILZPASS(r600_translate_stencil_op(state->stencil[0].zpass_op));
183 db_depth_control |= S_028800_STENCILZFAIL(r600_translate_stencil_op(state->stencil[0].zfail_op));
184
185
186 stencil_ref_mask = S_028430_STENCILMASK(state->stencil[0].valuemask) |
187 S_028430_STENCILWRITEMASK(state->stencil[0].writemask);
188 if (state->stencil[1].enabled) {
189 db_depth_control |= S_028800_BACKFACE_ENABLE(1);
190 db_depth_control |= S_028800_STENCILFUNC_BF(r600_translate_ds_func(state->stencil[1].func));
191 db_depth_control |= S_028800_STENCILFAIL_BF(r600_translate_stencil_op(state->stencil[1].fail_op));
192 db_depth_control |= S_028800_STENCILZPASS_BF(r600_translate_stencil_op(state->stencil[1].zpass_op));
193 db_depth_control |= S_028800_STENCILZFAIL_BF(r600_translate_stencil_op(state->stencil[1].zfail_op));
194 stencil_ref_mask_bf = S_028434_STENCILMASK_BF(state->stencil[1].valuemask) |
195 S_028434_STENCILWRITEMASK_BF(state->stencil[1].writemask);
196 }
197 }
198
199 /* alpha */
200 alpha_test_control = 0;
201 alpha_ref = 0;
202 if (state->alpha.enabled) {
203 alpha_test_control = S_028410_ALPHA_FUNC(state->alpha.func);
204 alpha_test_control |= S_028410_ALPHA_TEST_ENABLE(1);
205 alpha_ref = fui(state->alpha.ref_value);
206 }
207 dsa->alpha_ref = alpha_ref;
208
209 /* misc */
210 db_render_control = 0;
211 db_render_override = S_02800C_FORCE_HIZ_ENABLE(V_02800C_FORCE_DISABLE) |
212 S_02800C_FORCE_HIS_ENABLE0(V_02800C_FORCE_DISABLE) |
213 S_02800C_FORCE_HIS_ENABLE1(V_02800C_FORCE_DISABLE);
214 /* TODO db_render_override depends on query */
215 r600_pipe_state_add_reg(rstate, R_028028_DB_STENCIL_CLEAR, 0x00000000, 0xFFFFFFFF, NULL);
216 r600_pipe_state_add_reg(rstate, R_02802C_DB_DEPTH_CLEAR, 0x3F800000, 0xFFFFFFFF, NULL);
217 r600_pipe_state_add_reg(rstate, R_028410_SX_ALPHA_TEST_CONTROL, alpha_test_control, 0xFFFFFFFF, NULL);
218 r600_pipe_state_add_reg(rstate,
219 R_028430_DB_STENCILREFMASK, stencil_ref_mask,
220 0xFFFFFFFF & C_028430_STENCILREF, NULL);
221 r600_pipe_state_add_reg(rstate,
222 R_028434_DB_STENCILREFMASK_BF, stencil_ref_mask_bf,
223 0xFFFFFFFF & C_028434_STENCILREF_BF, NULL);
224 r600_pipe_state_add_reg(rstate, R_0286DC_SPI_FOG_CNTL, 0x00000000, 0xFFFFFFFF, NULL);
225 r600_pipe_state_add_reg(rstate, R_028800_DB_DEPTH_CONTROL, db_depth_control, 0xFFFFFFFF, NULL);
226 /* The DB_SHADER_CONTROL mask is 0xFFFFFFBC since Z_EXPORT_ENABLE,
227 * STENCIL_EXPORT_ENABLE and KILL_ENABLE are controlled by
228 * evergreen_pipe_shader_ps().*/
229 r600_pipe_state_add_reg(rstate, R_02880C_DB_SHADER_CONTROL, db_shader_control, 0xFFFFFFBC, NULL);
230 r600_pipe_state_add_reg(rstate, R_028000_DB_RENDER_CONTROL, db_render_control, 0xFFFFFFFF, NULL);
231 r600_pipe_state_add_reg(rstate, R_02800C_DB_RENDER_OVERRIDE, db_render_override, 0xFFFFFFFF, NULL);
232 r600_pipe_state_add_reg(rstate, R_028AC0_DB_SRESULTS_COMPARE_STATE0, 0x0, 0xFFFFFFFF, NULL);
233 r600_pipe_state_add_reg(rstate, R_028AC4_DB_SRESULTS_COMPARE_STATE1, 0x0, 0xFFFFFFFF, NULL);
234 r600_pipe_state_add_reg(rstate, R_028AC8_DB_PRELOAD_CONTROL, 0x0, 0xFFFFFFFF, NULL);
235 r600_pipe_state_add_reg(rstate, R_028B70_DB_ALPHA_TO_MASK, 0x0000AA00, 0xFFFFFFFF, NULL);
236
237 return rstate;
238 }
239
240 static void *evergreen_create_rs_state(struct pipe_context *ctx,
241 const struct pipe_rasterizer_state *state)
242 {
243 struct r600_pipe_context *rctx = (struct r600_pipe_context *)ctx;
244 struct r600_pipe_rasterizer *rs = CALLOC_STRUCT(r600_pipe_rasterizer);
245 struct r600_pipe_state *rstate;
246 unsigned tmp;
247 unsigned prov_vtx = 1, polygon_dual_mode;
248 unsigned clip_rule;
249 enum radeon_family family;
250
251 family = r600_get_family(rctx->radeon);
252
253 if (rs == NULL) {
254 return NULL;
255 }
256
257 rstate = &rs->rstate;
258 rs->flatshade = state->flatshade;
259 rs->sprite_coord_enable = state->sprite_coord_enable;
260
261 clip_rule = state->scissor ? 0xAAAA : 0xFFFF;
262
263 /* offset */
264 rs->offset_units = state->offset_units;
265 rs->offset_scale = state->offset_scale * 12.0f;
266
267 rstate->id = R600_PIPE_STATE_RASTERIZER;
268 if (state->flatshade_first)
269 prov_vtx = 0;
270 tmp = S_0286D4_FLAT_SHADE_ENA(1);
271 if (state->sprite_coord_enable) {
272 tmp |= S_0286D4_PNT_SPRITE_ENA(1) |
273 S_0286D4_PNT_SPRITE_OVRD_X(2) |
274 S_0286D4_PNT_SPRITE_OVRD_Y(3) |
275 S_0286D4_PNT_SPRITE_OVRD_Z(0) |
276 S_0286D4_PNT_SPRITE_OVRD_W(1);
277 if (state->sprite_coord_mode != PIPE_SPRITE_COORD_UPPER_LEFT) {
278 tmp |= S_0286D4_PNT_SPRITE_TOP_1(1);
279 }
280 }
281 r600_pipe_state_add_reg(rstate, R_0286D4_SPI_INTERP_CONTROL_0, tmp, 0xFFFFFFFF, NULL);
282
283 polygon_dual_mode = (state->fill_front != PIPE_POLYGON_MODE_FILL ||
284 state->fill_back != PIPE_POLYGON_MODE_FILL);
285 r600_pipe_state_add_reg(rstate, R_028814_PA_SU_SC_MODE_CNTL,
286 S_028814_PROVOKING_VTX_LAST(prov_vtx) |
287 S_028814_CULL_FRONT((state->cull_face & PIPE_FACE_FRONT) ? 1 : 0) |
288 S_028814_CULL_BACK((state->cull_face & PIPE_FACE_BACK) ? 1 : 0) |
289 S_028814_FACE(!state->front_ccw) |
290 S_028814_POLY_OFFSET_FRONT_ENABLE(state->offset_tri) |
291 S_028814_POLY_OFFSET_BACK_ENABLE(state->offset_tri) |
292 S_028814_POLY_OFFSET_PARA_ENABLE(state->offset_tri) |
293 S_028814_POLY_MODE(polygon_dual_mode) |
294 S_028814_POLYMODE_FRONT_PTYPE(r600_translate_fill(state->fill_front)) |
295 S_028814_POLYMODE_BACK_PTYPE(r600_translate_fill(state->fill_back)), 0xFFFFFFFF, NULL);
296 r600_pipe_state_add_reg(rstate, R_02881C_PA_CL_VS_OUT_CNTL,
297 S_02881C_USE_VTX_POINT_SIZE(state->point_size_per_vertex) |
298 S_02881C_VS_OUT_MISC_VEC_ENA(state->point_size_per_vertex), 0xFFFFFFFF, NULL);
299 r600_pipe_state_add_reg(rstate, R_028820_PA_CL_NANINF_CNTL, 0x00000000, 0xFFFFFFFF, NULL);
300 /* point size 12.4 fixed point */
301 tmp = (unsigned)(state->point_size * 8.0);
302 r600_pipe_state_add_reg(rstate, R_028A00_PA_SU_POINT_SIZE, S_028A00_HEIGHT(tmp) | S_028A00_WIDTH(tmp), 0xFFFFFFFF, NULL);
303 r600_pipe_state_add_reg(rstate, R_028A04_PA_SU_POINT_MINMAX, 0x80000000, 0xFFFFFFFF, NULL);
304
305 tmp = (unsigned)state->line_width * 8;
306 r600_pipe_state_add_reg(rstate, R_028A08_PA_SU_LINE_CNTL, S_028A08_WIDTH(tmp), 0xFFFFFFFF, NULL);
307
308 if (family == CHIP_CAYMAN) {
309 r600_pipe_state_add_reg(rstate, CM_R_028BDC_PA_SC_LINE_CNTL, 0x00000400, 0xFFFFFFFF, NULL);
310 r600_pipe_state_add_reg(rstate, CM_R_028BE4_PA_SU_VTX_CNTL,
311 S_028C08_PIX_CENTER_HALF(state->gl_rasterization_rules),
312 0xFFFFFFFF, NULL);
313 r600_pipe_state_add_reg(rstate, CM_R_028BE8_PA_CL_GB_VERT_CLIP_ADJ, 0x3F800000, 0xFFFFFFFF, NULL);
314 r600_pipe_state_add_reg(rstate, CM_R_028BEC_PA_CL_GB_VERT_DISC_ADJ, 0x3F800000, 0xFFFFFFFF, NULL);
315 r600_pipe_state_add_reg(rstate, CM_R_028BF0_PA_CL_GB_HORZ_CLIP_ADJ, 0x3F800000, 0xFFFFFFFF, NULL);
316 r600_pipe_state_add_reg(rstate, CM_R_028BF4_PA_CL_GB_HORZ_DISC_ADJ, 0x3F800000, 0xFFFFFFFF, NULL);
317
318
319 } else {
320 r600_pipe_state_add_reg(rstate, R_028C00_PA_SC_LINE_CNTL, 0x00000400, 0xFFFFFFFF, NULL);
321
322 r600_pipe_state_add_reg(rstate, R_028C0C_PA_CL_GB_VERT_CLIP_ADJ, 0x3F800000, 0xFFFFFFFF, NULL);
323 r600_pipe_state_add_reg(rstate, R_028C10_PA_CL_GB_VERT_DISC_ADJ, 0x3F800000, 0xFFFFFFFF, NULL);
324 r600_pipe_state_add_reg(rstate, R_028C14_PA_CL_GB_HORZ_CLIP_ADJ, 0x3F800000, 0xFFFFFFFF, NULL);
325 r600_pipe_state_add_reg(rstate, R_028C18_PA_CL_GB_HORZ_DISC_ADJ, 0x3F800000, 0xFFFFFFFF, NULL);
326
327 r600_pipe_state_add_reg(rstate, R_028C08_PA_SU_VTX_CNTL,
328 S_028C08_PIX_CENTER_HALF(state->gl_rasterization_rules),
329 0xFFFFFFFF, NULL);
330 }
331 r600_pipe_state_add_reg(rstate, R_028B7C_PA_SU_POLY_OFFSET_CLAMP, 0x0, 0xFFFFFFFF, NULL);
332 r600_pipe_state_add_reg(rstate, R_02820C_PA_SC_CLIPRECT_RULE, clip_rule, 0xFFFFFFFF, NULL);
333 return rstate;
334 }
335
336 static void *evergreen_create_sampler_state(struct pipe_context *ctx,
337 const struct pipe_sampler_state *state)
338 {
339 struct r600_pipe_state *rstate = CALLOC_STRUCT(r600_pipe_state);
340 union util_color uc;
341 unsigned aniso_flag_offset = state->max_anisotropy > 1 ? 2 : 0;
342
343 if (rstate == NULL) {
344 return NULL;
345 }
346
347 rstate->id = R600_PIPE_STATE_SAMPLER;
348 util_pack_color(state->border_color, PIPE_FORMAT_B8G8R8A8_UNORM, &uc);
349 r600_pipe_state_add_reg(rstate, R_03C000_SQ_TEX_SAMPLER_WORD0_0,
350 S_03C000_CLAMP_X(r600_tex_wrap(state->wrap_s)) |
351 S_03C000_CLAMP_Y(r600_tex_wrap(state->wrap_t)) |
352 S_03C000_CLAMP_Z(r600_tex_wrap(state->wrap_r)) |
353 S_03C000_XY_MAG_FILTER(r600_tex_filter(state->mag_img_filter) | aniso_flag_offset) |
354 S_03C000_XY_MIN_FILTER(r600_tex_filter(state->min_img_filter) | aniso_flag_offset) |
355 S_03C000_MIP_FILTER(r600_tex_mipfilter(state->min_mip_filter)) |
356 S_03C000_MAX_ANISO(r600_tex_aniso_filter(state->max_anisotropy)) |
357 S_03C000_DEPTH_COMPARE_FUNCTION(r600_tex_compare(state->compare_func)) |
358 S_03C000_BORDER_COLOR_TYPE(uc.ui ? V_03C000_SQ_TEX_BORDER_COLOR_REGISTER : 0), 0xFFFFFFFF, NULL);
359 r600_pipe_state_add_reg(rstate, R_03C004_SQ_TEX_SAMPLER_WORD1_0,
360 S_03C004_MIN_LOD(S_FIXED(CLAMP(state->min_lod, 0, 15), 8)) |
361 S_03C004_MAX_LOD(S_FIXED(CLAMP(state->max_lod, 0, 15), 8)),
362 0xFFFFFFFF, NULL);
363 r600_pipe_state_add_reg(rstate, R_03C008_SQ_TEX_SAMPLER_WORD2_0,
364 S_03C008_LOD_BIAS(S_FIXED(CLAMP(state->lod_bias, -16, 16), 8)) |
365 (state->seamless_cube_map ? 0 : S_03C008_DISABLE_CUBE_WRAP(1)) |
366 S_03C008_TYPE(1),
367 0xFFFFFFFF, NULL);
368
369 if (uc.ui) {
370 r600_pipe_state_add_reg(rstate, R_00A404_TD_PS_SAMPLER0_BORDER_RED, fui(state->border_color[0]), 0xFFFFFFFF, NULL);
371 r600_pipe_state_add_reg(rstate, R_00A408_TD_PS_SAMPLER0_BORDER_GREEN, fui(state->border_color[1]), 0xFFFFFFFF, NULL);
372 r600_pipe_state_add_reg(rstate, R_00A40C_TD_PS_SAMPLER0_BORDER_BLUE, fui(state->border_color[2]), 0xFFFFFFFF, NULL);
373 r600_pipe_state_add_reg(rstate, R_00A410_TD_PS_SAMPLER0_BORDER_ALPHA, fui(state->border_color[3]), 0xFFFFFFFF, NULL);
374 }
375 return rstate;
376 }
377
378 static struct pipe_sampler_view *evergreen_create_sampler_view(struct pipe_context *ctx,
379 struct pipe_resource *texture,
380 const struct pipe_sampler_view *state)
381 {
382 struct r600_pipe_sampler_view *resource = CALLOC_STRUCT(r600_pipe_sampler_view);
383 struct r600_pipe_state *rstate;
384 const struct util_format_description *desc;
385 struct r600_resource_texture *tmp;
386 struct r600_resource *rbuffer;
387 unsigned format, endian;
388 uint32_t word4 = 0, yuv_format = 0, pitch = 0;
389 unsigned char swizzle[4], array_mode = 0, tile_type = 0;
390 struct r600_bo *bo[2];
391
392 if (resource == NULL)
393 return NULL;
394 rstate = &resource->state;
395
396 /* initialize base object */
397 resource->base = *state;
398 resource->base.texture = NULL;
399 pipe_reference(NULL, &texture->reference);
400 resource->base.texture = texture;
401 resource->base.reference.count = 1;
402 resource->base.context = ctx;
403
404 swizzle[0] = state->swizzle_r;
405 swizzle[1] = state->swizzle_g;
406 swizzle[2] = state->swizzle_b;
407 swizzle[3] = state->swizzle_a;
408 format = r600_translate_texformat(ctx->screen, state->format,
409 swizzle,
410 &word4, &yuv_format);
411 if (format == ~0) {
412 format = 0;
413 }
414 desc = util_format_description(state->format);
415 if (desc == NULL) {
416 R600_ERR("unknow format %d\n", state->format);
417 }
418 tmp = (struct r600_resource_texture *)texture;
419 if (tmp->depth && !tmp->is_flushing_texture) {
420 r600_texture_depth_flush(ctx, texture, TRUE);
421 tmp = tmp->flushed_depth_texture;
422 }
423
424 endian = r600_colorformat_endian_swap(format);
425
426 if (tmp->force_int_type) {
427 word4 &= C_030010_NUM_FORMAT_ALL;
428 word4 |= S_030010_NUM_FORMAT_ALL(V_030010_SQ_NUM_FORMAT_INT);
429 }
430
431 rbuffer = &tmp->resource;
432 bo[0] = rbuffer->bo;
433 bo[1] = rbuffer->bo;
434
435 pitch = align(tmp->pitch_in_blocks[0] * util_format_get_blockwidth(state->format), 8);
436 array_mode = tmp->array_mode[0];
437 tile_type = tmp->tile_type;
438
439 r600_pipe_state_add_reg(rstate, R_030000_RESOURCE0_WORD0,
440 S_030000_DIM(r600_tex_dim(texture->target)) |
441 S_030000_PITCH((pitch / 8) - 1) |
442 S_030000_NON_DISP_TILING_ORDER(tile_type) |
443 S_030000_TEX_WIDTH(texture->width0 - 1), 0xFFFFFFFF, NULL);
444 r600_pipe_state_add_reg(rstate, R_030004_RESOURCE0_WORD1,
445 S_030004_TEX_HEIGHT(texture->height0 - 1) |
446 S_030004_TEX_DEPTH(texture->depth0 - 1) |
447 S_030004_ARRAY_MODE(array_mode),
448 0xFFFFFFFF, NULL);
449 r600_pipe_state_add_reg(rstate, R_030008_RESOURCE0_WORD2,
450 (tmp->offset[0] + r600_bo_offset(bo[0])) >> 8, 0xFFFFFFFF, bo[0]);
451 r600_pipe_state_add_reg(rstate, R_03000C_RESOURCE0_WORD3,
452 (tmp->offset[1] + r600_bo_offset(bo[1])) >> 8, 0xFFFFFFFF, bo[1]);
453 r600_pipe_state_add_reg(rstate, R_030010_RESOURCE0_WORD4,
454 word4 |
455 S_030010_SRF_MODE_ALL(V_030010_SRF_MODE_ZERO_CLAMP_MINUS_ONE) |
456 S_030010_ENDIAN_SWAP(endian) |
457 S_030010_BASE_LEVEL(state->u.tex.first_level), 0xFFFFFFFF, NULL);
458 r600_pipe_state_add_reg(rstate, R_030014_RESOURCE0_WORD5,
459 S_030014_LAST_LEVEL(state->u.tex.last_level) |
460 S_030014_BASE_ARRAY(0) |
461 S_030014_LAST_ARRAY(0), 0xffffffff, NULL);
462 r600_pipe_state_add_reg(rstate, R_030018_RESOURCE0_WORD6,
463 S_030018_MAX_ANISO(4 /* max 16 samples */),
464 0xFFFFFFFF, NULL);
465 r600_pipe_state_add_reg(rstate, R_03001C_RESOURCE0_WORD7,
466 S_03001C_DATA_FORMAT(format) |
467 S_03001C_TYPE(V_03001C_SQ_TEX_VTX_VALID_TEXTURE), 0xFFFFFFFF, NULL);
468
469 return &resource->base;
470 }
471
472 static void evergreen_set_vs_sampler_view(struct pipe_context *ctx, unsigned count,
473 struct pipe_sampler_view **views)
474 {
475 struct r600_pipe_context *rctx = (struct r600_pipe_context *)ctx;
476 struct r600_pipe_sampler_view **resource = (struct r600_pipe_sampler_view **)views;
477
478 for (int i = 0; i < count; i++) {
479 if (resource[i]) {
480 evergreen_context_pipe_state_set_vs_resource(&rctx->ctx, &resource[i]->state,
481 i + R600_MAX_CONST_BUFFERS);
482 }
483 }
484 }
485
486 static void evergreen_set_ps_sampler_view(struct pipe_context *ctx, unsigned count,
487 struct pipe_sampler_view **views)
488 {
489 struct r600_pipe_context *rctx = (struct r600_pipe_context *)ctx;
490 struct r600_pipe_sampler_view **resource = (struct r600_pipe_sampler_view **)views;
491 int i;
492
493 for (i = 0; i < count; i++) {
494 if (&rctx->ps_samplers.views[i]->base != views[i]) {
495 if (resource[i])
496 evergreen_context_pipe_state_set_ps_resource(&rctx->ctx, &resource[i]->state,
497 i + R600_MAX_CONST_BUFFERS);
498 else
499 evergreen_context_pipe_state_set_ps_resource(&rctx->ctx, NULL,
500 i + R600_MAX_CONST_BUFFERS);
501
502 pipe_sampler_view_reference(
503 (struct pipe_sampler_view **)&rctx->ps_samplers.views[i],
504 views[i]);
505 }
506 }
507 for (i = count; i < NUM_TEX_UNITS; i++) {
508 if (rctx->ps_samplers.views[i]) {
509 evergreen_context_pipe_state_set_ps_resource(&rctx->ctx, NULL,
510 i + R600_MAX_CONST_BUFFERS);
511 pipe_sampler_view_reference((struct pipe_sampler_view **)&rctx->ps_samplers.views[i], NULL);
512 }
513 }
514 rctx->ps_samplers.n_views = count;
515 }
516
517 static void evergreen_bind_ps_sampler(struct pipe_context *ctx, unsigned count, void **states)
518 {
519 struct r600_pipe_context *rctx = (struct r600_pipe_context *)ctx;
520 struct r600_pipe_state **rstates = (struct r600_pipe_state **)states;
521
522
523 memcpy(rctx->ps_samplers.samplers, states, sizeof(void*) * count);
524 rctx->ps_samplers.n_samplers = count;
525
526 for (int i = 0; i < count; i++) {
527 evergreen_context_pipe_state_set_ps_sampler(&rctx->ctx, rstates[i], i);
528 }
529 }
530
531 static void evergreen_bind_vs_sampler(struct pipe_context *ctx, unsigned count, void **states)
532 {
533 struct r600_pipe_context *rctx = (struct r600_pipe_context *)ctx;
534 struct r600_pipe_state **rstates = (struct r600_pipe_state **)states;
535
536 for (int i = 0; i < count; i++) {
537 evergreen_context_pipe_state_set_vs_sampler(&rctx->ctx, rstates[i], i);
538 }
539 }
540
541 static void evergreen_set_clip_state(struct pipe_context *ctx,
542 const struct pipe_clip_state *state)
543 {
544 struct r600_pipe_context *rctx = (struct r600_pipe_context *)ctx;
545 struct r600_pipe_state *rstate = CALLOC_STRUCT(r600_pipe_state);
546
547 if (rstate == NULL)
548 return;
549
550 rctx->clip = *state;
551 rstate->id = R600_PIPE_STATE_CLIP;
552 for (int i = 0; i < state->nr; i++) {
553 r600_pipe_state_add_reg(rstate,
554 R_0285BC_PA_CL_UCP0_X + i * 16,
555 fui(state->ucp[i][0]), 0xFFFFFFFF, NULL);
556 r600_pipe_state_add_reg(rstate,
557 R_0285C0_PA_CL_UCP0_Y + i * 16,
558 fui(state->ucp[i][1]) , 0xFFFFFFFF, NULL);
559 r600_pipe_state_add_reg(rstate,
560 R_0285C4_PA_CL_UCP0_Z + i * 16,
561 fui(state->ucp[i][2]), 0xFFFFFFFF, NULL);
562 r600_pipe_state_add_reg(rstate,
563 R_0285C8_PA_CL_UCP0_W + i * 16,
564 fui(state->ucp[i][3]), 0xFFFFFFFF, NULL);
565 }
566 r600_pipe_state_add_reg(rstate, R_028810_PA_CL_CLIP_CNTL,
567 S_028810_PS_UCP_MODE(3) | ((1 << state->nr) - 1) |
568 S_028810_ZCLIP_NEAR_DISABLE(state->depth_clamp) |
569 S_028810_ZCLIP_FAR_DISABLE(state->depth_clamp), 0xFFFFFFFF, NULL);
570
571 free(rctx->states[R600_PIPE_STATE_CLIP]);
572 rctx->states[R600_PIPE_STATE_CLIP] = rstate;
573 r600_context_pipe_state_set(&rctx->ctx, rstate);
574 }
575
576 static void evergreen_set_polygon_stipple(struct pipe_context *ctx,
577 const struct pipe_poly_stipple *state)
578 {
579 }
580
581 static void evergreen_set_sample_mask(struct pipe_context *pipe, unsigned sample_mask)
582 {
583 }
584
585 static void evergreen_set_scissor_state(struct pipe_context *ctx,
586 const struct pipe_scissor_state *state)
587 {
588 struct r600_pipe_context *rctx = (struct r600_pipe_context *)ctx;
589 struct r600_pipe_state *rstate = CALLOC_STRUCT(r600_pipe_state);
590 u32 tl, br;
591
592 if (rstate == NULL)
593 return;
594
595 rstate->id = R600_PIPE_STATE_SCISSOR;
596 tl = S_028240_TL_X(state->minx) | S_028240_TL_Y(state->miny);
597 br = S_028244_BR_X(state->maxx) | S_028244_BR_Y(state->maxy);
598 r600_pipe_state_add_reg(rstate,
599 R_028210_PA_SC_CLIPRECT_0_TL, tl,
600 0xFFFFFFFF, NULL);
601 r600_pipe_state_add_reg(rstate,
602 R_028214_PA_SC_CLIPRECT_0_BR, br,
603 0xFFFFFFFF, NULL);
604 r600_pipe_state_add_reg(rstate,
605 R_028218_PA_SC_CLIPRECT_1_TL, tl,
606 0xFFFFFFFF, NULL);
607 r600_pipe_state_add_reg(rstate,
608 R_02821C_PA_SC_CLIPRECT_1_BR, br,
609 0xFFFFFFFF, NULL);
610 r600_pipe_state_add_reg(rstate,
611 R_028220_PA_SC_CLIPRECT_2_TL, tl,
612 0xFFFFFFFF, NULL);
613 r600_pipe_state_add_reg(rstate,
614 R_028224_PA_SC_CLIPRECT_2_BR, br,
615 0xFFFFFFFF, NULL);
616 r600_pipe_state_add_reg(rstate,
617 R_028228_PA_SC_CLIPRECT_3_TL, tl,
618 0xFFFFFFFF, NULL);
619 r600_pipe_state_add_reg(rstate,
620 R_02822C_PA_SC_CLIPRECT_3_BR, br,
621 0xFFFFFFFF, NULL);
622
623 free(rctx->states[R600_PIPE_STATE_SCISSOR]);
624 rctx->states[R600_PIPE_STATE_SCISSOR] = rstate;
625 r600_context_pipe_state_set(&rctx->ctx, rstate);
626 }
627
628 static void evergreen_set_stencil_ref(struct pipe_context *ctx,
629 const struct pipe_stencil_ref *state)
630 {
631 struct r600_pipe_context *rctx = (struct r600_pipe_context *)ctx;
632 struct r600_pipe_state *rstate = CALLOC_STRUCT(r600_pipe_state);
633 u32 tmp;
634
635 if (rstate == NULL)
636 return;
637
638 rctx->stencil_ref = *state;
639 rstate->id = R600_PIPE_STATE_STENCIL_REF;
640 tmp = S_028430_STENCILREF(state->ref_value[0]);
641 r600_pipe_state_add_reg(rstate,
642 R_028430_DB_STENCILREFMASK, tmp,
643 ~C_028430_STENCILREF, NULL);
644 tmp = S_028434_STENCILREF_BF(state->ref_value[1]);
645 r600_pipe_state_add_reg(rstate,
646 R_028434_DB_STENCILREFMASK_BF, tmp,
647 ~C_028434_STENCILREF_BF, NULL);
648
649 free(rctx->states[R600_PIPE_STATE_STENCIL_REF]);
650 rctx->states[R600_PIPE_STATE_STENCIL_REF] = rstate;
651 r600_context_pipe_state_set(&rctx->ctx, rstate);
652 }
653
654 static void evergreen_set_viewport_state(struct pipe_context *ctx,
655 const struct pipe_viewport_state *state)
656 {
657 struct r600_pipe_context *rctx = (struct r600_pipe_context *)ctx;
658 struct r600_pipe_state *rstate = CALLOC_STRUCT(r600_pipe_state);
659
660 if (rstate == NULL)
661 return;
662
663 rctx->viewport = *state;
664 rstate->id = R600_PIPE_STATE_VIEWPORT;
665 r600_pipe_state_add_reg(rstate, R_0282D0_PA_SC_VPORT_ZMIN_0, 0x00000000, 0xFFFFFFFF, NULL);
666 r600_pipe_state_add_reg(rstate, R_0282D4_PA_SC_VPORT_ZMAX_0, 0x3F800000, 0xFFFFFFFF, NULL);
667 r600_pipe_state_add_reg(rstate, R_02843C_PA_CL_VPORT_XSCALE_0, fui(state->scale[0]), 0xFFFFFFFF, NULL);
668 r600_pipe_state_add_reg(rstate, R_028444_PA_CL_VPORT_YSCALE_0, fui(state->scale[1]), 0xFFFFFFFF, NULL);
669 r600_pipe_state_add_reg(rstate, R_02844C_PA_CL_VPORT_ZSCALE_0, fui(state->scale[2]), 0xFFFFFFFF, NULL);
670 r600_pipe_state_add_reg(rstate, R_028440_PA_CL_VPORT_XOFFSET_0, fui(state->translate[0]), 0xFFFFFFFF, NULL);
671 r600_pipe_state_add_reg(rstate, R_028448_PA_CL_VPORT_YOFFSET_0, fui(state->translate[1]), 0xFFFFFFFF, NULL);
672 r600_pipe_state_add_reg(rstate, R_028450_PA_CL_VPORT_ZOFFSET_0, fui(state->translate[2]), 0xFFFFFFFF, NULL);
673 r600_pipe_state_add_reg(rstate, R_028818_PA_CL_VTE_CNTL, 0x0000043F, 0xFFFFFFFF, NULL);
674
675 free(rctx->states[R600_PIPE_STATE_VIEWPORT]);
676 rctx->states[R600_PIPE_STATE_VIEWPORT] = rstate;
677 r600_context_pipe_state_set(&rctx->ctx, rstate);
678 }
679
680 static void evergreen_cb(struct r600_pipe_context *rctx, struct r600_pipe_state *rstate,
681 const struct pipe_framebuffer_state *state, int cb)
682 {
683 struct r600_resource_texture *rtex;
684 struct r600_resource *rbuffer;
685 struct r600_surface *surf;
686 unsigned level = state->cbufs[cb]->u.tex.level;
687 unsigned pitch, slice;
688 unsigned color_info;
689 unsigned format, swap, ntype, endian;
690 unsigned offset;
691 unsigned tile_type;
692 const struct util_format_description *desc;
693 struct r600_bo *bo[3];
694 int i;
695
696 surf = (struct r600_surface *)state->cbufs[cb];
697 rtex = (struct r600_resource_texture*)state->cbufs[cb]->texture;
698
699 if (rtex->depth && !rtex->is_flushing_texture) {
700 r600_texture_depth_flush(&rctx->context, state->cbufs[cb]->texture, TRUE);
701 rtex = rtex->flushed_depth_texture;
702 }
703
704 rbuffer = &rtex->resource;
705 bo[0] = rbuffer->bo;
706 bo[1] = rbuffer->bo;
707 bo[2] = rbuffer->bo;
708
709 /* XXX quite sure for dx10+ hw don't need any offset hacks */
710 offset = r600_texture_get_offset((struct r600_resource_texture *)state->cbufs[cb]->texture,
711 level, state->cbufs[cb]->u.tex.first_layer);
712 pitch = rtex->pitch_in_blocks[level] / 8 - 1;
713 slice = rtex->pitch_in_blocks[level] * surf->aligned_height / 64 - 1;
714 desc = util_format_description(surf->base.format);
715 for (i = 0; i < 4; i++) {
716 if (desc->channel[i].type != UTIL_FORMAT_TYPE_VOID) {
717 break;
718 }
719 }
720 ntype = V_028C70_NUMBER_UNORM;
721 if (desc->colorspace == UTIL_FORMAT_COLORSPACE_SRGB)
722 ntype = V_028C70_NUMBER_SRGB;
723 else if (desc->channel[i].type == UTIL_FORMAT_TYPE_SIGNED)
724 ntype = V_028C70_NUMBER_SNORM;
725
726 format = r600_translate_colorformat(surf->base.format);
727 swap = r600_translate_colorswap(surf->base.format);
728 if (rbuffer->b.b.b.usage == PIPE_USAGE_STAGING) {
729 endian = ENDIAN_NONE;
730 } else {
731 endian = r600_colorformat_endian_swap(format);
732 }
733
734 /* disable when gallium grows int textures */
735 if ((format == FMT_32_32_32_32 || format == FMT_16_16_16_16) && rtex->force_int_type)
736 ntype = V_028C70_NUMBER_UINT;
737
738 color_info = S_028C70_FORMAT(format) |
739 S_028C70_COMP_SWAP(swap) |
740 S_028C70_ARRAY_MODE(rtex->array_mode[level]) |
741 S_028C70_BLEND_CLAMP(1) |
742 S_028C70_NUMBER_TYPE(ntype) |
743 S_028C70_ENDIAN(endian);
744
745
746 /* EXPORT_NORM is an optimzation that can be enabled for better
747 * performance in certain cases.
748 * EXPORT_NORM can be enabled if:
749 * - 11-bit or smaller UNORM/SNORM/SRGB
750 * - 16-bit or smaller FLOAT
751 */
752 /* FIXME: This should probably be the same for all CBs if we want
753 * useful alpha tests. */
754 if (desc->colorspace != UTIL_FORMAT_COLORSPACE_ZS &&
755 ((desc->channel[i].size < 12 &&
756 desc->channel[i].type != UTIL_FORMAT_TYPE_FLOAT &&
757 ntype != V_028C70_NUMBER_UINT && ntype != V_028C70_NUMBER_SINT) ||
758 (desc->channel[i].size < 17 &&
759 desc->channel[i].type == UTIL_FORMAT_TYPE_FLOAT))) {
760 color_info |= S_028C70_SOURCE_FORMAT(V_028C70_EXPORT_4C_16BPC);
761 rctx->export_16bpc = true;
762 } else {
763 rctx->export_16bpc = false;
764 }
765 rctx->alpha_ref_dirty = true;
766
767 if (rtex->array_mode[level] > V_028C70_ARRAY_LINEAR_ALIGNED) {
768 tile_type = rtex->tile_type;
769 } else /* workaround for linear buffers */
770 tile_type = 1;
771
772 /* FIXME handle enabling of CB beyond BASE8 which has different offset */
773 r600_pipe_state_add_reg(rstate,
774 R_028C60_CB_COLOR0_BASE + cb * 0x3C,
775 (offset + r600_bo_offset(bo[0])) >> 8, 0xFFFFFFFF, bo[0]);
776 r600_pipe_state_add_reg(rstate,
777 R_028C78_CB_COLOR0_DIM + cb * 0x3C,
778 0x0, 0xFFFFFFFF, NULL);
779 r600_pipe_state_add_reg(rstate,
780 R_028C70_CB_COLOR0_INFO + cb * 0x3C,
781 color_info, 0xFFFFFFFF, bo[0]);
782 r600_pipe_state_add_reg(rstate,
783 R_028C64_CB_COLOR0_PITCH + cb * 0x3C,
784 S_028C64_PITCH_TILE_MAX(pitch),
785 0xFFFFFFFF, NULL);
786 r600_pipe_state_add_reg(rstate,
787 R_028C68_CB_COLOR0_SLICE + cb * 0x3C,
788 S_028C68_SLICE_TILE_MAX(slice),
789 0xFFFFFFFF, NULL);
790 r600_pipe_state_add_reg(rstate,
791 R_028C6C_CB_COLOR0_VIEW + cb * 0x3C,
792 0x00000000, 0xFFFFFFFF, NULL);
793 r600_pipe_state_add_reg(rstate,
794 R_028C74_CB_COLOR0_ATTRIB + cb * 0x3C,
795 S_028C74_NON_DISP_TILING_ORDER(tile_type),
796 0xFFFFFFFF, bo[0]);
797 }
798
799 static void evergreen_db(struct r600_pipe_context *rctx, struct r600_pipe_state *rstate,
800 const struct pipe_framebuffer_state *state)
801 {
802 struct r600_resource_texture *rtex;
803 struct r600_resource *rbuffer;
804 struct r600_surface *surf;
805 unsigned level;
806 unsigned pitch, slice, format, stencil_format;
807 unsigned offset;
808
809 if (state->zsbuf == NULL)
810 return;
811
812 level = state->zsbuf->u.tex.level;
813
814 surf = (struct r600_surface *)state->zsbuf;
815 rtex = (struct r600_resource_texture*)state->zsbuf->texture;
816
817 rbuffer = &rtex->resource;
818
819 /* XXX quite sure for dx10+ hw don't need any offset hacks */
820 offset = r600_texture_get_offset((struct r600_resource_texture *)state->zsbuf->texture,
821 level, state->zsbuf->u.tex.first_layer);
822 pitch = rtex->pitch_in_blocks[level] / 8 - 1;
823 slice = rtex->pitch_in_blocks[level] * surf->aligned_height / 64 - 1;
824 format = r600_translate_dbformat(state->zsbuf->texture->format);
825 stencil_format = r600_translate_stencilformat(state->zsbuf->texture->format);
826
827 r600_pipe_state_add_reg(rstate, R_028048_DB_Z_READ_BASE,
828 (offset + r600_bo_offset(rbuffer->bo)) >> 8, 0xFFFFFFFF, rbuffer->bo);
829 r600_pipe_state_add_reg(rstate, R_028050_DB_Z_WRITE_BASE,
830 (offset + r600_bo_offset(rbuffer->bo)) >> 8, 0xFFFFFFFF, rbuffer->bo);
831
832 if (stencil_format) {
833 uint32_t stencil_offset;
834
835 stencil_offset = ((surf->aligned_height * rtex->pitch_in_bytes[level]) + 255) & ~255;
836 r600_pipe_state_add_reg(rstate, R_02804C_DB_STENCIL_READ_BASE,
837 (offset + stencil_offset + r600_bo_offset(rbuffer->bo)) >> 8, 0xFFFFFFFF, rbuffer->bo);
838 r600_pipe_state_add_reg(rstate, R_028054_DB_STENCIL_WRITE_BASE,
839 (offset + stencil_offset + r600_bo_offset(rbuffer->bo)) >> 8, 0xFFFFFFFF, rbuffer->bo);
840 }
841
842 r600_pipe_state_add_reg(rstate, R_028008_DB_DEPTH_VIEW, 0x00000000, 0xFFFFFFFF, NULL);
843 r600_pipe_state_add_reg(rstate, R_028044_DB_STENCIL_INFO,
844 S_028044_FORMAT(stencil_format), 0xFFFFFFFF, rbuffer->bo);
845
846 r600_pipe_state_add_reg(rstate, R_028040_DB_Z_INFO,
847 S_028040_ARRAY_MODE(rtex->array_mode[level]) | S_028040_FORMAT(format),
848 0xFFFFFFFF, rbuffer->bo);
849 r600_pipe_state_add_reg(rstate, R_028058_DB_DEPTH_SIZE,
850 S_028058_PITCH_TILE_MAX(pitch),
851 0xFFFFFFFF, NULL);
852 r600_pipe_state_add_reg(rstate, R_02805C_DB_DEPTH_SLICE,
853 S_02805C_SLICE_TILE_MAX(slice),
854 0xFFFFFFFF, NULL);
855 }
856
857 static void evergreen_set_framebuffer_state(struct pipe_context *ctx,
858 const struct pipe_framebuffer_state *state)
859 {
860 struct r600_pipe_context *rctx = (struct r600_pipe_context *)ctx;
861 struct r600_pipe_state *rstate = CALLOC_STRUCT(r600_pipe_state);
862 u32 shader_mask, tl, br, target_mask;
863 enum radeon_family family;
864 int tl_x, tl_y, br_x, br_y;
865
866 if (rstate == NULL)
867 return;
868
869 family = r600_get_family(rctx->radeon);
870
871 evergreen_context_flush_dest_caches(&rctx->ctx);
872 rctx->ctx.num_dest_buffers = state->nr_cbufs;
873
874 /* unreference old buffer and reference new one */
875 rstate->id = R600_PIPE_STATE_FRAMEBUFFER;
876
877 util_copy_framebuffer_state(&rctx->framebuffer, state);
878
879 /* build states */
880 for (int i = 0; i < state->nr_cbufs; i++) {
881 evergreen_cb(rctx, rstate, state, i);
882 }
883 if (state->zsbuf) {
884 evergreen_db(rctx, rstate, state);
885 rctx->ctx.num_dest_buffers++;
886 }
887
888 target_mask = 0x00000000;
889 target_mask = 0xFFFFFFFF;
890 shader_mask = 0;
891 for (int i = 0; i < state->nr_cbufs; i++) {
892 target_mask ^= 0xf << (i * 4);
893 shader_mask |= 0xf << (i * 4);
894 }
895 tl_x = 0;
896 tl_y = 0;
897 br_x = state->width;
898 br_y = state->height;
899 /* EG hw workaround */
900 if (br_x == 0)
901 tl_x = 1;
902 if (br_y == 0)
903 tl_y = 1;
904 /* cayman hw workaround */
905 if (family == CHIP_CAYMAN) {
906 if (br_x == 1 && br_y == 1)
907 br_x = 2;
908 }
909 tl = S_028240_TL_X(tl_x) | S_028240_TL_Y(tl_y);
910 br = S_028244_BR_X(br_x) | S_028244_BR_Y(br_y);
911
912 r600_pipe_state_add_reg(rstate,
913 R_028240_PA_SC_GENERIC_SCISSOR_TL, tl,
914 0xFFFFFFFF, NULL);
915 r600_pipe_state_add_reg(rstate,
916 R_028244_PA_SC_GENERIC_SCISSOR_BR, br,
917 0xFFFFFFFF, NULL);
918 r600_pipe_state_add_reg(rstate,
919 R_028250_PA_SC_VPORT_SCISSOR_0_TL, tl,
920 0xFFFFFFFF, NULL);
921 r600_pipe_state_add_reg(rstate,
922 R_028254_PA_SC_VPORT_SCISSOR_0_BR, br,
923 0xFFFFFFFF, NULL);
924 r600_pipe_state_add_reg(rstate,
925 R_028030_PA_SC_SCREEN_SCISSOR_TL, tl,
926 0xFFFFFFFF, NULL);
927 r600_pipe_state_add_reg(rstate,
928 R_028034_PA_SC_SCREEN_SCISSOR_BR, br,
929 0xFFFFFFFF, NULL);
930 r600_pipe_state_add_reg(rstate,
931 R_028204_PA_SC_WINDOW_SCISSOR_TL, tl,
932 0xFFFFFFFF, NULL);
933 r600_pipe_state_add_reg(rstate,
934 R_028208_PA_SC_WINDOW_SCISSOR_BR, br,
935 0xFFFFFFFF, NULL);
936 r600_pipe_state_add_reg(rstate,
937 R_028200_PA_SC_WINDOW_OFFSET, 0x00000000,
938 0xFFFFFFFF, NULL);
939 r600_pipe_state_add_reg(rstate,
940 R_028230_PA_SC_EDGERULE, 0xAAAAAAAA,
941 0xFFFFFFFF, NULL);
942
943 r600_pipe_state_add_reg(rstate, R_028238_CB_TARGET_MASK,
944 0x00000000, target_mask, NULL);
945 r600_pipe_state_add_reg(rstate, R_02823C_CB_SHADER_MASK,
946 shader_mask, 0xFFFFFFFF, NULL);
947
948
949 if (family == CHIP_CAYMAN) {
950 r600_pipe_state_add_reg(rstate, CM_R_028BE0_PA_SC_AA_CONFIG,
951 0x00000000, 0xFFFFFFFF, NULL);
952 } else {
953 r600_pipe_state_add_reg(rstate, R_028C04_PA_SC_AA_CONFIG,
954 0x00000000, 0xFFFFFFFF, NULL);
955 r600_pipe_state_add_reg(rstate, R_028C1C_PA_SC_AA_SAMPLE_LOCS_MCTX,
956 0x00000000, 0xFFFFFFFF, NULL);
957 }
958
959 free(rctx->states[R600_PIPE_STATE_FRAMEBUFFER]);
960 rctx->states[R600_PIPE_STATE_FRAMEBUFFER] = rstate;
961 r600_context_pipe_state_set(&rctx->ctx, rstate);
962
963 if (state->zsbuf) {
964 evergreen_polygon_offset_update(rctx);
965 }
966 }
967
968 static void evergreen_texture_barrier(struct pipe_context *ctx)
969 {
970 struct r600_pipe_context *rctx = (struct r600_pipe_context *)ctx;
971
972 r600_context_flush_all(&rctx->ctx, S_0085F0_TC_ACTION_ENA(1) | S_0085F0_CB_ACTION_ENA(1) |
973 S_0085F0_CB0_DEST_BASE_ENA(1) | S_0085F0_CB1_DEST_BASE_ENA(1) |
974 S_0085F0_CB2_DEST_BASE_ENA(1) | S_0085F0_CB3_DEST_BASE_ENA(1) |
975 S_0085F0_CB4_DEST_BASE_ENA(1) | S_0085F0_CB5_DEST_BASE_ENA(1) |
976 S_0085F0_CB6_DEST_BASE_ENA(1) | S_0085F0_CB7_DEST_BASE_ENA(1) |
977 S_0085F0_CB8_DEST_BASE_ENA(1) | S_0085F0_CB9_DEST_BASE_ENA(1) |
978 S_0085F0_CB10_DEST_BASE_ENA(1) | S_0085F0_CB11_DEST_BASE_ENA(1));
979 }
980
981 void evergreen_init_state_functions(struct r600_pipe_context *rctx)
982 {
983 rctx->context.create_blend_state = evergreen_create_blend_state;
984 rctx->context.create_depth_stencil_alpha_state = evergreen_create_dsa_state;
985 rctx->context.create_fs_state = r600_create_shader_state;
986 rctx->context.create_rasterizer_state = evergreen_create_rs_state;
987 rctx->context.create_sampler_state = evergreen_create_sampler_state;
988 rctx->context.create_sampler_view = evergreen_create_sampler_view;
989 rctx->context.create_vertex_elements_state = r600_create_vertex_elements;
990 rctx->context.create_vs_state = r600_create_shader_state;
991 rctx->context.bind_blend_state = r600_bind_blend_state;
992 rctx->context.bind_depth_stencil_alpha_state = r600_bind_dsa_state;
993 rctx->context.bind_fragment_sampler_states = evergreen_bind_ps_sampler;
994 rctx->context.bind_fs_state = r600_bind_ps_shader;
995 rctx->context.bind_rasterizer_state = r600_bind_rs_state;
996 rctx->context.bind_vertex_elements_state = r600_bind_vertex_elements;
997 rctx->context.bind_vertex_sampler_states = evergreen_bind_vs_sampler;
998 rctx->context.bind_vs_state = r600_bind_vs_shader;
999 rctx->context.delete_blend_state = r600_delete_state;
1000 rctx->context.delete_depth_stencil_alpha_state = r600_delete_state;
1001 rctx->context.delete_fs_state = r600_delete_ps_shader;
1002 rctx->context.delete_rasterizer_state = r600_delete_rs_state;
1003 rctx->context.delete_sampler_state = r600_delete_state;
1004 rctx->context.delete_vertex_elements_state = r600_delete_vertex_element;
1005 rctx->context.delete_vs_state = r600_delete_vs_shader;
1006 rctx->context.set_blend_color = evergreen_set_blend_color;
1007 rctx->context.set_clip_state = evergreen_set_clip_state;
1008 rctx->context.set_constant_buffer = r600_set_constant_buffer;
1009 rctx->context.set_fragment_sampler_views = evergreen_set_ps_sampler_view;
1010 rctx->context.set_framebuffer_state = evergreen_set_framebuffer_state;
1011 rctx->context.set_polygon_stipple = evergreen_set_polygon_stipple;
1012 rctx->context.set_sample_mask = evergreen_set_sample_mask;
1013 rctx->context.set_scissor_state = evergreen_set_scissor_state;
1014 rctx->context.set_stencil_ref = evergreen_set_stencil_ref;
1015 rctx->context.set_vertex_buffers = r600_set_vertex_buffers;
1016 rctx->context.set_index_buffer = r600_set_index_buffer;
1017 rctx->context.set_vertex_sampler_views = evergreen_set_vs_sampler_view;
1018 rctx->context.set_viewport_state = evergreen_set_viewport_state;
1019 rctx->context.sampler_view_destroy = r600_sampler_view_destroy;
1020 rctx->context.redefine_user_buffer = u_default_redefine_user_buffer;
1021 rctx->context.texture_barrier = evergreen_texture_barrier;
1022 }
1023
1024 static void cayman_init_config(struct r600_pipe_context *rctx)
1025 {
1026 struct r600_pipe_state *rstate = &rctx->config;
1027 unsigned tmp;
1028
1029 tmp = 0x00000000;
1030 tmp |= S_008C00_EXPORT_SRC_C(1);
1031 r600_pipe_state_add_reg(rstate, R_008C00_SQ_CONFIG, tmp, 0xFFFFFFFF, NULL);
1032
1033 r600_pipe_state_add_reg(rstate, CM_R_008C10_SQ_GLOBAL_GPR_RESOURCE_MGMT_1, (4 << 28), 0xFFFFFFFF, NULL);
1034 r600_pipe_state_add_reg(rstate, R_008D8C_SQ_DYN_GPR_CNTL_PS_FLUSH_REQ, (1 << 8), 0xFFFFFFFF, NULL);
1035
1036 r600_pipe_state_add_reg(rstate, R_028A48_PA_SC_MODE_CNTL_0, 0x0, 0xFFFFFFFF, NULL);
1037 r600_pipe_state_add_reg(rstate, R_028A4C_PA_SC_MODE_CNTL_1, 0x0, 0xFFFFFFFF, NULL);
1038
1039 r600_pipe_state_add_reg(rstate, R_028A10_VGT_OUTPUT_PATH_CNTL, 0x0, 0xFFFFFFFF, NULL);
1040 r600_pipe_state_add_reg(rstate, R_028A14_VGT_HOS_CNTL, 0x0, 0xFFFFFFFF, NULL);
1041 r600_pipe_state_add_reg(rstate, R_028A18_VGT_HOS_MAX_TESS_LEVEL, 0x0, 0xFFFFFFFF, NULL);
1042 r600_pipe_state_add_reg(rstate, R_028A1C_VGT_HOS_MIN_TESS_LEVEL, 0x0, 0xFFFFFFFF, NULL);
1043 r600_pipe_state_add_reg(rstate, R_028A20_VGT_HOS_REUSE_DEPTH, 0x0, 0xFFFFFFFF, NULL);
1044 r600_pipe_state_add_reg(rstate, R_028A24_VGT_GROUP_PRIM_TYPE, 0x0, 0xFFFFFFFF, NULL);
1045 r600_pipe_state_add_reg(rstate, R_028A28_VGT_GROUP_FIRST_DECR, 0x0, 0xFFFFFFFF, NULL);
1046 r600_pipe_state_add_reg(rstate, R_028A2C_VGT_GROUP_DECR, 0x0, 0xFFFFFFFF, NULL);
1047 r600_pipe_state_add_reg(rstate, R_028A30_VGT_GROUP_VECT_0_CNTL, 0x0, 0xFFFFFFFF, NULL);
1048 r600_pipe_state_add_reg(rstate, R_028A34_VGT_GROUP_VECT_1_CNTL, 0x0, 0xFFFFFFFF, NULL);
1049 r600_pipe_state_add_reg(rstate, R_028A38_VGT_GROUP_VECT_0_FMT_CNTL, 0x0, 0xFFFFFFFF, NULL);
1050 r600_pipe_state_add_reg(rstate, R_028A3C_VGT_GROUP_VECT_1_FMT_CNTL, 0x0, 0xFFFFFFFF, NULL);
1051 r600_pipe_state_add_reg(rstate, R_028A40_VGT_GS_MODE, 0x0, 0xFFFFFFFF, NULL);
1052 r600_pipe_state_add_reg(rstate, R_028B94_VGT_STRMOUT_CONFIG, 0x0, 0xFFFFFFFF, NULL);
1053 r600_pipe_state_add_reg(rstate, R_028B98_VGT_STRMOUT_BUFFER_CONFIG, 0x0, 0xFFFFFFFF, NULL);
1054 r600_pipe_state_add_reg(rstate, R_028AB4_VGT_REUSE_OFF, 0x00000000, 0xFFFFFFFF, NULL);
1055 r600_pipe_state_add_reg(rstate, R_028AB8_VGT_VTX_CNT_EN, 0x0, 0xFFFFFFFF, NULL);
1056 r600_pipe_state_add_reg(rstate, R_008A14_PA_CL_ENHANCE, (3 << 1) | 1, 0xFFFFFFFF, NULL);
1057
1058 r600_pipe_state_add_reg(rstate, R_028380_SQ_VTX_SEMANTIC_0, 0x0, 0xFFFFFFFF, NULL);
1059 r600_pipe_state_add_reg(rstate, R_028384_SQ_VTX_SEMANTIC_1, 0x0, 0xFFFFFFFF, NULL);
1060 r600_pipe_state_add_reg(rstate, R_028388_SQ_VTX_SEMANTIC_2, 0x0, 0xFFFFFFFF, NULL);
1061 r600_pipe_state_add_reg(rstate, R_02838C_SQ_VTX_SEMANTIC_3, 0x0, 0xFFFFFFFF, NULL);
1062 r600_pipe_state_add_reg(rstate, R_028390_SQ_VTX_SEMANTIC_4, 0x0, 0xFFFFFFFF, NULL);
1063 r600_pipe_state_add_reg(rstate, R_028394_SQ_VTX_SEMANTIC_5, 0x0, 0xFFFFFFFF, NULL);
1064 r600_pipe_state_add_reg(rstate, R_028398_SQ_VTX_SEMANTIC_6, 0x0, 0xFFFFFFFF, NULL);
1065 r600_pipe_state_add_reg(rstate, R_02839C_SQ_VTX_SEMANTIC_7, 0x0, 0xFFFFFFFF, NULL);
1066 r600_pipe_state_add_reg(rstate, R_0283A0_SQ_VTX_SEMANTIC_8, 0x0, 0xFFFFFFFF, NULL);
1067 r600_pipe_state_add_reg(rstate, R_0283A4_SQ_VTX_SEMANTIC_9, 0x0, 0xFFFFFFFF, NULL);
1068 r600_pipe_state_add_reg(rstate, R_0283A8_SQ_VTX_SEMANTIC_10, 0x0, 0xFFFFFFFF, NULL);
1069 r600_pipe_state_add_reg(rstate, R_0283AC_SQ_VTX_SEMANTIC_11, 0x0, 0xFFFFFFFF, NULL);
1070 r600_pipe_state_add_reg(rstate, R_0283B0_SQ_VTX_SEMANTIC_12, 0x0, 0xFFFFFFFF, NULL);
1071 r600_pipe_state_add_reg(rstate, R_0283B4_SQ_VTX_SEMANTIC_13, 0x0, 0xFFFFFFFF, NULL);
1072 r600_pipe_state_add_reg(rstate, R_0283B8_SQ_VTX_SEMANTIC_14, 0x0, 0xFFFFFFFF, NULL);
1073 r600_pipe_state_add_reg(rstate, R_0283BC_SQ_VTX_SEMANTIC_15, 0x0, 0xFFFFFFFF, NULL);
1074 r600_pipe_state_add_reg(rstate, R_0283C0_SQ_VTX_SEMANTIC_16, 0x0, 0xFFFFFFFF, NULL);
1075 r600_pipe_state_add_reg(rstate, R_0283C4_SQ_VTX_SEMANTIC_17, 0x0, 0xFFFFFFFF, NULL);
1076 r600_pipe_state_add_reg(rstate, R_0283C8_SQ_VTX_SEMANTIC_18, 0x0, 0xFFFFFFFF, NULL);
1077 r600_pipe_state_add_reg(rstate, R_0283CC_SQ_VTX_SEMANTIC_19, 0x0, 0xFFFFFFFF, NULL);
1078 r600_pipe_state_add_reg(rstate, R_0283D0_SQ_VTX_SEMANTIC_20, 0x0, 0xFFFFFFFF, NULL);
1079 r600_pipe_state_add_reg(rstate, R_0283D4_SQ_VTX_SEMANTIC_21, 0x0, 0xFFFFFFFF, NULL);
1080 r600_pipe_state_add_reg(rstate, R_0283D8_SQ_VTX_SEMANTIC_22, 0x0, 0xFFFFFFFF, NULL);
1081 r600_pipe_state_add_reg(rstate, R_0283DC_SQ_VTX_SEMANTIC_23, 0x0, 0xFFFFFFFF, NULL);
1082 r600_pipe_state_add_reg(rstate, R_0283E0_SQ_VTX_SEMANTIC_24, 0x0, 0xFFFFFFFF, NULL);
1083 r600_pipe_state_add_reg(rstate, R_0283E4_SQ_VTX_SEMANTIC_25, 0x0, 0xFFFFFFFF, NULL);
1084 r600_pipe_state_add_reg(rstate, R_0283E8_SQ_VTX_SEMANTIC_26, 0x0, 0xFFFFFFFF, NULL);
1085 r600_pipe_state_add_reg(rstate, R_0283EC_SQ_VTX_SEMANTIC_27, 0x0, 0xFFFFFFFF, NULL);
1086 r600_pipe_state_add_reg(rstate, R_0283F0_SQ_VTX_SEMANTIC_28, 0x0, 0xFFFFFFFF, NULL);
1087 r600_pipe_state_add_reg(rstate, R_0283F4_SQ_VTX_SEMANTIC_29, 0x0, 0xFFFFFFFF, NULL);
1088 r600_pipe_state_add_reg(rstate, R_0283F8_SQ_VTX_SEMANTIC_30, 0x0, 0xFFFFFFFF, NULL);
1089 r600_pipe_state_add_reg(rstate, R_0283FC_SQ_VTX_SEMANTIC_31, 0x0, 0xFFFFFFFF, NULL);
1090
1091 r600_pipe_state_add_reg(rstate, R_028810_PA_CL_CLIP_CNTL, 0x0, 0xFFFFFFFF, NULL);
1092
1093 r600_pipe_state_add_reg(rstate, CM_R_028BD4_PA_SC_CENTROID_PRIORITY_0, 0x76543210, 0xffffffff, 0);
1094 r600_pipe_state_add_reg(rstate, CM_R_028BD8_PA_SC_CENTROID_PRIORITY_1, 0xfedcba98, 0xffffffff, 0);
1095
1096 r600_pipe_state_add_reg(rstate, CM_R_0288E8_SQ_LDS_ALLOC, 0, 0xffffffff, NULL);
1097 r600_pipe_state_add_reg(rstate, R_0288EC_SQ_LDS_ALLOC_PS, 0, 0xffffffff, NULL);
1098
1099 r600_pipe_state_add_reg(rstate, CM_R_028804_DB_EQAA, 0x110000, 0xffffffff, NULL);
1100 r600_context_pipe_state_set(&rctx->ctx, rstate);
1101 }
1102
1103 void evergreen_init_config(struct r600_pipe_context *rctx)
1104 {
1105 struct r600_pipe_state *rstate = &rctx->config;
1106 int ps_prio;
1107 int vs_prio;
1108 int gs_prio;
1109 int es_prio;
1110 int hs_prio, cs_prio, ls_prio;
1111 int num_ps_gprs;
1112 int num_vs_gprs;
1113 int num_gs_gprs;
1114 int num_es_gprs;
1115 int num_hs_gprs;
1116 int num_ls_gprs;
1117 int num_temp_gprs;
1118 int num_ps_threads;
1119 int num_vs_threads;
1120 int num_gs_threads;
1121 int num_es_threads;
1122 int num_hs_threads;
1123 int num_ls_threads;
1124 int num_ps_stack_entries;
1125 int num_vs_stack_entries;
1126 int num_gs_stack_entries;
1127 int num_es_stack_entries;
1128 int num_hs_stack_entries;
1129 int num_ls_stack_entries;
1130 enum radeon_family family;
1131 unsigned tmp;
1132
1133 family = r600_get_family(rctx->radeon);
1134
1135 if (family == CHIP_CAYMAN) {
1136 cayman_init_config(rctx);
1137 return;
1138 }
1139
1140 ps_prio = 0;
1141 vs_prio = 1;
1142 gs_prio = 2;
1143 es_prio = 3;
1144 hs_prio = 0;
1145 ls_prio = 0;
1146 cs_prio = 0;
1147
1148 switch (family) {
1149 case CHIP_CEDAR:
1150 default:
1151 num_ps_gprs = 93;
1152 num_vs_gprs = 46;
1153 num_temp_gprs = 4;
1154 num_gs_gprs = 31;
1155 num_es_gprs = 31;
1156 num_hs_gprs = 23;
1157 num_ls_gprs = 23;
1158 num_ps_threads = 96;
1159 num_vs_threads = 16;
1160 num_gs_threads = 16;
1161 num_es_threads = 16;
1162 num_hs_threads = 16;
1163 num_ls_threads = 16;
1164 num_ps_stack_entries = 42;
1165 num_vs_stack_entries = 42;
1166 num_gs_stack_entries = 42;
1167 num_es_stack_entries = 42;
1168 num_hs_stack_entries = 42;
1169 num_ls_stack_entries = 42;
1170 break;
1171 case CHIP_REDWOOD:
1172 num_ps_gprs = 93;
1173 num_vs_gprs = 46;
1174 num_temp_gprs = 4;
1175 num_gs_gprs = 31;
1176 num_es_gprs = 31;
1177 num_hs_gprs = 23;
1178 num_ls_gprs = 23;
1179 num_ps_threads = 128;
1180 num_vs_threads = 20;
1181 num_gs_threads = 20;
1182 num_es_threads = 20;
1183 num_hs_threads = 20;
1184 num_ls_threads = 20;
1185 num_ps_stack_entries = 42;
1186 num_vs_stack_entries = 42;
1187 num_gs_stack_entries = 42;
1188 num_es_stack_entries = 42;
1189 num_hs_stack_entries = 42;
1190 num_ls_stack_entries = 42;
1191 break;
1192 case CHIP_JUNIPER:
1193 num_ps_gprs = 93;
1194 num_vs_gprs = 46;
1195 num_temp_gprs = 4;
1196 num_gs_gprs = 31;
1197 num_es_gprs = 31;
1198 num_hs_gprs = 23;
1199 num_ls_gprs = 23;
1200 num_ps_threads = 128;
1201 num_vs_threads = 20;
1202 num_gs_threads = 20;
1203 num_es_threads = 20;
1204 num_hs_threads = 20;
1205 num_ls_threads = 20;
1206 num_ps_stack_entries = 85;
1207 num_vs_stack_entries = 85;
1208 num_gs_stack_entries = 85;
1209 num_es_stack_entries = 85;
1210 num_hs_stack_entries = 85;
1211 num_ls_stack_entries = 85;
1212 break;
1213 case CHIP_CYPRESS:
1214 case CHIP_HEMLOCK:
1215 num_ps_gprs = 93;
1216 num_vs_gprs = 46;
1217 num_temp_gprs = 4;
1218 num_gs_gprs = 31;
1219 num_es_gprs = 31;
1220 num_hs_gprs = 23;
1221 num_ls_gprs = 23;
1222 num_ps_threads = 128;
1223 num_vs_threads = 20;
1224 num_gs_threads = 20;
1225 num_es_threads = 20;
1226 num_hs_threads = 20;
1227 num_ls_threads = 20;
1228 num_ps_stack_entries = 85;
1229 num_vs_stack_entries = 85;
1230 num_gs_stack_entries = 85;
1231 num_es_stack_entries = 85;
1232 num_hs_stack_entries = 85;
1233 num_ls_stack_entries = 85;
1234 break;
1235 case CHIP_PALM:
1236 num_ps_gprs = 93;
1237 num_vs_gprs = 46;
1238 num_temp_gprs = 4;
1239 num_gs_gprs = 31;
1240 num_es_gprs = 31;
1241 num_hs_gprs = 23;
1242 num_ls_gprs = 23;
1243 num_ps_threads = 96;
1244 num_vs_threads = 16;
1245 num_gs_threads = 16;
1246 num_es_threads = 16;
1247 num_hs_threads = 16;
1248 num_ls_threads = 16;
1249 num_ps_stack_entries = 42;
1250 num_vs_stack_entries = 42;
1251 num_gs_stack_entries = 42;
1252 num_es_stack_entries = 42;
1253 num_hs_stack_entries = 42;
1254 num_ls_stack_entries = 42;
1255 break;
1256 case CHIP_BARTS:
1257 num_ps_gprs = 93;
1258 num_vs_gprs = 46;
1259 num_temp_gprs = 4;
1260 num_gs_gprs = 31;
1261 num_es_gprs = 31;
1262 num_hs_gprs = 23;
1263 num_ls_gprs = 23;
1264 num_ps_threads = 128;
1265 num_vs_threads = 20;
1266 num_gs_threads = 20;
1267 num_es_threads = 20;
1268 num_hs_threads = 20;
1269 num_ls_threads = 20;
1270 num_ps_stack_entries = 85;
1271 num_vs_stack_entries = 85;
1272 num_gs_stack_entries = 85;
1273 num_es_stack_entries = 85;
1274 num_hs_stack_entries = 85;
1275 num_ls_stack_entries = 85;
1276 break;
1277 case CHIP_TURKS:
1278 num_ps_gprs = 93;
1279 num_vs_gprs = 46;
1280 num_temp_gprs = 4;
1281 num_gs_gprs = 31;
1282 num_es_gprs = 31;
1283 num_hs_gprs = 23;
1284 num_ls_gprs = 23;
1285 num_ps_threads = 128;
1286 num_vs_threads = 20;
1287 num_gs_threads = 20;
1288 num_es_threads = 20;
1289 num_hs_threads = 20;
1290 num_ls_threads = 20;
1291 num_ps_stack_entries = 42;
1292 num_vs_stack_entries = 42;
1293 num_gs_stack_entries = 42;
1294 num_es_stack_entries = 42;
1295 num_hs_stack_entries = 42;
1296 num_ls_stack_entries = 42;
1297 break;
1298 case CHIP_CAICOS:
1299 num_ps_gprs = 93;
1300 num_vs_gprs = 46;
1301 num_temp_gprs = 4;
1302 num_gs_gprs = 31;
1303 num_es_gprs = 31;
1304 num_hs_gprs = 23;
1305 num_ls_gprs = 23;
1306 num_ps_threads = 128;
1307 num_vs_threads = 10;
1308 num_gs_threads = 10;
1309 num_es_threads = 10;
1310 num_hs_threads = 10;
1311 num_ls_threads = 10;
1312 num_ps_stack_entries = 42;
1313 num_vs_stack_entries = 42;
1314 num_gs_stack_entries = 42;
1315 num_es_stack_entries = 42;
1316 num_hs_stack_entries = 42;
1317 num_ls_stack_entries = 42;
1318 break;
1319 }
1320
1321 tmp = 0x00000000;
1322 switch (family) {
1323 case CHIP_CEDAR:
1324 case CHIP_PALM:
1325 case CHIP_CAICOS:
1326 break;
1327 default:
1328 tmp |= S_008C00_VC_ENABLE(1);
1329 break;
1330 }
1331 tmp |= S_008C00_EXPORT_SRC_C(1);
1332 tmp |= S_008C00_CS_PRIO(cs_prio);
1333 tmp |= S_008C00_LS_PRIO(ls_prio);
1334 tmp |= S_008C00_HS_PRIO(hs_prio);
1335 tmp |= S_008C00_PS_PRIO(ps_prio);
1336 tmp |= S_008C00_VS_PRIO(vs_prio);
1337 tmp |= S_008C00_GS_PRIO(gs_prio);
1338 tmp |= S_008C00_ES_PRIO(es_prio);
1339 r600_pipe_state_add_reg(rstate, R_008C00_SQ_CONFIG, tmp, 0xFFFFFFFF, NULL);
1340
1341 tmp = 0;
1342 tmp |= S_008C04_NUM_PS_GPRS(num_ps_gprs);
1343 tmp |= S_008C04_NUM_VS_GPRS(num_vs_gprs);
1344 tmp |= S_008C04_NUM_CLAUSE_TEMP_GPRS(num_temp_gprs);
1345 r600_pipe_state_add_reg(rstate, R_008C04_SQ_GPR_RESOURCE_MGMT_1, tmp, 0xFFFFFFFF, NULL);
1346
1347 tmp = 0;
1348 tmp |= S_008C08_NUM_GS_GPRS(num_gs_gprs);
1349 tmp |= S_008C08_NUM_ES_GPRS(num_es_gprs);
1350 r600_pipe_state_add_reg(rstate, R_008C08_SQ_GPR_RESOURCE_MGMT_2, tmp, 0xFFFFFFFF, NULL);
1351
1352 tmp = 0;
1353 tmp |= S_008C0C_NUM_HS_GPRS(num_hs_gprs);
1354 tmp |= S_008C0C_NUM_LS_GPRS(num_ls_gprs);
1355 r600_pipe_state_add_reg(rstate, R_008C0C_SQ_GPR_RESOURCE_MGMT_3, tmp, 0xFFFFFFFF, NULL);
1356
1357 tmp = 0;
1358 tmp |= S_008C18_NUM_PS_THREADS(num_ps_threads);
1359 tmp |= S_008C18_NUM_VS_THREADS(num_vs_threads);
1360 tmp |= S_008C18_NUM_GS_THREADS(num_gs_threads);
1361 tmp |= S_008C18_NUM_ES_THREADS(num_es_threads);
1362 r600_pipe_state_add_reg(rstate, R_008C18_SQ_THREAD_RESOURCE_MGMT_1, tmp, 0xFFFFFFFF, NULL);
1363
1364 tmp = 0;
1365 tmp |= S_008C1C_NUM_HS_THREADS(num_hs_threads);
1366 tmp |= S_008C1C_NUM_LS_THREADS(num_ls_threads);
1367 r600_pipe_state_add_reg(rstate, R_008C1C_SQ_THREAD_RESOURCE_MGMT_2, tmp, 0xFFFFFFFF, NULL);
1368
1369 tmp = 0;
1370 tmp |= S_008C20_NUM_PS_STACK_ENTRIES(num_ps_stack_entries);
1371 tmp |= S_008C20_NUM_VS_STACK_ENTRIES(num_vs_stack_entries);
1372 r600_pipe_state_add_reg(rstate, R_008C20_SQ_STACK_RESOURCE_MGMT_1, tmp, 0xFFFFFFFF, NULL);
1373
1374 tmp = 0;
1375 tmp |= S_008C24_NUM_GS_STACK_ENTRIES(num_gs_stack_entries);
1376 tmp |= S_008C24_NUM_ES_STACK_ENTRIES(num_es_stack_entries);
1377 r600_pipe_state_add_reg(rstate, R_008C24_SQ_STACK_RESOURCE_MGMT_2, tmp, 0xFFFFFFFF, NULL);
1378
1379 tmp = 0;
1380 tmp |= S_008C28_NUM_HS_STACK_ENTRIES(num_hs_stack_entries);
1381 tmp |= S_008C28_NUM_LS_STACK_ENTRIES(num_ls_stack_entries);
1382 r600_pipe_state_add_reg(rstate, R_008C28_SQ_STACK_RESOURCE_MGMT_3, tmp, 0xFFFFFFFF, NULL);
1383
1384 r600_pipe_state_add_reg(rstate, R_009100_SPI_CONFIG_CNTL, 0x0, 0xFFFFFFFF, NULL);
1385 r600_pipe_state_add_reg(rstate, R_00913C_SPI_CONFIG_CNTL_1, S_00913C_VTX_DONE_DELAY(4), 0xFFFFFFFF, NULL);
1386
1387 #if 0
1388 r600_pipe_state_add_reg(rstate, R_028350_SX_MISC, 0x0, 0xFFFFFFFF, NULL);
1389
1390 r600_pipe_state_add_reg(rstate, R_008D8C_SQ_DYN_GPR_CNTL_PS_FLUSH_REQ, 0x0, 0xFFFFFFFF, NULL);
1391 #endif
1392 r600_pipe_state_add_reg(rstate, R_028A48_PA_SC_MODE_CNTL_0, 0x0, 0xFFFFFFFF, NULL);
1393 r600_pipe_state_add_reg(rstate, R_028A4C_PA_SC_MODE_CNTL_1, 0x0, 0xFFFFFFFF, NULL);
1394
1395 r600_pipe_state_add_reg(rstate, R_028900_SQ_ESGS_RING_ITEMSIZE, 0x0, 0xFFFFFFFF, NULL);
1396 r600_pipe_state_add_reg(rstate, R_028904_SQ_GSVS_RING_ITEMSIZE, 0x0, 0xFFFFFFFF, NULL);
1397 r600_pipe_state_add_reg(rstate, R_028908_SQ_ESTMP_RING_ITEMSIZE, 0x0, 0xFFFFFFFF, NULL);
1398 r600_pipe_state_add_reg(rstate, R_02890C_SQ_GSTMP_RING_ITEMSIZE, 0x0, 0xFFFFFFFF, NULL);
1399 r600_pipe_state_add_reg(rstate, R_028910_SQ_VSTMP_RING_ITEMSIZE, 0x0, 0xFFFFFFFF, NULL);
1400 r600_pipe_state_add_reg(rstate, R_028914_SQ_PSTMP_RING_ITEMSIZE, 0x0, 0xFFFFFFFF, NULL);
1401
1402 r600_pipe_state_add_reg(rstate, R_02891C_SQ_GS_VERT_ITEMSIZE, 0x0, 0xFFFFFFFF, NULL);
1403 r600_pipe_state_add_reg(rstate, R_028920_SQ_GS_VERT_ITEMSIZE_1, 0x0, 0xFFFFFFFF, NULL);
1404 r600_pipe_state_add_reg(rstate, R_028924_SQ_GS_VERT_ITEMSIZE_2, 0x0, 0xFFFFFFFF, NULL);
1405 r600_pipe_state_add_reg(rstate, R_028928_SQ_GS_VERT_ITEMSIZE_3, 0x0, 0xFFFFFFFF, NULL);
1406
1407 r600_pipe_state_add_reg(rstate, R_028A10_VGT_OUTPUT_PATH_CNTL, 0x0, 0xFFFFFFFF, NULL);
1408 r600_pipe_state_add_reg(rstate, R_028A14_VGT_HOS_CNTL, 0x0, 0xFFFFFFFF, NULL);
1409 r600_pipe_state_add_reg(rstate, R_028A18_VGT_HOS_MAX_TESS_LEVEL, 0x0, 0xFFFFFFFF, NULL);
1410 r600_pipe_state_add_reg(rstate, R_028A1C_VGT_HOS_MIN_TESS_LEVEL, 0x0, 0xFFFFFFFF, NULL);
1411 r600_pipe_state_add_reg(rstate, R_028A20_VGT_HOS_REUSE_DEPTH, 0x0, 0xFFFFFFFF, NULL);
1412 r600_pipe_state_add_reg(rstate, R_028A24_VGT_GROUP_PRIM_TYPE, 0x0, 0xFFFFFFFF, NULL);
1413 r600_pipe_state_add_reg(rstate, R_028A28_VGT_GROUP_FIRST_DECR, 0x0, 0xFFFFFFFF, NULL);
1414 r600_pipe_state_add_reg(rstate, R_028A2C_VGT_GROUP_DECR, 0x0, 0xFFFFFFFF, NULL);
1415 r600_pipe_state_add_reg(rstate, R_028A30_VGT_GROUP_VECT_0_CNTL, 0x0, 0xFFFFFFFF, NULL);
1416 r600_pipe_state_add_reg(rstate, R_028A34_VGT_GROUP_VECT_1_CNTL, 0x0, 0xFFFFFFFF, NULL);
1417 r600_pipe_state_add_reg(rstate, R_028A38_VGT_GROUP_VECT_0_FMT_CNTL, 0x0, 0xFFFFFFFF, NULL);
1418 r600_pipe_state_add_reg(rstate, R_028A3C_VGT_GROUP_VECT_1_FMT_CNTL, 0x0, 0xFFFFFFFF, NULL);
1419 r600_pipe_state_add_reg(rstate, R_028A40_VGT_GS_MODE, 0x0, 0xFFFFFFFF, NULL);
1420 r600_pipe_state_add_reg(rstate, R_028B94_VGT_STRMOUT_CONFIG, 0x0, 0xFFFFFFFF, NULL);
1421 r600_pipe_state_add_reg(rstate, R_028B98_VGT_STRMOUT_BUFFER_CONFIG, 0x0, 0xFFFFFFFF, NULL);
1422 r600_pipe_state_add_reg(rstate, R_028AB4_VGT_REUSE_OFF, 0x00000000, 0xFFFFFFFF, NULL);
1423 r600_pipe_state_add_reg(rstate, R_028AB8_VGT_VTX_CNT_EN, 0x0, 0xFFFFFFFF, NULL);
1424 r600_pipe_state_add_reg(rstate, R_008A14_PA_CL_ENHANCE, (3 << 1) | 1, 0xFFFFFFFF, NULL);
1425
1426 r600_pipe_state_add_reg(rstate, R_028380_SQ_VTX_SEMANTIC_0, 0x0, 0xFFFFFFFF, NULL);
1427 r600_pipe_state_add_reg(rstate, R_028384_SQ_VTX_SEMANTIC_1, 0x0, 0xFFFFFFFF, NULL);
1428 r600_pipe_state_add_reg(rstate, R_028388_SQ_VTX_SEMANTIC_2, 0x0, 0xFFFFFFFF, NULL);
1429 r600_pipe_state_add_reg(rstate, R_02838C_SQ_VTX_SEMANTIC_3, 0x0, 0xFFFFFFFF, NULL);
1430 r600_pipe_state_add_reg(rstate, R_028390_SQ_VTX_SEMANTIC_4, 0x0, 0xFFFFFFFF, NULL);
1431 r600_pipe_state_add_reg(rstate, R_028394_SQ_VTX_SEMANTIC_5, 0x0, 0xFFFFFFFF, NULL);
1432 r600_pipe_state_add_reg(rstate, R_028398_SQ_VTX_SEMANTIC_6, 0x0, 0xFFFFFFFF, NULL);
1433 r600_pipe_state_add_reg(rstate, R_02839C_SQ_VTX_SEMANTIC_7, 0x0, 0xFFFFFFFF, NULL);
1434 r600_pipe_state_add_reg(rstate, R_0283A0_SQ_VTX_SEMANTIC_8, 0x0, 0xFFFFFFFF, NULL);
1435 r600_pipe_state_add_reg(rstate, R_0283A4_SQ_VTX_SEMANTIC_9, 0x0, 0xFFFFFFFF, NULL);
1436 r600_pipe_state_add_reg(rstate, R_0283A8_SQ_VTX_SEMANTIC_10, 0x0, 0xFFFFFFFF, NULL);
1437 r600_pipe_state_add_reg(rstate, R_0283AC_SQ_VTX_SEMANTIC_11, 0x0, 0xFFFFFFFF, NULL);
1438 r600_pipe_state_add_reg(rstate, R_0283B0_SQ_VTX_SEMANTIC_12, 0x0, 0xFFFFFFFF, NULL);
1439 r600_pipe_state_add_reg(rstate, R_0283B4_SQ_VTX_SEMANTIC_13, 0x0, 0xFFFFFFFF, NULL);
1440 r600_pipe_state_add_reg(rstate, R_0283B8_SQ_VTX_SEMANTIC_14, 0x0, 0xFFFFFFFF, NULL);
1441 r600_pipe_state_add_reg(rstate, R_0283BC_SQ_VTX_SEMANTIC_15, 0x0, 0xFFFFFFFF, NULL);
1442 r600_pipe_state_add_reg(rstate, R_0283C0_SQ_VTX_SEMANTIC_16, 0x0, 0xFFFFFFFF, NULL);
1443 r600_pipe_state_add_reg(rstate, R_0283C4_SQ_VTX_SEMANTIC_17, 0x0, 0xFFFFFFFF, NULL);
1444 r600_pipe_state_add_reg(rstate, R_0283C8_SQ_VTX_SEMANTIC_18, 0x0, 0xFFFFFFFF, NULL);
1445 r600_pipe_state_add_reg(rstate, R_0283CC_SQ_VTX_SEMANTIC_19, 0x0, 0xFFFFFFFF, NULL);
1446 r600_pipe_state_add_reg(rstate, R_0283D0_SQ_VTX_SEMANTIC_20, 0x0, 0xFFFFFFFF, NULL);
1447 r600_pipe_state_add_reg(rstate, R_0283D4_SQ_VTX_SEMANTIC_21, 0x0, 0xFFFFFFFF, NULL);
1448 r600_pipe_state_add_reg(rstate, R_0283D8_SQ_VTX_SEMANTIC_22, 0x0, 0xFFFFFFFF, NULL);
1449 r600_pipe_state_add_reg(rstate, R_0283DC_SQ_VTX_SEMANTIC_23, 0x0, 0xFFFFFFFF, NULL);
1450 r600_pipe_state_add_reg(rstate, R_0283E0_SQ_VTX_SEMANTIC_24, 0x0, 0xFFFFFFFF, NULL);
1451 r600_pipe_state_add_reg(rstate, R_0283E4_SQ_VTX_SEMANTIC_25, 0x0, 0xFFFFFFFF, NULL);
1452 r600_pipe_state_add_reg(rstate, R_0283E8_SQ_VTX_SEMANTIC_26, 0x0, 0xFFFFFFFF, NULL);
1453 r600_pipe_state_add_reg(rstate, R_0283EC_SQ_VTX_SEMANTIC_27, 0x0, 0xFFFFFFFF, NULL);
1454 r600_pipe_state_add_reg(rstate, R_0283F0_SQ_VTX_SEMANTIC_28, 0x0, 0xFFFFFFFF, NULL);
1455 r600_pipe_state_add_reg(rstate, R_0283F4_SQ_VTX_SEMANTIC_29, 0x0, 0xFFFFFFFF, NULL);
1456 r600_pipe_state_add_reg(rstate, R_0283F8_SQ_VTX_SEMANTIC_30, 0x0, 0xFFFFFFFF, NULL);
1457 r600_pipe_state_add_reg(rstate, R_0283FC_SQ_VTX_SEMANTIC_31, 0x0, 0xFFFFFFFF, NULL);
1458
1459 r600_pipe_state_add_reg(rstate, R_028810_PA_CL_CLIP_CNTL, 0x0, 0xFFFFFFFF, NULL);
1460
1461 r600_context_pipe_state_set(&rctx->ctx, rstate);
1462 }
1463
1464 void evergreen_polygon_offset_update(struct r600_pipe_context *rctx)
1465 {
1466 struct r600_pipe_state state;
1467
1468 state.id = R600_PIPE_STATE_POLYGON_OFFSET;
1469 state.nregs = 0;
1470 if (rctx->rasterizer && rctx->framebuffer.zsbuf) {
1471 float offset_units = rctx->rasterizer->offset_units;
1472 unsigned offset_db_fmt_cntl = 0, depth;
1473
1474 switch (rctx->framebuffer.zsbuf->texture->format) {
1475 case PIPE_FORMAT_Z24X8_UNORM:
1476 case PIPE_FORMAT_Z24_UNORM_S8_USCALED:
1477 depth = -24;
1478 offset_units *= 2.0f;
1479 break;
1480 case PIPE_FORMAT_Z32_FLOAT:
1481 depth = -23;
1482 offset_units *= 1.0f;
1483 offset_db_fmt_cntl |= S_028B78_POLY_OFFSET_DB_IS_FLOAT_FMT(1);
1484 break;
1485 case PIPE_FORMAT_Z16_UNORM:
1486 depth = -16;
1487 offset_units *= 4.0f;
1488 break;
1489 default:
1490 return;
1491 }
1492 /* FIXME some of those reg can be computed with cso */
1493 offset_db_fmt_cntl |= S_028B78_POLY_OFFSET_NEG_NUM_DB_BITS(depth);
1494 r600_pipe_state_add_reg(&state,
1495 R_028B80_PA_SU_POLY_OFFSET_FRONT_SCALE,
1496 fui(rctx->rasterizer->offset_scale), 0xFFFFFFFF, NULL);
1497 r600_pipe_state_add_reg(&state,
1498 R_028B84_PA_SU_POLY_OFFSET_FRONT_OFFSET,
1499 fui(offset_units), 0xFFFFFFFF, NULL);
1500 r600_pipe_state_add_reg(&state,
1501 R_028B88_PA_SU_POLY_OFFSET_BACK_SCALE,
1502 fui(rctx->rasterizer->offset_scale), 0xFFFFFFFF, NULL);
1503 r600_pipe_state_add_reg(&state,
1504 R_028B8C_PA_SU_POLY_OFFSET_BACK_OFFSET,
1505 fui(offset_units), 0xFFFFFFFF, NULL);
1506 r600_pipe_state_add_reg(&state,
1507 R_028B78_PA_SU_POLY_OFFSET_DB_FMT_CNTL,
1508 offset_db_fmt_cntl, 0xFFFFFFFF, NULL);
1509 r600_context_pipe_state_set(&rctx->ctx, &state);
1510 }
1511 }
1512
1513 void evergreen_pipe_shader_ps(struct pipe_context *ctx, struct r600_pipe_shader *shader)
1514 {
1515 struct r600_pipe_state *rstate = &shader->rstate;
1516 struct r600_shader *rshader = &shader->shader;
1517 unsigned i, exports_ps, num_cout, spi_ps_in_control_0, spi_input_z, spi_ps_in_control_1, db_shader_control;
1518 int pos_index = -1, face_index = -1;
1519 int ninterp = 0;
1520 boolean have_linear = FALSE, have_centroid = FALSE, have_perspective = FALSE;
1521 unsigned spi_baryc_cntl;
1522
1523 rstate->nregs = 0;
1524
1525 db_shader_control = 0;
1526 for (i = 0; i < rshader->ninput; i++) {
1527 /* evergreen NUM_INTERP only contains values interpolated into the LDS,
1528 POSITION goes via GPRs from the SC so isn't counted */
1529 if (rshader->input[i].name == TGSI_SEMANTIC_POSITION)
1530 pos_index = i;
1531 else if (rshader->input[i].name == TGSI_SEMANTIC_FACE)
1532 face_index = i;
1533 else {
1534 if (rshader->input[i].interpolate == TGSI_INTERPOLATE_LINEAR ||
1535 rshader->input[i].interpolate == TGSI_INTERPOLATE_PERSPECTIVE)
1536 ninterp++;
1537 if (rshader->input[i].interpolate == TGSI_INTERPOLATE_LINEAR)
1538 have_linear = TRUE;
1539 if (rshader->input[i].interpolate == TGSI_INTERPOLATE_PERSPECTIVE)
1540 have_perspective = TRUE;
1541 if (rshader->input[i].centroid)
1542 have_centroid = TRUE;
1543 }
1544 }
1545 for (i = 0; i < rshader->noutput; i++) {
1546 if (rshader->output[i].name == TGSI_SEMANTIC_POSITION)
1547 db_shader_control |= S_02880C_Z_EXPORT_ENABLE(1);
1548 if (rshader->output[i].name == TGSI_SEMANTIC_STENCIL)
1549 db_shader_control |= S_02880C_STENCIL_EXPORT_ENABLE(1);
1550 }
1551 if (rshader->uses_kill)
1552 db_shader_control |= S_02880C_KILL_ENABLE(1);
1553
1554 exports_ps = 0;
1555 num_cout = 0;
1556 for (i = 0; i < rshader->noutput; i++) {
1557 if (rshader->output[i].name == TGSI_SEMANTIC_POSITION ||
1558 rshader->output[i].name == TGSI_SEMANTIC_STENCIL)
1559 exports_ps |= 1;
1560 else if (rshader->output[i].name == TGSI_SEMANTIC_COLOR) {
1561 num_cout++;
1562 }
1563 }
1564 exports_ps |= S_02884C_EXPORT_COLORS(num_cout);
1565 if (!exports_ps) {
1566 /* always at least export 1 component per pixel */
1567 exports_ps = 2;
1568 }
1569
1570 if (ninterp == 0) {
1571 ninterp = 1;
1572 have_perspective = TRUE;
1573 }
1574
1575 spi_ps_in_control_0 = S_0286CC_NUM_INTERP(ninterp) |
1576 S_0286CC_PERSP_GRADIENT_ENA(have_perspective) |
1577 S_0286CC_LINEAR_GRADIENT_ENA(have_linear);
1578 spi_input_z = 0;
1579 if (pos_index != -1) {
1580 spi_ps_in_control_0 |= S_0286CC_POSITION_ENA(1) |
1581 S_0286CC_POSITION_CENTROID(rshader->input[pos_index].centroid) |
1582 S_0286CC_POSITION_ADDR(rshader->input[pos_index].gpr);
1583 spi_input_z |= 1;
1584 }
1585
1586 spi_ps_in_control_1 = 0;
1587 if (face_index != -1) {
1588 spi_ps_in_control_1 |= S_0286D0_FRONT_FACE_ENA(1) |
1589 S_0286D0_FRONT_FACE_ADDR(rshader->input[face_index].gpr);
1590 }
1591
1592 spi_baryc_cntl = 0;
1593 if (have_perspective)
1594 spi_baryc_cntl |= S_0286E0_PERSP_CENTER_ENA(1) |
1595 S_0286E0_PERSP_CENTROID_ENA(have_centroid);
1596 if (have_linear)
1597 spi_baryc_cntl |= S_0286E0_LINEAR_CENTER_ENA(1) |
1598 S_0286E0_LINEAR_CENTROID_ENA(have_centroid);
1599
1600 r600_pipe_state_add_reg(rstate, R_0286CC_SPI_PS_IN_CONTROL_0,
1601 spi_ps_in_control_0, 0xFFFFFFFF, NULL);
1602 r600_pipe_state_add_reg(rstate, R_0286D0_SPI_PS_IN_CONTROL_1,
1603 spi_ps_in_control_1, 0xFFFFFFFF, NULL);
1604 r600_pipe_state_add_reg(rstate, R_0286E4_SPI_PS_IN_CONTROL_2,
1605 0, 0xFFFFFFFF, NULL);
1606 r600_pipe_state_add_reg(rstate, R_0286D8_SPI_INPUT_Z, spi_input_z, 0xFFFFFFFF, NULL);
1607 r600_pipe_state_add_reg(rstate,
1608 R_0286E0_SPI_BARYC_CNTL,
1609 spi_baryc_cntl,
1610 0xFFFFFFFF, NULL);
1611
1612 r600_pipe_state_add_reg(rstate,
1613 R_028840_SQ_PGM_START_PS,
1614 (r600_bo_offset(shader->bo)) >> 8, 0xFFFFFFFF, shader->bo);
1615 r600_pipe_state_add_reg(rstate,
1616 R_028844_SQ_PGM_RESOURCES_PS,
1617 S_028844_NUM_GPRS(rshader->bc.ngpr) |
1618 S_028844_PRIME_CACHE_ON_DRAW(1) |
1619 S_028844_STACK_SIZE(rshader->bc.nstack),
1620 0xFFFFFFFF, NULL);
1621 r600_pipe_state_add_reg(rstate,
1622 R_028848_SQ_PGM_RESOURCES_2_PS,
1623 0x0, 0xFFFFFFFF, NULL);
1624 r600_pipe_state_add_reg(rstate,
1625 R_02884C_SQ_PGM_EXPORTS_PS,
1626 exports_ps, 0xFFFFFFFF, NULL);
1627 /* FIXME: Evergreen doesn't seem to support MULTIWRITE_ENABLE. */
1628 /* only set some bits here, the other bits are set in the dsa state */
1629 r600_pipe_state_add_reg(rstate,
1630 R_02880C_DB_SHADER_CONTROL,
1631 db_shader_control,
1632 S_02880C_Z_EXPORT_ENABLE(1) |
1633 S_02880C_STENCIL_EXPORT_ENABLE(1) |
1634 S_02880C_KILL_ENABLE(1),
1635 NULL);
1636 r600_pipe_state_add_reg(rstate,
1637 R_03A200_SQ_LOOP_CONST_0, 0x01000FFF,
1638 0xFFFFFFFF, NULL);
1639 }
1640
1641 void evergreen_pipe_shader_vs(struct pipe_context *ctx, struct r600_pipe_shader *shader)
1642 {
1643 struct r600_pipe_state *rstate = &shader->rstate;
1644 struct r600_shader *rshader = &shader->shader;
1645 unsigned spi_vs_out_id[10];
1646 unsigned i, tmp;
1647
1648 /* clear previous register */
1649 rstate->nregs = 0;
1650
1651 /* so far never got proper semantic id from tgsi */
1652 for (i = 0; i < 10; i++) {
1653 spi_vs_out_id[i] = 0;
1654 }
1655 for (i = 0; i < 32; i++) {
1656 tmp = i << ((i & 3) * 8);
1657 spi_vs_out_id[i / 4] |= tmp;
1658 }
1659 for (i = 0; i < 10; i++) {
1660 r600_pipe_state_add_reg(rstate,
1661 R_02861C_SPI_VS_OUT_ID_0 + i * 4,
1662 spi_vs_out_id[i], 0xFFFFFFFF, NULL);
1663 }
1664
1665 r600_pipe_state_add_reg(rstate,
1666 R_0286C4_SPI_VS_OUT_CONFIG,
1667 S_0286C4_VS_EXPORT_COUNT(rshader->noutput - 2),
1668 0xFFFFFFFF, NULL);
1669 r600_pipe_state_add_reg(rstate,
1670 R_028860_SQ_PGM_RESOURCES_VS,
1671 S_028860_NUM_GPRS(rshader->bc.ngpr) |
1672 S_028860_STACK_SIZE(rshader->bc.nstack),
1673 0xFFFFFFFF, NULL);
1674 r600_pipe_state_add_reg(rstate,
1675 R_028864_SQ_PGM_RESOURCES_2_VS,
1676 0x0, 0xFFFFFFFF, NULL);
1677 r600_pipe_state_add_reg(rstate,
1678 R_02885C_SQ_PGM_START_VS,
1679 (r600_bo_offset(shader->bo)) >> 8, 0xFFFFFFFF, shader->bo);
1680
1681 r600_pipe_state_add_reg(rstate,
1682 R_03A200_SQ_LOOP_CONST_0 + (32 * 4), 0x01000FFF,
1683 0xFFFFFFFF, NULL);
1684 }
1685
1686 void evergreen_fetch_shader(struct r600_vertex_element *ve)
1687 {
1688 struct r600_pipe_state *rstate = &ve->rstate;
1689 rstate->id = R600_PIPE_STATE_FETCH_SHADER;
1690 rstate->nregs = 0;
1691 r600_pipe_state_add_reg(rstate, R_0288A8_SQ_PGM_RESOURCES_FS,
1692 0x00000000, 0xFFFFFFFF, NULL);
1693 r600_pipe_state_add_reg(rstate, R_0288A4_SQ_PGM_START_FS,
1694 (r600_bo_offset(ve->fetch_shader)) >> 8,
1695 0xFFFFFFFF, ve->fetch_shader);
1696 }
1697
1698 void *evergreen_create_db_flush_dsa(struct r600_pipe_context *rctx)
1699 {
1700 struct pipe_depth_stencil_alpha_state dsa;
1701 struct r600_pipe_state *rstate;
1702
1703 memset(&dsa, 0, sizeof(dsa));
1704
1705 rstate = rctx->context.create_depth_stencil_alpha_state(&rctx->context, &dsa);
1706 r600_pipe_state_add_reg(rstate,
1707 R_02880C_DB_SHADER_CONTROL,
1708 0x0,
1709 S_02880C_DUAL_EXPORT_ENABLE(1), NULL);
1710 r600_pipe_state_add_reg(rstate,
1711 R_028000_DB_RENDER_CONTROL,
1712 S_028000_DEPTH_COPY_ENABLE(1) |
1713 S_028000_STENCIL_COPY_ENABLE(1) |
1714 S_028000_COPY_CENTROID(1),
1715 S_028000_DEPTH_COPY_ENABLE(1) |
1716 S_028000_STENCIL_COPY_ENABLE(1) |
1717 S_028000_COPY_CENTROID(1), NULL);
1718 return rstate;
1719 }
1720
1721 void evergreen_pipe_set_buffer_resource(struct r600_pipe_context *rctx,
1722 struct r600_pipe_state *rstate,
1723 struct r600_resource *rbuffer,
1724 unsigned offset, unsigned stride)
1725 {
1726 r600_pipe_state_add_reg(rstate, R_030000_RESOURCE0_WORD0,
1727 offset, 0xFFFFFFFF, rbuffer->bo);
1728 r600_pipe_state_add_reg(rstate, R_030004_RESOURCE0_WORD1,
1729 rbuffer->bo_size - offset - 1, 0xFFFFFFFF, NULL);
1730 r600_pipe_state_add_reg(rstate, R_030008_RESOURCE0_WORD2,
1731 S_030008_ENDIAN_SWAP(r600_endian_swap(32)) |
1732 S_030008_STRIDE(stride), 0xFFFFFFFF, NULL);
1733 r600_pipe_state_add_reg(rstate, R_03000C_RESOURCE0_WORD3,
1734 S_03000C_DST_SEL_X(V_03000C_SQ_SEL_X) |
1735 S_03000C_DST_SEL_Y(V_03000C_SQ_SEL_Y) |
1736 S_03000C_DST_SEL_Z(V_03000C_SQ_SEL_Z) |
1737 S_03000C_DST_SEL_W(V_03000C_SQ_SEL_W),
1738 0xFFFFFFFF, NULL);
1739 r600_pipe_state_add_reg(rstate, R_030010_RESOURCE0_WORD4,
1740 0x00000000, 0xFFFFFFFF, NULL);
1741 r600_pipe_state_add_reg(rstate, R_030014_RESOURCE0_WORD5,
1742 0x00000000, 0xFFFFFFFF, NULL);
1743 r600_pipe_state_add_reg(rstate, R_030018_RESOURCE0_WORD6,
1744 0x00000000, 0xFFFFFFFF, NULL);
1745 r600_pipe_state_add_reg(rstate, R_03001C_RESOURCE0_WORD7,
1746 0xC0000000, 0xFFFFFFFF, NULL);
1747 }