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2135b8ac580b368df838c59ca07b085bd3695e66
[mesa.git] / src / gallium / drivers / r600 / evergreen_state.c
1 /*
2 * Copyright 2010 Jerome Glisse <glisse@freedesktop.org>
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * on the rights to use, copy, modify, merge, publish, distribute, sub
8 * license, and/or sell copies of the Software, and to permit persons to whom
9 * the Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
13 * Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHOR(S) AND/OR THEIR SUPPLIERS BE LIABLE FOR ANY CLAIM,
19 * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
20 * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
21 * USE OR OTHER DEALINGS IN THE SOFTWARE.
22 */
23
24 /* TODO:
25 * - fix mask for depth control & cull for query
26 */
27 #include <stdio.h>
28 #include <errno.h>
29 #include <pipe/p_defines.h>
30 #include <pipe/p_state.h>
31 #include <pipe/p_context.h>
32 #include <tgsi/tgsi_scan.h>
33 #include <tgsi/tgsi_parse.h>
34 #include <tgsi/tgsi_util.h>
35 #include <util/u_blitter.h>
36 #include <util/u_double_list.h>
37 #include <util/u_transfer.h>
38 #include <util/u_surface.h>
39 #include <util/u_pack_color.h>
40 #include <util/u_memory.h>
41 #include <util/u_inlines.h>
42 #include <util/u_framebuffer.h>
43 #include <pipebuffer/pb_buffer.h>
44 #include "r600.h"
45 #include "evergreend.h"
46 #include "r600_resource.h"
47 #include "r600_shader.h"
48 #include "r600_pipe.h"
49 #include "r600_formats.h"
50
51 static uint32_t r600_translate_blend_function(int blend_func)
52 {
53 switch (blend_func) {
54 case PIPE_BLEND_ADD:
55 return V_028780_COMB_DST_PLUS_SRC;
56 case PIPE_BLEND_SUBTRACT:
57 return V_028780_COMB_SRC_MINUS_DST;
58 case PIPE_BLEND_REVERSE_SUBTRACT:
59 return V_028780_COMB_DST_MINUS_SRC;
60 case PIPE_BLEND_MIN:
61 return V_028780_COMB_MIN_DST_SRC;
62 case PIPE_BLEND_MAX:
63 return V_028780_COMB_MAX_DST_SRC;
64 default:
65 R600_ERR("Unknown blend function %d\n", blend_func);
66 assert(0);
67 break;
68 }
69 return 0;
70 }
71
72 static uint32_t r600_translate_blend_factor(int blend_fact)
73 {
74 switch (blend_fact) {
75 case PIPE_BLENDFACTOR_ONE:
76 return V_028780_BLEND_ONE;
77 case PIPE_BLENDFACTOR_SRC_COLOR:
78 return V_028780_BLEND_SRC_COLOR;
79 case PIPE_BLENDFACTOR_SRC_ALPHA:
80 return V_028780_BLEND_SRC_ALPHA;
81 case PIPE_BLENDFACTOR_DST_ALPHA:
82 return V_028780_BLEND_DST_ALPHA;
83 case PIPE_BLENDFACTOR_DST_COLOR:
84 return V_028780_BLEND_DST_COLOR;
85 case PIPE_BLENDFACTOR_SRC_ALPHA_SATURATE:
86 return V_028780_BLEND_SRC_ALPHA_SATURATE;
87 case PIPE_BLENDFACTOR_CONST_COLOR:
88 return V_028780_BLEND_CONST_COLOR;
89 case PIPE_BLENDFACTOR_CONST_ALPHA:
90 return V_028780_BLEND_CONST_ALPHA;
91 case PIPE_BLENDFACTOR_ZERO:
92 return V_028780_BLEND_ZERO;
93 case PIPE_BLENDFACTOR_INV_SRC_COLOR:
94 return V_028780_BLEND_ONE_MINUS_SRC_COLOR;
95 case PIPE_BLENDFACTOR_INV_SRC_ALPHA:
96 return V_028780_BLEND_ONE_MINUS_SRC_ALPHA;
97 case PIPE_BLENDFACTOR_INV_DST_ALPHA:
98 return V_028780_BLEND_ONE_MINUS_DST_ALPHA;
99 case PIPE_BLENDFACTOR_INV_DST_COLOR:
100 return V_028780_BLEND_ONE_MINUS_DST_COLOR;
101 case PIPE_BLENDFACTOR_INV_CONST_COLOR:
102 return V_028780_BLEND_ONE_MINUS_CONST_COLOR;
103 case PIPE_BLENDFACTOR_INV_CONST_ALPHA:
104 return V_028780_BLEND_ONE_MINUS_CONST_ALPHA;
105 case PIPE_BLENDFACTOR_SRC1_COLOR:
106 return V_028780_BLEND_SRC1_COLOR;
107 case PIPE_BLENDFACTOR_SRC1_ALPHA:
108 return V_028780_BLEND_SRC1_ALPHA;
109 case PIPE_BLENDFACTOR_INV_SRC1_COLOR:
110 return V_028780_BLEND_INV_SRC1_COLOR;
111 case PIPE_BLENDFACTOR_INV_SRC1_ALPHA:
112 return V_028780_BLEND_INV_SRC1_ALPHA;
113 default:
114 R600_ERR("Bad blend factor %d not supported!\n", blend_fact);
115 assert(0);
116 break;
117 }
118 return 0;
119 }
120
121 static uint32_t r600_translate_stencil_op(int s_op)
122 {
123 switch (s_op) {
124 case PIPE_STENCIL_OP_KEEP:
125 return V_028800_STENCIL_KEEP;
126 case PIPE_STENCIL_OP_ZERO:
127 return V_028800_STENCIL_ZERO;
128 case PIPE_STENCIL_OP_REPLACE:
129 return V_028800_STENCIL_REPLACE;
130 case PIPE_STENCIL_OP_INCR:
131 return V_028800_STENCIL_INCR;
132 case PIPE_STENCIL_OP_DECR:
133 return V_028800_STENCIL_DECR;
134 case PIPE_STENCIL_OP_INCR_WRAP:
135 return V_028800_STENCIL_INCR_WRAP;
136 case PIPE_STENCIL_OP_DECR_WRAP:
137 return V_028800_STENCIL_DECR_WRAP;
138 case PIPE_STENCIL_OP_INVERT:
139 return V_028800_STENCIL_INVERT;
140 default:
141 R600_ERR("Unknown stencil op %d", s_op);
142 assert(0);
143 break;
144 }
145 return 0;
146 }
147
148 static uint32_t r600_translate_fill(uint32_t func)
149 {
150 switch(func) {
151 case PIPE_POLYGON_MODE_FILL:
152 return 2;
153 case PIPE_POLYGON_MODE_LINE:
154 return 1;
155 case PIPE_POLYGON_MODE_POINT:
156 return 0;
157 default:
158 assert(0);
159 return 0;
160 }
161 }
162
163 /* translates straight */
164 static uint32_t r600_translate_ds_func(int func)
165 {
166 return func;
167 }
168
169 static unsigned r600_tex_wrap(unsigned wrap)
170 {
171 switch (wrap) {
172 default:
173 case PIPE_TEX_WRAP_REPEAT:
174 return V_03C000_SQ_TEX_WRAP;
175 case PIPE_TEX_WRAP_CLAMP:
176 return V_03C000_SQ_TEX_CLAMP_HALF_BORDER;
177 case PIPE_TEX_WRAP_CLAMP_TO_EDGE:
178 return V_03C000_SQ_TEX_CLAMP_LAST_TEXEL;
179 case PIPE_TEX_WRAP_CLAMP_TO_BORDER:
180 return V_03C000_SQ_TEX_CLAMP_BORDER;
181 case PIPE_TEX_WRAP_MIRROR_REPEAT:
182 return V_03C000_SQ_TEX_MIRROR;
183 case PIPE_TEX_WRAP_MIRROR_CLAMP:
184 return V_03C000_SQ_TEX_MIRROR_ONCE_HALF_BORDER;
185 case PIPE_TEX_WRAP_MIRROR_CLAMP_TO_EDGE:
186 return V_03C000_SQ_TEX_MIRROR_ONCE_LAST_TEXEL;
187 case PIPE_TEX_WRAP_MIRROR_CLAMP_TO_BORDER:
188 return V_03C000_SQ_TEX_MIRROR_ONCE_BORDER;
189 }
190 }
191
192 static unsigned r600_tex_filter(unsigned filter)
193 {
194 switch (filter) {
195 default:
196 case PIPE_TEX_FILTER_NEAREST:
197 return V_03C000_SQ_TEX_XY_FILTER_POINT;
198 case PIPE_TEX_FILTER_LINEAR:
199 return V_03C000_SQ_TEX_XY_FILTER_BILINEAR;
200 }
201 }
202
203 static unsigned r600_tex_mipfilter(unsigned filter)
204 {
205 switch (filter) {
206 case PIPE_TEX_MIPFILTER_NEAREST:
207 return V_03C000_SQ_TEX_Z_FILTER_POINT;
208 case PIPE_TEX_MIPFILTER_LINEAR:
209 return V_03C000_SQ_TEX_Z_FILTER_LINEAR;
210 default:
211 case PIPE_TEX_MIPFILTER_NONE:
212 return V_03C000_SQ_TEX_Z_FILTER_NONE;
213 }
214 }
215
216 static unsigned r600_tex_compare(unsigned compare)
217 {
218 switch (compare) {
219 default:
220 case PIPE_FUNC_NEVER:
221 return V_03C000_SQ_TEX_DEPTH_COMPARE_NEVER;
222 case PIPE_FUNC_LESS:
223 return V_03C000_SQ_TEX_DEPTH_COMPARE_LESS;
224 case PIPE_FUNC_EQUAL:
225 return V_03C000_SQ_TEX_DEPTH_COMPARE_EQUAL;
226 case PIPE_FUNC_LEQUAL:
227 return V_03C000_SQ_TEX_DEPTH_COMPARE_LESSEQUAL;
228 case PIPE_FUNC_GREATER:
229 return V_03C000_SQ_TEX_DEPTH_COMPARE_GREATER;
230 case PIPE_FUNC_NOTEQUAL:
231 return V_03C000_SQ_TEX_DEPTH_COMPARE_NOTEQUAL;
232 case PIPE_FUNC_GEQUAL:
233 return V_03C000_SQ_TEX_DEPTH_COMPARE_GREATEREQUAL;
234 case PIPE_FUNC_ALWAYS:
235 return V_03C000_SQ_TEX_DEPTH_COMPARE_ALWAYS;
236 }
237 }
238
239 static unsigned r600_tex_dim(unsigned dim)
240 {
241 switch (dim) {
242 default:
243 case PIPE_TEXTURE_1D:
244 return V_030000_SQ_TEX_DIM_1D;
245 case PIPE_TEXTURE_1D_ARRAY:
246 return V_030000_SQ_TEX_DIM_1D_ARRAY;
247 case PIPE_TEXTURE_2D:
248 case PIPE_TEXTURE_RECT:
249 return V_030000_SQ_TEX_DIM_2D;
250 case PIPE_TEXTURE_2D_ARRAY:
251 return V_030000_SQ_TEX_DIM_2D_ARRAY;
252 case PIPE_TEXTURE_3D:
253 return V_030000_SQ_TEX_DIM_3D;
254 case PIPE_TEXTURE_CUBE:
255 return V_030000_SQ_TEX_DIM_CUBEMAP;
256 }
257 }
258
259 static uint32_t r600_translate_dbformat(enum pipe_format format)
260 {
261 switch (format) {
262 case PIPE_FORMAT_Z16_UNORM:
263 return V_028040_Z_16;
264 case PIPE_FORMAT_Z24X8_UNORM:
265 case PIPE_FORMAT_Z24_UNORM_S8_USCALED:
266 return V_028040_Z_24;
267 case PIPE_FORMAT_Z32_FLOAT:
268 case PIPE_FORMAT_Z32_FLOAT_S8X24_USCALED:
269 return V_028040_Z_32_FLOAT;
270 default:
271 return ~0U;
272 }
273 }
274
275 static uint32_t r600_translate_colorswap(enum pipe_format format)
276 {
277 switch (format) {
278 /* 8-bit buffers. */
279 case PIPE_FORMAT_L4A4_UNORM:
280 return V_028C70_SWAP_ALT;
281
282 case PIPE_FORMAT_A8_UNORM:
283 return V_028C70_SWAP_ALT_REV;
284 case PIPE_FORMAT_I8_UNORM:
285 case PIPE_FORMAT_L8_UNORM:
286 case PIPE_FORMAT_L8_SRGB:
287 case PIPE_FORMAT_R8_UNORM:
288 case PIPE_FORMAT_R8_SNORM:
289 return V_028C70_SWAP_STD;
290
291 /* 16-bit buffers. */
292 case PIPE_FORMAT_B5G6R5_UNORM:
293 return V_028C70_SWAP_STD_REV;
294
295 case PIPE_FORMAT_B5G5R5A1_UNORM:
296 case PIPE_FORMAT_B5G5R5X1_UNORM:
297 return V_028C70_SWAP_ALT;
298
299 case PIPE_FORMAT_B4G4R4A4_UNORM:
300 case PIPE_FORMAT_B4G4R4X4_UNORM:
301 return V_028C70_SWAP_ALT;
302
303 case PIPE_FORMAT_Z16_UNORM:
304 return V_028C70_SWAP_STD;
305
306 case PIPE_FORMAT_L8A8_UNORM:
307 case PIPE_FORMAT_L8A8_SRGB:
308 return V_028C70_SWAP_ALT;
309 case PIPE_FORMAT_R8G8_UNORM:
310 return V_028C70_SWAP_STD;
311
312 case PIPE_FORMAT_R16_UNORM:
313 case PIPE_FORMAT_R16_FLOAT:
314 return V_028C70_SWAP_STD;
315
316 /* 32-bit buffers. */
317 case PIPE_FORMAT_A8B8G8R8_SRGB:
318 return V_028C70_SWAP_STD_REV;
319 case PIPE_FORMAT_B8G8R8A8_SRGB:
320 return V_028C70_SWAP_ALT;
321
322 case PIPE_FORMAT_B8G8R8A8_UNORM:
323 case PIPE_FORMAT_B8G8R8X8_UNORM:
324 return V_028C70_SWAP_ALT;
325
326 case PIPE_FORMAT_A8R8G8B8_UNORM:
327 case PIPE_FORMAT_X8R8G8B8_UNORM:
328 return V_028C70_SWAP_ALT_REV;
329 case PIPE_FORMAT_R8G8B8A8_SNORM:
330 case PIPE_FORMAT_R8G8B8A8_UNORM:
331 case PIPE_FORMAT_R8G8B8X8_UNORM:
332 return V_028C70_SWAP_STD;
333
334 case PIPE_FORMAT_A8B8G8R8_UNORM:
335 case PIPE_FORMAT_X8B8G8R8_UNORM:
336 /* case PIPE_FORMAT_R8SG8SB8UX8U_NORM: */
337 return V_028C70_SWAP_STD_REV;
338
339 case PIPE_FORMAT_Z24X8_UNORM:
340 case PIPE_FORMAT_Z24_UNORM_S8_USCALED:
341 return V_028C70_SWAP_STD;
342
343 case PIPE_FORMAT_X8Z24_UNORM:
344 case PIPE_FORMAT_S8_USCALED_Z24_UNORM:
345 return V_028C70_SWAP_STD;
346
347 case PIPE_FORMAT_R10G10B10A2_UNORM:
348 case PIPE_FORMAT_R10G10B10X2_SNORM:
349 case PIPE_FORMAT_R10SG10SB10SA2U_NORM:
350 return V_028C70_SWAP_STD;
351
352 case PIPE_FORMAT_B10G10R10A2_UNORM:
353 return V_028C70_SWAP_ALT;
354
355 case PIPE_FORMAT_R11G11B10_FLOAT:
356 case PIPE_FORMAT_R32_FLOAT:
357 case PIPE_FORMAT_Z32_FLOAT:
358 case PIPE_FORMAT_R16G16_FLOAT:
359 case PIPE_FORMAT_R16G16_UNORM:
360 return V_028C70_SWAP_STD;
361
362 /* 64-bit buffers. */
363 case PIPE_FORMAT_R32G32_FLOAT:
364 case PIPE_FORMAT_R16G16B16A16_UNORM:
365 case PIPE_FORMAT_R16G16B16A16_SNORM:
366 case PIPE_FORMAT_R16G16B16A16_FLOAT:
367 case PIPE_FORMAT_Z32_FLOAT_S8X24_USCALED:
368
369 /* 128-bit buffers. */
370 case PIPE_FORMAT_R32G32B32A32_FLOAT:
371 case PIPE_FORMAT_R32G32B32A32_SNORM:
372 case PIPE_FORMAT_R32G32B32A32_UNORM:
373 return V_028C70_SWAP_STD;
374 default:
375 R600_ERR("unsupported colorswap format %d\n", format);
376 return ~0U;
377 }
378 return ~0U;
379 }
380
381 static uint32_t r600_translate_colorformat(enum pipe_format format)
382 {
383 switch (format) {
384 /* 8-bit buffers. */
385 case PIPE_FORMAT_L4A4_UNORM:
386 return V_028C70_COLOR_4_4;
387
388 case PIPE_FORMAT_A8_UNORM:
389 case PIPE_FORMAT_I8_UNORM:
390 case PIPE_FORMAT_L8_UNORM:
391 case PIPE_FORMAT_L8_SRGB:
392 case PIPE_FORMAT_R8_UNORM:
393 case PIPE_FORMAT_R8_SNORM:
394 return V_028C70_COLOR_8;
395
396 /* 16-bit buffers. */
397 case PIPE_FORMAT_B5G6R5_UNORM:
398 return V_028C70_COLOR_5_6_5;
399
400 case PIPE_FORMAT_B5G5R5A1_UNORM:
401 case PIPE_FORMAT_B5G5R5X1_UNORM:
402 return V_028C70_COLOR_1_5_5_5;
403
404 case PIPE_FORMAT_B4G4R4A4_UNORM:
405 case PIPE_FORMAT_B4G4R4X4_UNORM:
406 return V_028C70_COLOR_4_4_4_4;
407
408 case PIPE_FORMAT_Z16_UNORM:
409 return V_028C70_COLOR_16;
410
411 case PIPE_FORMAT_L8A8_UNORM:
412 case PIPE_FORMAT_L8A8_SRGB:
413 case PIPE_FORMAT_R8G8_UNORM:
414 return V_028C70_COLOR_8_8;
415
416 case PIPE_FORMAT_R16_UNORM:
417 return V_028C70_COLOR_16;
418
419 case PIPE_FORMAT_R16_FLOAT:
420 return V_028C70_COLOR_16_FLOAT;
421
422 /* 32-bit buffers. */
423 case PIPE_FORMAT_A8B8G8R8_SRGB:
424 case PIPE_FORMAT_A8B8G8R8_UNORM:
425 case PIPE_FORMAT_A8R8G8B8_UNORM:
426 case PIPE_FORMAT_B8G8R8A8_SRGB:
427 case PIPE_FORMAT_B8G8R8A8_UNORM:
428 case PIPE_FORMAT_B8G8R8X8_UNORM:
429 case PIPE_FORMAT_R8G8B8A8_SNORM:
430 case PIPE_FORMAT_R8G8B8A8_UNORM:
431 case PIPE_FORMAT_R8G8B8X8_UNORM:
432 case PIPE_FORMAT_R8SG8SB8UX8U_NORM:
433 case PIPE_FORMAT_X8B8G8R8_UNORM:
434 case PIPE_FORMAT_X8R8G8B8_UNORM:
435 case PIPE_FORMAT_R8G8B8_UNORM:
436 return V_028C70_COLOR_8_8_8_8;
437
438 case PIPE_FORMAT_R10G10B10A2_UNORM:
439 case PIPE_FORMAT_R10G10B10X2_SNORM:
440 case PIPE_FORMAT_B10G10R10A2_UNORM:
441 case PIPE_FORMAT_R10SG10SB10SA2U_NORM:
442 return V_028C70_COLOR_2_10_10_10;
443
444 case PIPE_FORMAT_Z24X8_UNORM:
445 case PIPE_FORMAT_Z24_UNORM_S8_USCALED:
446 return V_028C70_COLOR_8_24;
447
448 case PIPE_FORMAT_X8Z24_UNORM:
449 case PIPE_FORMAT_S8_USCALED_Z24_UNORM:
450 return V_028C70_COLOR_24_8;
451
452 case PIPE_FORMAT_Z32_FLOAT_S8X24_USCALED:
453 return V_028C70_COLOR_X24_8_32_FLOAT;
454
455 case PIPE_FORMAT_R32_FLOAT:
456 case PIPE_FORMAT_Z32_FLOAT:
457 return V_028C70_COLOR_32_FLOAT;
458
459 case PIPE_FORMAT_R16G16_FLOAT:
460 return V_028C70_COLOR_16_16_FLOAT;
461
462 case PIPE_FORMAT_R16G16_SSCALED:
463 case PIPE_FORMAT_R16G16_UNORM:
464 return V_028C70_COLOR_16_16;
465
466 case PIPE_FORMAT_R11G11B10_FLOAT:
467 return V_028C70_COLOR_10_11_11_FLOAT;
468
469 /* 64-bit buffers. */
470 case PIPE_FORMAT_R16G16B16_USCALED:
471 case PIPE_FORMAT_R16G16B16A16_USCALED:
472 case PIPE_FORMAT_R16G16B16_SSCALED:
473 case PIPE_FORMAT_R16G16B16A16_SSCALED:
474 case PIPE_FORMAT_R16G16B16A16_UNORM:
475 case PIPE_FORMAT_R16G16B16A16_SNORM:
476 return V_028C70_COLOR_16_16_16_16;
477
478 case PIPE_FORMAT_R16G16B16_FLOAT:
479 case PIPE_FORMAT_R16G16B16A16_FLOAT:
480 return V_028C70_COLOR_16_16_16_16_FLOAT;
481
482 case PIPE_FORMAT_R32G32_FLOAT:
483 return V_028C70_COLOR_32_32_FLOAT;
484
485 case PIPE_FORMAT_R32G32_USCALED:
486 case PIPE_FORMAT_R32G32_SSCALED:
487 return V_028C70_COLOR_32_32;
488
489 /* 96-bit buffers. */
490 case PIPE_FORMAT_R32G32B32_FLOAT:
491 return V_028C70_COLOR_32_32_32_FLOAT;
492
493 /* 128-bit buffers. */
494 case PIPE_FORMAT_R32G32B32A32_SNORM:
495 case PIPE_FORMAT_R32G32B32A32_UNORM:
496 return V_028C70_COLOR_32_32_32_32;
497 case PIPE_FORMAT_R32G32B32A32_FLOAT:
498 return V_028C70_COLOR_32_32_32_32_FLOAT;
499
500 /* YUV buffers. */
501 case PIPE_FORMAT_UYVY:
502 case PIPE_FORMAT_YUYV:
503 default:
504 return ~0U; /* Unsupported. */
505 }
506 }
507
508 static uint32_t r600_colorformat_endian_swap(uint32_t colorformat)
509 {
510 if (R600_BIG_ENDIAN) {
511 switch(colorformat) {
512 case V_028C70_COLOR_4_4:
513 return ENDIAN_NONE;
514
515 /* 8-bit buffers. */
516 case V_028C70_COLOR_8:
517 return ENDIAN_NONE;
518
519 /* 16-bit buffers. */
520 case V_028C70_COLOR_5_6_5:
521 case V_028C70_COLOR_1_5_5_5:
522 case V_028C70_COLOR_4_4_4_4:
523 case V_028C70_COLOR_16:
524 case V_028C70_COLOR_8_8:
525 return ENDIAN_8IN16;
526
527 /* 32-bit buffers. */
528 case V_028C70_COLOR_8_8_8_8:
529 case V_028C70_COLOR_2_10_10_10:
530 case V_028C70_COLOR_8_24:
531 case V_028C70_COLOR_24_8:
532 case V_028C70_COLOR_32_FLOAT:
533 case V_028C70_COLOR_16_16_FLOAT:
534 case V_028C70_COLOR_16_16:
535 return ENDIAN_8IN32;
536
537 /* 64-bit buffers. */
538 case V_028C70_COLOR_16_16_16_16:
539 case V_028C70_COLOR_16_16_16_16_FLOAT:
540 return ENDIAN_8IN16;
541
542 case V_028C70_COLOR_32_32_FLOAT:
543 case V_028C70_COLOR_32_32:
544 case V_028C70_COLOR_X24_8_32_FLOAT:
545 return ENDIAN_8IN32;
546
547 /* 96-bit buffers. */
548 case V_028C70_COLOR_32_32_32_FLOAT:
549 /* 128-bit buffers. */
550 case V_028C70_COLOR_32_32_32_32_FLOAT:
551 case V_028C70_COLOR_32_32_32_32:
552 return ENDIAN_8IN32;
553 default:
554 return ENDIAN_NONE; /* Unsupported. */
555 }
556 } else {
557 return ENDIAN_NONE;
558 }
559 }
560
561 static bool r600_is_sampler_format_supported(struct pipe_screen *screen, enum pipe_format format)
562 {
563 return r600_translate_texformat(screen, format, NULL, NULL, NULL) != ~0U;
564 }
565
566 static bool r600_is_colorbuffer_format_supported(enum pipe_format format)
567 {
568 return r600_translate_colorformat(format) != ~0U &&
569 r600_translate_colorswap(format) != ~0U;
570 }
571
572 static bool r600_is_zs_format_supported(enum pipe_format format)
573 {
574 return r600_translate_dbformat(format) != ~0U;
575 }
576
577 boolean evergreen_is_format_supported(struct pipe_screen *screen,
578 enum pipe_format format,
579 enum pipe_texture_target target,
580 unsigned sample_count,
581 unsigned usage)
582 {
583 unsigned retval = 0;
584
585 if (target >= PIPE_MAX_TEXTURE_TYPES) {
586 R600_ERR("r600: unsupported texture type %d\n", target);
587 return FALSE;
588 }
589
590 if (!util_format_is_supported(format, usage))
591 return FALSE;
592
593 /* Multisample */
594 if (sample_count > 1)
595 return FALSE;
596
597 if ((usage & PIPE_BIND_SAMPLER_VIEW) &&
598 r600_is_sampler_format_supported(screen, format)) {
599 retval |= PIPE_BIND_SAMPLER_VIEW;
600 }
601
602 if ((usage & (PIPE_BIND_RENDER_TARGET |
603 PIPE_BIND_DISPLAY_TARGET |
604 PIPE_BIND_SCANOUT |
605 PIPE_BIND_SHARED)) &&
606 r600_is_colorbuffer_format_supported(format)) {
607 retval |= usage &
608 (PIPE_BIND_RENDER_TARGET |
609 PIPE_BIND_DISPLAY_TARGET |
610 PIPE_BIND_SCANOUT |
611 PIPE_BIND_SHARED);
612 }
613
614 if ((usage & PIPE_BIND_DEPTH_STENCIL) &&
615 r600_is_zs_format_supported(format)) {
616 retval |= PIPE_BIND_DEPTH_STENCIL;
617 }
618
619 if ((usage & PIPE_BIND_VERTEX_BUFFER) &&
620 r600_is_vertex_format_supported(format)) {
621 retval |= PIPE_BIND_VERTEX_BUFFER;
622 }
623
624 if (usage & PIPE_BIND_TRANSFER_READ)
625 retval |= PIPE_BIND_TRANSFER_READ;
626 if (usage & PIPE_BIND_TRANSFER_WRITE)
627 retval |= PIPE_BIND_TRANSFER_WRITE;
628
629 return retval == usage;
630 }
631
632 static void evergreen_set_blend_color(struct pipe_context *ctx,
633 const struct pipe_blend_color *state)
634 {
635 struct r600_pipe_context *rctx = (struct r600_pipe_context *)ctx;
636 struct r600_pipe_state *rstate = CALLOC_STRUCT(r600_pipe_state);
637
638 if (rstate == NULL)
639 return;
640
641 rstate->id = R600_PIPE_STATE_BLEND_COLOR;
642 r600_pipe_state_add_reg(rstate, R_028414_CB_BLEND_RED, fui(state->color[0]), 0xFFFFFFFF, NULL, 0);
643 r600_pipe_state_add_reg(rstate, R_028418_CB_BLEND_GREEN, fui(state->color[1]), 0xFFFFFFFF, NULL, 0);
644 r600_pipe_state_add_reg(rstate, R_02841C_CB_BLEND_BLUE, fui(state->color[2]), 0xFFFFFFFF, NULL, 0);
645 r600_pipe_state_add_reg(rstate, R_028420_CB_BLEND_ALPHA, fui(state->color[3]), 0xFFFFFFFF, NULL, 0);
646
647 free(rctx->states[R600_PIPE_STATE_BLEND_COLOR]);
648 rctx->states[R600_PIPE_STATE_BLEND_COLOR] = rstate;
649 r600_context_pipe_state_set(&rctx->ctx, rstate);
650 }
651
652 static void *evergreen_create_blend_state(struct pipe_context *ctx,
653 const struct pipe_blend_state *state)
654 {
655 struct r600_pipe_context *rctx = (struct r600_pipe_context *)ctx;
656 struct r600_pipe_blend *blend = CALLOC_STRUCT(r600_pipe_blend);
657 struct r600_pipe_state *rstate;
658 u32 color_control, target_mask;
659 /* FIXME there is more then 8 framebuffer */
660 unsigned blend_cntl[8];
661
662 if (blend == NULL) {
663 return NULL;
664 }
665
666 rstate = &blend->rstate;
667
668 rstate->id = R600_PIPE_STATE_BLEND;
669
670 target_mask = 0;
671 color_control = S_028808_MODE(1);
672 if (state->logicop_enable) {
673 color_control |= (state->logicop_func << 16) | (state->logicop_func << 20);
674 } else {
675 color_control |= (0xcc << 16);
676 }
677 /* we pretend 8 buffer are used, CB_SHADER_MASK will disable unused one */
678 if (state->independent_blend_enable) {
679 for (int i = 0; i < 8; i++) {
680 target_mask |= (state->rt[i].colormask << (4 * i));
681 }
682 } else {
683 for (int i = 0; i < 8; i++) {
684 target_mask |= (state->rt[0].colormask << (4 * i));
685 }
686 }
687 blend->cb_target_mask = target_mask;
688
689 r600_pipe_state_add_reg(rstate, R_028808_CB_COLOR_CONTROL,
690 color_control, 0xFFFFFFFD, NULL, 0);
691
692 if (rctx->chip_class != CAYMAN)
693 r600_pipe_state_add_reg(rstate, R_028C3C_PA_SC_AA_MASK, 0xFFFFFFFF, 0xFFFFFFFF, NULL, 0);
694 else {
695 r600_pipe_state_add_reg(rstate, CM_R_028C38_PA_SC_AA_MASK_X0Y0_X1Y0, 0xFFFFFFFF, 0xFFFFFFFF, NULL, 0);
696 r600_pipe_state_add_reg(rstate, CM_R_028C3C_PA_SC_AA_MASK_X0Y1_X1Y1, 0xFFFFFFFF, 0xFFFFFFFF, NULL, 0);
697 }
698
699 for (int i = 0; i < 8; i++) {
700 /* state->rt entries > 0 only written if independent blending */
701 const int j = state->independent_blend_enable ? i : 0;
702
703 unsigned eqRGB = state->rt[j].rgb_func;
704 unsigned srcRGB = state->rt[j].rgb_src_factor;
705 unsigned dstRGB = state->rt[j].rgb_dst_factor;
706 unsigned eqA = state->rt[j].alpha_func;
707 unsigned srcA = state->rt[j].alpha_src_factor;
708 unsigned dstA = state->rt[j].alpha_dst_factor;
709
710 blend_cntl[i] = 0;
711 if (!state->rt[j].blend_enable)
712 continue;
713
714 blend_cntl[i] |= S_028780_BLEND_CONTROL_ENABLE(1);
715 blend_cntl[i] |= S_028780_COLOR_COMB_FCN(r600_translate_blend_function(eqRGB));
716 blend_cntl[i] |= S_028780_COLOR_SRCBLEND(r600_translate_blend_factor(srcRGB));
717 blend_cntl[i] |= S_028780_COLOR_DESTBLEND(r600_translate_blend_factor(dstRGB));
718
719 if (srcA != srcRGB || dstA != dstRGB || eqA != eqRGB) {
720 blend_cntl[i] |= S_028780_SEPARATE_ALPHA_BLEND(1);
721 blend_cntl[i] |= S_028780_ALPHA_COMB_FCN(r600_translate_blend_function(eqA));
722 blend_cntl[i] |= S_028780_ALPHA_SRCBLEND(r600_translate_blend_factor(srcA));
723 blend_cntl[i] |= S_028780_ALPHA_DESTBLEND(r600_translate_blend_factor(dstA));
724 }
725 }
726 for (int i = 0; i < 8; i++) {
727 r600_pipe_state_add_reg(rstate, R_028780_CB_BLEND0_CONTROL + i * 4, blend_cntl[i], 0xFFFFFFFF, NULL, 0);
728 }
729
730 return rstate;
731 }
732
733 static void *evergreen_create_dsa_state(struct pipe_context *ctx,
734 const struct pipe_depth_stencil_alpha_state *state)
735 {
736 struct r600_pipe_context *rctx = (struct r600_pipe_context *)ctx;
737 struct r600_pipe_dsa *dsa = CALLOC_STRUCT(r600_pipe_dsa);
738 unsigned db_depth_control, alpha_test_control, alpha_ref, db_shader_control;
739 unsigned stencil_ref_mask, stencil_ref_mask_bf, db_render_override, db_render_control;
740 struct r600_pipe_state *rstate;
741
742 if (dsa == NULL) {
743 return NULL;
744 }
745
746 rstate = &dsa->rstate;
747
748 rstate->id = R600_PIPE_STATE_DSA;
749 /* depth TODO some of those db_shader_control field depend on shader adjust mask & add it to shader */
750 db_shader_control = S_02880C_Z_ORDER(V_02880C_EARLY_Z_THEN_LATE_Z);
751 stencil_ref_mask = 0;
752 stencil_ref_mask_bf = 0;
753 db_depth_control = S_028800_Z_ENABLE(state->depth.enabled) |
754 S_028800_Z_WRITE_ENABLE(state->depth.writemask) |
755 S_028800_ZFUNC(state->depth.func);
756
757 /* stencil */
758 if (state->stencil[0].enabled) {
759 db_depth_control |= S_028800_STENCIL_ENABLE(1);
760 db_depth_control |= S_028800_STENCILFUNC(r600_translate_ds_func(state->stencil[0].func));
761 db_depth_control |= S_028800_STENCILFAIL(r600_translate_stencil_op(state->stencil[0].fail_op));
762 db_depth_control |= S_028800_STENCILZPASS(r600_translate_stencil_op(state->stencil[0].zpass_op));
763 db_depth_control |= S_028800_STENCILZFAIL(r600_translate_stencil_op(state->stencil[0].zfail_op));
764
765
766 stencil_ref_mask = S_028430_STENCILMASK(state->stencil[0].valuemask) |
767 S_028430_STENCILWRITEMASK(state->stencil[0].writemask);
768 if (state->stencil[1].enabled) {
769 db_depth_control |= S_028800_BACKFACE_ENABLE(1);
770 db_depth_control |= S_028800_STENCILFUNC_BF(r600_translate_ds_func(state->stencil[1].func));
771 db_depth_control |= S_028800_STENCILFAIL_BF(r600_translate_stencil_op(state->stencil[1].fail_op));
772 db_depth_control |= S_028800_STENCILZPASS_BF(r600_translate_stencil_op(state->stencil[1].zpass_op));
773 db_depth_control |= S_028800_STENCILZFAIL_BF(r600_translate_stencil_op(state->stencil[1].zfail_op));
774 stencil_ref_mask_bf = S_028434_STENCILMASK_BF(state->stencil[1].valuemask) |
775 S_028434_STENCILWRITEMASK_BF(state->stencil[1].writemask);
776 }
777 }
778
779 /* alpha */
780 alpha_test_control = 0;
781 alpha_ref = 0;
782 if (state->alpha.enabled) {
783 alpha_test_control = S_028410_ALPHA_FUNC(state->alpha.func);
784 alpha_test_control |= S_028410_ALPHA_TEST_ENABLE(1);
785 alpha_ref = fui(state->alpha.ref_value);
786 }
787 dsa->alpha_ref = alpha_ref;
788
789 /* misc */
790 db_render_control = 0;
791 db_render_override = S_02800C_FORCE_HIZ_ENABLE(V_02800C_FORCE_DISABLE) |
792 S_02800C_FORCE_HIS_ENABLE0(V_02800C_FORCE_DISABLE) |
793 S_02800C_FORCE_HIS_ENABLE1(V_02800C_FORCE_DISABLE);
794 /* TODO db_render_override depends on query */
795 r600_pipe_state_add_reg(rstate, R_028028_DB_STENCIL_CLEAR, 0x00000000, 0xFFFFFFFF, NULL, 0);
796 r600_pipe_state_add_reg(rstate, R_02802C_DB_DEPTH_CLEAR, 0x3F800000, 0xFFFFFFFF, NULL, 0);
797 r600_pipe_state_add_reg(rstate, R_028410_SX_ALPHA_TEST_CONTROL, alpha_test_control, 0xFFFFFFFF, NULL, 0);
798 r600_pipe_state_add_reg(rstate,
799 R_028430_DB_STENCILREFMASK, stencil_ref_mask,
800 0xFFFFFFFF & C_028430_STENCILREF, NULL, 0);
801 r600_pipe_state_add_reg(rstate,
802 R_028434_DB_STENCILREFMASK_BF, stencil_ref_mask_bf,
803 0xFFFFFFFF & C_028434_STENCILREF_BF, NULL, 0);
804 r600_pipe_state_add_reg(rstate, R_0286DC_SPI_FOG_CNTL, 0x00000000, 0xFFFFFFFF, NULL, 0);
805 r600_pipe_state_add_reg(rstate, R_028800_DB_DEPTH_CONTROL, db_depth_control, 0xFFFFFFFF, NULL, 0);
806 /* The DB_SHADER_CONTROL mask is 0xFFFFFFBC since Z_EXPORT_ENABLE,
807 * STENCIL_EXPORT_ENABLE and KILL_ENABLE are controlled by
808 * evergreen_pipe_shader_ps().*/
809 r600_pipe_state_add_reg(rstate, R_02880C_DB_SHADER_CONTROL, db_shader_control, 0xFFFFFFBC, NULL, 0);
810 r600_pipe_state_add_reg(rstate, R_028000_DB_RENDER_CONTROL, db_render_control, 0xFFFFFFFF, NULL, 0);
811 r600_pipe_state_add_reg(rstate, R_02800C_DB_RENDER_OVERRIDE, db_render_override, 0xFFFFFFFF, NULL, 0);
812 r600_pipe_state_add_reg(rstate, R_028AC0_DB_SRESULTS_COMPARE_STATE0, 0x0, 0xFFFFFFFF, NULL, 0);
813 r600_pipe_state_add_reg(rstate, R_028AC4_DB_SRESULTS_COMPARE_STATE1, 0x0, 0xFFFFFFFF, NULL, 0);
814 r600_pipe_state_add_reg(rstate, R_028AC8_DB_PRELOAD_CONTROL, 0x0, 0xFFFFFFFF, NULL, 0);
815 r600_pipe_state_add_reg(rstate, R_028B70_DB_ALPHA_TO_MASK, 0x0000AA00, 0xFFFFFFFF, NULL, 0);
816
817 return rstate;
818 }
819
820 static void *evergreen_create_rs_state(struct pipe_context *ctx,
821 const struct pipe_rasterizer_state *state)
822 {
823 struct r600_pipe_context *rctx = (struct r600_pipe_context *)ctx;
824 struct r600_pipe_rasterizer *rs = CALLOC_STRUCT(r600_pipe_rasterizer);
825 struct r600_pipe_state *rstate;
826 unsigned tmp;
827 unsigned prov_vtx = 1, polygon_dual_mode;
828 unsigned clip_rule;
829
830 if (rs == NULL) {
831 return NULL;
832 }
833
834 rstate = &rs->rstate;
835 rs->clamp_vertex_color = state->clamp_vertex_color;
836 rs->clamp_fragment_color = state->clamp_fragment_color;
837 rs->flatshade = state->flatshade;
838 rs->sprite_coord_enable = state->sprite_coord_enable;
839
840 clip_rule = state->scissor ? 0xAAAA : 0xFFFF;
841
842 /* offset */
843 rs->offset_units = state->offset_units;
844 rs->offset_scale = state->offset_scale * 12.0f;
845
846 rstate->id = R600_PIPE_STATE_RASTERIZER;
847 if (state->flatshade_first)
848 prov_vtx = 0;
849 tmp = S_0286D4_FLAT_SHADE_ENA(1);
850 if (state->sprite_coord_enable) {
851 tmp |= S_0286D4_PNT_SPRITE_ENA(1) |
852 S_0286D4_PNT_SPRITE_OVRD_X(2) |
853 S_0286D4_PNT_SPRITE_OVRD_Y(3) |
854 S_0286D4_PNT_SPRITE_OVRD_Z(0) |
855 S_0286D4_PNT_SPRITE_OVRD_W(1);
856 if (state->sprite_coord_mode != PIPE_SPRITE_COORD_UPPER_LEFT) {
857 tmp |= S_0286D4_PNT_SPRITE_TOP_1(1);
858 }
859 }
860 r600_pipe_state_add_reg(rstate, R_0286D4_SPI_INTERP_CONTROL_0, tmp, 0xFFFFFFFF, NULL, 0);
861
862 polygon_dual_mode = (state->fill_front != PIPE_POLYGON_MODE_FILL ||
863 state->fill_back != PIPE_POLYGON_MODE_FILL);
864 r600_pipe_state_add_reg(rstate, R_028814_PA_SU_SC_MODE_CNTL,
865 S_028814_PROVOKING_VTX_LAST(prov_vtx) |
866 S_028814_CULL_FRONT((state->cull_face & PIPE_FACE_FRONT) ? 1 : 0) |
867 S_028814_CULL_BACK((state->cull_face & PIPE_FACE_BACK) ? 1 : 0) |
868 S_028814_FACE(!state->front_ccw) |
869 S_028814_POLY_OFFSET_FRONT_ENABLE(state->offset_tri) |
870 S_028814_POLY_OFFSET_BACK_ENABLE(state->offset_tri) |
871 S_028814_POLY_OFFSET_PARA_ENABLE(state->offset_tri) |
872 S_028814_POLY_MODE(polygon_dual_mode) |
873 S_028814_POLYMODE_FRONT_PTYPE(r600_translate_fill(state->fill_front)) |
874 S_028814_POLYMODE_BACK_PTYPE(r600_translate_fill(state->fill_back)), 0xFFFFFFFF, NULL, 0);
875 r600_pipe_state_add_reg(rstate, R_02881C_PA_CL_VS_OUT_CNTL,
876 S_02881C_USE_VTX_POINT_SIZE(state->point_size_per_vertex) |
877 S_02881C_VS_OUT_MISC_VEC_ENA(state->point_size_per_vertex), 0xFFFFFFFF, NULL, 0);
878 r600_pipe_state_add_reg(rstate, R_028820_PA_CL_NANINF_CNTL, 0x00000000, 0xFFFFFFFF, NULL, 0);
879 /* point size 12.4 fixed point */
880 tmp = (unsigned)(state->point_size * 8.0);
881 r600_pipe_state_add_reg(rstate, R_028A00_PA_SU_POINT_SIZE, S_028A00_HEIGHT(tmp) | S_028A00_WIDTH(tmp), 0xFFFFFFFF, NULL, 0);
882 r600_pipe_state_add_reg(rstate, R_028A04_PA_SU_POINT_MINMAX, 0x80000000, 0xFFFFFFFF, NULL, 0);
883
884 tmp = (unsigned)state->line_width * 8;
885 r600_pipe_state_add_reg(rstate, R_028A08_PA_SU_LINE_CNTL, S_028A08_WIDTH(tmp), 0xFFFFFFFF, NULL, 0);
886
887 if (rctx->chip_class == CAYMAN) {
888 r600_pipe_state_add_reg(rstate, CM_R_028BDC_PA_SC_LINE_CNTL, 0x00000400, 0xFFFFFFFF, NULL, 0);
889 r600_pipe_state_add_reg(rstate, CM_R_028BE4_PA_SU_VTX_CNTL,
890 S_028C08_PIX_CENTER_HALF(state->gl_rasterization_rules),
891 0xFFFFFFFF, NULL, 0);
892 r600_pipe_state_add_reg(rstate, CM_R_028BE8_PA_CL_GB_VERT_CLIP_ADJ, 0x3F800000, 0xFFFFFFFF, NULL, 0);
893 r600_pipe_state_add_reg(rstate, CM_R_028BEC_PA_CL_GB_VERT_DISC_ADJ, 0x3F800000, 0xFFFFFFFF, NULL, 0);
894 r600_pipe_state_add_reg(rstate, CM_R_028BF0_PA_CL_GB_HORZ_CLIP_ADJ, 0x3F800000, 0xFFFFFFFF, NULL, 0);
895 r600_pipe_state_add_reg(rstate, CM_R_028BF4_PA_CL_GB_HORZ_DISC_ADJ, 0x3F800000, 0xFFFFFFFF, NULL, 0);
896
897
898 } else {
899 r600_pipe_state_add_reg(rstate, R_028C00_PA_SC_LINE_CNTL, 0x00000400, 0xFFFFFFFF, NULL, 0);
900
901 r600_pipe_state_add_reg(rstate, R_028C0C_PA_CL_GB_VERT_CLIP_ADJ, 0x3F800000, 0xFFFFFFFF, NULL, 0);
902 r600_pipe_state_add_reg(rstate, R_028C10_PA_CL_GB_VERT_DISC_ADJ, 0x3F800000, 0xFFFFFFFF, NULL, 0);
903 r600_pipe_state_add_reg(rstate, R_028C14_PA_CL_GB_HORZ_CLIP_ADJ, 0x3F800000, 0xFFFFFFFF, NULL, 0);
904 r600_pipe_state_add_reg(rstate, R_028C18_PA_CL_GB_HORZ_DISC_ADJ, 0x3F800000, 0xFFFFFFFF, NULL, 0);
905
906 r600_pipe_state_add_reg(rstate, R_028C08_PA_SU_VTX_CNTL,
907 S_028C08_PIX_CENTER_HALF(state->gl_rasterization_rules),
908 0xFFFFFFFF, NULL, 0);
909 }
910 r600_pipe_state_add_reg(rstate, R_028B7C_PA_SU_POLY_OFFSET_CLAMP, 0x0, 0xFFFFFFFF, NULL, 0);
911 r600_pipe_state_add_reg(rstate, R_02820C_PA_SC_CLIPRECT_RULE, clip_rule, 0xFFFFFFFF, NULL, 0);
912 return rstate;
913 }
914
915 static void *evergreen_create_sampler_state(struct pipe_context *ctx,
916 const struct pipe_sampler_state *state)
917 {
918 struct r600_pipe_state *rstate = CALLOC_STRUCT(r600_pipe_state);
919 union util_color uc;
920 unsigned aniso_flag_offset = state->max_anisotropy > 1 ? 2 : 0;
921
922 if (rstate == NULL) {
923 return NULL;
924 }
925
926 rstate->id = R600_PIPE_STATE_SAMPLER;
927 util_pack_color(state->border_color, PIPE_FORMAT_B8G8R8A8_UNORM, &uc);
928 r600_pipe_state_add_reg_noblock(rstate, R_03C000_SQ_TEX_SAMPLER_WORD0_0,
929 S_03C000_CLAMP_X(r600_tex_wrap(state->wrap_s)) |
930 S_03C000_CLAMP_Y(r600_tex_wrap(state->wrap_t)) |
931 S_03C000_CLAMP_Z(r600_tex_wrap(state->wrap_r)) |
932 S_03C000_XY_MAG_FILTER(r600_tex_filter(state->mag_img_filter) | aniso_flag_offset) |
933 S_03C000_XY_MIN_FILTER(r600_tex_filter(state->min_img_filter) | aniso_flag_offset) |
934 S_03C000_MIP_FILTER(r600_tex_mipfilter(state->min_mip_filter)) |
935 S_03C000_MAX_ANISO(r600_tex_aniso_filter(state->max_anisotropy)) |
936 S_03C000_DEPTH_COMPARE_FUNCTION(r600_tex_compare(state->compare_func)) |
937 S_03C000_BORDER_COLOR_TYPE(uc.ui ? V_03C000_SQ_TEX_BORDER_COLOR_REGISTER : 0), 0xFFFFFFFF, NULL, 0);
938 r600_pipe_state_add_reg_noblock(rstate, R_03C004_SQ_TEX_SAMPLER_WORD1_0,
939 S_03C004_MIN_LOD(S_FIXED(CLAMP(state->min_lod, 0, 15), 8)) |
940 S_03C004_MAX_LOD(S_FIXED(CLAMP(state->max_lod, 0, 15), 8)),
941 0xFFFFFFFF, NULL, 0);
942 r600_pipe_state_add_reg_noblock(rstate, R_03C008_SQ_TEX_SAMPLER_WORD2_0,
943 S_03C008_LOD_BIAS(S_FIXED(CLAMP(state->lod_bias, -16, 16), 8)) |
944 (state->seamless_cube_map ? 0 : S_03C008_DISABLE_CUBE_WRAP(1)) |
945 S_03C008_TYPE(1),
946 0xFFFFFFFF, NULL, 0);
947
948 if (uc.ui) {
949 r600_pipe_state_add_reg_noblock(rstate, R_00A404_TD_PS_SAMPLER0_BORDER_RED, fui(state->border_color[0]), 0xFFFFFFFF, NULL, 0);
950 r600_pipe_state_add_reg_noblock(rstate, R_00A408_TD_PS_SAMPLER0_BORDER_GREEN, fui(state->border_color[1]), 0xFFFFFFFF, NULL, 0);
951 r600_pipe_state_add_reg_noblock(rstate, R_00A40C_TD_PS_SAMPLER0_BORDER_BLUE, fui(state->border_color[2]), 0xFFFFFFFF, NULL, 0);
952 r600_pipe_state_add_reg_noblock(rstate, R_00A410_TD_PS_SAMPLER0_BORDER_ALPHA, fui(state->border_color[3]), 0xFFFFFFFF, NULL, 0);
953 }
954 return rstate;
955 }
956
957 static struct pipe_sampler_view *evergreen_create_sampler_view(struct pipe_context *ctx,
958 struct pipe_resource *texture,
959 const struct pipe_sampler_view *state)
960 {
961 struct r600_pipe_sampler_view *view = CALLOC_STRUCT(r600_pipe_sampler_view);
962 struct r600_pipe_resource_state *rstate;
963 struct r600_resource_texture *tmp = (struct r600_resource_texture*)texture;
964 struct r600_resource *rbuffer;
965 unsigned format, endian;
966 uint32_t word4 = 0, yuv_format = 0, pitch = 0;
967 unsigned char swizzle[4], array_mode = 0, tile_type = 0;
968 struct r600_bo *bo[2];
969
970 if (view == NULL)
971 return NULL;
972 rstate = &view->state;
973
974 /* initialize base object */
975 view->base = *state;
976 view->base.texture = NULL;
977 pipe_reference(NULL, &texture->reference);
978 view->base.texture = texture;
979 view->base.reference.count = 1;
980 view->base.context = ctx;
981
982 swizzle[0] = state->swizzle_r;
983 swizzle[1] = state->swizzle_g;
984 swizzle[2] = state->swizzle_b;
985 swizzle[3] = state->swizzle_a;
986
987 format = r600_translate_texformat(ctx->screen, state->format,
988 swizzle,
989 &word4, &yuv_format);
990 if (format == ~0) {
991 format = 0;
992 }
993
994 if (tmp->depth && !tmp->is_flushing_texture) {
995 r600_texture_depth_flush(ctx, texture, TRUE);
996 tmp = tmp->flushed_depth_texture;
997 }
998
999 endian = r600_colorformat_endian_swap(format);
1000
1001 if (tmp->force_int_type) {
1002 word4 &= C_030010_NUM_FORMAT_ALL;
1003 word4 |= S_030010_NUM_FORMAT_ALL(V_030010_SQ_NUM_FORMAT_INT);
1004 }
1005
1006 rbuffer = &tmp->resource;
1007 bo[0] = rbuffer->bo;
1008 bo[1] = rbuffer->bo;
1009
1010 pitch = align(tmp->pitch_in_blocks[0] * util_format_get_blockwidth(state->format), 8);
1011 array_mode = tmp->array_mode[0];
1012 tile_type = tmp->tile_type;
1013
1014 rstate->bo[0] = bo[0];
1015 rstate->bo[1] = bo[1];
1016 rstate->bo_usage[0] = RADEON_USAGE_READ;
1017 rstate->bo_usage[1] = RADEON_USAGE_READ;
1018 rstate->val[0] = (S_030000_DIM(r600_tex_dim(texture->target)) |
1019 S_030000_PITCH((pitch / 8) - 1) |
1020 S_030000_NON_DISP_TILING_ORDER(tile_type) |
1021 S_030000_TEX_WIDTH(texture->width0 - 1));
1022 rstate->val[1] = (S_030004_TEX_HEIGHT(texture->height0 - 1) |
1023 S_030004_TEX_DEPTH(texture->depth0 - 1) |
1024 S_030004_ARRAY_MODE(array_mode));
1025 rstate->val[2] = tmp->offset[0] >> 8;
1026 rstate->val[3] = tmp->offset[1] >> 8;
1027 rstate->val[4] = (word4 |
1028 S_030010_SRF_MODE_ALL(V_030010_SRF_MODE_ZERO_CLAMP_MINUS_ONE) |
1029 S_030010_ENDIAN_SWAP(endian) |
1030 S_030010_BASE_LEVEL(state->u.tex.first_level));
1031 rstate->val[5] = (S_030014_LAST_LEVEL(state->u.tex.last_level) |
1032 S_030014_BASE_ARRAY(0) |
1033 S_030014_LAST_ARRAY(0));
1034 rstate->val[6] = (S_030018_MAX_ANISO(4 /* max 16 samples */));
1035 rstate->val[7] = (S_03001C_DATA_FORMAT(format) |
1036 S_03001C_TYPE(V_03001C_SQ_TEX_VTX_VALID_TEXTURE));
1037
1038 return &view->base;
1039 }
1040
1041 static void evergreen_set_vs_sampler_view(struct pipe_context *ctx, unsigned count,
1042 struct pipe_sampler_view **views)
1043 {
1044 struct r600_pipe_context *rctx = (struct r600_pipe_context *)ctx;
1045 struct r600_pipe_sampler_view **resource = (struct r600_pipe_sampler_view **)views;
1046
1047 for (int i = 0; i < count; i++) {
1048 if (resource[i]) {
1049 evergreen_context_pipe_state_set_vs_resource(&rctx->ctx, &resource[i]->state,
1050 i + R600_MAX_CONST_BUFFERS);
1051 }
1052 }
1053 }
1054
1055 static void evergreen_set_ps_sampler_view(struct pipe_context *ctx, unsigned count,
1056 struct pipe_sampler_view **views)
1057 {
1058 struct r600_pipe_context *rctx = (struct r600_pipe_context *)ctx;
1059 struct r600_pipe_sampler_view **resource = (struct r600_pipe_sampler_view **)views;
1060 int i;
1061 int has_depth = 0;
1062
1063 for (i = 0; i < count; i++) {
1064 if (&rctx->ps_samplers.views[i]->base != views[i]) {
1065 if (resource[i]) {
1066 if (((struct r600_resource_texture *)resource[i]->base.texture)->depth)
1067 has_depth = 1;
1068 evergreen_context_pipe_state_set_ps_resource(&rctx->ctx, &resource[i]->state,
1069 i + R600_MAX_CONST_BUFFERS);
1070 } else
1071 evergreen_context_pipe_state_set_ps_resource(&rctx->ctx, NULL,
1072 i + R600_MAX_CONST_BUFFERS);
1073
1074 pipe_sampler_view_reference(
1075 (struct pipe_sampler_view **)&rctx->ps_samplers.views[i],
1076 views[i]);
1077 } else {
1078 if (resource[i]) {
1079 if (((struct r600_resource_texture *)resource[i]->base.texture)->depth)
1080 has_depth = 1;
1081 }
1082 }
1083 }
1084 for (i = count; i < NUM_TEX_UNITS; i++) {
1085 if (rctx->ps_samplers.views[i]) {
1086 evergreen_context_pipe_state_set_ps_resource(&rctx->ctx, NULL,
1087 i + R600_MAX_CONST_BUFFERS);
1088 pipe_sampler_view_reference((struct pipe_sampler_view **)&rctx->ps_samplers.views[i], NULL);
1089 }
1090 }
1091 rctx->have_depth_texture = has_depth;
1092 rctx->ps_samplers.n_views = count;
1093 }
1094
1095 static void evergreen_bind_ps_sampler(struct pipe_context *ctx, unsigned count, void **states)
1096 {
1097 struct r600_pipe_context *rctx = (struct r600_pipe_context *)ctx;
1098 struct r600_pipe_state **rstates = (struct r600_pipe_state **)states;
1099
1100
1101 memcpy(rctx->ps_samplers.samplers, states, sizeof(void*) * count);
1102 rctx->ps_samplers.n_samplers = count;
1103
1104 for (int i = 0; i < count; i++) {
1105 evergreen_context_pipe_state_set_ps_sampler(&rctx->ctx, rstates[i], i);
1106 }
1107 }
1108
1109 static void evergreen_bind_vs_sampler(struct pipe_context *ctx, unsigned count, void **states)
1110 {
1111 struct r600_pipe_context *rctx = (struct r600_pipe_context *)ctx;
1112 struct r600_pipe_state **rstates = (struct r600_pipe_state **)states;
1113
1114 for (int i = 0; i < count; i++) {
1115 evergreen_context_pipe_state_set_vs_sampler(&rctx->ctx, rstates[i], i);
1116 }
1117 }
1118
1119 static void evergreen_set_clip_state(struct pipe_context *ctx,
1120 const struct pipe_clip_state *state)
1121 {
1122 struct r600_pipe_context *rctx = (struct r600_pipe_context *)ctx;
1123 struct r600_pipe_state *rstate = CALLOC_STRUCT(r600_pipe_state);
1124
1125 if (rstate == NULL)
1126 return;
1127
1128 rctx->clip = *state;
1129 rstate->id = R600_PIPE_STATE_CLIP;
1130 for (int i = 0; i < state->nr; i++) {
1131 r600_pipe_state_add_reg(rstate,
1132 R_0285BC_PA_CL_UCP0_X + i * 16,
1133 fui(state->ucp[i][0]), 0xFFFFFFFF, NULL, 0);
1134 r600_pipe_state_add_reg(rstate,
1135 R_0285C0_PA_CL_UCP0_Y + i * 16,
1136 fui(state->ucp[i][1]) , 0xFFFFFFFF, NULL, 0);
1137 r600_pipe_state_add_reg(rstate,
1138 R_0285C4_PA_CL_UCP0_Z + i * 16,
1139 fui(state->ucp[i][2]), 0xFFFFFFFF, NULL, 0);
1140 r600_pipe_state_add_reg(rstate,
1141 R_0285C8_PA_CL_UCP0_W + i * 16,
1142 fui(state->ucp[i][3]), 0xFFFFFFFF, NULL, 0);
1143 }
1144 r600_pipe_state_add_reg(rstate, R_028810_PA_CL_CLIP_CNTL,
1145 S_028810_PS_UCP_MODE(3) | ((1 << state->nr) - 1) |
1146 S_028810_ZCLIP_NEAR_DISABLE(state->depth_clamp) |
1147 S_028810_ZCLIP_FAR_DISABLE(state->depth_clamp), 0xFFFFFFFF, NULL, 0);
1148
1149 free(rctx->states[R600_PIPE_STATE_CLIP]);
1150 rctx->states[R600_PIPE_STATE_CLIP] = rstate;
1151 r600_context_pipe_state_set(&rctx->ctx, rstate);
1152 }
1153
1154 static void evergreen_set_polygon_stipple(struct pipe_context *ctx,
1155 const struct pipe_poly_stipple *state)
1156 {
1157 }
1158
1159 static void evergreen_set_sample_mask(struct pipe_context *pipe, unsigned sample_mask)
1160 {
1161 }
1162
1163 static void evergreen_set_scissor_state(struct pipe_context *ctx,
1164 const struct pipe_scissor_state *state)
1165 {
1166 struct r600_pipe_context *rctx = (struct r600_pipe_context *)ctx;
1167 struct r600_pipe_state *rstate = CALLOC_STRUCT(r600_pipe_state);
1168 u32 tl, br;
1169
1170 if (rstate == NULL)
1171 return;
1172
1173 rstate->id = R600_PIPE_STATE_SCISSOR;
1174 tl = S_028240_TL_X(state->minx) | S_028240_TL_Y(state->miny);
1175 br = S_028244_BR_X(state->maxx) | S_028244_BR_Y(state->maxy);
1176 r600_pipe_state_add_reg(rstate,
1177 R_028210_PA_SC_CLIPRECT_0_TL, tl,
1178 0xFFFFFFFF, NULL, 0);
1179 r600_pipe_state_add_reg(rstate,
1180 R_028214_PA_SC_CLIPRECT_0_BR, br,
1181 0xFFFFFFFF, NULL, 0);
1182 r600_pipe_state_add_reg(rstate,
1183 R_028218_PA_SC_CLIPRECT_1_TL, tl,
1184 0xFFFFFFFF, NULL, 0);
1185 r600_pipe_state_add_reg(rstate,
1186 R_02821C_PA_SC_CLIPRECT_1_BR, br,
1187 0xFFFFFFFF, NULL, 0);
1188 r600_pipe_state_add_reg(rstate,
1189 R_028220_PA_SC_CLIPRECT_2_TL, tl,
1190 0xFFFFFFFF, NULL, 0);
1191 r600_pipe_state_add_reg(rstate,
1192 R_028224_PA_SC_CLIPRECT_2_BR, br,
1193 0xFFFFFFFF, NULL, 0);
1194 r600_pipe_state_add_reg(rstate,
1195 R_028228_PA_SC_CLIPRECT_3_TL, tl,
1196 0xFFFFFFFF, NULL, 0);
1197 r600_pipe_state_add_reg(rstate,
1198 R_02822C_PA_SC_CLIPRECT_3_BR, br,
1199 0xFFFFFFFF, NULL, 0);
1200
1201 free(rctx->states[R600_PIPE_STATE_SCISSOR]);
1202 rctx->states[R600_PIPE_STATE_SCISSOR] = rstate;
1203 r600_context_pipe_state_set(&rctx->ctx, rstate);
1204 }
1205
1206 static void evergreen_set_stencil_ref(struct pipe_context *ctx,
1207 const struct pipe_stencil_ref *state)
1208 {
1209 struct r600_pipe_context *rctx = (struct r600_pipe_context *)ctx;
1210 struct r600_pipe_state *rstate = CALLOC_STRUCT(r600_pipe_state);
1211 u32 tmp;
1212
1213 if (rstate == NULL)
1214 return;
1215
1216 rctx->stencil_ref = *state;
1217 rstate->id = R600_PIPE_STATE_STENCIL_REF;
1218 tmp = S_028430_STENCILREF(state->ref_value[0]);
1219 r600_pipe_state_add_reg(rstate,
1220 R_028430_DB_STENCILREFMASK, tmp,
1221 ~C_028430_STENCILREF, NULL, 0);
1222 tmp = S_028434_STENCILREF_BF(state->ref_value[1]);
1223 r600_pipe_state_add_reg(rstate,
1224 R_028434_DB_STENCILREFMASK_BF, tmp,
1225 ~C_028434_STENCILREF_BF, NULL, 0);
1226
1227 free(rctx->states[R600_PIPE_STATE_STENCIL_REF]);
1228 rctx->states[R600_PIPE_STATE_STENCIL_REF] = rstate;
1229 r600_context_pipe_state_set(&rctx->ctx, rstate);
1230 }
1231
1232 static void evergreen_set_viewport_state(struct pipe_context *ctx,
1233 const struct pipe_viewport_state *state)
1234 {
1235 struct r600_pipe_context *rctx = (struct r600_pipe_context *)ctx;
1236 struct r600_pipe_state *rstate = CALLOC_STRUCT(r600_pipe_state);
1237
1238 if (rstate == NULL)
1239 return;
1240
1241 rctx->viewport = *state;
1242 rstate->id = R600_PIPE_STATE_VIEWPORT;
1243 r600_pipe_state_add_reg(rstate, R_0282D0_PA_SC_VPORT_ZMIN_0, 0x00000000, 0xFFFFFFFF, NULL, 0);
1244 r600_pipe_state_add_reg(rstate, R_0282D4_PA_SC_VPORT_ZMAX_0, 0x3F800000, 0xFFFFFFFF, NULL, 0);
1245 r600_pipe_state_add_reg(rstate, R_02843C_PA_CL_VPORT_XSCALE_0, fui(state->scale[0]), 0xFFFFFFFF, NULL, 0);
1246 r600_pipe_state_add_reg(rstate, R_028444_PA_CL_VPORT_YSCALE_0, fui(state->scale[1]), 0xFFFFFFFF, NULL, 0);
1247 r600_pipe_state_add_reg(rstate, R_02844C_PA_CL_VPORT_ZSCALE_0, fui(state->scale[2]), 0xFFFFFFFF, NULL, 0);
1248 r600_pipe_state_add_reg(rstate, R_028440_PA_CL_VPORT_XOFFSET_0, fui(state->translate[0]), 0xFFFFFFFF, NULL, 0);
1249 r600_pipe_state_add_reg(rstate, R_028448_PA_CL_VPORT_YOFFSET_0, fui(state->translate[1]), 0xFFFFFFFF, NULL, 0);
1250 r600_pipe_state_add_reg(rstate, R_028450_PA_CL_VPORT_ZOFFSET_0, fui(state->translate[2]), 0xFFFFFFFF, NULL, 0);
1251 r600_pipe_state_add_reg(rstate, R_028818_PA_CL_VTE_CNTL, 0x0000043F, 0xFFFFFFFF, NULL, 0);
1252
1253 free(rctx->states[R600_PIPE_STATE_VIEWPORT]);
1254 rctx->states[R600_PIPE_STATE_VIEWPORT] = rstate;
1255 r600_context_pipe_state_set(&rctx->ctx, rstate);
1256 }
1257
1258 static void evergreen_cb(struct r600_pipe_context *rctx, struct r600_pipe_state *rstate,
1259 const struct pipe_framebuffer_state *state, int cb)
1260 {
1261 struct r600_resource_texture *rtex;
1262 struct r600_resource *rbuffer;
1263 struct r600_surface *surf;
1264 unsigned level = state->cbufs[cb]->u.tex.level;
1265 unsigned pitch, slice;
1266 unsigned color_info;
1267 unsigned format, swap, ntype, endian;
1268 unsigned offset;
1269 unsigned tile_type;
1270 const struct util_format_description *desc;
1271 struct r600_bo *bo[3];
1272 int i;
1273
1274 surf = (struct r600_surface *)state->cbufs[cb];
1275 rtex = (struct r600_resource_texture*)state->cbufs[cb]->texture;
1276
1277 if (rtex->depth)
1278 rctx->have_depth_fb = TRUE;
1279
1280 if (rtex->depth && !rtex->is_flushing_texture) {
1281 r600_texture_depth_flush(&rctx->context, state->cbufs[cb]->texture, TRUE);
1282 rtex = rtex->flushed_depth_texture;
1283 }
1284
1285 rbuffer = &rtex->resource;
1286 bo[0] = rbuffer->bo;
1287 bo[1] = rbuffer->bo;
1288 bo[2] = rbuffer->bo;
1289
1290 /* XXX quite sure for dx10+ hw don't need any offset hacks */
1291 offset = r600_texture_get_offset((struct r600_resource_texture *)state->cbufs[cb]->texture,
1292 level, state->cbufs[cb]->u.tex.first_layer);
1293 pitch = rtex->pitch_in_blocks[level] / 8 - 1;
1294 slice = rtex->pitch_in_blocks[level] * surf->aligned_height / 64 - 1;
1295 desc = util_format_description(surf->base.format);
1296 for (i = 0; i < 4; i++) {
1297 if (desc->channel[i].type != UTIL_FORMAT_TYPE_VOID) {
1298 break;
1299 }
1300 }
1301 ntype = V_028C70_NUMBER_UNORM;
1302 if (desc->colorspace == UTIL_FORMAT_COLORSPACE_SRGB)
1303 ntype = V_028C70_NUMBER_SRGB;
1304 else if (desc->channel[i].type == UTIL_FORMAT_TYPE_SIGNED)
1305 ntype = V_028C70_NUMBER_SNORM;
1306
1307 format = r600_translate_colorformat(surf->base.format);
1308 swap = r600_translate_colorswap(surf->base.format);
1309 if (rbuffer->b.b.b.usage == PIPE_USAGE_STAGING) {
1310 endian = ENDIAN_NONE;
1311 } else {
1312 endian = r600_colorformat_endian_swap(format);
1313 }
1314
1315 /* disable when gallium grows int textures */
1316 if ((format == FMT_32_32_32_32 || format == FMT_16_16_16_16) && rtex->force_int_type)
1317 ntype = V_028C70_NUMBER_UINT;
1318
1319 color_info = S_028C70_FORMAT(format) |
1320 S_028C70_COMP_SWAP(swap) |
1321 S_028C70_ARRAY_MODE(rtex->array_mode[level]) |
1322 S_028C70_BLEND_CLAMP(1) |
1323 S_028C70_NUMBER_TYPE(ntype) |
1324 S_028C70_ENDIAN(endian);
1325
1326
1327 /* EXPORT_NORM is an optimzation that can be enabled for better
1328 * performance in certain cases.
1329 * EXPORT_NORM can be enabled if:
1330 * - 11-bit or smaller UNORM/SNORM/SRGB
1331 * - 16-bit or smaller FLOAT
1332 */
1333 /* FIXME: This should probably be the same for all CBs if we want
1334 * useful alpha tests. */
1335 if (desc->colorspace != UTIL_FORMAT_COLORSPACE_ZS &&
1336 ((desc->channel[i].size < 12 &&
1337 desc->channel[i].type != UTIL_FORMAT_TYPE_FLOAT &&
1338 ntype != V_028C70_NUMBER_UINT && ntype != V_028C70_NUMBER_SINT) ||
1339 (desc->channel[i].size < 17 &&
1340 desc->channel[i].type == UTIL_FORMAT_TYPE_FLOAT))) {
1341 color_info |= S_028C70_SOURCE_FORMAT(V_028C70_EXPORT_4C_16BPC);
1342 rctx->export_16bpc = true;
1343 } else {
1344 rctx->export_16bpc = false;
1345 }
1346 rctx->alpha_ref_dirty = true;
1347
1348 if (rtex->array_mode[level] > V_028C70_ARRAY_LINEAR_ALIGNED) {
1349 tile_type = rtex->tile_type;
1350 } else /* workaround for linear buffers */
1351 tile_type = 1;
1352
1353 /* FIXME handle enabling of CB beyond BASE8 which has different offset */
1354 r600_pipe_state_add_reg(rstate,
1355 R_028C60_CB_COLOR0_BASE + cb * 0x3C,
1356 offset >> 8, 0xFFFFFFFF, bo[0], RADEON_USAGE_READWRITE);
1357 r600_pipe_state_add_reg(rstate,
1358 R_028C78_CB_COLOR0_DIM + cb * 0x3C,
1359 0x0, 0xFFFFFFFF, NULL, 0);
1360 r600_pipe_state_add_reg(rstate,
1361 R_028C70_CB_COLOR0_INFO + cb * 0x3C,
1362 color_info, 0xFFFFFFFF, bo[0], RADEON_USAGE_READWRITE);
1363 r600_pipe_state_add_reg(rstate,
1364 R_028C64_CB_COLOR0_PITCH + cb * 0x3C,
1365 S_028C64_PITCH_TILE_MAX(pitch),
1366 0xFFFFFFFF, NULL, 0);
1367 r600_pipe_state_add_reg(rstate,
1368 R_028C68_CB_COLOR0_SLICE + cb * 0x3C,
1369 S_028C68_SLICE_TILE_MAX(slice),
1370 0xFFFFFFFF, NULL, 0);
1371 r600_pipe_state_add_reg(rstate,
1372 R_028C6C_CB_COLOR0_VIEW + cb * 0x3C,
1373 0x00000000, 0xFFFFFFFF, NULL, 0);
1374 r600_pipe_state_add_reg(rstate,
1375 R_028C74_CB_COLOR0_ATTRIB + cb * 0x3C,
1376 S_028C74_NON_DISP_TILING_ORDER(tile_type),
1377 0xFFFFFFFF, bo[0], RADEON_USAGE_READWRITE);
1378 }
1379
1380 static void evergreen_db(struct r600_pipe_context *rctx, struct r600_pipe_state *rstate,
1381 const struct pipe_framebuffer_state *state)
1382 {
1383 struct r600_resource_texture *rtex;
1384 struct r600_surface *surf;
1385 unsigned level, first_layer;
1386 unsigned pitch, slice, format;
1387 unsigned offset;
1388
1389 if (state->zsbuf == NULL)
1390 return;
1391
1392 surf = (struct r600_surface *)state->zsbuf;
1393 rtex = (struct r600_resource_texture*)surf->base.texture;
1394
1395 level = surf->base.u.tex.level;
1396 first_layer = surf->base.u.tex.first_layer;
1397 offset = r600_texture_get_offset(rtex, level, first_layer);
1398 pitch = rtex->pitch_in_blocks[level] / 8 - 1;
1399 slice = rtex->pitch_in_blocks[level] * surf->aligned_height / 64 - 1;
1400 format = r600_translate_dbformat(rtex->real_format);
1401
1402 r600_pipe_state_add_reg(rstate, R_028048_DB_Z_READ_BASE,
1403 offset >> 8, 0xFFFFFFFF, rtex->resource.bo, RADEON_USAGE_READWRITE);
1404 r600_pipe_state_add_reg(rstate, R_028050_DB_Z_WRITE_BASE,
1405 offset >> 8, 0xFFFFFFFF, rtex->resource.bo, RADEON_USAGE_READWRITE);
1406 r600_pipe_state_add_reg(rstate, R_028008_DB_DEPTH_VIEW, 0x00000000, 0xFFFFFFFF, NULL, 0);
1407
1408 if (rtex->stencil) {
1409 uint32_t stencil_offset =
1410 r600_texture_get_offset(rtex->stencil, level, first_layer);
1411
1412 r600_pipe_state_add_reg(rstate, R_02804C_DB_STENCIL_READ_BASE,
1413 stencil_offset >> 8, 0xFFFFFFFF, rtex->stencil->resource.bo, RADEON_USAGE_READWRITE);
1414 r600_pipe_state_add_reg(rstate, R_028054_DB_STENCIL_WRITE_BASE,
1415 stencil_offset >> 8, 0xFFFFFFFF, rtex->stencil->resource.bo, RADEON_USAGE_READWRITE);
1416 r600_pipe_state_add_reg(rstate, R_028044_DB_STENCIL_INFO,
1417 1, 0xFFFFFFFF, rtex->stencil->resource.bo, RADEON_USAGE_READWRITE);
1418 } else {
1419 r600_pipe_state_add_reg(rstate, R_028044_DB_STENCIL_INFO,
1420 0, 0xFFFFFFFF, NULL, RADEON_USAGE_READWRITE);
1421 }
1422
1423 r600_pipe_state_add_reg(rstate, R_028040_DB_Z_INFO,
1424 S_028040_ARRAY_MODE(rtex->array_mode[level]) | S_028040_FORMAT(format),
1425 0xFFFFFFFF, rtex->resource.bo, RADEON_USAGE_READWRITE);
1426 r600_pipe_state_add_reg(rstate, R_028058_DB_DEPTH_SIZE,
1427 S_028058_PITCH_TILE_MAX(pitch),
1428 0xFFFFFFFF, NULL, 0);
1429 r600_pipe_state_add_reg(rstate, R_02805C_DB_DEPTH_SLICE,
1430 S_02805C_SLICE_TILE_MAX(slice),
1431 0xFFFFFFFF, NULL, 0);
1432 }
1433
1434 static void evergreen_set_framebuffer_state(struct pipe_context *ctx,
1435 const struct pipe_framebuffer_state *state)
1436 {
1437 struct r600_pipe_context *rctx = (struct r600_pipe_context *)ctx;
1438 struct r600_pipe_state *rstate = CALLOC_STRUCT(r600_pipe_state);
1439 u32 shader_mask, tl, br, target_mask;
1440 int tl_x, tl_y, br_x, br_y;
1441
1442 if (rstate == NULL)
1443 return;
1444
1445 evergreen_context_flush_dest_caches(&rctx->ctx);
1446 rctx->ctx.num_dest_buffers = state->nr_cbufs;
1447
1448 /* unreference old buffer and reference new one */
1449 rstate->id = R600_PIPE_STATE_FRAMEBUFFER;
1450
1451 util_copy_framebuffer_state(&rctx->framebuffer, state);
1452
1453 /* build states */
1454 rctx->have_depth_fb = 0;
1455 rctx->nr_cbufs = state->nr_cbufs;
1456 for (int i = 0; i < state->nr_cbufs; i++) {
1457 evergreen_cb(rctx, rstate, state, i);
1458 }
1459 if (state->zsbuf) {
1460 evergreen_db(rctx, rstate, state);
1461 rctx->ctx.num_dest_buffers++;
1462 }
1463
1464 target_mask = 0x00000000;
1465 target_mask = 0xFFFFFFFF;
1466 shader_mask = 0;
1467 for (int i = 0; i < state->nr_cbufs; i++) {
1468 target_mask ^= 0xf << (i * 4);
1469 shader_mask |= 0xf << (i * 4);
1470 }
1471 tl_x = 0;
1472 tl_y = 0;
1473 br_x = state->width;
1474 br_y = state->height;
1475 /* EG hw workaround */
1476 if (br_x == 0)
1477 tl_x = 1;
1478 if (br_y == 0)
1479 tl_y = 1;
1480 /* cayman hw workaround */
1481 if (rctx->chip_class == CAYMAN) {
1482 if (br_x == 1 && br_y == 1)
1483 br_x = 2;
1484 }
1485 tl = S_028240_TL_X(tl_x) | S_028240_TL_Y(tl_y);
1486 br = S_028244_BR_X(br_x) | S_028244_BR_Y(br_y);
1487
1488 r600_pipe_state_add_reg(rstate,
1489 R_028240_PA_SC_GENERIC_SCISSOR_TL, tl,
1490 0xFFFFFFFF, NULL, 0);
1491 r600_pipe_state_add_reg(rstate,
1492 R_028244_PA_SC_GENERIC_SCISSOR_BR, br,
1493 0xFFFFFFFF, NULL, 0);
1494 r600_pipe_state_add_reg(rstate,
1495 R_028250_PA_SC_VPORT_SCISSOR_0_TL, tl,
1496 0xFFFFFFFF, NULL, 0);
1497 r600_pipe_state_add_reg(rstate,
1498 R_028254_PA_SC_VPORT_SCISSOR_0_BR, br,
1499 0xFFFFFFFF, NULL, 0);
1500 r600_pipe_state_add_reg(rstate,
1501 R_028030_PA_SC_SCREEN_SCISSOR_TL, tl,
1502 0xFFFFFFFF, NULL, 0);
1503 r600_pipe_state_add_reg(rstate,
1504 R_028034_PA_SC_SCREEN_SCISSOR_BR, br,
1505 0xFFFFFFFF, NULL, 0);
1506 r600_pipe_state_add_reg(rstate,
1507 R_028204_PA_SC_WINDOW_SCISSOR_TL, tl,
1508 0xFFFFFFFF, NULL, 0);
1509 r600_pipe_state_add_reg(rstate,
1510 R_028208_PA_SC_WINDOW_SCISSOR_BR, br,
1511 0xFFFFFFFF, NULL, 0);
1512 r600_pipe_state_add_reg(rstate,
1513 R_028200_PA_SC_WINDOW_OFFSET, 0x00000000,
1514 0xFFFFFFFF, NULL, 0);
1515 r600_pipe_state_add_reg(rstate,
1516 R_028230_PA_SC_EDGERULE, 0xAAAAAAAA,
1517 0xFFFFFFFF, NULL, 0);
1518
1519 r600_pipe_state_add_reg(rstate, R_028238_CB_TARGET_MASK,
1520 0x00000000, target_mask, NULL, 0);
1521 r600_pipe_state_add_reg(rstate, R_02823C_CB_SHADER_MASK,
1522 shader_mask, 0xFFFFFFFF, NULL, 0);
1523
1524
1525 if (rctx->chip_class == CAYMAN) {
1526 r600_pipe_state_add_reg(rstate, CM_R_028BE0_PA_SC_AA_CONFIG,
1527 0x00000000, 0xFFFFFFFF, NULL, 0);
1528 } else {
1529 r600_pipe_state_add_reg(rstate, R_028C04_PA_SC_AA_CONFIG,
1530 0x00000000, 0xFFFFFFFF, NULL, 0);
1531 r600_pipe_state_add_reg(rstate, R_028C1C_PA_SC_AA_SAMPLE_LOCS_MCTX,
1532 0x00000000, 0xFFFFFFFF, NULL, 0);
1533 }
1534
1535 free(rctx->states[R600_PIPE_STATE_FRAMEBUFFER]);
1536 rctx->states[R600_PIPE_STATE_FRAMEBUFFER] = rstate;
1537 r600_context_pipe_state_set(&rctx->ctx, rstate);
1538
1539 if (state->zsbuf) {
1540 evergreen_polygon_offset_update(rctx);
1541 }
1542 }
1543
1544 static void evergreen_texture_barrier(struct pipe_context *ctx)
1545 {
1546 struct r600_pipe_context *rctx = (struct r600_pipe_context *)ctx;
1547
1548 r600_context_flush_all(&rctx->ctx, S_0085F0_TC_ACTION_ENA(1) | S_0085F0_CB_ACTION_ENA(1) |
1549 S_0085F0_CB0_DEST_BASE_ENA(1) | S_0085F0_CB1_DEST_BASE_ENA(1) |
1550 S_0085F0_CB2_DEST_BASE_ENA(1) | S_0085F0_CB3_DEST_BASE_ENA(1) |
1551 S_0085F0_CB4_DEST_BASE_ENA(1) | S_0085F0_CB5_DEST_BASE_ENA(1) |
1552 S_0085F0_CB6_DEST_BASE_ENA(1) | S_0085F0_CB7_DEST_BASE_ENA(1) |
1553 S_0085F0_CB8_DEST_BASE_ENA(1) | S_0085F0_CB9_DEST_BASE_ENA(1) |
1554 S_0085F0_CB10_DEST_BASE_ENA(1) | S_0085F0_CB11_DEST_BASE_ENA(1));
1555 }
1556
1557 void evergreen_init_state_functions(struct r600_pipe_context *rctx)
1558 {
1559 rctx->context.create_blend_state = evergreen_create_blend_state;
1560 rctx->context.create_depth_stencil_alpha_state = evergreen_create_dsa_state;
1561 rctx->context.create_fs_state = r600_create_shader_state;
1562 rctx->context.create_rasterizer_state = evergreen_create_rs_state;
1563 rctx->context.create_sampler_state = evergreen_create_sampler_state;
1564 rctx->context.create_sampler_view = evergreen_create_sampler_view;
1565 rctx->context.create_vertex_elements_state = r600_create_vertex_elements;
1566 rctx->context.create_vs_state = r600_create_shader_state;
1567 rctx->context.bind_blend_state = r600_bind_blend_state;
1568 rctx->context.bind_depth_stencil_alpha_state = r600_bind_dsa_state;
1569 rctx->context.bind_fragment_sampler_states = evergreen_bind_ps_sampler;
1570 rctx->context.bind_fs_state = r600_bind_ps_shader;
1571 rctx->context.bind_rasterizer_state = r600_bind_rs_state;
1572 rctx->context.bind_vertex_elements_state = r600_bind_vertex_elements;
1573 rctx->context.bind_vertex_sampler_states = evergreen_bind_vs_sampler;
1574 rctx->context.bind_vs_state = r600_bind_vs_shader;
1575 rctx->context.delete_blend_state = r600_delete_state;
1576 rctx->context.delete_depth_stencil_alpha_state = r600_delete_state;
1577 rctx->context.delete_fs_state = r600_delete_ps_shader;
1578 rctx->context.delete_rasterizer_state = r600_delete_rs_state;
1579 rctx->context.delete_sampler_state = r600_delete_state;
1580 rctx->context.delete_vertex_elements_state = r600_delete_vertex_element;
1581 rctx->context.delete_vs_state = r600_delete_vs_shader;
1582 rctx->context.set_blend_color = evergreen_set_blend_color;
1583 rctx->context.set_clip_state = evergreen_set_clip_state;
1584 rctx->context.set_constant_buffer = r600_set_constant_buffer;
1585 rctx->context.set_fragment_sampler_views = evergreen_set_ps_sampler_view;
1586 rctx->context.set_framebuffer_state = evergreen_set_framebuffer_state;
1587 rctx->context.set_polygon_stipple = evergreen_set_polygon_stipple;
1588 rctx->context.set_sample_mask = evergreen_set_sample_mask;
1589 rctx->context.set_scissor_state = evergreen_set_scissor_state;
1590 rctx->context.set_stencil_ref = evergreen_set_stencil_ref;
1591 rctx->context.set_vertex_buffers = r600_set_vertex_buffers;
1592 rctx->context.set_index_buffer = r600_set_index_buffer;
1593 rctx->context.set_vertex_sampler_views = evergreen_set_vs_sampler_view;
1594 rctx->context.set_viewport_state = evergreen_set_viewport_state;
1595 rctx->context.sampler_view_destroy = r600_sampler_view_destroy;
1596 rctx->context.redefine_user_buffer = u_default_redefine_user_buffer;
1597 rctx->context.texture_barrier = evergreen_texture_barrier;
1598 }
1599
1600 static void cayman_init_config(struct r600_pipe_context *rctx)
1601 {
1602 struct r600_pipe_state *rstate = &rctx->config;
1603 unsigned tmp;
1604
1605 tmp = 0x00000000;
1606 tmp |= S_008C00_EXPORT_SRC_C(1);
1607 r600_pipe_state_add_reg(rstate, R_008C00_SQ_CONFIG, tmp, 0xFFFFFFFF, NULL, 0);
1608
1609 /* always set the temp clauses */
1610 r600_pipe_state_add_reg(rstate, R_008C04_SQ_GPR_RESOURCE_MGMT_1, S_008C04_NUM_CLAUSE_TEMP_GPRS(4), 0xFFFFFFFF, NULL, 0);
1611 r600_pipe_state_add_reg(rstate, R_008C10_SQ_GLOBAL_GPR_RESOURCE_MGMT_1, 0, 0xFFFFFFFF, NULL, 0);
1612 r600_pipe_state_add_reg(rstate, R_008C14_SQ_GLOBAL_GPR_RESOURCE_MGMT_2, 0, 0xFFFFFFFF, NULL, 0);
1613 r600_pipe_state_add_reg(rstate, R_008D8C_SQ_DYN_GPR_CNTL_PS_FLUSH_REQ, (1 << 8), 0xFFFFFFFF, NULL, 0);
1614
1615 r600_pipe_state_add_reg(rstate, R_028A48_PA_SC_MODE_CNTL_0, 0x0, 0xFFFFFFFF, NULL, 0);
1616 r600_pipe_state_add_reg(rstate, R_028A4C_PA_SC_MODE_CNTL_1, 0x0, 0xFFFFFFFF, NULL, 0);
1617
1618 r600_pipe_state_add_reg(rstate, R_028A10_VGT_OUTPUT_PATH_CNTL, 0x0, 0xFFFFFFFF, NULL, 0);
1619 r600_pipe_state_add_reg(rstate, R_028A14_VGT_HOS_CNTL, 0x0, 0xFFFFFFFF, NULL, 0);
1620 r600_pipe_state_add_reg(rstate, R_028A18_VGT_HOS_MAX_TESS_LEVEL, 0x0, 0xFFFFFFFF, NULL, 0);
1621 r600_pipe_state_add_reg(rstate, R_028A1C_VGT_HOS_MIN_TESS_LEVEL, 0x0, 0xFFFFFFFF, NULL, 0);
1622 r600_pipe_state_add_reg(rstate, R_028A20_VGT_HOS_REUSE_DEPTH, 0x0, 0xFFFFFFFF, NULL, 0);
1623 r600_pipe_state_add_reg(rstate, R_028A24_VGT_GROUP_PRIM_TYPE, 0x0, 0xFFFFFFFF, NULL, 0);
1624 r600_pipe_state_add_reg(rstate, R_028A28_VGT_GROUP_FIRST_DECR, 0x0, 0xFFFFFFFF, NULL, 0);
1625 r600_pipe_state_add_reg(rstate, R_028A2C_VGT_GROUP_DECR, 0x0, 0xFFFFFFFF, NULL, 0);
1626 r600_pipe_state_add_reg(rstate, R_028A30_VGT_GROUP_VECT_0_CNTL, 0x0, 0xFFFFFFFF, NULL, 0);
1627 r600_pipe_state_add_reg(rstate, R_028A34_VGT_GROUP_VECT_1_CNTL, 0x0, 0xFFFFFFFF, NULL, 0);
1628 r600_pipe_state_add_reg(rstate, R_028A38_VGT_GROUP_VECT_0_FMT_CNTL, 0x0, 0xFFFFFFFF, NULL, 0);
1629 r600_pipe_state_add_reg(rstate, R_028A3C_VGT_GROUP_VECT_1_FMT_CNTL, 0x0, 0xFFFFFFFF, NULL, 0);
1630 r600_pipe_state_add_reg(rstate, R_028A40_VGT_GS_MODE, 0x0, 0xFFFFFFFF, NULL, 0);
1631 r600_pipe_state_add_reg(rstate, R_028B94_VGT_STRMOUT_CONFIG, 0x0, 0xFFFFFFFF, NULL, 0);
1632 r600_pipe_state_add_reg(rstate, R_028B98_VGT_STRMOUT_BUFFER_CONFIG, 0x0, 0xFFFFFFFF, NULL, 0);
1633 r600_pipe_state_add_reg(rstate, R_028AB4_VGT_REUSE_OFF, 0x00000000, 0xFFFFFFFF, NULL, 0);
1634 r600_pipe_state_add_reg(rstate, R_028AB8_VGT_VTX_CNT_EN, 0x0, 0xFFFFFFFF, NULL, 0);
1635 r600_pipe_state_add_reg(rstate, R_008A14_PA_CL_ENHANCE, (3 << 1) | 1, 0xFFFFFFFF, NULL, 0);
1636
1637 r600_pipe_state_add_reg(rstate, R_028380_SQ_VTX_SEMANTIC_0, 0x0, 0xFFFFFFFF, NULL, 0);
1638 r600_pipe_state_add_reg(rstate, R_028384_SQ_VTX_SEMANTIC_1, 0x0, 0xFFFFFFFF, NULL, 0);
1639 r600_pipe_state_add_reg(rstate, R_028388_SQ_VTX_SEMANTIC_2, 0x0, 0xFFFFFFFF, NULL, 0);
1640 r600_pipe_state_add_reg(rstate, R_02838C_SQ_VTX_SEMANTIC_3, 0x0, 0xFFFFFFFF, NULL, 0);
1641 r600_pipe_state_add_reg(rstate, R_028390_SQ_VTX_SEMANTIC_4, 0x0, 0xFFFFFFFF, NULL, 0);
1642 r600_pipe_state_add_reg(rstate, R_028394_SQ_VTX_SEMANTIC_5, 0x0, 0xFFFFFFFF, NULL, 0);
1643 r600_pipe_state_add_reg(rstate, R_028398_SQ_VTX_SEMANTIC_6, 0x0, 0xFFFFFFFF, NULL, 0);
1644 r600_pipe_state_add_reg(rstate, R_02839C_SQ_VTX_SEMANTIC_7, 0x0, 0xFFFFFFFF, NULL, 0);
1645 r600_pipe_state_add_reg(rstate, R_0283A0_SQ_VTX_SEMANTIC_8, 0x0, 0xFFFFFFFF, NULL, 0);
1646 r600_pipe_state_add_reg(rstate, R_0283A4_SQ_VTX_SEMANTIC_9, 0x0, 0xFFFFFFFF, NULL, 0);
1647 r600_pipe_state_add_reg(rstate, R_0283A8_SQ_VTX_SEMANTIC_10, 0x0, 0xFFFFFFFF, NULL, 0);
1648 r600_pipe_state_add_reg(rstate, R_0283AC_SQ_VTX_SEMANTIC_11, 0x0, 0xFFFFFFFF, NULL, 0);
1649 r600_pipe_state_add_reg(rstate, R_0283B0_SQ_VTX_SEMANTIC_12, 0x0, 0xFFFFFFFF, NULL, 0);
1650 r600_pipe_state_add_reg(rstate, R_0283B4_SQ_VTX_SEMANTIC_13, 0x0, 0xFFFFFFFF, NULL, 0);
1651 r600_pipe_state_add_reg(rstate, R_0283B8_SQ_VTX_SEMANTIC_14, 0x0, 0xFFFFFFFF, NULL, 0);
1652 r600_pipe_state_add_reg(rstate, R_0283BC_SQ_VTX_SEMANTIC_15, 0x0, 0xFFFFFFFF, NULL, 0);
1653 r600_pipe_state_add_reg(rstate, R_0283C0_SQ_VTX_SEMANTIC_16, 0x0, 0xFFFFFFFF, NULL, 0);
1654 r600_pipe_state_add_reg(rstate, R_0283C4_SQ_VTX_SEMANTIC_17, 0x0, 0xFFFFFFFF, NULL, 0);
1655 r600_pipe_state_add_reg(rstate, R_0283C8_SQ_VTX_SEMANTIC_18, 0x0, 0xFFFFFFFF, NULL, 0);
1656 r600_pipe_state_add_reg(rstate, R_0283CC_SQ_VTX_SEMANTIC_19, 0x0, 0xFFFFFFFF, NULL, 0);
1657 r600_pipe_state_add_reg(rstate, R_0283D0_SQ_VTX_SEMANTIC_20, 0x0, 0xFFFFFFFF, NULL, 0);
1658 r600_pipe_state_add_reg(rstate, R_0283D4_SQ_VTX_SEMANTIC_21, 0x0, 0xFFFFFFFF, NULL, 0);
1659 r600_pipe_state_add_reg(rstate, R_0283D8_SQ_VTX_SEMANTIC_22, 0x0, 0xFFFFFFFF, NULL, 0);
1660 r600_pipe_state_add_reg(rstate, R_0283DC_SQ_VTX_SEMANTIC_23, 0x0, 0xFFFFFFFF, NULL, 0);
1661 r600_pipe_state_add_reg(rstate, R_0283E0_SQ_VTX_SEMANTIC_24, 0x0, 0xFFFFFFFF, NULL, 0);
1662 r600_pipe_state_add_reg(rstate, R_0283E4_SQ_VTX_SEMANTIC_25, 0x0, 0xFFFFFFFF, NULL, 0);
1663 r600_pipe_state_add_reg(rstate, R_0283E8_SQ_VTX_SEMANTIC_26, 0x0, 0xFFFFFFFF, NULL, 0);
1664 r600_pipe_state_add_reg(rstate, R_0283EC_SQ_VTX_SEMANTIC_27, 0x0, 0xFFFFFFFF, NULL, 0);
1665 r600_pipe_state_add_reg(rstate, R_0283F0_SQ_VTX_SEMANTIC_28, 0x0, 0xFFFFFFFF, NULL, 0);
1666 r600_pipe_state_add_reg(rstate, R_0283F4_SQ_VTX_SEMANTIC_29, 0x0, 0xFFFFFFFF, NULL, 0);
1667 r600_pipe_state_add_reg(rstate, R_0283F8_SQ_VTX_SEMANTIC_30, 0x0, 0xFFFFFFFF, NULL, 0);
1668 r600_pipe_state_add_reg(rstate, R_0283FC_SQ_VTX_SEMANTIC_31, 0x0, 0xFFFFFFFF, NULL, 0);
1669
1670 r600_pipe_state_add_reg(rstate, R_028810_PA_CL_CLIP_CNTL, 0x0, 0xFFFFFFFF, NULL, 0);
1671
1672 r600_pipe_state_add_reg(rstate, CM_R_028BD4_PA_SC_CENTROID_PRIORITY_0, 0x76543210, 0xffffffff, NULL, 0);
1673 r600_pipe_state_add_reg(rstate, CM_R_028BD8_PA_SC_CENTROID_PRIORITY_1, 0xfedcba98, 0xffffffff, NULL, 0);
1674
1675 r600_pipe_state_add_reg(rstate, CM_R_0288E8_SQ_LDS_ALLOC, 0, 0xFFFFFFFF, NULL, 0);
1676 r600_pipe_state_add_reg(rstate, R_0288EC_SQ_LDS_ALLOC_PS, 0, 0xFFFFFFFF, NULL, 0);
1677
1678 r600_pipe_state_add_reg(rstate, CM_R_028804_DB_EQAA, 0x110000, 0xFFFFFFFF, NULL, 0);
1679 r600_context_pipe_state_set(&rctx->ctx, rstate);
1680 }
1681
1682 void evergreen_init_config(struct r600_pipe_context *rctx)
1683 {
1684 struct r600_pipe_state *rstate = &rctx->config;
1685 int ps_prio;
1686 int vs_prio;
1687 int gs_prio;
1688 int es_prio;
1689 int hs_prio, cs_prio, ls_prio;
1690 int num_ps_gprs;
1691 int num_vs_gprs;
1692 int num_gs_gprs;
1693 int num_es_gprs;
1694 int num_hs_gprs;
1695 int num_ls_gprs;
1696 int num_temp_gprs;
1697 int num_ps_threads;
1698 int num_vs_threads;
1699 int num_gs_threads;
1700 int num_es_threads;
1701 int num_hs_threads;
1702 int num_ls_threads;
1703 int num_ps_stack_entries;
1704 int num_vs_stack_entries;
1705 int num_gs_stack_entries;
1706 int num_es_stack_entries;
1707 int num_hs_stack_entries;
1708 int num_ls_stack_entries;
1709 enum radeon_family family;
1710 unsigned tmp;
1711
1712 family = rctx->family;
1713
1714 if (rctx->chip_class == CAYMAN) {
1715 cayman_init_config(rctx);
1716 return;
1717 }
1718
1719 ps_prio = 0;
1720 vs_prio = 1;
1721 gs_prio = 2;
1722 es_prio = 3;
1723 hs_prio = 0;
1724 ls_prio = 0;
1725 cs_prio = 0;
1726
1727 switch (family) {
1728 case CHIP_CEDAR:
1729 default:
1730 num_ps_gprs = 93;
1731 num_vs_gprs = 46;
1732 num_temp_gprs = 4;
1733 num_gs_gprs = 31;
1734 num_es_gprs = 31;
1735 num_hs_gprs = 23;
1736 num_ls_gprs = 23;
1737 num_ps_threads = 96;
1738 num_vs_threads = 16;
1739 num_gs_threads = 16;
1740 num_es_threads = 16;
1741 num_hs_threads = 16;
1742 num_ls_threads = 16;
1743 num_ps_stack_entries = 42;
1744 num_vs_stack_entries = 42;
1745 num_gs_stack_entries = 42;
1746 num_es_stack_entries = 42;
1747 num_hs_stack_entries = 42;
1748 num_ls_stack_entries = 42;
1749 break;
1750 case CHIP_REDWOOD:
1751 num_ps_gprs = 93;
1752 num_vs_gprs = 46;
1753 num_temp_gprs = 4;
1754 num_gs_gprs = 31;
1755 num_es_gprs = 31;
1756 num_hs_gprs = 23;
1757 num_ls_gprs = 23;
1758 num_ps_threads = 128;
1759 num_vs_threads = 20;
1760 num_gs_threads = 20;
1761 num_es_threads = 20;
1762 num_hs_threads = 20;
1763 num_ls_threads = 20;
1764 num_ps_stack_entries = 42;
1765 num_vs_stack_entries = 42;
1766 num_gs_stack_entries = 42;
1767 num_es_stack_entries = 42;
1768 num_hs_stack_entries = 42;
1769 num_ls_stack_entries = 42;
1770 break;
1771 case CHIP_JUNIPER:
1772 num_ps_gprs = 93;
1773 num_vs_gprs = 46;
1774 num_temp_gprs = 4;
1775 num_gs_gprs = 31;
1776 num_es_gprs = 31;
1777 num_hs_gprs = 23;
1778 num_ls_gprs = 23;
1779 num_ps_threads = 128;
1780 num_vs_threads = 20;
1781 num_gs_threads = 20;
1782 num_es_threads = 20;
1783 num_hs_threads = 20;
1784 num_ls_threads = 20;
1785 num_ps_stack_entries = 85;
1786 num_vs_stack_entries = 85;
1787 num_gs_stack_entries = 85;
1788 num_es_stack_entries = 85;
1789 num_hs_stack_entries = 85;
1790 num_ls_stack_entries = 85;
1791 break;
1792 case CHIP_CYPRESS:
1793 case CHIP_HEMLOCK:
1794 num_ps_gprs = 93;
1795 num_vs_gprs = 46;
1796 num_temp_gprs = 4;
1797 num_gs_gprs = 31;
1798 num_es_gprs = 31;
1799 num_hs_gprs = 23;
1800 num_ls_gprs = 23;
1801 num_ps_threads = 128;
1802 num_vs_threads = 20;
1803 num_gs_threads = 20;
1804 num_es_threads = 20;
1805 num_hs_threads = 20;
1806 num_ls_threads = 20;
1807 num_ps_stack_entries = 85;
1808 num_vs_stack_entries = 85;
1809 num_gs_stack_entries = 85;
1810 num_es_stack_entries = 85;
1811 num_hs_stack_entries = 85;
1812 num_ls_stack_entries = 85;
1813 break;
1814 case CHIP_PALM:
1815 num_ps_gprs = 93;
1816 num_vs_gprs = 46;
1817 num_temp_gprs = 4;
1818 num_gs_gprs = 31;
1819 num_es_gprs = 31;
1820 num_hs_gprs = 23;
1821 num_ls_gprs = 23;
1822 num_ps_threads = 96;
1823 num_vs_threads = 16;
1824 num_gs_threads = 16;
1825 num_es_threads = 16;
1826 num_hs_threads = 16;
1827 num_ls_threads = 16;
1828 num_ps_stack_entries = 42;
1829 num_vs_stack_entries = 42;
1830 num_gs_stack_entries = 42;
1831 num_es_stack_entries = 42;
1832 num_hs_stack_entries = 42;
1833 num_ls_stack_entries = 42;
1834 break;
1835 case CHIP_SUMO:
1836 num_ps_gprs = 93;
1837 num_vs_gprs = 46;
1838 num_temp_gprs = 4;
1839 num_gs_gprs = 31;
1840 num_es_gprs = 31;
1841 num_hs_gprs = 23;
1842 num_ls_gprs = 23;
1843 num_ps_threads = 96;
1844 num_vs_threads = 25;
1845 num_gs_threads = 25;
1846 num_es_threads = 25;
1847 num_hs_threads = 25;
1848 num_ls_threads = 25;
1849 num_ps_stack_entries = 42;
1850 num_vs_stack_entries = 42;
1851 num_gs_stack_entries = 42;
1852 num_es_stack_entries = 42;
1853 num_hs_stack_entries = 42;
1854 num_ls_stack_entries = 42;
1855 break;
1856 case CHIP_SUMO2:
1857 num_ps_gprs = 93;
1858 num_vs_gprs = 46;
1859 num_temp_gprs = 4;
1860 num_gs_gprs = 31;
1861 num_es_gprs = 31;
1862 num_hs_gprs = 23;
1863 num_ls_gprs = 23;
1864 num_ps_threads = 96;
1865 num_vs_threads = 25;
1866 num_gs_threads = 25;
1867 num_es_threads = 25;
1868 num_hs_threads = 25;
1869 num_ls_threads = 25;
1870 num_ps_stack_entries = 85;
1871 num_vs_stack_entries = 85;
1872 num_gs_stack_entries = 85;
1873 num_es_stack_entries = 85;
1874 num_hs_stack_entries = 85;
1875 num_ls_stack_entries = 85;
1876 break;
1877 case CHIP_BARTS:
1878 num_ps_gprs = 93;
1879 num_vs_gprs = 46;
1880 num_temp_gprs = 4;
1881 num_gs_gprs = 31;
1882 num_es_gprs = 31;
1883 num_hs_gprs = 23;
1884 num_ls_gprs = 23;
1885 num_ps_threads = 128;
1886 num_vs_threads = 20;
1887 num_gs_threads = 20;
1888 num_es_threads = 20;
1889 num_hs_threads = 20;
1890 num_ls_threads = 20;
1891 num_ps_stack_entries = 85;
1892 num_vs_stack_entries = 85;
1893 num_gs_stack_entries = 85;
1894 num_es_stack_entries = 85;
1895 num_hs_stack_entries = 85;
1896 num_ls_stack_entries = 85;
1897 break;
1898 case CHIP_TURKS:
1899 num_ps_gprs = 93;
1900 num_vs_gprs = 46;
1901 num_temp_gprs = 4;
1902 num_gs_gprs = 31;
1903 num_es_gprs = 31;
1904 num_hs_gprs = 23;
1905 num_ls_gprs = 23;
1906 num_ps_threads = 128;
1907 num_vs_threads = 20;
1908 num_gs_threads = 20;
1909 num_es_threads = 20;
1910 num_hs_threads = 20;
1911 num_ls_threads = 20;
1912 num_ps_stack_entries = 42;
1913 num_vs_stack_entries = 42;
1914 num_gs_stack_entries = 42;
1915 num_es_stack_entries = 42;
1916 num_hs_stack_entries = 42;
1917 num_ls_stack_entries = 42;
1918 break;
1919 case CHIP_CAICOS:
1920 num_ps_gprs = 93;
1921 num_vs_gprs = 46;
1922 num_temp_gprs = 4;
1923 num_gs_gprs = 31;
1924 num_es_gprs = 31;
1925 num_hs_gprs = 23;
1926 num_ls_gprs = 23;
1927 num_ps_threads = 128;
1928 num_vs_threads = 10;
1929 num_gs_threads = 10;
1930 num_es_threads = 10;
1931 num_hs_threads = 10;
1932 num_ls_threads = 10;
1933 num_ps_stack_entries = 42;
1934 num_vs_stack_entries = 42;
1935 num_gs_stack_entries = 42;
1936 num_es_stack_entries = 42;
1937 num_hs_stack_entries = 42;
1938 num_ls_stack_entries = 42;
1939 break;
1940 }
1941
1942 tmp = 0x00000000;
1943 switch (family) {
1944 case CHIP_CEDAR:
1945 case CHIP_PALM:
1946 case CHIP_SUMO:
1947 case CHIP_SUMO2:
1948 case CHIP_CAICOS:
1949 break;
1950 default:
1951 tmp |= S_008C00_VC_ENABLE(1);
1952 break;
1953 }
1954 tmp |= S_008C00_EXPORT_SRC_C(1);
1955 tmp |= S_008C00_CS_PRIO(cs_prio);
1956 tmp |= S_008C00_LS_PRIO(ls_prio);
1957 tmp |= S_008C00_HS_PRIO(hs_prio);
1958 tmp |= S_008C00_PS_PRIO(ps_prio);
1959 tmp |= S_008C00_VS_PRIO(vs_prio);
1960 tmp |= S_008C00_GS_PRIO(gs_prio);
1961 tmp |= S_008C00_ES_PRIO(es_prio);
1962 r600_pipe_state_add_reg(rstate, R_008C00_SQ_CONFIG, tmp, 0xFFFFFFFF, NULL, 0);
1963
1964 /* enable dynamic GPR resource management */
1965 if (r600_get_minor_version(rctx->radeon) >= 7) {
1966 /* always set temp clauses */
1967 r600_pipe_state_add_reg(rstate, R_008C04_SQ_GPR_RESOURCE_MGMT_1,
1968 S_008C04_NUM_CLAUSE_TEMP_GPRS(num_temp_gprs), 0xFFFFFFFF, NULL, 0);
1969 r600_pipe_state_add_reg(rstate, R_008C10_SQ_GLOBAL_GPR_RESOURCE_MGMT_1, 0, 0xFFFFFFFF, NULL, 0);
1970 r600_pipe_state_add_reg(rstate, R_008C14_SQ_GLOBAL_GPR_RESOURCE_MGMT_2, 0, 0xFFFFFFFF, NULL, 0);
1971 r600_pipe_state_add_reg(rstate, R_008D8C_SQ_DYN_GPR_CNTL_PS_FLUSH_REQ, (1 << 8), 0xFFFFFFFF, NULL, 0);
1972 r600_pipe_state_add_reg(rstate, R_028838_SQ_DYN_GPR_RESOURCE_LIMIT_1,
1973 S_028838_PS_GPRS(0x1e) |
1974 S_028838_VS_GPRS(0x1e) |
1975 S_028838_GS_GPRS(0x1e) |
1976 S_028838_ES_GPRS(0x1e) |
1977 S_028838_HS_GPRS(0x1e) |
1978 S_028838_LS_GPRS(0x1e), 0xFFFFFFFF, NULL, 0); /* workaround for hw issues with dyn gpr - must set all limits to 240 instead of 0, 0x1e == 240 / 8*/
1979 } else {
1980 tmp = 0;
1981 tmp |= S_008C04_NUM_PS_GPRS(num_ps_gprs);
1982 tmp |= S_008C04_NUM_VS_GPRS(num_vs_gprs);
1983 tmp |= S_008C04_NUM_CLAUSE_TEMP_GPRS(num_temp_gprs);
1984 r600_pipe_state_add_reg(rstate, R_008C04_SQ_GPR_RESOURCE_MGMT_1, tmp, 0xFFFFFFFF, NULL, 0);
1985
1986 tmp = 0;
1987 tmp |= S_008C08_NUM_GS_GPRS(num_gs_gprs);
1988 tmp |= S_008C08_NUM_ES_GPRS(num_es_gprs);
1989 r600_pipe_state_add_reg(rstate, R_008C08_SQ_GPR_RESOURCE_MGMT_2, tmp, 0xFFFFFFFF, NULL, 0);
1990
1991 tmp = 0;
1992 tmp |= S_008C0C_NUM_HS_GPRS(num_hs_gprs);
1993 tmp |= S_008C0C_NUM_HS_GPRS(num_ls_gprs);
1994 r600_pipe_state_add_reg(rstate, R_008C0C_SQ_GPR_RESOURCE_MGMT_3, tmp, 0xFFFFFFFF, NULL, 0);
1995 }
1996
1997 tmp = 0;
1998 tmp |= S_008C18_NUM_PS_THREADS(num_ps_threads);
1999 tmp |= S_008C18_NUM_VS_THREADS(num_vs_threads);
2000 tmp |= S_008C18_NUM_GS_THREADS(num_gs_threads);
2001 tmp |= S_008C18_NUM_ES_THREADS(num_es_threads);
2002 r600_pipe_state_add_reg(rstate, R_008C18_SQ_THREAD_RESOURCE_MGMT_1, tmp, 0xFFFFFFFF, NULL, 0);
2003
2004 tmp = 0;
2005 tmp |= S_008C1C_NUM_HS_THREADS(num_hs_threads);
2006 tmp |= S_008C1C_NUM_LS_THREADS(num_ls_threads);
2007 r600_pipe_state_add_reg(rstate, R_008C1C_SQ_THREAD_RESOURCE_MGMT_2, tmp, 0xFFFFFFFF, NULL, 0);
2008
2009 tmp = 0;
2010 tmp |= S_008C20_NUM_PS_STACK_ENTRIES(num_ps_stack_entries);
2011 tmp |= S_008C20_NUM_VS_STACK_ENTRIES(num_vs_stack_entries);
2012 r600_pipe_state_add_reg(rstate, R_008C20_SQ_STACK_RESOURCE_MGMT_1, tmp, 0xFFFFFFFF, NULL, 0);
2013
2014 tmp = 0;
2015 tmp |= S_008C24_NUM_GS_STACK_ENTRIES(num_gs_stack_entries);
2016 tmp |= S_008C24_NUM_ES_STACK_ENTRIES(num_es_stack_entries);
2017 r600_pipe_state_add_reg(rstate, R_008C24_SQ_STACK_RESOURCE_MGMT_2, tmp, 0xFFFFFFFF, NULL, 0);
2018
2019 tmp = 0;
2020 tmp |= S_008C28_NUM_HS_STACK_ENTRIES(num_hs_stack_entries);
2021 tmp |= S_008C28_NUM_LS_STACK_ENTRIES(num_ls_stack_entries);
2022 r600_pipe_state_add_reg(rstate, R_008C28_SQ_STACK_RESOURCE_MGMT_3, tmp, 0xFFFFFFFF, NULL, 0);
2023
2024 tmp = 0;
2025 tmp |= S_008E2C_NUM_PS_LDS(0x1000);
2026 tmp |= S_008E2C_NUM_LS_LDS(0x1000);
2027 r600_pipe_state_add_reg(rstate, R_008E2C_SQ_LDS_RESOURCE_MGMT, tmp, 0xFFFFFFFF, NULL, 0);
2028
2029 r600_pipe_state_add_reg(rstate, R_009100_SPI_CONFIG_CNTL, 0x0, 0xFFFFFFFF, NULL, 0);
2030 r600_pipe_state_add_reg(rstate, R_00913C_SPI_CONFIG_CNTL_1, S_00913C_VTX_DONE_DELAY(4), 0xFFFFFFFF, NULL, 0);
2031
2032 #if 0
2033 r600_pipe_state_add_reg(rstate, R_028350_SX_MISC, 0x0, 0xFFFFFFFF, NULL, 0);
2034
2035 r600_pipe_state_add_reg(rstate, R_008D8C_SQ_DYN_GPR_CNTL_PS_FLUSH_REQ, 0x0, 0xFFFFFFFF, NULL, 0);
2036 #endif
2037 r600_pipe_state_add_reg(rstate, R_028A48_PA_SC_MODE_CNTL_0, 0x0, 0xFFFFFFFF, NULL, 0);
2038 r600_pipe_state_add_reg(rstate, R_028A4C_PA_SC_MODE_CNTL_1, 0x0, 0xFFFFFFFF, NULL, 0);
2039
2040 r600_pipe_state_add_reg(rstate, R_028900_SQ_ESGS_RING_ITEMSIZE, 0x0, 0xFFFFFFFF, NULL, 0);
2041 r600_pipe_state_add_reg(rstate, R_028904_SQ_GSVS_RING_ITEMSIZE, 0x0, 0xFFFFFFFF, NULL, 0);
2042 r600_pipe_state_add_reg(rstate, R_028908_SQ_ESTMP_RING_ITEMSIZE, 0x0, 0xFFFFFFFF, NULL, 0);
2043 r600_pipe_state_add_reg(rstate, R_02890C_SQ_GSTMP_RING_ITEMSIZE, 0x0, 0xFFFFFFFF, NULL, 0);
2044 r600_pipe_state_add_reg(rstate, R_028910_SQ_VSTMP_RING_ITEMSIZE, 0x0, 0xFFFFFFFF, NULL, 0);
2045 r600_pipe_state_add_reg(rstate, R_028914_SQ_PSTMP_RING_ITEMSIZE, 0x0, 0xFFFFFFFF, NULL, 0);
2046
2047 r600_pipe_state_add_reg(rstate, R_02891C_SQ_GS_VERT_ITEMSIZE, 0x0, 0xFFFFFFFF, NULL, 0);
2048 r600_pipe_state_add_reg(rstate, R_028920_SQ_GS_VERT_ITEMSIZE_1, 0x0, 0xFFFFFFFF, NULL, 0);
2049 r600_pipe_state_add_reg(rstate, R_028924_SQ_GS_VERT_ITEMSIZE_2, 0x0, 0xFFFFFFFF, NULL, 0);
2050 r600_pipe_state_add_reg(rstate, R_028928_SQ_GS_VERT_ITEMSIZE_3, 0x0, 0xFFFFFFFF, NULL, 0);
2051
2052 r600_pipe_state_add_reg(rstate, R_028A10_VGT_OUTPUT_PATH_CNTL, 0x0, 0xFFFFFFFF, NULL, 0);
2053 r600_pipe_state_add_reg(rstate, R_028A14_VGT_HOS_CNTL, 0x0, 0xFFFFFFFF, NULL, 0);
2054 r600_pipe_state_add_reg(rstate, R_028A18_VGT_HOS_MAX_TESS_LEVEL, 0x0, 0xFFFFFFFF, NULL, 0);
2055 r600_pipe_state_add_reg(rstate, R_028A1C_VGT_HOS_MIN_TESS_LEVEL, 0x0, 0xFFFFFFFF, NULL, 0);
2056 r600_pipe_state_add_reg(rstate, R_028A20_VGT_HOS_REUSE_DEPTH, 0x0, 0xFFFFFFFF, NULL, 0);
2057 r600_pipe_state_add_reg(rstate, R_028A24_VGT_GROUP_PRIM_TYPE, 0x0, 0xFFFFFFFF, NULL, 0);
2058 r600_pipe_state_add_reg(rstate, R_028A28_VGT_GROUP_FIRST_DECR, 0x0, 0xFFFFFFFF, NULL, 0);
2059 r600_pipe_state_add_reg(rstate, R_028A2C_VGT_GROUP_DECR, 0x0, 0xFFFFFFFF, NULL, 0);
2060 r600_pipe_state_add_reg(rstate, R_028A30_VGT_GROUP_VECT_0_CNTL, 0x0, 0xFFFFFFFF, NULL, 0);
2061 r600_pipe_state_add_reg(rstate, R_028A34_VGT_GROUP_VECT_1_CNTL, 0x0, 0xFFFFFFFF, NULL, 0);
2062 r600_pipe_state_add_reg(rstate, R_028A38_VGT_GROUP_VECT_0_FMT_CNTL, 0x0, 0xFFFFFFFF, NULL, 0);
2063 r600_pipe_state_add_reg(rstate, R_028A3C_VGT_GROUP_VECT_1_FMT_CNTL, 0x0, 0xFFFFFFFF, NULL, 0);
2064 r600_pipe_state_add_reg(rstate, R_028A40_VGT_GS_MODE, 0x0, 0xFFFFFFFF, NULL, 0);
2065 r600_pipe_state_add_reg(rstate, R_028B94_VGT_STRMOUT_CONFIG, 0x0, 0xFFFFFFFF, NULL, 0);
2066 r600_pipe_state_add_reg(rstate, R_028B98_VGT_STRMOUT_BUFFER_CONFIG, 0x0, 0xFFFFFFFF, NULL, 0);
2067 r600_pipe_state_add_reg(rstate, R_028AB4_VGT_REUSE_OFF, 0x00000000, 0xFFFFFFFF, NULL, 0);
2068 r600_pipe_state_add_reg(rstate, R_028AB8_VGT_VTX_CNT_EN, 0x0, 0xFFFFFFFF, NULL, 0);
2069 r600_pipe_state_add_reg(rstate, R_008A14_PA_CL_ENHANCE, (3 << 1) | 1, 0xFFFFFFFF, NULL, 0);
2070
2071 r600_pipe_state_add_reg(rstate, R_028380_SQ_VTX_SEMANTIC_0, 0x0, 0xFFFFFFFF, NULL, 0);
2072 r600_pipe_state_add_reg(rstate, R_028384_SQ_VTX_SEMANTIC_1, 0x0, 0xFFFFFFFF, NULL, 0);
2073 r600_pipe_state_add_reg(rstate, R_028388_SQ_VTX_SEMANTIC_2, 0x0, 0xFFFFFFFF, NULL, 0);
2074 r600_pipe_state_add_reg(rstate, R_02838C_SQ_VTX_SEMANTIC_3, 0x0, 0xFFFFFFFF, NULL, 0);
2075 r600_pipe_state_add_reg(rstate, R_028390_SQ_VTX_SEMANTIC_4, 0x0, 0xFFFFFFFF, NULL, 0);
2076 r600_pipe_state_add_reg(rstate, R_028394_SQ_VTX_SEMANTIC_5, 0x0, 0xFFFFFFFF, NULL, 0);
2077 r600_pipe_state_add_reg(rstate, R_028398_SQ_VTX_SEMANTIC_6, 0x0, 0xFFFFFFFF, NULL, 0);
2078 r600_pipe_state_add_reg(rstate, R_02839C_SQ_VTX_SEMANTIC_7, 0x0, 0xFFFFFFFF, NULL, 0);
2079 r600_pipe_state_add_reg(rstate, R_0283A0_SQ_VTX_SEMANTIC_8, 0x0, 0xFFFFFFFF, NULL, 0);
2080 r600_pipe_state_add_reg(rstate, R_0283A4_SQ_VTX_SEMANTIC_9, 0x0, 0xFFFFFFFF, NULL, 0);
2081 r600_pipe_state_add_reg(rstate, R_0283A8_SQ_VTX_SEMANTIC_10, 0x0, 0xFFFFFFFF, NULL, 0);
2082 r600_pipe_state_add_reg(rstate, R_0283AC_SQ_VTX_SEMANTIC_11, 0x0, 0xFFFFFFFF, NULL, 0);
2083 r600_pipe_state_add_reg(rstate, R_0283B0_SQ_VTX_SEMANTIC_12, 0x0, 0xFFFFFFFF, NULL, 0);
2084 r600_pipe_state_add_reg(rstate, R_0283B4_SQ_VTX_SEMANTIC_13, 0x0, 0xFFFFFFFF, NULL, 0);
2085 r600_pipe_state_add_reg(rstate, R_0283B8_SQ_VTX_SEMANTIC_14, 0x0, 0xFFFFFFFF, NULL, 0);
2086 r600_pipe_state_add_reg(rstate, R_0283BC_SQ_VTX_SEMANTIC_15, 0x0, 0xFFFFFFFF, NULL, 0);
2087 r600_pipe_state_add_reg(rstate, R_0283C0_SQ_VTX_SEMANTIC_16, 0x0, 0xFFFFFFFF, NULL, 0);
2088 r600_pipe_state_add_reg(rstate, R_0283C4_SQ_VTX_SEMANTIC_17, 0x0, 0xFFFFFFFF, NULL, 0);
2089 r600_pipe_state_add_reg(rstate, R_0283C8_SQ_VTX_SEMANTIC_18, 0x0, 0xFFFFFFFF, NULL, 0);
2090 r600_pipe_state_add_reg(rstate, R_0283CC_SQ_VTX_SEMANTIC_19, 0x0, 0xFFFFFFFF, NULL, 0);
2091 r600_pipe_state_add_reg(rstate, R_0283D0_SQ_VTX_SEMANTIC_20, 0x0, 0xFFFFFFFF, NULL, 0);
2092 r600_pipe_state_add_reg(rstate, R_0283D4_SQ_VTX_SEMANTIC_21, 0x0, 0xFFFFFFFF, NULL, 0);
2093 r600_pipe_state_add_reg(rstate, R_0283D8_SQ_VTX_SEMANTIC_22, 0x0, 0xFFFFFFFF, NULL, 0);
2094 r600_pipe_state_add_reg(rstate, R_0283DC_SQ_VTX_SEMANTIC_23, 0x0, 0xFFFFFFFF, NULL, 0);
2095 r600_pipe_state_add_reg(rstate, R_0283E0_SQ_VTX_SEMANTIC_24, 0x0, 0xFFFFFFFF, NULL, 0);
2096 r600_pipe_state_add_reg(rstate, R_0283E4_SQ_VTX_SEMANTIC_25, 0x0, 0xFFFFFFFF, NULL, 0);
2097 r600_pipe_state_add_reg(rstate, R_0283E8_SQ_VTX_SEMANTIC_26, 0x0, 0xFFFFFFFF, NULL, 0);
2098 r600_pipe_state_add_reg(rstate, R_0283EC_SQ_VTX_SEMANTIC_27, 0x0, 0xFFFFFFFF, NULL, 0);
2099 r600_pipe_state_add_reg(rstate, R_0283F0_SQ_VTX_SEMANTIC_28, 0x0, 0xFFFFFFFF, NULL, 0);
2100 r600_pipe_state_add_reg(rstate, R_0283F4_SQ_VTX_SEMANTIC_29, 0x0, 0xFFFFFFFF, NULL, 0);
2101 r600_pipe_state_add_reg(rstate, R_0283F8_SQ_VTX_SEMANTIC_30, 0x0, 0xFFFFFFFF, NULL, 0);
2102 r600_pipe_state_add_reg(rstate, R_0283FC_SQ_VTX_SEMANTIC_31, 0x0, 0xFFFFFFFF, NULL, 0);
2103
2104 r600_pipe_state_add_reg(rstate, R_028810_PA_CL_CLIP_CNTL, 0x0, 0xFFFFFFFF, NULL, 0);
2105
2106 r600_context_pipe_state_set(&rctx->ctx, rstate);
2107 }
2108
2109 void evergreen_polygon_offset_update(struct r600_pipe_context *rctx)
2110 {
2111 struct r600_pipe_state state;
2112
2113 state.id = R600_PIPE_STATE_POLYGON_OFFSET;
2114 state.nregs = 0;
2115 if (rctx->rasterizer && rctx->framebuffer.zsbuf) {
2116 float offset_units = rctx->rasterizer->offset_units;
2117 unsigned offset_db_fmt_cntl = 0, depth;
2118
2119 switch (rctx->framebuffer.zsbuf->texture->format) {
2120 case PIPE_FORMAT_Z24X8_UNORM:
2121 case PIPE_FORMAT_Z24_UNORM_S8_USCALED:
2122 depth = -24;
2123 offset_units *= 2.0f;
2124 break;
2125 case PIPE_FORMAT_Z32_FLOAT:
2126 case PIPE_FORMAT_Z32_FLOAT_S8X24_USCALED:
2127 depth = -23;
2128 offset_units *= 1.0f;
2129 offset_db_fmt_cntl |= S_028B78_POLY_OFFSET_DB_IS_FLOAT_FMT(1);
2130 break;
2131 case PIPE_FORMAT_Z16_UNORM:
2132 depth = -16;
2133 offset_units *= 4.0f;
2134 break;
2135 default:
2136 return;
2137 }
2138 /* FIXME some of those reg can be computed with cso */
2139 offset_db_fmt_cntl |= S_028B78_POLY_OFFSET_NEG_NUM_DB_BITS(depth);
2140 r600_pipe_state_add_reg(&state,
2141 R_028B80_PA_SU_POLY_OFFSET_FRONT_SCALE,
2142 fui(rctx->rasterizer->offset_scale), 0xFFFFFFFF, NULL, 0);
2143 r600_pipe_state_add_reg(&state,
2144 R_028B84_PA_SU_POLY_OFFSET_FRONT_OFFSET,
2145 fui(offset_units), 0xFFFFFFFF, NULL, 0);
2146 r600_pipe_state_add_reg(&state,
2147 R_028B88_PA_SU_POLY_OFFSET_BACK_SCALE,
2148 fui(rctx->rasterizer->offset_scale), 0xFFFFFFFF, NULL, 0);
2149 r600_pipe_state_add_reg(&state,
2150 R_028B8C_PA_SU_POLY_OFFSET_BACK_OFFSET,
2151 fui(offset_units), 0xFFFFFFFF, NULL, 0);
2152 r600_pipe_state_add_reg(&state,
2153 R_028B78_PA_SU_POLY_OFFSET_DB_FMT_CNTL,
2154 offset_db_fmt_cntl, 0xFFFFFFFF, NULL, 0);
2155 r600_context_pipe_state_set(&rctx->ctx, &state);
2156 }
2157 }
2158
2159 void evergreen_pipe_shader_ps(struct pipe_context *ctx, struct r600_pipe_shader *shader)
2160 {
2161 struct r600_pipe_context *rctx = (struct r600_pipe_context *)ctx;
2162 struct r600_pipe_state *rstate = &shader->rstate;
2163 struct r600_shader *rshader = &shader->shader;
2164 unsigned i, exports_ps, num_cout, spi_ps_in_control_0, spi_input_z, spi_ps_in_control_1, db_shader_control;
2165 int pos_index = -1, face_index = -1;
2166 int ninterp = 0;
2167 boolean have_linear = FALSE, have_centroid = FALSE, have_perspective = FALSE;
2168 unsigned spi_baryc_cntl;
2169
2170 rstate->nregs = 0;
2171
2172 db_shader_control = 0;
2173 for (i = 0; i < rshader->ninput; i++) {
2174 /* evergreen NUM_INTERP only contains values interpolated into the LDS,
2175 POSITION goes via GPRs from the SC so isn't counted */
2176 if (rshader->input[i].name == TGSI_SEMANTIC_POSITION)
2177 pos_index = i;
2178 else if (rshader->input[i].name == TGSI_SEMANTIC_FACE)
2179 face_index = i;
2180 else {
2181 if (rshader->input[i].interpolate == TGSI_INTERPOLATE_LINEAR ||
2182 rshader->input[i].interpolate == TGSI_INTERPOLATE_PERSPECTIVE)
2183 ninterp++;
2184 if (rshader->input[i].interpolate == TGSI_INTERPOLATE_LINEAR)
2185 have_linear = TRUE;
2186 if (rshader->input[i].interpolate == TGSI_INTERPOLATE_PERSPECTIVE)
2187 have_perspective = TRUE;
2188 if (rshader->input[i].centroid)
2189 have_centroid = TRUE;
2190 }
2191 }
2192 for (i = 0; i < rshader->noutput; i++) {
2193 if (rshader->output[i].name == TGSI_SEMANTIC_POSITION)
2194 db_shader_control |= S_02880C_Z_EXPORT_ENABLE(1);
2195 if (rshader->output[i].name == TGSI_SEMANTIC_STENCIL)
2196 db_shader_control |= S_02880C_STENCIL_EXPORT_ENABLE(1);
2197 }
2198 if (rshader->uses_kill)
2199 db_shader_control |= S_02880C_KILL_ENABLE(1);
2200
2201 exports_ps = 0;
2202 num_cout = 0;
2203 for (i = 0; i < rshader->noutput; i++) {
2204 if (rshader->output[i].name == TGSI_SEMANTIC_POSITION ||
2205 rshader->output[i].name == TGSI_SEMANTIC_STENCIL)
2206 exports_ps |= 1;
2207 else if (rshader->output[i].name == TGSI_SEMANTIC_COLOR) {
2208 if (rshader->fs_write_all)
2209 num_cout = rshader->nr_cbufs;
2210 else
2211 num_cout++;
2212 }
2213 }
2214 exports_ps |= S_02884C_EXPORT_COLORS(num_cout);
2215 if (!exports_ps) {
2216 /* always at least export 1 component per pixel */
2217 exports_ps = 2;
2218 }
2219
2220 if (ninterp == 0) {
2221 ninterp = 1;
2222 have_perspective = TRUE;
2223 }
2224
2225 spi_ps_in_control_0 = S_0286CC_NUM_INTERP(ninterp) |
2226 S_0286CC_PERSP_GRADIENT_ENA(have_perspective) |
2227 S_0286CC_LINEAR_GRADIENT_ENA(have_linear);
2228 spi_input_z = 0;
2229 if (pos_index != -1) {
2230 spi_ps_in_control_0 |= S_0286CC_POSITION_ENA(1) |
2231 S_0286CC_POSITION_CENTROID(rshader->input[pos_index].centroid) |
2232 S_0286CC_POSITION_ADDR(rshader->input[pos_index].gpr);
2233 spi_input_z |= 1;
2234 }
2235
2236 spi_ps_in_control_1 = 0;
2237 if (face_index != -1) {
2238 spi_ps_in_control_1 |= S_0286D0_FRONT_FACE_ENA(1) |
2239 S_0286D0_FRONT_FACE_ADDR(rshader->input[face_index].gpr);
2240 }
2241
2242 spi_baryc_cntl = 0;
2243 if (have_perspective)
2244 spi_baryc_cntl |= S_0286E0_PERSP_CENTER_ENA(1) |
2245 S_0286E0_PERSP_CENTROID_ENA(have_centroid);
2246 if (have_linear)
2247 spi_baryc_cntl |= S_0286E0_LINEAR_CENTER_ENA(1) |
2248 S_0286E0_LINEAR_CENTROID_ENA(have_centroid);
2249
2250 r600_pipe_state_add_reg(rstate, R_0286CC_SPI_PS_IN_CONTROL_0,
2251 spi_ps_in_control_0, 0xFFFFFFFF, NULL, 0);
2252 r600_pipe_state_add_reg(rstate, R_0286D0_SPI_PS_IN_CONTROL_1,
2253 spi_ps_in_control_1, 0xFFFFFFFF, NULL, 0);
2254 r600_pipe_state_add_reg(rstate, R_0286E4_SPI_PS_IN_CONTROL_2,
2255 0, 0xFFFFFFFF, NULL, 0);
2256 r600_pipe_state_add_reg(rstate, R_0286D8_SPI_INPUT_Z, spi_input_z, 0xFFFFFFFF, NULL, 0);
2257 r600_pipe_state_add_reg(rstate,
2258 R_0286E0_SPI_BARYC_CNTL,
2259 spi_baryc_cntl,
2260 0xFFFFFFFF, NULL, 0);
2261
2262 r600_pipe_state_add_reg(rstate,
2263 R_028840_SQ_PGM_START_PS,
2264 0, 0xFFFFFFFF, shader->bo, RADEON_USAGE_READ);
2265 r600_pipe_state_add_reg(rstate,
2266 R_028844_SQ_PGM_RESOURCES_PS,
2267 S_028844_NUM_GPRS(rshader->bc.ngpr) |
2268 S_028844_PRIME_CACHE_ON_DRAW(1) |
2269 S_028844_STACK_SIZE(rshader->bc.nstack),
2270 0xFFFFFFFF, NULL, 0);
2271 r600_pipe_state_add_reg(rstate,
2272 R_028848_SQ_PGM_RESOURCES_2_PS,
2273 0x0, 0xFFFFFFFF, NULL, 0);
2274 r600_pipe_state_add_reg(rstate,
2275 R_02884C_SQ_PGM_EXPORTS_PS,
2276 exports_ps, 0xFFFFFFFF, NULL, 0);
2277 /* FIXME: Evergreen doesn't seem to support MULTIWRITE_ENABLE. */
2278 /* only set some bits here, the other bits are set in the dsa state */
2279 r600_pipe_state_add_reg(rstate,
2280 R_02880C_DB_SHADER_CONTROL,
2281 db_shader_control,
2282 S_02880C_Z_EXPORT_ENABLE(1) |
2283 S_02880C_STENCIL_EXPORT_ENABLE(1) |
2284 S_02880C_KILL_ENABLE(1),
2285 NULL, 0);
2286 r600_pipe_state_add_reg(rstate,
2287 R_03A200_SQ_LOOP_CONST_0, 0x01000FFF,
2288 0xFFFFFFFF, NULL, 0);
2289 }
2290
2291 void evergreen_pipe_shader_vs(struct pipe_context *ctx, struct r600_pipe_shader *shader)
2292 {
2293 struct r600_pipe_context *rctx = (struct r600_pipe_context *)ctx;
2294 struct r600_pipe_state *rstate = &shader->rstate;
2295 struct r600_shader *rshader = &shader->shader;
2296 unsigned spi_vs_out_id[10];
2297 unsigned i, tmp, nparams;
2298
2299 /* clear previous register */
2300 rstate->nregs = 0;
2301
2302 /* so far never got proper semantic id from tgsi */
2303 for (i = 0; i < 10; i++) {
2304 spi_vs_out_id[i] = 0;
2305 }
2306 for (i = 0; i < 32; i++) {
2307 tmp = i << ((i & 3) * 8);
2308 spi_vs_out_id[i / 4] |= tmp;
2309 }
2310 for (i = 0; i < 10; i++) {
2311 r600_pipe_state_add_reg(rstate,
2312 R_02861C_SPI_VS_OUT_ID_0 + i * 4,
2313 spi_vs_out_id[i], 0xFFFFFFFF, NULL, 0);
2314 }
2315
2316 /* Certain attributes (position, psize, etc.) don't count as params.
2317 * VS is required to export at least one param and r600_shader_from_tgsi()
2318 * takes care of adding a dummy export.
2319 */
2320 nparams = rshader->noutput - rshader->npos;
2321 if (nparams < 1)
2322 nparams = 1;
2323
2324 r600_pipe_state_add_reg(rstate,
2325 R_0286C4_SPI_VS_OUT_CONFIG,
2326 S_0286C4_VS_EXPORT_COUNT(nparams - 1),
2327 0xFFFFFFFF, NULL, 0);
2328 r600_pipe_state_add_reg(rstate,
2329 R_028860_SQ_PGM_RESOURCES_VS,
2330 S_028860_NUM_GPRS(rshader->bc.ngpr) |
2331 S_028860_STACK_SIZE(rshader->bc.nstack),
2332 0xFFFFFFFF, NULL, 0);
2333 r600_pipe_state_add_reg(rstate,
2334 R_028864_SQ_PGM_RESOURCES_2_VS,
2335 0x0, 0xFFFFFFFF, NULL, 0);
2336 r600_pipe_state_add_reg(rstate,
2337 R_02885C_SQ_PGM_START_VS,
2338 0, 0xFFFFFFFF, shader->bo, RADEON_USAGE_READ);
2339
2340 r600_pipe_state_add_reg(rstate,
2341 R_03A200_SQ_LOOP_CONST_0 + (32 * 4), 0x01000FFF,
2342 0xFFFFFFFF, NULL, 0);
2343 }
2344
2345 void evergreen_fetch_shader(struct pipe_context *ctx,
2346 struct r600_vertex_element *ve)
2347 {
2348 struct r600_pipe_context *rctx = (struct r600_pipe_context *)ctx;
2349 struct r600_pipe_state *rstate = &ve->rstate;
2350 rstate->id = R600_PIPE_STATE_FETCH_SHADER;
2351 rstate->nregs = 0;
2352 r600_pipe_state_add_reg(rstate, R_0288A8_SQ_PGM_RESOURCES_FS,
2353 0x00000000, 0xFFFFFFFF, NULL, 0);
2354 r600_pipe_state_add_reg(rstate, R_0288A4_SQ_PGM_START_FS,
2355 0,
2356 0xFFFFFFFF, ve->fetch_shader, RADEON_USAGE_READ);
2357 }
2358
2359 void *evergreen_create_db_flush_dsa(struct r600_pipe_context *rctx)
2360 {
2361 struct pipe_depth_stencil_alpha_state dsa;
2362 struct r600_pipe_state *rstate;
2363
2364 memset(&dsa, 0, sizeof(dsa));
2365
2366 rstate = rctx->context.create_depth_stencil_alpha_state(&rctx->context, &dsa);
2367 r600_pipe_state_add_reg(rstate,
2368 R_02880C_DB_SHADER_CONTROL,
2369 0x0,
2370 S_02880C_DUAL_EXPORT_ENABLE(1), NULL, 0);
2371 r600_pipe_state_add_reg(rstate,
2372 R_028000_DB_RENDER_CONTROL,
2373 S_028000_DEPTH_COPY_ENABLE(1) |
2374 S_028000_STENCIL_COPY_ENABLE(1) |
2375 S_028000_COPY_CENTROID(1),
2376 S_028000_DEPTH_COPY_ENABLE(1) |
2377 S_028000_STENCIL_COPY_ENABLE(1) |
2378 S_028000_COPY_CENTROID(1), NULL, 0);
2379 return rstate;
2380 }
2381
2382 void evergreen_pipe_init_buffer_resource(struct r600_pipe_context *rctx,
2383 struct r600_pipe_resource_state *rstate)
2384 {
2385 rstate->id = R600_PIPE_STATE_RESOURCE;
2386
2387 rstate->val[0] = 0;
2388 rstate->bo[0] = NULL;
2389 rstate->val[1] = 0;
2390 rstate->val[2] = S_030008_ENDIAN_SWAP(r600_endian_swap(32));
2391 rstate->val[3] = S_03000C_DST_SEL_X(V_03000C_SQ_SEL_X) |
2392 S_03000C_DST_SEL_Y(V_03000C_SQ_SEL_Y) |
2393 S_03000C_DST_SEL_Z(V_03000C_SQ_SEL_Z) |
2394 S_03000C_DST_SEL_W(V_03000C_SQ_SEL_W);
2395 rstate->val[4] = 0;
2396 rstate->val[5] = 0;
2397 rstate->val[6] = 0;
2398 rstate->val[7] = 0xc0000000;
2399 }
2400
2401
2402 void evergreen_pipe_mod_buffer_resource(struct r600_pipe_resource_state *rstate,
2403 struct r600_resource *rbuffer,
2404 unsigned offset, unsigned stride,
2405 enum radeon_bo_usage usage)
2406 {
2407 rstate->bo[0] = rbuffer->bo;
2408 rstate->bo_usage[0] = usage;
2409 rstate->val[0] = offset;
2410 rstate->val[1] = rbuffer->bo_size - offset - 1;
2411 rstate->val[2] = S_030008_ENDIAN_SWAP(r600_endian_swap(32)) |
2412 S_030008_STRIDE(stride);
2413 }