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radeonsi: merge si_pipe_shader into si_shader
[mesa.git] / src / gallium / drivers / r600 / evergreen_state.c
1 /*
2 * Copyright 2010 Jerome Glisse <glisse@freedesktop.org>
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * on the rights to use, copy, modify, merge, publish, distribute, sub
8 * license, and/or sell copies of the Software, and to permit persons to whom
9 * the Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
13 * Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHOR(S) AND/OR THEIR SUPPLIERS BE LIABLE FOR ANY CLAIM,
19 * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
20 * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
21 * USE OR OTHER DEALINGS IN THE SOFTWARE.
22 */
23 #include "r600_formats.h"
24 #include "r600_shader.h"
25 #include "evergreend.h"
26
27 #include "pipe/p_shader_tokens.h"
28 #include "util/u_pack_color.h"
29 #include "util/u_memory.h"
30 #include "util/u_framebuffer.h"
31 #include "util/u_dual_blend.h"
32 #include "evergreen_compute.h"
33 #include "util/u_math.h"
34
35 static INLINE unsigned evergreen_array_mode(unsigned mode)
36 {
37 switch (mode) {
38 case RADEON_SURF_MODE_LINEAR_ALIGNED: return V_028C70_ARRAY_LINEAR_ALIGNED;
39 break;
40 case RADEON_SURF_MODE_1D: return V_028C70_ARRAY_1D_TILED_THIN1;
41 break;
42 case RADEON_SURF_MODE_2D: return V_028C70_ARRAY_2D_TILED_THIN1;
43 default:
44 case RADEON_SURF_MODE_LINEAR: return V_028C70_ARRAY_LINEAR_GENERAL;
45 }
46 }
47
48 static uint32_t eg_num_banks(uint32_t nbanks)
49 {
50 switch (nbanks) {
51 case 2:
52 return 0;
53 case 4:
54 return 1;
55 case 8:
56 default:
57 return 2;
58 case 16:
59 return 3;
60 }
61 }
62
63
64 static unsigned eg_tile_split(unsigned tile_split)
65 {
66 switch (tile_split) {
67 case 64: tile_split = 0; break;
68 case 128: tile_split = 1; break;
69 case 256: tile_split = 2; break;
70 case 512: tile_split = 3; break;
71 default:
72 case 1024: tile_split = 4; break;
73 case 2048: tile_split = 5; break;
74 case 4096: tile_split = 6; break;
75 }
76 return tile_split;
77 }
78
79 static unsigned eg_macro_tile_aspect(unsigned macro_tile_aspect)
80 {
81 switch (macro_tile_aspect) {
82 default:
83 case 1: macro_tile_aspect = 0; break;
84 case 2: macro_tile_aspect = 1; break;
85 case 4: macro_tile_aspect = 2; break;
86 case 8: macro_tile_aspect = 3; break;
87 }
88 return macro_tile_aspect;
89 }
90
91 static unsigned eg_bank_wh(unsigned bankwh)
92 {
93 switch (bankwh) {
94 default:
95 case 1: bankwh = 0; break;
96 case 2: bankwh = 1; break;
97 case 4: bankwh = 2; break;
98 case 8: bankwh = 3; break;
99 }
100 return bankwh;
101 }
102
103 static uint32_t r600_translate_blend_function(int blend_func)
104 {
105 switch (blend_func) {
106 case PIPE_BLEND_ADD:
107 return V_028780_COMB_DST_PLUS_SRC;
108 case PIPE_BLEND_SUBTRACT:
109 return V_028780_COMB_SRC_MINUS_DST;
110 case PIPE_BLEND_REVERSE_SUBTRACT:
111 return V_028780_COMB_DST_MINUS_SRC;
112 case PIPE_BLEND_MIN:
113 return V_028780_COMB_MIN_DST_SRC;
114 case PIPE_BLEND_MAX:
115 return V_028780_COMB_MAX_DST_SRC;
116 default:
117 R600_ERR("Unknown blend function %d\n", blend_func);
118 assert(0);
119 break;
120 }
121 return 0;
122 }
123
124 static uint32_t r600_translate_blend_factor(int blend_fact)
125 {
126 switch (blend_fact) {
127 case PIPE_BLENDFACTOR_ONE:
128 return V_028780_BLEND_ONE;
129 case PIPE_BLENDFACTOR_SRC_COLOR:
130 return V_028780_BLEND_SRC_COLOR;
131 case PIPE_BLENDFACTOR_SRC_ALPHA:
132 return V_028780_BLEND_SRC_ALPHA;
133 case PIPE_BLENDFACTOR_DST_ALPHA:
134 return V_028780_BLEND_DST_ALPHA;
135 case PIPE_BLENDFACTOR_DST_COLOR:
136 return V_028780_BLEND_DST_COLOR;
137 case PIPE_BLENDFACTOR_SRC_ALPHA_SATURATE:
138 return V_028780_BLEND_SRC_ALPHA_SATURATE;
139 case PIPE_BLENDFACTOR_CONST_COLOR:
140 return V_028780_BLEND_CONST_COLOR;
141 case PIPE_BLENDFACTOR_CONST_ALPHA:
142 return V_028780_BLEND_CONST_ALPHA;
143 case PIPE_BLENDFACTOR_ZERO:
144 return V_028780_BLEND_ZERO;
145 case PIPE_BLENDFACTOR_INV_SRC_COLOR:
146 return V_028780_BLEND_ONE_MINUS_SRC_COLOR;
147 case PIPE_BLENDFACTOR_INV_SRC_ALPHA:
148 return V_028780_BLEND_ONE_MINUS_SRC_ALPHA;
149 case PIPE_BLENDFACTOR_INV_DST_ALPHA:
150 return V_028780_BLEND_ONE_MINUS_DST_ALPHA;
151 case PIPE_BLENDFACTOR_INV_DST_COLOR:
152 return V_028780_BLEND_ONE_MINUS_DST_COLOR;
153 case PIPE_BLENDFACTOR_INV_CONST_COLOR:
154 return V_028780_BLEND_ONE_MINUS_CONST_COLOR;
155 case PIPE_BLENDFACTOR_INV_CONST_ALPHA:
156 return V_028780_BLEND_ONE_MINUS_CONST_ALPHA;
157 case PIPE_BLENDFACTOR_SRC1_COLOR:
158 return V_028780_BLEND_SRC1_COLOR;
159 case PIPE_BLENDFACTOR_SRC1_ALPHA:
160 return V_028780_BLEND_SRC1_ALPHA;
161 case PIPE_BLENDFACTOR_INV_SRC1_COLOR:
162 return V_028780_BLEND_INV_SRC1_COLOR;
163 case PIPE_BLENDFACTOR_INV_SRC1_ALPHA:
164 return V_028780_BLEND_INV_SRC1_ALPHA;
165 default:
166 R600_ERR("Bad blend factor %d not supported!\n", blend_fact);
167 assert(0);
168 break;
169 }
170 return 0;
171 }
172
173 static unsigned r600_tex_dim(unsigned dim, unsigned nr_samples)
174 {
175 switch (dim) {
176 default:
177 case PIPE_TEXTURE_1D:
178 return V_030000_SQ_TEX_DIM_1D;
179 case PIPE_TEXTURE_1D_ARRAY:
180 return V_030000_SQ_TEX_DIM_1D_ARRAY;
181 case PIPE_TEXTURE_2D:
182 case PIPE_TEXTURE_RECT:
183 return nr_samples > 1 ? V_030000_SQ_TEX_DIM_2D_MSAA :
184 V_030000_SQ_TEX_DIM_2D;
185 case PIPE_TEXTURE_2D_ARRAY:
186 return nr_samples > 1 ? V_030000_SQ_TEX_DIM_2D_ARRAY_MSAA :
187 V_030000_SQ_TEX_DIM_2D_ARRAY;
188 case PIPE_TEXTURE_3D:
189 return V_030000_SQ_TEX_DIM_3D;
190 case PIPE_TEXTURE_CUBE:
191 case PIPE_TEXTURE_CUBE_ARRAY:
192 return V_030000_SQ_TEX_DIM_CUBEMAP;
193 }
194 }
195
196 static uint32_t r600_translate_dbformat(enum pipe_format format)
197 {
198 switch (format) {
199 case PIPE_FORMAT_Z16_UNORM:
200 return V_028040_Z_16;
201 case PIPE_FORMAT_Z24X8_UNORM:
202 case PIPE_FORMAT_Z24_UNORM_S8_UINT:
203 case PIPE_FORMAT_X8Z24_UNORM:
204 case PIPE_FORMAT_S8_UINT_Z24_UNORM:
205 return V_028040_Z_24;
206 case PIPE_FORMAT_Z32_FLOAT:
207 case PIPE_FORMAT_Z32_FLOAT_S8X24_UINT:
208 return V_028040_Z_32_FLOAT;
209 default:
210 return ~0U;
211 }
212 }
213
214 static bool r600_is_sampler_format_supported(struct pipe_screen *screen, enum pipe_format format)
215 {
216 return r600_translate_texformat(screen, format, NULL, NULL, NULL) != ~0U;
217 }
218
219 static bool r600_is_colorbuffer_format_supported(enum chip_class chip, enum pipe_format format)
220 {
221 return r600_translate_colorformat(chip, format) != ~0U &&
222 r600_translate_colorswap(format) != ~0U;
223 }
224
225 static bool r600_is_zs_format_supported(enum pipe_format format)
226 {
227 return r600_translate_dbformat(format) != ~0U;
228 }
229
230 boolean evergreen_is_format_supported(struct pipe_screen *screen,
231 enum pipe_format format,
232 enum pipe_texture_target target,
233 unsigned sample_count,
234 unsigned usage)
235 {
236 struct r600_screen *rscreen = (struct r600_screen*)screen;
237 unsigned retval = 0;
238
239 if (target >= PIPE_MAX_TEXTURE_TYPES) {
240 R600_ERR("r600: unsupported texture type %d\n", target);
241 return FALSE;
242 }
243
244 if (!util_format_is_supported(format, usage))
245 return FALSE;
246
247 if (sample_count > 1) {
248 if (!rscreen->has_msaa)
249 return FALSE;
250
251 switch (sample_count) {
252 case 2:
253 case 4:
254 case 8:
255 break;
256 default:
257 return FALSE;
258 }
259 }
260
261 if (usage & PIPE_BIND_SAMPLER_VIEW) {
262 if (target == PIPE_BUFFER) {
263 if (r600_is_vertex_format_supported(format))
264 retval |= PIPE_BIND_SAMPLER_VIEW;
265 } else {
266 if (r600_is_sampler_format_supported(screen, format))
267 retval |= PIPE_BIND_SAMPLER_VIEW;
268 }
269 }
270
271 if ((usage & (PIPE_BIND_RENDER_TARGET |
272 PIPE_BIND_DISPLAY_TARGET |
273 PIPE_BIND_SCANOUT |
274 PIPE_BIND_SHARED |
275 PIPE_BIND_BLENDABLE)) &&
276 r600_is_colorbuffer_format_supported(rscreen->b.chip_class, format)) {
277 retval |= usage &
278 (PIPE_BIND_RENDER_TARGET |
279 PIPE_BIND_DISPLAY_TARGET |
280 PIPE_BIND_SCANOUT |
281 PIPE_BIND_SHARED);
282 if (!util_format_is_pure_integer(format) &&
283 !util_format_is_depth_or_stencil(format))
284 retval |= usage & PIPE_BIND_BLENDABLE;
285 }
286
287 if ((usage & PIPE_BIND_DEPTH_STENCIL) &&
288 r600_is_zs_format_supported(format)) {
289 retval |= PIPE_BIND_DEPTH_STENCIL;
290 }
291
292 if ((usage & PIPE_BIND_VERTEX_BUFFER) &&
293 r600_is_vertex_format_supported(format)) {
294 retval |= PIPE_BIND_VERTEX_BUFFER;
295 }
296
297 if (usage & PIPE_BIND_TRANSFER_READ)
298 retval |= PIPE_BIND_TRANSFER_READ;
299 if (usage & PIPE_BIND_TRANSFER_WRITE)
300 retval |= PIPE_BIND_TRANSFER_WRITE;
301
302 return retval == usage;
303 }
304
305 static void *evergreen_create_blend_state_mode(struct pipe_context *ctx,
306 const struct pipe_blend_state *state, int mode)
307 {
308 uint32_t color_control = 0, target_mask = 0;
309 struct r600_blend_state *blend = CALLOC_STRUCT(r600_blend_state);
310
311 if (!blend) {
312 return NULL;
313 }
314
315 r600_init_command_buffer(&blend->buffer, 20);
316 r600_init_command_buffer(&blend->buffer_no_blend, 20);
317
318 if (state->logicop_enable) {
319 color_control |= (state->logicop_func << 16) | (state->logicop_func << 20);
320 } else {
321 color_control |= (0xcc << 16);
322 }
323 /* we pretend 8 buffer are used, CB_SHADER_MASK will disable unused one */
324 if (state->independent_blend_enable) {
325 for (int i = 0; i < 8; i++) {
326 target_mask |= (state->rt[i].colormask << (4 * i));
327 }
328 } else {
329 for (int i = 0; i < 8; i++) {
330 target_mask |= (state->rt[0].colormask << (4 * i));
331 }
332 }
333
334 /* only have dual source on MRT0 */
335 blend->dual_src_blend = util_blend_state_is_dual(state, 0);
336 blend->cb_target_mask = target_mask;
337 blend->alpha_to_one = state->alpha_to_one;
338
339 if (target_mask)
340 color_control |= S_028808_MODE(mode);
341 else
342 color_control |= S_028808_MODE(V_028808_CB_DISABLE);
343
344
345 r600_store_context_reg(&blend->buffer, R_028808_CB_COLOR_CONTROL, color_control);
346 r600_store_context_reg(&blend->buffer, R_028B70_DB_ALPHA_TO_MASK,
347 S_028B70_ALPHA_TO_MASK_ENABLE(state->alpha_to_coverage) |
348 S_028B70_ALPHA_TO_MASK_OFFSET0(2) |
349 S_028B70_ALPHA_TO_MASK_OFFSET1(2) |
350 S_028B70_ALPHA_TO_MASK_OFFSET2(2) |
351 S_028B70_ALPHA_TO_MASK_OFFSET3(2));
352 r600_store_context_reg_seq(&blend->buffer, R_028780_CB_BLEND0_CONTROL, 8);
353
354 /* Copy over the dwords set so far into buffer_no_blend.
355 * Only the CB_BLENDi_CONTROL registers must be set after this. */
356 memcpy(blend->buffer_no_blend.buf, blend->buffer.buf, blend->buffer.num_dw * 4);
357 blend->buffer_no_blend.num_dw = blend->buffer.num_dw;
358
359 for (int i = 0; i < 8; i++) {
360 /* state->rt entries > 0 only written if independent blending */
361 const int j = state->independent_blend_enable ? i : 0;
362
363 unsigned eqRGB = state->rt[j].rgb_func;
364 unsigned srcRGB = state->rt[j].rgb_src_factor;
365 unsigned dstRGB = state->rt[j].rgb_dst_factor;
366 unsigned eqA = state->rt[j].alpha_func;
367 unsigned srcA = state->rt[j].alpha_src_factor;
368 unsigned dstA = state->rt[j].alpha_dst_factor;
369 uint32_t bc = 0;
370
371 r600_store_value(&blend->buffer_no_blend, 0);
372
373 if (!state->rt[j].blend_enable) {
374 r600_store_value(&blend->buffer, 0);
375 continue;
376 }
377
378 bc |= S_028780_BLEND_CONTROL_ENABLE(1);
379 bc |= S_028780_COLOR_COMB_FCN(r600_translate_blend_function(eqRGB));
380 bc |= S_028780_COLOR_SRCBLEND(r600_translate_blend_factor(srcRGB));
381 bc |= S_028780_COLOR_DESTBLEND(r600_translate_blend_factor(dstRGB));
382
383 if (srcA != srcRGB || dstA != dstRGB || eqA != eqRGB) {
384 bc |= S_028780_SEPARATE_ALPHA_BLEND(1);
385 bc |= S_028780_ALPHA_COMB_FCN(r600_translate_blend_function(eqA));
386 bc |= S_028780_ALPHA_SRCBLEND(r600_translate_blend_factor(srcA));
387 bc |= S_028780_ALPHA_DESTBLEND(r600_translate_blend_factor(dstA));
388 }
389 r600_store_value(&blend->buffer, bc);
390 }
391 return blend;
392 }
393
394 static void *evergreen_create_blend_state(struct pipe_context *ctx,
395 const struct pipe_blend_state *state)
396 {
397
398 return evergreen_create_blend_state_mode(ctx, state, V_028808_CB_NORMAL);
399 }
400
401 static void *evergreen_create_dsa_state(struct pipe_context *ctx,
402 const struct pipe_depth_stencil_alpha_state *state)
403 {
404 unsigned db_depth_control, alpha_test_control, alpha_ref;
405 struct r600_dsa_state *dsa = CALLOC_STRUCT(r600_dsa_state);
406
407 if (dsa == NULL) {
408 return NULL;
409 }
410
411 r600_init_command_buffer(&dsa->buffer, 3);
412
413 dsa->valuemask[0] = state->stencil[0].valuemask;
414 dsa->valuemask[1] = state->stencil[1].valuemask;
415 dsa->writemask[0] = state->stencil[0].writemask;
416 dsa->writemask[1] = state->stencil[1].writemask;
417 dsa->zwritemask = state->depth.writemask;
418
419 db_depth_control = S_028800_Z_ENABLE(state->depth.enabled) |
420 S_028800_Z_WRITE_ENABLE(state->depth.writemask) |
421 S_028800_ZFUNC(state->depth.func);
422
423 /* stencil */
424 if (state->stencil[0].enabled) {
425 db_depth_control |= S_028800_STENCIL_ENABLE(1);
426 db_depth_control |= S_028800_STENCILFUNC(state->stencil[0].func); /* translates straight */
427 db_depth_control |= S_028800_STENCILFAIL(r600_translate_stencil_op(state->stencil[0].fail_op));
428 db_depth_control |= S_028800_STENCILZPASS(r600_translate_stencil_op(state->stencil[0].zpass_op));
429 db_depth_control |= S_028800_STENCILZFAIL(r600_translate_stencil_op(state->stencil[0].zfail_op));
430
431 if (state->stencil[1].enabled) {
432 db_depth_control |= S_028800_BACKFACE_ENABLE(1);
433 db_depth_control |= S_028800_STENCILFUNC_BF(state->stencil[1].func); /* translates straight */
434 db_depth_control |= S_028800_STENCILFAIL_BF(r600_translate_stencil_op(state->stencil[1].fail_op));
435 db_depth_control |= S_028800_STENCILZPASS_BF(r600_translate_stencil_op(state->stencil[1].zpass_op));
436 db_depth_control |= S_028800_STENCILZFAIL_BF(r600_translate_stencil_op(state->stencil[1].zfail_op));
437 }
438 }
439
440 /* alpha */
441 alpha_test_control = 0;
442 alpha_ref = 0;
443 if (state->alpha.enabled) {
444 alpha_test_control = S_028410_ALPHA_FUNC(state->alpha.func);
445 alpha_test_control |= S_028410_ALPHA_TEST_ENABLE(1);
446 alpha_ref = fui(state->alpha.ref_value);
447 }
448 dsa->sx_alpha_test_control = alpha_test_control & 0xff;
449 dsa->alpha_ref = alpha_ref;
450
451 /* misc */
452 r600_store_context_reg(&dsa->buffer, R_028800_DB_DEPTH_CONTROL, db_depth_control);
453 return dsa;
454 }
455
456 static void *evergreen_create_rs_state(struct pipe_context *ctx,
457 const struct pipe_rasterizer_state *state)
458 {
459 struct r600_context *rctx = (struct r600_context *)ctx;
460 unsigned tmp, spi_interp;
461 float psize_min, psize_max;
462 struct r600_rasterizer_state *rs = CALLOC_STRUCT(r600_rasterizer_state);
463
464 if (rs == NULL) {
465 return NULL;
466 }
467
468 r600_init_command_buffer(&rs->buffer, 30);
469
470 rs->flatshade = state->flatshade;
471 rs->sprite_coord_enable = state->sprite_coord_enable;
472 rs->two_side = state->light_twoside;
473 rs->clip_plane_enable = state->clip_plane_enable;
474 rs->pa_sc_line_stipple = state->line_stipple_enable ?
475 S_028A0C_LINE_PATTERN(state->line_stipple_pattern) |
476 S_028A0C_REPEAT_COUNT(state->line_stipple_factor) : 0;
477 rs->pa_cl_clip_cntl =
478 S_028810_PS_UCP_MODE(3) |
479 S_028810_ZCLIP_NEAR_DISABLE(!state->depth_clip) |
480 S_028810_ZCLIP_FAR_DISABLE(!state->depth_clip) |
481 S_028810_DX_LINEAR_ATTR_CLIP_ENA(1) |
482 S_028810_DX_RASTERIZATION_KILL(state->rasterizer_discard);
483 rs->multisample_enable = state->multisample;
484
485 /* offset */
486 rs->offset_units = state->offset_units;
487 rs->offset_scale = state->offset_scale * 12.0f;
488 rs->offset_enable = state->offset_point || state->offset_line || state->offset_tri;
489
490 if (state->point_size_per_vertex) {
491 psize_min = util_get_min_point_size(state);
492 psize_max = 8192;
493 } else {
494 /* Force the point size to be as if the vertex output was disabled. */
495 psize_min = state->point_size;
496 psize_max = state->point_size;
497 }
498
499 spi_interp = S_0286D4_FLAT_SHADE_ENA(1);
500 if (state->sprite_coord_enable) {
501 spi_interp |= S_0286D4_PNT_SPRITE_ENA(1) |
502 S_0286D4_PNT_SPRITE_OVRD_X(2) |
503 S_0286D4_PNT_SPRITE_OVRD_Y(3) |
504 S_0286D4_PNT_SPRITE_OVRD_Z(0) |
505 S_0286D4_PNT_SPRITE_OVRD_W(1);
506 if (state->sprite_coord_mode != PIPE_SPRITE_COORD_UPPER_LEFT) {
507 spi_interp |= S_0286D4_PNT_SPRITE_TOP_1(1);
508 }
509 }
510
511 r600_store_context_reg_seq(&rs->buffer, R_028A00_PA_SU_POINT_SIZE, 3);
512 /* point size 12.4 fixed point (divide by two, because 0.5 = 1 pixel) */
513 tmp = r600_pack_float_12p4(state->point_size/2);
514 r600_store_value(&rs->buffer, /* R_028A00_PA_SU_POINT_SIZE */
515 S_028A00_HEIGHT(tmp) | S_028A00_WIDTH(tmp));
516 r600_store_value(&rs->buffer, /* R_028A04_PA_SU_POINT_MINMAX */
517 S_028A04_MIN_SIZE(r600_pack_float_12p4(psize_min/2)) |
518 S_028A04_MAX_SIZE(r600_pack_float_12p4(psize_max/2)));
519 r600_store_value(&rs->buffer, /* R_028A08_PA_SU_LINE_CNTL */
520 S_028A08_WIDTH((unsigned)(state->line_width * 8)));
521
522 r600_store_context_reg(&rs->buffer, R_0286D4_SPI_INTERP_CONTROL_0, spi_interp);
523 r600_store_context_reg(&rs->buffer, R_028A48_PA_SC_MODE_CNTL_0,
524 S_028A48_MSAA_ENABLE(state->multisample) |
525 S_028A48_VPORT_SCISSOR_ENABLE(state->scissor) |
526 S_028A48_LINE_STIPPLE_ENABLE(state->line_stipple_enable));
527
528 if (rctx->b.chip_class == CAYMAN) {
529 r600_store_context_reg(&rs->buffer, CM_R_028BE4_PA_SU_VTX_CNTL,
530 S_028C08_PIX_CENTER_HALF(state->half_pixel_center) |
531 S_028C08_QUANT_MODE(V_028C08_X_1_256TH));
532 } else {
533 r600_store_context_reg(&rs->buffer, R_028C08_PA_SU_VTX_CNTL,
534 S_028C08_PIX_CENTER_HALF(state->half_pixel_center) |
535 S_028C08_QUANT_MODE(V_028C08_X_1_256TH));
536 }
537
538 r600_store_context_reg(&rs->buffer, R_028B7C_PA_SU_POLY_OFFSET_CLAMP, fui(state->offset_clamp));
539 r600_store_context_reg(&rs->buffer, R_028814_PA_SU_SC_MODE_CNTL,
540 S_028814_PROVOKING_VTX_LAST(!state->flatshade_first) |
541 S_028814_CULL_FRONT((state->cull_face & PIPE_FACE_FRONT) ? 1 : 0) |
542 S_028814_CULL_BACK((state->cull_face & PIPE_FACE_BACK) ? 1 : 0) |
543 S_028814_FACE(!state->front_ccw) |
544 S_028814_POLY_OFFSET_FRONT_ENABLE(state->offset_tri) |
545 S_028814_POLY_OFFSET_BACK_ENABLE(state->offset_tri) |
546 S_028814_POLY_OFFSET_PARA_ENABLE(state->offset_tri) |
547 S_028814_POLY_MODE(state->fill_front != PIPE_POLYGON_MODE_FILL ||
548 state->fill_back != PIPE_POLYGON_MODE_FILL) |
549 S_028814_POLYMODE_FRONT_PTYPE(r600_translate_fill(state->fill_front)) |
550 S_028814_POLYMODE_BACK_PTYPE(r600_translate_fill(state->fill_back)));
551 return rs;
552 }
553
554 static void *evergreen_create_sampler_state(struct pipe_context *ctx,
555 const struct pipe_sampler_state *state)
556 {
557 struct r600_pipe_sampler_state *ss = CALLOC_STRUCT(r600_pipe_sampler_state);
558 unsigned aniso_flag_offset = state->max_anisotropy > 1 ? 2 : 0;
559
560 if (ss == NULL) {
561 return NULL;
562 }
563
564 ss->border_color_use = sampler_state_needs_border_color(state);
565
566 /* R_03C000_SQ_TEX_SAMPLER_WORD0_0 */
567 ss->tex_sampler_words[0] =
568 S_03C000_CLAMP_X(r600_tex_wrap(state->wrap_s)) |
569 S_03C000_CLAMP_Y(r600_tex_wrap(state->wrap_t)) |
570 S_03C000_CLAMP_Z(r600_tex_wrap(state->wrap_r)) |
571 S_03C000_XY_MAG_FILTER(r600_tex_filter(state->mag_img_filter) | aniso_flag_offset) |
572 S_03C000_XY_MIN_FILTER(r600_tex_filter(state->min_img_filter) | aniso_flag_offset) |
573 S_03C000_MIP_FILTER(r600_tex_mipfilter(state->min_mip_filter)) |
574 S_03C000_MAX_ANISO(r600_tex_aniso_filter(state->max_anisotropy)) |
575 S_03C000_DEPTH_COMPARE_FUNCTION(r600_tex_compare(state->compare_func)) |
576 S_03C000_BORDER_COLOR_TYPE(ss->border_color_use ? V_03C000_SQ_TEX_BORDER_COLOR_REGISTER : 0);
577 /* R_03C004_SQ_TEX_SAMPLER_WORD1_0 */
578 ss->tex_sampler_words[1] =
579 S_03C004_MIN_LOD(S_FIXED(CLAMP(state->min_lod, 0, 15), 8)) |
580 S_03C004_MAX_LOD(S_FIXED(CLAMP(state->max_lod, 0, 15), 8));
581 /* R_03C008_SQ_TEX_SAMPLER_WORD2_0 */
582 ss->tex_sampler_words[2] =
583 S_03C008_LOD_BIAS(S_FIXED(CLAMP(state->lod_bias, -16, 16), 8)) |
584 (state->seamless_cube_map ? 0 : S_03C008_DISABLE_CUBE_WRAP(1)) |
585 S_03C008_TYPE(1);
586
587 if (ss->border_color_use) {
588 memcpy(&ss->border_color, &state->border_color, sizeof(state->border_color));
589 }
590 return ss;
591 }
592
593 static struct pipe_sampler_view *
594 texture_buffer_sampler_view(struct r600_context *rctx,
595 struct r600_pipe_sampler_view *view,
596 unsigned width0, unsigned height0)
597
598 {
599 struct r600_texture *tmp = (struct r600_texture*)view->base.texture;
600 uint64_t va;
601 int stride = util_format_get_blocksize(view->base.format);
602 unsigned format, num_format, format_comp, endian;
603 unsigned swizzle_res;
604 unsigned char swizzle[4];
605 const struct util_format_description *desc;
606 unsigned offset = view->base.u.buf.first_element * stride;
607 unsigned size = (view->base.u.buf.last_element - view->base.u.buf.first_element + 1) * stride;
608
609 swizzle[0] = view->base.swizzle_r;
610 swizzle[1] = view->base.swizzle_g;
611 swizzle[2] = view->base.swizzle_b;
612 swizzle[3] = view->base.swizzle_a;
613
614 r600_vertex_data_type(view->base.format,
615 &format, &num_format, &format_comp,
616 &endian);
617
618 desc = util_format_description(view->base.format);
619
620 swizzle_res = r600_get_swizzle_combined(desc->swizzle, swizzle, TRUE);
621
622 va = tmp->resource.gpu_address + offset;
623 view->tex_resource = &tmp->resource;
624
625 view->skip_mip_address_reloc = true;
626 view->tex_resource_words[0] = va;
627 view->tex_resource_words[1] = size - 1;
628 view->tex_resource_words[2] = S_030008_BASE_ADDRESS_HI(va >> 32UL) |
629 S_030008_STRIDE(stride) |
630 S_030008_DATA_FORMAT(format) |
631 S_030008_NUM_FORMAT_ALL(num_format) |
632 S_030008_FORMAT_COMP_ALL(format_comp) |
633 S_030008_ENDIAN_SWAP(endian);
634 view->tex_resource_words[3] = swizzle_res;
635 /*
636 * in theory dword 4 is for number of elements, for use with resinfo,
637 * but it seems to utterly fail to work, the amd gpu shader analyser
638 * uses a const buffer to store the element sizes for buffer txq
639 */
640 view->tex_resource_words[4] = 0;
641 view->tex_resource_words[5] = view->tex_resource_words[6] = 0;
642 view->tex_resource_words[7] = S_03001C_TYPE(V_03001C_SQ_TEX_VTX_VALID_BUFFER);
643
644 if (tmp->resource.gpu_address)
645 LIST_ADDTAIL(&view->list, &rctx->b.texture_buffers);
646 return &view->base;
647 }
648
649 struct pipe_sampler_view *
650 evergreen_create_sampler_view_custom(struct pipe_context *ctx,
651 struct pipe_resource *texture,
652 const struct pipe_sampler_view *state,
653 unsigned width0, unsigned height0,
654 unsigned force_level)
655 {
656 struct r600_context *rctx = (struct r600_context*)ctx;
657 struct r600_screen *rscreen = (struct r600_screen*)ctx->screen;
658 struct r600_pipe_sampler_view *view = CALLOC_STRUCT(r600_pipe_sampler_view);
659 struct r600_texture *tmp = (struct r600_texture*)texture;
660 unsigned format, endian;
661 uint32_t word4 = 0, yuv_format = 0, pitch = 0;
662 unsigned char swizzle[4], array_mode = 0, non_disp_tiling = 0;
663 unsigned height, depth, width;
664 unsigned macro_aspect, tile_split, bankh, bankw, nbanks, fmask_bankh;
665 enum pipe_format pipe_format = state->format;
666 struct radeon_surface_level *surflevel;
667 unsigned base_level, first_level, last_level;
668 uint64_t va;
669
670 if (view == NULL)
671 return NULL;
672
673 /* initialize base object */
674 view->base = *state;
675 view->base.texture = NULL;
676 pipe_reference(NULL, &texture->reference);
677 view->base.texture = texture;
678 view->base.reference.count = 1;
679 view->base.context = ctx;
680
681 if (texture->target == PIPE_BUFFER)
682 return texture_buffer_sampler_view(rctx, view, width0, height0);
683
684 swizzle[0] = state->swizzle_r;
685 swizzle[1] = state->swizzle_g;
686 swizzle[2] = state->swizzle_b;
687 swizzle[3] = state->swizzle_a;
688
689 tile_split = tmp->surface.tile_split;
690 surflevel = tmp->surface.level;
691
692 /* Texturing with separate depth and stencil. */
693 if (tmp->is_depth && !tmp->is_flushing_texture) {
694 switch (pipe_format) {
695 case PIPE_FORMAT_Z32_FLOAT_S8X24_UINT:
696 pipe_format = PIPE_FORMAT_Z32_FLOAT;
697 break;
698 case PIPE_FORMAT_X8Z24_UNORM:
699 case PIPE_FORMAT_S8_UINT_Z24_UNORM:
700 /* Z24 is always stored like this. */
701 pipe_format = PIPE_FORMAT_Z24X8_UNORM;
702 break;
703 case PIPE_FORMAT_X24S8_UINT:
704 case PIPE_FORMAT_S8X24_UINT:
705 case PIPE_FORMAT_X32_S8X24_UINT:
706 pipe_format = PIPE_FORMAT_S8_UINT;
707 tile_split = tmp->surface.stencil_tile_split;
708 surflevel = tmp->surface.stencil_level;
709 break;
710 default:;
711 }
712 }
713
714 format = r600_translate_texformat(ctx->screen, pipe_format,
715 swizzle,
716 &word4, &yuv_format);
717 assert(format != ~0);
718 if (format == ~0) {
719 FREE(view);
720 return NULL;
721 }
722
723 endian = r600_colorformat_endian_swap(format);
724
725 base_level = 0;
726 first_level = state->u.tex.first_level;
727 last_level = state->u.tex.last_level;
728 width = width0;
729 height = height0;
730 depth = texture->depth0;
731
732 if (force_level) {
733 base_level = force_level;
734 first_level = 0;
735 last_level = 0;
736 width = u_minify(width, force_level);
737 height = u_minify(height, force_level);
738 depth = u_minify(depth, force_level);
739 }
740
741 pitch = surflevel[base_level].nblk_x * util_format_get_blockwidth(pipe_format);
742 non_disp_tiling = tmp->non_disp_tiling;
743
744 switch (surflevel[base_level].mode) {
745 case RADEON_SURF_MODE_LINEAR_ALIGNED:
746 array_mode = V_028C70_ARRAY_LINEAR_ALIGNED;
747 break;
748 case RADEON_SURF_MODE_2D:
749 array_mode = V_028C70_ARRAY_2D_TILED_THIN1;
750 break;
751 case RADEON_SURF_MODE_1D:
752 array_mode = V_028C70_ARRAY_1D_TILED_THIN1;
753 break;
754 case RADEON_SURF_MODE_LINEAR:
755 default:
756 array_mode = V_028C70_ARRAY_LINEAR_GENERAL;
757 break;
758 }
759 macro_aspect = tmp->surface.mtilea;
760 bankw = tmp->surface.bankw;
761 bankh = tmp->surface.bankh;
762 tile_split = eg_tile_split(tile_split);
763 macro_aspect = eg_macro_tile_aspect(macro_aspect);
764 bankw = eg_bank_wh(bankw);
765 bankh = eg_bank_wh(bankh);
766 fmask_bankh = eg_bank_wh(tmp->fmask.bank_height);
767
768 /* 128 bit formats require tile type = 1 */
769 if (rscreen->b.chip_class == CAYMAN) {
770 if (util_format_get_blocksize(pipe_format) >= 16)
771 non_disp_tiling = 1;
772 }
773 nbanks = eg_num_banks(rscreen->b.tiling_info.num_banks);
774
775 if (texture->target == PIPE_TEXTURE_1D_ARRAY) {
776 height = 1;
777 depth = texture->array_size;
778 } else if (texture->target == PIPE_TEXTURE_2D_ARRAY) {
779 depth = texture->array_size;
780 } else if (texture->target == PIPE_TEXTURE_CUBE_ARRAY)
781 depth = texture->array_size / 6;
782
783 va = tmp->resource.gpu_address;
784
785 view->tex_resource = &tmp->resource;
786 view->tex_resource_words[0] = (S_030000_DIM(r600_tex_dim(texture->target, texture->nr_samples)) |
787 S_030000_PITCH((pitch / 8) - 1) |
788 S_030000_TEX_WIDTH(width - 1));
789 if (rscreen->b.chip_class == CAYMAN)
790 view->tex_resource_words[0] |= CM_S_030000_NON_DISP_TILING_ORDER(non_disp_tiling);
791 else
792 view->tex_resource_words[0] |= S_030000_NON_DISP_TILING_ORDER(non_disp_tiling);
793 view->tex_resource_words[1] = (S_030004_TEX_HEIGHT(height - 1) |
794 S_030004_TEX_DEPTH(depth - 1) |
795 S_030004_ARRAY_MODE(array_mode));
796 view->tex_resource_words[2] = (surflevel[base_level].offset + va) >> 8;
797
798 /* TEX_RESOURCE_WORD3.MIP_ADDRESS */
799 if (texture->nr_samples > 1 && rscreen->has_compressed_msaa_texturing) {
800 if (tmp->is_depth) {
801 /* disable FMASK (0 = disabled) */
802 view->tex_resource_words[3] = 0;
803 view->skip_mip_address_reloc = true;
804 } else {
805 /* FMASK should be in MIP_ADDRESS for multisample textures */
806 view->tex_resource_words[3] = (tmp->fmask.offset + va) >> 8;
807 }
808 } else if (last_level && texture->nr_samples <= 1) {
809 view->tex_resource_words[3] = (surflevel[1].offset + va) >> 8;
810 } else {
811 view->tex_resource_words[3] = (surflevel[base_level].offset + va) >> 8;
812 }
813
814 view->tex_resource_words[4] = (word4 |
815 S_030010_ENDIAN_SWAP(endian));
816 view->tex_resource_words[5] = S_030014_BASE_ARRAY(state->u.tex.first_layer) |
817 S_030014_LAST_ARRAY(state->u.tex.last_layer);
818 view->tex_resource_words[6] = S_030018_TILE_SPLIT(tile_split);
819
820 if (texture->nr_samples > 1) {
821 unsigned log_samples = util_logbase2(texture->nr_samples);
822 if (rscreen->b.chip_class == CAYMAN) {
823 view->tex_resource_words[4] |= S_030010_LOG2_NUM_FRAGMENTS(log_samples);
824 }
825 /* LAST_LEVEL holds log2(nr_samples) for multisample textures */
826 view->tex_resource_words[5] |= S_030014_LAST_LEVEL(log_samples);
827 view->tex_resource_words[6] |= S_030018_FMASK_BANK_HEIGHT(fmask_bankh);
828 } else {
829 view->tex_resource_words[4] |= S_030010_BASE_LEVEL(first_level);
830 view->tex_resource_words[5] |= S_030014_LAST_LEVEL(last_level);
831 /* aniso max 16 samples */
832 view->tex_resource_words[6] |= S_030018_MAX_ANISO(4);
833 }
834
835 view->tex_resource_words[7] = S_03001C_DATA_FORMAT(format) |
836 S_03001C_TYPE(V_03001C_SQ_TEX_VTX_VALID_TEXTURE) |
837 S_03001C_BANK_WIDTH(bankw) |
838 S_03001C_BANK_HEIGHT(bankh) |
839 S_03001C_MACRO_TILE_ASPECT(macro_aspect) |
840 S_03001C_NUM_BANKS(nbanks) |
841 S_03001C_DEPTH_SAMPLE_ORDER(tmp->is_depth && !tmp->is_flushing_texture);
842 return &view->base;
843 }
844
845 static struct pipe_sampler_view *
846 evergreen_create_sampler_view(struct pipe_context *ctx,
847 struct pipe_resource *tex,
848 const struct pipe_sampler_view *state)
849 {
850 return evergreen_create_sampler_view_custom(ctx, tex, state,
851 tex->width0, tex->height0, 0);
852 }
853
854 static void evergreen_emit_clip_state(struct r600_context *rctx, struct r600_atom *atom)
855 {
856 struct radeon_winsys_cs *cs = rctx->b.rings.gfx.cs;
857 struct pipe_clip_state *state = &rctx->clip_state.state;
858
859 r600_write_context_reg_seq(cs, R_0285BC_PA_CL_UCP0_X, 6*4);
860 radeon_emit_array(cs, (unsigned*)state, 6*4);
861 }
862
863 static void evergreen_set_polygon_stipple(struct pipe_context *ctx,
864 const struct pipe_poly_stipple *state)
865 {
866 }
867
868 static void evergreen_get_scissor_rect(struct r600_context *rctx,
869 unsigned tl_x, unsigned tl_y, unsigned br_x, unsigned br_y,
870 uint32_t *tl, uint32_t *br)
871 {
872 /* EG hw workaround */
873 if (br_x == 0)
874 tl_x = 1;
875 if (br_y == 0)
876 tl_y = 1;
877
878 /* cayman hw workaround */
879 if (rctx->b.chip_class == CAYMAN) {
880 if (br_x == 1 && br_y == 1)
881 br_x = 2;
882 }
883
884 *tl = S_028240_TL_X(tl_x) | S_028240_TL_Y(tl_y);
885 *br = S_028244_BR_X(br_x) | S_028244_BR_Y(br_y);
886 }
887
888 static void evergreen_set_scissor_states(struct pipe_context *ctx,
889 unsigned start_slot,
890 unsigned num_scissors,
891 const struct pipe_scissor_state *state)
892 {
893 struct r600_context *rctx = (struct r600_context *)ctx;
894 int i;
895
896 for (i = start_slot; i < start_slot + num_scissors; i++) {
897 rctx->scissor[i].scissor = state[i - start_slot];
898 rctx->scissor[i].atom.dirty = true;
899 }
900 }
901
902 static void evergreen_emit_scissor_state(struct r600_context *rctx, struct r600_atom *atom)
903 {
904 struct radeon_winsys_cs *cs = rctx->b.rings.gfx.cs;
905 struct r600_scissor_state *rstate = (struct r600_scissor_state *)atom;
906 struct pipe_scissor_state *state = &rstate->scissor;
907 unsigned offset = rstate->idx * 4 * 2;
908 uint32_t tl, br;
909
910 evergreen_get_scissor_rect(rctx, state->minx, state->miny, state->maxx, state->maxy, &tl, &br);
911
912 r600_write_context_reg_seq(cs, R_028250_PA_SC_VPORT_SCISSOR_0_TL + offset, 2);
913 radeon_emit(cs, tl);
914 radeon_emit(cs, br);
915 }
916
917 /**
918 * This function intializes the CB* register values for RATs. It is meant
919 * to be used for 1D aligned buffers that do not have an associated
920 * radeon_surface.
921 */
922 void evergreen_init_color_surface_rat(struct r600_context *rctx,
923 struct r600_surface *surf)
924 {
925 struct pipe_resource *pipe_buffer = surf->base.texture;
926 unsigned format = r600_translate_colorformat(rctx->b.chip_class,
927 surf->base.format);
928 unsigned endian = r600_colorformat_endian_swap(format);
929 unsigned swap = r600_translate_colorswap(surf->base.format);
930 unsigned block_size =
931 align(util_format_get_blocksize(pipe_buffer->format), 4);
932 unsigned pitch_alignment =
933 MAX2(64, rctx->screen->b.tiling_info.group_bytes / block_size);
934 unsigned pitch = align(pipe_buffer->width0, pitch_alignment);
935
936 /* XXX: This is copied from evergreen_init_color_surface(). I don't
937 * know why this is necessary.
938 */
939 if (pipe_buffer->usage == PIPE_USAGE_STAGING) {
940 endian = ENDIAN_NONE;
941 }
942
943 surf->cb_color_base = r600_resource(pipe_buffer)->gpu_address >> 8;
944
945 surf->cb_color_pitch = (pitch / 8) - 1;
946
947 surf->cb_color_slice = 0;
948
949 surf->cb_color_view = 0;
950
951 surf->cb_color_info =
952 S_028C70_ENDIAN(endian)
953 | S_028C70_FORMAT(format)
954 | S_028C70_ARRAY_MODE(V_028C70_ARRAY_LINEAR_ALIGNED)
955 | S_028C70_NUMBER_TYPE(V_028C70_NUMBER_UINT)
956 | S_028C70_COMP_SWAP(swap)
957 | S_028C70_BLEND_BYPASS(1) /* We must set this bit because we
958 * are using NUMBER_UINT */
959 | S_028C70_RAT(1)
960 ;
961
962 surf->cb_color_attrib = S_028C74_NON_DISP_TILING_ORDER(1);
963
964 /* For buffers, CB_COLOR0_DIM needs to be set to the number of
965 * elements. */
966 surf->cb_color_dim = pipe_buffer->width0;
967
968 /* Set the buffer range the GPU will have access to: */
969 util_range_add(&r600_resource(pipe_buffer)->valid_buffer_range,
970 0, pipe_buffer->width0);
971
972 surf->cb_color_fmask = surf->cb_color_base;
973 surf->cb_color_fmask_slice = 0;
974 }
975
976 void evergreen_init_color_surface(struct r600_context *rctx,
977 struct r600_surface *surf)
978 {
979 struct r600_screen *rscreen = rctx->screen;
980 struct r600_texture *rtex = (struct r600_texture*)surf->base.texture;
981 unsigned level = surf->base.u.tex.level;
982 unsigned pitch, slice;
983 unsigned color_info, color_attrib, color_dim = 0, color_view;
984 unsigned format, swap, ntype, endian;
985 uint64_t offset, base_offset;
986 unsigned non_disp_tiling, macro_aspect, tile_split, bankh, bankw, fmask_bankh, nbanks;
987 const struct util_format_description *desc;
988 int i;
989 bool blend_clamp = 0, blend_bypass = 0;
990
991 offset = rtex->surface.level[level].offset;
992 if (rtex->surface.level[level].mode == RADEON_SURF_MODE_LINEAR) {
993 assert(surf->base.u.tex.first_layer == surf->base.u.tex.last_layer);
994 offset += rtex->surface.level[level].slice_size *
995 surf->base.u.tex.first_layer;
996 color_view = 0;
997 } else
998 color_view = S_028C6C_SLICE_START(surf->base.u.tex.first_layer) |
999 S_028C6C_SLICE_MAX(surf->base.u.tex.last_layer);
1000
1001 pitch = (rtex->surface.level[level].nblk_x) / 8 - 1;
1002 slice = (rtex->surface.level[level].nblk_x * rtex->surface.level[level].nblk_y) / 64;
1003 if (slice) {
1004 slice = slice - 1;
1005 }
1006 color_info = 0;
1007 switch (rtex->surface.level[level].mode) {
1008 case RADEON_SURF_MODE_LINEAR_ALIGNED:
1009 color_info = S_028C70_ARRAY_MODE(V_028C70_ARRAY_LINEAR_ALIGNED);
1010 non_disp_tiling = 1;
1011 break;
1012 case RADEON_SURF_MODE_1D:
1013 color_info = S_028C70_ARRAY_MODE(V_028C70_ARRAY_1D_TILED_THIN1);
1014 non_disp_tiling = rtex->non_disp_tiling;
1015 break;
1016 case RADEON_SURF_MODE_2D:
1017 color_info = S_028C70_ARRAY_MODE(V_028C70_ARRAY_2D_TILED_THIN1);
1018 non_disp_tiling = rtex->non_disp_tiling;
1019 break;
1020 case RADEON_SURF_MODE_LINEAR:
1021 default:
1022 color_info = S_028C70_ARRAY_MODE(V_028C70_ARRAY_LINEAR_GENERAL);
1023 non_disp_tiling = 1;
1024 break;
1025 }
1026 tile_split = rtex->surface.tile_split;
1027 macro_aspect = rtex->surface.mtilea;
1028 bankw = rtex->surface.bankw;
1029 bankh = rtex->surface.bankh;
1030 fmask_bankh = rtex->fmask.bank_height;
1031 tile_split = eg_tile_split(tile_split);
1032 macro_aspect = eg_macro_tile_aspect(macro_aspect);
1033 bankw = eg_bank_wh(bankw);
1034 bankh = eg_bank_wh(bankh);
1035 fmask_bankh = eg_bank_wh(fmask_bankh);
1036
1037 /* 128 bit formats require tile type = 1 */
1038 if (rscreen->b.chip_class == CAYMAN) {
1039 if (util_format_get_blocksize(surf->base.format) >= 16)
1040 non_disp_tiling = 1;
1041 }
1042 nbanks = eg_num_banks(rscreen->b.tiling_info.num_banks);
1043 desc = util_format_description(surf->base.format);
1044 for (i = 0; i < 4; i++) {
1045 if (desc->channel[i].type != UTIL_FORMAT_TYPE_VOID) {
1046 break;
1047 }
1048 }
1049
1050 color_attrib = S_028C74_TILE_SPLIT(tile_split)|
1051 S_028C74_NUM_BANKS(nbanks) |
1052 S_028C74_BANK_WIDTH(bankw) |
1053 S_028C74_BANK_HEIGHT(bankh) |
1054 S_028C74_MACRO_TILE_ASPECT(macro_aspect) |
1055 S_028C74_NON_DISP_TILING_ORDER(non_disp_tiling) |
1056 S_028C74_FMASK_BANK_HEIGHT(fmask_bankh);
1057
1058 if (rctx->b.chip_class == CAYMAN) {
1059 color_attrib |= S_028C74_FORCE_DST_ALPHA_1(desc->swizzle[3] ==
1060 UTIL_FORMAT_SWIZZLE_1);
1061
1062 if (rtex->resource.b.b.nr_samples > 1) {
1063 unsigned log_samples = util_logbase2(rtex->resource.b.b.nr_samples);
1064 color_attrib |= S_028C74_NUM_SAMPLES(log_samples) |
1065 S_028C74_NUM_FRAGMENTS(log_samples);
1066 }
1067 }
1068
1069 ntype = V_028C70_NUMBER_UNORM;
1070 if (desc->colorspace == UTIL_FORMAT_COLORSPACE_SRGB)
1071 ntype = V_028C70_NUMBER_SRGB;
1072 else if (desc->channel[i].type == UTIL_FORMAT_TYPE_SIGNED) {
1073 if (desc->channel[i].normalized)
1074 ntype = V_028C70_NUMBER_SNORM;
1075 else if (desc->channel[i].pure_integer)
1076 ntype = V_028C70_NUMBER_SINT;
1077 } else if (desc->channel[i].type == UTIL_FORMAT_TYPE_UNSIGNED) {
1078 if (desc->channel[i].normalized)
1079 ntype = V_028C70_NUMBER_UNORM;
1080 else if (desc->channel[i].pure_integer)
1081 ntype = V_028C70_NUMBER_UINT;
1082 }
1083
1084 format = r600_translate_colorformat(rctx->b.chip_class, surf->base.format);
1085 assert(format != ~0);
1086
1087 swap = r600_translate_colorswap(surf->base.format);
1088 assert(swap != ~0);
1089
1090 if (rtex->resource.b.b.usage == PIPE_USAGE_STAGING) {
1091 endian = ENDIAN_NONE;
1092 } else {
1093 endian = r600_colorformat_endian_swap(format);
1094 }
1095
1096 /* blend clamp should be set for all NORM/SRGB types */
1097 if (ntype == V_028C70_NUMBER_UNORM || ntype == V_028C70_NUMBER_SNORM ||
1098 ntype == V_028C70_NUMBER_SRGB)
1099 blend_clamp = 1;
1100
1101 /* set blend bypass according to docs if SINT/UINT or
1102 8/24 COLOR variants */
1103 if (ntype == V_028C70_NUMBER_UINT || ntype == V_028C70_NUMBER_SINT ||
1104 format == V_028C70_COLOR_8_24 || format == V_028C70_COLOR_24_8 ||
1105 format == V_028C70_COLOR_X24_8_32_FLOAT) {
1106 blend_clamp = 0;
1107 blend_bypass = 1;
1108 }
1109
1110 surf->alphatest_bypass = ntype == V_028C70_NUMBER_UINT || ntype == V_028C70_NUMBER_SINT;
1111
1112 color_info |= S_028C70_FORMAT(format) |
1113 S_028C70_COMP_SWAP(swap) |
1114 S_028C70_BLEND_CLAMP(blend_clamp) |
1115 S_028C70_BLEND_BYPASS(blend_bypass) |
1116 S_028C70_NUMBER_TYPE(ntype) |
1117 S_028C70_ENDIAN(endian);
1118
1119 /* EXPORT_NORM is an optimzation that can be enabled for better
1120 * performance in certain cases.
1121 * EXPORT_NORM can be enabled if:
1122 * - 11-bit or smaller UNORM/SNORM/SRGB
1123 * - 16-bit or smaller FLOAT
1124 */
1125 if (desc->colorspace != UTIL_FORMAT_COLORSPACE_ZS &&
1126 ((desc->channel[i].size < 12 &&
1127 desc->channel[i].type != UTIL_FORMAT_TYPE_FLOAT &&
1128 ntype != V_028C70_NUMBER_UINT && ntype != V_028C70_NUMBER_SINT) ||
1129 (desc->channel[i].size < 17 &&
1130 desc->channel[i].type == UTIL_FORMAT_TYPE_FLOAT))) {
1131 color_info |= S_028C70_SOURCE_FORMAT(V_028C70_EXPORT_4C_16BPC);
1132 surf->export_16bpc = true;
1133 }
1134
1135 if (rtex->fmask.size) {
1136 color_info |= S_028C70_COMPRESSION(1);
1137 }
1138
1139 base_offset = rtex->resource.gpu_address;
1140
1141 /* XXX handle enabling of CB beyond BASE8 which has different offset */
1142 surf->cb_color_base = (base_offset + offset) >> 8;
1143 surf->cb_color_dim = color_dim;
1144 surf->cb_color_info = color_info;
1145 surf->cb_color_pitch = S_028C64_PITCH_TILE_MAX(pitch);
1146 surf->cb_color_slice = S_028C68_SLICE_TILE_MAX(slice);
1147 surf->cb_color_view = color_view;
1148 surf->cb_color_attrib = color_attrib;
1149 if (rtex->fmask.size) {
1150 surf->cb_color_fmask = (base_offset + rtex->fmask.offset) >> 8;
1151 } else {
1152 surf->cb_color_fmask = surf->cb_color_base;
1153 }
1154 surf->cb_color_fmask_slice = S_028C88_TILE_MAX(rtex->fmask.slice_tile_max);
1155
1156 surf->color_initialized = true;
1157 }
1158
1159 static void evergreen_init_depth_surface(struct r600_context *rctx,
1160 struct r600_surface *surf)
1161 {
1162 struct r600_screen *rscreen = rctx->screen;
1163 struct r600_texture *rtex = (struct r600_texture*)surf->base.texture;
1164 unsigned level = surf->base.u.tex.level;
1165 struct radeon_surface_level *levelinfo = &rtex->surface.level[level];
1166 uint64_t offset;
1167 unsigned format, array_mode;
1168 unsigned macro_aspect, tile_split, bankh, bankw, nbanks;
1169
1170
1171 format = r600_translate_dbformat(surf->base.format);
1172 assert(format != ~0);
1173
1174 offset = rtex->resource.gpu_address;
1175 offset += rtex->surface.level[level].offset;
1176
1177 switch (rtex->surface.level[level].mode) {
1178 case RADEON_SURF_MODE_2D:
1179 array_mode = V_028C70_ARRAY_2D_TILED_THIN1;
1180 break;
1181 case RADEON_SURF_MODE_1D:
1182 case RADEON_SURF_MODE_LINEAR_ALIGNED:
1183 case RADEON_SURF_MODE_LINEAR:
1184 default:
1185 array_mode = V_028C70_ARRAY_1D_TILED_THIN1;
1186 break;
1187 }
1188 tile_split = rtex->surface.tile_split;
1189 macro_aspect = rtex->surface.mtilea;
1190 bankw = rtex->surface.bankw;
1191 bankh = rtex->surface.bankh;
1192 tile_split = eg_tile_split(tile_split);
1193 macro_aspect = eg_macro_tile_aspect(macro_aspect);
1194 bankw = eg_bank_wh(bankw);
1195 bankh = eg_bank_wh(bankh);
1196 nbanks = eg_num_banks(rscreen->b.tiling_info.num_banks);
1197 offset >>= 8;
1198
1199 surf->db_z_info = S_028040_ARRAY_MODE(array_mode) |
1200 S_028040_FORMAT(format) |
1201 S_028040_TILE_SPLIT(tile_split)|
1202 S_028040_NUM_BANKS(nbanks) |
1203 S_028040_BANK_WIDTH(bankw) |
1204 S_028040_BANK_HEIGHT(bankh) |
1205 S_028040_MACRO_TILE_ASPECT(macro_aspect);
1206 if (rscreen->b.chip_class == CAYMAN && rtex->resource.b.b.nr_samples > 1) {
1207 surf->db_z_info |= S_028040_NUM_SAMPLES(util_logbase2(rtex->resource.b.b.nr_samples));
1208 }
1209
1210 assert(levelinfo->nblk_x % 8 == 0 && levelinfo->nblk_y % 8 == 0);
1211
1212 surf->db_depth_base = offset;
1213 surf->db_depth_view = S_028008_SLICE_START(surf->base.u.tex.first_layer) |
1214 S_028008_SLICE_MAX(surf->base.u.tex.last_layer);
1215 surf->db_depth_size = S_028058_PITCH_TILE_MAX(levelinfo->nblk_x / 8 - 1) |
1216 S_028058_HEIGHT_TILE_MAX(levelinfo->nblk_y / 8 - 1);
1217 surf->db_depth_slice = S_02805C_SLICE_TILE_MAX(levelinfo->nblk_x *
1218 levelinfo->nblk_y / 64 - 1);
1219
1220 switch (surf->base.format) {
1221 case PIPE_FORMAT_Z24X8_UNORM:
1222 case PIPE_FORMAT_Z24_UNORM_S8_UINT:
1223 case PIPE_FORMAT_X8Z24_UNORM:
1224 case PIPE_FORMAT_S8_UINT_Z24_UNORM:
1225 surf->pa_su_poly_offset_db_fmt_cntl =
1226 S_028B78_POLY_OFFSET_NEG_NUM_DB_BITS((char)-24);
1227 break;
1228 case PIPE_FORMAT_Z32_FLOAT:
1229 case PIPE_FORMAT_Z32_FLOAT_S8X24_UINT:
1230 surf->pa_su_poly_offset_db_fmt_cntl =
1231 S_028B78_POLY_OFFSET_NEG_NUM_DB_BITS((char)-23) |
1232 S_028B78_POLY_OFFSET_DB_IS_FLOAT_FMT(1);
1233 break;
1234 case PIPE_FORMAT_Z16_UNORM:
1235 surf->pa_su_poly_offset_db_fmt_cntl =
1236 S_028B78_POLY_OFFSET_NEG_NUM_DB_BITS((char)-16);
1237 break;
1238 default:;
1239 }
1240
1241 if (rtex->surface.flags & RADEON_SURF_SBUFFER) {
1242 uint64_t stencil_offset;
1243 unsigned stile_split = rtex->surface.stencil_tile_split;
1244
1245 stile_split = eg_tile_split(stile_split);
1246
1247 stencil_offset = rtex->surface.stencil_level[level].offset;
1248 stencil_offset += rtex->resource.gpu_address;
1249
1250 surf->db_stencil_base = stencil_offset >> 8;
1251 surf->db_stencil_info = S_028044_FORMAT(V_028044_STENCIL_8) |
1252 S_028044_TILE_SPLIT(stile_split);
1253 } else {
1254 surf->db_stencil_base = offset;
1255 /* DRM 2.6.18 allows the INVALID format to disable stencil.
1256 * Older kernels are out of luck. */
1257 surf->db_stencil_info = rctx->screen->b.info.drm_minor >= 18 ?
1258 S_028044_FORMAT(V_028044_STENCIL_INVALID) :
1259 S_028044_FORMAT(V_028044_STENCIL_8);
1260 }
1261
1262 /* use htile only for first level */
1263 if (rtex->htile_buffer && !level) {
1264 uint64_t va = rtex->htile_buffer->gpu_address;
1265 surf->db_htile_data_base = va >> 8;
1266 surf->db_htile_surface = S_028ABC_HTILE_WIDTH(1) |
1267 S_028ABC_HTILE_HEIGHT(1) |
1268 S_028ABC_FULL_CACHE(1);
1269 surf->db_z_info |= S_028040_TILE_SURFACE_ENABLE(1);
1270 surf->db_preload_control = 0;
1271 }
1272
1273 surf->depth_initialized = true;
1274 }
1275
1276 static void evergreen_set_framebuffer_state(struct pipe_context *ctx,
1277 const struct pipe_framebuffer_state *state)
1278 {
1279 struct r600_context *rctx = (struct r600_context *)ctx;
1280 struct r600_surface *surf;
1281 struct r600_texture *rtex;
1282 uint32_t i, log_samples;
1283
1284 if (rctx->framebuffer.state.nr_cbufs) {
1285 rctx->b.flags |= R600_CONTEXT_WAIT_3D_IDLE | R600_CONTEXT_FLUSH_AND_INV;
1286 rctx->b.flags |= R600_CONTEXT_FLUSH_AND_INV_CB |
1287 R600_CONTEXT_FLUSH_AND_INV_CB_META;
1288 }
1289 if (rctx->framebuffer.state.zsbuf) {
1290 rctx->b.flags |= R600_CONTEXT_WAIT_3D_IDLE | R600_CONTEXT_FLUSH_AND_INV;
1291 rctx->b.flags |= R600_CONTEXT_FLUSH_AND_INV_DB;
1292
1293 rtex = (struct r600_texture*)rctx->framebuffer.state.zsbuf->texture;
1294 if (rtex->htile_buffer) {
1295 rctx->b.flags |= R600_CONTEXT_FLUSH_AND_INV_DB_META;
1296 }
1297 }
1298
1299 util_copy_framebuffer_state(&rctx->framebuffer.state, state);
1300
1301 /* Colorbuffers. */
1302 rctx->framebuffer.export_16bpc = state->nr_cbufs != 0;
1303 rctx->framebuffer.cb0_is_integer = state->nr_cbufs && state->cbufs[0] &&
1304 util_format_is_pure_integer(state->cbufs[0]->format);
1305 rctx->framebuffer.compressed_cb_mask = 0;
1306 rctx->framebuffer.nr_samples = util_framebuffer_get_num_samples(state);
1307
1308 for (i = 0; i < state->nr_cbufs; i++) {
1309 surf = (struct r600_surface*)state->cbufs[i];
1310 if (!surf)
1311 continue;
1312
1313 rtex = (struct r600_texture*)surf->base.texture;
1314
1315 r600_context_add_resource_size(ctx, state->cbufs[i]->texture);
1316
1317 if (!surf->color_initialized) {
1318 evergreen_init_color_surface(rctx, surf);
1319 }
1320
1321 if (!surf->export_16bpc) {
1322 rctx->framebuffer.export_16bpc = false;
1323 }
1324
1325 if (rtex->fmask.size && rtex->cmask.size) {
1326 rctx->framebuffer.compressed_cb_mask |= 1 << i;
1327 }
1328 }
1329
1330 /* Update alpha-test state dependencies.
1331 * Alpha-test is done on the first colorbuffer only. */
1332 if (state->nr_cbufs) {
1333 bool alphatest_bypass = false;
1334 bool export_16bpc = true;
1335
1336 surf = (struct r600_surface*)state->cbufs[0];
1337 if (surf) {
1338 alphatest_bypass = surf->alphatest_bypass;
1339 export_16bpc = surf->export_16bpc;
1340 }
1341
1342 if (rctx->alphatest_state.bypass != alphatest_bypass) {
1343 rctx->alphatest_state.bypass = alphatest_bypass;
1344 rctx->alphatest_state.atom.dirty = true;
1345 }
1346 if (rctx->alphatest_state.cb0_export_16bpc != export_16bpc) {
1347 rctx->alphatest_state.cb0_export_16bpc = export_16bpc;
1348 rctx->alphatest_state.atom.dirty = true;
1349 }
1350 }
1351
1352 /* ZS buffer. */
1353 if (state->zsbuf) {
1354 surf = (struct r600_surface*)state->zsbuf;
1355
1356 r600_context_add_resource_size(ctx, state->zsbuf->texture);
1357
1358 if (!surf->depth_initialized) {
1359 evergreen_init_depth_surface(rctx, surf);
1360 }
1361
1362 if (state->zsbuf->format != rctx->poly_offset_state.zs_format) {
1363 rctx->poly_offset_state.zs_format = state->zsbuf->format;
1364 rctx->poly_offset_state.atom.dirty = true;
1365 }
1366
1367 if (rctx->db_state.rsurf != surf) {
1368 rctx->db_state.rsurf = surf;
1369 rctx->db_state.atom.dirty = true;
1370 rctx->db_misc_state.atom.dirty = true;
1371 }
1372 } else if (rctx->db_state.rsurf) {
1373 rctx->db_state.rsurf = NULL;
1374 rctx->db_state.atom.dirty = true;
1375 rctx->db_misc_state.atom.dirty = true;
1376 }
1377
1378 if (rctx->cb_misc_state.nr_cbufs != state->nr_cbufs) {
1379 rctx->cb_misc_state.nr_cbufs = state->nr_cbufs;
1380 rctx->cb_misc_state.atom.dirty = true;
1381 }
1382
1383 if (state->nr_cbufs == 0 && rctx->alphatest_state.bypass) {
1384 rctx->alphatest_state.bypass = false;
1385 rctx->alphatest_state.atom.dirty = true;
1386 }
1387
1388 log_samples = util_logbase2(rctx->framebuffer.nr_samples);
1389 /* This is for Cayman to program SAMPLE_RATE, and for RV770 to fix a hw bug. */
1390 if ((rctx->b.chip_class == CAYMAN ||
1391 rctx->b.family == CHIP_RV770) &&
1392 rctx->db_misc_state.log_samples != log_samples) {
1393 rctx->db_misc_state.log_samples = log_samples;
1394 rctx->db_misc_state.atom.dirty = true;
1395 }
1396
1397
1398 /* Calculate the CS size. */
1399 rctx->framebuffer.atom.num_dw = 4; /* SCISSOR */
1400
1401 /* MSAA. */
1402 if (rctx->b.chip_class == EVERGREEN)
1403 rctx->framebuffer.atom.num_dw += 14; /* Evergreen */
1404 else
1405 rctx->framebuffer.atom.num_dw += 28; /* Cayman */
1406
1407 /* Colorbuffers. */
1408 rctx->framebuffer.atom.num_dw += state->nr_cbufs * 23;
1409 if (rctx->keep_tiling_flags)
1410 rctx->framebuffer.atom.num_dw += state->nr_cbufs * 2;
1411 rctx->framebuffer.atom.num_dw += (12 - state->nr_cbufs) * 3;
1412
1413 /* ZS buffer. */
1414 if (state->zsbuf) {
1415 rctx->framebuffer.atom.num_dw += 24;
1416 if (rctx->keep_tiling_flags)
1417 rctx->framebuffer.atom.num_dw += 2;
1418 } else if (rctx->screen->b.info.drm_minor >= 18) {
1419 rctx->framebuffer.atom.num_dw += 4;
1420 }
1421
1422 rctx->framebuffer.atom.dirty = true;
1423 }
1424
1425
1426 /* 8xMSAA */
1427 static uint32_t sample_locs_8x[] = {
1428 FILL_SREG(-1, 1, 1, 5, 3, -5, 5, 3),
1429 FILL_SREG(-7, -1, -3, -7, 7, -3, -5, 7),
1430 FILL_SREG(-1, 1, 1, 5, 3, -5, 5, 3),
1431 FILL_SREG(-7, -1, -3, -7, 7, -3, -5, 7),
1432 FILL_SREG(-1, 1, 1, 5, 3, -5, 5, 3),
1433 FILL_SREG(-7, -1, -3, -7, 7, -3, -5, 7),
1434 FILL_SREG(-1, 1, 1, 5, 3, -5, 5, 3),
1435 FILL_SREG(-7, -1, -3, -7, 7, -3, -5, 7),
1436 };
1437 static unsigned max_dist_8x = 7;
1438
1439 static void evergreen_get_sample_position(struct pipe_context *ctx,
1440 unsigned sample_count,
1441 unsigned sample_index,
1442 float *out_value)
1443 {
1444 int offset, index;
1445 struct {
1446 int idx:4;
1447 } val;
1448 switch (sample_count) {
1449 case 1:
1450 default:
1451 out_value[0] = out_value[1] = 0.5;
1452 break;
1453 case 2:
1454 offset = 4 * (sample_index * 2);
1455 val.idx = (eg_sample_locs_2x[0] >> offset) & 0xf;
1456 out_value[0] = (float)(val.idx + 8) / 16.0f;
1457 val.idx = (eg_sample_locs_2x[0] >> (offset + 4)) & 0xf;
1458 out_value[1] = (float)(val.idx + 8) / 16.0f;
1459 break;
1460 case 4:
1461 offset = 4 * (sample_index * 2);
1462 val.idx = (eg_sample_locs_4x[0] >> offset) & 0xf;
1463 out_value[0] = (float)(val.idx + 8) / 16.0f;
1464 val.idx = (eg_sample_locs_4x[0] >> (offset + 4)) & 0xf;
1465 out_value[1] = (float)(val.idx + 8) / 16.0f;
1466 break;
1467 case 8:
1468 offset = 4 * (sample_index % 4 * 2);
1469 index = (sample_index / 4);
1470 val.idx = (sample_locs_8x[index] >> offset) & 0xf;
1471 out_value[0] = (float)(val.idx + 8) / 16.0f;
1472 val.idx = (sample_locs_8x[index] >> (offset + 4)) & 0xf;
1473 out_value[1] = (float)(val.idx + 8) / 16.0f;
1474 break;
1475 }
1476 }
1477
1478 static void evergreen_emit_msaa_state(struct r600_context *rctx, int nr_samples)
1479 {
1480
1481 struct radeon_winsys_cs *cs = rctx->b.rings.gfx.cs;
1482 unsigned max_dist = 0;
1483
1484 switch (nr_samples) {
1485 default:
1486 nr_samples = 0;
1487 break;
1488 case 2:
1489 r600_write_context_reg_seq(cs, R_028C1C_PA_SC_AA_SAMPLE_LOCS_0, Elements(eg_sample_locs_2x));
1490 radeon_emit_array(cs, eg_sample_locs_2x, Elements(eg_sample_locs_2x));
1491 max_dist = eg_max_dist_2x;
1492 break;
1493 case 4:
1494 r600_write_context_reg_seq(cs, R_028C1C_PA_SC_AA_SAMPLE_LOCS_0, Elements(eg_sample_locs_4x));
1495 radeon_emit_array(cs, eg_sample_locs_4x, Elements(eg_sample_locs_4x));
1496 max_dist = eg_max_dist_4x;
1497 break;
1498 case 8:
1499 r600_write_context_reg_seq(cs, R_028C1C_PA_SC_AA_SAMPLE_LOCS_0, Elements(sample_locs_8x));
1500 radeon_emit_array(cs, sample_locs_8x, Elements(sample_locs_8x));
1501 max_dist = max_dist_8x;
1502 break;
1503 }
1504
1505 if (nr_samples > 1) {
1506 r600_write_context_reg_seq(cs, R_028C00_PA_SC_LINE_CNTL, 2);
1507 radeon_emit(cs, S_028C00_LAST_PIXEL(1) |
1508 S_028C00_EXPAND_LINE_WIDTH(1)); /* R_028C00_PA_SC_LINE_CNTL */
1509 radeon_emit(cs, S_028C04_MSAA_NUM_SAMPLES(util_logbase2(nr_samples)) |
1510 S_028C04_MAX_SAMPLE_DIST(max_dist)); /* R_028C04_PA_SC_AA_CONFIG */
1511 } else {
1512 r600_write_context_reg_seq(cs, R_028C00_PA_SC_LINE_CNTL, 2);
1513 radeon_emit(cs, S_028C00_LAST_PIXEL(1)); /* R_028C00_PA_SC_LINE_CNTL */
1514 radeon_emit(cs, 0); /* R_028C04_PA_SC_AA_CONFIG */
1515 }
1516 }
1517
1518 static void evergreen_emit_framebuffer_state(struct r600_context *rctx, struct r600_atom *atom)
1519 {
1520 struct radeon_winsys_cs *cs = rctx->b.rings.gfx.cs;
1521 struct pipe_framebuffer_state *state = &rctx->framebuffer.state;
1522 unsigned nr_cbufs = state->nr_cbufs;
1523 unsigned i, tl, br;
1524 struct r600_texture *tex = NULL;
1525 struct r600_surface *cb = NULL;
1526
1527 /* XXX support more colorbuffers once we need them */
1528 assert(nr_cbufs <= 8);
1529 if (nr_cbufs > 8)
1530 nr_cbufs = 8;
1531
1532 /* Colorbuffers. */
1533 for (i = 0; i < nr_cbufs; i++) {
1534 unsigned reloc, cmask_reloc;
1535
1536 cb = (struct r600_surface*)state->cbufs[i];
1537 if (!cb) {
1538 r600_write_context_reg(cs, R_028C70_CB_COLOR0_INFO + i * 0x3C,
1539 S_028C70_FORMAT(V_028C70_COLOR_INVALID));
1540 continue;
1541 }
1542
1543 tex = (struct r600_texture *)cb->base.texture;
1544 reloc = r600_context_bo_reloc(&rctx->b,
1545 &rctx->b.rings.gfx,
1546 (struct r600_resource*)cb->base.texture,
1547 RADEON_USAGE_READWRITE,
1548 tex->surface.nsamples > 1 ?
1549 RADEON_PRIO_COLOR_BUFFER_MSAA :
1550 RADEON_PRIO_COLOR_BUFFER);
1551
1552 if (tex->cmask_buffer && tex->cmask_buffer != &tex->resource) {
1553 cmask_reloc = r600_context_bo_reloc(&rctx->b, &rctx->b.rings.gfx,
1554 tex->cmask_buffer, RADEON_USAGE_READWRITE,
1555 RADEON_PRIO_COLOR_META);
1556 } else {
1557 cmask_reloc = reloc;
1558 }
1559
1560 r600_write_context_reg_seq(cs, R_028C60_CB_COLOR0_BASE + i * 0x3C, 13);
1561 radeon_emit(cs, cb->cb_color_base); /* R_028C60_CB_COLOR0_BASE */
1562 radeon_emit(cs, cb->cb_color_pitch); /* R_028C64_CB_COLOR0_PITCH */
1563 radeon_emit(cs, cb->cb_color_slice); /* R_028C68_CB_COLOR0_SLICE */
1564 radeon_emit(cs, cb->cb_color_view); /* R_028C6C_CB_COLOR0_VIEW */
1565 radeon_emit(cs, cb->cb_color_info | tex->cb_color_info); /* R_028C70_CB_COLOR0_INFO */
1566 radeon_emit(cs, cb->cb_color_attrib); /* R_028C74_CB_COLOR0_ATTRIB */
1567 radeon_emit(cs, cb->cb_color_dim); /* R_028C78_CB_COLOR0_DIM */
1568 radeon_emit(cs, tex->cmask.base_address_reg); /* R_028C7C_CB_COLOR0_CMASK */
1569 radeon_emit(cs, tex->cmask.slice_tile_max); /* R_028C80_CB_COLOR0_CMASK_SLICE */
1570 radeon_emit(cs, cb->cb_color_fmask); /* R_028C84_CB_COLOR0_FMASK */
1571 radeon_emit(cs, cb->cb_color_fmask_slice); /* R_028C88_CB_COLOR0_FMASK_SLICE */
1572 radeon_emit(cs, tex->color_clear_value[0]); /* R_028C8C_CB_COLOR0_CLEAR_WORD0 */
1573 radeon_emit(cs, tex->color_clear_value[1]); /* R_028C90_CB_COLOR0_CLEAR_WORD1 */
1574
1575 radeon_emit(cs, PKT3(PKT3_NOP, 0, 0)); /* R_028C60_CB_COLOR0_BASE */
1576 radeon_emit(cs, reloc);
1577
1578 if (!rctx->keep_tiling_flags) {
1579 radeon_emit(cs, PKT3(PKT3_NOP, 0, 0)); /* R_028C70_CB_COLOR0_INFO */
1580 radeon_emit(cs, reloc);
1581 }
1582
1583 radeon_emit(cs, PKT3(PKT3_NOP, 0, 0)); /* R_028C74_CB_COLOR0_ATTRIB */
1584 radeon_emit(cs, reloc);
1585
1586 radeon_emit(cs, PKT3(PKT3_NOP, 0, 0)); /* R_028C7C_CB_COLOR0_CMASK */
1587 radeon_emit(cs, cmask_reloc);
1588
1589 radeon_emit(cs, PKT3(PKT3_NOP, 0, 0)); /* R_028C84_CB_COLOR0_FMASK */
1590 radeon_emit(cs, reloc);
1591 }
1592 /* set CB_COLOR1_INFO for possible dual-src blending */
1593 if (i == 1 && state->cbufs[0]) {
1594 r600_write_context_reg(cs, R_028C70_CB_COLOR0_INFO + 1 * 0x3C,
1595 cb->cb_color_info | tex->cb_color_info);
1596
1597 if (!rctx->keep_tiling_flags) {
1598 unsigned reloc = r600_context_bo_reloc(&rctx->b,
1599 &rctx->b.rings.gfx,
1600 (struct r600_resource*)state->cbufs[0]->texture,
1601 RADEON_USAGE_READWRITE,
1602 RADEON_PRIO_COLOR_BUFFER);
1603
1604 radeon_emit(cs, PKT3(PKT3_NOP, 0, 0)); /* R_028C70_CB_COLOR0_INFO */
1605 radeon_emit(cs, reloc);
1606 }
1607 i++;
1608 }
1609 if (rctx->keep_tiling_flags) {
1610 for (; i < 8 ; i++) {
1611 r600_write_context_reg(cs, R_028C70_CB_COLOR0_INFO + i * 0x3C, 0);
1612 }
1613 for (; i < 12; i++) {
1614 r600_write_context_reg(cs, R_028E50_CB_COLOR8_INFO + (i - 8) * 0x1C, 0);
1615 }
1616 }
1617
1618 /* ZS buffer. */
1619 if (state->zsbuf) {
1620 struct r600_surface *zb = (struct r600_surface*)state->zsbuf;
1621 unsigned reloc = r600_context_bo_reloc(&rctx->b,
1622 &rctx->b.rings.gfx,
1623 (struct r600_resource*)state->zsbuf->texture,
1624 RADEON_USAGE_READWRITE,
1625 zb->base.texture->nr_samples > 1 ?
1626 RADEON_PRIO_DEPTH_BUFFER_MSAA :
1627 RADEON_PRIO_DEPTH_BUFFER);
1628
1629 r600_write_context_reg(cs, R_028B78_PA_SU_POLY_OFFSET_DB_FMT_CNTL,
1630 zb->pa_su_poly_offset_db_fmt_cntl);
1631 r600_write_context_reg(cs, R_028008_DB_DEPTH_VIEW, zb->db_depth_view);
1632
1633 r600_write_context_reg_seq(cs, R_028040_DB_Z_INFO, 8);
1634 radeon_emit(cs, zb->db_z_info); /* R_028040_DB_Z_INFO */
1635 radeon_emit(cs, zb->db_stencil_info); /* R_028044_DB_STENCIL_INFO */
1636 radeon_emit(cs, zb->db_depth_base); /* R_028048_DB_Z_READ_BASE */
1637 radeon_emit(cs, zb->db_stencil_base); /* R_02804C_DB_STENCIL_READ_BASE */
1638 radeon_emit(cs, zb->db_depth_base); /* R_028050_DB_Z_WRITE_BASE */
1639 radeon_emit(cs, zb->db_stencil_base); /* R_028054_DB_STENCIL_WRITE_BASE */
1640 radeon_emit(cs, zb->db_depth_size); /* R_028058_DB_DEPTH_SIZE */
1641 radeon_emit(cs, zb->db_depth_slice); /* R_02805C_DB_DEPTH_SLICE */
1642
1643 if (!rctx->keep_tiling_flags) {
1644 radeon_emit(cs, PKT3(PKT3_NOP, 0, 0)); /* R_028040_DB_Z_INFO */
1645 radeon_emit(cs, reloc);
1646 }
1647
1648 radeon_emit(cs, PKT3(PKT3_NOP, 0, 0)); /* R_028048_DB_Z_READ_BASE */
1649 radeon_emit(cs, reloc);
1650
1651 radeon_emit(cs, PKT3(PKT3_NOP, 0, 0)); /* R_02804C_DB_STENCIL_READ_BASE */
1652 radeon_emit(cs, reloc);
1653
1654 radeon_emit(cs, PKT3(PKT3_NOP, 0, 0)); /* R_028050_DB_Z_WRITE_BASE */
1655 radeon_emit(cs, reloc);
1656
1657 radeon_emit(cs, PKT3(PKT3_NOP, 0, 0)); /* R_028054_DB_STENCIL_WRITE_BASE */
1658 radeon_emit(cs, reloc);
1659 } else if (rctx->screen->b.info.drm_minor >= 18) {
1660 /* DRM 2.6.18 allows the INVALID format to disable depth/stencil.
1661 * Older kernels are out of luck. */
1662 r600_write_context_reg_seq(cs, R_028040_DB_Z_INFO, 2);
1663 radeon_emit(cs, S_028040_FORMAT(V_028040_Z_INVALID)); /* R_028040_DB_Z_INFO */
1664 radeon_emit(cs, S_028044_FORMAT(V_028044_STENCIL_INVALID)); /* R_028044_DB_STENCIL_INFO */
1665 }
1666
1667 /* Framebuffer dimensions. */
1668 evergreen_get_scissor_rect(rctx, 0, 0, state->width, state->height, &tl, &br);
1669
1670 r600_write_context_reg_seq(cs, R_028204_PA_SC_WINDOW_SCISSOR_TL, 2);
1671 radeon_emit(cs, tl); /* R_028204_PA_SC_WINDOW_SCISSOR_TL */
1672 radeon_emit(cs, br); /* R_028208_PA_SC_WINDOW_SCISSOR_BR */
1673
1674 if (rctx->b.chip_class == EVERGREEN) {
1675 evergreen_emit_msaa_state(rctx, rctx->framebuffer.nr_samples);
1676 } else {
1677 cayman_emit_msaa_sample_locs(cs, rctx->framebuffer.nr_samples);
1678 cayman_emit_msaa_config(cs, rctx->framebuffer.nr_samples, 1);
1679 }
1680 }
1681
1682 static void evergreen_emit_polygon_offset(struct r600_context *rctx, struct r600_atom *a)
1683 {
1684 struct radeon_winsys_cs *cs = rctx->b.rings.gfx.cs;
1685 struct r600_poly_offset_state *state = (struct r600_poly_offset_state*)a;
1686 float offset_units = state->offset_units;
1687 float offset_scale = state->offset_scale;
1688
1689 switch (state->zs_format) {
1690 case PIPE_FORMAT_Z24X8_UNORM:
1691 case PIPE_FORMAT_Z24_UNORM_S8_UINT:
1692 case PIPE_FORMAT_X8Z24_UNORM:
1693 case PIPE_FORMAT_S8_UINT_Z24_UNORM:
1694 offset_units *= 2.0f;
1695 break;
1696 case PIPE_FORMAT_Z16_UNORM:
1697 offset_units *= 4.0f;
1698 break;
1699 default:;
1700 }
1701
1702 r600_write_context_reg_seq(cs, R_028B80_PA_SU_POLY_OFFSET_FRONT_SCALE, 4);
1703 radeon_emit(cs, fui(offset_scale));
1704 radeon_emit(cs, fui(offset_units));
1705 radeon_emit(cs, fui(offset_scale));
1706 radeon_emit(cs, fui(offset_units));
1707 }
1708
1709 static void evergreen_emit_cb_misc_state(struct r600_context *rctx, struct r600_atom *atom)
1710 {
1711 struct radeon_winsys_cs *cs = rctx->b.rings.gfx.cs;
1712 struct r600_cb_misc_state *a = (struct r600_cb_misc_state*)atom;
1713 unsigned fb_colormask = (1ULL << ((unsigned)a->nr_cbufs * 4)) - 1;
1714 unsigned ps_colormask = (1ULL << ((unsigned)a->nr_ps_color_outputs * 4)) - 1;
1715
1716 r600_write_context_reg_seq(cs, R_028238_CB_TARGET_MASK, 2);
1717 radeon_emit(cs, a->blend_colormask & fb_colormask); /* R_028238_CB_TARGET_MASK */
1718 /* Always enable the first colorbuffer in CB_SHADER_MASK. This
1719 * will assure that the alpha-test will work even if there is
1720 * no colorbuffer bound. */
1721 radeon_emit(cs, 0xf | (a->dual_src_blend ? ps_colormask : 0) | fb_colormask); /* R_02823C_CB_SHADER_MASK */
1722 }
1723
1724 static void evergreen_emit_db_state(struct r600_context *rctx, struct r600_atom *atom)
1725 {
1726 struct radeon_winsys_cs *cs = rctx->b.rings.gfx.cs;
1727 struct r600_db_state *a = (struct r600_db_state*)atom;
1728
1729 if (a->rsurf && a->rsurf->db_htile_surface) {
1730 struct r600_texture *rtex = (struct r600_texture *)a->rsurf->base.texture;
1731 unsigned reloc_idx;
1732
1733 r600_write_context_reg(cs, R_02802C_DB_DEPTH_CLEAR, fui(rtex->depth_clear_value));
1734 r600_write_context_reg(cs, R_028ABC_DB_HTILE_SURFACE, a->rsurf->db_htile_surface);
1735 r600_write_context_reg(cs, R_028AC8_DB_PRELOAD_CONTROL, a->rsurf->db_preload_control);
1736 r600_write_context_reg(cs, R_028014_DB_HTILE_DATA_BASE, a->rsurf->db_htile_data_base);
1737 reloc_idx = r600_context_bo_reloc(&rctx->b, &rctx->b.rings.gfx, rtex->htile_buffer,
1738 RADEON_USAGE_READWRITE, RADEON_PRIO_DEPTH_META);
1739 cs->buf[cs->cdw++] = PKT3(PKT3_NOP, 0, 0);
1740 cs->buf[cs->cdw++] = reloc_idx;
1741 } else {
1742 r600_write_context_reg(cs, R_028ABC_DB_HTILE_SURFACE, 0);
1743 r600_write_context_reg(cs, R_028AC8_DB_PRELOAD_CONTROL, 0);
1744 }
1745 }
1746
1747 static void evergreen_emit_db_misc_state(struct r600_context *rctx, struct r600_atom *atom)
1748 {
1749 struct radeon_winsys_cs *cs = rctx->b.rings.gfx.cs;
1750 struct r600_db_misc_state *a = (struct r600_db_misc_state*)atom;
1751 unsigned db_render_control = 0;
1752 unsigned db_count_control = 0;
1753 unsigned db_render_override =
1754 S_02800C_FORCE_HIS_ENABLE0(V_02800C_FORCE_DISABLE) |
1755 S_02800C_FORCE_HIS_ENABLE1(V_02800C_FORCE_DISABLE) |
1756 /* There is a hang with HTILE if stencil is used and
1757 * fast stencil is enabled. */
1758 S_02800C_FAST_STENCIL_DISABLE(1);
1759
1760 if (a->occlusion_query_enabled) {
1761 db_count_control |= S_028004_PERFECT_ZPASS_COUNTS(1);
1762 if (rctx->b.chip_class == CAYMAN) {
1763 db_count_control |= S_028004_SAMPLE_RATE(a->log_samples);
1764 }
1765 db_render_override |= S_02800C_NOOP_CULL_DISABLE(1);
1766 }
1767 /* FIXME we should be able to use hyperz even if we are not writing to
1768 * zbuffer but somehow this trigger GPU lockup. See :
1769 *
1770 * https://bugs.freedesktop.org/show_bug.cgi?id=60848
1771 *
1772 * Disable hyperz for now if not writing to zbuffer.
1773 */
1774 if (rctx->db_state.rsurf && rctx->db_state.rsurf->db_htile_surface && rctx->zwritemask) {
1775 /* FORCE_OFF means HiZ/HiS are determined by DB_SHADER_CONTROL */
1776 db_render_override |= S_02800C_FORCE_HIZ_ENABLE(V_02800C_FORCE_OFF);
1777 /* This is to fix a lockup when hyperz and alpha test are enabled at
1778 * the same time somehow GPU get confuse on which order to pick for
1779 * z test
1780 */
1781 if (rctx->alphatest_state.sx_alpha_test_control) {
1782 db_render_override |= S_02800C_FORCE_SHADER_Z_ORDER(1);
1783 }
1784 } else {
1785 db_render_override |= S_02800C_FORCE_HIZ_ENABLE(V_02800C_FORCE_DISABLE);
1786 }
1787 if (a->flush_depthstencil_through_cb) {
1788 assert(a->copy_depth || a->copy_stencil);
1789
1790 db_render_control |= S_028000_DEPTH_COPY_ENABLE(a->copy_depth) |
1791 S_028000_STENCIL_COPY_ENABLE(a->copy_stencil) |
1792 S_028000_COPY_CENTROID(1) |
1793 S_028000_COPY_SAMPLE(a->copy_sample);
1794 } else if (a->flush_depthstencil_in_place) {
1795 db_render_control |= S_028000_DEPTH_COMPRESS_DISABLE(1) |
1796 S_028000_STENCIL_COMPRESS_DISABLE(1);
1797 db_render_override |= S_02800C_DISABLE_PIXEL_RATE_TILES(1);
1798 }
1799 if (a->htile_clear) {
1800 /* FIXME we might want to disable cliprect here */
1801 db_render_control |= S_028000_DEPTH_CLEAR_ENABLE(1);
1802 }
1803
1804 r600_write_context_reg_seq(cs, R_028000_DB_RENDER_CONTROL, 2);
1805 radeon_emit(cs, db_render_control); /* R_028000_DB_RENDER_CONTROL */
1806 radeon_emit(cs, db_count_control); /* R_028004_DB_COUNT_CONTROL */
1807 r600_write_context_reg(cs, R_02800C_DB_RENDER_OVERRIDE, db_render_override);
1808 r600_write_context_reg(cs, R_02880C_DB_SHADER_CONTROL, a->db_shader_control);
1809 }
1810
1811 static void evergreen_emit_vertex_buffers(struct r600_context *rctx,
1812 struct r600_vertexbuf_state *state,
1813 unsigned resource_offset,
1814 unsigned pkt_flags)
1815 {
1816 struct radeon_winsys_cs *cs = rctx->b.rings.gfx.cs;
1817 uint32_t dirty_mask = state->dirty_mask;
1818
1819 while (dirty_mask) {
1820 struct pipe_vertex_buffer *vb;
1821 struct r600_resource *rbuffer;
1822 uint64_t va;
1823 unsigned buffer_index = u_bit_scan(&dirty_mask);
1824
1825 vb = &state->vb[buffer_index];
1826 rbuffer = (struct r600_resource*)vb->buffer;
1827 assert(rbuffer);
1828
1829 va = rbuffer->gpu_address + vb->buffer_offset;
1830
1831 /* fetch resources start at index 992 */
1832 radeon_emit(cs, PKT3(PKT3_SET_RESOURCE, 8, 0) | pkt_flags);
1833 radeon_emit(cs, (resource_offset + buffer_index) * 8);
1834 radeon_emit(cs, va); /* RESOURCEi_WORD0 */
1835 radeon_emit(cs, rbuffer->buf->size - vb->buffer_offset - 1); /* RESOURCEi_WORD1 */
1836 radeon_emit(cs, /* RESOURCEi_WORD2 */
1837 S_030008_ENDIAN_SWAP(r600_endian_swap(32)) |
1838 S_030008_STRIDE(vb->stride) |
1839 S_030008_BASE_ADDRESS_HI(va >> 32UL));
1840 radeon_emit(cs, /* RESOURCEi_WORD3 */
1841 S_03000C_DST_SEL_X(V_03000C_SQ_SEL_X) |
1842 S_03000C_DST_SEL_Y(V_03000C_SQ_SEL_Y) |
1843 S_03000C_DST_SEL_Z(V_03000C_SQ_SEL_Z) |
1844 S_03000C_DST_SEL_W(V_03000C_SQ_SEL_W));
1845 radeon_emit(cs, 0); /* RESOURCEi_WORD4 */
1846 radeon_emit(cs, 0); /* RESOURCEi_WORD5 */
1847 radeon_emit(cs, 0); /* RESOURCEi_WORD6 */
1848 radeon_emit(cs, 0xc0000000); /* RESOURCEi_WORD7 */
1849
1850 radeon_emit(cs, PKT3(PKT3_NOP, 0, 0) | pkt_flags);
1851 radeon_emit(cs, r600_context_bo_reloc(&rctx->b, &rctx->b.rings.gfx, rbuffer,
1852 RADEON_USAGE_READ, RADEON_PRIO_SHADER_BUFFER_RO));
1853 }
1854 state->dirty_mask = 0;
1855 }
1856
1857 static void evergreen_fs_emit_vertex_buffers(struct r600_context *rctx, struct r600_atom * atom)
1858 {
1859 evergreen_emit_vertex_buffers(rctx, &rctx->vertex_buffer_state, 992, 0);
1860 }
1861
1862 static void evergreen_cs_emit_vertex_buffers(struct r600_context *rctx, struct r600_atom * atom)
1863 {
1864 evergreen_emit_vertex_buffers(rctx, &rctx->cs_vertex_buffer_state, 816,
1865 RADEON_CP_PACKET3_COMPUTE_MODE);
1866 }
1867
1868 static void evergreen_emit_constant_buffers(struct r600_context *rctx,
1869 struct r600_constbuf_state *state,
1870 unsigned buffer_id_base,
1871 unsigned reg_alu_constbuf_size,
1872 unsigned reg_alu_const_cache,
1873 unsigned pkt_flags)
1874 {
1875 struct radeon_winsys_cs *cs = rctx->b.rings.gfx.cs;
1876 uint32_t dirty_mask = state->dirty_mask;
1877
1878 while (dirty_mask) {
1879 struct pipe_constant_buffer *cb;
1880 struct r600_resource *rbuffer;
1881 uint64_t va;
1882 unsigned buffer_index = ffs(dirty_mask) - 1;
1883 unsigned gs_ring_buffer = (buffer_index == R600_GS_RING_CONST_BUFFER);
1884
1885 cb = &state->cb[buffer_index];
1886 rbuffer = (struct r600_resource*)cb->buffer;
1887 assert(rbuffer);
1888
1889 va = rbuffer->gpu_address + cb->buffer_offset;
1890
1891 if (!gs_ring_buffer) {
1892 r600_write_context_reg_flag(cs, reg_alu_constbuf_size + buffer_index * 4,
1893 ALIGN_DIVUP(cb->buffer_size >> 4, 16), pkt_flags);
1894 r600_write_context_reg_flag(cs, reg_alu_const_cache + buffer_index * 4, va >> 8,
1895 pkt_flags);
1896 }
1897
1898 radeon_emit(cs, PKT3(PKT3_NOP, 0, 0) | pkt_flags);
1899 radeon_emit(cs, r600_context_bo_reloc(&rctx->b, &rctx->b.rings.gfx, rbuffer,
1900 RADEON_USAGE_READ, RADEON_PRIO_SHADER_BUFFER_RO));
1901
1902 radeon_emit(cs, PKT3(PKT3_SET_RESOURCE, 8, 0) | pkt_flags);
1903 radeon_emit(cs, (buffer_id_base + buffer_index) * 8);
1904 radeon_emit(cs, va); /* RESOURCEi_WORD0 */
1905 radeon_emit(cs, rbuffer->buf->size - cb->buffer_offset - 1); /* RESOURCEi_WORD1 */
1906 radeon_emit(cs, /* RESOURCEi_WORD2 */
1907 S_030008_ENDIAN_SWAP(gs_ring_buffer ? ENDIAN_NONE : r600_endian_swap(32)) |
1908 S_030008_STRIDE(gs_ring_buffer ? 4 : 16) |
1909 S_030008_BASE_ADDRESS_HI(va >> 32UL) |
1910 S_030008_DATA_FORMAT(FMT_32_32_32_32_FLOAT));
1911 radeon_emit(cs, /* RESOURCEi_WORD3 */
1912 S_03000C_UNCACHED(gs_ring_buffer ? 1 : 0) |
1913 S_03000C_DST_SEL_X(V_03000C_SQ_SEL_X) |
1914 S_03000C_DST_SEL_Y(V_03000C_SQ_SEL_Y) |
1915 S_03000C_DST_SEL_Z(V_03000C_SQ_SEL_Z) |
1916 S_03000C_DST_SEL_W(V_03000C_SQ_SEL_W));
1917 radeon_emit(cs, 0); /* RESOURCEi_WORD4 */
1918 radeon_emit(cs, 0); /* RESOURCEi_WORD5 */
1919 radeon_emit(cs, 0); /* RESOURCEi_WORD6 */
1920 radeon_emit(cs, /* RESOURCEi_WORD7 */
1921 S_03001C_TYPE(V_03001C_SQ_TEX_VTX_VALID_BUFFER));
1922
1923 radeon_emit(cs, PKT3(PKT3_NOP, 0, 0) | pkt_flags);
1924 radeon_emit(cs, r600_context_bo_reloc(&rctx->b, &rctx->b.rings.gfx, rbuffer,
1925 RADEON_USAGE_READ, RADEON_PRIO_SHADER_BUFFER_RO));
1926
1927 dirty_mask &= ~(1 << buffer_index);
1928 }
1929 state->dirty_mask = 0;
1930 }
1931
1932 static void evergreen_emit_vs_constant_buffers(struct r600_context *rctx, struct r600_atom *atom)
1933 {
1934 evergreen_emit_constant_buffers(rctx, &rctx->constbuf_state[PIPE_SHADER_VERTEX], 176,
1935 R_028180_ALU_CONST_BUFFER_SIZE_VS_0,
1936 R_028980_ALU_CONST_CACHE_VS_0,
1937 0 /* PKT3 flags */);
1938 }
1939
1940 static void evergreen_emit_gs_constant_buffers(struct r600_context *rctx, struct r600_atom *atom)
1941 {
1942 evergreen_emit_constant_buffers(rctx, &rctx->constbuf_state[PIPE_SHADER_GEOMETRY], 336,
1943 R_0281C0_ALU_CONST_BUFFER_SIZE_GS_0,
1944 R_0289C0_ALU_CONST_CACHE_GS_0,
1945 0 /* PKT3 flags */);
1946 }
1947
1948 static void evergreen_emit_ps_constant_buffers(struct r600_context *rctx, struct r600_atom *atom)
1949 {
1950 evergreen_emit_constant_buffers(rctx, &rctx->constbuf_state[PIPE_SHADER_FRAGMENT], 0,
1951 R_028140_ALU_CONST_BUFFER_SIZE_PS_0,
1952 R_028940_ALU_CONST_CACHE_PS_0,
1953 0 /* PKT3 flags */);
1954 }
1955
1956 static void evergreen_emit_cs_constant_buffers(struct r600_context *rctx, struct r600_atom *atom)
1957 {
1958 evergreen_emit_constant_buffers(rctx, &rctx->constbuf_state[PIPE_SHADER_COMPUTE], 816,
1959 R_028FC0_ALU_CONST_BUFFER_SIZE_LS_0,
1960 R_028F40_ALU_CONST_CACHE_LS_0,
1961 RADEON_CP_PACKET3_COMPUTE_MODE);
1962 }
1963
1964 static void evergreen_emit_sampler_views(struct r600_context *rctx,
1965 struct r600_samplerview_state *state,
1966 unsigned resource_id_base)
1967 {
1968 struct radeon_winsys_cs *cs = rctx->b.rings.gfx.cs;
1969 uint32_t dirty_mask = state->dirty_mask;
1970
1971 while (dirty_mask) {
1972 struct r600_pipe_sampler_view *rview;
1973 unsigned resource_index = u_bit_scan(&dirty_mask);
1974 unsigned reloc;
1975
1976 rview = state->views[resource_index];
1977 assert(rview);
1978
1979 radeon_emit(cs, PKT3(PKT3_SET_RESOURCE, 8, 0));
1980 radeon_emit(cs, (resource_id_base + resource_index) * 8);
1981 radeon_emit_array(cs, rview->tex_resource_words, 8);
1982
1983 reloc = r600_context_bo_reloc(&rctx->b, &rctx->b.rings.gfx, rview->tex_resource,
1984 RADEON_USAGE_READ,
1985 rview->tex_resource->b.b.nr_samples > 1 ?
1986 RADEON_PRIO_SHADER_TEXTURE_MSAA :
1987 RADEON_PRIO_SHADER_TEXTURE_RO);
1988 radeon_emit(cs, PKT3(PKT3_NOP, 0, 0));
1989 radeon_emit(cs, reloc);
1990
1991 if (!rview->skip_mip_address_reloc) {
1992 radeon_emit(cs, PKT3(PKT3_NOP, 0, 0));
1993 radeon_emit(cs, reloc);
1994 }
1995 }
1996 state->dirty_mask = 0;
1997 }
1998
1999 static void evergreen_emit_vs_sampler_views(struct r600_context *rctx, struct r600_atom *atom)
2000 {
2001 evergreen_emit_sampler_views(rctx, &rctx->samplers[PIPE_SHADER_VERTEX].views, 176 + R600_MAX_CONST_BUFFERS);
2002 }
2003
2004 static void evergreen_emit_gs_sampler_views(struct r600_context *rctx, struct r600_atom *atom)
2005 {
2006 evergreen_emit_sampler_views(rctx, &rctx->samplers[PIPE_SHADER_GEOMETRY].views, 336 + R600_MAX_CONST_BUFFERS);
2007 }
2008
2009 static void evergreen_emit_ps_sampler_views(struct r600_context *rctx, struct r600_atom *atom)
2010 {
2011 evergreen_emit_sampler_views(rctx, &rctx->samplers[PIPE_SHADER_FRAGMENT].views, R600_MAX_CONST_BUFFERS);
2012 }
2013
2014 static void evergreen_emit_sampler_states(struct r600_context *rctx,
2015 struct r600_textures_info *texinfo,
2016 unsigned resource_id_base,
2017 unsigned border_index_reg)
2018 {
2019 struct radeon_winsys_cs *cs = rctx->b.rings.gfx.cs;
2020 uint32_t dirty_mask = texinfo->states.dirty_mask;
2021
2022 while (dirty_mask) {
2023 struct r600_pipe_sampler_state *rstate;
2024 unsigned i = u_bit_scan(&dirty_mask);
2025
2026 rstate = texinfo->states.states[i];
2027 assert(rstate);
2028
2029 radeon_emit(cs, PKT3(PKT3_SET_SAMPLER, 3, 0));
2030 radeon_emit(cs, (resource_id_base + i) * 3);
2031 radeon_emit_array(cs, rstate->tex_sampler_words, 3);
2032
2033 if (rstate->border_color_use) {
2034 r600_write_config_reg_seq(cs, border_index_reg, 5);
2035 radeon_emit(cs, i);
2036 radeon_emit_array(cs, rstate->border_color.ui, 4);
2037 }
2038 }
2039 texinfo->states.dirty_mask = 0;
2040 }
2041
2042 static void evergreen_emit_vs_sampler_states(struct r600_context *rctx, struct r600_atom *atom)
2043 {
2044 evergreen_emit_sampler_states(rctx, &rctx->samplers[PIPE_SHADER_VERTEX], 18, R_00A414_TD_VS_SAMPLER0_BORDER_INDEX);
2045 }
2046
2047 static void evergreen_emit_gs_sampler_states(struct r600_context *rctx, struct r600_atom *atom)
2048 {
2049 evergreen_emit_sampler_states(rctx, &rctx->samplers[PIPE_SHADER_GEOMETRY], 36, R_00A428_TD_GS_SAMPLER0_BORDER_INDEX);
2050 }
2051
2052 static void evergreen_emit_ps_sampler_states(struct r600_context *rctx, struct r600_atom *atom)
2053 {
2054 evergreen_emit_sampler_states(rctx, &rctx->samplers[PIPE_SHADER_FRAGMENT], 0, R_00A400_TD_PS_SAMPLER0_BORDER_INDEX);
2055 }
2056
2057 static void evergreen_emit_sample_mask(struct r600_context *rctx, struct r600_atom *a)
2058 {
2059 struct r600_sample_mask *s = (struct r600_sample_mask*)a;
2060 uint8_t mask = s->sample_mask;
2061
2062 r600_write_context_reg(rctx->b.rings.gfx.cs, R_028C3C_PA_SC_AA_MASK,
2063 mask | (mask << 8) | (mask << 16) | (mask << 24));
2064 }
2065
2066 static void cayman_emit_sample_mask(struct r600_context *rctx, struct r600_atom *a)
2067 {
2068 struct r600_sample_mask *s = (struct r600_sample_mask*)a;
2069 struct radeon_winsys_cs *cs = rctx->b.rings.gfx.cs;
2070 uint16_t mask = s->sample_mask;
2071
2072 r600_write_context_reg_seq(cs, CM_R_028C38_PA_SC_AA_MASK_X0Y0_X1Y0, 2);
2073 radeon_emit(cs, mask | (mask << 16)); /* X0Y0_X1Y0 */
2074 radeon_emit(cs, mask | (mask << 16)); /* X0Y1_X1Y1 */
2075 }
2076
2077 static void evergreen_emit_vertex_fetch_shader(struct r600_context *rctx, struct r600_atom *a)
2078 {
2079 struct radeon_winsys_cs *cs = rctx->b.rings.gfx.cs;
2080 struct r600_cso_state *state = (struct r600_cso_state*)a;
2081 struct r600_fetch_shader *shader = (struct r600_fetch_shader*)state->cso;
2082
2083 r600_write_context_reg(cs, R_0288A4_SQ_PGM_START_FS,
2084 (shader->buffer->gpu_address + shader->offset) >> 8);
2085 radeon_emit(cs, PKT3(PKT3_NOP, 0, 0));
2086 radeon_emit(cs, r600_context_bo_reloc(&rctx->b, &rctx->b.rings.gfx, shader->buffer,
2087 RADEON_USAGE_READ, RADEON_PRIO_SHADER_DATA));
2088 }
2089
2090 static void evergreen_emit_shader_stages(struct r600_context *rctx, struct r600_atom *a)
2091 {
2092 struct radeon_winsys_cs *cs = rctx->b.rings.gfx.cs;
2093 struct r600_shader_stages_state *state = (struct r600_shader_stages_state*)a;
2094
2095 uint32_t v = 0, v2 = 0, primid = 0;
2096
2097 if (state->geom_enable) {
2098 uint32_t cut_val;
2099
2100 if (rctx->gs_shader->current->shader.gs_max_out_vertices <= 128)
2101 cut_val = V_028A40_GS_CUT_128;
2102 else if (rctx->gs_shader->current->shader.gs_max_out_vertices <= 256)
2103 cut_val = V_028A40_GS_CUT_256;
2104 else if (rctx->gs_shader->current->shader.gs_max_out_vertices <= 512)
2105 cut_val = V_028A40_GS_CUT_512;
2106 else
2107 cut_val = V_028A40_GS_CUT_1024;
2108 v = S_028B54_ES_EN(V_028B54_ES_STAGE_REAL) |
2109 S_028B54_GS_EN(1) |
2110 S_028B54_VS_EN(V_028B54_VS_STAGE_COPY_SHADER);
2111
2112 v2 = S_028A40_MODE(V_028A40_GS_SCENARIO_G) |
2113 S_028A40_CUT_MODE(cut_val);
2114
2115 if (rctx->gs_shader->current->shader.gs_prim_id_input)
2116 primid = 1;
2117 }
2118
2119 r600_write_context_reg(cs, R_028B54_VGT_SHADER_STAGES_EN, v);
2120 r600_write_context_reg(cs, R_028A40_VGT_GS_MODE, v2);
2121 r600_write_context_reg(cs, R_028A84_VGT_PRIMITIVEID_EN, primid);
2122 }
2123
2124 static void evergreen_emit_gs_rings(struct r600_context *rctx, struct r600_atom *a)
2125 {
2126 struct radeon_winsys_cs *cs = rctx->b.rings.gfx.cs;
2127 struct r600_gs_rings_state *state = (struct r600_gs_rings_state*)a;
2128 struct r600_resource *rbuffer;
2129
2130 r600_write_config_reg(cs, R_008040_WAIT_UNTIL, S_008040_WAIT_3D_IDLE(1));
2131 radeon_emit(cs, PKT3(PKT3_EVENT_WRITE, 0, 0));
2132 radeon_emit(cs, EVENT_TYPE(EVENT_TYPE_VGT_FLUSH));
2133
2134 if (state->enable) {
2135 rbuffer =(struct r600_resource*)state->esgs_ring.buffer;
2136 r600_write_config_reg(cs, R_008C40_SQ_ESGS_RING_BASE,
2137 rbuffer->gpu_address >> 8);
2138 radeon_emit(cs, PKT3(PKT3_NOP, 0, 0));
2139 radeon_emit(cs, r600_context_bo_reloc(&rctx->b, &rctx->b.rings.gfx, rbuffer,
2140 RADEON_USAGE_READWRITE,
2141 RADEON_PRIO_SHADER_RESOURCE_RW));
2142 r600_write_config_reg(cs, R_008C44_SQ_ESGS_RING_SIZE,
2143 state->esgs_ring.buffer_size >> 8);
2144
2145 rbuffer =(struct r600_resource*)state->gsvs_ring.buffer;
2146 r600_write_config_reg(cs, R_008C48_SQ_GSVS_RING_BASE,
2147 rbuffer->gpu_address >> 8);
2148 radeon_emit(cs, PKT3(PKT3_NOP, 0, 0));
2149 radeon_emit(cs, r600_context_bo_reloc(&rctx->b, &rctx->b.rings.gfx, rbuffer,
2150 RADEON_USAGE_READWRITE,
2151 RADEON_PRIO_SHADER_RESOURCE_RW));
2152 r600_write_config_reg(cs, R_008C4C_SQ_GSVS_RING_SIZE,
2153 state->gsvs_ring.buffer_size >> 8);
2154 } else {
2155 r600_write_config_reg(cs, R_008C44_SQ_ESGS_RING_SIZE, 0);
2156 r600_write_config_reg(cs, R_008C4C_SQ_GSVS_RING_SIZE, 0);
2157 }
2158
2159 r600_write_config_reg(cs, R_008040_WAIT_UNTIL, S_008040_WAIT_3D_IDLE(1));
2160 radeon_emit(cs, PKT3(PKT3_EVENT_WRITE, 0, 0));
2161 radeon_emit(cs, EVENT_TYPE(EVENT_TYPE_VGT_FLUSH));
2162 }
2163
2164 void cayman_init_common_regs(struct r600_command_buffer *cb,
2165 enum chip_class ctx_chip_class,
2166 enum radeon_family ctx_family,
2167 int ctx_drm_minor)
2168 {
2169 r600_store_config_reg_seq(cb, R_008C00_SQ_CONFIG, 2);
2170 r600_store_value(cb, S_008C00_EXPORT_SRC_C(1)); /* R_008C00_SQ_CONFIG */
2171 /* always set the temp clauses */
2172 r600_store_value(cb, S_008C04_NUM_CLAUSE_TEMP_GPRS(4)); /* R_008C04_SQ_GPR_RESOURCE_MGMT_1 */
2173
2174 r600_store_config_reg_seq(cb, R_008C10_SQ_GLOBAL_GPR_RESOURCE_MGMT_1, 2);
2175 r600_store_value(cb, 0); /* R_008C10_SQ_GLOBAL_GPR_RESOURCE_MGMT_1 */
2176 r600_store_value(cb, 0); /* R_008C14_SQ_GLOBAL_GPR_RESOURCE_MGMT_2 */
2177
2178 r600_store_config_reg(cb, R_008D8C_SQ_DYN_GPR_CNTL_PS_FLUSH_REQ, (1 << 8));
2179
2180 r600_store_context_reg_seq(cb, R_028350_SX_MISC, 2);
2181 r600_store_value(cb, 0);
2182 r600_store_value(cb, S_028354_SURFACE_SYNC_MASK(0xf));
2183
2184 r600_store_context_reg(cb, R_028800_DB_DEPTH_CONTROL, 0);
2185 }
2186
2187 static void cayman_init_atom_start_cs(struct r600_context *rctx)
2188 {
2189 struct r600_command_buffer *cb = &rctx->start_cs_cmd;
2190 int tmp, i;
2191
2192 r600_init_command_buffer(cb, 320);
2193
2194 /* This must be first. */
2195 r600_store_value(cb, PKT3(PKT3_CONTEXT_CONTROL, 1, 0));
2196 r600_store_value(cb, 0x80000000);
2197 r600_store_value(cb, 0x80000000);
2198
2199 /* We're setting config registers here. */
2200 r600_store_value(cb, PKT3(PKT3_EVENT_WRITE, 0, 0));
2201 r600_store_value(cb, EVENT_TYPE(EVENT_TYPE_PS_PARTIAL_FLUSH) | EVENT_INDEX(4));
2202
2203 cayman_init_common_regs(cb, rctx->b.chip_class,
2204 rctx->b.family, rctx->screen->b.info.drm_minor);
2205
2206 r600_store_config_reg(cb, R_009100_SPI_CONFIG_CNTL, 0);
2207 r600_store_config_reg(cb, R_00913C_SPI_CONFIG_CNTL_1, S_00913C_VTX_DONE_DELAY(4));
2208
2209 r600_store_context_reg_seq(cb, R_028900_SQ_ESGS_RING_ITEMSIZE, 6);
2210 r600_store_value(cb, 0); /* R_028900_SQ_ESGS_RING_ITEMSIZE */
2211 r600_store_value(cb, 0); /* R_028904_SQ_GSVS_RING_ITEMSIZE */
2212 r600_store_value(cb, 0); /* R_028908_SQ_ESTMP_RING_ITEMSIZE */
2213 r600_store_value(cb, 0); /* R_02890C_SQ_GSTMP_RING_ITEMSIZE */
2214 r600_store_value(cb, 0); /* R_028910_SQ_VSTMP_RING_ITEMSIZE */
2215 r600_store_value(cb, 0); /* R_028914_SQ_PSTMP_RING_ITEMSIZE */
2216
2217 r600_store_context_reg_seq(cb, R_02891C_SQ_GS_VERT_ITEMSIZE, 4);
2218 r600_store_value(cb, 0); /* R_02891C_SQ_GS_VERT_ITEMSIZE */
2219 r600_store_value(cb, 0); /* R_028920_SQ_GS_VERT_ITEMSIZE_1 */
2220 r600_store_value(cb, 0); /* R_028924_SQ_GS_VERT_ITEMSIZE_2 */
2221 r600_store_value(cb, 0); /* R_028928_SQ_GS_VERT_ITEMSIZE_3 */
2222
2223 r600_store_context_reg_seq(cb, R_028A10_VGT_OUTPUT_PATH_CNTL, 13);
2224 r600_store_value(cb, 0); /* R_028A10_VGT_OUTPUT_PATH_CNTL */
2225 r600_store_value(cb, 0); /* R_028A14_VGT_HOS_CNTL */
2226 r600_store_value(cb, 0); /* R_028A18_VGT_HOS_MAX_TESS_LEVEL */
2227 r600_store_value(cb, 0); /* R_028A1C_VGT_HOS_MIN_TESS_LEVEL */
2228 r600_store_value(cb, 0); /* R_028A20_VGT_HOS_REUSE_DEPTH */
2229 r600_store_value(cb, 0); /* R_028A24_VGT_GROUP_PRIM_TYPE */
2230 r600_store_value(cb, 0); /* R_028A28_VGT_GROUP_FIRST_DECR */
2231 r600_store_value(cb, 0); /* R_028A2C_VGT_GROUP_DECR */
2232 r600_store_value(cb, 0); /* R_028A30_VGT_GROUP_VECT_0_CNTL */
2233 r600_store_value(cb, 0); /* R_028A34_VGT_GROUP_VECT_1_CNTL */
2234 r600_store_value(cb, 0); /* R_028A38_VGT_GROUP_VECT_0_FMT_CNTL */
2235 r600_store_value(cb, 0); /* R_028A3C_VGT_GROUP_VECT_1_FMT_CNTL */
2236 r600_store_value(cb, 0); /* R_028A40_VGT_GS_MODE */
2237
2238 r600_store_context_reg(cb, R_028B98_VGT_STRMOUT_BUFFER_CONFIG, 0);
2239
2240 r600_store_context_reg_seq(cb, R_028AB4_VGT_REUSE_OFF, 2);
2241 r600_store_value(cb, 0); /* R_028AB4_VGT_REUSE_OFF */
2242 r600_store_value(cb, 0); /* R_028AB8_VGT_VTX_CNT_EN */
2243
2244 r600_store_config_reg(cb, R_008A14_PA_CL_ENHANCE, (3 << 1) | 1);
2245
2246 r600_store_context_reg_seq(cb, CM_R_028BD4_PA_SC_CENTROID_PRIORITY_0, 2);
2247 r600_store_value(cb, 0x76543210); /* CM_R_028BD4_PA_SC_CENTROID_PRIORITY_0 */
2248 r600_store_value(cb, 0xfedcba98); /* CM_R_028BD8_PA_SC_CENTROID_PRIORITY_1 */
2249
2250 r600_store_context_reg_seq(cb, CM_R_0288E8_SQ_LDS_ALLOC, 2);
2251 r600_store_value(cb, 0); /* CM_R_0288E8_SQ_LDS_ALLOC */
2252 r600_store_value(cb, 0); /* R_0288EC_SQ_LDS_ALLOC_PS */
2253
2254 r600_store_context_reg(cb, R_0288F0_SQ_VTX_SEMANTIC_CLEAR, ~0);
2255
2256 r600_store_context_reg_seq(cb, R_028400_VGT_MAX_VTX_INDX, 2);
2257 r600_store_value(cb, ~0); /* R_028400_VGT_MAX_VTX_INDX */
2258 r600_store_value(cb, 0); /* R_028404_VGT_MIN_VTX_INDX */
2259
2260 r600_store_ctl_const(cb, R_03CFF0_SQ_VTX_BASE_VTX_LOC, 0);
2261
2262 r600_store_context_reg(cb, R_028028_DB_STENCIL_CLEAR, 0);
2263
2264 r600_store_context_reg(cb, R_0286DC_SPI_FOG_CNTL, 0);
2265
2266 r600_store_context_reg_seq(cb, R_028AC0_DB_SRESULTS_COMPARE_STATE0, 3);
2267 r600_store_value(cb, 0); /* R_028AC0_DB_SRESULTS_COMPARE_STATE0 */
2268 r600_store_value(cb, 0); /* R_028AC4_DB_SRESULTS_COMPARE_STATE1 */
2269 r600_store_value(cb, 0); /* R_028AC8_DB_PRELOAD_CONTROL */
2270
2271 r600_store_context_reg(cb, R_028200_PA_SC_WINDOW_OFFSET, 0);
2272 r600_store_context_reg(cb, R_02820C_PA_SC_CLIPRECT_RULE, 0xFFFF);
2273
2274 r600_store_context_reg_seq(cb, R_0282D0_PA_SC_VPORT_ZMIN_0, 2 * 16);
2275 for (tmp = 0; tmp < 16; tmp++) {
2276 r600_store_value(cb, 0); /* R_0282D0_PA_SC_VPORT_ZMIN_0 */
2277 r600_store_value(cb, 0x3F800000); /* R_0282D4_PA_SC_VPORT_ZMAX_0 */
2278 }
2279
2280 r600_store_context_reg(cb, R_028230_PA_SC_EDGERULE, 0xAAAAAAAA);
2281 r600_store_context_reg(cb, R_028820_PA_CL_NANINF_CNTL, 0);
2282
2283 r600_store_context_reg_seq(cb, CM_R_028BE8_PA_CL_GB_VERT_CLIP_ADJ, 4);
2284 r600_store_value(cb, 0x3F800000); /* CM_R_028BE8_PA_CL_GB_VERT_CLIP_ADJ */
2285 r600_store_value(cb, 0x3F800000); /* CM_R_028BEC_PA_CL_GB_VERT_DISC_ADJ */
2286 r600_store_value(cb, 0x3F800000); /* CM_R_028BF0_PA_CL_GB_HORZ_CLIP_ADJ */
2287 r600_store_value(cb, 0x3F800000); /* CM_R_028BF4_PA_CL_GB_HORZ_DISC_ADJ */
2288
2289 r600_store_context_reg_seq(cb, R_028240_PA_SC_GENERIC_SCISSOR_TL, 2);
2290 r600_store_value(cb, 0); /* R_028240_PA_SC_GENERIC_SCISSOR_TL */
2291 r600_store_value(cb, S_028244_BR_X(16384) | S_028244_BR_Y(16384)); /* R_028244_PA_SC_GENERIC_SCISSOR_BR */
2292
2293 r600_store_context_reg_seq(cb, R_028030_PA_SC_SCREEN_SCISSOR_TL, 2);
2294 r600_store_value(cb, 0); /* R_028030_PA_SC_SCREEN_SCISSOR_TL */
2295 r600_store_value(cb, S_028034_BR_X(16384) | S_028034_BR_Y(16384)); /* R_028034_PA_SC_SCREEN_SCISSOR_BR */
2296
2297 r600_store_context_reg(cb, R_028848_SQ_PGM_RESOURCES_2_PS, S_028848_SINGLE_ROUND(V_SQ_ROUND_NEAREST_EVEN));
2298 r600_store_context_reg(cb, R_028864_SQ_PGM_RESOURCES_2_VS, S_028864_SINGLE_ROUND(V_SQ_ROUND_NEAREST_EVEN));
2299 r600_store_context_reg(cb, R_0288A8_SQ_PGM_RESOURCES_FS, 0);
2300
2301 /* to avoid GPU doing any preloading of constant from random address */
2302 r600_store_context_reg_seq(cb, R_028140_ALU_CONST_BUFFER_SIZE_PS_0, 16);
2303 for (i = 0; i < 16; i++)
2304 r600_store_value(cb, 0);
2305
2306 r600_store_context_reg_seq(cb, R_028180_ALU_CONST_BUFFER_SIZE_VS_0, 16);
2307 for (i = 0; i < 16; i++)
2308 r600_store_value(cb, 0);
2309
2310 r600_store_context_reg_seq(cb, R_0281C0_ALU_CONST_BUFFER_SIZE_GS_0, 16);
2311 for (i = 0; i < 16; i++)
2312 r600_store_value(cb, 0);
2313
2314 r600_store_context_reg_seq(cb, R_028FC0_ALU_CONST_BUFFER_SIZE_LS_0, 16);
2315 for (i = 0; i < 16; i++)
2316 r600_store_value(cb, 0);
2317
2318 r600_store_context_reg_seq(cb, R_028F80_ALU_CONST_BUFFER_SIZE_HS_0, 16);
2319 for (i = 0; i < 16; i++)
2320 r600_store_value(cb, 0);
2321
2322 if (rctx->screen->b.has_streamout) {
2323 r600_store_context_reg(cb, R_028B28_VGT_STRMOUT_DRAW_OPAQUE_OFFSET, 0);
2324 }
2325
2326 r600_store_context_reg(cb, R_028010_DB_RENDER_OVERRIDE2, 0);
2327 r600_store_context_reg(cb, R_028234_PA_SU_HARDWARE_SCREEN_OFFSET, 0);
2328 r600_store_context_reg(cb, R_0286C8_SPI_THREAD_GROUPING, 0);
2329 r600_store_context_reg_seq(cb, R_0286E4_SPI_PS_IN_CONTROL_2, 2);
2330 r600_store_value(cb, 0); /* R_0286E4_SPI_PS_IN_CONTROL_2 */
2331 r600_store_value(cb, 0); /* R_0286E8_SPI_COMPUTE_INPUT_CNTL */
2332 r600_store_context_reg(cb, R_028B54_VGT_SHADER_STAGES_EN, 0);
2333
2334 eg_store_loop_const(cb, R_03A200_SQ_LOOP_CONST_0, 0x01000FFF);
2335 eg_store_loop_const(cb, R_03A200_SQ_LOOP_CONST_0 + (32 * 4), 0x01000FFF);
2336 eg_store_loop_const(cb, R_03A200_SQ_LOOP_CONST_0 + (64 * 4), 0x01000FFF);
2337 }
2338
2339 void evergreen_init_common_regs(struct r600_command_buffer *cb,
2340 enum chip_class ctx_chip_class,
2341 enum radeon_family ctx_family,
2342 int ctx_drm_minor)
2343 {
2344 int ps_prio;
2345 int vs_prio;
2346 int gs_prio;
2347 int es_prio;
2348
2349 int hs_prio;
2350 int cs_prio;
2351 int ls_prio;
2352
2353 int num_ps_gprs;
2354 int num_vs_gprs;
2355 int num_gs_gprs;
2356 int num_es_gprs;
2357 int num_hs_gprs;
2358 int num_ls_gprs;
2359 int num_temp_gprs;
2360
2361 unsigned tmp;
2362
2363 ps_prio = 0;
2364 vs_prio = 1;
2365 gs_prio = 2;
2366 es_prio = 3;
2367 hs_prio = 0;
2368 ls_prio = 0;
2369 cs_prio = 0;
2370
2371 num_ps_gprs = 93;
2372 num_vs_gprs = 46;
2373 num_temp_gprs = 4;
2374 num_gs_gprs = 31;
2375 num_es_gprs = 31;
2376 num_hs_gprs = 23;
2377 num_ls_gprs = 23;
2378
2379 tmp = 0;
2380 switch (ctx_family) {
2381 case CHIP_CEDAR:
2382 case CHIP_PALM:
2383 case CHIP_SUMO:
2384 case CHIP_SUMO2:
2385 case CHIP_CAICOS:
2386 break;
2387 default:
2388 tmp |= S_008C00_VC_ENABLE(1);
2389 break;
2390 }
2391 tmp |= S_008C00_EXPORT_SRC_C(1);
2392 tmp |= S_008C00_CS_PRIO(cs_prio);
2393 tmp |= S_008C00_LS_PRIO(ls_prio);
2394 tmp |= S_008C00_HS_PRIO(hs_prio);
2395 tmp |= S_008C00_PS_PRIO(ps_prio);
2396 tmp |= S_008C00_VS_PRIO(vs_prio);
2397 tmp |= S_008C00_GS_PRIO(gs_prio);
2398 tmp |= S_008C00_ES_PRIO(es_prio);
2399
2400 /* enable dynamic GPR resource management */
2401 if (ctx_drm_minor >= 7) {
2402 r600_store_config_reg_seq(cb, R_008C00_SQ_CONFIG, 2);
2403 r600_store_value(cb, tmp); /* R_008C00_SQ_CONFIG */
2404 /* always set temp clauses */
2405 r600_store_value(cb, S_008C04_NUM_CLAUSE_TEMP_GPRS(num_temp_gprs)); /* R_008C04_SQ_GPR_RESOURCE_MGMT_1 */
2406 r600_store_config_reg_seq(cb, R_008C10_SQ_GLOBAL_GPR_RESOURCE_MGMT_1, 2);
2407 r600_store_value(cb, 0); /* R_008C10_SQ_GLOBAL_GPR_RESOURCE_MGMT_1 */
2408 r600_store_value(cb, 0); /* R_008C14_SQ_GLOBAL_GPR_RESOURCE_MGMT_2 */
2409 r600_store_config_reg(cb, R_008D8C_SQ_DYN_GPR_CNTL_PS_FLUSH_REQ, (1 << 8));
2410 r600_store_context_reg(cb, R_028838_SQ_DYN_GPR_RESOURCE_LIMIT_1,
2411 S_028838_PS_GPRS(0x1e) |
2412 S_028838_VS_GPRS(0x1e) |
2413 S_028838_GS_GPRS(0x1e) |
2414 S_028838_ES_GPRS(0x1e) |
2415 S_028838_HS_GPRS(0x1e) |
2416 S_028838_LS_GPRS(0x1e)); /* workaround for hw issues with dyn gpr - must set all limits to 240 instead of 0, 0x1e == 240 / 8*/
2417 } else {
2418 r600_store_config_reg_seq(cb, R_008C00_SQ_CONFIG, 4);
2419 r600_store_value(cb, tmp); /* R_008C00_SQ_CONFIG */
2420
2421 tmp = S_008C04_NUM_PS_GPRS(num_ps_gprs);
2422 tmp |= S_008C04_NUM_VS_GPRS(num_vs_gprs);
2423 tmp |= S_008C04_NUM_CLAUSE_TEMP_GPRS(num_temp_gprs);
2424 r600_store_value(cb, tmp); /* R_008C04_SQ_GPR_RESOURCE_MGMT_1 */
2425
2426 tmp = S_008C08_NUM_GS_GPRS(num_gs_gprs);
2427 tmp |= S_008C08_NUM_ES_GPRS(num_es_gprs);
2428 r600_store_value(cb, tmp); /* R_008C08_SQ_GPR_RESOURCE_MGMT_2 */
2429
2430 tmp = S_008C0C_NUM_HS_GPRS(num_hs_gprs);
2431 tmp |= S_008C0C_NUM_HS_GPRS(num_ls_gprs);
2432 r600_store_value(cb, tmp); /* R_008C0C_SQ_GPR_RESOURCE_MGMT_3 */
2433 }
2434
2435 r600_store_context_reg(cb, R_028A4C_PA_SC_MODE_CNTL_1, 0);
2436
2437 /* The cs checker requires this register to be set. */
2438 r600_store_context_reg(cb, R_028800_DB_DEPTH_CONTROL, 0);
2439
2440 r600_store_context_reg_seq(cb, R_028350_SX_MISC, 2);
2441 r600_store_value(cb, 0);
2442 r600_store_value(cb, S_028354_SURFACE_SYNC_MASK(0xf));
2443
2444 return;
2445 }
2446
2447 void evergreen_init_atom_start_cs(struct r600_context *rctx)
2448 {
2449 struct r600_command_buffer *cb = &rctx->start_cs_cmd;
2450 int num_ps_threads;
2451 int num_vs_threads;
2452 int num_gs_threads;
2453 int num_es_threads;
2454 int num_hs_threads;
2455 int num_ls_threads;
2456
2457 int num_ps_stack_entries;
2458 int num_vs_stack_entries;
2459 int num_gs_stack_entries;
2460 int num_es_stack_entries;
2461 int num_hs_stack_entries;
2462 int num_ls_stack_entries;
2463 enum radeon_family family;
2464 unsigned tmp, i;
2465
2466 if (rctx->b.chip_class == CAYMAN) {
2467 cayman_init_atom_start_cs(rctx);
2468 return;
2469 }
2470
2471 r600_init_command_buffer(cb, 320);
2472
2473 /* This must be first. */
2474 r600_store_value(cb, PKT3(PKT3_CONTEXT_CONTROL, 1, 0));
2475 r600_store_value(cb, 0x80000000);
2476 r600_store_value(cb, 0x80000000);
2477
2478 /* We're setting config registers here. */
2479 r600_store_value(cb, PKT3(PKT3_EVENT_WRITE, 0, 0));
2480 r600_store_value(cb, EVENT_TYPE(EVENT_TYPE_PS_PARTIAL_FLUSH) | EVENT_INDEX(4));
2481
2482 evergreen_init_common_regs(cb, rctx->b.chip_class,
2483 rctx->b.family, rctx->screen->b.info.drm_minor);
2484
2485 family = rctx->b.family;
2486 switch (family) {
2487 case CHIP_CEDAR:
2488 default:
2489 num_ps_threads = 96;
2490 num_vs_threads = 16;
2491 num_gs_threads = 16;
2492 num_es_threads = 16;
2493 num_hs_threads = 16;
2494 num_ls_threads = 16;
2495 num_ps_stack_entries = 42;
2496 num_vs_stack_entries = 42;
2497 num_gs_stack_entries = 42;
2498 num_es_stack_entries = 42;
2499 num_hs_stack_entries = 42;
2500 num_ls_stack_entries = 42;
2501 break;
2502 case CHIP_REDWOOD:
2503 num_ps_threads = 128;
2504 num_vs_threads = 20;
2505 num_gs_threads = 20;
2506 num_es_threads = 20;
2507 num_hs_threads = 20;
2508 num_ls_threads = 20;
2509 num_ps_stack_entries = 42;
2510 num_vs_stack_entries = 42;
2511 num_gs_stack_entries = 42;
2512 num_es_stack_entries = 42;
2513 num_hs_stack_entries = 42;
2514 num_ls_stack_entries = 42;
2515 break;
2516 case CHIP_JUNIPER:
2517 num_ps_threads = 128;
2518 num_vs_threads = 20;
2519 num_gs_threads = 20;
2520 num_es_threads = 20;
2521 num_hs_threads = 20;
2522 num_ls_threads = 20;
2523 num_ps_stack_entries = 85;
2524 num_vs_stack_entries = 85;
2525 num_gs_stack_entries = 85;
2526 num_es_stack_entries = 85;
2527 num_hs_stack_entries = 85;
2528 num_ls_stack_entries = 85;
2529 break;
2530 case CHIP_CYPRESS:
2531 case CHIP_HEMLOCK:
2532 num_ps_threads = 128;
2533 num_vs_threads = 20;
2534 num_gs_threads = 20;
2535 num_es_threads = 20;
2536 num_hs_threads = 20;
2537 num_ls_threads = 20;
2538 num_ps_stack_entries = 85;
2539 num_vs_stack_entries = 85;
2540 num_gs_stack_entries = 85;
2541 num_es_stack_entries = 85;
2542 num_hs_stack_entries = 85;
2543 num_ls_stack_entries = 85;
2544 break;
2545 case CHIP_PALM:
2546 num_ps_threads = 96;
2547 num_vs_threads = 16;
2548 num_gs_threads = 16;
2549 num_es_threads = 16;
2550 num_hs_threads = 16;
2551 num_ls_threads = 16;
2552 num_ps_stack_entries = 42;
2553 num_vs_stack_entries = 42;
2554 num_gs_stack_entries = 42;
2555 num_es_stack_entries = 42;
2556 num_hs_stack_entries = 42;
2557 num_ls_stack_entries = 42;
2558 break;
2559 case CHIP_SUMO:
2560 num_ps_threads = 96;
2561 num_vs_threads = 25;
2562 num_gs_threads = 25;
2563 num_es_threads = 25;
2564 num_hs_threads = 25;
2565 num_ls_threads = 25;
2566 num_ps_stack_entries = 42;
2567 num_vs_stack_entries = 42;
2568 num_gs_stack_entries = 42;
2569 num_es_stack_entries = 42;
2570 num_hs_stack_entries = 42;
2571 num_ls_stack_entries = 42;
2572 break;
2573 case CHIP_SUMO2:
2574 num_ps_threads = 96;
2575 num_vs_threads = 25;
2576 num_gs_threads = 25;
2577 num_es_threads = 25;
2578 num_hs_threads = 25;
2579 num_ls_threads = 25;
2580 num_ps_stack_entries = 85;
2581 num_vs_stack_entries = 85;
2582 num_gs_stack_entries = 85;
2583 num_es_stack_entries = 85;
2584 num_hs_stack_entries = 85;
2585 num_ls_stack_entries = 85;
2586 break;
2587 case CHIP_BARTS:
2588 num_ps_threads = 128;
2589 num_vs_threads = 20;
2590 num_gs_threads = 20;
2591 num_es_threads = 20;
2592 num_hs_threads = 20;
2593 num_ls_threads = 20;
2594 num_ps_stack_entries = 85;
2595 num_vs_stack_entries = 85;
2596 num_gs_stack_entries = 85;
2597 num_es_stack_entries = 85;
2598 num_hs_stack_entries = 85;
2599 num_ls_stack_entries = 85;
2600 break;
2601 case CHIP_TURKS:
2602 num_ps_threads = 128;
2603 num_vs_threads = 20;
2604 num_gs_threads = 20;
2605 num_es_threads = 20;
2606 num_hs_threads = 20;
2607 num_ls_threads = 20;
2608 num_ps_stack_entries = 42;
2609 num_vs_stack_entries = 42;
2610 num_gs_stack_entries = 42;
2611 num_es_stack_entries = 42;
2612 num_hs_stack_entries = 42;
2613 num_ls_stack_entries = 42;
2614 break;
2615 case CHIP_CAICOS:
2616 num_ps_threads = 128;
2617 num_vs_threads = 10;
2618 num_gs_threads = 10;
2619 num_es_threads = 10;
2620 num_hs_threads = 10;
2621 num_ls_threads = 10;
2622 num_ps_stack_entries = 42;
2623 num_vs_stack_entries = 42;
2624 num_gs_stack_entries = 42;
2625 num_es_stack_entries = 42;
2626 num_hs_stack_entries = 42;
2627 num_ls_stack_entries = 42;
2628 break;
2629 }
2630
2631 tmp = S_008C18_NUM_PS_THREADS(num_ps_threads);
2632 tmp |= S_008C18_NUM_VS_THREADS(num_vs_threads);
2633 tmp |= S_008C18_NUM_GS_THREADS(num_gs_threads);
2634 tmp |= S_008C18_NUM_ES_THREADS(num_es_threads);
2635
2636 r600_store_config_reg_seq(cb, R_008C18_SQ_THREAD_RESOURCE_MGMT_1, 5);
2637 r600_store_value(cb, tmp); /* R_008C18_SQ_THREAD_RESOURCE_MGMT_1 */
2638
2639 tmp = S_008C1C_NUM_HS_THREADS(num_hs_threads);
2640 tmp |= S_008C1C_NUM_LS_THREADS(num_ls_threads);
2641 r600_store_value(cb, tmp); /* R_008C1C_SQ_THREAD_RESOURCE_MGMT_2 */
2642
2643 tmp = S_008C20_NUM_PS_STACK_ENTRIES(num_ps_stack_entries);
2644 tmp |= S_008C20_NUM_VS_STACK_ENTRIES(num_vs_stack_entries);
2645 r600_store_value(cb, tmp); /* R_008C20_SQ_STACK_RESOURCE_MGMT_1 */
2646
2647 tmp = S_008C24_NUM_GS_STACK_ENTRIES(num_gs_stack_entries);
2648 tmp |= S_008C24_NUM_ES_STACK_ENTRIES(num_es_stack_entries);
2649 r600_store_value(cb, tmp); /* R_008C24_SQ_STACK_RESOURCE_MGMT_2 */
2650
2651 tmp = S_008C28_NUM_HS_STACK_ENTRIES(num_hs_stack_entries);
2652 tmp |= S_008C28_NUM_LS_STACK_ENTRIES(num_ls_stack_entries);
2653 r600_store_value(cb, tmp); /* R_008C28_SQ_STACK_RESOURCE_MGMT_3 */
2654
2655 r600_store_config_reg(cb, R_008E2C_SQ_LDS_RESOURCE_MGMT,
2656 S_008E2C_NUM_PS_LDS(0x1000) | S_008E2C_NUM_LS_LDS(0x1000));
2657
2658 r600_store_config_reg(cb, R_009100_SPI_CONFIG_CNTL, 0);
2659 r600_store_config_reg(cb, R_00913C_SPI_CONFIG_CNTL_1, S_00913C_VTX_DONE_DELAY(4));
2660
2661 r600_store_context_reg_seq(cb, R_028900_SQ_ESGS_RING_ITEMSIZE, 6);
2662 r600_store_value(cb, 0); /* R_028900_SQ_ESGS_RING_ITEMSIZE */
2663 r600_store_value(cb, 0); /* R_028904_SQ_GSVS_RING_ITEMSIZE */
2664 r600_store_value(cb, 0); /* R_028908_SQ_ESTMP_RING_ITEMSIZE */
2665 r600_store_value(cb, 0); /* R_02890C_SQ_GSTMP_RING_ITEMSIZE */
2666 r600_store_value(cb, 0); /* R_028910_SQ_VSTMP_RING_ITEMSIZE */
2667 r600_store_value(cb, 0); /* R_028914_SQ_PSTMP_RING_ITEMSIZE */
2668
2669 r600_store_context_reg_seq(cb, R_02891C_SQ_GS_VERT_ITEMSIZE, 4);
2670 r600_store_value(cb, 0); /* R_02891C_SQ_GS_VERT_ITEMSIZE */
2671 r600_store_value(cb, 0); /* R_028920_SQ_GS_VERT_ITEMSIZE_1 */
2672 r600_store_value(cb, 0); /* R_028924_SQ_GS_VERT_ITEMSIZE_2 */
2673 r600_store_value(cb, 0); /* R_028928_SQ_GS_VERT_ITEMSIZE_3 */
2674
2675 r600_store_context_reg_seq(cb, R_028A10_VGT_OUTPUT_PATH_CNTL, 13);
2676 r600_store_value(cb, 0); /* R_028A10_VGT_OUTPUT_PATH_CNTL */
2677 r600_store_value(cb, 0); /* R_028A14_VGT_HOS_CNTL */
2678 r600_store_value(cb, 0); /* R_028A18_VGT_HOS_MAX_TESS_LEVEL */
2679 r600_store_value(cb, 0); /* R_028A1C_VGT_HOS_MIN_TESS_LEVEL */
2680 r600_store_value(cb, 0); /* R_028A20_VGT_HOS_REUSE_DEPTH */
2681 r600_store_value(cb, 0); /* R_028A24_VGT_GROUP_PRIM_TYPE */
2682 r600_store_value(cb, 0); /* R_028A28_VGT_GROUP_FIRST_DECR */
2683 r600_store_value(cb, 0); /* R_028A2C_VGT_GROUP_DECR */
2684 r600_store_value(cb, 0); /* R_028A30_VGT_GROUP_VECT_0_CNTL */
2685 r600_store_value(cb, 0); /* R_028A34_VGT_GROUP_VECT_1_CNTL */
2686 r600_store_value(cb, 0); /* R_028A38_VGT_GROUP_VECT_0_FMT_CNTL */
2687 r600_store_value(cb, 0); /* R_028A3C_VGT_GROUP_VECT_1_FMT_CNTL */
2688 r600_store_value(cb, 0); /* R_028A40_VGT_GS_MODE */
2689
2690 r600_store_context_reg_seq(cb, R_028AB4_VGT_REUSE_OFF, 2);
2691 r600_store_value(cb, 0); /* R_028AB4_VGT_REUSE_OFF */
2692 r600_store_value(cb, 0); /* R_028AB8_VGT_VTX_CNT_EN */
2693
2694 r600_store_config_reg(cb, R_008A14_PA_CL_ENHANCE, (3 << 1) | 1);
2695
2696 r600_store_context_reg(cb, R_0288F0_SQ_VTX_SEMANTIC_CLEAR, ~0);
2697
2698 r600_store_context_reg_seq(cb, R_028400_VGT_MAX_VTX_INDX, 2);
2699 r600_store_value(cb, ~0); /* R_028400_VGT_MAX_VTX_INDX */
2700 r600_store_value(cb, 0); /* R_028404_VGT_MIN_VTX_INDX */
2701
2702 r600_store_ctl_const(cb, R_03CFF0_SQ_VTX_BASE_VTX_LOC, 0);
2703
2704 r600_store_context_reg(cb, R_028028_DB_STENCIL_CLEAR, 0);
2705
2706 r600_store_context_reg(cb, R_028200_PA_SC_WINDOW_OFFSET, 0);
2707 r600_store_context_reg(cb, R_02820C_PA_SC_CLIPRECT_RULE, 0xFFFF);
2708 r600_store_context_reg(cb, R_028230_PA_SC_EDGERULE, 0xAAAAAAAA);
2709
2710 r600_store_context_reg_seq(cb, R_0282D0_PA_SC_VPORT_ZMIN_0, 2 * 16);
2711 for (tmp = 0; tmp < 16; tmp++) {
2712 r600_store_value(cb, 0); /* R_0282D0_PA_SC_VPORT_ZMIN_0 */
2713 r600_store_value(cb, 0x3F800000); /* R_0282D4_PA_SC_VPORT_ZMAX_0 */
2714 }
2715
2716 r600_store_context_reg(cb, R_0286DC_SPI_FOG_CNTL, 0);
2717 r600_store_context_reg(cb, R_028820_PA_CL_NANINF_CNTL, 0);
2718
2719 r600_store_context_reg_seq(cb, R_028AC0_DB_SRESULTS_COMPARE_STATE0, 3);
2720 r600_store_value(cb, 0); /* R_028AC0_DB_SRESULTS_COMPARE_STATE0 */
2721 r600_store_value(cb, 0); /* R_028AC4_DB_SRESULTS_COMPARE_STATE1 */
2722 r600_store_value(cb, 0); /* R_028AC8_DB_PRELOAD_CONTROL */
2723
2724 r600_store_context_reg_seq(cb, R_028C0C_PA_CL_GB_VERT_CLIP_ADJ, 4);
2725 r600_store_value(cb, 0x3F800000); /* R_028C0C_PA_CL_GB_VERT_CLIP_ADJ */
2726 r600_store_value(cb, 0x3F800000); /* R_028C10_PA_CL_GB_VERT_DISC_ADJ */
2727 r600_store_value(cb, 0x3F800000); /* R_028C14_PA_CL_GB_HORZ_CLIP_ADJ */
2728 r600_store_value(cb, 0x3F800000); /* R_028C18_PA_CL_GB_HORZ_DISC_ADJ */
2729
2730 r600_store_context_reg_seq(cb, R_028240_PA_SC_GENERIC_SCISSOR_TL, 2);
2731 r600_store_value(cb, 0); /* R_028240_PA_SC_GENERIC_SCISSOR_TL */
2732 r600_store_value(cb, S_028244_BR_X(16384) | S_028244_BR_Y(16384)); /* R_028244_PA_SC_GENERIC_SCISSOR_BR */
2733
2734 r600_store_context_reg_seq(cb, R_028030_PA_SC_SCREEN_SCISSOR_TL, 2);
2735 r600_store_value(cb, 0); /* R_028030_PA_SC_SCREEN_SCISSOR_TL */
2736 r600_store_value(cb, S_028034_BR_X(16384) | S_028034_BR_Y(16384)); /* R_028034_PA_SC_SCREEN_SCISSOR_BR */
2737
2738 r600_store_context_reg(cb, R_028848_SQ_PGM_RESOURCES_2_PS, S_028848_SINGLE_ROUND(V_SQ_ROUND_NEAREST_EVEN));
2739 r600_store_context_reg(cb, R_028864_SQ_PGM_RESOURCES_2_VS, S_028864_SINGLE_ROUND(V_SQ_ROUND_NEAREST_EVEN));
2740 r600_store_context_reg(cb, R_0288A8_SQ_PGM_RESOURCES_FS, 0);
2741
2742 /* to avoid GPU doing any preloading of constant from random address */
2743 r600_store_context_reg_seq(cb, R_028140_ALU_CONST_BUFFER_SIZE_PS_0, 16);
2744 for (i = 0; i < 16; i++)
2745 r600_store_value(cb, 0);
2746
2747 r600_store_context_reg_seq(cb, R_028180_ALU_CONST_BUFFER_SIZE_VS_0, 16);
2748 for (i = 0; i < 16; i++)
2749 r600_store_value(cb, 0);
2750
2751 r600_store_context_reg_seq(cb, R_0281C0_ALU_CONST_BUFFER_SIZE_GS_0, 16);
2752 for (i = 0; i < 16; i++)
2753 r600_store_value(cb, 0);
2754
2755 r600_store_context_reg_seq(cb, R_028FC0_ALU_CONST_BUFFER_SIZE_LS_0, 16);
2756 for (i = 0; i < 16; i++)
2757 r600_store_value(cb, 0);
2758
2759 r600_store_context_reg_seq(cb, R_028F80_ALU_CONST_BUFFER_SIZE_HS_0, 16);
2760 for (i = 0; i < 16; i++)
2761 r600_store_value(cb, 0);
2762
2763 r600_store_context_reg(cb, R_028B98_VGT_STRMOUT_BUFFER_CONFIG, 0);
2764
2765 if (rctx->screen->b.has_streamout) {
2766 r600_store_context_reg(cb, R_028B28_VGT_STRMOUT_DRAW_OPAQUE_OFFSET, 0);
2767 }
2768
2769 r600_store_context_reg(cb, R_028010_DB_RENDER_OVERRIDE2, 0);
2770 r600_store_context_reg(cb, R_028234_PA_SU_HARDWARE_SCREEN_OFFSET, 0);
2771 r600_store_context_reg(cb, R_0286C8_SPI_THREAD_GROUPING, 0);
2772 r600_store_context_reg_seq(cb, R_0286E4_SPI_PS_IN_CONTROL_2, 2);
2773 r600_store_value(cb, 0); /* R_0286E4_SPI_PS_IN_CONTROL_2 */
2774 r600_store_value(cb, 0); /* R_0286E8_SPI_COMPUTE_INPUT_CNTL */
2775 r600_store_context_reg(cb, R_0288EC_SQ_LDS_ALLOC_PS, 0);
2776 r600_store_context_reg(cb, R_028B54_VGT_SHADER_STAGES_EN, 0);
2777
2778 eg_store_loop_const(cb, R_03A200_SQ_LOOP_CONST_0, 0x01000FFF);
2779 eg_store_loop_const(cb, R_03A200_SQ_LOOP_CONST_0 + (32 * 4), 0x01000FFF);
2780 eg_store_loop_const(cb, R_03A200_SQ_LOOP_CONST_0 + (64 * 4), 0x01000FFF);
2781 }
2782
2783 void evergreen_update_ps_state(struct pipe_context *ctx, struct r600_pipe_shader *shader)
2784 {
2785 struct r600_context *rctx = (struct r600_context *)ctx;
2786 struct r600_command_buffer *cb = &shader->command_buffer;
2787 struct r600_shader *rshader = &shader->shader;
2788 unsigned i, exports_ps, num_cout, spi_ps_in_control_0, spi_input_z, spi_ps_in_control_1, db_shader_control = 0;
2789 int pos_index = -1, face_index = -1;
2790 int ninterp = 0;
2791 boolean have_linear = FALSE, have_centroid = FALSE, have_perspective = FALSE;
2792 unsigned spi_baryc_cntl, sid, tmp, num = 0;
2793 unsigned z_export = 0, stencil_export = 0;
2794 unsigned sprite_coord_enable = rctx->rasterizer ? rctx->rasterizer->sprite_coord_enable : 0;
2795 uint32_t spi_ps_input_cntl[32];
2796
2797 if (!cb->buf) {
2798 r600_init_command_buffer(cb, 64);
2799 } else {
2800 cb->num_dw = 0;
2801 }
2802
2803 for (i = 0; i < rshader->ninput; i++) {
2804 /* evergreen NUM_INTERP only contains values interpolated into the LDS,
2805 POSITION goes via GPRs from the SC so isn't counted */
2806 if (rshader->input[i].name == TGSI_SEMANTIC_POSITION)
2807 pos_index = i;
2808 else if (rshader->input[i].name == TGSI_SEMANTIC_FACE) {
2809 if (face_index == -1)
2810 face_index = i;
2811 }
2812 else if (rshader->input[i].name == TGSI_SEMANTIC_SAMPLEMASK) {
2813 if (face_index == -1)
2814 face_index = i; /* lives in same register, same enable bit */
2815 }
2816 else {
2817 ninterp++;
2818 if (rshader->input[i].interpolate == TGSI_INTERPOLATE_LINEAR)
2819 have_linear = TRUE;
2820 if (rshader->input[i].interpolate == TGSI_INTERPOLATE_PERSPECTIVE)
2821 have_perspective = TRUE;
2822 if (rshader->input[i].centroid)
2823 have_centroid = TRUE;
2824 }
2825
2826 sid = rshader->input[i].spi_sid;
2827
2828 if (sid) {
2829 tmp = S_028644_SEMANTIC(sid);
2830
2831 if (rshader->input[i].name == TGSI_SEMANTIC_POSITION ||
2832 rshader->input[i].interpolate == TGSI_INTERPOLATE_CONSTANT ||
2833 (rshader->input[i].interpolate == TGSI_INTERPOLATE_COLOR &&
2834 rctx->rasterizer && rctx->rasterizer->flatshade)) {
2835 tmp |= S_028644_FLAT_SHADE(1);
2836 }
2837
2838 if (rshader->input[i].name == TGSI_SEMANTIC_GENERIC &&
2839 (sprite_coord_enable & (1 << rshader->input[i].sid))) {
2840 tmp |= S_028644_PT_SPRITE_TEX(1);
2841 }
2842
2843 spi_ps_input_cntl[num++] = tmp;
2844 }
2845 }
2846
2847 r600_store_context_reg_seq(cb, R_028644_SPI_PS_INPUT_CNTL_0, num);
2848 r600_store_array(cb, num, spi_ps_input_cntl);
2849
2850 for (i = 0; i < rshader->noutput; i++) {
2851 if (rshader->output[i].name == TGSI_SEMANTIC_POSITION)
2852 z_export = 1;
2853 if (rshader->output[i].name == TGSI_SEMANTIC_STENCIL)
2854 stencil_export = 1;
2855 }
2856 if (rshader->uses_kill)
2857 db_shader_control |= S_02880C_KILL_ENABLE(1);
2858
2859 db_shader_control |= S_02880C_Z_EXPORT_ENABLE(z_export);
2860 db_shader_control |= S_02880C_STENCIL_EXPORT_ENABLE(stencil_export);
2861
2862 exports_ps = 0;
2863 for (i = 0; i < rshader->noutput; i++) {
2864 if (rshader->output[i].name == TGSI_SEMANTIC_POSITION ||
2865 rshader->output[i].name == TGSI_SEMANTIC_STENCIL)
2866 exports_ps |= 1;
2867 }
2868
2869 num_cout = rshader->nr_ps_color_exports;
2870
2871 exports_ps |= S_02884C_EXPORT_COLORS(num_cout);
2872 if (!exports_ps) {
2873 /* always at least export 1 component per pixel */
2874 exports_ps = 2;
2875 }
2876 shader->nr_ps_color_outputs = num_cout;
2877 if (ninterp == 0) {
2878 ninterp = 1;
2879 have_perspective = TRUE;
2880 }
2881
2882 if (!have_perspective && !have_linear)
2883 have_perspective = TRUE;
2884
2885 spi_ps_in_control_0 = S_0286CC_NUM_INTERP(ninterp) |
2886 S_0286CC_PERSP_GRADIENT_ENA(have_perspective) |
2887 S_0286CC_LINEAR_GRADIENT_ENA(have_linear);
2888 spi_input_z = 0;
2889 if (pos_index != -1) {
2890 spi_ps_in_control_0 |= S_0286CC_POSITION_ENA(1) |
2891 S_0286CC_POSITION_CENTROID(rshader->input[pos_index].centroid) |
2892 S_0286CC_POSITION_ADDR(rshader->input[pos_index].gpr);
2893 spi_input_z |= S_0286D8_PROVIDE_Z_TO_SPI(1);
2894 }
2895
2896 spi_ps_in_control_1 = 0;
2897 if (face_index != -1) {
2898 spi_ps_in_control_1 |= S_0286D0_FRONT_FACE_ENA(1) |
2899 S_0286D0_FRONT_FACE_ADDR(rshader->input[face_index].gpr);
2900 }
2901
2902 spi_baryc_cntl = 0;
2903 if (have_perspective)
2904 spi_baryc_cntl |= S_0286E0_PERSP_CENTER_ENA(1) |
2905 S_0286E0_PERSP_CENTROID_ENA(have_centroid);
2906 if (have_linear)
2907 spi_baryc_cntl |= S_0286E0_LINEAR_CENTER_ENA(1) |
2908 S_0286E0_LINEAR_CENTROID_ENA(have_centroid);
2909
2910 r600_store_context_reg_seq(cb, R_0286CC_SPI_PS_IN_CONTROL_0, 2);
2911 r600_store_value(cb, spi_ps_in_control_0); /* R_0286CC_SPI_PS_IN_CONTROL_0 */
2912 r600_store_value(cb, spi_ps_in_control_1); /* R_0286D0_SPI_PS_IN_CONTROL_1 */
2913
2914 r600_store_context_reg(cb, R_0286E0_SPI_BARYC_CNTL, spi_baryc_cntl);
2915 r600_store_context_reg(cb, R_0286D8_SPI_INPUT_Z, spi_input_z);
2916 r600_store_context_reg(cb, R_02884C_SQ_PGM_EXPORTS_PS, exports_ps);
2917
2918 r600_store_context_reg_seq(cb, R_028840_SQ_PGM_START_PS, 2);
2919 r600_store_value(cb, shader->bo->gpu_address >> 8);
2920 r600_store_value(cb, /* R_028844_SQ_PGM_RESOURCES_PS */
2921 S_028844_NUM_GPRS(rshader->bc.ngpr) |
2922 S_028844_PRIME_CACHE_ON_DRAW(1) |
2923 S_028844_STACK_SIZE(rshader->bc.nstack));
2924 /* After that, the NOP relocation packet must be emitted (shader->bo, RADEON_USAGE_READ). */
2925
2926 shader->db_shader_control = db_shader_control;
2927 shader->ps_depth_export = z_export | stencil_export;
2928
2929 shader->sprite_coord_enable = sprite_coord_enable;
2930 if (rctx->rasterizer)
2931 shader->flatshade = rctx->rasterizer->flatshade;
2932 }
2933
2934 void evergreen_update_es_state(struct pipe_context *ctx, struct r600_pipe_shader *shader)
2935 {
2936 struct r600_command_buffer *cb = &shader->command_buffer;
2937 struct r600_shader *rshader = &shader->shader;
2938
2939 r600_init_command_buffer(cb, 32);
2940
2941 r600_store_context_reg(cb, R_028890_SQ_PGM_RESOURCES_ES,
2942 S_028890_NUM_GPRS(rshader->bc.ngpr) |
2943 S_028890_STACK_SIZE(rshader->bc.nstack));
2944 r600_store_context_reg(cb, R_02888C_SQ_PGM_START_ES,
2945 shader->bo->gpu_address >> 8);
2946 /* After that, the NOP relocation packet must be emitted (shader->bo, RADEON_USAGE_READ). */
2947 }
2948
2949 void evergreen_update_gs_state(struct pipe_context *ctx, struct r600_pipe_shader *shader)
2950 {
2951 struct r600_context *rctx = (struct r600_context *)ctx;
2952 struct r600_command_buffer *cb = &shader->command_buffer;
2953 struct r600_shader *rshader = &shader->shader;
2954 struct r600_shader *cp_shader = &shader->gs_copy_shader->shader;
2955 unsigned gsvs_itemsize =
2956 (cp_shader->ring_item_size * rshader->gs_max_out_vertices) >> 2;
2957
2958 r600_init_command_buffer(cb, 64);
2959
2960 /* VGT_GS_MODE is written by evergreen_emit_shader_stages */
2961
2962 r600_store_context_reg(cb, R_028AB8_VGT_VTX_CNT_EN, 1);
2963
2964 r600_store_context_reg(cb, R_028B38_VGT_GS_MAX_VERT_OUT,
2965 S_028B38_MAX_VERT_OUT(rshader->gs_max_out_vertices));
2966 r600_store_context_reg(cb, R_028A6C_VGT_GS_OUT_PRIM_TYPE,
2967 r600_conv_prim_to_gs_out(rshader->gs_output_prim));
2968
2969 if (rctx->screen->b.info.drm_minor >= 35) {
2970 r600_store_context_reg(cb, R_028B90_VGT_GS_INSTANCE_CNT,
2971 S_028B90_CNT(MIN2(rshader->gs_num_invocations, 127)) |
2972 S_028B90_ENABLE(rshader->gs_num_invocations > 0));
2973 }
2974 r600_store_context_reg_seq(cb, R_02891C_SQ_GS_VERT_ITEMSIZE, 4);
2975 r600_store_value(cb, cp_shader->ring_item_size >> 2);
2976 r600_store_value(cb, 0);
2977 r600_store_value(cb, 0);
2978 r600_store_value(cb, 0);
2979
2980 r600_store_context_reg(cb, R_028900_SQ_ESGS_RING_ITEMSIZE,
2981 (rshader->ring_item_size) >> 2);
2982
2983 r600_store_context_reg(cb, R_028904_SQ_GSVS_RING_ITEMSIZE,
2984 gsvs_itemsize);
2985
2986 r600_store_context_reg_seq(cb, R_02892C_SQ_GSVS_RING_OFFSET_1, 3);
2987 r600_store_value(cb, gsvs_itemsize);
2988 r600_store_value(cb, gsvs_itemsize);
2989 r600_store_value(cb, gsvs_itemsize);
2990
2991 /* FIXME calculate these values somehow ??? */
2992 r600_store_context_reg_seq(cb, R_028A54_GS_PER_ES, 3);
2993 r600_store_value(cb, 0x80); /* GS_PER_ES */
2994 r600_store_value(cb, 0x100); /* ES_PER_GS */
2995 r600_store_value(cb, 0x2); /* GS_PER_VS */
2996
2997 r600_store_context_reg(cb, R_028878_SQ_PGM_RESOURCES_GS,
2998 S_028878_NUM_GPRS(rshader->bc.ngpr) |
2999 S_028878_STACK_SIZE(rshader->bc.nstack));
3000 r600_store_context_reg(cb, R_028874_SQ_PGM_START_GS,
3001 shader->bo->gpu_address >> 8);
3002 /* After that, the NOP relocation packet must be emitted (shader->bo, RADEON_USAGE_READ). */
3003 }
3004
3005
3006 void evergreen_update_vs_state(struct pipe_context *ctx, struct r600_pipe_shader *shader)
3007 {
3008 struct r600_command_buffer *cb = &shader->command_buffer;
3009 struct r600_shader *rshader = &shader->shader;
3010 unsigned spi_vs_out_id[10] = {};
3011 unsigned i, tmp, nparams = 0;
3012
3013 for (i = 0; i < rshader->noutput; i++) {
3014 if (rshader->output[i].spi_sid) {
3015 tmp = rshader->output[i].spi_sid << ((nparams & 3) * 8);
3016 spi_vs_out_id[nparams / 4] |= tmp;
3017 nparams++;
3018 }
3019 }
3020
3021 r600_init_command_buffer(cb, 32);
3022
3023 r600_store_context_reg_seq(cb, R_02861C_SPI_VS_OUT_ID_0, 10);
3024 for (i = 0; i < 10; i++) {
3025 r600_store_value(cb, spi_vs_out_id[i]);
3026 }
3027
3028 /* Certain attributes (position, psize, etc.) don't count as params.
3029 * VS is required to export at least one param and r600_shader_from_tgsi()
3030 * takes care of adding a dummy export.
3031 */
3032 if (nparams < 1)
3033 nparams = 1;
3034
3035 r600_store_context_reg(cb, R_0286C4_SPI_VS_OUT_CONFIG,
3036 S_0286C4_VS_EXPORT_COUNT(nparams - 1));
3037 r600_store_context_reg(cb, R_028860_SQ_PGM_RESOURCES_VS,
3038 S_028860_NUM_GPRS(rshader->bc.ngpr) |
3039 S_028860_STACK_SIZE(rshader->bc.nstack));
3040 if (rshader->vs_position_window_space) {
3041 r600_store_context_reg(cb, R_028818_PA_CL_VTE_CNTL,
3042 S_028818_VTX_XY_FMT(1) | S_028818_VTX_Z_FMT(1));
3043 } else {
3044 r600_store_context_reg(cb, R_028818_PA_CL_VTE_CNTL,
3045 S_028818_VTX_W0_FMT(1) |
3046 S_028818_VPORT_X_SCALE_ENA(1) | S_028818_VPORT_X_OFFSET_ENA(1) |
3047 S_028818_VPORT_Y_SCALE_ENA(1) | S_028818_VPORT_Y_OFFSET_ENA(1) |
3048 S_028818_VPORT_Z_SCALE_ENA(1) | S_028818_VPORT_Z_OFFSET_ENA(1));
3049
3050 }
3051 r600_store_context_reg(cb, R_02885C_SQ_PGM_START_VS,
3052 shader->bo->gpu_address >> 8);
3053 /* After that, the NOP relocation packet must be emitted (shader->bo, RADEON_USAGE_READ). */
3054
3055 shader->pa_cl_vs_out_cntl =
3056 S_02881C_VS_OUT_CCDIST0_VEC_ENA((rshader->clip_dist_write & 0x0F) != 0) |
3057 S_02881C_VS_OUT_CCDIST1_VEC_ENA((rshader->clip_dist_write & 0xF0) != 0) |
3058 S_02881C_VS_OUT_MISC_VEC_ENA(rshader->vs_out_misc_write) |
3059 S_02881C_USE_VTX_POINT_SIZE(rshader->vs_out_point_size) |
3060 S_02881C_USE_VTX_EDGE_FLAG(rshader->vs_out_edgeflag) |
3061 S_02881C_USE_VTX_VIEWPORT_INDX(rshader->vs_out_viewport) |
3062 S_02881C_USE_VTX_RENDER_TARGET_INDX(rshader->vs_out_layer);
3063 }
3064
3065 void *evergreen_create_resolve_blend(struct r600_context *rctx)
3066 {
3067 struct pipe_blend_state blend;
3068
3069 memset(&blend, 0, sizeof(blend));
3070 blend.independent_blend_enable = true;
3071 blend.rt[0].colormask = 0xf;
3072 return evergreen_create_blend_state_mode(&rctx->b.b, &blend, V_028808_CB_RESOLVE);
3073 }
3074
3075 void *evergreen_create_decompress_blend(struct r600_context *rctx)
3076 {
3077 struct pipe_blend_state blend;
3078 unsigned mode = rctx->screen->has_compressed_msaa_texturing ?
3079 V_028808_CB_FMASK_DECOMPRESS : V_028808_CB_DECOMPRESS;
3080
3081 memset(&blend, 0, sizeof(blend));
3082 blend.independent_blend_enable = true;
3083 blend.rt[0].colormask = 0xf;
3084 return evergreen_create_blend_state_mode(&rctx->b.b, &blend, mode);
3085 }
3086
3087 void *evergreen_create_fastclear_blend(struct r600_context *rctx)
3088 {
3089 struct pipe_blend_state blend;
3090 unsigned mode = V_028808_CB_ELIMINATE_FAST_CLEAR;
3091
3092 memset(&blend, 0, sizeof(blend));
3093 blend.independent_blend_enable = true;
3094 blend.rt[0].colormask = 0xf;
3095 return evergreen_create_blend_state_mode(&rctx->b.b, &blend, mode);
3096 }
3097
3098 void *evergreen_create_db_flush_dsa(struct r600_context *rctx)
3099 {
3100 struct pipe_depth_stencil_alpha_state dsa = {{0}};
3101
3102 return rctx->b.b.create_depth_stencil_alpha_state(&rctx->b.b, &dsa);
3103 }
3104
3105 void evergreen_update_db_shader_control(struct r600_context * rctx)
3106 {
3107 bool dual_export;
3108 unsigned db_shader_control;
3109
3110 if (!rctx->ps_shader) {
3111 return;
3112 }
3113
3114 dual_export = rctx->framebuffer.export_16bpc &&
3115 !rctx->ps_shader->current->ps_depth_export;
3116
3117 db_shader_control = rctx->ps_shader->current->db_shader_control |
3118 S_02880C_DUAL_EXPORT_ENABLE(dual_export) |
3119 S_02880C_DB_SOURCE_FORMAT(dual_export ? V_02880C_EXPORT_DB_TWO :
3120 V_02880C_EXPORT_DB_FULL) |
3121 S_02880C_ALPHA_TO_MASK_DISABLE(rctx->framebuffer.cb0_is_integer);
3122
3123 /* When alpha test is enabled we can't trust the hw to make the proper
3124 * decision on the order in which ztest should be run related to fragment
3125 * shader execution.
3126 *
3127 * If alpha test is enabled perform early z rejection (RE_Z) but don't early
3128 * write to the zbuffer. Write to zbuffer is delayed after fragment shader
3129 * execution and thus after alpha test so if discarded by the alpha test
3130 * the z value is not written.
3131 * If ReZ is enabled, and the zfunc/zenable/zwrite values change you can
3132 * get a hang unless you flush the DB in between. For now just use
3133 * LATE_Z.
3134 */
3135 if (rctx->alphatest_state.sx_alpha_test_control) {
3136 db_shader_control |= S_02880C_Z_ORDER(V_02880C_LATE_Z);
3137 } else {
3138 db_shader_control |= S_02880C_Z_ORDER(V_02880C_EARLY_Z_THEN_LATE_Z);
3139 }
3140
3141 if (db_shader_control != rctx->db_misc_state.db_shader_control) {
3142 rctx->db_misc_state.db_shader_control = db_shader_control;
3143 rctx->db_misc_state.atom.dirty = true;
3144 }
3145 }
3146
3147 static void evergreen_dma_copy_tile(struct r600_context *rctx,
3148 struct pipe_resource *dst,
3149 unsigned dst_level,
3150 unsigned dst_x,
3151 unsigned dst_y,
3152 unsigned dst_z,
3153 struct pipe_resource *src,
3154 unsigned src_level,
3155 unsigned src_x,
3156 unsigned src_y,
3157 unsigned src_z,
3158 unsigned copy_height,
3159 unsigned pitch,
3160 unsigned bpp)
3161 {
3162 struct radeon_winsys_cs *cs = rctx->b.rings.dma.cs;
3163 struct r600_texture *rsrc = (struct r600_texture*)src;
3164 struct r600_texture *rdst = (struct r600_texture*)dst;
3165 unsigned array_mode, lbpp, pitch_tile_max, slice_tile_max, size;
3166 unsigned ncopy, height, cheight, detile, i, x, y, z, src_mode, dst_mode;
3167 unsigned sub_cmd, bank_h, bank_w, mt_aspect, nbanks, tile_split, non_disp_tiling = 0;
3168 uint64_t base, addr;
3169
3170 dst_mode = rdst->surface.level[dst_level].mode;
3171 src_mode = rsrc->surface.level[src_level].mode;
3172 /* downcast linear aligned to linear to simplify test */
3173 src_mode = src_mode == RADEON_SURF_MODE_LINEAR_ALIGNED ? RADEON_SURF_MODE_LINEAR : src_mode;
3174 dst_mode = dst_mode == RADEON_SURF_MODE_LINEAR_ALIGNED ? RADEON_SURF_MODE_LINEAR : dst_mode;
3175 assert(dst_mode != src_mode);
3176
3177 /* non_disp_tiling bit needs to be set for depth, stencil, and fmask surfaces */
3178 if (util_format_has_depth(util_format_description(src->format)))
3179 non_disp_tiling = 1;
3180
3181 y = 0;
3182 sub_cmd = EG_DMA_COPY_TILED;
3183 lbpp = util_logbase2(bpp);
3184 pitch_tile_max = ((pitch / bpp) / 8) - 1;
3185 nbanks = eg_num_banks(rctx->screen->b.tiling_info.num_banks);
3186
3187 if (dst_mode == RADEON_SURF_MODE_LINEAR) {
3188 /* T2L */
3189 array_mode = evergreen_array_mode(src_mode);
3190 slice_tile_max = (rsrc->surface.level[src_level].nblk_x * rsrc->surface.level[src_level].nblk_y) / (8*8);
3191 slice_tile_max = slice_tile_max ? slice_tile_max - 1 : 0;
3192 /* linear height must be the same as the slice tile max height, it's ok even
3193 * if the linear destination/source have smaller heigh as the size of the
3194 * dma packet will be using the copy_height which is always smaller or equal
3195 * to the linear height
3196 */
3197 height = rsrc->surface.level[src_level].npix_y;
3198 detile = 1;
3199 x = src_x;
3200 y = src_y;
3201 z = src_z;
3202 base = rsrc->surface.level[src_level].offset;
3203 addr = rdst->surface.level[dst_level].offset;
3204 addr += rdst->surface.level[dst_level].slice_size * dst_z;
3205 addr += dst_y * pitch + dst_x * bpp;
3206 bank_h = eg_bank_wh(rsrc->surface.bankh);
3207 bank_w = eg_bank_wh(rsrc->surface.bankw);
3208 mt_aspect = eg_macro_tile_aspect(rsrc->surface.mtilea);
3209 tile_split = eg_tile_split(rsrc->surface.tile_split);
3210 base += rsrc->resource.gpu_address;
3211 addr += rdst->resource.gpu_address;
3212 } else {
3213 /* L2T */
3214 array_mode = evergreen_array_mode(dst_mode);
3215 slice_tile_max = (rdst->surface.level[dst_level].nblk_x * rdst->surface.level[dst_level].nblk_y) / (8*8);
3216 slice_tile_max = slice_tile_max ? slice_tile_max - 1 : 0;
3217 /* linear height must be the same as the slice tile max height, it's ok even
3218 * if the linear destination/source have smaller heigh as the size of the
3219 * dma packet will be using the copy_height which is always smaller or equal
3220 * to the linear height
3221 */
3222 height = rdst->surface.level[dst_level].npix_y;
3223 detile = 0;
3224 x = dst_x;
3225 y = dst_y;
3226 z = dst_z;
3227 base = rdst->surface.level[dst_level].offset;
3228 addr = rsrc->surface.level[src_level].offset;
3229 addr += rsrc->surface.level[src_level].slice_size * src_z;
3230 addr += src_y * pitch + src_x * bpp;
3231 bank_h = eg_bank_wh(rdst->surface.bankh);
3232 bank_w = eg_bank_wh(rdst->surface.bankw);
3233 mt_aspect = eg_macro_tile_aspect(rdst->surface.mtilea);
3234 tile_split = eg_tile_split(rdst->surface.tile_split);
3235 base += rdst->resource.gpu_address;
3236 addr += rsrc->resource.gpu_address;
3237 }
3238
3239 size = (copy_height * pitch) / 4;
3240 ncopy = (size / EG_DMA_COPY_MAX_SIZE) + !!(size % EG_DMA_COPY_MAX_SIZE);
3241 r600_need_dma_space(&rctx->b, ncopy * 9);
3242
3243 for (i = 0; i < ncopy; i++) {
3244 cheight = copy_height;
3245 if (((cheight * pitch) / 4) > EG_DMA_COPY_MAX_SIZE) {
3246 cheight = (EG_DMA_COPY_MAX_SIZE * 4) / pitch;
3247 }
3248 size = (cheight * pitch) / 4;
3249 /* emit reloc before writting cs so that cs is always in consistent state */
3250 r600_context_bo_reloc(&rctx->b, &rctx->b.rings.dma, &rsrc->resource,
3251 RADEON_USAGE_READ, RADEON_PRIO_MIN);
3252 r600_context_bo_reloc(&rctx->b, &rctx->b.rings.dma, &rdst->resource,
3253 RADEON_USAGE_WRITE, RADEON_PRIO_MIN);
3254 cs->buf[cs->cdw++] = DMA_PACKET(DMA_PACKET_COPY, sub_cmd, size);
3255 cs->buf[cs->cdw++] = base >> 8;
3256 cs->buf[cs->cdw++] = (detile << 31) | (array_mode << 27) |
3257 (lbpp << 24) | (bank_h << 21) |
3258 (bank_w << 18) | (mt_aspect << 16);
3259 cs->buf[cs->cdw++] = (pitch_tile_max << 0) | ((height - 1) << 16);
3260 cs->buf[cs->cdw++] = (slice_tile_max << 0);
3261 cs->buf[cs->cdw++] = (x << 0) | (z << 18);
3262 cs->buf[cs->cdw++] = (y << 0) | (tile_split << 21) | (nbanks << 25) | (non_disp_tiling << 28);
3263 cs->buf[cs->cdw++] = addr & 0xfffffffc;
3264 cs->buf[cs->cdw++] = (addr >> 32UL) & 0xff;
3265 copy_height -= cheight;
3266 addr += cheight * pitch;
3267 y += cheight;
3268 }
3269 }
3270
3271 static void evergreen_dma_copy(struct pipe_context *ctx,
3272 struct pipe_resource *dst,
3273 unsigned dst_level,
3274 unsigned dstx, unsigned dsty, unsigned dstz,
3275 struct pipe_resource *src,
3276 unsigned src_level,
3277 const struct pipe_box *src_box)
3278 {
3279 struct r600_context *rctx = (struct r600_context *)ctx;
3280 struct r600_texture *rsrc = (struct r600_texture*)src;
3281 struct r600_texture *rdst = (struct r600_texture*)dst;
3282 unsigned dst_pitch, src_pitch, bpp, dst_mode, src_mode, copy_height;
3283 unsigned src_w, dst_w;
3284 unsigned src_x, src_y;
3285 unsigned dst_x = dstx, dst_y = dsty, dst_z = dstz;
3286
3287 if (rctx->b.rings.dma.cs == NULL) {
3288 goto fallback;
3289 }
3290
3291 if (dst->target == PIPE_BUFFER && src->target == PIPE_BUFFER) {
3292 evergreen_dma_copy_buffer(rctx, dst, src, dst_x, src_box->x, src_box->width);
3293 return;
3294 }
3295
3296 if (src->format != dst->format || src_box->depth > 1 ||
3297 rdst->dirty_level_mask != 0) {
3298 goto fallback;
3299 }
3300
3301 if (rsrc->dirty_level_mask) {
3302 ctx->flush_resource(ctx, src);
3303 }
3304
3305 src_x = util_format_get_nblocksx(src->format, src_box->x);
3306 dst_x = util_format_get_nblocksx(src->format, dst_x);
3307 src_y = util_format_get_nblocksy(src->format, src_box->y);
3308 dst_y = util_format_get_nblocksy(src->format, dst_y);
3309
3310 bpp = rdst->surface.bpe;
3311 dst_pitch = rdst->surface.level[dst_level].pitch_bytes;
3312 src_pitch = rsrc->surface.level[src_level].pitch_bytes;
3313 src_w = rsrc->surface.level[src_level].npix_x;
3314 dst_w = rdst->surface.level[dst_level].npix_x;
3315 copy_height = src_box->height / rsrc->surface.blk_h;
3316
3317 dst_mode = rdst->surface.level[dst_level].mode;
3318 src_mode = rsrc->surface.level[src_level].mode;
3319 /* downcast linear aligned to linear to simplify test */
3320 src_mode = src_mode == RADEON_SURF_MODE_LINEAR_ALIGNED ? RADEON_SURF_MODE_LINEAR : src_mode;
3321 dst_mode = dst_mode == RADEON_SURF_MODE_LINEAR_ALIGNED ? RADEON_SURF_MODE_LINEAR : dst_mode;
3322
3323 if (src_pitch != dst_pitch || src_box->x || dst_x || src_w != dst_w) {
3324 /* FIXME evergreen can do partial blit */
3325 goto fallback;
3326 }
3327 /* the x test here are currently useless (because we don't support partial blit)
3328 * but keep them around so we don't forget about those
3329 */
3330 if (src_pitch % 8 || src_box->x % 8 || dst_x % 8 || src_box->y % 8 || dst_y % 8) {
3331 goto fallback;
3332 }
3333
3334 /* 128 bpp surfaces require non_disp_tiling for both
3335 * tiled and linear buffers on cayman. However, async
3336 * DMA only supports it on the tiled side. As such
3337 * the tile order is backwards after a L2T/T2L packet.
3338 */
3339 if ((rctx->b.chip_class == CAYMAN) &&
3340 (src_mode != dst_mode) &&
3341 (util_format_get_blocksize(src->format) >= 16)) {
3342 goto fallback;
3343 }
3344
3345 if (src_mode == dst_mode) {
3346 uint64_t dst_offset, src_offset;
3347 /* simple dma blit would do NOTE code here assume :
3348 * src_box.x/y == 0
3349 * dst_x/y == 0
3350 * dst_pitch == src_pitch
3351 */
3352 src_offset= rsrc->surface.level[src_level].offset;
3353 src_offset += rsrc->surface.level[src_level].slice_size * src_box->z;
3354 src_offset += src_y * src_pitch + src_x * bpp;
3355 dst_offset = rdst->surface.level[dst_level].offset;
3356 dst_offset += rdst->surface.level[dst_level].slice_size * dst_z;
3357 dst_offset += dst_y * dst_pitch + dst_x * bpp;
3358 evergreen_dma_copy_buffer(rctx, dst, src, dst_offset, src_offset,
3359 src_box->height * src_pitch);
3360 } else {
3361 evergreen_dma_copy_tile(rctx, dst, dst_level, dst_x, dst_y, dst_z,
3362 src, src_level, src_x, src_y, src_box->z,
3363 copy_height, dst_pitch, bpp);
3364 }
3365 return;
3366
3367 fallback:
3368 r600_resource_copy_region(ctx, dst, dst_level, dstx, dsty, dstz,
3369 src, src_level, src_box);
3370 }
3371
3372 void evergreen_init_state_functions(struct r600_context *rctx)
3373 {
3374 unsigned id = 4;
3375 int i;
3376 /* !!!
3377 * To avoid GPU lockup registers must be emited in a specific order
3378 * (no kidding ...). The order below is important and have been
3379 * partialy infered from analyzing fglrx command stream.
3380 *
3381 * Don't reorder atom without carefully checking the effect (GPU lockup
3382 * or piglit regression).
3383 * !!!
3384 */
3385
3386 r600_init_atom(rctx, &rctx->framebuffer.atom, id++, evergreen_emit_framebuffer_state, 0);
3387 /* shader const */
3388 r600_init_atom(rctx, &rctx->constbuf_state[PIPE_SHADER_VERTEX].atom, id++, evergreen_emit_vs_constant_buffers, 0);
3389 r600_init_atom(rctx, &rctx->constbuf_state[PIPE_SHADER_GEOMETRY].atom, id++, evergreen_emit_gs_constant_buffers, 0);
3390 r600_init_atom(rctx, &rctx->constbuf_state[PIPE_SHADER_FRAGMENT].atom, id++, evergreen_emit_ps_constant_buffers, 0);
3391 r600_init_atom(rctx, &rctx->constbuf_state[PIPE_SHADER_COMPUTE].atom, id++, evergreen_emit_cs_constant_buffers, 0);
3392 /* shader program */
3393 r600_init_atom(rctx, &rctx->cs_shader_state.atom, id++, evergreen_emit_cs_shader, 0);
3394 /* sampler */
3395 r600_init_atom(rctx, &rctx->samplers[PIPE_SHADER_VERTEX].states.atom, id++, evergreen_emit_vs_sampler_states, 0);
3396 r600_init_atom(rctx, &rctx->samplers[PIPE_SHADER_GEOMETRY].states.atom, id++, evergreen_emit_gs_sampler_states, 0);
3397 r600_init_atom(rctx, &rctx->samplers[PIPE_SHADER_FRAGMENT].states.atom, id++, evergreen_emit_ps_sampler_states, 0);
3398 /* resources */
3399 r600_init_atom(rctx, &rctx->vertex_buffer_state.atom, id++, evergreen_fs_emit_vertex_buffers, 0);
3400 r600_init_atom(rctx, &rctx->cs_vertex_buffer_state.atom, id++, evergreen_cs_emit_vertex_buffers, 0);
3401 r600_init_atom(rctx, &rctx->samplers[PIPE_SHADER_VERTEX].views.atom, id++, evergreen_emit_vs_sampler_views, 0);
3402 r600_init_atom(rctx, &rctx->samplers[PIPE_SHADER_GEOMETRY].views.atom, id++, evergreen_emit_gs_sampler_views, 0);
3403 r600_init_atom(rctx, &rctx->samplers[PIPE_SHADER_FRAGMENT].views.atom, id++, evergreen_emit_ps_sampler_views, 0);
3404
3405 r600_init_atom(rctx, &rctx->vgt_state.atom, id++, r600_emit_vgt_state, 7);
3406
3407 if (rctx->b.chip_class == EVERGREEN) {
3408 r600_init_atom(rctx, &rctx->sample_mask.atom, id++, evergreen_emit_sample_mask, 3);
3409 } else {
3410 r600_init_atom(rctx, &rctx->sample_mask.atom, id++, cayman_emit_sample_mask, 4);
3411 }
3412 rctx->sample_mask.sample_mask = ~0;
3413
3414 r600_init_atom(rctx, &rctx->alphatest_state.atom, id++, r600_emit_alphatest_state, 6);
3415 r600_init_atom(rctx, &rctx->blend_color.atom, id++, r600_emit_blend_color, 6);
3416 r600_init_atom(rctx, &rctx->blend_state.atom, id++, r600_emit_cso_state, 0);
3417 r600_init_atom(rctx, &rctx->cb_misc_state.atom, id++, evergreen_emit_cb_misc_state, 4);
3418 r600_init_atom(rctx, &rctx->clip_misc_state.atom, id++, r600_emit_clip_misc_state, 6);
3419 r600_init_atom(rctx, &rctx->clip_state.atom, id++, evergreen_emit_clip_state, 26);
3420 r600_init_atom(rctx, &rctx->db_misc_state.atom, id++, evergreen_emit_db_misc_state, 10);
3421 r600_init_atom(rctx, &rctx->db_state.atom, id++, evergreen_emit_db_state, 14);
3422 r600_init_atom(rctx, &rctx->dsa_state.atom, id++, r600_emit_cso_state, 0);
3423 r600_init_atom(rctx, &rctx->poly_offset_state.atom, id++, evergreen_emit_polygon_offset, 6);
3424 r600_init_atom(rctx, &rctx->rasterizer_state.atom, id++, r600_emit_cso_state, 0);
3425 for (i = 0; i < 16; i++) {
3426 r600_init_atom(rctx, &rctx->viewport[i].atom, id++, r600_emit_viewport_state, 8);
3427 r600_init_atom(rctx, &rctx->scissor[i].atom, id++, evergreen_emit_scissor_state, 4);
3428 rctx->viewport[i].idx = i;
3429 rctx->scissor[i].idx = i;
3430 }
3431 r600_init_atom(rctx, &rctx->stencil_ref.atom, id++, r600_emit_stencil_ref, 4);
3432 r600_init_atom(rctx, &rctx->vertex_fetch_shader.atom, id++, evergreen_emit_vertex_fetch_shader, 5);
3433 rctx->atoms[id++] = &rctx->b.streamout.begin_atom;
3434 rctx->atoms[id++] = &rctx->b.streamout.enable_atom;
3435 r600_init_atom(rctx, &rctx->vertex_shader.atom, id++, r600_emit_shader, 23);
3436 r600_init_atom(rctx, &rctx->pixel_shader.atom, id++, r600_emit_shader, 0);
3437 r600_init_atom(rctx, &rctx->geometry_shader.atom, id++, r600_emit_shader, 0);
3438 r600_init_atom(rctx, &rctx->export_shader.atom, id++, r600_emit_shader, 0);
3439 r600_init_atom(rctx, &rctx->shader_stages.atom, id++, evergreen_emit_shader_stages, 6);
3440 r600_init_atom(rctx, &rctx->gs_rings.atom, id++, evergreen_emit_gs_rings, 26);
3441
3442 rctx->b.b.create_blend_state = evergreen_create_blend_state;
3443 rctx->b.b.create_depth_stencil_alpha_state = evergreen_create_dsa_state;
3444 rctx->b.b.create_rasterizer_state = evergreen_create_rs_state;
3445 rctx->b.b.create_sampler_state = evergreen_create_sampler_state;
3446 rctx->b.b.create_sampler_view = evergreen_create_sampler_view;
3447 rctx->b.b.set_framebuffer_state = evergreen_set_framebuffer_state;
3448 rctx->b.b.set_polygon_stipple = evergreen_set_polygon_stipple;
3449 rctx->b.b.set_scissor_states = evergreen_set_scissor_states;
3450
3451 if (rctx->b.chip_class == EVERGREEN)
3452 rctx->b.b.get_sample_position = evergreen_get_sample_position;
3453 else
3454 rctx->b.b.get_sample_position = cayman_get_sample_position;
3455 rctx->b.dma_copy = evergreen_dma_copy;
3456
3457 evergreen_init_compute_state_functions(rctx);
3458 }