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r600g: fix evergreen new path
[mesa.git] / src / gallium / drivers / r600 / evergreen_state.c
1 /*
2 * Copyright 2010 Jerome Glisse <glisse@freedesktop.org>
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * on the rights to use, copy, modify, merge, publish, distribute, sub
8 * license, and/or sell copies of the Software, and to permit persons to whom
9 * the Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
13 * Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHOR(S) AND/OR THEIR SUPPLIERS BE LIABLE FOR ANY CLAIM,
19 * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
20 * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
21 * USE OR OTHER DEALINGS IN THE SOFTWARE.
22 */
23
24 /* TODO:
25 * - fix mask for depth control & cull for query
26 */
27 #include <stdio.h>
28 #include <errno.h>
29 #include <pipe/p_defines.h>
30 #include <pipe/p_state.h>
31 #include <pipe/p_context.h>
32 #include <tgsi/tgsi_scan.h>
33 #include <tgsi/tgsi_parse.h>
34 #include <tgsi/tgsi_util.h>
35 #include <util/u_blitter.h>
36 #include <util/u_double_list.h>
37 #include <util/u_transfer.h>
38 #include <util/u_surface.h>
39 #include <util/u_pack_color.h>
40 #include <util/u_memory.h>
41 #include <util/u_inlines.h>
42 #include <pipebuffer/pb_buffer.h>
43 #include "r600.h"
44 #include "evergreend.h"
45 struct radeon_state {
46 unsigned dummy;
47 };
48 #include "r600_resource.h"
49 #include "r600_shader.h"
50 #include "r600_pipe.h"
51 #include "eg_state_inlines.h"
52
53 static void evergreen_set_blend_color(struct pipe_context *ctx,
54 const struct pipe_blend_color *state)
55 {
56 struct r600_pipe_context *rctx = (struct r600_pipe_context *)ctx;
57 struct r600_pipe_state *rstate = CALLOC_STRUCT(r600_pipe_state);
58
59 if (rstate == NULL)
60 return;
61
62 rstate->id = R600_PIPE_STATE_BLEND_COLOR;
63 r600_pipe_state_add_reg(rstate, EVERGREEN_GROUP_CONTEXT, R_028414_CB_BLEND_RED, fui(state->color[0]), 0xFFFFFFFF, NULL);
64 r600_pipe_state_add_reg(rstate, EVERGREEN_GROUP_CONTEXT, R_028418_CB_BLEND_GREEN, fui(state->color[1]), 0xFFFFFFFF, NULL);
65 r600_pipe_state_add_reg(rstate, EVERGREEN_GROUP_CONTEXT, R_02841C_CB_BLEND_BLUE, fui(state->color[2]), 0xFFFFFFFF, NULL);
66 r600_pipe_state_add_reg(rstate, EVERGREEN_GROUP_CONTEXT, R_028420_CB_BLEND_ALPHA, fui(state->color[3]), 0xFFFFFFFF, NULL);
67
68 free(rctx->states[R600_PIPE_STATE_BLEND_COLOR]);
69 rctx->states[R600_PIPE_STATE_BLEND_COLOR] = rstate;
70 r600_context_pipe_state_set(&rctx->ctx, rstate);
71 }
72
73 static void *evergreen_create_blend_state(struct pipe_context *ctx,
74 const struct pipe_blend_state *state)
75 {
76 struct r600_pipe_blend *blend = CALLOC_STRUCT(r600_pipe_blend);
77 struct r600_pipe_state *rstate;
78 u32 color_control, target_mask;
79 /* FIXME there is more then 8 framebuffer */
80 unsigned blend_cntl[8];
81
82 if (blend == NULL) {
83 return NULL;
84 }
85 rstate = &blend->rstate;
86
87 rstate->id = R600_PIPE_STATE_BLEND;
88
89 target_mask = 0;
90 color_control = S_028808_MODE(1);
91 if (state->logicop_enable) {
92 color_control |= (state->logicop_func << 16) | (state->logicop_func << 20);
93 } else {
94 color_control |= (0xcc << 16);
95 }
96 /* we pretend 8 buffer are used, CB_SHADER_MASK will disable unused one */
97 if (state->independent_blend_enable) {
98 for (int i = 0; i < 8; i++) {
99 target_mask |= (state->rt[i].colormask << (4 * i));
100 }
101 } else {
102 for (int i = 0; i < 8; i++) {
103 target_mask |= (state->rt[0].colormask << (4 * i));
104 }
105 }
106 blend->cb_target_mask = target_mask;
107 r600_pipe_state_add_reg(rstate, EVERGREEN_GROUP_CONTEXT, R_028808_CB_COLOR_CONTROL,
108 color_control, 0xFFFFFFFF, NULL);
109 r600_pipe_state_add_reg(rstate, EVERGREEN_GROUP_CONTEXT, R_028C3C_PA_SC_AA_MASK, 0xFFFFFFFF, 0xFFFFFFFF, NULL);
110
111 for (int i = 0; i < 8; i++) {
112 unsigned eqRGB = state->rt[i].rgb_func;
113 unsigned srcRGB = state->rt[i].rgb_src_factor;
114 unsigned dstRGB = state->rt[i].rgb_dst_factor;
115 unsigned eqA = state->rt[i].alpha_func;
116 unsigned srcA = state->rt[i].alpha_src_factor;
117 unsigned dstA = state->rt[i].alpha_dst_factor;
118
119 blend_cntl[i] = 0;
120 if (!state->rt[i].blend_enable)
121 continue;
122
123 blend_cntl[i] |= S_028780_BLEND_CONTROL_ENABLE(1);
124 blend_cntl[i] |= S_028780_COLOR_COMB_FCN(r600_translate_blend_function(eqRGB));
125 blend_cntl[i] |= S_028780_COLOR_SRCBLEND(r600_translate_blend_factor(srcRGB));
126 blend_cntl[i] |= S_028780_COLOR_DESTBLEND(r600_translate_blend_factor(dstRGB));
127
128 if (srcA != srcRGB || dstA != dstRGB || eqA != eqRGB) {
129 blend_cntl[i] |= S_028780_SEPARATE_ALPHA_BLEND(1);
130 blend_cntl[i] |= S_028780_ALPHA_COMB_FCN(r600_translate_blend_function(eqA));
131 blend_cntl[i] |= S_028780_ALPHA_SRCBLEND(r600_translate_blend_factor(srcA));
132 blend_cntl[i] |= S_028780_ALPHA_DESTBLEND(r600_translate_blend_factor(dstA));
133 }
134 }
135 for (int i = 0; i < 8; i++) {
136 r600_pipe_state_add_reg(rstate, EVERGREEN_GROUP_CONTEXT, R_028780_CB_BLEND0_CONTROL + i * 4, blend_cntl[i], 0xFFFFFFFF, NULL);
137 }
138
139 return rstate;
140 }
141
142 static void evergreen_bind_blend_state(struct pipe_context *ctx, void *state)
143 {
144 struct r600_pipe_context *rctx = (struct r600_pipe_context *)ctx;
145 struct r600_pipe_blend *blend = (struct r600_pipe_blend *)state;
146 struct r600_pipe_state *rstate;
147
148 if (state == NULL)
149 return;
150 rstate = &blend->rstate;
151 rctx->states[rstate->id] = rstate;
152 rctx->cb_target_mask = blend->cb_target_mask;
153 r600_context_pipe_state_set(&rctx->ctx, rstate);
154 }
155
156 static void *evergreen_create_dsa_state(struct pipe_context *ctx,
157 const struct pipe_depth_stencil_alpha_state *state)
158 {
159 struct r600_pipe_state *rstate = CALLOC_STRUCT(r600_pipe_state);
160 unsigned db_depth_control, alpha_test_control, alpha_ref, db_shader_control;
161 unsigned stencil_ref_mask, stencil_ref_mask_bf, db_render_override, db_render_control;
162
163 if (rstate == NULL) {
164 return NULL;
165 }
166
167 rstate->id = R600_PIPE_STATE_DSA;
168 /* depth TODO some of those db_shader_control field depend on shader adjust mask & add it to shader */
169 /* db_shader_control is 0xFFFFFFBE as Z_EXPORT_ENABLE (bit 0) will be
170 * set by fragment shader if it export Z and KILL_ENABLE (bit 6) will
171 * be set if shader use texkill instruction
172 */
173 db_shader_control = 0x210;
174 stencil_ref_mask = 0;
175 stencil_ref_mask_bf = 0;
176 db_depth_control = S_028800_Z_ENABLE(state->depth.enabled) |
177 S_028800_Z_WRITE_ENABLE(state->depth.writemask) |
178 S_028800_ZFUNC(state->depth.func);
179
180 /* stencil */
181 if (state->stencil[0].enabled) {
182 db_depth_control |= S_028800_STENCIL_ENABLE(1);
183 db_depth_control |= S_028800_STENCILFUNC(r600_translate_ds_func(state->stencil[0].func));
184 db_depth_control |= S_028800_STENCILFAIL(r600_translate_stencil_op(state->stencil[0].fail_op));
185 db_depth_control |= S_028800_STENCILZPASS(r600_translate_stencil_op(state->stencil[0].zpass_op));
186 db_depth_control |= S_028800_STENCILZFAIL(r600_translate_stencil_op(state->stencil[0].zfail_op));
187
188
189 stencil_ref_mask = S_028430_STENCILMASK(state->stencil[0].valuemask) |
190 S_028430_STENCILWRITEMASK(state->stencil[0].writemask);
191 if (state->stencil[1].enabled) {
192 db_depth_control |= S_028800_BACKFACE_ENABLE(1);
193 db_depth_control |= S_028800_STENCILFUNC_BF(r600_translate_ds_func(state->stencil[1].func));
194 db_depth_control |= S_028800_STENCILFAIL_BF(r600_translate_stencil_op(state->stencil[1].fail_op));
195 db_depth_control |= S_028800_STENCILZPASS_BF(r600_translate_stencil_op(state->stencil[1].zpass_op));
196 db_depth_control |= S_028800_STENCILZFAIL_BF(r600_translate_stencil_op(state->stencil[1].zfail_op));
197 stencil_ref_mask_bf = S_028434_STENCILMASK_BF(state->stencil[1].valuemask) |
198 S_028434_STENCILWRITEMASK_BF(state->stencil[1].writemask);
199 }
200 }
201
202 /* alpha */
203 alpha_test_control = 0;
204 alpha_ref = 0;
205 if (state->alpha.enabled) {
206 alpha_test_control = S_028410_ALPHA_FUNC(state->alpha.func);
207 alpha_test_control |= S_028410_ALPHA_TEST_ENABLE(1);
208 alpha_ref = fui(state->alpha.ref_value);
209 }
210
211 /* misc */
212 db_render_control = 0;
213 db_render_override = S_02800C_FORCE_HIZ_ENABLE(V_02800C_FORCE_DISABLE) |
214 S_02800C_FORCE_HIS_ENABLE0(V_02800C_FORCE_DISABLE) |
215 S_02800C_FORCE_HIS_ENABLE1(V_02800C_FORCE_DISABLE);
216 /* TODO db_render_override depends on query */
217 r600_pipe_state_add_reg(rstate, EVERGREEN_GROUP_CONTEXT, R_028028_DB_STENCIL_CLEAR, 0x00000000, 0xFFFFFFFF, NULL);
218 r600_pipe_state_add_reg(rstate, EVERGREEN_GROUP_CONTEXT, R_02802C_DB_DEPTH_CLEAR, 0x3F800000, 0xFFFFFFFF, NULL);
219 r600_pipe_state_add_reg(rstate, EVERGREEN_GROUP_CONTEXT, R_028410_SX_ALPHA_TEST_CONTROL, alpha_test_control, 0xFFFFFFFF, NULL);
220 r600_pipe_state_add_reg(rstate, EVERGREEN_GROUP_CONTEXT,
221 R_028430_DB_STENCILREFMASK, stencil_ref_mask,
222 0xFFFFFFFF & C_028430_STENCILREF, NULL);
223 r600_pipe_state_add_reg(rstate, EVERGREEN_GROUP_CONTEXT,
224 R_028434_DB_STENCILREFMASK_BF, stencil_ref_mask_bf,
225 0xFFFFFFFF & C_028434_STENCILREF_BF, NULL);
226 r600_pipe_state_add_reg(rstate, EVERGREEN_GROUP_CONTEXT, R_028438_SX_ALPHA_REF, alpha_ref, 0xFFFFFFFF, NULL);
227 r600_pipe_state_add_reg(rstate, EVERGREEN_GROUP_CONTEXT, R_0286DC_SPI_FOG_CNTL, 0x00000000, 0xFFFFFFFF, NULL);
228 r600_pipe_state_add_reg(rstate, EVERGREEN_GROUP_CONTEXT, R_028800_DB_DEPTH_CONTROL, db_depth_control, 0xFFFFFFFF, NULL);
229 r600_pipe_state_add_reg(rstate, EVERGREEN_GROUP_CONTEXT, R_02880C_DB_SHADER_CONTROL, db_shader_control, 0xFFFFFFBE, NULL);
230 r600_pipe_state_add_reg(rstate, EVERGREEN_GROUP_CONTEXT, R_028000_DB_RENDER_CONTROL, db_render_control, 0xFFFFFFFF, NULL);
231 r600_pipe_state_add_reg(rstate, EVERGREEN_GROUP_CONTEXT, R_02800C_DB_RENDER_OVERRIDE, db_render_override, 0xFFFFFFFF, NULL);
232 r600_pipe_state_add_reg(rstate, EVERGREEN_GROUP_CONTEXT, R_028AC0_DB_SRESULTS_COMPARE_STATE0, 0x0, 0xFFFFFFFF, NULL);
233 r600_pipe_state_add_reg(rstate, EVERGREEN_GROUP_CONTEXT, R_028AC4_DB_SRESULTS_COMPARE_STATE1, 0x0, 0xFFFFFFFF, NULL);
234 r600_pipe_state_add_reg(rstate, EVERGREEN_GROUP_CONTEXT, R_028AC8_DB_PRELOAD_CONTROL, 0x0, 0xFFFFFFFF, NULL);
235 r600_pipe_state_add_reg(rstate, EVERGREEN_GROUP_CONTEXT, R_028B70_DB_ALPHA_TO_MASK, 0x0000AA00, 0xFFFFFFFF, NULL);
236
237 return rstate;
238 }
239
240 static void *evergreen_create_rs_state(struct pipe_context *ctx,
241 const struct pipe_rasterizer_state *state)
242 {
243 struct r600_pipe_rasterizer *rs = CALLOC_STRUCT(r600_pipe_rasterizer);
244 struct r600_pipe_state *rstate;
245 float offset_units = 0, offset_scale = 0;
246 unsigned offset_db_fmt_cntl = 0;
247 unsigned tmp;
248 unsigned prov_vtx = 1;
249
250 if (rs == NULL) {
251 return NULL;
252 }
253
254 rstate = &rs->rstate;
255 rs->flatshade = state->flatshade;
256 rs->sprite_coord_enable = state->sprite_coord_enable;
257
258 rstate->id = R600_PIPE_STATE_RASTERIZER;
259 if (state->flatshade_first)
260 prov_vtx = 0;
261 tmp = 0x00000001;
262 if (state->sprite_coord_enable) {
263 tmp |= S_0286D4_PNT_SPRITE_ENA(1) |
264 S_0286D4_PNT_SPRITE_OVRD_X(2) |
265 S_0286D4_PNT_SPRITE_OVRD_Y(3) |
266 S_0286D4_PNT_SPRITE_OVRD_Z(0) |
267 S_0286D4_PNT_SPRITE_OVRD_W(1);
268 if (state->sprite_coord_mode != PIPE_SPRITE_COORD_UPPER_LEFT) {
269 tmp |= S_0286D4_PNT_SPRITE_TOP_1(1);
270 }
271 }
272 r600_pipe_state_add_reg(rstate, EVERGREEN_GROUP_CONTEXT, R_0286D4_SPI_INTERP_CONTROL_0, tmp, 0xFFFFFFFF, NULL);
273
274 r600_pipe_state_add_reg(rstate, EVERGREEN_GROUP_CONTEXT, R_028814_PA_SU_SC_MODE_CNTL,
275 S_028814_PROVOKING_VTX_LAST(prov_vtx) |
276 S_028814_CULL_FRONT((state->cull_face & PIPE_FACE_FRONT) ? 1 : 0) |
277 S_028814_CULL_BACK((state->cull_face & PIPE_FACE_BACK) ? 1 : 0) |
278 S_028814_FACE(!state->front_ccw) |
279 S_028814_POLY_OFFSET_FRONT_ENABLE(state->offset_tri) |
280 S_028814_POLY_OFFSET_BACK_ENABLE(state->offset_tri) |
281 S_028814_POLY_OFFSET_PARA_ENABLE(state->offset_tri), 0xFFFFFFFF, NULL);
282 r600_pipe_state_add_reg(rstate, EVERGREEN_GROUP_CONTEXT, R_02881C_PA_CL_VS_OUT_CNTL,
283 S_02881C_USE_VTX_POINT_SIZE(state->point_size_per_vertex) |
284 S_02881C_VS_OUT_MISC_VEC_ENA(state->point_size_per_vertex), 0xFFFFFFFF, NULL);
285 r600_pipe_state_add_reg(rstate, EVERGREEN_GROUP_CONTEXT, R_028820_PA_CL_NANINF_CNTL, 0x00000000, 0xFFFFFFFF, NULL);
286 /* point size 12.4 fixed point */
287 tmp = (unsigned)(state->point_size * 8.0);
288 r600_pipe_state_add_reg(rstate, EVERGREEN_GROUP_CONTEXT, R_028A00_PA_SU_POINT_SIZE, S_028A00_HEIGHT(tmp) | S_028A00_WIDTH(tmp), 0xFFFFFFFF, NULL);
289 r600_pipe_state_add_reg(rstate, EVERGREEN_GROUP_CONTEXT, R_028A04_PA_SU_POINT_MINMAX, 0x80000000, 0xFFFFFFFF, NULL);
290 r600_pipe_state_add_reg(rstate, EVERGREEN_GROUP_CONTEXT, R_028A08_PA_SU_LINE_CNTL, 0x00000008, 0xFFFFFFFF, NULL);
291 r600_pipe_state_add_reg(rstate, EVERGREEN_GROUP_CONTEXT, R_028C00_PA_SC_LINE_CNTL, 0x00000400, 0xFFFFFFFF, NULL);
292 r600_pipe_state_add_reg(rstate, EVERGREEN_GROUP_CONTEXT, R_028C0C_PA_CL_GB_VERT_CLIP_ADJ, 0x3F800000, 0xFFFFFFFF, NULL);
293 r600_pipe_state_add_reg(rstate, EVERGREEN_GROUP_CONTEXT, R_028C10_PA_CL_GB_VERT_DISC_ADJ, 0x3F800000, 0xFFFFFFFF, NULL);
294 r600_pipe_state_add_reg(rstate, EVERGREEN_GROUP_CONTEXT, R_028C14_PA_CL_GB_HORZ_CLIP_ADJ, 0x3F800000, 0xFFFFFFFF, NULL);
295 r600_pipe_state_add_reg(rstate, EVERGREEN_GROUP_CONTEXT, R_028C18_PA_CL_GB_HORZ_DISC_ADJ, 0x3F800000, 0xFFFFFFFF, NULL);
296 r600_pipe_state_add_reg(rstate, EVERGREEN_GROUP_CONTEXT, R_028B78_PA_SU_POLY_OFFSET_DB_FMT_CNTL, offset_db_fmt_cntl, 0xFFFFFFFF, NULL);
297 r600_pipe_state_add_reg(rstate, EVERGREEN_GROUP_CONTEXT, R_028B80_PA_SU_POLY_OFFSET_FRONT_SCALE, fui(offset_scale), 0xFFFFFFFF, NULL);
298 r600_pipe_state_add_reg(rstate, EVERGREEN_GROUP_CONTEXT, R_028B84_PA_SU_POLY_OFFSET_FRONT_OFFSET, fui(offset_units), 0xFFFFFFFF, NULL);
299 r600_pipe_state_add_reg(rstate, EVERGREEN_GROUP_CONTEXT, R_028B88_PA_SU_POLY_OFFSET_BACK_SCALE, fui(offset_scale), 0xFFFFFFFF, NULL);
300 r600_pipe_state_add_reg(rstate, EVERGREEN_GROUP_CONTEXT, R_028B8C_PA_SU_POLY_OFFSET_BACK_OFFSET, fui(offset_units), 0xFFFFFFFF, NULL);
301 r600_pipe_state_add_reg(rstate, EVERGREEN_GROUP_CONTEXT, R_028B7C_PA_SU_POLY_OFFSET_CLAMP, 0x0, 0xFFFFFFFF, NULL);
302 r600_pipe_state_add_reg(rstate, EVERGREEN_GROUP_CONTEXT, R_028C08_PA_SU_VTX_CNTL, 0x00000005, 0xFFFFFFFF, NULL);
303 return rstate;
304 }
305
306 static void evergreen_bind_rs_state(struct pipe_context *ctx, void *state)
307 {
308 struct r600_pipe_rasterizer *rs = (struct r600_pipe_rasterizer *)state;
309 struct r600_pipe_context *rctx = (struct r600_pipe_context *)ctx;
310
311 if (state == NULL)
312 return;
313
314 if (rctx->flatshade != rs->flatshade) {
315 // rctx->ps_rebuild = TRUE;
316 }
317 if (rctx->sprite_coord_enable != rs->sprite_coord_enable) {
318 // rctx->ps_rebuild = TRUE;
319 }
320 rctx->flatshade = rs->flatshade;
321 rctx->sprite_coord_enable = rs->sprite_coord_enable;
322
323 rctx->states[rs->rstate.id] = &rs->rstate;
324 r600_context_pipe_state_set(&rctx->ctx, &rs->rstate);
325 }
326
327 static void evergreen_delete_rs_state(struct pipe_context *ctx, void *state)
328 {
329 struct r600_pipe_context *rctx = (struct r600_pipe_context *)ctx;
330 struct r600_pipe_rasterizer *rs = (struct r600_pipe_rasterizer *)state;
331
332 if (rctx->states[rs->rstate.id] == &rs->rstate) {
333 rctx->states[rs->rstate.id] = NULL;
334 }
335 free(rs);
336 }
337
338 static void *evergreen_create_sampler_state(struct pipe_context *ctx,
339 const struct pipe_sampler_state *state)
340 {
341 struct r600_pipe_state *rstate = CALLOC_STRUCT(r600_pipe_state);
342 union util_color uc;
343
344 if (rstate == NULL) {
345 return NULL;
346 }
347
348 rstate->id = R600_PIPE_STATE_SAMPLER;
349 util_pack_color(state->border_color, PIPE_FORMAT_B8G8R8A8_UNORM, &uc);
350 r600_pipe_state_add_reg(rstate, EVERGREEN_GROUP_SAMPLER, R_03C000_SQ_TEX_SAMPLER_WORD0_0,
351 S_03C000_CLAMP_X(r600_tex_wrap(state->wrap_s)) |
352 S_03C000_CLAMP_Y(r600_tex_wrap(state->wrap_t)) |
353 S_03C000_CLAMP_Z(r600_tex_wrap(state->wrap_r)) |
354 S_03C000_XY_MAG_FILTER(r600_tex_filter(state->mag_img_filter)) |
355 S_03C000_XY_MIN_FILTER(r600_tex_filter(state->min_img_filter)) |
356 S_03C000_MIP_FILTER(r600_tex_mipfilter(state->min_mip_filter)) |
357 S_03C000_DEPTH_COMPARE_FUNCTION(r600_tex_compare(state->compare_func)) |
358 S_03C000_BORDER_COLOR_TYPE(uc.ui ? V_03C000_SQ_TEX_BORDER_COLOR_REGISTER : 0), 0xFFFFFFFF, NULL);
359 /* FIXME LOD it depends on texture base level ... */
360 r600_pipe_state_add_reg(rstate, EVERGREEN_GROUP_SAMPLER, R_03C004_SQ_TEX_SAMPLER_WORD1_0,
361 S_03C004_MIN_LOD(S_FIXED(CLAMP(state->min_lod, 0, 15), 6)) |
362 S_03C004_MAX_LOD(S_FIXED(CLAMP(state->max_lod, 0, 15), 6)),
363 0xFFFFFFFF, NULL);
364 r600_pipe_state_add_reg(rstate, EVERGREEN_GROUP_SAMPLER, R_03C008_SQ_TEX_SAMPLER_WORD2_0,
365 S_03C008_LOD_BIAS(S_FIXED(CLAMP(state->lod_bias, -16, 16), 6)) |
366 S_03C008_TYPE(1),
367 0xFFFFFFFF, NULL);
368
369 if (uc.ui) {
370 /* TODO border color */
371 }
372 return rstate;
373 }
374
375 static void *evergreen_create_vertex_elements(struct pipe_context *ctx,
376 unsigned count,
377 const struct pipe_vertex_element *elements)
378 {
379 struct r600_vertex_element *v = CALLOC_STRUCT(r600_vertex_element);
380
381 assert(count < 32);
382 v->count = count;
383 v->refcount = 1;
384 memcpy(v->elements, elements, count * sizeof(struct pipe_vertex_element));
385 return v;
386 }
387
388 static void evergreen_sampler_view_destroy(struct pipe_context *ctx,
389 struct pipe_sampler_view *state)
390 {
391 struct r600_pipe_sampler_view *resource = (struct r600_pipe_sampler_view *)state;
392
393 pipe_resource_reference(&state->texture, NULL);
394 FREE(resource);
395 }
396
397 static struct pipe_sampler_view *evergreen_create_sampler_view(struct pipe_context *ctx,
398 struct pipe_resource *texture,
399 const struct pipe_sampler_view *state)
400 {
401 struct r600_pipe_sampler_view *resource = CALLOC_STRUCT(r600_pipe_sampler_view);
402 struct r600_pipe_state *rstate;
403 const struct util_format_description *desc;
404 struct r600_resource_texture *tmp;
405 struct r600_resource *rbuffer;
406 unsigned format;
407 uint32_t word4 = 0, yuv_format = 0, pitch = 0;
408 unsigned char swizzle[4];
409 struct radeon_ws_bo *bo[2];
410
411 if (resource == NULL)
412 return NULL;
413 rstate = &resource->state;
414
415 /* initialize base object */
416 resource->base = *state;
417 resource->base.texture = NULL;
418 pipe_reference(NULL, &texture->reference);
419 resource->base.texture = texture;
420 resource->base.reference.count = 1;
421 resource->base.context = ctx;
422
423 swizzle[0] = state->swizzle_r;
424 swizzle[1] = state->swizzle_g;
425 swizzle[2] = state->swizzle_b;
426 swizzle[3] = state->swizzle_a;
427 format = r600_translate_texformat(texture->format,
428 swizzle,
429 &word4, &yuv_format);
430 if (format == ~0) {
431 format = 0;
432 }
433 desc = util_format_description(texture->format);
434 if (desc == NULL) {
435 R600_ERR("unknow format %d\n", texture->format);
436 }
437 tmp = (struct r600_resource_texture*)texture;
438 rbuffer = &tmp->resource;
439 bo[0] = rbuffer->bo;
440 bo[1] = rbuffer->bo;
441 /* FIXME depth texture decompression */
442 if (tmp->depth) {
443 #if 0
444 r = evergreen_texture_from_depth(ctx, tmp, view->first_level);
445 if (r) {
446 return;
447 }
448 bo[0] = radeon_ws_bo_incref(rscreen->rw, tmp->uncompressed);
449 bo[1] = radeon_ws_bo_incref(rscreen->rw, tmp->uncompressed);
450 #endif
451 }
452 pitch = align(tmp->pitch[0] / tmp->bpt, 8);
453
454 /* FIXME properly handle first level != 0 */
455 r600_pipe_state_add_reg(rstate, EVERGREEN_GROUP_RESOURCE, R_030000_RESOURCE0_WORD0,
456 S_030000_DIM(r600_tex_dim(texture->target)) |
457 S_030000_PITCH((pitch / 8) - 1) |
458 S_030000_TEX_WIDTH(texture->width0 - 1), 0xFFFFFFFF, NULL);
459 r600_pipe_state_add_reg(rstate, EVERGREEN_GROUP_RESOURCE, R_030004_RESOURCE0_WORD1,
460 S_030004_TEX_HEIGHT(texture->height0 - 1) |
461 S_030004_TEX_DEPTH(texture->depth0 - 1),
462 0xFFFFFFFF, NULL);
463 r600_pipe_state_add_reg(rstate, EVERGREEN_GROUP_RESOURCE, R_030008_RESOURCE0_WORD2,
464 tmp->offset[0] >> 8, 0xFFFFFFFF, bo[0]);
465 r600_pipe_state_add_reg(rstate, EVERGREEN_GROUP_RESOURCE, R_03000C_RESOURCE0_WORD3,
466 tmp->offset[1] >> 8, 0xFFFFFFFF, bo[1]);
467 r600_pipe_state_add_reg(rstate, EVERGREEN_GROUP_RESOURCE, R_030010_RESOURCE0_WORD4,
468 word4 | S_030010_NUM_FORMAT_ALL(V_030010_SQ_NUM_FORMAT_NORM) |
469 S_030010_SRF_MODE_ALL(V_030010_SFR_MODE_NO_ZERO) |
470 S_030010_REQUEST_SIZE(1) |
471 S_030010_BASE_LEVEL(state->first_level), 0xFFFFFFFF, NULL);
472 r600_pipe_state_add_reg(rstate, EVERGREEN_GROUP_RESOURCE, R_030014_RESOURCE0_WORD5,
473 S_030014_LAST_LEVEL(state->last_level) |
474 S_030014_BASE_ARRAY(0) |
475 S_030014_LAST_ARRAY(0), 0xffffffff, NULL);
476 r600_pipe_state_add_reg(rstate, EVERGREEN_GROUP_RESOURCE, R_030018_RESOURCE0_WORD6, 0x0, 0xFFFFFFFF, NULL);
477 r600_pipe_state_add_reg(rstate, EVERGREEN_GROUP_RESOURCE, R_03001C_RESOURCE0_WORD7,
478 S_03001C_DATA_FORMAT(format) |
479 S_03001C_TYPE(V_03001C_SQ_TEX_VTX_VALID_TEXTURE), 0xFFFFFFFF, NULL);
480
481 return &resource->base;
482 }
483
484 static void evergreen_set_vs_sampler_view(struct pipe_context *ctx, unsigned count,
485 struct pipe_sampler_view **views)
486 {
487 /* TODO */
488 assert(1);
489 }
490
491 static void evergreen_set_ps_sampler_view(struct pipe_context *ctx, unsigned count,
492 struct pipe_sampler_view **views)
493 {
494 struct r600_pipe_context *rctx = (struct r600_pipe_context *)ctx;
495 struct r600_pipe_sampler_view **resource = (struct r600_pipe_sampler_view **)views;
496
497 for (int i = 0; i < count; i++) {
498 if (resource[i]) {
499 r600_context_pipe_state_set_ps_resource(&rctx->ctx, &resource[i]->state, i);
500 }
501 }
502 }
503
504 static void evergreen_bind_state(struct pipe_context *ctx, void *state)
505 {
506 struct r600_pipe_context *rctx = (struct r600_pipe_context *)ctx;
507 struct r600_pipe_state *rstate = (struct r600_pipe_state *)state;
508
509 if (state == NULL)
510 return;
511 rctx->states[rstate->id] = rstate;
512 r600_context_pipe_state_set(&rctx->ctx, rstate);
513 }
514
515 static void evergreen_bind_ps_sampler(struct pipe_context *ctx, unsigned count, void **states)
516 {
517 struct r600_pipe_context *rctx = (struct r600_pipe_context *)ctx;
518 struct r600_pipe_state **rstates = (struct r600_pipe_state **)states;
519
520 for (int i = 0; i < count; i++) {
521 r600_context_pipe_state_set_ps_sampler(&rctx->ctx, rstates[i], i);
522 }
523 }
524
525 static void evergreen_bind_vs_sampler(struct pipe_context *ctx, unsigned count, void **states)
526 {
527 struct r600_pipe_context *rctx = (struct r600_pipe_context *)ctx;
528 struct r600_pipe_state **rstates = (struct r600_pipe_state **)states;
529
530 /* TODO implement */
531 for (int i = 0; i < count; i++) {
532 r600_context_pipe_state_set_vs_sampler(&rctx->ctx, rstates[i], i);
533 }
534 }
535
536 static void evergreen_delete_state(struct pipe_context *ctx, void *state)
537 {
538 struct r600_pipe_context *rctx = (struct r600_pipe_context *)ctx;
539 struct r600_pipe_state *rstate = (struct r600_pipe_state *)state;
540
541 if (rctx->states[rstate->id] == rstate) {
542 rctx->states[rstate->id] = NULL;
543 }
544 for (int i = 0; i < rstate->nregs; i++) {
545 radeon_ws_bo_reference(rctx->radeon, &rstate->regs[i].bo, NULL);
546 }
547 free(rstate);
548 }
549
550 static void evergreen_delete_vertex_element(struct pipe_context *ctx, void *state)
551 {
552 struct r600_vertex_element *v = (struct r600_vertex_element*)state;
553
554 if (v == NULL)
555 return;
556 if (--v->refcount)
557 return;
558 free(v);
559 }
560
561 static void evergreen_set_clip_state(struct pipe_context *ctx,
562 const struct pipe_clip_state *state)
563 {
564 struct r600_pipe_context *rctx = (struct r600_pipe_context *)ctx;
565 struct r600_pipe_state *rstate = CALLOC_STRUCT(r600_pipe_state);
566
567 if (rstate == NULL)
568 return;
569
570 rctx->clip = *state;
571 rstate->id = R600_PIPE_STATE_CLIP;
572 for (int i = 0; i < state->nr; i++) {
573 r600_pipe_state_add_reg(rstate, EVERGREEN_GROUP_CONTEXT,
574 R_0285BC_PA_CL_UCP0_X + i * 4,
575 fui(state->ucp[i][0]), 0xFFFFFFFF, NULL);
576 r600_pipe_state_add_reg(rstate, EVERGREEN_GROUP_CONTEXT,
577 R_0285C0_PA_CL_UCP0_Y + i * 4,
578 fui(state->ucp[i][1]) , 0xFFFFFFFF, NULL);
579 r600_pipe_state_add_reg(rstate, EVERGREEN_GROUP_CONTEXT,
580 R_0285C4_PA_CL_UCP0_Z + i * 4,
581 fui(state->ucp[i][2]), 0xFFFFFFFF, NULL);
582 r600_pipe_state_add_reg(rstate, EVERGREEN_GROUP_CONTEXT,
583 R_0285C8_PA_CL_UCP0_W + i * 4,
584 fui(state->ucp[i][3]), 0xFFFFFFFF, NULL);
585 }
586 r600_pipe_state_add_reg(rstate, EVERGREEN_GROUP_CONTEXT, R_028810_PA_CL_CLIP_CNTL,
587 S_028810_PS_UCP_MODE(3) | ((1 << state->nr) - 1) |
588 S_028810_ZCLIP_NEAR_DISABLE(state->depth_clamp) |
589 S_028810_ZCLIP_FAR_DISABLE(state->depth_clamp), 0xFFFFFFFF, NULL);
590
591 free(rctx->states[R600_PIPE_STATE_CLIP]);
592 rctx->states[R600_PIPE_STATE_CLIP] = rstate;
593 r600_context_pipe_state_set(&rctx->ctx, rstate);
594 }
595
596 static void evergreen_bind_vertex_elements(struct pipe_context *ctx, void *state)
597 {
598 struct r600_pipe_context *rctx = (struct r600_pipe_context *)ctx;
599 struct r600_vertex_element *v = (struct r600_vertex_element*)state;
600
601 evergreen_delete_vertex_element(ctx, rctx->vertex_elements);
602 rctx->vertex_elements = v;
603 if (v) {
604 v->refcount++;
605 // rctx->vs_rebuild = TRUE;
606 }
607 }
608
609 static void evergreen_set_polygon_stipple(struct pipe_context *ctx,
610 const struct pipe_poly_stipple *state)
611 {
612 }
613
614 static void evergreen_set_sample_mask(struct pipe_context *pipe, unsigned sample_mask)
615 {
616 }
617
618 static void evergreen_set_scissor_state(struct pipe_context *ctx,
619 const struct pipe_scissor_state *state)
620 {
621 struct r600_pipe_context *rctx = (struct r600_pipe_context *)ctx;
622 struct r600_pipe_state *rstate = CALLOC_STRUCT(r600_pipe_state);
623 u32 tl, br;
624
625 if (rstate == NULL)
626 return;
627
628 rstate->id = R600_PIPE_STATE_SCISSOR;
629 tl = S_028240_TL_X(state->minx) | S_028240_TL_Y(state->miny);
630 br = S_028244_BR_X(state->maxx) | S_028244_BR_Y(state->maxy);
631 r600_pipe_state_add_reg(rstate, EVERGREEN_GROUP_CONTEXT,
632 R_028030_PA_SC_SCREEN_SCISSOR_TL, tl,
633 0xFFFFFFFF, NULL);
634 r600_pipe_state_add_reg(rstate, EVERGREEN_GROUP_CONTEXT,
635 R_028034_PA_SC_SCREEN_SCISSOR_BR, br,
636 0xFFFFFFFF, NULL);
637 r600_pipe_state_add_reg(rstate, EVERGREEN_GROUP_CONTEXT,
638 R_028204_PA_SC_WINDOW_SCISSOR_TL, tl,
639 0xFFFFFFFF, NULL);
640 r600_pipe_state_add_reg(rstate, EVERGREEN_GROUP_CONTEXT,
641 R_028208_PA_SC_WINDOW_SCISSOR_BR, br,
642 0xFFFFFFFF, NULL);
643 r600_pipe_state_add_reg(rstate, EVERGREEN_GROUP_CONTEXT,
644 R_028210_PA_SC_CLIPRECT_0_TL, tl,
645 0xFFFFFFFF, NULL);
646 r600_pipe_state_add_reg(rstate, EVERGREEN_GROUP_CONTEXT,
647 R_028214_PA_SC_CLIPRECT_0_BR, br,
648 0xFFFFFFFF, NULL);
649 r600_pipe_state_add_reg(rstate, EVERGREEN_GROUP_CONTEXT,
650 R_028218_PA_SC_CLIPRECT_1_TL, tl,
651 0xFFFFFFFF, NULL);
652 r600_pipe_state_add_reg(rstate, EVERGREEN_GROUP_CONTEXT,
653 R_02821C_PA_SC_CLIPRECT_1_BR, br,
654 0xFFFFFFFF, NULL);
655 r600_pipe_state_add_reg(rstate, EVERGREEN_GROUP_CONTEXT,
656 R_028220_PA_SC_CLIPRECT_2_TL, tl,
657 0xFFFFFFFF, NULL);
658 r600_pipe_state_add_reg(rstate, EVERGREEN_GROUP_CONTEXT,
659 R_028224_PA_SC_CLIPRECT_2_BR, br,
660 0xFFFFFFFF, NULL);
661 r600_pipe_state_add_reg(rstate, EVERGREEN_GROUP_CONTEXT,
662 R_028228_PA_SC_CLIPRECT_3_TL, tl,
663 0xFFFFFFFF, NULL);
664 r600_pipe_state_add_reg(rstate, EVERGREEN_GROUP_CONTEXT,
665 R_02822C_PA_SC_CLIPRECT_3_BR, br,
666 0xFFFFFFFF, NULL);
667 r600_pipe_state_add_reg(rstate, EVERGREEN_GROUP_CONTEXT,
668 R_028200_PA_SC_WINDOW_OFFSET, 0x00000000,
669 0xFFFFFFFF, NULL);
670 r600_pipe_state_add_reg(rstate, EVERGREEN_GROUP_CONTEXT,
671 R_02820C_PA_SC_CLIPRECT_RULE, 0x0000FFFF,
672 0xFFFFFFFF, NULL);
673 r600_pipe_state_add_reg(rstate, EVERGREEN_GROUP_CONTEXT,
674 R_028230_PA_SC_EDGERULE, 0xAAAAAAAA,
675 0xFFFFFFFF, NULL);
676
677 free(rctx->states[R600_PIPE_STATE_SCISSOR]);
678 rctx->states[R600_PIPE_STATE_SCISSOR] = rstate;
679 r600_context_pipe_state_set(&rctx->ctx, rstate);
680 }
681
682 static void evergreen_set_stencil_ref(struct pipe_context *ctx,
683 const struct pipe_stencil_ref *state)
684 {
685 struct r600_pipe_context *rctx = (struct r600_pipe_context *)ctx;
686 struct r600_pipe_state *rstate = CALLOC_STRUCT(r600_pipe_state);
687 u32 tmp;
688
689 if (rstate == NULL)
690 return;
691
692 rctx->stencil_ref = *state;
693 rstate->id = R600_PIPE_STATE_STENCIL_REF;
694 tmp = S_028430_STENCILREF(state->ref_value[0]);
695 r600_pipe_state_add_reg(rstate, EVERGREEN_GROUP_CONTEXT,
696 R_028430_DB_STENCILREFMASK, tmp,
697 ~C_028430_STENCILREF, NULL);
698 tmp = S_028434_STENCILREF_BF(state->ref_value[1]);
699 r600_pipe_state_add_reg(rstate, EVERGREEN_GROUP_CONTEXT,
700 R_028434_DB_STENCILREFMASK_BF, tmp,
701 ~C_028434_STENCILREF_BF, NULL);
702
703 free(rctx->states[R600_PIPE_STATE_STENCIL_REF]);
704 rctx->states[R600_PIPE_STATE_STENCIL_REF] = rstate;
705 r600_context_pipe_state_set(&rctx->ctx, rstate);
706 }
707
708 static void evergreen_set_viewport_state(struct pipe_context *ctx,
709 const struct pipe_viewport_state *state)
710 {
711 struct r600_pipe_context *rctx = (struct r600_pipe_context *)ctx;
712 struct r600_pipe_state *rstate = CALLOC_STRUCT(r600_pipe_state);
713
714 if (rstate == NULL)
715 return;
716
717 rctx->viewport = *state;
718 rstate->id = R600_PIPE_STATE_VIEWPORT;
719 r600_pipe_state_add_reg(rstate, EVERGREEN_GROUP_CONTEXT, R_0282D0_PA_SC_VPORT_ZMIN_0, 0x00000000, 0xFFFFFFFF, NULL);
720 r600_pipe_state_add_reg(rstate, EVERGREEN_GROUP_CONTEXT, R_0282D4_PA_SC_VPORT_ZMAX_0, 0x3F800000, 0xFFFFFFFF, NULL);
721 r600_pipe_state_add_reg(rstate, EVERGREEN_GROUP_CONTEXT, R_02843C_PA_CL_VPORT_XSCALE_0, fui(state->scale[0]), 0xFFFFFFFF, NULL);
722 r600_pipe_state_add_reg(rstate, EVERGREEN_GROUP_CONTEXT, R_028444_PA_CL_VPORT_YSCALE_0, fui(state->scale[1]), 0xFFFFFFFF, NULL);
723 r600_pipe_state_add_reg(rstate, EVERGREEN_GROUP_CONTEXT, R_02844C_PA_CL_VPORT_ZSCALE_0, fui(state->scale[2]), 0xFFFFFFFF, NULL);
724 r600_pipe_state_add_reg(rstate, EVERGREEN_GROUP_CONTEXT, R_028440_PA_CL_VPORT_XOFFSET_0, fui(state->translate[0]), 0xFFFFFFFF, NULL);
725 r600_pipe_state_add_reg(rstate, EVERGREEN_GROUP_CONTEXT, R_028448_PA_CL_VPORT_YOFFSET_0, fui(state->translate[1]), 0xFFFFFFFF, NULL);
726 r600_pipe_state_add_reg(rstate, EVERGREEN_GROUP_CONTEXT, R_028450_PA_CL_VPORT_ZOFFSET_0, fui(state->translate[2]), 0xFFFFFFFF, NULL);
727 r600_pipe_state_add_reg(rstate, EVERGREEN_GROUP_CONTEXT, R_028818_PA_CL_VTE_CNTL, 0x0000043F, 0xFFFFFFFF, NULL);
728
729 free(rctx->states[R600_PIPE_STATE_VIEWPORT]);
730 rctx->states[R600_PIPE_STATE_VIEWPORT] = rstate;
731 r600_context_pipe_state_set(&rctx->ctx, rstate);
732 }
733
734 static void evergreen_cb(struct r600_pipe_context *rctx, struct r600_pipe_state *rstate,
735 const struct pipe_framebuffer_state *state, int cb)
736 {
737 struct r600_resource_texture *rtex;
738 struct r600_resource *rbuffer;
739 unsigned level = state->cbufs[cb]->level;
740 unsigned pitch, slice;
741 unsigned color_info;
742 unsigned format, swap, ntype;
743 const struct util_format_description *desc;
744 struct radeon_ws_bo *bo[3];
745
746 rtex = (struct r600_resource_texture*)state->cbufs[cb]->texture;
747 rbuffer = &rtex->resource;
748 bo[0] = rbuffer->bo;
749 bo[1] = rbuffer->bo;
750 bo[2] = rbuffer->bo;
751
752 pitch = (rtex->pitch[level] / rtex->bpt) / 8 - 1;
753 slice = (rtex->pitch[level] / rtex->bpt) * state->cbufs[cb]->height / 64 - 1;
754 ntype = 0;
755 desc = util_format_description(rtex->resource.base.b.format);
756 if (desc->colorspace == UTIL_FORMAT_COLORSPACE_SRGB)
757 ntype = V_028C70_NUMBER_SRGB;
758
759 format = r600_translate_colorformat(rtex->resource.base.b.format);
760 swap = r600_translate_colorswap(rtex->resource.base.b.format);
761 color_info = S_028C70_FORMAT(format) |
762 S_028C70_COMP_SWAP(swap) |
763 S_028C70_BLEND_CLAMP(1) |
764 S_028C70_SOURCE_FORMAT(1) |
765 S_028C70_NUMBER_TYPE(ntype);
766
767 /* FIXME handle enabling of CB beyond BASE8 which has different offset */
768 r600_pipe_state_add_reg(rstate, EVERGREEN_GROUP_CONTEXT,
769 R_028C60_CB_COLOR0_BASE + cb * 0x3C,
770 state->cbufs[cb]->offset >> 8, 0xFFFFFFFF, bo[0]);
771 r600_pipe_state_add_reg(rstate, EVERGREEN_GROUP_CONTEXT,
772 R_028C78_CB_COLOR0_DIM + cb * 0x3C,
773 0x0, 0xFFFFFFFF, NULL);
774 r600_pipe_state_add_reg(rstate, EVERGREEN_GROUP_CONTEXT,
775 R_028C70_CB_COLOR0_INFO + cb * 0x3C,
776 color_info, 0xFFFFFFFF, bo[0]);
777 r600_pipe_state_add_reg(rstate, EVERGREEN_GROUP_CONTEXT,
778 R_028C64_CB_COLOR0_PITCH + cb * 0x3C,
779 S_028C64_PITCH_TILE_MAX(pitch),
780 0xFFFFFFFF, NULL);
781 r600_pipe_state_add_reg(rstate, EVERGREEN_GROUP_CONTEXT,
782 R_028C68_CB_COLOR0_SLICE + cb * 0x3C,
783 S_028C68_SLICE_TILE_MAX(slice),
784 0xFFFFFFFF, NULL);
785 r600_pipe_state_add_reg(rstate, EVERGREEN_GROUP_CONTEXT,
786 R_028C6C_CB_COLOR0_VIEW + cb * 0x3C,
787 0x00000000, 0xFFFFFFFF, NULL);
788 r600_pipe_state_add_reg(rstate, EVERGREEN_GROUP_CONTEXT,
789 R_028C74_CB_COLOR0_ATTRIB + cb * 0x3C,
790 S_028C74_NON_DISP_TILING_ORDER(1),
791 0xFFFFFFFF, NULL);
792 }
793
794 static void evergreen_db(struct r600_pipe_context *rctx, struct r600_pipe_state *rstate,
795 const struct pipe_framebuffer_state *state)
796 {
797 struct r600_resource_texture *rtex;
798 struct r600_resource *rbuffer;
799 unsigned level;
800 unsigned pitch, slice, format;
801
802 if (state->zsbuf == NULL)
803 return;
804
805 rtex = (struct r600_resource_texture*)state->zsbuf->texture;
806 rtex->tiled = 1;
807 rtex->array_mode = 2;
808 rtex->tile_type = 1;
809 rtex->depth = 1;
810 rbuffer = &rtex->resource;
811
812 level = state->zsbuf->level;
813 pitch = (rtex->pitch[level] / rtex->bpt) / 8 - 1;
814 slice = (rtex->pitch[level] / rtex->bpt) * state->zsbuf->height / 64 - 1;
815 format = r600_translate_dbformat(state->zsbuf->texture->format);
816
817 r600_pipe_state_add_reg(rstate, EVERGREEN_GROUP_CONTEXT, R_028048_DB_Z_READ_BASE,
818 state->zsbuf->offset >> 8, 0xFFFFFFFF, rbuffer->bo);
819 r600_pipe_state_add_reg(rstate, EVERGREEN_GROUP_CONTEXT, R_028050_DB_Z_WRITE_BASE,
820 state->zsbuf->offset >> 8, 0xFFFFFFFF, rbuffer->bo);
821 // r600_pipe_state_add_reg(rstate, EVERGREEN_GROUP_CONTEXT, R_028014_DB_HTILE_DATA_BASE, state->zsbuf->offset >> 8, 0xFFFFFFFF, rbuffer->bo);
822 r600_pipe_state_add_reg(rstate, EVERGREEN_GROUP_CONTEXT, R_028008_DB_DEPTH_VIEW, 0x00000000, 0xFFFFFFFF, NULL);
823 r600_pipe_state_add_reg(rstate, EVERGREEN_GROUP_CONTEXT, R_028040_DB_Z_INFO,
824 S_028040_ARRAY_MODE(rtex->array_mode) | S_028040_FORMAT(format),
825 0xFFFFFFFF, rbuffer->bo);
826 r600_pipe_state_add_reg(rstate, EVERGREEN_GROUP_CONTEXT, R_028058_DB_DEPTH_SIZE,
827 S_028058_PITCH_TILE_MAX(pitch),
828 0xFFFFFFFF, NULL);
829 r600_pipe_state_add_reg(rstate, EVERGREEN_GROUP_CONTEXT, R_02805C_DB_DEPTH_SLICE,
830 S_02805C_SLICE_TILE_MAX(slice),
831 0xFFFFFFFF, NULL);
832 }
833
834 static void evergreen_set_framebuffer_state(struct pipe_context *ctx,
835 const struct pipe_framebuffer_state *state)
836 {
837 struct r600_pipe_context *rctx = (struct r600_pipe_context *)ctx;
838 struct r600_pipe_state *rstate = CALLOC_STRUCT(r600_pipe_state);
839 u32 shader_mask, tl, br, target_mask;
840
841 if (rstate == NULL)
842 return;
843
844 /* unreference old buffer and reference new one */
845 rstate->id = R600_PIPE_STATE_FRAMEBUFFER;
846 for (int i = 0; i < rctx->framebuffer.nr_cbufs; i++) {
847 pipe_surface_reference(&rctx->framebuffer.cbufs[i], NULL);
848 }
849 for (int i = 0; i < state->nr_cbufs; i++) {
850 pipe_surface_reference(&rctx->framebuffer.cbufs[i], state->cbufs[i]);
851 }
852 pipe_surface_reference(&rctx->framebuffer.zsbuf, state->zsbuf);
853 rctx->framebuffer = *state;
854
855 /* build states */
856 for (int i = 0; i < state->nr_cbufs; i++) {
857 evergreen_cb(rctx, rstate, state, i);
858 }
859 if (state->zsbuf) {
860 evergreen_db(rctx, rstate, state);
861 }
862
863 target_mask = 0x00000000;
864 target_mask = 0xFFFFFFFF;
865 shader_mask = 0;
866 for (int i = 0; i < state->nr_cbufs; i++) {
867 target_mask ^= 0xf << (i * 4);
868 shader_mask |= 0xf << (i * 4);
869 }
870 tl = S_028240_TL_X(0) | S_028240_TL_Y(0);
871 br = S_028244_BR_X(state->width) | S_028244_BR_Y(state->height);
872
873 r600_pipe_state_add_reg(rstate, EVERGREEN_GROUP_CONTEXT,
874 R_028240_PA_SC_GENERIC_SCISSOR_TL, tl,
875 0xFFFFFFFF, NULL);
876 r600_pipe_state_add_reg(rstate, EVERGREEN_GROUP_CONTEXT,
877 R_028244_PA_SC_GENERIC_SCISSOR_BR, br,
878 0xFFFFFFFF, NULL);
879 r600_pipe_state_add_reg(rstate, EVERGREEN_GROUP_CONTEXT,
880 R_028250_PA_SC_VPORT_SCISSOR_0_TL, tl,
881 0xFFFFFFFF, NULL);
882 r600_pipe_state_add_reg(rstate, EVERGREEN_GROUP_CONTEXT,
883 R_028254_PA_SC_VPORT_SCISSOR_0_BR, br,
884 0xFFFFFFFF, NULL);
885
886 r600_pipe_state_add_reg(rstate, EVERGREEN_GROUP_CONTEXT, R_028238_CB_TARGET_MASK,
887 0x00000000, target_mask, NULL);
888 r600_pipe_state_add_reg(rstate, EVERGREEN_GROUP_CONTEXT, R_02823C_CB_SHADER_MASK,
889 shader_mask, 0xFFFFFFFF, NULL);
890 r600_pipe_state_add_reg(rstate, EVERGREEN_GROUP_CONTEXT, R_028C04_PA_SC_AA_CONFIG,
891 0x00000000, 0xFFFFFFFF, NULL);
892 r600_pipe_state_add_reg(rstate, EVERGREEN_GROUP_CONTEXT, R_028C1C_PA_SC_AA_SAMPLE_LOCS_MCTX,
893 0x00000000, 0xFFFFFFFF, NULL);
894
895 free(rctx->states[R600_PIPE_STATE_FRAMEBUFFER]);
896 rctx->states[R600_PIPE_STATE_FRAMEBUFFER] = rstate;
897 r600_context_pipe_state_set(&rctx->ctx, rstate);
898 }
899
900 static void evergreen_set_index_buffer(struct pipe_context *ctx,
901 const struct pipe_index_buffer *ib)
902 {
903 struct r600_pipe_context *rctx = (struct r600_pipe_context *)ctx;
904
905 if (ib) {
906 pipe_resource_reference(&rctx->index_buffer.buffer, ib->buffer);
907 memcpy(&rctx->index_buffer, ib, sizeof(rctx->index_buffer));
908 } else {
909 pipe_resource_reference(&rctx->index_buffer.buffer, NULL);
910 memset(&rctx->index_buffer, 0, sizeof(rctx->index_buffer));
911 }
912
913 /* TODO make this more like a state */
914 }
915
916 static void evergreen_set_vertex_buffers(struct pipe_context *ctx, unsigned count,
917 const struct pipe_vertex_buffer *buffers)
918 {
919 struct r600_pipe_context *rctx = (struct r600_pipe_context *)ctx;
920
921 for (int i = 0; i < rctx->nvertex_buffer; i++) {
922 pipe_resource_reference(&rctx->vertex_buffer[i].buffer, NULL);
923 }
924 memcpy(rctx->vertex_buffer, buffers, sizeof(struct pipe_vertex_buffer) * count);
925 for (int i = 0; i < count; i++) {
926 rctx->vertex_buffer[i].buffer = NULL;
927 pipe_resource_reference(&rctx->vertex_buffer[i].buffer, buffers[i].buffer);
928 }
929 rctx->nvertex_buffer = count;
930 }
931
932 static void evergreen_set_constant_buffer(struct pipe_context *ctx, uint shader, uint index,
933 struct pipe_resource *buffer)
934 {
935 struct r600_pipe_context *rctx = (struct r600_pipe_context *)ctx;
936 struct r600_resource *rbuffer = (struct r600_resource*)buffer;
937
938 switch (shader) {
939 case PIPE_SHADER_VERTEX:
940 rctx->vs_const_buffer.nregs = 0;
941 r600_pipe_state_add_reg(&rctx->vs_const_buffer, EVERGREEN_GROUP_CONTEXT,
942 R_028180_ALU_CONST_BUFFER_SIZE_VS_0,
943 ALIGN_DIVUP(buffer->width0 >> 4, 16),
944 0xFFFFFFFF, NULL);
945 r600_pipe_state_add_reg(&rctx->vs_const_buffer, EVERGREEN_GROUP_CONTEXT,
946 R_028980_ALU_CONST_CACHE_VS_0,
947 0, 0xFFFFFFFF, rbuffer->bo);
948 r600_context_pipe_state_set(&rctx->ctx, &rctx->vs_const_buffer);
949 break;
950 case PIPE_SHADER_FRAGMENT:
951 rctx->ps_const_buffer.nregs = 0;
952 r600_pipe_state_add_reg(&rctx->ps_const_buffer, EVERGREEN_GROUP_CONTEXT,
953 R_028140_ALU_CONST_BUFFER_SIZE_PS_0,
954 ALIGN_DIVUP(buffer->width0 >> 4, 16),
955 0xFFFFFFFF, NULL);
956 r600_pipe_state_add_reg(&rctx->ps_const_buffer, EVERGREEN_GROUP_CONTEXT,
957 R_028940_ALU_CONST_CACHE_PS_0,
958 0, 0xFFFFFFFF, rbuffer->bo);
959 r600_context_pipe_state_set(&rctx->ctx, &rctx->ps_const_buffer);
960 break;
961 default:
962 R600_ERR("unsupported %d\n", shader);
963 return;
964 }
965 }
966
967 static void *evergreen_create_shader_state(struct pipe_context *ctx,
968 const struct pipe_shader_state *state)
969 {
970 struct r600_pipe_shader *shader = CALLOC_STRUCT(r600_pipe_shader);
971 int r;
972
973 shader->shader.use_mem_constant = TRUE;
974 r = r600_pipe_shader_create2(ctx, shader, state->tokens);
975 if (r) {
976 return NULL;
977 }
978 return shader;
979 }
980
981 static void evergreen_bind_ps_shader(struct pipe_context *ctx, void *state)
982 {
983 struct r600_pipe_context *rctx = (struct r600_pipe_context *)ctx;
984
985 /* TODO delete old shader */
986 rctx->ps_shader = (struct r600_pipe_shader *)state;
987 }
988
989 static void evergreen_bind_vs_shader(struct pipe_context *ctx, void *state)
990 {
991 struct r600_pipe_context *rctx = (struct r600_pipe_context *)ctx;
992
993 /* TODO delete old shader */
994 rctx->vs_shader = (struct r600_pipe_shader *)state;
995 }
996
997 static void evergreen_delete_ps_shader(struct pipe_context *ctx, void *state)
998 {
999 struct r600_pipe_context *rctx = (struct r600_pipe_context *)ctx;
1000 struct r600_pipe_shader *shader = (struct r600_pipe_shader *)state;
1001
1002 if (rctx->ps_shader == shader) {
1003 rctx->ps_shader = NULL;
1004 }
1005 /* TODO proper delete */
1006 free(shader);
1007 }
1008
1009 static void evergreen_delete_vs_shader(struct pipe_context *ctx, void *state)
1010 {
1011 struct r600_pipe_context *rctx = (struct r600_pipe_context *)ctx;
1012 struct r600_pipe_shader *shader = (struct r600_pipe_shader *)state;
1013
1014 if (rctx->vs_shader == shader) {
1015 rctx->vs_shader = NULL;
1016 }
1017 /* TODO proper delete */
1018 free(shader);
1019 }
1020
1021 void evergreen_init_state_functions2(struct r600_pipe_context *rctx)
1022 {
1023 rctx->context.create_blend_state = evergreen_create_blend_state;
1024 rctx->context.create_depth_stencil_alpha_state = evergreen_create_dsa_state;
1025 rctx->context.create_fs_state = evergreen_create_shader_state;
1026 rctx->context.create_rasterizer_state = evergreen_create_rs_state;
1027 rctx->context.create_sampler_state = evergreen_create_sampler_state;
1028 rctx->context.create_sampler_view = evergreen_create_sampler_view;
1029 rctx->context.create_vertex_elements_state = evergreen_create_vertex_elements;
1030 rctx->context.create_vs_state = evergreen_create_shader_state;
1031 rctx->context.bind_blend_state = evergreen_bind_blend_state;
1032 rctx->context.bind_depth_stencil_alpha_state = evergreen_bind_state;
1033 rctx->context.bind_fragment_sampler_states = evergreen_bind_ps_sampler;
1034 rctx->context.bind_fs_state = evergreen_bind_ps_shader;
1035 rctx->context.bind_rasterizer_state = evergreen_bind_rs_state;
1036 rctx->context.bind_vertex_elements_state = evergreen_bind_vertex_elements;
1037 rctx->context.bind_vertex_sampler_states = evergreen_bind_vs_sampler;
1038 rctx->context.bind_vs_state = evergreen_bind_vs_shader;
1039 rctx->context.delete_blend_state = evergreen_delete_state;
1040 rctx->context.delete_depth_stencil_alpha_state = evergreen_delete_state;
1041 rctx->context.delete_fs_state = evergreen_delete_ps_shader;
1042 rctx->context.delete_rasterizer_state = evergreen_delete_rs_state;
1043 rctx->context.delete_sampler_state = evergreen_delete_state;
1044 rctx->context.delete_vertex_elements_state = evergreen_delete_vertex_element;
1045 rctx->context.delete_vs_state = evergreen_delete_vs_shader;
1046 rctx->context.set_blend_color = evergreen_set_blend_color;
1047 rctx->context.set_clip_state = evergreen_set_clip_state;
1048 rctx->context.set_constant_buffer = evergreen_set_constant_buffer;
1049 rctx->context.set_fragment_sampler_views = evergreen_set_ps_sampler_view;
1050 rctx->context.set_framebuffer_state = evergreen_set_framebuffer_state;
1051 rctx->context.set_polygon_stipple = evergreen_set_polygon_stipple;
1052 rctx->context.set_sample_mask = evergreen_set_sample_mask;
1053 rctx->context.set_scissor_state = evergreen_set_scissor_state;
1054 rctx->context.set_stencil_ref = evergreen_set_stencil_ref;
1055 rctx->context.set_vertex_buffers = evergreen_set_vertex_buffers;
1056 rctx->context.set_index_buffer = evergreen_set_index_buffer;
1057 rctx->context.set_vertex_sampler_views = evergreen_set_vs_sampler_view;
1058 rctx->context.set_viewport_state = evergreen_set_viewport_state;
1059 rctx->context.sampler_view_destroy = evergreen_sampler_view_destroy;
1060 }
1061
1062 void evergreen_init_config2(struct r600_pipe_context *rctx)
1063 {
1064 struct r600_pipe_state *rstate = &rctx->config;
1065 int ps_prio;
1066 int vs_prio;
1067 int gs_prio;
1068 int es_prio;
1069 int hs_prio, cs_prio, ls_prio;
1070 int num_ps_gprs;
1071 int num_vs_gprs;
1072 int num_gs_gprs;
1073 int num_es_gprs;
1074 int num_hs_gprs;
1075 int num_ls_gprs;
1076 int num_temp_gprs;
1077 int num_ps_threads;
1078 int num_vs_threads;
1079 int num_gs_threads;
1080 int num_es_threads;
1081 int num_hs_threads;
1082 int num_ls_threads;
1083 int num_ps_stack_entries;
1084 int num_vs_stack_entries;
1085 int num_gs_stack_entries;
1086 int num_es_stack_entries;
1087 int num_hs_stack_entries;
1088 int num_ls_stack_entries;
1089 enum radeon_family family;
1090 unsigned tmp;
1091
1092 family = r600_get_family(rctx->radeon);
1093 ps_prio = 0;
1094 vs_prio = 1;
1095 gs_prio = 2;
1096 es_prio = 3;
1097 hs_prio = 0;
1098 ls_prio = 0;
1099 cs_prio = 0;
1100
1101 switch (family) {
1102 case CHIP_CEDAR:
1103 default:
1104 num_ps_gprs = 93;
1105 num_vs_gprs = 46;
1106 num_temp_gprs = 4;
1107 num_gs_gprs = 31;
1108 num_es_gprs = 31;
1109 num_hs_gprs = 23;
1110 num_ls_gprs = 23;
1111 num_ps_threads = 96;
1112 num_vs_threads = 16;
1113 num_gs_threads = 16;
1114 num_es_threads = 16;
1115 num_hs_threads = 16;
1116 num_ls_threads = 16;
1117 num_ps_stack_entries = 42;
1118 num_vs_stack_entries = 42;
1119 num_gs_stack_entries = 42;
1120 num_es_stack_entries = 42;
1121 num_hs_stack_entries = 42;
1122 num_ls_stack_entries = 42;
1123 break;
1124 case CHIP_REDWOOD:
1125 num_ps_gprs = 93;
1126 num_vs_gprs = 46;
1127 num_temp_gprs = 4;
1128 num_gs_gprs = 31;
1129 num_es_gprs = 31;
1130 num_hs_gprs = 23;
1131 num_ls_gprs = 23;
1132 num_ps_threads = 128;
1133 num_vs_threads = 20;
1134 num_gs_threads = 20;
1135 num_es_threads = 20;
1136 num_hs_threads = 20;
1137 num_ls_threads = 20;
1138 num_ps_stack_entries = 42;
1139 num_vs_stack_entries = 42;
1140 num_gs_stack_entries = 42;
1141 num_es_stack_entries = 42;
1142 num_hs_stack_entries = 42;
1143 num_ls_stack_entries = 42;
1144 break;
1145 case CHIP_JUNIPER:
1146 num_ps_gprs = 93;
1147 num_vs_gprs = 46;
1148 num_temp_gprs = 4;
1149 num_gs_gprs = 31;
1150 num_es_gprs = 31;
1151 num_hs_gprs = 23;
1152 num_ls_gprs = 23;
1153 num_ps_threads = 128;
1154 num_vs_threads = 20;
1155 num_gs_threads = 20;
1156 num_es_threads = 20;
1157 num_hs_threads = 20;
1158 num_ls_threads = 20;
1159 num_ps_stack_entries = 85;
1160 num_vs_stack_entries = 85;
1161 num_gs_stack_entries = 85;
1162 num_es_stack_entries = 85;
1163 num_hs_stack_entries = 85;
1164 num_ls_stack_entries = 85;
1165 break;
1166 case CHIP_CYPRESS:
1167 case CHIP_HEMLOCK:
1168 num_ps_gprs = 93;
1169 num_vs_gprs = 46;
1170 num_temp_gprs = 4;
1171 num_gs_gprs = 31;
1172 num_es_gprs = 31;
1173 num_hs_gprs = 23;
1174 num_ls_gprs = 23;
1175 num_ps_threads = 128;
1176 num_vs_threads = 20;
1177 num_gs_threads = 20;
1178 num_es_threads = 20;
1179 num_hs_threads = 20;
1180 num_ls_threads = 20;
1181 num_ps_stack_entries = 85;
1182 num_vs_stack_entries = 85;
1183 num_gs_stack_entries = 85;
1184 num_es_stack_entries = 85;
1185 num_hs_stack_entries = 85;
1186 num_ls_stack_entries = 85;
1187 break;
1188 }
1189
1190 tmp = 0x00000000;
1191 switch (family) {
1192 case CHIP_CEDAR:
1193 break;
1194 default:
1195 tmp |= S_008C00_VC_ENABLE(1);
1196 break;
1197 }
1198 tmp |= S_008C00_EXPORT_SRC_C(1);
1199 tmp |= S_008C00_CS_PRIO(cs_prio);
1200 tmp |= S_008C00_LS_PRIO(ls_prio);
1201 tmp |= S_008C00_HS_PRIO(hs_prio);
1202 tmp |= S_008C00_PS_PRIO(ps_prio);
1203 tmp |= S_008C00_VS_PRIO(vs_prio);
1204 tmp |= S_008C00_GS_PRIO(gs_prio);
1205 tmp |= S_008C00_ES_PRIO(es_prio);
1206 r600_pipe_state_add_reg(rstate, EVERGREEN_GROUP_CONFIG, R_008C00_SQ_CONFIG, tmp, 0xFFFFFFFF, NULL);
1207
1208 tmp = 0;
1209 tmp |= S_008C04_NUM_PS_GPRS(num_ps_gprs);
1210 tmp |= S_008C04_NUM_VS_GPRS(num_vs_gprs);
1211 tmp |= S_008C04_NUM_CLAUSE_TEMP_GPRS(num_temp_gprs);
1212 r600_pipe_state_add_reg(rstate, EVERGREEN_GROUP_CONFIG, R_008C04_SQ_GPR_RESOURCE_MGMT_1, tmp, 0xFFFFFFFF, NULL);
1213
1214 tmp = 0;
1215 tmp |= S_008C08_NUM_GS_GPRS(num_gs_gprs);
1216 tmp |= S_008C08_NUM_ES_GPRS(num_es_gprs);
1217 r600_pipe_state_add_reg(rstate, EVERGREEN_GROUP_CONFIG, R_008C08_SQ_GPR_RESOURCE_MGMT_2, tmp, 0xFFFFFFFF, NULL);
1218
1219 tmp = 0;
1220 tmp |= S_008C0C_NUM_HS_GPRS(num_hs_gprs);
1221 tmp |= S_008C0C_NUM_LS_GPRS(num_ls_gprs);
1222 r600_pipe_state_add_reg(rstate, EVERGREEN_GROUP_CONFIG, R_008C0C_SQ_GPR_RESOURCE_MGMT_3, tmp, 0xFFFFFFFF, NULL);
1223
1224 tmp = 0;
1225 tmp |= S_008C18_NUM_PS_THREADS(num_ps_threads);
1226 tmp |= S_008C18_NUM_VS_THREADS(num_vs_threads);
1227 tmp |= S_008C18_NUM_GS_THREADS(num_gs_threads);
1228 tmp |= S_008C18_NUM_ES_THREADS(num_es_threads);
1229 r600_pipe_state_add_reg(rstate, EVERGREEN_GROUP_CONFIG, R_008C18_SQ_THREAD_RESOURCE_MGMT_1, tmp, 0xFFFFFFFF, NULL);
1230
1231 tmp = 0;
1232 tmp |= S_008C1C_NUM_HS_THREADS(num_hs_threads);
1233 tmp |= S_008C1C_NUM_LS_THREADS(num_ls_threads);
1234 r600_pipe_state_add_reg(rstate, EVERGREEN_GROUP_CONFIG, R_008C1C_SQ_THREAD_RESOURCE_MGMT_2, tmp, 0xFFFFFFFF, NULL);
1235
1236 tmp = 0;
1237 tmp |= S_008C20_NUM_PS_STACK_ENTRIES(num_ps_stack_entries);
1238 tmp |= S_008C20_NUM_VS_STACK_ENTRIES(num_vs_stack_entries);
1239 r600_pipe_state_add_reg(rstate, EVERGREEN_GROUP_CONFIG, R_008C20_SQ_STACK_RESOURCE_MGMT_1, tmp, 0xFFFFFFFF, NULL);
1240
1241 tmp = 0;
1242 tmp |= S_008C24_NUM_GS_STACK_ENTRIES(num_gs_stack_entries);
1243 tmp |= S_008C24_NUM_ES_STACK_ENTRIES(num_es_stack_entries);
1244 r600_pipe_state_add_reg(rstate, EVERGREEN_GROUP_CONFIG, R_008C24_SQ_STACK_RESOURCE_MGMT_2, tmp, 0xFFFFFFFF, NULL);
1245
1246 tmp = 0;
1247 tmp |= S_008C28_NUM_HS_STACK_ENTRIES(num_hs_stack_entries);
1248 tmp |= S_008C28_NUM_LS_STACK_ENTRIES(num_ls_stack_entries);
1249 r600_pipe_state_add_reg(rstate, EVERGREEN_GROUP_CONFIG, R_008C28_SQ_STACK_RESOURCE_MGMT_3, tmp, 0xFFFFFFFF, NULL);
1250
1251 r600_pipe_state_add_reg(rstate, EVERGREEN_GROUP_CONFIG, R_009100_SPI_CONFIG_CNTL, 0x0, 0xFFFFFFFF, NULL);
1252 r600_pipe_state_add_reg(rstate, EVERGREEN_GROUP_CONFIG, R_00913C_SPI_CONFIG_CNTL_1, S_00913C_VTX_DONE_DELAY(4), 0xFFFFFFFF, NULL);
1253
1254 // r600_pipe_state_add_reg(rstate, EVERGREEN_GROUP_CONTEXT, R_028350_SX_MISC, 0x0, 0xFFFFFFFF, NULL);
1255
1256 // r600_pipe_state_add_reg(rstate, EVERGREEN_GROUP_CONFIG, R_008D8C_SQ_DYN_GPR_CNTL_PS_FLUSH_REQ, 0x0, 0xFFFFFFFF, NULL);
1257 r600_pipe_state_add_reg(rstate, EVERGREEN_GROUP_CONTEXT, R_028A48_PA_SC_MODE_CNTL_0, 0x0, 0xFFFFFFFF, NULL);
1258 r600_pipe_state_add_reg(rstate, EVERGREEN_GROUP_CONTEXT, R_028A4C_PA_SC_MODE_CNTL_1, 0x0, 0xFFFFFFFF, NULL);
1259
1260 r600_pipe_state_add_reg(rstate, EVERGREEN_GROUP_CONTEXT, R_028900_SQ_ESGS_RING_ITEMSIZE, 0x0, 0xFFFFFFFF, NULL);
1261 r600_pipe_state_add_reg(rstate, EVERGREEN_GROUP_CONTEXT, R_028904_SQ_GSVS_RING_ITEMSIZE, 0x0, 0xFFFFFFFF, NULL);
1262 r600_pipe_state_add_reg(rstate, EVERGREEN_GROUP_CONTEXT, R_028908_SQ_ESTMP_RING_ITEMSIZE, 0x0, 0xFFFFFFFF, NULL);
1263 r600_pipe_state_add_reg(rstate, EVERGREEN_GROUP_CONTEXT, R_02890C_SQ_GSTMP_RING_ITEMSIZE, 0x0, 0xFFFFFFFF, NULL);
1264 r600_pipe_state_add_reg(rstate, EVERGREEN_GROUP_CONTEXT, R_028910_SQ_VSTMP_RING_ITEMSIZE, 0x0, 0xFFFFFFFF, NULL);
1265 r600_pipe_state_add_reg(rstate, EVERGREEN_GROUP_CONTEXT, R_028914_SQ_PSTMP_RING_ITEMSIZE, 0x0, 0xFFFFFFFF, NULL);
1266
1267 r600_pipe_state_add_reg(rstate, EVERGREEN_GROUP_CONTEXT, R_02891C_SQ_GS_VERT_ITEMSIZE, 0x0, 0xFFFFFFFF, NULL);
1268 r600_pipe_state_add_reg(rstate, EVERGREEN_GROUP_CONTEXT, R_028920_SQ_GS_VERT_ITEMSIZE_1, 0x0, 0xFFFFFFFF, NULL);
1269 r600_pipe_state_add_reg(rstate, EVERGREEN_GROUP_CONTEXT, R_028924_SQ_GS_VERT_ITEMSIZE_2, 0x0, 0xFFFFFFFF, NULL);
1270 r600_pipe_state_add_reg(rstate, EVERGREEN_GROUP_CONTEXT, R_028928_SQ_GS_VERT_ITEMSIZE_3, 0x0, 0xFFFFFFFF, NULL);
1271
1272 r600_pipe_state_add_reg(rstate, EVERGREEN_GROUP_CONTEXT, R_028A10_VGT_OUTPUT_PATH_CNTL, 0x0, 0xFFFFFFFF, NULL);
1273 r600_pipe_state_add_reg(rstate, EVERGREEN_GROUP_CONTEXT, R_028A14_VGT_HOS_CNTL, 0x0, 0xFFFFFFFF, NULL);
1274 r600_pipe_state_add_reg(rstate, EVERGREEN_GROUP_CONTEXT, R_028A18_VGT_HOS_MAX_TESS_LEVEL, 0x0, 0xFFFFFFFF, NULL);
1275 r600_pipe_state_add_reg(rstate, EVERGREEN_GROUP_CONTEXT, R_028A1C_VGT_HOS_MIN_TESS_LEVEL, 0x0, 0xFFFFFFFF, NULL);
1276 r600_pipe_state_add_reg(rstate, EVERGREEN_GROUP_CONTEXT, R_028A20_VGT_HOS_REUSE_DEPTH, 0x0, 0xFFFFFFFF, NULL);
1277 r600_pipe_state_add_reg(rstate, EVERGREEN_GROUP_CONTEXT, R_028A24_VGT_GROUP_PRIM_TYPE, 0x0, 0xFFFFFFFF, NULL);
1278 r600_pipe_state_add_reg(rstate, EVERGREEN_GROUP_CONTEXT, R_028A28_VGT_GROUP_FIRST_DECR, 0x0, 0xFFFFFFFF, NULL);
1279 r600_pipe_state_add_reg(rstate, EVERGREEN_GROUP_CONTEXT, R_028A2C_VGT_GROUP_DECR, 0x0, 0xFFFFFFFF, NULL);
1280 r600_pipe_state_add_reg(rstate, EVERGREEN_GROUP_CONTEXT, R_028A30_VGT_GROUP_VECT_0_CNTL, 0x0, 0xFFFFFFFF, NULL);
1281 r600_pipe_state_add_reg(rstate, EVERGREEN_GROUP_CONTEXT, R_028A34_VGT_GROUP_VECT_1_CNTL, 0x0, 0xFFFFFFFF, NULL);
1282 r600_pipe_state_add_reg(rstate, EVERGREEN_GROUP_CONTEXT, R_028A38_VGT_GROUP_VECT_0_FMT_CNTL, 0x0, 0xFFFFFFFF, NULL);
1283 r600_pipe_state_add_reg(rstate, EVERGREEN_GROUP_CONTEXT, R_028A3C_VGT_GROUP_VECT_1_FMT_CNTL, 0x0, 0xFFFFFFFF, NULL);
1284 r600_pipe_state_add_reg(rstate, EVERGREEN_GROUP_CONTEXT, R_028A40_VGT_GS_MODE, 0x0, 0xFFFFFFFF, NULL);
1285 r600_pipe_state_add_reg(rstate, EVERGREEN_GROUP_CONTEXT, R_028B94_VGT_STRMOUT_CONFIG, 0x0, 0xFFFFFFFF, NULL);
1286 r600_pipe_state_add_reg(rstate, EVERGREEN_GROUP_CONTEXT, R_028B98_VGT_STRMOUT_BUFFER_CONFIG, 0x0, 0xFFFFFFFF, NULL);
1287 r600_pipe_state_add_reg(rstate, EVERGREEN_GROUP_CONTEXT, R_028AB4_VGT_REUSE_OFF, 0x00000000, 0xFFFFFFFF, NULL);
1288 r600_pipe_state_add_reg(rstate, EVERGREEN_GROUP_CONTEXT, R_028AB8_VGT_VTX_CNT_EN, 0x0, 0xFFFFFFFF, NULL);
1289 r600_pipe_state_add_reg(rstate, EVERGREEN_GROUP_CONFIG, R_008A14_PA_CL_ENHANCE, (3 << 1) | 1, 0xFFFFFFFF, NULL);
1290
1291 r600_pipe_state_add_reg(rstate, EVERGREEN_GROUP_CONTEXT, R_028380_SQ_VTX_SEMANTIC_0, 0x0, 0xFFFFFFFF, NULL);
1292 r600_pipe_state_add_reg(rstate, EVERGREEN_GROUP_CONTEXT, R_028384_SQ_VTX_SEMANTIC_1, 0x0, 0xFFFFFFFF, NULL);
1293 r600_pipe_state_add_reg(rstate, EVERGREEN_GROUP_CONTEXT, R_028388_SQ_VTX_SEMANTIC_2, 0x0, 0xFFFFFFFF, NULL);
1294 r600_pipe_state_add_reg(rstate, EVERGREEN_GROUP_CONTEXT, R_02838C_SQ_VTX_SEMANTIC_3, 0x0, 0xFFFFFFFF, NULL);
1295 r600_pipe_state_add_reg(rstate, EVERGREEN_GROUP_CONTEXT, R_028390_SQ_VTX_SEMANTIC_4, 0x0, 0xFFFFFFFF, NULL);
1296 r600_pipe_state_add_reg(rstate, EVERGREEN_GROUP_CONTEXT, R_028394_SQ_VTX_SEMANTIC_5, 0x0, 0xFFFFFFFF, NULL);
1297 r600_pipe_state_add_reg(rstate, EVERGREEN_GROUP_CONTEXT, R_028398_SQ_VTX_SEMANTIC_6, 0x0, 0xFFFFFFFF, NULL);
1298 r600_pipe_state_add_reg(rstate, EVERGREEN_GROUP_CONTEXT, R_02839C_SQ_VTX_SEMANTIC_7, 0x0, 0xFFFFFFFF, NULL);
1299 r600_pipe_state_add_reg(rstate, EVERGREEN_GROUP_CONTEXT, R_0283A0_SQ_VTX_SEMANTIC_8, 0x0, 0xFFFFFFFF, NULL);
1300 r600_pipe_state_add_reg(rstate, EVERGREEN_GROUP_CONTEXT, R_0283A4_SQ_VTX_SEMANTIC_9, 0x0, 0xFFFFFFFF, NULL);
1301 r600_pipe_state_add_reg(rstate, EVERGREEN_GROUP_CONTEXT, R_0283A8_SQ_VTX_SEMANTIC_10, 0x0, 0xFFFFFFFF, NULL);
1302 r600_pipe_state_add_reg(rstate, EVERGREEN_GROUP_CONTEXT, R_0283AC_SQ_VTX_SEMANTIC_11, 0x0, 0xFFFFFFFF, NULL);
1303 r600_pipe_state_add_reg(rstate, EVERGREEN_GROUP_CONTEXT, R_0283B0_SQ_VTX_SEMANTIC_12, 0x0, 0xFFFFFFFF, NULL);
1304 r600_pipe_state_add_reg(rstate, EVERGREEN_GROUP_CONTEXT, R_0283B4_SQ_VTX_SEMANTIC_13, 0x0, 0xFFFFFFFF, NULL);
1305 r600_pipe_state_add_reg(rstate, EVERGREEN_GROUP_CONTEXT, R_0283B8_SQ_VTX_SEMANTIC_14, 0x0, 0xFFFFFFFF, NULL);
1306 r600_pipe_state_add_reg(rstate, EVERGREEN_GROUP_CONTEXT, R_0283BC_SQ_VTX_SEMANTIC_15, 0x0, 0xFFFFFFFF, NULL);
1307 r600_pipe_state_add_reg(rstate, EVERGREEN_GROUP_CONTEXT, R_0283C0_SQ_VTX_SEMANTIC_16, 0x0, 0xFFFFFFFF, NULL);
1308 r600_pipe_state_add_reg(rstate, EVERGREEN_GROUP_CONTEXT, R_0283C4_SQ_VTX_SEMANTIC_17, 0x0, 0xFFFFFFFF, NULL);
1309 r600_pipe_state_add_reg(rstate, EVERGREEN_GROUP_CONTEXT, R_0283C8_SQ_VTX_SEMANTIC_18, 0x0, 0xFFFFFFFF, NULL);
1310 r600_pipe_state_add_reg(rstate, EVERGREEN_GROUP_CONTEXT, R_0283CC_SQ_VTX_SEMANTIC_19, 0x0, 0xFFFFFFFF, NULL);
1311 r600_pipe_state_add_reg(rstate, EVERGREEN_GROUP_CONTEXT, R_0283D0_SQ_VTX_SEMANTIC_20, 0x0, 0xFFFFFFFF, NULL);
1312 r600_pipe_state_add_reg(rstate, EVERGREEN_GROUP_CONTEXT, R_0283D4_SQ_VTX_SEMANTIC_21, 0x0, 0xFFFFFFFF, NULL);
1313 r600_pipe_state_add_reg(rstate, EVERGREEN_GROUP_CONTEXT, R_0283D8_SQ_VTX_SEMANTIC_22, 0x0, 0xFFFFFFFF, NULL);
1314 r600_pipe_state_add_reg(rstate, EVERGREEN_GROUP_CONTEXT, R_0283DC_SQ_VTX_SEMANTIC_23, 0x0, 0xFFFFFFFF, NULL);
1315 r600_pipe_state_add_reg(rstate, EVERGREEN_GROUP_CONTEXT, R_0283E0_SQ_VTX_SEMANTIC_24, 0x0, 0xFFFFFFFF, NULL);
1316 r600_pipe_state_add_reg(rstate, EVERGREEN_GROUP_CONTEXT, R_0283E4_SQ_VTX_SEMANTIC_25, 0x0, 0xFFFFFFFF, NULL);
1317 r600_pipe_state_add_reg(rstate, EVERGREEN_GROUP_CONTEXT, R_0283E8_SQ_VTX_SEMANTIC_26, 0x0, 0xFFFFFFFF, NULL);
1318 r600_pipe_state_add_reg(rstate, EVERGREEN_GROUP_CONTEXT, R_0283EC_SQ_VTX_SEMANTIC_27, 0x0, 0xFFFFFFFF, NULL);
1319 r600_pipe_state_add_reg(rstate, EVERGREEN_GROUP_CONTEXT, R_0283F0_SQ_VTX_SEMANTIC_28, 0x0, 0xFFFFFFFF, NULL);
1320 r600_pipe_state_add_reg(rstate, EVERGREEN_GROUP_CONTEXT, R_0283F4_SQ_VTX_SEMANTIC_29, 0x0, 0xFFFFFFFF, NULL);
1321 r600_pipe_state_add_reg(rstate, EVERGREEN_GROUP_CONTEXT, R_0283F8_SQ_VTX_SEMANTIC_30, 0x0, 0xFFFFFFFF, NULL);
1322 r600_pipe_state_add_reg(rstate, EVERGREEN_GROUP_CONTEXT, R_0283FC_SQ_VTX_SEMANTIC_31, 0x0, 0xFFFFFFFF, NULL);
1323
1324 r600_pipe_state_add_reg(rstate, EVERGREEN_GROUP_CONTEXT, R_028810_PA_CL_CLIP_CNTL,
1325 0x0, 0xFFFFFFFF, NULL);
1326
1327 r600_context_pipe_state_set(&rctx->ctx, rstate);
1328 }
1329
1330 int r600_conv_pipe_prim(unsigned pprim, unsigned *prim);
1331 void evergreen_draw(struct pipe_context *ctx, const struct pipe_draw_info *info)
1332 {
1333 struct r600_pipe_context *rctx = (struct r600_pipe_context *)ctx;
1334 struct r600_pipe_state *rstate;
1335 struct r600_resource *rbuffer;
1336 unsigned i, j, offset, format, prim;
1337 u32 vgt_dma_index_type, vgt_draw_initiator, mask;
1338 struct pipe_vertex_buffer *vertex_buffer;
1339 struct r600_draw rdraw;
1340 struct r600_pipe_state vgt;
1341 struct r600_drawl draw;
1342
1343 assert(info->index_bias == 0);
1344
1345 draw.mode = info->mode;
1346 draw.start = info->start;
1347 draw.count = info->count;
1348 if (info->indexed && rctx->index_buffer.buffer) {
1349 draw.index_size = rctx->index_buffer.index_size;
1350 draw.index_buffer = rctx->index_buffer.buffer;
1351 assert(rctx->index_buffer.offset %
1352 rctx->index_buffer.index_size == 0);
1353 draw.start += rctx->index_buffer.offset /
1354 rctx->index_buffer.index_size;
1355 } else {
1356 draw.index_size = 0;
1357 draw.index_buffer = NULL;
1358 }
1359 switch (draw.index_size) {
1360 case 2:
1361 vgt_draw_initiator = 0;
1362 vgt_dma_index_type = 0;
1363 break;
1364 case 4:
1365 vgt_draw_initiator = 0;
1366 vgt_dma_index_type = 1;
1367 break;
1368 case 0:
1369 vgt_draw_initiator = 2;
1370 vgt_dma_index_type = 0;
1371 break;
1372 default:
1373 R600_ERR("unsupported index size %d\n", draw.index_size);
1374 return;
1375 }
1376 if (r600_conv_pipe_prim(draw.mode, &prim))
1377 return;
1378
1379 /* rebuild vertex shader if input format changed */
1380 if (r600_pipe_shader_update2(&rctx->context, rctx->vs_shader))
1381 return;
1382 if (r600_pipe_shader_update2(&rctx->context, rctx->ps_shader))
1383 return;
1384
1385 for (i = 0 ; i < rctx->vertex_elements->count; i++) {
1386 rstate = &rctx->vs_resource[i];
1387 j = rctx->vertex_elements->elements[i].vertex_buffer_index;
1388 vertex_buffer = &rctx->vertex_buffer[j];
1389 rbuffer = (struct r600_resource*)vertex_buffer->buffer;
1390 offset = rctx->vertex_elements->elements[i].src_offset + vertex_buffer->buffer_offset;
1391 format = r600_translate_colorformat(rctx->vertex_elements->elements[i].src_format);
1392 rstate->id = R600_PIPE_STATE_RESOURCE;
1393 rstate->nregs = 0;
1394
1395 r600_pipe_state_add_reg(rstate, EVERGREEN_GROUP_RESOURCE, R_030000_RESOURCE0_WORD0, offset, 0xFFFFFFFF, rbuffer->bo);
1396 r600_pipe_state_add_reg(rstate, EVERGREEN_GROUP_RESOURCE, R_030004_RESOURCE0_WORD1, rbuffer->size - offset - 1, 0xFFFFFFFF, NULL);
1397 r600_pipe_state_add_reg(rstate, EVERGREEN_GROUP_RESOURCE,
1398 R_030008_RESOURCE0_WORD2,
1399 S_030008_STRIDE(vertex_buffer->stride) |
1400 S_030008_DATA_FORMAT(format),
1401 0xFFFFFFFF, NULL);
1402 r600_pipe_state_add_reg(rstate, EVERGREEN_GROUP_RESOURCE,
1403 R_03000C_RESOURCE0_WORD3,
1404 S_03000C_DST_SEL_X(V_03000C_SQ_SEL_X) |
1405 S_03000C_DST_SEL_Y(V_03000C_SQ_SEL_Y) |
1406 S_03000C_DST_SEL_Z(V_03000C_SQ_SEL_Z) |
1407 S_03000C_DST_SEL_W(V_03000C_SQ_SEL_W),
1408 0xFFFFFFFF, NULL);
1409 r600_pipe_state_add_reg(rstate, EVERGREEN_GROUP_RESOURCE, R_030010_RESOURCE0_WORD4, 0x00000000, 0xFFFFFFFF, NULL);
1410 r600_pipe_state_add_reg(rstate, EVERGREEN_GROUP_RESOURCE, R_030014_RESOURCE0_WORD5, 0x00000000, 0xFFFFFFFF, NULL);
1411 r600_pipe_state_add_reg(rstate, EVERGREEN_GROUP_RESOURCE, R_030018_RESOURCE0_WORD6, 0x00000000, 0xFFFFFFFF, NULL);
1412 r600_pipe_state_add_reg(rstate, EVERGREEN_GROUP_RESOURCE, R_03001C_RESOURCE0_WORD7, 0xC0000000, 0xFFFFFFFF, NULL);
1413 evergreen_vs_resource_set(&rctx->ctx, rstate, i);
1414 }
1415
1416 mask = 0;
1417 for (int i = 0; i < rctx->framebuffer.nr_cbufs; i++) {
1418 mask |= (0xF << (i * 4));
1419 }
1420
1421 vgt.id = R600_PIPE_STATE_VGT;
1422 vgt.nregs = 0;
1423 r600_pipe_state_add_reg(&vgt, EVERGREEN_GROUP_CONFIG, R_008958_VGT_PRIMITIVE_TYPE, prim, 0xFFFFFFFF, NULL);
1424 r600_pipe_state_add_reg(&vgt, EVERGREEN_GROUP_CONTEXT, R_028408_VGT_INDX_OFFSET, draw.start, 0xFFFFFFFF, NULL);
1425 r600_pipe_state_add_reg(&vgt, EVERGREEN_GROUP_CONTEXT, R_028238_CB_TARGET_MASK, rctx->cb_target_mask & mask, 0xFFFFFFFF, NULL);
1426 r600_pipe_state_add_reg(&vgt, EVERGREEN_GROUP_CONTEXT, R_028400_VGT_MAX_VTX_INDX, info->max_index, 0xFFFFFFFF, NULL);
1427 r600_pipe_state_add_reg(&vgt, EVERGREEN_GROUP_CONTEXT, R_028404_VGT_MIN_VTX_INDX, 0x00000000, 0xFFFFFFFF, NULL);
1428 r600_context_pipe_state_set(&rctx->ctx, &vgt);
1429
1430 rdraw.vgt_num_indices = draw.count;
1431 rdraw.vgt_num_instances = 1;
1432 rdraw.vgt_index_type = vgt_dma_index_type;
1433 rdraw.vgt_draw_initiator = vgt_draw_initiator;
1434 rdraw.indices = NULL;
1435 if (draw.index_buffer) {
1436 rbuffer = (struct r600_resource*)draw.index_buffer;
1437 rdraw.indices = rbuffer->bo;
1438 rdraw.indices_bo_offset = 0;
1439 }
1440 evergreen_context_draw(&rctx->ctx, &rdraw);
1441 }
1442
1443 void evergreen_pipe_shader_ps(struct pipe_context *ctx, struct r600_pipe_shader *shader)
1444 {
1445 struct r600_pipe_context *rctx = (struct r600_pipe_context *)ctx;
1446 struct r600_pipe_state *rstate = &shader->rstate;
1447 struct r600_shader *rshader = &shader->shader;
1448 unsigned i, tmp, exports_ps, num_cout, spi_ps_in_control_0, spi_input_z;
1449 boolean have_pos = FALSE, have_face = FALSE;
1450
1451 /* clear previous register */
1452 rstate->nregs = 0;
1453
1454 for (i = 0; i < rshader->ninput; i++) {
1455 tmp = S_028644_SEMANTIC(i);
1456 tmp |= S_028644_SEL_CENTROID(1);
1457 if (rshader->input[i].name == TGSI_SEMANTIC_POSITION)
1458 have_pos = TRUE;
1459 if (rshader->input[i].name == TGSI_SEMANTIC_COLOR ||
1460 rshader->input[i].name == TGSI_SEMANTIC_BCOLOR ||
1461 rshader->input[i].name == TGSI_SEMANTIC_POSITION) {
1462 tmp |= S_028644_FLAT_SHADE(rshader->flat_shade);
1463 }
1464 if (rshader->input[i].name == TGSI_SEMANTIC_FACE)
1465 have_face = TRUE;
1466 if (rctx->sprite_coord_enable & (1 << i)) {
1467 tmp |= S_028644_PT_SPRITE_TEX(1);
1468 }
1469 r600_pipe_state_add_reg(rstate, EVERGREEN_GROUP_CONTEXT, R_028644_SPI_PS_INPUT_CNTL_0 + i * 4, tmp, 0xFFFFFFFF, NULL);
1470 }
1471
1472 exports_ps = 0;
1473 num_cout = 0;
1474 for (i = 0; i < rshader->noutput; i++) {
1475 if (rshader->output[i].name == TGSI_SEMANTIC_POSITION)
1476 exports_ps |= 1;
1477 else if (rshader->output[i].name == TGSI_SEMANTIC_COLOR) {
1478 num_cout++;
1479 }
1480 }
1481 exports_ps |= S_02884C_EXPORT_COLORS(num_cout);
1482 if (!exports_ps) {
1483 /* always at least export 1 component per pixel */
1484 exports_ps = 2;
1485 }
1486
1487 spi_ps_in_control_0 = S_0286CC_NUM_INTERP(rshader->ninput) |
1488 S_0286CC_PERSP_GRADIENT_ENA(1);
1489 spi_input_z = 0;
1490 if (have_pos) {
1491 spi_ps_in_control_0 |= S_0286CC_POSITION_ENA(1);
1492 spi_input_z |= 1;
1493 }
1494 r600_pipe_state_add_reg(rstate, EVERGREEN_GROUP_CONTEXT, R_0286CC_SPI_PS_IN_CONTROL_0,
1495 spi_ps_in_control_0, 0xFFFFFFFF, NULL);
1496 r600_pipe_state_add_reg(rstate, EVERGREEN_GROUP_CONTEXT, R_0286D0_SPI_PS_IN_CONTROL_1,
1497 S_0286D0_FRONT_FACE_ENA(have_face), 0xFFFFFFFF, NULL);
1498 r600_pipe_state_add_reg(rstate, EVERGREEN_GROUP_CONTEXT, R_0286D8_SPI_INPUT_Z, spi_input_z, 0xFFFFFFFF, NULL);
1499 r600_pipe_state_add_reg(rstate, EVERGREEN_GROUP_CONTEXT,
1500 R_028840_SQ_PGM_START_PS,
1501 0x00000000, 0xFFFFFFFF, shader->bo);
1502 r600_pipe_state_add_reg(rstate, EVERGREEN_GROUP_CONTEXT,
1503 R_028844_SQ_PGM_RESOURCES_PS,
1504 S_028844_NUM_GPRS(rshader->bc.ngpr) |
1505 S_028844_PRIME_CACHE_ON_DRAW(1) |
1506 S_028844_STACK_SIZE(rshader->bc.nstack),
1507 0xFFFFFFFF, NULL);
1508 r600_pipe_state_add_reg(rstate, EVERGREEN_GROUP_CONTEXT,
1509 R_028848_SQ_PGM_RESOURCES_2_PS,
1510 0x0, 0xFFFFFFFF, NULL);
1511 r600_pipe_state_add_reg(rstate, EVERGREEN_GROUP_CONTEXT,
1512 R_02884C_SQ_PGM_EXPORTS_PS,
1513 exports_ps, 0xFFFFFFFF, NULL);
1514 r600_pipe_state_add_reg(rstate, EVERGREEN_GROUP_CONTEXT,
1515 R_0286E0_SPI_BARYC_CNTL,
1516 S_0286E0_PERSP_CENTROID_ENA(1) |
1517 S_0286E0_LINEAR_CENTROID_ENA(1),
1518 0xFFFFFFFF, NULL);
1519 }
1520
1521 void evergreen_pipe_shader_vs(struct pipe_context *ctx, struct r600_pipe_shader *shader)
1522 {
1523 struct r600_pipe_state *rstate = &shader->rstate;
1524 struct r600_shader *rshader = &shader->shader;
1525 unsigned spi_vs_out_id[10];
1526 unsigned i, tmp;
1527
1528 /* clear previous register */
1529 rstate->nregs = 0;
1530
1531 /* so far never got proper semantic id from tgsi */
1532 for (i = 0; i < 10; i++) {
1533 spi_vs_out_id[i] = 0;
1534 }
1535 for (i = 0; i < 32; i++) {
1536 tmp = i << ((i & 3) * 8);
1537 spi_vs_out_id[i / 4] |= tmp;
1538 }
1539 for (i = 0; i < 10; i++) {
1540 r600_pipe_state_add_reg(rstate, EVERGREEN_GROUP_CONTEXT,
1541 R_02861C_SPI_VS_OUT_ID_0 + i * 4,
1542 spi_vs_out_id[i], 0xFFFFFFFF, NULL);
1543 }
1544
1545 r600_pipe_state_add_reg(rstate, EVERGREEN_GROUP_CONTEXT,
1546 R_0286C4_SPI_VS_OUT_CONFIG,
1547 S_0286C4_VS_EXPORT_COUNT(rshader->noutput - 2),
1548 0xFFFFFFFF, NULL);
1549 r600_pipe_state_add_reg(rstate, EVERGREEN_GROUP_CONTEXT,
1550 R_028860_SQ_PGM_RESOURCES_VS,
1551 S_028860_NUM_GPRS(rshader->bc.ngpr) |
1552 S_028860_STACK_SIZE(rshader->bc.nstack),
1553 0xFFFFFFFF, NULL);
1554 r600_pipe_state_add_reg(rstate, EVERGREEN_GROUP_CONTEXT,
1555 R_028864_SQ_PGM_RESOURCES_2_VS,
1556 0x0, 0xFFFFFFFF, NULL);
1557 r600_pipe_state_add_reg(rstate, EVERGREEN_GROUP_CONTEXT,
1558 R_0288A8_SQ_PGM_RESOURCES_FS,
1559 0x00000000, 0xFFFFFFFF, NULL);
1560 r600_pipe_state_add_reg(rstate, EVERGREEN_GROUP_CONTEXT,
1561 R_02885C_SQ_PGM_START_VS,
1562 0x00000000, 0xFFFFFFFF, shader->bo);
1563 r600_pipe_state_add_reg(rstate, EVERGREEN_GROUP_CONTEXT,
1564 R_0288A4_SQ_PGM_START_FS,
1565 0x00000000, 0xFFFFFFFF, shader->bo);
1566 }