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gallium: change pipe_sampler_view::first_element/last_element -> offset/size
[mesa.git] / src / gallium / drivers / r600 / evergreen_state.c
1 /*
2 * Copyright 2010 Jerome Glisse <glisse@freedesktop.org>
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * on the rights to use, copy, modify, merge, publish, distribute, sub
8 * license, and/or sell copies of the Software, and to permit persons to whom
9 * the Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
13 * Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHOR(S) AND/OR THEIR SUPPLIERS BE LIABLE FOR ANY CLAIM,
19 * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
20 * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
21 * USE OR OTHER DEALINGS IN THE SOFTWARE.
22 */
23 #include "r600_formats.h"
24 #include "r600_shader.h"
25 #include "evergreend.h"
26
27 #include "pipe/p_shader_tokens.h"
28 #include "util/u_pack_color.h"
29 #include "util/u_memory.h"
30 #include "util/u_framebuffer.h"
31 #include "util/u_dual_blend.h"
32 #include "evergreen_compute.h"
33 #include "util/u_math.h"
34
35 static inline unsigned evergreen_array_mode(unsigned mode)
36 {
37 switch (mode) {
38 default:
39 case RADEON_SURF_MODE_LINEAR_ALIGNED: return V_028C70_ARRAY_LINEAR_ALIGNED;
40 break;
41 case RADEON_SURF_MODE_1D: return V_028C70_ARRAY_1D_TILED_THIN1;
42 break;
43 case RADEON_SURF_MODE_2D: return V_028C70_ARRAY_2D_TILED_THIN1;
44 }
45 }
46
47 static uint32_t eg_num_banks(uint32_t nbanks)
48 {
49 switch (nbanks) {
50 case 2:
51 return 0;
52 case 4:
53 return 1;
54 case 8:
55 default:
56 return 2;
57 case 16:
58 return 3;
59 }
60 }
61
62
63 static unsigned eg_tile_split(unsigned tile_split)
64 {
65 switch (tile_split) {
66 case 64: tile_split = 0; break;
67 case 128: tile_split = 1; break;
68 case 256: tile_split = 2; break;
69 case 512: tile_split = 3; break;
70 default:
71 case 1024: tile_split = 4; break;
72 case 2048: tile_split = 5; break;
73 case 4096: tile_split = 6; break;
74 }
75 return tile_split;
76 }
77
78 static unsigned eg_macro_tile_aspect(unsigned macro_tile_aspect)
79 {
80 switch (macro_tile_aspect) {
81 default:
82 case 1: macro_tile_aspect = 0; break;
83 case 2: macro_tile_aspect = 1; break;
84 case 4: macro_tile_aspect = 2; break;
85 case 8: macro_tile_aspect = 3; break;
86 }
87 return macro_tile_aspect;
88 }
89
90 static unsigned eg_bank_wh(unsigned bankwh)
91 {
92 switch (bankwh) {
93 default:
94 case 1: bankwh = 0; break;
95 case 2: bankwh = 1; break;
96 case 4: bankwh = 2; break;
97 case 8: bankwh = 3; break;
98 }
99 return bankwh;
100 }
101
102 static uint32_t r600_translate_blend_function(int blend_func)
103 {
104 switch (blend_func) {
105 case PIPE_BLEND_ADD:
106 return V_028780_COMB_DST_PLUS_SRC;
107 case PIPE_BLEND_SUBTRACT:
108 return V_028780_COMB_SRC_MINUS_DST;
109 case PIPE_BLEND_REVERSE_SUBTRACT:
110 return V_028780_COMB_DST_MINUS_SRC;
111 case PIPE_BLEND_MIN:
112 return V_028780_COMB_MIN_DST_SRC;
113 case PIPE_BLEND_MAX:
114 return V_028780_COMB_MAX_DST_SRC;
115 default:
116 R600_ERR("Unknown blend function %d\n", blend_func);
117 assert(0);
118 break;
119 }
120 return 0;
121 }
122
123 static uint32_t r600_translate_blend_factor(int blend_fact)
124 {
125 switch (blend_fact) {
126 case PIPE_BLENDFACTOR_ONE:
127 return V_028780_BLEND_ONE;
128 case PIPE_BLENDFACTOR_SRC_COLOR:
129 return V_028780_BLEND_SRC_COLOR;
130 case PIPE_BLENDFACTOR_SRC_ALPHA:
131 return V_028780_BLEND_SRC_ALPHA;
132 case PIPE_BLENDFACTOR_DST_ALPHA:
133 return V_028780_BLEND_DST_ALPHA;
134 case PIPE_BLENDFACTOR_DST_COLOR:
135 return V_028780_BLEND_DST_COLOR;
136 case PIPE_BLENDFACTOR_SRC_ALPHA_SATURATE:
137 return V_028780_BLEND_SRC_ALPHA_SATURATE;
138 case PIPE_BLENDFACTOR_CONST_COLOR:
139 return V_028780_BLEND_CONST_COLOR;
140 case PIPE_BLENDFACTOR_CONST_ALPHA:
141 return V_028780_BLEND_CONST_ALPHA;
142 case PIPE_BLENDFACTOR_ZERO:
143 return V_028780_BLEND_ZERO;
144 case PIPE_BLENDFACTOR_INV_SRC_COLOR:
145 return V_028780_BLEND_ONE_MINUS_SRC_COLOR;
146 case PIPE_BLENDFACTOR_INV_SRC_ALPHA:
147 return V_028780_BLEND_ONE_MINUS_SRC_ALPHA;
148 case PIPE_BLENDFACTOR_INV_DST_ALPHA:
149 return V_028780_BLEND_ONE_MINUS_DST_ALPHA;
150 case PIPE_BLENDFACTOR_INV_DST_COLOR:
151 return V_028780_BLEND_ONE_MINUS_DST_COLOR;
152 case PIPE_BLENDFACTOR_INV_CONST_COLOR:
153 return V_028780_BLEND_ONE_MINUS_CONST_COLOR;
154 case PIPE_BLENDFACTOR_INV_CONST_ALPHA:
155 return V_028780_BLEND_ONE_MINUS_CONST_ALPHA;
156 case PIPE_BLENDFACTOR_SRC1_COLOR:
157 return V_028780_BLEND_SRC1_COLOR;
158 case PIPE_BLENDFACTOR_SRC1_ALPHA:
159 return V_028780_BLEND_SRC1_ALPHA;
160 case PIPE_BLENDFACTOR_INV_SRC1_COLOR:
161 return V_028780_BLEND_INV_SRC1_COLOR;
162 case PIPE_BLENDFACTOR_INV_SRC1_ALPHA:
163 return V_028780_BLEND_INV_SRC1_ALPHA;
164 default:
165 R600_ERR("Bad blend factor %d not supported!\n", blend_fact);
166 assert(0);
167 break;
168 }
169 return 0;
170 }
171
172 static unsigned r600_tex_dim(unsigned dim, unsigned nr_samples)
173 {
174 switch (dim) {
175 default:
176 case PIPE_TEXTURE_1D:
177 return V_030000_SQ_TEX_DIM_1D;
178 case PIPE_TEXTURE_1D_ARRAY:
179 return V_030000_SQ_TEX_DIM_1D_ARRAY;
180 case PIPE_TEXTURE_2D:
181 case PIPE_TEXTURE_RECT:
182 return nr_samples > 1 ? V_030000_SQ_TEX_DIM_2D_MSAA :
183 V_030000_SQ_TEX_DIM_2D;
184 case PIPE_TEXTURE_2D_ARRAY:
185 return nr_samples > 1 ? V_030000_SQ_TEX_DIM_2D_ARRAY_MSAA :
186 V_030000_SQ_TEX_DIM_2D_ARRAY;
187 case PIPE_TEXTURE_3D:
188 return V_030000_SQ_TEX_DIM_3D;
189 case PIPE_TEXTURE_CUBE:
190 case PIPE_TEXTURE_CUBE_ARRAY:
191 return V_030000_SQ_TEX_DIM_CUBEMAP;
192 }
193 }
194
195 static uint32_t r600_translate_dbformat(enum pipe_format format)
196 {
197 switch (format) {
198 case PIPE_FORMAT_Z16_UNORM:
199 return V_028040_Z_16;
200 case PIPE_FORMAT_Z24X8_UNORM:
201 case PIPE_FORMAT_Z24_UNORM_S8_UINT:
202 case PIPE_FORMAT_X8Z24_UNORM:
203 case PIPE_FORMAT_S8_UINT_Z24_UNORM:
204 return V_028040_Z_24;
205 case PIPE_FORMAT_Z32_FLOAT:
206 case PIPE_FORMAT_Z32_FLOAT_S8X24_UINT:
207 return V_028040_Z_32_FLOAT;
208 default:
209 return ~0U;
210 }
211 }
212
213 static bool r600_is_sampler_format_supported(struct pipe_screen *screen, enum pipe_format format)
214 {
215 return r600_translate_texformat(screen, format, NULL, NULL, NULL,
216 FALSE) != ~0U;
217 }
218
219 static bool r600_is_colorbuffer_format_supported(enum chip_class chip, enum pipe_format format)
220 {
221 return r600_translate_colorformat(chip, format, FALSE) != ~0U &&
222 r600_translate_colorswap(format, FALSE) != ~0U;
223 }
224
225 static bool r600_is_zs_format_supported(enum pipe_format format)
226 {
227 return r600_translate_dbformat(format) != ~0U;
228 }
229
230 boolean evergreen_is_format_supported(struct pipe_screen *screen,
231 enum pipe_format format,
232 enum pipe_texture_target target,
233 unsigned sample_count,
234 unsigned usage)
235 {
236 struct r600_screen *rscreen = (struct r600_screen*)screen;
237 unsigned retval = 0;
238
239 if (target >= PIPE_MAX_TEXTURE_TYPES) {
240 R600_ERR("r600: unsupported texture type %d\n", target);
241 return FALSE;
242 }
243
244 if (!util_format_is_supported(format, usage))
245 return FALSE;
246
247 if (sample_count > 1) {
248 if (!rscreen->has_msaa)
249 return FALSE;
250
251 switch (sample_count) {
252 case 2:
253 case 4:
254 case 8:
255 break;
256 default:
257 return FALSE;
258 }
259 }
260
261 if (usage & PIPE_BIND_SAMPLER_VIEW) {
262 if (target == PIPE_BUFFER) {
263 if (r600_is_vertex_format_supported(format))
264 retval |= PIPE_BIND_SAMPLER_VIEW;
265 } else {
266 if (r600_is_sampler_format_supported(screen, format))
267 retval |= PIPE_BIND_SAMPLER_VIEW;
268 }
269 }
270
271 if ((usage & (PIPE_BIND_RENDER_TARGET |
272 PIPE_BIND_DISPLAY_TARGET |
273 PIPE_BIND_SCANOUT |
274 PIPE_BIND_SHARED |
275 PIPE_BIND_BLENDABLE)) &&
276 r600_is_colorbuffer_format_supported(rscreen->b.chip_class, format)) {
277 retval |= usage &
278 (PIPE_BIND_RENDER_TARGET |
279 PIPE_BIND_DISPLAY_TARGET |
280 PIPE_BIND_SCANOUT |
281 PIPE_BIND_SHARED);
282 if (!util_format_is_pure_integer(format) &&
283 !util_format_is_depth_or_stencil(format))
284 retval |= usage & PIPE_BIND_BLENDABLE;
285 }
286
287 if ((usage & PIPE_BIND_DEPTH_STENCIL) &&
288 r600_is_zs_format_supported(format)) {
289 retval |= PIPE_BIND_DEPTH_STENCIL;
290 }
291
292 if ((usage & PIPE_BIND_VERTEX_BUFFER) &&
293 r600_is_vertex_format_supported(format)) {
294 retval |= PIPE_BIND_VERTEX_BUFFER;
295 }
296
297 if (usage & PIPE_BIND_TRANSFER_READ)
298 retval |= PIPE_BIND_TRANSFER_READ;
299 if (usage & PIPE_BIND_TRANSFER_WRITE)
300 retval |= PIPE_BIND_TRANSFER_WRITE;
301
302 if ((usage & PIPE_BIND_LINEAR) &&
303 !util_format_is_compressed(format) &&
304 !(usage & PIPE_BIND_DEPTH_STENCIL))
305 retval |= PIPE_BIND_LINEAR;
306
307 return retval == usage;
308 }
309
310 static void *evergreen_create_blend_state_mode(struct pipe_context *ctx,
311 const struct pipe_blend_state *state, int mode)
312 {
313 uint32_t color_control = 0, target_mask = 0;
314 struct r600_blend_state *blend = CALLOC_STRUCT(r600_blend_state);
315
316 if (!blend) {
317 return NULL;
318 }
319
320 r600_init_command_buffer(&blend->buffer, 20);
321 r600_init_command_buffer(&blend->buffer_no_blend, 20);
322
323 if (state->logicop_enable) {
324 color_control |= (state->logicop_func << 16) | (state->logicop_func << 20);
325 } else {
326 color_control |= (0xcc << 16);
327 }
328 /* we pretend 8 buffer are used, CB_SHADER_MASK will disable unused one */
329 if (state->independent_blend_enable) {
330 for (int i = 0; i < 8; i++) {
331 target_mask |= (state->rt[i].colormask << (4 * i));
332 }
333 } else {
334 for (int i = 0; i < 8; i++) {
335 target_mask |= (state->rt[0].colormask << (4 * i));
336 }
337 }
338
339 /* only have dual source on MRT0 */
340 blend->dual_src_blend = util_blend_state_is_dual(state, 0);
341 blend->cb_target_mask = target_mask;
342 blend->alpha_to_one = state->alpha_to_one;
343
344 if (target_mask)
345 color_control |= S_028808_MODE(mode);
346 else
347 color_control |= S_028808_MODE(V_028808_CB_DISABLE);
348
349
350 r600_store_context_reg(&blend->buffer, R_028808_CB_COLOR_CONTROL, color_control);
351 r600_store_context_reg(&blend->buffer, R_028B70_DB_ALPHA_TO_MASK,
352 S_028B70_ALPHA_TO_MASK_ENABLE(state->alpha_to_coverage) |
353 S_028B70_ALPHA_TO_MASK_OFFSET0(2) |
354 S_028B70_ALPHA_TO_MASK_OFFSET1(2) |
355 S_028B70_ALPHA_TO_MASK_OFFSET2(2) |
356 S_028B70_ALPHA_TO_MASK_OFFSET3(2));
357 r600_store_context_reg_seq(&blend->buffer, R_028780_CB_BLEND0_CONTROL, 8);
358
359 /* Copy over the dwords set so far into buffer_no_blend.
360 * Only the CB_BLENDi_CONTROL registers must be set after this. */
361 memcpy(blend->buffer_no_blend.buf, blend->buffer.buf, blend->buffer.num_dw * 4);
362 blend->buffer_no_blend.num_dw = blend->buffer.num_dw;
363
364 for (int i = 0; i < 8; i++) {
365 /* state->rt entries > 0 only written if independent blending */
366 const int j = state->independent_blend_enable ? i : 0;
367
368 unsigned eqRGB = state->rt[j].rgb_func;
369 unsigned srcRGB = state->rt[j].rgb_src_factor;
370 unsigned dstRGB = state->rt[j].rgb_dst_factor;
371 unsigned eqA = state->rt[j].alpha_func;
372 unsigned srcA = state->rt[j].alpha_src_factor;
373 unsigned dstA = state->rt[j].alpha_dst_factor;
374 uint32_t bc = 0;
375
376 r600_store_value(&blend->buffer_no_blend, 0);
377
378 if (!state->rt[j].blend_enable) {
379 r600_store_value(&blend->buffer, 0);
380 continue;
381 }
382
383 bc |= S_028780_BLEND_CONTROL_ENABLE(1);
384 bc |= S_028780_COLOR_COMB_FCN(r600_translate_blend_function(eqRGB));
385 bc |= S_028780_COLOR_SRCBLEND(r600_translate_blend_factor(srcRGB));
386 bc |= S_028780_COLOR_DESTBLEND(r600_translate_blend_factor(dstRGB));
387
388 if (srcA != srcRGB || dstA != dstRGB || eqA != eqRGB) {
389 bc |= S_028780_SEPARATE_ALPHA_BLEND(1);
390 bc |= S_028780_ALPHA_COMB_FCN(r600_translate_blend_function(eqA));
391 bc |= S_028780_ALPHA_SRCBLEND(r600_translate_blend_factor(srcA));
392 bc |= S_028780_ALPHA_DESTBLEND(r600_translate_blend_factor(dstA));
393 }
394 r600_store_value(&blend->buffer, bc);
395 }
396 return blend;
397 }
398
399 static void *evergreen_create_blend_state(struct pipe_context *ctx,
400 const struct pipe_blend_state *state)
401 {
402
403 return evergreen_create_blend_state_mode(ctx, state, V_028808_CB_NORMAL);
404 }
405
406 static void *evergreen_create_dsa_state(struct pipe_context *ctx,
407 const struct pipe_depth_stencil_alpha_state *state)
408 {
409 unsigned db_depth_control, alpha_test_control, alpha_ref;
410 struct r600_dsa_state *dsa = CALLOC_STRUCT(r600_dsa_state);
411
412 if (!dsa) {
413 return NULL;
414 }
415
416 r600_init_command_buffer(&dsa->buffer, 3);
417
418 dsa->valuemask[0] = state->stencil[0].valuemask;
419 dsa->valuemask[1] = state->stencil[1].valuemask;
420 dsa->writemask[0] = state->stencil[0].writemask;
421 dsa->writemask[1] = state->stencil[1].writemask;
422 dsa->zwritemask = state->depth.writemask;
423
424 db_depth_control = S_028800_Z_ENABLE(state->depth.enabled) |
425 S_028800_Z_WRITE_ENABLE(state->depth.writemask) |
426 S_028800_ZFUNC(state->depth.func);
427
428 /* stencil */
429 if (state->stencil[0].enabled) {
430 db_depth_control |= S_028800_STENCIL_ENABLE(1);
431 db_depth_control |= S_028800_STENCILFUNC(state->stencil[0].func); /* translates straight */
432 db_depth_control |= S_028800_STENCILFAIL(r600_translate_stencil_op(state->stencil[0].fail_op));
433 db_depth_control |= S_028800_STENCILZPASS(r600_translate_stencil_op(state->stencil[0].zpass_op));
434 db_depth_control |= S_028800_STENCILZFAIL(r600_translate_stencil_op(state->stencil[0].zfail_op));
435
436 if (state->stencil[1].enabled) {
437 db_depth_control |= S_028800_BACKFACE_ENABLE(1);
438 db_depth_control |= S_028800_STENCILFUNC_BF(state->stencil[1].func); /* translates straight */
439 db_depth_control |= S_028800_STENCILFAIL_BF(r600_translate_stencil_op(state->stencil[1].fail_op));
440 db_depth_control |= S_028800_STENCILZPASS_BF(r600_translate_stencil_op(state->stencil[1].zpass_op));
441 db_depth_control |= S_028800_STENCILZFAIL_BF(r600_translate_stencil_op(state->stencil[1].zfail_op));
442 }
443 }
444
445 /* alpha */
446 alpha_test_control = 0;
447 alpha_ref = 0;
448 if (state->alpha.enabled) {
449 alpha_test_control = S_028410_ALPHA_FUNC(state->alpha.func);
450 alpha_test_control |= S_028410_ALPHA_TEST_ENABLE(1);
451 alpha_ref = fui(state->alpha.ref_value);
452 }
453 dsa->sx_alpha_test_control = alpha_test_control & 0xff;
454 dsa->alpha_ref = alpha_ref;
455
456 /* misc */
457 r600_store_context_reg(&dsa->buffer, R_028800_DB_DEPTH_CONTROL, db_depth_control);
458 return dsa;
459 }
460
461 static void *evergreen_create_rs_state(struct pipe_context *ctx,
462 const struct pipe_rasterizer_state *state)
463 {
464 struct r600_context *rctx = (struct r600_context *)ctx;
465 unsigned tmp, spi_interp;
466 float psize_min, psize_max;
467 struct r600_rasterizer_state *rs = CALLOC_STRUCT(r600_rasterizer_state);
468
469 if (!rs) {
470 return NULL;
471 }
472
473 r600_init_command_buffer(&rs->buffer, 30);
474
475 rs->scissor_enable = state->scissor;
476 rs->flatshade = state->flatshade;
477 rs->sprite_coord_enable = state->sprite_coord_enable;
478 rs->two_side = state->light_twoside;
479 rs->clip_plane_enable = state->clip_plane_enable;
480 rs->pa_sc_line_stipple = state->line_stipple_enable ?
481 S_028A0C_LINE_PATTERN(state->line_stipple_pattern) |
482 S_028A0C_REPEAT_COUNT(state->line_stipple_factor) : 0;
483 rs->pa_cl_clip_cntl =
484 S_028810_DX_CLIP_SPACE_DEF(state->clip_halfz) |
485 S_028810_ZCLIP_NEAR_DISABLE(!state->depth_clip) |
486 S_028810_ZCLIP_FAR_DISABLE(!state->depth_clip) |
487 S_028810_DX_LINEAR_ATTR_CLIP_ENA(1) |
488 S_028810_DX_RASTERIZATION_KILL(state->rasterizer_discard);
489 rs->multisample_enable = state->multisample;
490
491 /* offset */
492 rs->offset_units = state->offset_units;
493 rs->offset_scale = state->offset_scale * 16.0f;
494 rs->offset_enable = state->offset_point || state->offset_line || state->offset_tri;
495 rs->offset_units_unscaled = state->offset_units_unscaled;
496
497 if (state->point_size_per_vertex) {
498 psize_min = util_get_min_point_size(state);
499 psize_max = 8192;
500 } else {
501 /* Force the point size to be as if the vertex output was disabled. */
502 psize_min = state->point_size;
503 psize_max = state->point_size;
504 }
505
506 spi_interp = S_0286D4_FLAT_SHADE_ENA(1);
507 if (state->sprite_coord_enable) {
508 spi_interp |= S_0286D4_PNT_SPRITE_ENA(1) |
509 S_0286D4_PNT_SPRITE_OVRD_X(2) |
510 S_0286D4_PNT_SPRITE_OVRD_Y(3) |
511 S_0286D4_PNT_SPRITE_OVRD_Z(0) |
512 S_0286D4_PNT_SPRITE_OVRD_W(1);
513 if (state->sprite_coord_mode != PIPE_SPRITE_COORD_UPPER_LEFT) {
514 spi_interp |= S_0286D4_PNT_SPRITE_TOP_1(1);
515 }
516 }
517
518 r600_store_context_reg_seq(&rs->buffer, R_028A00_PA_SU_POINT_SIZE, 3);
519 /* point size 12.4 fixed point (divide by two, because 0.5 = 1 pixel) */
520 tmp = r600_pack_float_12p4(state->point_size/2);
521 r600_store_value(&rs->buffer, /* R_028A00_PA_SU_POINT_SIZE */
522 S_028A00_HEIGHT(tmp) | S_028A00_WIDTH(tmp));
523 r600_store_value(&rs->buffer, /* R_028A04_PA_SU_POINT_MINMAX */
524 S_028A04_MIN_SIZE(r600_pack_float_12p4(psize_min/2)) |
525 S_028A04_MAX_SIZE(r600_pack_float_12p4(psize_max/2)));
526 r600_store_value(&rs->buffer, /* R_028A08_PA_SU_LINE_CNTL */
527 S_028A08_WIDTH((unsigned)(state->line_width * 8)));
528
529 r600_store_context_reg(&rs->buffer, R_0286D4_SPI_INTERP_CONTROL_0, spi_interp);
530 r600_store_context_reg(&rs->buffer, R_028A48_PA_SC_MODE_CNTL_0,
531 S_028A48_MSAA_ENABLE(state->multisample) |
532 S_028A48_VPORT_SCISSOR_ENABLE(1) |
533 S_028A48_LINE_STIPPLE_ENABLE(state->line_stipple_enable));
534
535 if (rctx->b.chip_class == CAYMAN) {
536 r600_store_context_reg(&rs->buffer, CM_R_028BE4_PA_SU_VTX_CNTL,
537 S_028C08_PIX_CENTER_HALF(state->half_pixel_center) |
538 S_028C08_QUANT_MODE(V_028C08_X_1_256TH));
539 } else {
540 r600_store_context_reg(&rs->buffer, R_028C08_PA_SU_VTX_CNTL,
541 S_028C08_PIX_CENTER_HALF(state->half_pixel_center) |
542 S_028C08_QUANT_MODE(V_028C08_X_1_256TH));
543 }
544
545 r600_store_context_reg(&rs->buffer, R_028B7C_PA_SU_POLY_OFFSET_CLAMP, fui(state->offset_clamp));
546 r600_store_context_reg(&rs->buffer, R_028814_PA_SU_SC_MODE_CNTL,
547 S_028814_PROVOKING_VTX_LAST(!state->flatshade_first) |
548 S_028814_CULL_FRONT((state->cull_face & PIPE_FACE_FRONT) ? 1 : 0) |
549 S_028814_CULL_BACK((state->cull_face & PIPE_FACE_BACK) ? 1 : 0) |
550 S_028814_FACE(!state->front_ccw) |
551 S_028814_POLY_OFFSET_FRONT_ENABLE(util_get_offset(state, state->fill_front)) |
552 S_028814_POLY_OFFSET_BACK_ENABLE(util_get_offset(state, state->fill_back)) |
553 S_028814_POLY_OFFSET_PARA_ENABLE(state->offset_point || state->offset_line) |
554 S_028814_POLY_MODE(state->fill_front != PIPE_POLYGON_MODE_FILL ||
555 state->fill_back != PIPE_POLYGON_MODE_FILL) |
556 S_028814_POLYMODE_FRONT_PTYPE(r600_translate_fill(state->fill_front)) |
557 S_028814_POLYMODE_BACK_PTYPE(r600_translate_fill(state->fill_back)));
558 return rs;
559 }
560
561 static void *evergreen_create_sampler_state(struct pipe_context *ctx,
562 const struct pipe_sampler_state *state)
563 {
564 struct r600_common_screen *rscreen = (struct r600_common_screen*)ctx->screen;
565 struct r600_pipe_sampler_state *ss = CALLOC_STRUCT(r600_pipe_sampler_state);
566 unsigned max_aniso = rscreen->force_aniso >= 0 ? rscreen->force_aniso
567 : state->max_anisotropy;
568 unsigned max_aniso_ratio = r600_tex_aniso_filter(max_aniso);
569
570 if (!ss) {
571 return NULL;
572 }
573
574 ss->border_color_use = sampler_state_needs_border_color(state);
575
576 /* R_03C000_SQ_TEX_SAMPLER_WORD0_0 */
577 ss->tex_sampler_words[0] =
578 S_03C000_CLAMP_X(r600_tex_wrap(state->wrap_s)) |
579 S_03C000_CLAMP_Y(r600_tex_wrap(state->wrap_t)) |
580 S_03C000_CLAMP_Z(r600_tex_wrap(state->wrap_r)) |
581 S_03C000_XY_MAG_FILTER(eg_tex_filter(state->mag_img_filter, max_aniso)) |
582 S_03C000_XY_MIN_FILTER(eg_tex_filter(state->min_img_filter, max_aniso)) |
583 S_03C000_MIP_FILTER(r600_tex_mipfilter(state->min_mip_filter)) |
584 S_03C000_MAX_ANISO_RATIO(max_aniso_ratio) |
585 S_03C000_DEPTH_COMPARE_FUNCTION(r600_tex_compare(state->compare_func)) |
586 S_03C000_BORDER_COLOR_TYPE(ss->border_color_use ? V_03C000_SQ_TEX_BORDER_COLOR_REGISTER : 0);
587 /* R_03C004_SQ_TEX_SAMPLER_WORD1_0 */
588 ss->tex_sampler_words[1] =
589 S_03C004_MIN_LOD(S_FIXED(CLAMP(state->min_lod, 0, 15), 8)) |
590 S_03C004_MAX_LOD(S_FIXED(CLAMP(state->max_lod, 0, 15), 8));
591 /* R_03C008_SQ_TEX_SAMPLER_WORD2_0 */
592 ss->tex_sampler_words[2] =
593 S_03C008_LOD_BIAS(S_FIXED(CLAMP(state->lod_bias, -16, 16), 8)) |
594 (state->seamless_cube_map ? 0 : S_03C008_DISABLE_CUBE_WRAP(1)) |
595 S_03C008_TYPE(1);
596
597 if (ss->border_color_use) {
598 memcpy(&ss->border_color, &state->border_color, sizeof(state->border_color));
599 }
600 return ss;
601 }
602
603 static struct pipe_sampler_view *
604 texture_buffer_sampler_view(struct r600_context *rctx,
605 struct r600_pipe_sampler_view *view,
606 unsigned width0, unsigned height0)
607
608 {
609 struct r600_texture *tmp = (struct r600_texture*)view->base.texture;
610 uint64_t va;
611 int stride = util_format_get_blocksize(view->base.format);
612 unsigned format, num_format, format_comp, endian;
613 unsigned swizzle_res;
614 unsigned char swizzle[4];
615 const struct util_format_description *desc;
616 unsigned offset = view->base.u.buf.offset;
617 unsigned size = view->base.u.buf.size;
618
619 swizzle[0] = view->base.swizzle_r;
620 swizzle[1] = view->base.swizzle_g;
621 swizzle[2] = view->base.swizzle_b;
622 swizzle[3] = view->base.swizzle_a;
623
624 r600_vertex_data_type(view->base.format,
625 &format, &num_format, &format_comp,
626 &endian);
627
628 desc = util_format_description(view->base.format);
629
630 swizzle_res = r600_get_swizzle_combined(desc->swizzle, swizzle, TRUE);
631
632 va = tmp->resource.gpu_address + offset;
633 view->tex_resource = &tmp->resource;
634
635 view->skip_mip_address_reloc = true;
636 view->tex_resource_words[0] = va;
637 view->tex_resource_words[1] = size - 1;
638 view->tex_resource_words[2] = S_030008_BASE_ADDRESS_HI(va >> 32UL) |
639 S_030008_STRIDE(stride) |
640 S_030008_DATA_FORMAT(format) |
641 S_030008_NUM_FORMAT_ALL(num_format) |
642 S_030008_FORMAT_COMP_ALL(format_comp) |
643 S_030008_ENDIAN_SWAP(endian);
644 view->tex_resource_words[3] = swizzle_res;
645 /*
646 * in theory dword 4 is for number of elements, for use with resinfo,
647 * but it seems to utterly fail to work, the amd gpu shader analyser
648 * uses a const buffer to store the element sizes for buffer txq
649 */
650 view->tex_resource_words[4] = 0;
651 view->tex_resource_words[5] = view->tex_resource_words[6] = 0;
652 view->tex_resource_words[7] = S_03001C_TYPE(V_03001C_SQ_TEX_VTX_VALID_BUFFER);
653
654 if (tmp->resource.gpu_address)
655 LIST_ADDTAIL(&view->list, &rctx->b.texture_buffers);
656 return &view->base;
657 }
658
659 struct pipe_sampler_view *
660 evergreen_create_sampler_view_custom(struct pipe_context *ctx,
661 struct pipe_resource *texture,
662 const struct pipe_sampler_view *state,
663 unsigned width0, unsigned height0,
664 unsigned force_level)
665 {
666 struct r600_context *rctx = (struct r600_context*)ctx;
667 struct r600_screen *rscreen = (struct r600_screen*)ctx->screen;
668 struct r600_pipe_sampler_view *view = CALLOC_STRUCT(r600_pipe_sampler_view);
669 struct r600_texture *tmp = (struct r600_texture*)texture;
670 unsigned format, endian;
671 uint32_t word4 = 0, yuv_format = 0, pitch = 0;
672 unsigned char swizzle[4], array_mode = 0, non_disp_tiling = 0;
673 unsigned height, depth, width;
674 unsigned macro_aspect, tile_split, bankh, bankw, nbanks, fmask_bankh;
675 enum pipe_format pipe_format = state->format;
676 struct radeon_surf_level *surflevel;
677 unsigned base_level, first_level, last_level;
678 unsigned dim, last_layer;
679 uint64_t va;
680 bool do_endian_swap = FALSE;
681
682 if (!view)
683 return NULL;
684
685 /* initialize base object */
686 view->base = *state;
687 view->base.texture = NULL;
688 pipe_reference(NULL, &texture->reference);
689 view->base.texture = texture;
690 view->base.reference.count = 1;
691 view->base.context = ctx;
692
693 if (state->target == PIPE_BUFFER)
694 return texture_buffer_sampler_view(rctx, view, width0, height0);
695
696 swizzle[0] = state->swizzle_r;
697 swizzle[1] = state->swizzle_g;
698 swizzle[2] = state->swizzle_b;
699 swizzle[3] = state->swizzle_a;
700
701 tile_split = tmp->surface.tile_split;
702 surflevel = tmp->surface.level;
703
704 /* Texturing with separate depth and stencil. */
705 if (tmp->db_compatible) {
706 switch (pipe_format) {
707 case PIPE_FORMAT_Z32_FLOAT_S8X24_UINT:
708 pipe_format = PIPE_FORMAT_Z32_FLOAT;
709 break;
710 case PIPE_FORMAT_X8Z24_UNORM:
711 case PIPE_FORMAT_S8_UINT_Z24_UNORM:
712 /* Z24 is always stored like this for DB
713 * compatibility.
714 */
715 pipe_format = PIPE_FORMAT_Z24X8_UNORM;
716 break;
717 case PIPE_FORMAT_X24S8_UINT:
718 case PIPE_FORMAT_S8X24_UINT:
719 case PIPE_FORMAT_X32_S8X24_UINT:
720 pipe_format = PIPE_FORMAT_S8_UINT;
721 tile_split = tmp->surface.stencil_tile_split;
722 surflevel = tmp->surface.stencil_level;
723 break;
724 default:;
725 }
726 }
727
728 if (R600_BIG_ENDIAN)
729 do_endian_swap = !tmp->db_compatible;
730
731 format = r600_translate_texformat(ctx->screen, pipe_format,
732 swizzle,
733 &word4, &yuv_format, do_endian_swap);
734 assert(format != ~0);
735 if (format == ~0) {
736 FREE(view);
737 return NULL;
738 }
739
740 endian = r600_colorformat_endian_swap(format, do_endian_swap);
741
742 base_level = 0;
743 first_level = state->u.tex.first_level;
744 last_level = state->u.tex.last_level;
745 width = width0;
746 height = height0;
747 depth = texture->depth0;
748
749 if (force_level) {
750 base_level = force_level;
751 first_level = 0;
752 last_level = 0;
753 width = u_minify(width, force_level);
754 height = u_minify(height, force_level);
755 depth = u_minify(depth, force_level);
756 }
757
758 pitch = surflevel[base_level].nblk_x * util_format_get_blockwidth(pipe_format);
759 non_disp_tiling = tmp->non_disp_tiling;
760
761 switch (surflevel[base_level].mode) {
762 default:
763 case RADEON_SURF_MODE_LINEAR_ALIGNED:
764 array_mode = V_028C70_ARRAY_LINEAR_ALIGNED;
765 break;
766 case RADEON_SURF_MODE_2D:
767 array_mode = V_028C70_ARRAY_2D_TILED_THIN1;
768 break;
769 case RADEON_SURF_MODE_1D:
770 array_mode = V_028C70_ARRAY_1D_TILED_THIN1;
771 break;
772 }
773 macro_aspect = tmp->surface.mtilea;
774 bankw = tmp->surface.bankw;
775 bankh = tmp->surface.bankh;
776 tile_split = eg_tile_split(tile_split);
777 macro_aspect = eg_macro_tile_aspect(macro_aspect);
778 bankw = eg_bank_wh(bankw);
779 bankh = eg_bank_wh(bankh);
780 fmask_bankh = eg_bank_wh(tmp->fmask.bank_height);
781
782 /* 128 bit formats require tile type = 1 */
783 if (rscreen->b.chip_class == CAYMAN) {
784 if (util_format_get_blocksize(pipe_format) >= 16)
785 non_disp_tiling = 1;
786 }
787 nbanks = eg_num_banks(rscreen->b.info.r600_num_banks);
788
789 if (state->target == PIPE_TEXTURE_1D_ARRAY) {
790 height = 1;
791 depth = texture->array_size;
792 } else if (state->target == PIPE_TEXTURE_2D_ARRAY) {
793 depth = texture->array_size;
794 } else if (state->target == PIPE_TEXTURE_CUBE_ARRAY)
795 depth = texture->array_size / 6;
796
797 va = tmp->resource.gpu_address;
798
799 if (state->format == PIPE_FORMAT_X24S8_UINT ||
800 state->format == PIPE_FORMAT_S8X24_UINT ||
801 state->format == PIPE_FORMAT_X32_S8X24_UINT ||
802 state->format == PIPE_FORMAT_S8_UINT)
803 view->is_stencil_sampler = true;
804
805 view->tex_resource = &tmp->resource;
806
807 /* array type views and views into array types need to use layer offset */
808 dim = state->target;
809 if (state->target != PIPE_TEXTURE_CUBE)
810 dim = MAX2(state->target, texture->target);
811
812 view->tex_resource_words[0] = (S_030000_DIM(r600_tex_dim(dim, texture->nr_samples)) |
813 S_030000_PITCH((pitch / 8) - 1) |
814 S_030000_TEX_WIDTH(width - 1));
815 if (rscreen->b.chip_class == CAYMAN)
816 view->tex_resource_words[0] |= CM_S_030000_NON_DISP_TILING_ORDER(non_disp_tiling);
817 else
818 view->tex_resource_words[0] |= S_030000_NON_DISP_TILING_ORDER(non_disp_tiling);
819 view->tex_resource_words[1] = (S_030004_TEX_HEIGHT(height - 1) |
820 S_030004_TEX_DEPTH(depth - 1) |
821 S_030004_ARRAY_MODE(array_mode));
822 view->tex_resource_words[2] = (surflevel[base_level].offset + va) >> 8;
823
824 /* TEX_RESOURCE_WORD3.MIP_ADDRESS */
825 if (texture->nr_samples > 1 && rscreen->has_compressed_msaa_texturing) {
826 if (tmp->is_depth) {
827 /* disable FMASK (0 = disabled) */
828 view->tex_resource_words[3] = 0;
829 view->skip_mip_address_reloc = true;
830 } else {
831 /* FMASK should be in MIP_ADDRESS for multisample textures */
832 view->tex_resource_words[3] = (tmp->fmask.offset + va) >> 8;
833 }
834 } else if (last_level && texture->nr_samples <= 1) {
835 view->tex_resource_words[3] = (surflevel[1].offset + va) >> 8;
836 } else {
837 view->tex_resource_words[3] = (surflevel[base_level].offset + va) >> 8;
838 }
839
840 last_layer = state->u.tex.last_layer;
841 if (state->target != texture->target && depth == 1) {
842 last_layer = state->u.tex.first_layer;
843 }
844 view->tex_resource_words[4] = (word4 |
845 S_030010_ENDIAN_SWAP(endian));
846 view->tex_resource_words[5] = S_030014_BASE_ARRAY(state->u.tex.first_layer) |
847 S_030014_LAST_ARRAY(last_layer);
848 view->tex_resource_words[6] = S_030018_TILE_SPLIT(tile_split);
849
850 if (texture->nr_samples > 1) {
851 unsigned log_samples = util_logbase2(texture->nr_samples);
852 if (rscreen->b.chip_class == CAYMAN) {
853 view->tex_resource_words[4] |= S_030010_LOG2_NUM_FRAGMENTS(log_samples);
854 }
855 /* LAST_LEVEL holds log2(nr_samples) for multisample textures */
856 view->tex_resource_words[5] |= S_030014_LAST_LEVEL(log_samples);
857 view->tex_resource_words[6] |= S_030018_FMASK_BANK_HEIGHT(fmask_bankh);
858 } else {
859 bool no_mip = first_level == last_level;
860
861 view->tex_resource_words[4] |= S_030010_BASE_LEVEL(first_level);
862 view->tex_resource_words[5] |= S_030014_LAST_LEVEL(last_level);
863 /* aniso max 16 samples */
864 view->tex_resource_words[6] |= S_030018_MAX_ANISO_RATIO(no_mip ? 0 : 4);
865 }
866
867 view->tex_resource_words[7] = S_03001C_DATA_FORMAT(format) |
868 S_03001C_TYPE(V_03001C_SQ_TEX_VTX_VALID_TEXTURE) |
869 S_03001C_BANK_WIDTH(bankw) |
870 S_03001C_BANK_HEIGHT(bankh) |
871 S_03001C_MACRO_TILE_ASPECT(macro_aspect) |
872 S_03001C_NUM_BANKS(nbanks) |
873 S_03001C_DEPTH_SAMPLE_ORDER(tmp->db_compatible);
874 return &view->base;
875 }
876
877 static struct pipe_sampler_view *
878 evergreen_create_sampler_view(struct pipe_context *ctx,
879 struct pipe_resource *tex,
880 const struct pipe_sampler_view *state)
881 {
882 return evergreen_create_sampler_view_custom(ctx, tex, state,
883 tex->width0, tex->height0, 0);
884 }
885
886 static void evergreen_emit_config_state(struct r600_context *rctx, struct r600_atom *atom)
887 {
888 struct radeon_winsys_cs *cs = rctx->b.gfx.cs;
889 struct r600_config_state *a = (struct r600_config_state*)atom;
890
891 radeon_set_config_reg_seq(cs, R_008C04_SQ_GPR_RESOURCE_MGMT_1, 3);
892 if (a->dyn_gpr_enabled) {
893 radeon_emit(cs, S_008C04_NUM_CLAUSE_TEMP_GPRS(rctx->r6xx_num_clause_temp_gprs));
894 radeon_emit(cs, 0);
895 radeon_emit(cs, 0);
896 } else {
897 radeon_emit(cs, a->sq_gpr_resource_mgmt_1);
898 radeon_emit(cs, a->sq_gpr_resource_mgmt_2);
899 radeon_emit(cs, a->sq_gpr_resource_mgmt_3);
900 }
901 radeon_set_config_reg(cs, R_008D8C_SQ_DYN_GPR_CNTL_PS_FLUSH_REQ, (a->dyn_gpr_enabled << 8));
902 if (a->dyn_gpr_enabled) {
903 radeon_set_context_reg(cs, R_028838_SQ_DYN_GPR_RESOURCE_LIMIT_1,
904 S_028838_PS_GPRS(0x1e) |
905 S_028838_VS_GPRS(0x1e) |
906 S_028838_GS_GPRS(0x1e) |
907 S_028838_ES_GPRS(0x1e) |
908 S_028838_HS_GPRS(0x1e) |
909 S_028838_LS_GPRS(0x1e)); /* workaround for hw issues with dyn gpr - must set all limits to 240 instead of 0, 0x1e == 240 / 8*/
910 }
911 }
912
913 static void evergreen_emit_clip_state(struct r600_context *rctx, struct r600_atom *atom)
914 {
915 struct radeon_winsys_cs *cs = rctx->b.gfx.cs;
916 struct pipe_clip_state *state = &rctx->clip_state.state;
917
918 radeon_set_context_reg_seq(cs, R_0285BC_PA_CL_UCP0_X, 6*4);
919 radeon_emit_array(cs, (unsigned*)state, 6*4);
920 }
921
922 static void evergreen_set_polygon_stipple(struct pipe_context *ctx,
923 const struct pipe_poly_stipple *state)
924 {
925 }
926
927 static void evergreen_get_scissor_rect(struct r600_context *rctx,
928 unsigned tl_x, unsigned tl_y, unsigned br_x, unsigned br_y,
929 uint32_t *tl, uint32_t *br)
930 {
931 struct pipe_scissor_state scissor = {tl_x, tl_y, br_x, br_y};
932
933 evergreen_apply_scissor_bug_workaround(&rctx->b, &scissor);
934
935 *tl = S_028240_TL_X(scissor.minx) | S_028240_TL_Y(scissor.miny);
936 *br = S_028244_BR_X(scissor.maxx) | S_028244_BR_Y(scissor.maxy);
937 }
938
939 /**
940 * This function intializes the CB* register values for RATs. It is meant
941 * to be used for 1D aligned buffers that do not have an associated
942 * radeon_surf.
943 */
944 void evergreen_init_color_surface_rat(struct r600_context *rctx,
945 struct r600_surface *surf)
946 {
947 struct pipe_resource *pipe_buffer = surf->base.texture;
948 unsigned format = r600_translate_colorformat(rctx->b.chip_class,
949 surf->base.format, FALSE);
950 unsigned endian = r600_colorformat_endian_swap(format, FALSE);
951 unsigned swap = r600_translate_colorswap(surf->base.format, FALSE);
952 unsigned block_size =
953 align(util_format_get_blocksize(pipe_buffer->format), 4);
954 unsigned pitch_alignment =
955 MAX2(64, rctx->screen->b.info.pipe_interleave_bytes / block_size);
956 unsigned pitch = align(pipe_buffer->width0, pitch_alignment);
957
958 surf->cb_color_base = r600_resource(pipe_buffer)->gpu_address >> 8;
959
960 surf->cb_color_pitch = (pitch / 8) - 1;
961
962 surf->cb_color_slice = 0;
963
964 surf->cb_color_view = 0;
965
966 surf->cb_color_info =
967 S_028C70_ENDIAN(endian)
968 | S_028C70_FORMAT(format)
969 | S_028C70_ARRAY_MODE(V_028C70_ARRAY_LINEAR_ALIGNED)
970 | S_028C70_NUMBER_TYPE(V_028C70_NUMBER_UINT)
971 | S_028C70_COMP_SWAP(swap)
972 | S_028C70_BLEND_BYPASS(1) /* We must set this bit because we
973 * are using NUMBER_UINT */
974 | S_028C70_RAT(1)
975 ;
976
977 surf->cb_color_attrib = S_028C74_NON_DISP_TILING_ORDER(1);
978
979 /* For buffers, CB_COLOR0_DIM needs to be set to the number of
980 * elements. */
981 surf->cb_color_dim = pipe_buffer->width0;
982
983 /* Set the buffer range the GPU will have access to: */
984 util_range_add(&r600_resource(pipe_buffer)->valid_buffer_range,
985 0, pipe_buffer->width0);
986
987 surf->cb_color_fmask = surf->cb_color_base;
988 surf->cb_color_fmask_slice = 0;
989 }
990
991 void evergreen_init_color_surface(struct r600_context *rctx,
992 struct r600_surface *surf)
993 {
994 struct r600_screen *rscreen = rctx->screen;
995 struct r600_texture *rtex = (struct r600_texture*)surf->base.texture;
996 unsigned level = surf->base.u.tex.level;
997 unsigned pitch, slice;
998 unsigned color_info, color_attrib, color_dim = 0, color_view;
999 unsigned format, swap, ntype, endian;
1000 uint64_t offset, base_offset;
1001 unsigned non_disp_tiling, macro_aspect, tile_split, bankh, bankw, fmask_bankh, nbanks;
1002 const struct util_format_description *desc;
1003 int i;
1004 bool blend_clamp = 0, blend_bypass = 0, do_endian_swap = FALSE;
1005
1006 offset = rtex->surface.level[level].offset;
1007 color_view = S_028C6C_SLICE_START(surf->base.u.tex.first_layer) |
1008 S_028C6C_SLICE_MAX(surf->base.u.tex.last_layer);
1009
1010 pitch = (rtex->surface.level[level].nblk_x) / 8 - 1;
1011 slice = (rtex->surface.level[level].nblk_x * rtex->surface.level[level].nblk_y) / 64;
1012 if (slice) {
1013 slice = slice - 1;
1014 }
1015 color_info = 0;
1016 switch (rtex->surface.level[level].mode) {
1017 default:
1018 case RADEON_SURF_MODE_LINEAR_ALIGNED:
1019 color_info = S_028C70_ARRAY_MODE(V_028C70_ARRAY_LINEAR_ALIGNED);
1020 non_disp_tiling = 1;
1021 break;
1022 case RADEON_SURF_MODE_1D:
1023 color_info = S_028C70_ARRAY_MODE(V_028C70_ARRAY_1D_TILED_THIN1);
1024 non_disp_tiling = rtex->non_disp_tiling;
1025 break;
1026 case RADEON_SURF_MODE_2D:
1027 color_info = S_028C70_ARRAY_MODE(V_028C70_ARRAY_2D_TILED_THIN1);
1028 non_disp_tiling = rtex->non_disp_tiling;
1029 break;
1030 }
1031 tile_split = rtex->surface.tile_split;
1032 macro_aspect = rtex->surface.mtilea;
1033 bankw = rtex->surface.bankw;
1034 bankh = rtex->surface.bankh;
1035 if (rtex->fmask.size)
1036 fmask_bankh = rtex->fmask.bank_height;
1037 else
1038 fmask_bankh = rtex->surface.bankh;
1039 tile_split = eg_tile_split(tile_split);
1040 macro_aspect = eg_macro_tile_aspect(macro_aspect);
1041 bankw = eg_bank_wh(bankw);
1042 bankh = eg_bank_wh(bankh);
1043 fmask_bankh = eg_bank_wh(fmask_bankh);
1044
1045 /* 128 bit formats require tile type = 1 */
1046 if (rscreen->b.chip_class == CAYMAN) {
1047 if (util_format_get_blocksize(surf->base.format) >= 16)
1048 non_disp_tiling = 1;
1049 }
1050 nbanks = eg_num_banks(rscreen->b.info.r600_num_banks);
1051 desc = util_format_description(surf->base.format);
1052 for (i = 0; i < 4; i++) {
1053 if (desc->channel[i].type != UTIL_FORMAT_TYPE_VOID) {
1054 break;
1055 }
1056 }
1057
1058 color_attrib = S_028C74_TILE_SPLIT(tile_split)|
1059 S_028C74_NUM_BANKS(nbanks) |
1060 S_028C74_BANK_WIDTH(bankw) |
1061 S_028C74_BANK_HEIGHT(bankh) |
1062 S_028C74_MACRO_TILE_ASPECT(macro_aspect) |
1063 S_028C74_NON_DISP_TILING_ORDER(non_disp_tiling) |
1064 S_028C74_FMASK_BANK_HEIGHT(fmask_bankh);
1065
1066 if (rctx->b.chip_class == CAYMAN) {
1067 color_attrib |= S_028C74_FORCE_DST_ALPHA_1(desc->swizzle[3] ==
1068 PIPE_SWIZZLE_1);
1069
1070 if (rtex->resource.b.b.nr_samples > 1) {
1071 unsigned log_samples = util_logbase2(rtex->resource.b.b.nr_samples);
1072 color_attrib |= S_028C74_NUM_SAMPLES(log_samples) |
1073 S_028C74_NUM_FRAGMENTS(log_samples);
1074 }
1075 }
1076
1077 ntype = V_028C70_NUMBER_UNORM;
1078 if (desc->colorspace == UTIL_FORMAT_COLORSPACE_SRGB)
1079 ntype = V_028C70_NUMBER_SRGB;
1080 else if (desc->channel[i].type == UTIL_FORMAT_TYPE_SIGNED) {
1081 if (desc->channel[i].normalized)
1082 ntype = V_028C70_NUMBER_SNORM;
1083 else if (desc->channel[i].pure_integer)
1084 ntype = V_028C70_NUMBER_SINT;
1085 } else if (desc->channel[i].type == UTIL_FORMAT_TYPE_UNSIGNED) {
1086 if (desc->channel[i].normalized)
1087 ntype = V_028C70_NUMBER_UNORM;
1088 else if (desc->channel[i].pure_integer)
1089 ntype = V_028C70_NUMBER_UINT;
1090 }
1091
1092 if (R600_BIG_ENDIAN)
1093 do_endian_swap = !rtex->db_compatible;
1094
1095 format = r600_translate_colorformat(rctx->b.chip_class, surf->base.format,
1096 do_endian_swap);
1097 assert(format != ~0);
1098
1099 swap = r600_translate_colorswap(surf->base.format, do_endian_swap);
1100 assert(swap != ~0);
1101
1102 endian = r600_colorformat_endian_swap(format, do_endian_swap);
1103
1104 /* blend clamp should be set for all NORM/SRGB types */
1105 if (ntype == V_028C70_NUMBER_UNORM || ntype == V_028C70_NUMBER_SNORM ||
1106 ntype == V_028C70_NUMBER_SRGB)
1107 blend_clamp = 1;
1108
1109 /* set blend bypass according to docs if SINT/UINT or
1110 8/24 COLOR variants */
1111 if (ntype == V_028C70_NUMBER_UINT || ntype == V_028C70_NUMBER_SINT ||
1112 format == V_028C70_COLOR_8_24 || format == V_028C70_COLOR_24_8 ||
1113 format == V_028C70_COLOR_X24_8_32_FLOAT) {
1114 blend_clamp = 0;
1115 blend_bypass = 1;
1116 }
1117
1118 surf->alphatest_bypass = ntype == V_028C70_NUMBER_UINT || ntype == V_028C70_NUMBER_SINT;
1119
1120 color_info |= S_028C70_FORMAT(format) |
1121 S_028C70_COMP_SWAP(swap) |
1122 S_028C70_BLEND_CLAMP(blend_clamp) |
1123 S_028C70_BLEND_BYPASS(blend_bypass) |
1124 S_028C70_NUMBER_TYPE(ntype) |
1125 S_028C70_ENDIAN(endian);
1126
1127 /* EXPORT_NORM is an optimzation that can be enabled for better
1128 * performance in certain cases.
1129 * EXPORT_NORM can be enabled if:
1130 * - 11-bit or smaller UNORM/SNORM/SRGB
1131 * - 16-bit or smaller FLOAT
1132 */
1133 if (desc->colorspace != UTIL_FORMAT_COLORSPACE_ZS &&
1134 ((desc->channel[i].size < 12 &&
1135 desc->channel[i].type != UTIL_FORMAT_TYPE_FLOAT &&
1136 ntype != V_028C70_NUMBER_UINT && ntype != V_028C70_NUMBER_SINT) ||
1137 (desc->channel[i].size < 17 &&
1138 desc->channel[i].type == UTIL_FORMAT_TYPE_FLOAT))) {
1139 color_info |= S_028C70_SOURCE_FORMAT(V_028C70_EXPORT_4C_16BPC);
1140 surf->export_16bpc = true;
1141 }
1142
1143 if (rtex->fmask.size) {
1144 color_info |= S_028C70_COMPRESSION(1);
1145 }
1146
1147 base_offset = rtex->resource.gpu_address;
1148
1149 /* XXX handle enabling of CB beyond BASE8 which has different offset */
1150 surf->cb_color_base = (base_offset + offset) >> 8;
1151 surf->cb_color_dim = color_dim;
1152 surf->cb_color_info = color_info;
1153 surf->cb_color_pitch = S_028C64_PITCH_TILE_MAX(pitch);
1154 surf->cb_color_slice = S_028C68_SLICE_TILE_MAX(slice);
1155 surf->cb_color_view = color_view;
1156 surf->cb_color_attrib = color_attrib;
1157 if (rtex->fmask.size) {
1158 surf->cb_color_fmask = (base_offset + rtex->fmask.offset) >> 8;
1159 surf->cb_color_fmask_slice = S_028C88_TILE_MAX(rtex->fmask.slice_tile_max);
1160 } else {
1161 surf->cb_color_fmask = surf->cb_color_base;
1162 surf->cb_color_fmask_slice = S_028C88_TILE_MAX(slice);
1163 }
1164
1165 surf->color_initialized = true;
1166 }
1167
1168 static void evergreen_init_depth_surface(struct r600_context *rctx,
1169 struct r600_surface *surf)
1170 {
1171 struct r600_screen *rscreen = rctx->screen;
1172 struct r600_texture *rtex = (struct r600_texture*)surf->base.texture;
1173 unsigned level = surf->base.u.tex.level;
1174 struct radeon_surf_level *levelinfo = &rtex->surface.level[level];
1175 uint64_t offset;
1176 unsigned format, array_mode;
1177 unsigned macro_aspect, tile_split, bankh, bankw, nbanks;
1178
1179
1180 format = r600_translate_dbformat(surf->base.format);
1181 assert(format != ~0);
1182
1183 offset = rtex->resource.gpu_address;
1184 offset += rtex->surface.level[level].offset;
1185
1186 switch (rtex->surface.level[level].mode) {
1187 case RADEON_SURF_MODE_2D:
1188 array_mode = V_028C70_ARRAY_2D_TILED_THIN1;
1189 break;
1190 case RADEON_SURF_MODE_1D:
1191 case RADEON_SURF_MODE_LINEAR_ALIGNED:
1192 default:
1193 array_mode = V_028C70_ARRAY_1D_TILED_THIN1;
1194 break;
1195 }
1196 tile_split = rtex->surface.tile_split;
1197 macro_aspect = rtex->surface.mtilea;
1198 bankw = rtex->surface.bankw;
1199 bankh = rtex->surface.bankh;
1200 tile_split = eg_tile_split(tile_split);
1201 macro_aspect = eg_macro_tile_aspect(macro_aspect);
1202 bankw = eg_bank_wh(bankw);
1203 bankh = eg_bank_wh(bankh);
1204 nbanks = eg_num_banks(rscreen->b.info.r600_num_banks);
1205 offset >>= 8;
1206
1207 surf->db_z_info = S_028040_ARRAY_MODE(array_mode) |
1208 S_028040_FORMAT(format) |
1209 S_028040_TILE_SPLIT(tile_split)|
1210 S_028040_NUM_BANKS(nbanks) |
1211 S_028040_BANK_WIDTH(bankw) |
1212 S_028040_BANK_HEIGHT(bankh) |
1213 S_028040_MACRO_TILE_ASPECT(macro_aspect);
1214 if (rscreen->b.chip_class == CAYMAN && rtex->resource.b.b.nr_samples > 1) {
1215 surf->db_z_info |= S_028040_NUM_SAMPLES(util_logbase2(rtex->resource.b.b.nr_samples));
1216 }
1217
1218 assert(levelinfo->nblk_x % 8 == 0 && levelinfo->nblk_y % 8 == 0);
1219
1220 surf->db_depth_base = offset;
1221 surf->db_depth_view = S_028008_SLICE_START(surf->base.u.tex.first_layer) |
1222 S_028008_SLICE_MAX(surf->base.u.tex.last_layer);
1223 surf->db_depth_size = S_028058_PITCH_TILE_MAX(levelinfo->nblk_x / 8 - 1) |
1224 S_028058_HEIGHT_TILE_MAX(levelinfo->nblk_y / 8 - 1);
1225 surf->db_depth_slice = S_02805C_SLICE_TILE_MAX(levelinfo->nblk_x *
1226 levelinfo->nblk_y / 64 - 1);
1227
1228 if (rtex->surface.flags & RADEON_SURF_SBUFFER) {
1229 uint64_t stencil_offset;
1230 unsigned stile_split = rtex->surface.stencil_tile_split;
1231
1232 stile_split = eg_tile_split(stile_split);
1233
1234 stencil_offset = rtex->surface.stencil_level[level].offset;
1235 stencil_offset += rtex->resource.gpu_address;
1236
1237 surf->db_stencil_base = stencil_offset >> 8;
1238 surf->db_stencil_info = S_028044_FORMAT(V_028044_STENCIL_8) |
1239 S_028044_TILE_SPLIT(stile_split);
1240 } else {
1241 surf->db_stencil_base = offset;
1242 /* DRM 2.6.18 allows the INVALID format to disable stencil.
1243 * Older kernels are out of luck. */
1244 surf->db_stencil_info = rctx->screen->b.info.drm_minor >= 18 ?
1245 S_028044_FORMAT(V_028044_STENCIL_INVALID) :
1246 S_028044_FORMAT(V_028044_STENCIL_8);
1247 }
1248
1249 /* use htile only for first level */
1250 if (rtex->htile_buffer && !level) {
1251 uint64_t va = rtex->htile_buffer->gpu_address;
1252 surf->db_htile_data_base = va >> 8;
1253 surf->db_htile_surface = S_028ABC_HTILE_WIDTH(1) |
1254 S_028ABC_HTILE_HEIGHT(1) |
1255 S_028ABC_FULL_CACHE(1);
1256 surf->db_z_info |= S_028040_TILE_SURFACE_ENABLE(1);
1257 surf->db_preload_control = 0;
1258 }
1259
1260 surf->depth_initialized = true;
1261 }
1262
1263 static void evergreen_set_framebuffer_state(struct pipe_context *ctx,
1264 const struct pipe_framebuffer_state *state)
1265 {
1266 struct r600_context *rctx = (struct r600_context *)ctx;
1267 struct r600_surface *surf;
1268 struct r600_texture *rtex;
1269 uint32_t i, log_samples;
1270
1271 /* Flush TC when changing the framebuffer state, because the only
1272 * client not using TC that can change textures is the framebuffer.
1273 * Other places don't typically have to flush TC.
1274 */
1275 rctx->b.flags |= R600_CONTEXT_WAIT_3D_IDLE |
1276 R600_CONTEXT_FLUSH_AND_INV |
1277 R600_CONTEXT_FLUSH_AND_INV_CB |
1278 R600_CONTEXT_FLUSH_AND_INV_CB_META |
1279 R600_CONTEXT_FLUSH_AND_INV_DB |
1280 R600_CONTEXT_FLUSH_AND_INV_DB_META |
1281 R600_CONTEXT_INV_TEX_CACHE;
1282
1283 util_copy_framebuffer_state(&rctx->framebuffer.state, state);
1284
1285 /* Colorbuffers. */
1286 rctx->framebuffer.export_16bpc = state->nr_cbufs != 0;
1287 rctx->framebuffer.cb0_is_integer = state->nr_cbufs && state->cbufs[0] &&
1288 util_format_is_pure_integer(state->cbufs[0]->format);
1289 rctx->framebuffer.compressed_cb_mask = 0;
1290 rctx->framebuffer.nr_samples = util_framebuffer_get_num_samples(state);
1291
1292 for (i = 0; i < state->nr_cbufs; i++) {
1293 surf = (struct r600_surface*)state->cbufs[i];
1294 if (!surf)
1295 continue;
1296
1297 rtex = (struct r600_texture*)surf->base.texture;
1298
1299 r600_context_add_resource_size(ctx, state->cbufs[i]->texture);
1300
1301 if (!surf->color_initialized) {
1302 evergreen_init_color_surface(rctx, surf);
1303 }
1304
1305 if (!surf->export_16bpc) {
1306 rctx->framebuffer.export_16bpc = false;
1307 }
1308
1309 if (rtex->fmask.size && rtex->cmask.size) {
1310 rctx->framebuffer.compressed_cb_mask |= 1 << i;
1311 }
1312 }
1313
1314 /* Update alpha-test state dependencies.
1315 * Alpha-test is done on the first colorbuffer only. */
1316 if (state->nr_cbufs) {
1317 bool alphatest_bypass = false;
1318 bool export_16bpc = true;
1319
1320 surf = (struct r600_surface*)state->cbufs[0];
1321 if (surf) {
1322 alphatest_bypass = surf->alphatest_bypass;
1323 export_16bpc = surf->export_16bpc;
1324 }
1325
1326 if (rctx->alphatest_state.bypass != alphatest_bypass) {
1327 rctx->alphatest_state.bypass = alphatest_bypass;
1328 r600_mark_atom_dirty(rctx, &rctx->alphatest_state.atom);
1329 }
1330 if (rctx->alphatest_state.cb0_export_16bpc != export_16bpc) {
1331 rctx->alphatest_state.cb0_export_16bpc = export_16bpc;
1332 r600_mark_atom_dirty(rctx, &rctx->alphatest_state.atom);
1333 }
1334 }
1335
1336 /* ZS buffer. */
1337 if (state->zsbuf) {
1338 surf = (struct r600_surface*)state->zsbuf;
1339
1340 r600_context_add_resource_size(ctx, state->zsbuf->texture);
1341
1342 if (!surf->depth_initialized) {
1343 evergreen_init_depth_surface(rctx, surf);
1344 }
1345
1346 if (state->zsbuf->format != rctx->poly_offset_state.zs_format) {
1347 rctx->poly_offset_state.zs_format = state->zsbuf->format;
1348 r600_mark_atom_dirty(rctx, &rctx->poly_offset_state.atom);
1349 }
1350
1351 if (rctx->db_state.rsurf != surf) {
1352 rctx->db_state.rsurf = surf;
1353 r600_mark_atom_dirty(rctx, &rctx->db_state.atom);
1354 r600_mark_atom_dirty(rctx, &rctx->db_misc_state.atom);
1355 }
1356 } else if (rctx->db_state.rsurf) {
1357 rctx->db_state.rsurf = NULL;
1358 r600_mark_atom_dirty(rctx, &rctx->db_state.atom);
1359 r600_mark_atom_dirty(rctx, &rctx->db_misc_state.atom);
1360 }
1361
1362 if (rctx->cb_misc_state.nr_cbufs != state->nr_cbufs) {
1363 rctx->cb_misc_state.nr_cbufs = state->nr_cbufs;
1364 r600_mark_atom_dirty(rctx, &rctx->cb_misc_state.atom);
1365 }
1366
1367 if (state->nr_cbufs == 0 && rctx->alphatest_state.bypass) {
1368 rctx->alphatest_state.bypass = false;
1369 r600_mark_atom_dirty(rctx, &rctx->alphatest_state.atom);
1370 }
1371
1372 log_samples = util_logbase2(rctx->framebuffer.nr_samples);
1373 /* This is for Cayman to program SAMPLE_RATE, and for RV770 to fix a hw bug. */
1374 if ((rctx->b.chip_class == CAYMAN ||
1375 rctx->b.family == CHIP_RV770) &&
1376 rctx->db_misc_state.log_samples != log_samples) {
1377 rctx->db_misc_state.log_samples = log_samples;
1378 r600_mark_atom_dirty(rctx, &rctx->db_misc_state.atom);
1379 }
1380
1381
1382 /* Calculate the CS size. */
1383 rctx->framebuffer.atom.num_dw = 4; /* SCISSOR */
1384
1385 /* MSAA. */
1386 if (rctx->b.chip_class == EVERGREEN)
1387 rctx->framebuffer.atom.num_dw += 17; /* Evergreen */
1388 else
1389 rctx->framebuffer.atom.num_dw += 28; /* Cayman */
1390
1391 /* Colorbuffers. */
1392 rctx->framebuffer.atom.num_dw += state->nr_cbufs * 23;
1393 rctx->framebuffer.atom.num_dw += state->nr_cbufs * 2;
1394 rctx->framebuffer.atom.num_dw += (12 - state->nr_cbufs) * 3;
1395
1396 /* ZS buffer. */
1397 if (state->zsbuf) {
1398 rctx->framebuffer.atom.num_dw += 24;
1399 rctx->framebuffer.atom.num_dw += 2;
1400 } else if (rctx->screen->b.info.drm_minor >= 18) {
1401 rctx->framebuffer.atom.num_dw += 4;
1402 }
1403
1404 r600_mark_atom_dirty(rctx, &rctx->framebuffer.atom);
1405
1406 r600_set_sample_locations_constant_buffer(rctx);
1407 }
1408
1409 static void evergreen_set_min_samples(struct pipe_context *ctx, unsigned min_samples)
1410 {
1411 struct r600_context *rctx = (struct r600_context *)ctx;
1412
1413 if (rctx->ps_iter_samples == min_samples)
1414 return;
1415
1416 rctx->ps_iter_samples = min_samples;
1417 if (rctx->framebuffer.nr_samples > 1) {
1418 r600_mark_atom_dirty(rctx, &rctx->framebuffer.atom);
1419 }
1420 }
1421
1422 /* 8xMSAA */
1423 static uint32_t sample_locs_8x[] = {
1424 FILL_SREG(-1, 1, 1, 5, 3, -5, 5, 3),
1425 FILL_SREG(-7, -1, -3, -7, 7, -3, -5, 7),
1426 FILL_SREG(-1, 1, 1, 5, 3, -5, 5, 3),
1427 FILL_SREG(-7, -1, -3, -7, 7, -3, -5, 7),
1428 FILL_SREG(-1, 1, 1, 5, 3, -5, 5, 3),
1429 FILL_SREG(-7, -1, -3, -7, 7, -3, -5, 7),
1430 FILL_SREG(-1, 1, 1, 5, 3, -5, 5, 3),
1431 FILL_SREG(-7, -1, -3, -7, 7, -3, -5, 7),
1432 };
1433 static unsigned max_dist_8x = 7;
1434
1435 static void evergreen_get_sample_position(struct pipe_context *ctx,
1436 unsigned sample_count,
1437 unsigned sample_index,
1438 float *out_value)
1439 {
1440 int offset, index;
1441 struct {
1442 int idx:4;
1443 } val;
1444 switch (sample_count) {
1445 case 1:
1446 default:
1447 out_value[0] = out_value[1] = 0.5;
1448 break;
1449 case 2:
1450 offset = 4 * (sample_index * 2);
1451 val.idx = (eg_sample_locs_2x[0] >> offset) & 0xf;
1452 out_value[0] = (float)(val.idx + 8) / 16.0f;
1453 val.idx = (eg_sample_locs_2x[0] >> (offset + 4)) & 0xf;
1454 out_value[1] = (float)(val.idx + 8) / 16.0f;
1455 break;
1456 case 4:
1457 offset = 4 * (sample_index * 2);
1458 val.idx = (eg_sample_locs_4x[0] >> offset) & 0xf;
1459 out_value[0] = (float)(val.idx + 8) / 16.0f;
1460 val.idx = (eg_sample_locs_4x[0] >> (offset + 4)) & 0xf;
1461 out_value[1] = (float)(val.idx + 8) / 16.0f;
1462 break;
1463 case 8:
1464 offset = 4 * (sample_index % 4 * 2);
1465 index = (sample_index / 4);
1466 val.idx = (sample_locs_8x[index] >> offset) & 0xf;
1467 out_value[0] = (float)(val.idx + 8) / 16.0f;
1468 val.idx = (sample_locs_8x[index] >> (offset + 4)) & 0xf;
1469 out_value[1] = (float)(val.idx + 8) / 16.0f;
1470 break;
1471 }
1472 }
1473
1474 static void evergreen_emit_msaa_state(struct r600_context *rctx, int nr_samples, int ps_iter_samples)
1475 {
1476
1477 struct radeon_winsys_cs *cs = rctx->b.gfx.cs;
1478 unsigned max_dist = 0;
1479
1480 switch (nr_samples) {
1481 default:
1482 nr_samples = 0;
1483 break;
1484 case 2:
1485 radeon_set_context_reg_seq(cs, R_028C1C_PA_SC_AA_SAMPLE_LOCS_0, ARRAY_SIZE(eg_sample_locs_2x));
1486 radeon_emit_array(cs, eg_sample_locs_2x, ARRAY_SIZE(eg_sample_locs_2x));
1487 max_dist = eg_max_dist_2x;
1488 break;
1489 case 4:
1490 radeon_set_context_reg_seq(cs, R_028C1C_PA_SC_AA_SAMPLE_LOCS_0, ARRAY_SIZE(eg_sample_locs_4x));
1491 radeon_emit_array(cs, eg_sample_locs_4x, ARRAY_SIZE(eg_sample_locs_4x));
1492 max_dist = eg_max_dist_4x;
1493 break;
1494 case 8:
1495 radeon_set_context_reg_seq(cs, R_028C1C_PA_SC_AA_SAMPLE_LOCS_0, ARRAY_SIZE(sample_locs_8x));
1496 radeon_emit_array(cs, sample_locs_8x, ARRAY_SIZE(sample_locs_8x));
1497 max_dist = max_dist_8x;
1498 break;
1499 }
1500
1501 if (nr_samples > 1) {
1502 radeon_set_context_reg_seq(cs, R_028C00_PA_SC_LINE_CNTL, 2);
1503 radeon_emit(cs, S_028C00_LAST_PIXEL(1) |
1504 S_028C00_EXPAND_LINE_WIDTH(1)); /* R_028C00_PA_SC_LINE_CNTL */
1505 radeon_emit(cs, S_028C04_MSAA_NUM_SAMPLES(util_logbase2(nr_samples)) |
1506 S_028C04_MAX_SAMPLE_DIST(max_dist)); /* R_028C04_PA_SC_AA_CONFIG */
1507 radeon_set_context_reg(cs, EG_R_028A4C_PA_SC_MODE_CNTL_1,
1508 EG_S_028A4C_PS_ITER_SAMPLE(ps_iter_samples > 1) |
1509 EG_S_028A4C_FORCE_EOV_CNTDWN_ENABLE(1) |
1510 EG_S_028A4C_FORCE_EOV_REZ_ENABLE(1));
1511 } else {
1512 radeon_set_context_reg_seq(cs, R_028C00_PA_SC_LINE_CNTL, 2);
1513 radeon_emit(cs, S_028C00_LAST_PIXEL(1)); /* R_028C00_PA_SC_LINE_CNTL */
1514 radeon_emit(cs, 0); /* R_028C04_PA_SC_AA_CONFIG */
1515 radeon_set_context_reg(cs, EG_R_028A4C_PA_SC_MODE_CNTL_1,
1516 EG_S_028A4C_FORCE_EOV_CNTDWN_ENABLE(1) |
1517 EG_S_028A4C_FORCE_EOV_REZ_ENABLE(1));
1518 }
1519 }
1520
1521 static void evergreen_emit_framebuffer_state(struct r600_context *rctx, struct r600_atom *atom)
1522 {
1523 struct radeon_winsys_cs *cs = rctx->b.gfx.cs;
1524 struct pipe_framebuffer_state *state = &rctx->framebuffer.state;
1525 unsigned nr_cbufs = state->nr_cbufs;
1526 unsigned i, tl, br;
1527 struct r600_texture *tex = NULL;
1528 struct r600_surface *cb = NULL;
1529
1530 /* XXX support more colorbuffers once we need them */
1531 assert(nr_cbufs <= 8);
1532 if (nr_cbufs > 8)
1533 nr_cbufs = 8;
1534
1535 /* Colorbuffers. */
1536 for (i = 0; i < nr_cbufs; i++) {
1537 unsigned reloc, cmask_reloc;
1538
1539 cb = (struct r600_surface*)state->cbufs[i];
1540 if (!cb) {
1541 radeon_set_context_reg(cs, R_028C70_CB_COLOR0_INFO + i * 0x3C,
1542 S_028C70_FORMAT(V_028C70_COLOR_INVALID));
1543 continue;
1544 }
1545
1546 tex = (struct r600_texture *)cb->base.texture;
1547 reloc = radeon_add_to_buffer_list(&rctx->b,
1548 &rctx->b.gfx,
1549 (struct r600_resource*)cb->base.texture,
1550 RADEON_USAGE_READWRITE,
1551 tex->surface.nsamples > 1 ?
1552 RADEON_PRIO_COLOR_BUFFER_MSAA :
1553 RADEON_PRIO_COLOR_BUFFER);
1554
1555 if (tex->cmask_buffer && tex->cmask_buffer != &tex->resource) {
1556 cmask_reloc = radeon_add_to_buffer_list(&rctx->b, &rctx->b.gfx,
1557 tex->cmask_buffer, RADEON_USAGE_READWRITE,
1558 RADEON_PRIO_CMASK);
1559 } else {
1560 cmask_reloc = reloc;
1561 }
1562
1563 radeon_set_context_reg_seq(cs, R_028C60_CB_COLOR0_BASE + i * 0x3C, 13);
1564 radeon_emit(cs, cb->cb_color_base); /* R_028C60_CB_COLOR0_BASE */
1565 radeon_emit(cs, cb->cb_color_pitch); /* R_028C64_CB_COLOR0_PITCH */
1566 radeon_emit(cs, cb->cb_color_slice); /* R_028C68_CB_COLOR0_SLICE */
1567 radeon_emit(cs, cb->cb_color_view); /* R_028C6C_CB_COLOR0_VIEW */
1568 radeon_emit(cs, cb->cb_color_info | tex->cb_color_info); /* R_028C70_CB_COLOR0_INFO */
1569 radeon_emit(cs, cb->cb_color_attrib); /* R_028C74_CB_COLOR0_ATTRIB */
1570 radeon_emit(cs, cb->cb_color_dim); /* R_028C78_CB_COLOR0_DIM */
1571 radeon_emit(cs, tex->cmask.base_address_reg); /* R_028C7C_CB_COLOR0_CMASK */
1572 radeon_emit(cs, tex->cmask.slice_tile_max); /* R_028C80_CB_COLOR0_CMASK_SLICE */
1573 radeon_emit(cs, cb->cb_color_fmask); /* R_028C84_CB_COLOR0_FMASK */
1574 radeon_emit(cs, cb->cb_color_fmask_slice); /* R_028C88_CB_COLOR0_FMASK_SLICE */
1575 radeon_emit(cs, tex->color_clear_value[0]); /* R_028C8C_CB_COLOR0_CLEAR_WORD0 */
1576 radeon_emit(cs, tex->color_clear_value[1]); /* R_028C90_CB_COLOR0_CLEAR_WORD1 */
1577
1578 radeon_emit(cs, PKT3(PKT3_NOP, 0, 0)); /* R_028C60_CB_COLOR0_BASE */
1579 radeon_emit(cs, reloc);
1580
1581 radeon_emit(cs, PKT3(PKT3_NOP, 0, 0)); /* R_028C74_CB_COLOR0_ATTRIB */
1582 radeon_emit(cs, reloc);
1583
1584 radeon_emit(cs, PKT3(PKT3_NOP, 0, 0)); /* R_028C7C_CB_COLOR0_CMASK */
1585 radeon_emit(cs, cmask_reloc);
1586
1587 radeon_emit(cs, PKT3(PKT3_NOP, 0, 0)); /* R_028C84_CB_COLOR0_FMASK */
1588 radeon_emit(cs, reloc);
1589 }
1590 /* set CB_COLOR1_INFO for possible dual-src blending */
1591 if (i == 1 && state->cbufs[0]) {
1592 radeon_set_context_reg(cs, R_028C70_CB_COLOR0_INFO + 1 * 0x3C,
1593 cb->cb_color_info | tex->cb_color_info);
1594 i++;
1595 }
1596 for (; i < 8 ; i++)
1597 radeon_set_context_reg(cs, R_028C70_CB_COLOR0_INFO + i * 0x3C, 0);
1598 for (; i < 12; i++)
1599 radeon_set_context_reg(cs, R_028E50_CB_COLOR8_INFO + (i - 8) * 0x1C, 0);
1600
1601 /* ZS buffer. */
1602 if (state->zsbuf) {
1603 struct r600_surface *zb = (struct r600_surface*)state->zsbuf;
1604 unsigned reloc = radeon_add_to_buffer_list(&rctx->b,
1605 &rctx->b.gfx,
1606 (struct r600_resource*)state->zsbuf->texture,
1607 RADEON_USAGE_READWRITE,
1608 zb->base.texture->nr_samples > 1 ?
1609 RADEON_PRIO_DEPTH_BUFFER_MSAA :
1610 RADEON_PRIO_DEPTH_BUFFER);
1611
1612 radeon_set_context_reg(cs, R_028008_DB_DEPTH_VIEW, zb->db_depth_view);
1613
1614 radeon_set_context_reg_seq(cs, R_028040_DB_Z_INFO, 8);
1615 radeon_emit(cs, zb->db_z_info); /* R_028040_DB_Z_INFO */
1616 radeon_emit(cs, zb->db_stencil_info); /* R_028044_DB_STENCIL_INFO */
1617 radeon_emit(cs, zb->db_depth_base); /* R_028048_DB_Z_READ_BASE */
1618 radeon_emit(cs, zb->db_stencil_base); /* R_02804C_DB_STENCIL_READ_BASE */
1619 radeon_emit(cs, zb->db_depth_base); /* R_028050_DB_Z_WRITE_BASE */
1620 radeon_emit(cs, zb->db_stencil_base); /* R_028054_DB_STENCIL_WRITE_BASE */
1621 radeon_emit(cs, zb->db_depth_size); /* R_028058_DB_DEPTH_SIZE */
1622 radeon_emit(cs, zb->db_depth_slice); /* R_02805C_DB_DEPTH_SLICE */
1623
1624 radeon_emit(cs, PKT3(PKT3_NOP, 0, 0)); /* R_028048_DB_Z_READ_BASE */
1625 radeon_emit(cs, reloc);
1626
1627 radeon_emit(cs, PKT3(PKT3_NOP, 0, 0)); /* R_02804C_DB_STENCIL_READ_BASE */
1628 radeon_emit(cs, reloc);
1629
1630 radeon_emit(cs, PKT3(PKT3_NOP, 0, 0)); /* R_028050_DB_Z_WRITE_BASE */
1631 radeon_emit(cs, reloc);
1632
1633 radeon_emit(cs, PKT3(PKT3_NOP, 0, 0)); /* R_028054_DB_STENCIL_WRITE_BASE */
1634 radeon_emit(cs, reloc);
1635 } else if (rctx->screen->b.info.drm_minor >= 18) {
1636 /* DRM 2.6.18 allows the INVALID format to disable depth/stencil.
1637 * Older kernels are out of luck. */
1638 radeon_set_context_reg_seq(cs, R_028040_DB_Z_INFO, 2);
1639 radeon_emit(cs, S_028040_FORMAT(V_028040_Z_INVALID)); /* R_028040_DB_Z_INFO */
1640 radeon_emit(cs, S_028044_FORMAT(V_028044_STENCIL_INVALID)); /* R_028044_DB_STENCIL_INFO */
1641 }
1642
1643 /* Framebuffer dimensions. */
1644 evergreen_get_scissor_rect(rctx, 0, 0, state->width, state->height, &tl, &br);
1645
1646 radeon_set_context_reg_seq(cs, R_028204_PA_SC_WINDOW_SCISSOR_TL, 2);
1647 radeon_emit(cs, tl); /* R_028204_PA_SC_WINDOW_SCISSOR_TL */
1648 radeon_emit(cs, br); /* R_028208_PA_SC_WINDOW_SCISSOR_BR */
1649
1650 if (rctx->b.chip_class == EVERGREEN) {
1651 evergreen_emit_msaa_state(rctx, rctx->framebuffer.nr_samples, rctx->ps_iter_samples);
1652 } else {
1653 unsigned sc_mode_cntl_1 =
1654 EG_S_028A4C_FORCE_EOV_CNTDWN_ENABLE(1) |
1655 EG_S_028A4C_FORCE_EOV_REZ_ENABLE(1);
1656
1657 if (rctx->framebuffer.nr_samples > 1)
1658 cayman_emit_msaa_sample_locs(cs, rctx->framebuffer.nr_samples);
1659 cayman_emit_msaa_config(cs, rctx->framebuffer.nr_samples,
1660 rctx->ps_iter_samples, 0, sc_mode_cntl_1);
1661 }
1662 }
1663
1664 static void evergreen_emit_polygon_offset(struct r600_context *rctx, struct r600_atom *a)
1665 {
1666 struct radeon_winsys_cs *cs = rctx->b.gfx.cs;
1667 struct r600_poly_offset_state *state = (struct r600_poly_offset_state*)a;
1668 float offset_units = state->offset_units;
1669 float offset_scale = state->offset_scale;
1670 uint32_t pa_su_poly_offset_db_fmt_cntl = 0;
1671
1672 if (!state->offset_units_unscaled) {
1673 switch (state->zs_format) {
1674 case PIPE_FORMAT_Z24X8_UNORM:
1675 case PIPE_FORMAT_Z24_UNORM_S8_UINT:
1676 case PIPE_FORMAT_X8Z24_UNORM:
1677 case PIPE_FORMAT_S8_UINT_Z24_UNORM:
1678 offset_units *= 2.0f;
1679 pa_su_poly_offset_db_fmt_cntl =
1680 S_028B78_POLY_OFFSET_NEG_NUM_DB_BITS((char)-24);
1681 break;
1682 case PIPE_FORMAT_Z16_UNORM:
1683 offset_units *= 4.0f;
1684 pa_su_poly_offset_db_fmt_cntl =
1685 S_028B78_POLY_OFFSET_NEG_NUM_DB_BITS((char)-16);
1686 break;
1687 default:
1688 pa_su_poly_offset_db_fmt_cntl =
1689 S_028B78_POLY_OFFSET_NEG_NUM_DB_BITS((char)-23) |
1690 S_028B78_POLY_OFFSET_DB_IS_FLOAT_FMT(1);
1691 }
1692 }
1693
1694 radeon_set_context_reg_seq(cs, R_028B80_PA_SU_POLY_OFFSET_FRONT_SCALE, 4);
1695 radeon_emit(cs, fui(offset_scale));
1696 radeon_emit(cs, fui(offset_units));
1697 radeon_emit(cs, fui(offset_scale));
1698 radeon_emit(cs, fui(offset_units));
1699
1700 radeon_set_context_reg(cs, R_028B78_PA_SU_POLY_OFFSET_DB_FMT_CNTL,
1701 pa_su_poly_offset_db_fmt_cntl);
1702 }
1703
1704 static void evergreen_emit_cb_misc_state(struct r600_context *rctx, struct r600_atom *atom)
1705 {
1706 struct radeon_winsys_cs *cs = rctx->b.gfx.cs;
1707 struct r600_cb_misc_state *a = (struct r600_cb_misc_state*)atom;
1708 unsigned fb_colormask = (1ULL << ((unsigned)a->nr_cbufs * 4)) - 1;
1709 unsigned ps_colormask = (1ULL << ((unsigned)a->nr_ps_color_outputs * 4)) - 1;
1710
1711 radeon_set_context_reg_seq(cs, R_028238_CB_TARGET_MASK, 2);
1712 radeon_emit(cs, a->blend_colormask & fb_colormask); /* R_028238_CB_TARGET_MASK */
1713 /* This must match the used export instructions exactly.
1714 * Other values may lead to undefined behavior and hangs.
1715 */
1716 radeon_emit(cs, ps_colormask); /* R_02823C_CB_SHADER_MASK */
1717 }
1718
1719 static void evergreen_emit_db_state(struct r600_context *rctx, struct r600_atom *atom)
1720 {
1721 struct radeon_winsys_cs *cs = rctx->b.gfx.cs;
1722 struct r600_db_state *a = (struct r600_db_state*)atom;
1723
1724 if (a->rsurf && a->rsurf->db_htile_surface) {
1725 struct r600_texture *rtex = (struct r600_texture *)a->rsurf->base.texture;
1726 unsigned reloc_idx;
1727
1728 radeon_set_context_reg(cs, R_02802C_DB_DEPTH_CLEAR, fui(rtex->depth_clear_value));
1729 radeon_set_context_reg(cs, R_028ABC_DB_HTILE_SURFACE, a->rsurf->db_htile_surface);
1730 radeon_set_context_reg(cs, R_028AC8_DB_PRELOAD_CONTROL, a->rsurf->db_preload_control);
1731 radeon_set_context_reg(cs, R_028014_DB_HTILE_DATA_BASE, a->rsurf->db_htile_data_base);
1732 reloc_idx = radeon_add_to_buffer_list(&rctx->b, &rctx->b.gfx, rtex->htile_buffer,
1733 RADEON_USAGE_READWRITE, RADEON_PRIO_HTILE);
1734 radeon_emit(cs, PKT3(PKT3_NOP, 0, 0));
1735 radeon_emit(cs, reloc_idx);
1736 } else {
1737 radeon_set_context_reg(cs, R_028ABC_DB_HTILE_SURFACE, 0);
1738 radeon_set_context_reg(cs, R_028AC8_DB_PRELOAD_CONTROL, 0);
1739 }
1740 }
1741
1742 static void evergreen_emit_db_misc_state(struct r600_context *rctx, struct r600_atom *atom)
1743 {
1744 struct radeon_winsys_cs *cs = rctx->b.gfx.cs;
1745 struct r600_db_misc_state *a = (struct r600_db_misc_state*)atom;
1746 unsigned db_render_control = 0;
1747 unsigned db_count_control = 0;
1748 unsigned db_render_override =
1749 S_02800C_FORCE_HIS_ENABLE0(V_02800C_FORCE_DISABLE) |
1750 S_02800C_FORCE_HIS_ENABLE1(V_02800C_FORCE_DISABLE);
1751
1752 if (rctx->b.num_occlusion_queries > 0 &&
1753 !a->occlusion_queries_disabled) {
1754 db_count_control |= S_028004_PERFECT_ZPASS_COUNTS(1);
1755 if (rctx->b.chip_class == CAYMAN) {
1756 db_count_control |= S_028004_SAMPLE_RATE(a->log_samples);
1757 }
1758 db_render_override |= S_02800C_NOOP_CULL_DISABLE(1);
1759 } else {
1760 db_count_control |= S_028004_ZPASS_INCREMENT_DISABLE(1);
1761 }
1762
1763 /* This is to fix a lockup when hyperz and alpha test are enabled at
1764 * the same time somehow GPU get confuse on which order to pick for
1765 * z test
1766 */
1767 if (rctx->alphatest_state.sx_alpha_test_control)
1768 db_render_override |= S_02800C_FORCE_SHADER_Z_ORDER(1);
1769
1770 if (a->flush_depthstencil_through_cb) {
1771 assert(a->copy_depth || a->copy_stencil);
1772
1773 db_render_control |= S_028000_DEPTH_COPY_ENABLE(a->copy_depth) |
1774 S_028000_STENCIL_COPY_ENABLE(a->copy_stencil) |
1775 S_028000_COPY_CENTROID(1) |
1776 S_028000_COPY_SAMPLE(a->copy_sample);
1777 } else if (a->flush_depth_inplace || a->flush_stencil_inplace) {
1778 db_render_control |= S_028000_DEPTH_COMPRESS_DISABLE(a->flush_depth_inplace) |
1779 S_028000_STENCIL_COMPRESS_DISABLE(a->flush_stencil_inplace);
1780 db_render_override |= S_02800C_DISABLE_PIXEL_RATE_TILES(1);
1781 }
1782 if (a->htile_clear) {
1783 /* FIXME we might want to disable cliprect here */
1784 db_render_control |= S_028000_DEPTH_CLEAR_ENABLE(1);
1785 }
1786
1787 radeon_set_context_reg_seq(cs, R_028000_DB_RENDER_CONTROL, 2);
1788 radeon_emit(cs, db_render_control); /* R_028000_DB_RENDER_CONTROL */
1789 radeon_emit(cs, db_count_control); /* R_028004_DB_COUNT_CONTROL */
1790 radeon_set_context_reg(cs, R_02800C_DB_RENDER_OVERRIDE, db_render_override);
1791 radeon_set_context_reg(cs, R_02880C_DB_SHADER_CONTROL, a->db_shader_control);
1792 }
1793
1794 static void evergreen_emit_vertex_buffers(struct r600_context *rctx,
1795 struct r600_vertexbuf_state *state,
1796 unsigned resource_offset,
1797 unsigned pkt_flags)
1798 {
1799 struct radeon_winsys_cs *cs = rctx->b.gfx.cs;
1800 uint32_t dirty_mask = state->dirty_mask;
1801
1802 while (dirty_mask) {
1803 struct pipe_vertex_buffer *vb;
1804 struct r600_resource *rbuffer;
1805 uint64_t va;
1806 unsigned buffer_index = u_bit_scan(&dirty_mask);
1807
1808 vb = &state->vb[buffer_index];
1809 rbuffer = (struct r600_resource*)vb->buffer;
1810 assert(rbuffer);
1811
1812 va = rbuffer->gpu_address + vb->buffer_offset;
1813
1814 /* fetch resources start at index 992 */
1815 radeon_emit(cs, PKT3(PKT3_SET_RESOURCE, 8, 0) | pkt_flags);
1816 radeon_emit(cs, (resource_offset + buffer_index) * 8);
1817 radeon_emit(cs, va); /* RESOURCEi_WORD0 */
1818 radeon_emit(cs, rbuffer->b.b.width0 - vb->buffer_offset - 1); /* RESOURCEi_WORD1 */
1819 radeon_emit(cs, /* RESOURCEi_WORD2 */
1820 S_030008_ENDIAN_SWAP(r600_endian_swap(32)) |
1821 S_030008_STRIDE(vb->stride) |
1822 S_030008_BASE_ADDRESS_HI(va >> 32UL));
1823 radeon_emit(cs, /* RESOURCEi_WORD3 */
1824 S_03000C_DST_SEL_X(V_03000C_SQ_SEL_X) |
1825 S_03000C_DST_SEL_Y(V_03000C_SQ_SEL_Y) |
1826 S_03000C_DST_SEL_Z(V_03000C_SQ_SEL_Z) |
1827 S_03000C_DST_SEL_W(V_03000C_SQ_SEL_W));
1828 radeon_emit(cs, 0); /* RESOURCEi_WORD4 */
1829 radeon_emit(cs, 0); /* RESOURCEi_WORD5 */
1830 radeon_emit(cs, 0); /* RESOURCEi_WORD6 */
1831 radeon_emit(cs, 0xc0000000); /* RESOURCEi_WORD7 */
1832
1833 radeon_emit(cs, PKT3(PKT3_NOP, 0, 0) | pkt_flags);
1834 radeon_emit(cs, radeon_add_to_buffer_list(&rctx->b, &rctx->b.gfx, rbuffer,
1835 RADEON_USAGE_READ, RADEON_PRIO_VERTEX_BUFFER));
1836 }
1837 state->dirty_mask = 0;
1838 }
1839
1840 static void evergreen_fs_emit_vertex_buffers(struct r600_context *rctx, struct r600_atom * atom)
1841 {
1842 evergreen_emit_vertex_buffers(rctx, &rctx->vertex_buffer_state, EG_FETCH_CONSTANTS_OFFSET_FS, 0);
1843 }
1844
1845 static void evergreen_cs_emit_vertex_buffers(struct r600_context *rctx, struct r600_atom * atom)
1846 {
1847 evergreen_emit_vertex_buffers(rctx, &rctx->cs_vertex_buffer_state, EG_FETCH_CONSTANTS_OFFSET_CS,
1848 RADEON_CP_PACKET3_COMPUTE_MODE);
1849 }
1850
1851 static void evergreen_emit_constant_buffers(struct r600_context *rctx,
1852 struct r600_constbuf_state *state,
1853 unsigned buffer_id_base,
1854 unsigned reg_alu_constbuf_size,
1855 unsigned reg_alu_const_cache,
1856 unsigned pkt_flags)
1857 {
1858 struct radeon_winsys_cs *cs = rctx->b.gfx.cs;
1859 uint32_t dirty_mask = state->dirty_mask;
1860
1861 while (dirty_mask) {
1862 struct pipe_constant_buffer *cb;
1863 struct r600_resource *rbuffer;
1864 uint64_t va;
1865 unsigned buffer_index = ffs(dirty_mask) - 1;
1866 unsigned gs_ring_buffer = (buffer_index == R600_GS_RING_CONST_BUFFER);
1867
1868 cb = &state->cb[buffer_index];
1869 rbuffer = (struct r600_resource*)cb->buffer;
1870 assert(rbuffer);
1871
1872 va = rbuffer->gpu_address + cb->buffer_offset;
1873
1874 if (!gs_ring_buffer) {
1875 radeon_set_context_reg_flag(cs, reg_alu_constbuf_size + buffer_index * 4,
1876 DIV_ROUND_UP(cb->buffer_size, 256), pkt_flags);
1877 radeon_set_context_reg_flag(cs, reg_alu_const_cache + buffer_index * 4, va >> 8,
1878 pkt_flags);
1879 }
1880
1881 radeon_emit(cs, PKT3(PKT3_NOP, 0, 0) | pkt_flags);
1882 radeon_emit(cs, radeon_add_to_buffer_list(&rctx->b, &rctx->b.gfx, rbuffer,
1883 RADEON_USAGE_READ, RADEON_PRIO_CONST_BUFFER));
1884
1885 radeon_emit(cs, PKT3(PKT3_SET_RESOURCE, 8, 0) | pkt_flags);
1886 radeon_emit(cs, (buffer_id_base + buffer_index) * 8);
1887 radeon_emit(cs, va); /* RESOURCEi_WORD0 */
1888 radeon_emit(cs, rbuffer->b.b.width0 - cb->buffer_offset - 1); /* RESOURCEi_WORD1 */
1889 radeon_emit(cs, /* RESOURCEi_WORD2 */
1890 S_030008_ENDIAN_SWAP(gs_ring_buffer ? ENDIAN_NONE : r600_endian_swap(32)) |
1891 S_030008_STRIDE(gs_ring_buffer ? 4 : 16) |
1892 S_030008_BASE_ADDRESS_HI(va >> 32UL) |
1893 S_030008_DATA_FORMAT(FMT_32_32_32_32_FLOAT));
1894 radeon_emit(cs, /* RESOURCEi_WORD3 */
1895 S_03000C_UNCACHED(gs_ring_buffer ? 1 : 0) |
1896 S_03000C_DST_SEL_X(V_03000C_SQ_SEL_X) |
1897 S_03000C_DST_SEL_Y(V_03000C_SQ_SEL_Y) |
1898 S_03000C_DST_SEL_Z(V_03000C_SQ_SEL_Z) |
1899 S_03000C_DST_SEL_W(V_03000C_SQ_SEL_W));
1900 radeon_emit(cs, 0); /* RESOURCEi_WORD4 */
1901 radeon_emit(cs, 0); /* RESOURCEi_WORD5 */
1902 radeon_emit(cs, 0); /* RESOURCEi_WORD6 */
1903 radeon_emit(cs, /* RESOURCEi_WORD7 */
1904 S_03001C_TYPE(V_03001C_SQ_TEX_VTX_VALID_BUFFER));
1905
1906 radeon_emit(cs, PKT3(PKT3_NOP, 0, 0) | pkt_flags);
1907 radeon_emit(cs, radeon_add_to_buffer_list(&rctx->b, &rctx->b.gfx, rbuffer,
1908 RADEON_USAGE_READ, RADEON_PRIO_CONST_BUFFER));
1909
1910 dirty_mask &= ~(1 << buffer_index);
1911 }
1912 state->dirty_mask = 0;
1913 }
1914
1915 /* VS constants can be in VS/ES (same space) or LS if tess is enabled */
1916 static void evergreen_emit_vs_constant_buffers(struct r600_context *rctx, struct r600_atom *atom)
1917 {
1918 if (rctx->vs_shader->current->shader.vs_as_ls) {
1919 evergreen_emit_constant_buffers(rctx, &rctx->constbuf_state[PIPE_SHADER_VERTEX],
1920 EG_FETCH_CONSTANTS_OFFSET_LS,
1921 R_028FC0_ALU_CONST_BUFFER_SIZE_LS_0,
1922 R_028F40_ALU_CONST_CACHE_LS_0,
1923 0 /* PKT3 flags */);
1924 } else {
1925 evergreen_emit_constant_buffers(rctx, &rctx->constbuf_state[PIPE_SHADER_VERTEX],
1926 EG_FETCH_CONSTANTS_OFFSET_VS,
1927 R_028180_ALU_CONST_BUFFER_SIZE_VS_0,
1928 R_028980_ALU_CONST_CACHE_VS_0,
1929 0 /* PKT3 flags */);
1930 }
1931 }
1932
1933 static void evergreen_emit_gs_constant_buffers(struct r600_context *rctx, struct r600_atom *atom)
1934 {
1935 evergreen_emit_constant_buffers(rctx, &rctx->constbuf_state[PIPE_SHADER_GEOMETRY],
1936 EG_FETCH_CONSTANTS_OFFSET_GS,
1937 R_0281C0_ALU_CONST_BUFFER_SIZE_GS_0,
1938 R_0289C0_ALU_CONST_CACHE_GS_0,
1939 0 /* PKT3 flags */);
1940 }
1941
1942 static void evergreen_emit_ps_constant_buffers(struct r600_context *rctx, struct r600_atom *atom)
1943 {
1944 evergreen_emit_constant_buffers(rctx, &rctx->constbuf_state[PIPE_SHADER_FRAGMENT],
1945 EG_FETCH_CONSTANTS_OFFSET_PS,
1946 R_028140_ALU_CONST_BUFFER_SIZE_PS_0,
1947 R_028940_ALU_CONST_CACHE_PS_0,
1948 0 /* PKT3 flags */);
1949 }
1950
1951 static void evergreen_emit_cs_constant_buffers(struct r600_context *rctx, struct r600_atom *atom)
1952 {
1953 evergreen_emit_constant_buffers(rctx, &rctx->constbuf_state[PIPE_SHADER_COMPUTE],
1954 EG_FETCH_CONSTANTS_OFFSET_CS,
1955 R_028FC0_ALU_CONST_BUFFER_SIZE_LS_0,
1956 R_028F40_ALU_CONST_CACHE_LS_0,
1957 RADEON_CP_PACKET3_COMPUTE_MODE);
1958 }
1959
1960 /* tes constants can be emitted to VS or ES - which are common */
1961 static void evergreen_emit_tes_constant_buffers(struct r600_context *rctx, struct r600_atom *atom)
1962 {
1963 if (!rctx->tes_shader)
1964 return;
1965 evergreen_emit_constant_buffers(rctx, &rctx->constbuf_state[PIPE_SHADER_TESS_EVAL],
1966 EG_FETCH_CONSTANTS_OFFSET_VS,
1967 R_028180_ALU_CONST_BUFFER_SIZE_VS_0,
1968 R_028980_ALU_CONST_CACHE_VS_0,
1969 0);
1970 }
1971
1972 static void evergreen_emit_tcs_constant_buffers(struct r600_context *rctx, struct r600_atom *atom)
1973 {
1974 if (!rctx->tes_shader)
1975 return;
1976 evergreen_emit_constant_buffers(rctx, &rctx->constbuf_state[PIPE_SHADER_TESS_CTRL],
1977 EG_FETCH_CONSTANTS_OFFSET_HS,
1978 R_028F80_ALU_CONST_BUFFER_SIZE_HS_0,
1979 R_028F00_ALU_CONST_CACHE_HS_0,
1980 0);
1981 }
1982
1983 static void evergreen_emit_sampler_views(struct r600_context *rctx,
1984 struct r600_samplerview_state *state,
1985 unsigned resource_id_base, unsigned pkt_flags)
1986 {
1987 struct radeon_winsys_cs *cs = rctx->b.gfx.cs;
1988 uint32_t dirty_mask = state->dirty_mask;
1989
1990 while (dirty_mask) {
1991 struct r600_pipe_sampler_view *rview;
1992 unsigned resource_index = u_bit_scan(&dirty_mask);
1993 unsigned reloc;
1994
1995 rview = state->views[resource_index];
1996 assert(rview);
1997
1998 radeon_emit(cs, PKT3(PKT3_SET_RESOURCE, 8, 0) | pkt_flags);
1999 radeon_emit(cs, (resource_id_base + resource_index) * 8);
2000 radeon_emit_array(cs, rview->tex_resource_words, 8);
2001
2002 reloc = radeon_add_to_buffer_list(&rctx->b, &rctx->b.gfx, rview->tex_resource,
2003 RADEON_USAGE_READ,
2004 r600_get_sampler_view_priority(rview->tex_resource));
2005 radeon_emit(cs, PKT3(PKT3_NOP, 0, 0) | pkt_flags);
2006 radeon_emit(cs, reloc);
2007
2008 if (!rview->skip_mip_address_reloc) {
2009 radeon_emit(cs, PKT3(PKT3_NOP, 0, 0) | pkt_flags);
2010 radeon_emit(cs, reloc);
2011 }
2012 }
2013 state->dirty_mask = 0;
2014 }
2015
2016 static void evergreen_emit_vs_sampler_views(struct r600_context *rctx, struct r600_atom *atom)
2017 {
2018 if (rctx->vs_shader->current->shader.vs_as_ls) {
2019 evergreen_emit_sampler_views(rctx, &rctx->samplers[PIPE_SHADER_VERTEX].views,
2020 EG_FETCH_CONSTANTS_OFFSET_LS + R600_MAX_CONST_BUFFERS, 0);
2021 } else {
2022 evergreen_emit_sampler_views(rctx, &rctx->samplers[PIPE_SHADER_VERTEX].views,
2023 EG_FETCH_CONSTANTS_OFFSET_VS + R600_MAX_CONST_BUFFERS, 0);
2024 }
2025 }
2026
2027 static void evergreen_emit_gs_sampler_views(struct r600_context *rctx, struct r600_atom *atom)
2028 {
2029 evergreen_emit_sampler_views(rctx, &rctx->samplers[PIPE_SHADER_GEOMETRY].views,
2030 EG_FETCH_CONSTANTS_OFFSET_GS + R600_MAX_CONST_BUFFERS, 0);
2031 }
2032
2033 static void evergreen_emit_tcs_sampler_views(struct r600_context *rctx, struct r600_atom *atom)
2034 {
2035 evergreen_emit_sampler_views(rctx, &rctx->samplers[PIPE_SHADER_TESS_CTRL].views,
2036 EG_FETCH_CONSTANTS_OFFSET_HS + R600_MAX_CONST_BUFFERS, 0);
2037 }
2038
2039 static void evergreen_emit_tes_sampler_views(struct r600_context *rctx, struct r600_atom *atom)
2040 {
2041 evergreen_emit_sampler_views(rctx, &rctx->samplers[PIPE_SHADER_TESS_EVAL].views,
2042 EG_FETCH_CONSTANTS_OFFSET_VS + R600_MAX_CONST_BUFFERS, 0);
2043 }
2044
2045 static void evergreen_emit_ps_sampler_views(struct r600_context *rctx, struct r600_atom *atom)
2046 {
2047 evergreen_emit_sampler_views(rctx, &rctx->samplers[PIPE_SHADER_FRAGMENT].views,
2048 EG_FETCH_CONSTANTS_OFFSET_PS + R600_MAX_CONST_BUFFERS, 0);
2049 }
2050
2051 static void evergreen_emit_cs_sampler_views(struct r600_context *rctx, struct r600_atom *atom)
2052 {
2053 evergreen_emit_sampler_views(rctx, &rctx->samplers[PIPE_SHADER_COMPUTE].views,
2054 EG_FETCH_CONSTANTS_OFFSET_CS + 2, RADEON_CP_PACKET3_COMPUTE_MODE);
2055 }
2056
2057 static void evergreen_emit_sampler_states(struct r600_context *rctx,
2058 struct r600_textures_info *texinfo,
2059 unsigned resource_id_base,
2060 unsigned border_index_reg,
2061 unsigned pkt_flags)
2062 {
2063 struct radeon_winsys_cs *cs = rctx->b.gfx.cs;
2064 uint32_t dirty_mask = texinfo->states.dirty_mask;
2065
2066 while (dirty_mask) {
2067 struct r600_pipe_sampler_state *rstate;
2068 unsigned i = u_bit_scan(&dirty_mask);
2069
2070 rstate = texinfo->states.states[i];
2071 assert(rstate);
2072
2073 radeon_emit(cs, PKT3(PKT3_SET_SAMPLER, 3, 0) | pkt_flags);
2074 radeon_emit(cs, (resource_id_base + i) * 3);
2075 radeon_emit_array(cs, rstate->tex_sampler_words, 3);
2076
2077 if (rstate->border_color_use) {
2078 radeon_set_config_reg_seq(cs, border_index_reg, 5);
2079 radeon_emit(cs, i);
2080 radeon_emit_array(cs, rstate->border_color.ui, 4);
2081 }
2082 }
2083 texinfo->states.dirty_mask = 0;
2084 }
2085
2086 static void evergreen_emit_vs_sampler_states(struct r600_context *rctx, struct r600_atom *atom)
2087 {
2088 if (rctx->vs_shader->current->shader.vs_as_ls) {
2089 evergreen_emit_sampler_states(rctx, &rctx->samplers[PIPE_SHADER_VERTEX], 72,
2090 R_00A450_TD_LS_SAMPLER0_BORDER_COLOR_INDEX, 0);
2091 } else {
2092 evergreen_emit_sampler_states(rctx, &rctx->samplers[PIPE_SHADER_VERTEX], 18,
2093 R_00A414_TD_VS_SAMPLER0_BORDER_INDEX, 0);
2094 }
2095 }
2096
2097 static void evergreen_emit_gs_sampler_states(struct r600_context *rctx, struct r600_atom *atom)
2098 {
2099 evergreen_emit_sampler_states(rctx, &rctx->samplers[PIPE_SHADER_GEOMETRY], 36,
2100 R_00A428_TD_GS_SAMPLER0_BORDER_INDEX, 0);
2101 }
2102
2103 static void evergreen_emit_tcs_sampler_states(struct r600_context *rctx, struct r600_atom *atom)
2104 {
2105 evergreen_emit_sampler_states(rctx, &rctx->samplers[PIPE_SHADER_TESS_CTRL], 54,
2106 R_00A43C_TD_HS_SAMPLER0_BORDER_COLOR_INDEX, 0);
2107 }
2108
2109 static void evergreen_emit_tes_sampler_states(struct r600_context *rctx, struct r600_atom *atom)
2110 {
2111 evergreen_emit_sampler_states(rctx, &rctx->samplers[PIPE_SHADER_TESS_EVAL], 18,
2112 R_00A414_TD_VS_SAMPLER0_BORDER_INDEX, 0);
2113 }
2114
2115 static void evergreen_emit_ps_sampler_states(struct r600_context *rctx, struct r600_atom *atom)
2116 {
2117 evergreen_emit_sampler_states(rctx, &rctx->samplers[PIPE_SHADER_FRAGMENT], 0,
2118 R_00A400_TD_PS_SAMPLER0_BORDER_INDEX, 0);
2119 }
2120
2121 static void evergreen_emit_cs_sampler_states(struct r600_context *rctx, struct r600_atom *atom)
2122 {
2123 evergreen_emit_sampler_states(rctx, &rctx->samplers[PIPE_SHADER_COMPUTE], 90,
2124 R_00A464_TD_CS_SAMPLER0_BORDER_INDEX,
2125 RADEON_CP_PACKET3_COMPUTE_MODE);
2126 }
2127
2128 static void evergreen_emit_sample_mask(struct r600_context *rctx, struct r600_atom *a)
2129 {
2130 struct r600_sample_mask *s = (struct r600_sample_mask*)a;
2131 uint8_t mask = s->sample_mask;
2132
2133 radeon_set_context_reg(rctx->b.gfx.cs, R_028C3C_PA_SC_AA_MASK,
2134 mask | (mask << 8) | (mask << 16) | (mask << 24));
2135 }
2136
2137 static void cayman_emit_sample_mask(struct r600_context *rctx, struct r600_atom *a)
2138 {
2139 struct r600_sample_mask *s = (struct r600_sample_mask*)a;
2140 struct radeon_winsys_cs *cs = rctx->b.gfx.cs;
2141 uint16_t mask = s->sample_mask;
2142
2143 radeon_set_context_reg_seq(cs, CM_R_028C38_PA_SC_AA_MASK_X0Y0_X1Y0, 2);
2144 radeon_emit(cs, mask | (mask << 16)); /* X0Y0_X1Y0 */
2145 radeon_emit(cs, mask | (mask << 16)); /* X0Y1_X1Y1 */
2146 }
2147
2148 static void evergreen_emit_vertex_fetch_shader(struct r600_context *rctx, struct r600_atom *a)
2149 {
2150 struct radeon_winsys_cs *cs = rctx->b.gfx.cs;
2151 struct r600_cso_state *state = (struct r600_cso_state*)a;
2152 struct r600_fetch_shader *shader = (struct r600_fetch_shader*)state->cso;
2153
2154 radeon_set_context_reg(cs, R_0288A4_SQ_PGM_START_FS,
2155 (shader->buffer->gpu_address + shader->offset) >> 8);
2156 radeon_emit(cs, PKT3(PKT3_NOP, 0, 0));
2157 radeon_emit(cs, radeon_add_to_buffer_list(&rctx->b, &rctx->b.gfx, shader->buffer,
2158 RADEON_USAGE_READ,
2159 RADEON_PRIO_INTERNAL_SHADER));
2160 }
2161
2162 static void evergreen_emit_shader_stages(struct r600_context *rctx, struct r600_atom *a)
2163 {
2164 struct radeon_winsys_cs *cs = rctx->b.gfx.cs;
2165 struct r600_shader_stages_state *state = (struct r600_shader_stages_state*)a;
2166
2167 uint32_t v = 0, v2 = 0, primid = 0, tf_param = 0;
2168
2169 if (rctx->vs_shader->current->shader.vs_as_gs_a) {
2170 v2 = S_028A40_MODE(V_028A40_GS_SCENARIO_A);
2171 primid = 1;
2172 }
2173
2174 if (state->geom_enable) {
2175 uint32_t cut_val;
2176
2177 if (rctx->gs_shader->gs_max_out_vertices <= 128)
2178 cut_val = V_028A40_GS_CUT_128;
2179 else if (rctx->gs_shader->gs_max_out_vertices <= 256)
2180 cut_val = V_028A40_GS_CUT_256;
2181 else if (rctx->gs_shader->gs_max_out_vertices <= 512)
2182 cut_val = V_028A40_GS_CUT_512;
2183 else
2184 cut_val = V_028A40_GS_CUT_1024;
2185
2186 v = S_028B54_GS_EN(1) |
2187 S_028B54_VS_EN(V_028B54_VS_STAGE_COPY_SHADER);
2188 if (!rctx->tes_shader)
2189 v |= S_028B54_ES_EN(V_028B54_ES_STAGE_REAL);
2190
2191 v2 = S_028A40_MODE(V_028A40_GS_SCENARIO_G) |
2192 S_028A40_CUT_MODE(cut_val);
2193
2194 if (rctx->gs_shader->current->shader.gs_prim_id_input)
2195 primid = 1;
2196 }
2197
2198 if (rctx->tes_shader) {
2199 uint32_t type, partitioning, topology;
2200 struct tgsi_shader_info *info = &rctx->tes_shader->current->selector->info;
2201 unsigned tes_prim_mode = info->properties[TGSI_PROPERTY_TES_PRIM_MODE];
2202 unsigned tes_spacing = info->properties[TGSI_PROPERTY_TES_SPACING];
2203 bool tes_vertex_order_cw = info->properties[TGSI_PROPERTY_TES_VERTEX_ORDER_CW];
2204 bool tes_point_mode = info->properties[TGSI_PROPERTY_TES_POINT_MODE];
2205 switch (tes_prim_mode) {
2206 case PIPE_PRIM_LINES:
2207 type = V_028B6C_TESS_ISOLINE;
2208 break;
2209 case PIPE_PRIM_TRIANGLES:
2210 type = V_028B6C_TESS_TRIANGLE;
2211 break;
2212 case PIPE_PRIM_QUADS:
2213 type = V_028B6C_TESS_QUAD;
2214 break;
2215 default:
2216 assert(0);
2217 return;
2218 }
2219
2220 switch (tes_spacing) {
2221 case PIPE_TESS_SPACING_FRACTIONAL_ODD:
2222 partitioning = V_028B6C_PART_FRAC_ODD;
2223 break;
2224 case PIPE_TESS_SPACING_FRACTIONAL_EVEN:
2225 partitioning = V_028B6C_PART_FRAC_EVEN;
2226 break;
2227 case PIPE_TESS_SPACING_EQUAL:
2228 partitioning = V_028B6C_PART_INTEGER;
2229 break;
2230 default:
2231 assert(0);
2232 return;
2233 }
2234
2235 if (tes_point_mode)
2236 topology = V_028B6C_OUTPUT_POINT;
2237 else if (tes_prim_mode == PIPE_PRIM_LINES)
2238 topology = V_028B6C_OUTPUT_LINE;
2239 else if (tes_vertex_order_cw)
2240 /* XXX follow radeonsi and invert */
2241 topology = V_028B6C_OUTPUT_TRIANGLE_CCW;
2242 else
2243 topology = V_028B6C_OUTPUT_TRIANGLE_CW;
2244
2245 tf_param = S_028B6C_TYPE(type) |
2246 S_028B6C_PARTITIONING(partitioning) |
2247 S_028B6C_TOPOLOGY(topology);
2248 }
2249
2250 if (rctx->tes_shader) {
2251 v |= S_028B54_LS_EN(V_028B54_LS_STAGE_ON) |
2252 S_028B54_HS_EN(1);
2253 if (!state->geom_enable)
2254 v |= S_028B54_VS_EN(V_028B54_VS_STAGE_DS);
2255 else
2256 v |= S_028B54_ES_EN(V_028B54_ES_STAGE_DS);
2257 }
2258
2259 radeon_set_context_reg(cs, R_028AB8_VGT_VTX_CNT_EN, v ? 1 : 0 );
2260 radeon_set_context_reg(cs, R_028B54_VGT_SHADER_STAGES_EN, v);
2261 radeon_set_context_reg(cs, R_028A40_VGT_GS_MODE, v2);
2262 radeon_set_context_reg(cs, R_028A84_VGT_PRIMITIVEID_EN, primid);
2263 radeon_set_context_reg(cs, R_028B6C_VGT_TF_PARAM, tf_param);
2264 }
2265
2266 static void evergreen_emit_gs_rings(struct r600_context *rctx, struct r600_atom *a)
2267 {
2268 struct radeon_winsys_cs *cs = rctx->b.gfx.cs;
2269 struct r600_gs_rings_state *state = (struct r600_gs_rings_state*)a;
2270 struct r600_resource *rbuffer;
2271
2272 radeon_set_config_reg(cs, R_008040_WAIT_UNTIL, S_008040_WAIT_3D_IDLE(1));
2273 radeon_emit(cs, PKT3(PKT3_EVENT_WRITE, 0, 0));
2274 radeon_emit(cs, EVENT_TYPE(EVENT_TYPE_VGT_FLUSH));
2275
2276 if (state->enable) {
2277 rbuffer =(struct r600_resource*)state->esgs_ring.buffer;
2278 radeon_set_config_reg(cs, R_008C40_SQ_ESGS_RING_BASE,
2279 rbuffer->gpu_address >> 8);
2280 radeon_emit(cs, PKT3(PKT3_NOP, 0, 0));
2281 radeon_emit(cs, radeon_add_to_buffer_list(&rctx->b, &rctx->b.gfx, rbuffer,
2282 RADEON_USAGE_READWRITE,
2283 RADEON_PRIO_SHADER_RINGS));
2284 radeon_set_config_reg(cs, R_008C44_SQ_ESGS_RING_SIZE,
2285 state->esgs_ring.buffer_size >> 8);
2286
2287 rbuffer =(struct r600_resource*)state->gsvs_ring.buffer;
2288 radeon_set_config_reg(cs, R_008C48_SQ_GSVS_RING_BASE,
2289 rbuffer->gpu_address >> 8);
2290 radeon_emit(cs, PKT3(PKT3_NOP, 0, 0));
2291 radeon_emit(cs, radeon_add_to_buffer_list(&rctx->b, &rctx->b.gfx, rbuffer,
2292 RADEON_USAGE_READWRITE,
2293 RADEON_PRIO_SHADER_RINGS));
2294 radeon_set_config_reg(cs, R_008C4C_SQ_GSVS_RING_SIZE,
2295 state->gsvs_ring.buffer_size >> 8);
2296 } else {
2297 radeon_set_config_reg(cs, R_008C44_SQ_ESGS_RING_SIZE, 0);
2298 radeon_set_config_reg(cs, R_008C4C_SQ_GSVS_RING_SIZE, 0);
2299 }
2300
2301 radeon_set_config_reg(cs, R_008040_WAIT_UNTIL, S_008040_WAIT_3D_IDLE(1));
2302 radeon_emit(cs, PKT3(PKT3_EVENT_WRITE, 0, 0));
2303 radeon_emit(cs, EVENT_TYPE(EVENT_TYPE_VGT_FLUSH));
2304 }
2305
2306 void cayman_init_common_regs(struct r600_command_buffer *cb,
2307 enum chip_class ctx_chip_class,
2308 enum radeon_family ctx_family,
2309 int ctx_drm_minor)
2310 {
2311 r600_store_config_reg_seq(cb, R_008C00_SQ_CONFIG, 2);
2312 r600_store_value(cb, S_008C00_EXPORT_SRC_C(1)); /* R_008C00_SQ_CONFIG */
2313 /* always set the temp clauses */
2314 r600_store_value(cb, S_008C04_NUM_CLAUSE_TEMP_GPRS(4)); /* R_008C04_SQ_GPR_RESOURCE_MGMT_1 */
2315
2316 r600_store_config_reg_seq(cb, R_008C10_SQ_GLOBAL_GPR_RESOURCE_MGMT_1, 2);
2317 r600_store_value(cb, 0); /* R_008C10_SQ_GLOBAL_GPR_RESOURCE_MGMT_1 */
2318 r600_store_value(cb, 0); /* R_008C14_SQ_GLOBAL_GPR_RESOURCE_MGMT_2 */
2319
2320 r600_store_config_reg(cb, R_008D8C_SQ_DYN_GPR_CNTL_PS_FLUSH_REQ, (1 << 8));
2321
2322 r600_store_context_reg_seq(cb, R_028350_SX_MISC, 2);
2323 r600_store_value(cb, 0);
2324 r600_store_value(cb, S_028354_SURFACE_SYNC_MASK(0xf));
2325
2326 r600_store_context_reg(cb, R_028800_DB_DEPTH_CONTROL, 0);
2327 }
2328
2329 static void cayman_init_atom_start_cs(struct r600_context *rctx)
2330 {
2331 struct r600_command_buffer *cb = &rctx->start_cs_cmd;
2332 int tmp, i;
2333
2334 r600_init_command_buffer(cb, 338);
2335
2336 /* This must be first. */
2337 r600_store_value(cb, PKT3(PKT3_CONTEXT_CONTROL, 1, 0));
2338 r600_store_value(cb, 0x80000000);
2339 r600_store_value(cb, 0x80000000);
2340
2341 /* We're setting config registers here. */
2342 r600_store_value(cb, PKT3(PKT3_EVENT_WRITE, 0, 0));
2343 r600_store_value(cb, EVENT_TYPE(EVENT_TYPE_PS_PARTIAL_FLUSH) | EVENT_INDEX(4));
2344
2345 /* This enables pipeline stat & streamout queries.
2346 * They are only disabled by blits.
2347 */
2348 r600_store_value(cb, PKT3(PKT3_EVENT_WRITE, 0, 0));
2349 r600_store_value(cb, EVENT_TYPE(EVENT_TYPE_PIPELINESTAT_START) | EVENT_INDEX(0));
2350
2351 cayman_init_common_regs(cb, rctx->b.chip_class,
2352 rctx->b.family, rctx->screen->b.info.drm_minor);
2353
2354 r600_store_config_reg(cb, R_009100_SPI_CONFIG_CNTL, 0);
2355 r600_store_config_reg(cb, R_00913C_SPI_CONFIG_CNTL_1, S_00913C_VTX_DONE_DELAY(4));
2356
2357 /* remove LS/HS from one SIMD for hw workaround */
2358 r600_store_config_reg_seq(cb, R_008E20_SQ_STATIC_THREAD_MGMT1, 3);
2359 r600_store_value(cb, 0xffffffff);
2360 r600_store_value(cb, 0xffffffff);
2361 r600_store_value(cb, 0xfffffffe);
2362
2363 r600_store_context_reg_seq(cb, R_028900_SQ_ESGS_RING_ITEMSIZE, 6);
2364 r600_store_value(cb, 0); /* R_028900_SQ_ESGS_RING_ITEMSIZE */
2365 r600_store_value(cb, 0); /* R_028904_SQ_GSVS_RING_ITEMSIZE */
2366 r600_store_value(cb, 0); /* R_028908_SQ_ESTMP_RING_ITEMSIZE */
2367 r600_store_value(cb, 0); /* R_02890C_SQ_GSTMP_RING_ITEMSIZE */
2368 r600_store_value(cb, 0); /* R_028910_SQ_VSTMP_RING_ITEMSIZE */
2369 r600_store_value(cb, 0); /* R_028914_SQ_PSTMP_RING_ITEMSIZE */
2370
2371 r600_store_context_reg_seq(cb, R_02891C_SQ_GS_VERT_ITEMSIZE, 4);
2372 r600_store_value(cb, 0); /* R_02891C_SQ_GS_VERT_ITEMSIZE */
2373 r600_store_value(cb, 0); /* R_028920_SQ_GS_VERT_ITEMSIZE_1 */
2374 r600_store_value(cb, 0); /* R_028924_SQ_GS_VERT_ITEMSIZE_2 */
2375 r600_store_value(cb, 0); /* R_028928_SQ_GS_VERT_ITEMSIZE_3 */
2376
2377 r600_store_context_reg_seq(cb, R_028A10_VGT_OUTPUT_PATH_CNTL, 13);
2378 r600_store_value(cb, 0); /* R_028A10_VGT_OUTPUT_PATH_CNTL */
2379 r600_store_value(cb, 0); /* R_028A14_VGT_HOS_CNTL */
2380 r600_store_value(cb, fui(64)); /* R_028A18_VGT_HOS_MAX_TESS_LEVEL */
2381 r600_store_value(cb, fui(0)); /* R_028A1C_VGT_HOS_MIN_TESS_LEVEL */
2382 r600_store_value(cb, 16); /* R_028A20_VGT_HOS_REUSE_DEPTH */
2383 r600_store_value(cb, 0); /* R_028A24_VGT_GROUP_PRIM_TYPE */
2384 r600_store_value(cb, 0); /* R_028A28_VGT_GROUP_FIRST_DECR */
2385 r600_store_value(cb, 0); /* R_028A2C_VGT_GROUP_DECR */
2386 r600_store_value(cb, 0); /* R_028A30_VGT_GROUP_VECT_0_CNTL */
2387 r600_store_value(cb, 0); /* R_028A34_VGT_GROUP_VECT_1_CNTL */
2388 r600_store_value(cb, 0); /* R_028A38_VGT_GROUP_VECT_0_FMT_CNTL */
2389 r600_store_value(cb, 0); /* R_028A3C_VGT_GROUP_VECT_1_FMT_CNTL */
2390 r600_store_value(cb, 0); /* R_028A40_VGT_GS_MODE */
2391
2392 r600_store_context_reg(cb, R_028B98_VGT_STRMOUT_BUFFER_CONFIG, 0);
2393
2394 r600_store_config_reg(cb, R_008A14_PA_CL_ENHANCE, (3 << 1) | 1);
2395
2396 r600_store_context_reg_seq(cb, CM_R_028BD4_PA_SC_CENTROID_PRIORITY_0, 2);
2397 r600_store_value(cb, 0x76543210); /* CM_R_028BD4_PA_SC_CENTROID_PRIORITY_0 */
2398 r600_store_value(cb, 0xfedcba98); /* CM_R_028BD8_PA_SC_CENTROID_PRIORITY_1 */
2399
2400 r600_store_context_reg_seq(cb, R_0288E8_SQ_LDS_ALLOC, 2);
2401 r600_store_value(cb, 0); /* R_0288E8_SQ_LDS_ALLOC */
2402 r600_store_value(cb, 0); /* R_0288EC_SQ_LDS_ALLOC_PS */
2403
2404 r600_store_context_reg(cb, R_0288F0_SQ_VTX_SEMANTIC_CLEAR, ~0);
2405
2406 r600_store_context_reg_seq(cb, R_028400_VGT_MAX_VTX_INDX, 2);
2407 r600_store_value(cb, ~0); /* R_028400_VGT_MAX_VTX_INDX */
2408 r600_store_value(cb, 0); /* R_028404_VGT_MIN_VTX_INDX */
2409
2410 r600_store_ctl_const(cb, R_03CFF0_SQ_VTX_BASE_VTX_LOC, 0);
2411
2412 r600_store_context_reg(cb, R_028028_DB_STENCIL_CLEAR, 0);
2413
2414 r600_store_context_reg(cb, R_0286DC_SPI_FOG_CNTL, 0);
2415
2416 r600_store_context_reg_seq(cb, R_028AC0_DB_SRESULTS_COMPARE_STATE0, 3);
2417 r600_store_value(cb, 0); /* R_028AC0_DB_SRESULTS_COMPARE_STATE0 */
2418 r600_store_value(cb, 0); /* R_028AC4_DB_SRESULTS_COMPARE_STATE1 */
2419 r600_store_value(cb, 0); /* R_028AC8_DB_PRELOAD_CONTROL */
2420
2421 r600_store_context_reg(cb, R_028200_PA_SC_WINDOW_OFFSET, 0);
2422 r600_store_context_reg(cb, R_02820C_PA_SC_CLIPRECT_RULE, 0xFFFF);
2423
2424 r600_store_context_reg_seq(cb, R_0282D0_PA_SC_VPORT_ZMIN_0, 2 * R600_MAX_VIEWPORTS);
2425 for (tmp = 0; tmp < R600_MAX_VIEWPORTS; tmp++) {
2426 r600_store_value(cb, 0); /* R_0282D0_PA_SC_VPORT_ZMIN_0 */
2427 r600_store_value(cb, fui(1.0)); /* R_0282D4_PA_SC_VPORT_ZMAX_0 */
2428 }
2429
2430 r600_store_context_reg(cb, R_028230_PA_SC_EDGERULE, 0xAAAAAAAA);
2431 r600_store_context_reg(cb, R_028820_PA_CL_NANINF_CNTL, 0);
2432
2433 r600_store_context_reg_seq(cb, R_028240_PA_SC_GENERIC_SCISSOR_TL, 2);
2434 r600_store_value(cb, 0); /* R_028240_PA_SC_GENERIC_SCISSOR_TL */
2435 r600_store_value(cb, S_028244_BR_X(16384) | S_028244_BR_Y(16384)); /* R_028244_PA_SC_GENERIC_SCISSOR_BR */
2436
2437 r600_store_context_reg_seq(cb, R_028030_PA_SC_SCREEN_SCISSOR_TL, 2);
2438 r600_store_value(cb, 0); /* R_028030_PA_SC_SCREEN_SCISSOR_TL */
2439 r600_store_value(cb, S_028034_BR_X(16384) | S_028034_BR_Y(16384)); /* R_028034_PA_SC_SCREEN_SCISSOR_BR */
2440
2441 r600_store_context_reg(cb, R_028848_SQ_PGM_RESOURCES_2_PS, S_028848_SINGLE_ROUND(V_SQ_ROUND_NEAREST_EVEN));
2442 r600_store_context_reg(cb, R_028864_SQ_PGM_RESOURCES_2_VS, S_028864_SINGLE_ROUND(V_SQ_ROUND_NEAREST_EVEN));
2443 r600_store_context_reg(cb, R_02887C_SQ_PGM_RESOURCES_2_GS, S_028848_SINGLE_ROUND(V_SQ_ROUND_NEAREST_EVEN));
2444 r600_store_context_reg(cb, R_028894_SQ_PGM_RESOURCES_2_ES, S_028848_SINGLE_ROUND(V_SQ_ROUND_NEAREST_EVEN));
2445 r600_store_context_reg(cb, R_0288C0_SQ_PGM_RESOURCES_2_HS, S_028848_SINGLE_ROUND(V_SQ_ROUND_NEAREST_EVEN));
2446 r600_store_context_reg(cb, R_0288D8_SQ_PGM_RESOURCES_2_LS, S_028848_SINGLE_ROUND(V_SQ_ROUND_NEAREST_EVEN));
2447
2448 r600_store_context_reg(cb, R_0288A8_SQ_PGM_RESOURCES_FS, 0);
2449
2450 /* to avoid GPU doing any preloading of constant from random address */
2451 r600_store_context_reg_seq(cb, R_028140_ALU_CONST_BUFFER_SIZE_PS_0, 16);
2452 for (i = 0; i < 16; i++)
2453 r600_store_value(cb, 0);
2454
2455 r600_store_context_reg_seq(cb, R_028180_ALU_CONST_BUFFER_SIZE_VS_0, 16);
2456 for (i = 0; i < 16; i++)
2457 r600_store_value(cb, 0);
2458
2459 r600_store_context_reg_seq(cb, R_0281C0_ALU_CONST_BUFFER_SIZE_GS_0, 16);
2460 for (i = 0; i < 16; i++)
2461 r600_store_value(cb, 0);
2462
2463 r600_store_context_reg_seq(cb, R_028FC0_ALU_CONST_BUFFER_SIZE_LS_0, 16);
2464 for (i = 0; i < 16; i++)
2465 r600_store_value(cb, 0);
2466
2467 r600_store_context_reg_seq(cb, R_028F80_ALU_CONST_BUFFER_SIZE_HS_0, 16);
2468 for (i = 0; i < 16; i++)
2469 r600_store_value(cb, 0);
2470
2471 if (rctx->screen->b.has_streamout) {
2472 r600_store_context_reg(cb, R_028B28_VGT_STRMOUT_DRAW_OPAQUE_OFFSET, 0);
2473 }
2474
2475 r600_store_context_reg(cb, R_028010_DB_RENDER_OVERRIDE2, 0);
2476 r600_store_context_reg(cb, R_028234_PA_SU_HARDWARE_SCREEN_OFFSET, 0);
2477 r600_store_context_reg(cb, R_0286C8_SPI_THREAD_GROUPING, 0);
2478 r600_store_context_reg_seq(cb, R_0286E4_SPI_PS_IN_CONTROL_2, 2);
2479 r600_store_value(cb, 0); /* R_0286E4_SPI_PS_IN_CONTROL_2 */
2480 r600_store_value(cb, 0); /* R_0286E8_SPI_COMPUTE_INPUT_CNTL */
2481
2482 r600_store_context_reg_seq(cb, R_028B54_VGT_SHADER_STAGES_EN, 2);
2483 r600_store_value(cb, 0); /* R028B54_VGT_SHADER_STAGES_EN */
2484 r600_store_value(cb, 0); /* R028B58_VGT_LS_HS_CONFIG */
2485 r600_store_context_reg(cb, R_028B6C_VGT_TF_PARAM, 0);
2486 eg_store_loop_const(cb, R_03A200_SQ_LOOP_CONST_0, 0x01000FFF);
2487 eg_store_loop_const(cb, R_03A200_SQ_LOOP_CONST_0 + (32 * 4), 0x01000FFF);
2488 eg_store_loop_const(cb, R_03A200_SQ_LOOP_CONST_0 + (64 * 4), 0x01000FFF);
2489 eg_store_loop_const(cb, R_03A200_SQ_LOOP_CONST_0 + (96 * 4), 0x01000FFF);
2490 eg_store_loop_const(cb, R_03A200_SQ_LOOP_CONST_0 + (128 * 4), 0x01000FFF);
2491 }
2492
2493 void evergreen_init_common_regs(struct r600_context *rctx, struct r600_command_buffer *cb,
2494 enum chip_class ctx_chip_class,
2495 enum radeon_family ctx_family,
2496 int ctx_drm_minor)
2497 {
2498 int ps_prio;
2499 int vs_prio;
2500 int gs_prio;
2501 int es_prio;
2502
2503 int hs_prio;
2504 int cs_prio;
2505 int ls_prio;
2506
2507 unsigned tmp;
2508
2509 ps_prio = 0;
2510 vs_prio = 1;
2511 gs_prio = 2;
2512 es_prio = 3;
2513 hs_prio = 3;
2514 ls_prio = 3;
2515 cs_prio = 0;
2516
2517 rctx->default_gprs[R600_HW_STAGE_PS] = 93;
2518 rctx->default_gprs[R600_HW_STAGE_VS] = 46;
2519 rctx->r6xx_num_clause_temp_gprs = 4;
2520 rctx->default_gprs[R600_HW_STAGE_GS] = 31;
2521 rctx->default_gprs[R600_HW_STAGE_ES] = 31;
2522 rctx->default_gprs[EG_HW_STAGE_HS] = 23;
2523 rctx->default_gprs[EG_HW_STAGE_LS] = 23;
2524
2525 tmp = 0;
2526 switch (ctx_family) {
2527 case CHIP_CEDAR:
2528 case CHIP_PALM:
2529 case CHIP_SUMO:
2530 case CHIP_SUMO2:
2531 case CHIP_CAICOS:
2532 break;
2533 default:
2534 tmp |= S_008C00_VC_ENABLE(1);
2535 break;
2536 }
2537 tmp |= S_008C00_EXPORT_SRC_C(1);
2538 tmp |= S_008C00_CS_PRIO(cs_prio);
2539 tmp |= S_008C00_LS_PRIO(ls_prio);
2540 tmp |= S_008C00_HS_PRIO(hs_prio);
2541 tmp |= S_008C00_PS_PRIO(ps_prio);
2542 tmp |= S_008C00_VS_PRIO(vs_prio);
2543 tmp |= S_008C00_GS_PRIO(gs_prio);
2544 tmp |= S_008C00_ES_PRIO(es_prio);
2545
2546 r600_store_config_reg_seq(cb, R_008C00_SQ_CONFIG, 1);
2547 r600_store_value(cb, tmp); /* R_008C00_SQ_CONFIG */
2548
2549 r600_store_config_reg_seq(cb, R_008C10_SQ_GLOBAL_GPR_RESOURCE_MGMT_1, 2);
2550 r600_store_value(cb, 0); /* R_008C10_SQ_GLOBAL_GPR_RESOURCE_MGMT_1 */
2551 r600_store_value(cb, 0); /* R_008C14_SQ_GLOBAL_GPR_RESOURCE_MGMT_2 */
2552
2553 /* The cs checker requires this register to be set. */
2554 r600_store_context_reg(cb, R_028800_DB_DEPTH_CONTROL, 0);
2555
2556 r600_store_context_reg_seq(cb, R_028350_SX_MISC, 2);
2557 r600_store_value(cb, 0);
2558 r600_store_value(cb, S_028354_SURFACE_SYNC_MASK(0xf));
2559
2560 return;
2561 }
2562
2563 void evergreen_init_atom_start_cs(struct r600_context *rctx)
2564 {
2565 struct r600_command_buffer *cb = &rctx->start_cs_cmd;
2566 int num_ps_threads;
2567 int num_vs_threads;
2568 int num_gs_threads;
2569 int num_es_threads;
2570 int num_hs_threads;
2571 int num_ls_threads;
2572
2573 int num_ps_stack_entries;
2574 int num_vs_stack_entries;
2575 int num_gs_stack_entries;
2576 int num_es_stack_entries;
2577 int num_hs_stack_entries;
2578 int num_ls_stack_entries;
2579 enum radeon_family family;
2580 unsigned tmp, i;
2581
2582 if (rctx->b.chip_class == CAYMAN) {
2583 cayman_init_atom_start_cs(rctx);
2584 return;
2585 }
2586
2587 r600_init_command_buffer(cb, 338);
2588
2589 /* This must be first. */
2590 r600_store_value(cb, PKT3(PKT3_CONTEXT_CONTROL, 1, 0));
2591 r600_store_value(cb, 0x80000000);
2592 r600_store_value(cb, 0x80000000);
2593
2594 /* We're setting config registers here. */
2595 r600_store_value(cb, PKT3(PKT3_EVENT_WRITE, 0, 0));
2596 r600_store_value(cb, EVENT_TYPE(EVENT_TYPE_PS_PARTIAL_FLUSH) | EVENT_INDEX(4));
2597
2598 /* This enables pipeline stat & streamout queries.
2599 * They are only disabled by blits.
2600 */
2601 r600_store_value(cb, PKT3(PKT3_EVENT_WRITE, 0, 0));
2602 r600_store_value(cb, EVENT_TYPE(EVENT_TYPE_PIPELINESTAT_START) | EVENT_INDEX(0));
2603
2604 evergreen_init_common_regs(rctx, cb, rctx->b.chip_class,
2605 rctx->b.family, rctx->screen->b.info.drm_minor);
2606
2607 family = rctx->b.family;
2608 switch (family) {
2609 case CHIP_CEDAR:
2610 default:
2611 num_ps_threads = 96;
2612 num_vs_threads = 16;
2613 num_gs_threads = 16;
2614 num_es_threads = 16;
2615 num_hs_threads = 16;
2616 num_ls_threads = 16;
2617 num_ps_stack_entries = 42;
2618 num_vs_stack_entries = 42;
2619 num_gs_stack_entries = 42;
2620 num_es_stack_entries = 42;
2621 num_hs_stack_entries = 42;
2622 num_ls_stack_entries = 42;
2623 break;
2624 case CHIP_REDWOOD:
2625 num_ps_threads = 128;
2626 num_vs_threads = 20;
2627 num_gs_threads = 20;
2628 num_es_threads = 20;
2629 num_hs_threads = 20;
2630 num_ls_threads = 20;
2631 num_ps_stack_entries = 42;
2632 num_vs_stack_entries = 42;
2633 num_gs_stack_entries = 42;
2634 num_es_stack_entries = 42;
2635 num_hs_stack_entries = 42;
2636 num_ls_stack_entries = 42;
2637 break;
2638 case CHIP_JUNIPER:
2639 num_ps_threads = 128;
2640 num_vs_threads = 20;
2641 num_gs_threads = 20;
2642 num_es_threads = 20;
2643 num_hs_threads = 20;
2644 num_ls_threads = 20;
2645 num_ps_stack_entries = 85;
2646 num_vs_stack_entries = 85;
2647 num_gs_stack_entries = 85;
2648 num_es_stack_entries = 85;
2649 num_hs_stack_entries = 85;
2650 num_ls_stack_entries = 85;
2651 break;
2652 case CHIP_CYPRESS:
2653 case CHIP_HEMLOCK:
2654 num_ps_threads = 128;
2655 num_vs_threads = 20;
2656 num_gs_threads = 20;
2657 num_es_threads = 20;
2658 num_hs_threads = 20;
2659 num_ls_threads = 20;
2660 num_ps_stack_entries = 85;
2661 num_vs_stack_entries = 85;
2662 num_gs_stack_entries = 85;
2663 num_es_stack_entries = 85;
2664 num_hs_stack_entries = 85;
2665 num_ls_stack_entries = 85;
2666 break;
2667 case CHIP_PALM:
2668 num_ps_threads = 96;
2669 num_vs_threads = 16;
2670 num_gs_threads = 16;
2671 num_es_threads = 16;
2672 num_hs_threads = 16;
2673 num_ls_threads = 16;
2674 num_ps_stack_entries = 42;
2675 num_vs_stack_entries = 42;
2676 num_gs_stack_entries = 42;
2677 num_es_stack_entries = 42;
2678 num_hs_stack_entries = 42;
2679 num_ls_stack_entries = 42;
2680 break;
2681 case CHIP_SUMO:
2682 num_ps_threads = 96;
2683 num_vs_threads = 25;
2684 num_gs_threads = 25;
2685 num_es_threads = 25;
2686 num_hs_threads = 16;
2687 num_ls_threads = 16;
2688 num_ps_stack_entries = 42;
2689 num_vs_stack_entries = 42;
2690 num_gs_stack_entries = 42;
2691 num_es_stack_entries = 42;
2692 num_hs_stack_entries = 42;
2693 num_ls_stack_entries = 42;
2694 break;
2695 case CHIP_SUMO2:
2696 num_ps_threads = 96;
2697 num_vs_threads = 25;
2698 num_gs_threads = 25;
2699 num_es_threads = 25;
2700 num_hs_threads = 16;
2701 num_ls_threads = 16;
2702 num_ps_stack_entries = 85;
2703 num_vs_stack_entries = 85;
2704 num_gs_stack_entries = 85;
2705 num_es_stack_entries = 85;
2706 num_hs_stack_entries = 85;
2707 num_ls_stack_entries = 85;
2708 break;
2709 case CHIP_BARTS:
2710 num_ps_threads = 128;
2711 num_vs_threads = 20;
2712 num_gs_threads = 20;
2713 num_es_threads = 20;
2714 num_hs_threads = 20;
2715 num_ls_threads = 20;
2716 num_ps_stack_entries = 85;
2717 num_vs_stack_entries = 85;
2718 num_gs_stack_entries = 85;
2719 num_es_stack_entries = 85;
2720 num_hs_stack_entries = 85;
2721 num_ls_stack_entries = 85;
2722 break;
2723 case CHIP_TURKS:
2724 num_ps_threads = 128;
2725 num_vs_threads = 20;
2726 num_gs_threads = 20;
2727 num_es_threads = 20;
2728 num_hs_threads = 20;
2729 num_ls_threads = 20;
2730 num_ps_stack_entries = 42;
2731 num_vs_stack_entries = 42;
2732 num_gs_stack_entries = 42;
2733 num_es_stack_entries = 42;
2734 num_hs_stack_entries = 42;
2735 num_ls_stack_entries = 42;
2736 break;
2737 case CHIP_CAICOS:
2738 num_ps_threads = 96;
2739 num_vs_threads = 10;
2740 num_gs_threads = 10;
2741 num_es_threads = 10;
2742 num_hs_threads = 10;
2743 num_ls_threads = 10;
2744 num_ps_stack_entries = 42;
2745 num_vs_stack_entries = 42;
2746 num_gs_stack_entries = 42;
2747 num_es_stack_entries = 42;
2748 num_hs_stack_entries = 42;
2749 num_ls_stack_entries = 42;
2750 break;
2751 }
2752
2753 tmp = S_008C18_NUM_PS_THREADS(num_ps_threads);
2754 tmp |= S_008C18_NUM_VS_THREADS(num_vs_threads);
2755 tmp |= S_008C18_NUM_GS_THREADS(num_gs_threads);
2756 tmp |= S_008C18_NUM_ES_THREADS(num_es_threads);
2757
2758 r600_store_config_reg_seq(cb, R_008C18_SQ_THREAD_RESOURCE_MGMT_1, 5);
2759 r600_store_value(cb, tmp); /* R_008C18_SQ_THREAD_RESOURCE_MGMT_1 */
2760
2761 tmp = S_008C1C_NUM_HS_THREADS(num_hs_threads);
2762 tmp |= S_008C1C_NUM_LS_THREADS(num_ls_threads);
2763 r600_store_value(cb, tmp); /* R_008C1C_SQ_THREAD_RESOURCE_MGMT_2 */
2764
2765 tmp = S_008C20_NUM_PS_STACK_ENTRIES(num_ps_stack_entries);
2766 tmp |= S_008C20_NUM_VS_STACK_ENTRIES(num_vs_stack_entries);
2767 r600_store_value(cb, tmp); /* R_008C20_SQ_STACK_RESOURCE_MGMT_1 */
2768
2769 tmp = S_008C24_NUM_GS_STACK_ENTRIES(num_gs_stack_entries);
2770 tmp |= S_008C24_NUM_ES_STACK_ENTRIES(num_es_stack_entries);
2771 r600_store_value(cb, tmp); /* R_008C24_SQ_STACK_RESOURCE_MGMT_2 */
2772
2773 tmp = S_008C28_NUM_HS_STACK_ENTRIES(num_hs_stack_entries);
2774 tmp |= S_008C28_NUM_LS_STACK_ENTRIES(num_ls_stack_entries);
2775 r600_store_value(cb, tmp); /* R_008C28_SQ_STACK_RESOURCE_MGMT_3 */
2776
2777 r600_store_config_reg(cb, R_008E2C_SQ_LDS_RESOURCE_MGMT,
2778 S_008E2C_NUM_PS_LDS(0x1000) | S_008E2C_NUM_LS_LDS(0x1000));
2779
2780 /* remove LS/HS from one SIMD for hw workaround */
2781 r600_store_config_reg_seq(cb, R_008E20_SQ_STATIC_THREAD_MGMT1, 3);
2782 r600_store_value(cb, 0xffffffff);
2783 r600_store_value(cb, 0xffffffff);
2784 r600_store_value(cb, 0xfffffffe);
2785
2786 r600_store_config_reg(cb, R_009100_SPI_CONFIG_CNTL, 0);
2787 r600_store_config_reg(cb, R_00913C_SPI_CONFIG_CNTL_1, S_00913C_VTX_DONE_DELAY(4));
2788
2789 r600_store_context_reg_seq(cb, R_028900_SQ_ESGS_RING_ITEMSIZE, 6);
2790 r600_store_value(cb, 0); /* R_028900_SQ_ESGS_RING_ITEMSIZE */
2791 r600_store_value(cb, 0); /* R_028904_SQ_GSVS_RING_ITEMSIZE */
2792 r600_store_value(cb, 0); /* R_028908_SQ_ESTMP_RING_ITEMSIZE */
2793 r600_store_value(cb, 0); /* R_02890C_SQ_GSTMP_RING_ITEMSIZE */
2794 r600_store_value(cb, 0); /* R_028910_SQ_VSTMP_RING_ITEMSIZE */
2795 r600_store_value(cb, 0); /* R_028914_SQ_PSTMP_RING_ITEMSIZE */
2796
2797 r600_store_context_reg_seq(cb, R_02891C_SQ_GS_VERT_ITEMSIZE, 4);
2798 r600_store_value(cb, 0); /* R_02891C_SQ_GS_VERT_ITEMSIZE */
2799 r600_store_value(cb, 0); /* R_028920_SQ_GS_VERT_ITEMSIZE_1 */
2800 r600_store_value(cb, 0); /* R_028924_SQ_GS_VERT_ITEMSIZE_2 */
2801 r600_store_value(cb, 0); /* R_028928_SQ_GS_VERT_ITEMSIZE_3 */
2802
2803 r600_store_context_reg_seq(cb, R_028A10_VGT_OUTPUT_PATH_CNTL, 13);
2804 r600_store_value(cb, 0); /* R_028A10_VGT_OUTPUT_PATH_CNTL */
2805 r600_store_value(cb, 0); /* R_028A14_VGT_HOS_CNTL */
2806 r600_store_value(cb, fui(64)); /* R_028A18_VGT_HOS_MAX_TESS_LEVEL */
2807 r600_store_value(cb, fui(1.0)); /* R_028A1C_VGT_HOS_MIN_TESS_LEVEL */
2808 r600_store_value(cb, 16); /* R_028A20_VGT_HOS_REUSE_DEPTH */
2809 r600_store_value(cb, 0); /* R_028A24_VGT_GROUP_PRIM_TYPE */
2810 r600_store_value(cb, 0); /* R_028A28_VGT_GROUP_FIRST_DECR */
2811 r600_store_value(cb, 0); /* R_028A2C_VGT_GROUP_DECR */
2812 r600_store_value(cb, 0); /* R_028A30_VGT_GROUP_VECT_0_CNTL */
2813 r600_store_value(cb, 0); /* R_028A34_VGT_GROUP_VECT_1_CNTL */
2814 r600_store_value(cb, 0); /* R_028A38_VGT_GROUP_VECT_0_FMT_CNTL */
2815 r600_store_value(cb, 0); /* R_028A3C_VGT_GROUP_VECT_1_FMT_CNTL */
2816 r600_store_value(cb, 0); /* R_028A40_VGT_GS_MODE */
2817
2818 r600_store_config_reg(cb, R_008A14_PA_CL_ENHANCE, (3 << 1) | 1);
2819
2820 r600_store_context_reg(cb, R_0288F0_SQ_VTX_SEMANTIC_CLEAR, ~0);
2821
2822 r600_store_context_reg_seq(cb, R_028400_VGT_MAX_VTX_INDX, 2);
2823 r600_store_value(cb, ~0); /* R_028400_VGT_MAX_VTX_INDX */
2824 r600_store_value(cb, 0); /* R_028404_VGT_MIN_VTX_INDX */
2825
2826 r600_store_ctl_const(cb, R_03CFF0_SQ_VTX_BASE_VTX_LOC, 0);
2827
2828 r600_store_context_reg(cb, R_028028_DB_STENCIL_CLEAR, 0);
2829
2830 r600_store_context_reg(cb, R_028200_PA_SC_WINDOW_OFFSET, 0);
2831 r600_store_context_reg(cb, R_02820C_PA_SC_CLIPRECT_RULE, 0xFFFF);
2832 r600_store_context_reg(cb, R_028230_PA_SC_EDGERULE, 0xAAAAAAAA);
2833
2834 r600_store_context_reg_seq(cb, R_0282D0_PA_SC_VPORT_ZMIN_0, 2 * R600_MAX_VIEWPORTS);
2835 for (tmp = 0; tmp < R600_MAX_VIEWPORTS; tmp++) {
2836 r600_store_value(cb, 0); /* R_0282D0_PA_SC_VPORT_ZMIN_0 */
2837 r600_store_value(cb, fui(1.0)); /* R_0282D4_PA_SC_VPORT_ZMAX_0 */
2838 }
2839
2840 r600_store_context_reg(cb, R_0286DC_SPI_FOG_CNTL, 0);
2841 r600_store_context_reg(cb, R_028820_PA_CL_NANINF_CNTL, 0);
2842
2843 r600_store_context_reg_seq(cb, R_028AC0_DB_SRESULTS_COMPARE_STATE0, 3);
2844 r600_store_value(cb, 0); /* R_028AC0_DB_SRESULTS_COMPARE_STATE0 */
2845 r600_store_value(cb, 0); /* R_028AC4_DB_SRESULTS_COMPARE_STATE1 */
2846 r600_store_value(cb, 0); /* R_028AC8_DB_PRELOAD_CONTROL */
2847
2848 r600_store_context_reg_seq(cb, R_028240_PA_SC_GENERIC_SCISSOR_TL, 2);
2849 r600_store_value(cb, 0); /* R_028240_PA_SC_GENERIC_SCISSOR_TL */
2850 r600_store_value(cb, S_028244_BR_X(16384) | S_028244_BR_Y(16384)); /* R_028244_PA_SC_GENERIC_SCISSOR_BR */
2851
2852 r600_store_context_reg_seq(cb, R_028030_PA_SC_SCREEN_SCISSOR_TL, 2);
2853 r600_store_value(cb, 0); /* R_028030_PA_SC_SCREEN_SCISSOR_TL */
2854 r600_store_value(cb, S_028034_BR_X(16384) | S_028034_BR_Y(16384)); /* R_028034_PA_SC_SCREEN_SCISSOR_BR */
2855
2856 r600_store_context_reg(cb, R_028848_SQ_PGM_RESOURCES_2_PS, S_028848_SINGLE_ROUND(V_SQ_ROUND_NEAREST_EVEN));
2857 r600_store_context_reg(cb, R_028864_SQ_PGM_RESOURCES_2_VS, S_028864_SINGLE_ROUND(V_SQ_ROUND_NEAREST_EVEN));
2858 r600_store_context_reg(cb, R_02887C_SQ_PGM_RESOURCES_2_GS, S_028848_SINGLE_ROUND(V_SQ_ROUND_NEAREST_EVEN));
2859 r600_store_context_reg(cb, R_028894_SQ_PGM_RESOURCES_2_ES, S_028848_SINGLE_ROUND(V_SQ_ROUND_NEAREST_EVEN));
2860 r600_store_context_reg(cb, R_0288A8_SQ_PGM_RESOURCES_FS, 0);
2861 r600_store_context_reg(cb, R_0288C0_SQ_PGM_RESOURCES_2_HS, S_028848_SINGLE_ROUND(V_SQ_ROUND_NEAREST_EVEN));
2862 r600_store_context_reg(cb, R_0288D8_SQ_PGM_RESOURCES_2_LS, S_028848_SINGLE_ROUND(V_SQ_ROUND_NEAREST_EVEN));
2863
2864 /* to avoid GPU doing any preloading of constant from random address */
2865 r600_store_context_reg_seq(cb, R_028140_ALU_CONST_BUFFER_SIZE_PS_0, 16);
2866 for (i = 0; i < 16; i++)
2867 r600_store_value(cb, 0);
2868
2869 r600_store_context_reg_seq(cb, R_028180_ALU_CONST_BUFFER_SIZE_VS_0, 16);
2870 for (i = 0; i < 16; i++)
2871 r600_store_value(cb, 0);
2872
2873 r600_store_context_reg_seq(cb, R_0281C0_ALU_CONST_BUFFER_SIZE_GS_0, 16);
2874 for (i = 0; i < 16; i++)
2875 r600_store_value(cb, 0);
2876
2877 r600_store_context_reg_seq(cb, R_028FC0_ALU_CONST_BUFFER_SIZE_LS_0, 16);
2878 for (i = 0; i < 16; i++)
2879 r600_store_value(cb, 0);
2880
2881 r600_store_context_reg_seq(cb, R_028F80_ALU_CONST_BUFFER_SIZE_HS_0, 16);
2882 for (i = 0; i < 16; i++)
2883 r600_store_value(cb, 0);
2884
2885 r600_store_context_reg(cb, R_028B98_VGT_STRMOUT_BUFFER_CONFIG, 0);
2886
2887 if (rctx->screen->b.has_streamout) {
2888 r600_store_context_reg(cb, R_028B28_VGT_STRMOUT_DRAW_OPAQUE_OFFSET, 0);
2889 }
2890
2891 r600_store_context_reg(cb, R_028010_DB_RENDER_OVERRIDE2, 0);
2892 r600_store_context_reg(cb, R_028234_PA_SU_HARDWARE_SCREEN_OFFSET, 0);
2893 r600_store_context_reg(cb, R_0286C8_SPI_THREAD_GROUPING, 0);
2894 r600_store_context_reg_seq(cb, R_0286E4_SPI_PS_IN_CONTROL_2, 2);
2895 r600_store_value(cb, 0); /* R_0286E4_SPI_PS_IN_CONTROL_2 */
2896 r600_store_value(cb, 0); /* R_0286E8_SPI_COMPUTE_INPUT_CNTL */
2897
2898 r600_store_context_reg_seq(cb, R_0288E8_SQ_LDS_ALLOC, 2);
2899 r600_store_value(cb, 0); /* R_0288E8_SQ_LDS_ALLOC */
2900 r600_store_value(cb, 0); /* R_0288EC_SQ_LDS_ALLOC_PS */
2901
2902 if (rctx->b.family == CHIP_CAICOS) {
2903 r600_store_context_reg_seq(cb, R_028B54_VGT_SHADER_STAGES_EN, 2);
2904 r600_store_value(cb, 0); /* R028B54_VGT_SHADER_STAGES_EN */
2905 r600_store_value(cb, 0); /* R028B58_VGT_LS_HS_CONFIG */
2906 r600_store_context_reg(cb, R_028B6C_VGT_TF_PARAM, 0);
2907 } else {
2908 r600_store_context_reg_seq(cb, R_028B54_VGT_SHADER_STAGES_EN, 7);
2909 r600_store_value(cb, 0); /* R028B54_VGT_SHADER_STAGES_EN */
2910 r600_store_value(cb, 0); /* R028B58_VGT_LS_HS_CONFIG */
2911 r600_store_value(cb, 0); /* R028B5C_VGT_LS_SIZE */
2912 r600_store_value(cb, 0); /* R028B60_VGT_HS_SIZE */
2913 r600_store_value(cb, 0); /* R028B64_VGT_LS_HS_ALLOC */
2914 r600_store_value(cb, 0); /* R028B68_VGT_HS_PATCH_CONST */
2915 r600_store_value(cb, 0); /* R028B68_VGT_TF_PARAM */
2916 }
2917
2918 eg_store_loop_const(cb, R_03A200_SQ_LOOP_CONST_0, 0x01000FFF);
2919 eg_store_loop_const(cb, R_03A200_SQ_LOOP_CONST_0 + (32 * 4), 0x01000FFF);
2920 eg_store_loop_const(cb, R_03A200_SQ_LOOP_CONST_0 + (64 * 4), 0x01000FFF);
2921 eg_store_loop_const(cb, R_03A200_SQ_LOOP_CONST_0 + (96 * 4), 0x01000FFF);
2922 eg_store_loop_const(cb, R_03A200_SQ_LOOP_CONST_0 + (128 * 4), 0x01000FFF);
2923 }
2924
2925 void evergreen_update_ps_state(struct pipe_context *ctx, struct r600_pipe_shader *shader)
2926 {
2927 struct r600_context *rctx = (struct r600_context *)ctx;
2928 struct r600_command_buffer *cb = &shader->command_buffer;
2929 struct r600_shader *rshader = &shader->shader;
2930 unsigned i, exports_ps, num_cout, spi_ps_in_control_0, spi_input_z, spi_ps_in_control_1, db_shader_control = 0;
2931 int pos_index = -1, face_index = -1, fixed_pt_position_index = -1;
2932 int ninterp = 0;
2933 boolean have_perspective = FALSE, have_linear = FALSE;
2934 static const unsigned spi_baryc_enable_bit[6] = {
2935 S_0286E0_PERSP_SAMPLE_ENA(1),
2936 S_0286E0_PERSP_CENTER_ENA(1),
2937 S_0286E0_PERSP_CENTROID_ENA(1),
2938 S_0286E0_LINEAR_SAMPLE_ENA(1),
2939 S_0286E0_LINEAR_CENTER_ENA(1),
2940 S_0286E0_LINEAR_CENTROID_ENA(1)
2941 };
2942 unsigned spi_baryc_cntl = 0, sid, tmp, num = 0;
2943 unsigned z_export = 0, stencil_export = 0, mask_export = 0;
2944 unsigned sprite_coord_enable = rctx->rasterizer ? rctx->rasterizer->sprite_coord_enable : 0;
2945 uint32_t spi_ps_input_cntl[32];
2946
2947 if (!cb->buf) {
2948 r600_init_command_buffer(cb, 64);
2949 } else {
2950 cb->num_dw = 0;
2951 }
2952
2953 for (i = 0; i < rshader->ninput; i++) {
2954 /* evergreen NUM_INTERP only contains values interpolated into the LDS,
2955 POSITION goes via GPRs from the SC so isn't counted */
2956 if (rshader->input[i].name == TGSI_SEMANTIC_POSITION)
2957 pos_index = i;
2958 else if (rshader->input[i].name == TGSI_SEMANTIC_FACE) {
2959 if (face_index == -1)
2960 face_index = i;
2961 }
2962 else if (rshader->input[i].name == TGSI_SEMANTIC_SAMPLEMASK) {
2963 if (face_index == -1)
2964 face_index = i; /* lives in same register, same enable bit */
2965 }
2966 else if (rshader->input[i].name == TGSI_SEMANTIC_SAMPLEID) {
2967 fixed_pt_position_index = i;
2968 }
2969 else {
2970 ninterp++;
2971 int k = eg_get_interpolator_index(
2972 rshader->input[i].interpolate,
2973 rshader->input[i].interpolate_location);
2974 if (k >= 0) {
2975 spi_baryc_cntl |= spi_baryc_enable_bit[k];
2976 have_perspective |= k < 3;
2977 have_linear |= !(k < 3);
2978 }
2979 }
2980
2981 sid = rshader->input[i].spi_sid;
2982
2983 if (sid) {
2984 tmp = S_028644_SEMANTIC(sid);
2985
2986 /* D3D 9 behaviour. GL is undefined */
2987 if (rshader->input[i].name == TGSI_SEMANTIC_COLOR && rshader->input[i].sid == 0)
2988 tmp |= S_028644_DEFAULT_VAL(3);
2989
2990 if (rshader->input[i].name == TGSI_SEMANTIC_POSITION ||
2991 rshader->input[i].interpolate == TGSI_INTERPOLATE_CONSTANT ||
2992 (rshader->input[i].interpolate == TGSI_INTERPOLATE_COLOR &&
2993 rctx->rasterizer && rctx->rasterizer->flatshade)) {
2994 tmp |= S_028644_FLAT_SHADE(1);
2995 }
2996
2997 if (rshader->input[i].name == TGSI_SEMANTIC_GENERIC &&
2998 (sprite_coord_enable & (1 << rshader->input[i].sid))) {
2999 tmp |= S_028644_PT_SPRITE_TEX(1);
3000 }
3001
3002 spi_ps_input_cntl[num++] = tmp;
3003 }
3004 }
3005
3006 r600_store_context_reg_seq(cb, R_028644_SPI_PS_INPUT_CNTL_0, num);
3007 r600_store_array(cb, num, spi_ps_input_cntl);
3008
3009 for (i = 0; i < rshader->noutput; i++) {
3010 if (rshader->output[i].name == TGSI_SEMANTIC_POSITION)
3011 z_export = 1;
3012 if (rshader->output[i].name == TGSI_SEMANTIC_STENCIL)
3013 stencil_export = 1;
3014 if (rshader->output[i].name == TGSI_SEMANTIC_SAMPLEMASK &&
3015 rctx->framebuffer.nr_samples > 1 && rctx->ps_iter_samples > 0)
3016 mask_export = 1;
3017 }
3018 if (rshader->uses_kill)
3019 db_shader_control |= S_02880C_KILL_ENABLE(1);
3020
3021 db_shader_control |= S_02880C_Z_EXPORT_ENABLE(z_export);
3022 db_shader_control |= S_02880C_STENCIL_EXPORT_ENABLE(stencil_export);
3023 db_shader_control |= S_02880C_MASK_EXPORT_ENABLE(mask_export);
3024
3025 switch (rshader->ps_conservative_z) {
3026 default: /* fall through */
3027 case TGSI_FS_DEPTH_LAYOUT_ANY:
3028 db_shader_control |= S_02880C_CONSERVATIVE_Z_EXPORT(V_02880C_EXPORT_ANY_Z);
3029 break;
3030 case TGSI_FS_DEPTH_LAYOUT_GREATER:
3031 db_shader_control |= S_02880C_CONSERVATIVE_Z_EXPORT(V_02880C_EXPORT_GREATER_THAN_Z);
3032 break;
3033 case TGSI_FS_DEPTH_LAYOUT_LESS:
3034 db_shader_control |= S_02880C_CONSERVATIVE_Z_EXPORT(V_02880C_EXPORT_LESS_THAN_Z);
3035 break;
3036 }
3037
3038 exports_ps = 0;
3039 for (i = 0; i < rshader->noutput; i++) {
3040 if (rshader->output[i].name == TGSI_SEMANTIC_POSITION ||
3041 rshader->output[i].name == TGSI_SEMANTIC_STENCIL ||
3042 rshader->output[i].name == TGSI_SEMANTIC_SAMPLEMASK)
3043 exports_ps |= 1;
3044 }
3045
3046 num_cout = rshader->nr_ps_color_exports;
3047
3048 exports_ps |= S_02884C_EXPORT_COLORS(num_cout);
3049 if (!exports_ps) {
3050 /* always at least export 1 component per pixel */
3051 exports_ps = 2;
3052 }
3053 shader->nr_ps_color_outputs = num_cout;
3054 if (ninterp == 0) {
3055 ninterp = 1;
3056 have_perspective = TRUE;
3057 }
3058 if (!spi_baryc_cntl)
3059 spi_baryc_cntl |= spi_baryc_enable_bit[0];
3060
3061 if (!have_perspective && !have_linear)
3062 have_perspective = TRUE;
3063
3064 spi_ps_in_control_0 = S_0286CC_NUM_INTERP(ninterp) |
3065 S_0286CC_PERSP_GRADIENT_ENA(have_perspective) |
3066 S_0286CC_LINEAR_GRADIENT_ENA(have_linear);
3067 spi_input_z = 0;
3068 if (pos_index != -1) {
3069 spi_ps_in_control_0 |= S_0286CC_POSITION_ENA(1) |
3070 S_0286CC_POSITION_CENTROID(rshader->input[pos_index].interpolate_location == TGSI_INTERPOLATE_LOC_CENTROID) |
3071 S_0286CC_POSITION_ADDR(rshader->input[pos_index].gpr);
3072 spi_input_z |= S_0286D8_PROVIDE_Z_TO_SPI(1);
3073 }
3074
3075 spi_ps_in_control_1 = 0;
3076 if (face_index != -1) {
3077 spi_ps_in_control_1 |= S_0286D0_FRONT_FACE_ENA(1) |
3078 S_0286D0_FRONT_FACE_ADDR(rshader->input[face_index].gpr);
3079 }
3080 if (fixed_pt_position_index != -1) {
3081 spi_ps_in_control_1 |= S_0286D0_FIXED_PT_POSITION_ENA(1) |
3082 S_0286D0_FIXED_PT_POSITION_ADDR(rshader->input[fixed_pt_position_index].gpr);
3083 }
3084
3085 r600_store_context_reg_seq(cb, R_0286CC_SPI_PS_IN_CONTROL_0, 2);
3086 r600_store_value(cb, spi_ps_in_control_0); /* R_0286CC_SPI_PS_IN_CONTROL_0 */
3087 r600_store_value(cb, spi_ps_in_control_1); /* R_0286D0_SPI_PS_IN_CONTROL_1 */
3088
3089 r600_store_context_reg(cb, R_0286E0_SPI_BARYC_CNTL, spi_baryc_cntl);
3090 r600_store_context_reg(cb, R_0286D8_SPI_INPUT_Z, spi_input_z);
3091 r600_store_context_reg(cb, R_02884C_SQ_PGM_EXPORTS_PS, exports_ps);
3092
3093 r600_store_context_reg_seq(cb, R_028840_SQ_PGM_START_PS, 2);
3094 r600_store_value(cb, shader->bo->gpu_address >> 8);
3095 r600_store_value(cb, /* R_028844_SQ_PGM_RESOURCES_PS */
3096 S_028844_NUM_GPRS(rshader->bc.ngpr) |
3097 S_028844_PRIME_CACHE_ON_DRAW(1) |
3098 S_028844_STACK_SIZE(rshader->bc.nstack));
3099 /* After that, the NOP relocation packet must be emitted (shader->bo, RADEON_USAGE_READ). */
3100
3101 shader->db_shader_control = db_shader_control;
3102 shader->ps_depth_export = z_export | stencil_export | mask_export;
3103
3104 shader->sprite_coord_enable = sprite_coord_enable;
3105 if (rctx->rasterizer)
3106 shader->flatshade = rctx->rasterizer->flatshade;
3107 }
3108
3109 void evergreen_update_es_state(struct pipe_context *ctx, struct r600_pipe_shader *shader)
3110 {
3111 struct r600_command_buffer *cb = &shader->command_buffer;
3112 struct r600_shader *rshader = &shader->shader;
3113
3114 r600_init_command_buffer(cb, 32);
3115
3116 r600_store_context_reg(cb, R_028890_SQ_PGM_RESOURCES_ES,
3117 S_028890_NUM_GPRS(rshader->bc.ngpr) |
3118 S_028890_STACK_SIZE(rshader->bc.nstack));
3119 r600_store_context_reg(cb, R_02888C_SQ_PGM_START_ES,
3120 shader->bo->gpu_address >> 8);
3121 /* After that, the NOP relocation packet must be emitted (shader->bo, RADEON_USAGE_READ). */
3122 }
3123
3124 void evergreen_update_gs_state(struct pipe_context *ctx, struct r600_pipe_shader *shader)
3125 {
3126 struct r600_context *rctx = (struct r600_context *)ctx;
3127 struct r600_command_buffer *cb = &shader->command_buffer;
3128 struct r600_shader *rshader = &shader->shader;
3129 struct r600_shader *cp_shader = &shader->gs_copy_shader->shader;
3130 unsigned gsvs_itemsizes[4] = {
3131 (cp_shader->ring_item_sizes[0] * shader->selector->gs_max_out_vertices) >> 2,
3132 (cp_shader->ring_item_sizes[1] * shader->selector->gs_max_out_vertices) >> 2,
3133 (cp_shader->ring_item_sizes[2] * shader->selector->gs_max_out_vertices) >> 2,
3134 (cp_shader->ring_item_sizes[3] * shader->selector->gs_max_out_vertices) >> 2
3135 };
3136
3137 r600_init_command_buffer(cb, 64);
3138
3139 /* VGT_GS_MODE is written by evergreen_emit_shader_stages */
3140
3141
3142 r600_store_context_reg(cb, R_028B38_VGT_GS_MAX_VERT_OUT,
3143 S_028B38_MAX_VERT_OUT(shader->selector->gs_max_out_vertices));
3144 r600_store_context_reg(cb, R_028A6C_VGT_GS_OUT_PRIM_TYPE,
3145 r600_conv_prim_to_gs_out(shader->selector->gs_output_prim));
3146
3147 if (rctx->screen->b.info.drm_minor >= 35) {
3148 r600_store_context_reg(cb, R_028B90_VGT_GS_INSTANCE_CNT,
3149 S_028B90_CNT(MIN2(shader->selector->gs_num_invocations, 127)) |
3150 S_028B90_ENABLE(shader->selector->gs_num_invocations > 0));
3151 }
3152 r600_store_context_reg_seq(cb, R_02891C_SQ_GS_VERT_ITEMSIZE, 4);
3153 r600_store_value(cb, cp_shader->ring_item_sizes[0] >> 2);
3154 r600_store_value(cb, cp_shader->ring_item_sizes[1] >> 2);
3155 r600_store_value(cb, cp_shader->ring_item_sizes[2] >> 2);
3156 r600_store_value(cb, cp_shader->ring_item_sizes[3] >> 2);
3157
3158 r600_store_context_reg(cb, R_028900_SQ_ESGS_RING_ITEMSIZE,
3159 (rshader->ring_item_sizes[0]) >> 2);
3160
3161 r600_store_context_reg(cb, R_028904_SQ_GSVS_RING_ITEMSIZE,
3162 gsvs_itemsizes[0] +
3163 gsvs_itemsizes[1] +
3164 gsvs_itemsizes[2] +
3165 gsvs_itemsizes[3]);
3166
3167 r600_store_context_reg_seq(cb, R_02892C_SQ_GSVS_RING_OFFSET_1, 3);
3168 r600_store_value(cb, gsvs_itemsizes[0]);
3169 r600_store_value(cb, gsvs_itemsizes[0] + gsvs_itemsizes[1]);
3170 r600_store_value(cb, gsvs_itemsizes[0] + gsvs_itemsizes[1] + gsvs_itemsizes[2]);
3171
3172 /* FIXME calculate these values somehow ??? */
3173 r600_store_context_reg_seq(cb, R_028A54_GS_PER_ES, 3);
3174 r600_store_value(cb, 0x80); /* GS_PER_ES */
3175 r600_store_value(cb, 0x100); /* ES_PER_GS */
3176 r600_store_value(cb, 0x2); /* GS_PER_VS */
3177
3178 r600_store_context_reg(cb, R_028878_SQ_PGM_RESOURCES_GS,
3179 S_028878_NUM_GPRS(rshader->bc.ngpr) |
3180 S_028878_STACK_SIZE(rshader->bc.nstack));
3181 r600_store_context_reg(cb, R_028874_SQ_PGM_START_GS,
3182 shader->bo->gpu_address >> 8);
3183 /* After that, the NOP relocation packet must be emitted (shader->bo, RADEON_USAGE_READ). */
3184 }
3185
3186
3187 void evergreen_update_vs_state(struct pipe_context *ctx, struct r600_pipe_shader *shader)
3188 {
3189 struct r600_command_buffer *cb = &shader->command_buffer;
3190 struct r600_shader *rshader = &shader->shader;
3191 unsigned spi_vs_out_id[10] = {};
3192 unsigned i, tmp, nparams = 0;
3193
3194 for (i = 0; i < rshader->noutput; i++) {
3195 if (rshader->output[i].spi_sid) {
3196 tmp = rshader->output[i].spi_sid << ((nparams & 3) * 8);
3197 spi_vs_out_id[nparams / 4] |= tmp;
3198 nparams++;
3199 }
3200 }
3201
3202 r600_init_command_buffer(cb, 32);
3203
3204 r600_store_context_reg_seq(cb, R_02861C_SPI_VS_OUT_ID_0, 10);
3205 for (i = 0; i < 10; i++) {
3206 r600_store_value(cb, spi_vs_out_id[i]);
3207 }
3208
3209 /* Certain attributes (position, psize, etc.) don't count as params.
3210 * VS is required to export at least one param and r600_shader_from_tgsi()
3211 * takes care of adding a dummy export.
3212 */
3213 if (nparams < 1)
3214 nparams = 1;
3215
3216 r600_store_context_reg(cb, R_0286C4_SPI_VS_OUT_CONFIG,
3217 S_0286C4_VS_EXPORT_COUNT(nparams - 1));
3218 r600_store_context_reg(cb, R_028860_SQ_PGM_RESOURCES_VS,
3219 S_028860_NUM_GPRS(rshader->bc.ngpr) |
3220 S_028860_STACK_SIZE(rshader->bc.nstack));
3221 if (rshader->vs_position_window_space) {
3222 r600_store_context_reg(cb, R_028818_PA_CL_VTE_CNTL,
3223 S_028818_VTX_XY_FMT(1) | S_028818_VTX_Z_FMT(1));
3224 } else {
3225 r600_store_context_reg(cb, R_028818_PA_CL_VTE_CNTL,
3226 S_028818_VTX_W0_FMT(1) |
3227 S_028818_VPORT_X_SCALE_ENA(1) | S_028818_VPORT_X_OFFSET_ENA(1) |
3228 S_028818_VPORT_Y_SCALE_ENA(1) | S_028818_VPORT_Y_OFFSET_ENA(1) |
3229 S_028818_VPORT_Z_SCALE_ENA(1) | S_028818_VPORT_Z_OFFSET_ENA(1));
3230
3231 }
3232 r600_store_context_reg(cb, R_02885C_SQ_PGM_START_VS,
3233 shader->bo->gpu_address >> 8);
3234 /* After that, the NOP relocation packet must be emitted (shader->bo, RADEON_USAGE_READ). */
3235
3236 shader->pa_cl_vs_out_cntl =
3237 S_02881C_VS_OUT_CCDIST0_VEC_ENA((rshader->clip_dist_write & 0x0F) != 0) |
3238 S_02881C_VS_OUT_CCDIST1_VEC_ENA((rshader->clip_dist_write & 0xF0) != 0) |
3239 S_02881C_VS_OUT_MISC_VEC_ENA(rshader->vs_out_misc_write) |
3240 S_02881C_USE_VTX_POINT_SIZE(rshader->vs_out_point_size) |
3241 S_02881C_USE_VTX_EDGE_FLAG(rshader->vs_out_edgeflag) |
3242 S_02881C_USE_VTX_VIEWPORT_INDX(rshader->vs_out_viewport) |
3243 S_02881C_USE_VTX_RENDER_TARGET_INDX(rshader->vs_out_layer);
3244 }
3245
3246 void evergreen_update_hs_state(struct pipe_context *ctx, struct r600_pipe_shader *shader)
3247 {
3248 struct r600_command_buffer *cb = &shader->command_buffer;
3249 struct r600_shader *rshader = &shader->shader;
3250
3251 r600_init_command_buffer(cb, 32);
3252 r600_store_context_reg(cb, R_0288BC_SQ_PGM_RESOURCES_HS,
3253 S_0288BC_NUM_GPRS(rshader->bc.ngpr) |
3254 S_0288BC_STACK_SIZE(rshader->bc.nstack));
3255 r600_store_context_reg(cb, R_0288B8_SQ_PGM_START_HS,
3256 shader->bo->gpu_address >> 8);
3257 }
3258
3259 void evergreen_update_ls_state(struct pipe_context *ctx, struct r600_pipe_shader *shader)
3260 {
3261 struct r600_command_buffer *cb = &shader->command_buffer;
3262 struct r600_shader *rshader = &shader->shader;
3263
3264 r600_init_command_buffer(cb, 32);
3265 r600_store_context_reg(cb, R_0288D4_SQ_PGM_RESOURCES_LS,
3266 S_0288D4_NUM_GPRS(rshader->bc.ngpr) |
3267 S_0288D4_STACK_SIZE(rshader->bc.nstack));
3268 r600_store_context_reg(cb, R_0288D0_SQ_PGM_START_LS,
3269 shader->bo->gpu_address >> 8);
3270 }
3271 void *evergreen_create_resolve_blend(struct r600_context *rctx)
3272 {
3273 struct pipe_blend_state blend;
3274
3275 memset(&blend, 0, sizeof(blend));
3276 blend.independent_blend_enable = true;
3277 blend.rt[0].colormask = 0xf;
3278 return evergreen_create_blend_state_mode(&rctx->b.b, &blend, V_028808_CB_RESOLVE);
3279 }
3280
3281 void *evergreen_create_decompress_blend(struct r600_context *rctx)
3282 {
3283 struct pipe_blend_state blend;
3284 unsigned mode = rctx->screen->has_compressed_msaa_texturing ?
3285 V_028808_CB_FMASK_DECOMPRESS : V_028808_CB_DECOMPRESS;
3286
3287 memset(&blend, 0, sizeof(blend));
3288 blend.independent_blend_enable = true;
3289 blend.rt[0].colormask = 0xf;
3290 return evergreen_create_blend_state_mode(&rctx->b.b, &blend, mode);
3291 }
3292
3293 void *evergreen_create_fastclear_blend(struct r600_context *rctx)
3294 {
3295 struct pipe_blend_state blend;
3296 unsigned mode = V_028808_CB_ELIMINATE_FAST_CLEAR;
3297
3298 memset(&blend, 0, sizeof(blend));
3299 blend.independent_blend_enable = true;
3300 blend.rt[0].colormask = 0xf;
3301 return evergreen_create_blend_state_mode(&rctx->b.b, &blend, mode);
3302 }
3303
3304 void *evergreen_create_db_flush_dsa(struct r600_context *rctx)
3305 {
3306 struct pipe_depth_stencil_alpha_state dsa = {{0}};
3307
3308 return rctx->b.b.create_depth_stencil_alpha_state(&rctx->b.b, &dsa);
3309 }
3310
3311 void evergreen_update_db_shader_control(struct r600_context * rctx)
3312 {
3313 bool dual_export;
3314 unsigned db_shader_control;
3315
3316 if (!rctx->ps_shader) {
3317 return;
3318 }
3319
3320 dual_export = rctx->framebuffer.export_16bpc &&
3321 !rctx->ps_shader->current->ps_depth_export;
3322
3323 db_shader_control = rctx->ps_shader->current->db_shader_control |
3324 S_02880C_DUAL_EXPORT_ENABLE(dual_export) |
3325 S_02880C_DB_SOURCE_FORMAT(dual_export ? V_02880C_EXPORT_DB_TWO :
3326 V_02880C_EXPORT_DB_FULL) |
3327 S_02880C_ALPHA_TO_MASK_DISABLE(rctx->framebuffer.cb0_is_integer);
3328
3329 /* When alpha test is enabled we can't trust the hw to make the proper
3330 * decision on the order in which ztest should be run related to fragment
3331 * shader execution.
3332 *
3333 * If alpha test is enabled perform early z rejection (RE_Z) but don't early
3334 * write to the zbuffer. Write to zbuffer is delayed after fragment shader
3335 * execution and thus after alpha test so if discarded by the alpha test
3336 * the z value is not written.
3337 * If ReZ is enabled, and the zfunc/zenable/zwrite values change you can
3338 * get a hang unless you flush the DB in between. For now just use
3339 * LATE_Z.
3340 */
3341 if (rctx->alphatest_state.sx_alpha_test_control) {
3342 db_shader_control |= S_02880C_Z_ORDER(V_02880C_LATE_Z);
3343 } else {
3344 db_shader_control |= S_02880C_Z_ORDER(V_02880C_EARLY_Z_THEN_LATE_Z);
3345 }
3346
3347 if (db_shader_control != rctx->db_misc_state.db_shader_control) {
3348 rctx->db_misc_state.db_shader_control = db_shader_control;
3349 r600_mark_atom_dirty(rctx, &rctx->db_misc_state.atom);
3350 }
3351 }
3352
3353 static void evergreen_dma_copy_tile(struct r600_context *rctx,
3354 struct pipe_resource *dst,
3355 unsigned dst_level,
3356 unsigned dst_x,
3357 unsigned dst_y,
3358 unsigned dst_z,
3359 struct pipe_resource *src,
3360 unsigned src_level,
3361 unsigned src_x,
3362 unsigned src_y,
3363 unsigned src_z,
3364 unsigned copy_height,
3365 unsigned pitch,
3366 unsigned bpp)
3367 {
3368 struct radeon_winsys_cs *cs = rctx->b.dma.cs;
3369 struct r600_texture *rsrc = (struct r600_texture*)src;
3370 struct r600_texture *rdst = (struct r600_texture*)dst;
3371 unsigned array_mode, lbpp, pitch_tile_max, slice_tile_max, size;
3372 unsigned ncopy, height, cheight, detile, i, x, y, z, src_mode, dst_mode;
3373 unsigned sub_cmd, bank_h, bank_w, mt_aspect, nbanks, tile_split, non_disp_tiling = 0;
3374 uint64_t base, addr;
3375
3376 dst_mode = rdst->surface.level[dst_level].mode;
3377 src_mode = rsrc->surface.level[src_level].mode;
3378 assert(dst_mode != src_mode);
3379
3380 /* non_disp_tiling bit needs to be set for depth, stencil, and fmask surfaces */
3381 if (util_format_has_depth(util_format_description(src->format)))
3382 non_disp_tiling = 1;
3383
3384 y = 0;
3385 sub_cmd = EG_DMA_COPY_TILED;
3386 lbpp = util_logbase2(bpp);
3387 pitch_tile_max = ((pitch / bpp) / 8) - 1;
3388 nbanks = eg_num_banks(rctx->screen->b.info.r600_num_banks);
3389
3390 if (dst_mode == RADEON_SURF_MODE_LINEAR_ALIGNED) {
3391 /* T2L */
3392 array_mode = evergreen_array_mode(src_mode);
3393 slice_tile_max = (rsrc->surface.level[src_level].nblk_x * rsrc->surface.level[src_level].nblk_y) / (8*8);
3394 slice_tile_max = slice_tile_max ? slice_tile_max - 1 : 0;
3395 /* linear height must be the same as the slice tile max height, it's ok even
3396 * if the linear destination/source have smaller heigh as the size of the
3397 * dma packet will be using the copy_height which is always smaller or equal
3398 * to the linear height
3399 */
3400 height = rsrc->surface.level[src_level].npix_y;
3401 detile = 1;
3402 x = src_x;
3403 y = src_y;
3404 z = src_z;
3405 base = rsrc->surface.level[src_level].offset;
3406 addr = rdst->surface.level[dst_level].offset;
3407 addr += rdst->surface.level[dst_level].slice_size * dst_z;
3408 addr += dst_y * pitch + dst_x * bpp;
3409 bank_h = eg_bank_wh(rsrc->surface.bankh);
3410 bank_w = eg_bank_wh(rsrc->surface.bankw);
3411 mt_aspect = eg_macro_tile_aspect(rsrc->surface.mtilea);
3412 tile_split = eg_tile_split(rsrc->surface.tile_split);
3413 base += rsrc->resource.gpu_address;
3414 addr += rdst->resource.gpu_address;
3415 } else {
3416 /* L2T */
3417 array_mode = evergreen_array_mode(dst_mode);
3418 slice_tile_max = (rdst->surface.level[dst_level].nblk_x * rdst->surface.level[dst_level].nblk_y) / (8*8);
3419 slice_tile_max = slice_tile_max ? slice_tile_max - 1 : 0;
3420 /* linear height must be the same as the slice tile max height, it's ok even
3421 * if the linear destination/source have smaller heigh as the size of the
3422 * dma packet will be using the copy_height which is always smaller or equal
3423 * to the linear height
3424 */
3425 height = rdst->surface.level[dst_level].npix_y;
3426 detile = 0;
3427 x = dst_x;
3428 y = dst_y;
3429 z = dst_z;
3430 base = rdst->surface.level[dst_level].offset;
3431 addr = rsrc->surface.level[src_level].offset;
3432 addr += rsrc->surface.level[src_level].slice_size * src_z;
3433 addr += src_y * pitch + src_x * bpp;
3434 bank_h = eg_bank_wh(rdst->surface.bankh);
3435 bank_w = eg_bank_wh(rdst->surface.bankw);
3436 mt_aspect = eg_macro_tile_aspect(rdst->surface.mtilea);
3437 tile_split = eg_tile_split(rdst->surface.tile_split);
3438 base += rdst->resource.gpu_address;
3439 addr += rsrc->resource.gpu_address;
3440 }
3441
3442 size = (copy_height * pitch) / 4;
3443 ncopy = (size / EG_DMA_COPY_MAX_SIZE) + !!(size % EG_DMA_COPY_MAX_SIZE);
3444 r600_need_dma_space(&rctx->b, ncopy * 9, &rdst->resource, &rsrc->resource);
3445
3446 for (i = 0; i < ncopy; i++) {
3447 cheight = copy_height;
3448 if (((cheight * pitch) / 4) > EG_DMA_COPY_MAX_SIZE) {
3449 cheight = (EG_DMA_COPY_MAX_SIZE * 4) / pitch;
3450 }
3451 size = (cheight * pitch) / 4;
3452 /* emit reloc before writing cs so that cs is always in consistent state */
3453 radeon_add_to_buffer_list(&rctx->b, &rctx->b.dma, &rsrc->resource,
3454 RADEON_USAGE_READ, RADEON_PRIO_SDMA_TEXTURE);
3455 radeon_add_to_buffer_list(&rctx->b, &rctx->b.dma, &rdst->resource,
3456 RADEON_USAGE_WRITE, RADEON_PRIO_SDMA_TEXTURE);
3457 radeon_emit(cs, DMA_PACKET(DMA_PACKET_COPY, sub_cmd, size));
3458 radeon_emit(cs, base >> 8);
3459 radeon_emit(cs, (detile << 31) | (array_mode << 27) |
3460 (lbpp << 24) | (bank_h << 21) |
3461 (bank_w << 18) | (mt_aspect << 16));
3462 radeon_emit(cs, (pitch_tile_max << 0) | ((height - 1) << 16));
3463 radeon_emit(cs, (slice_tile_max << 0));
3464 radeon_emit(cs, (x << 0) | (z << 18));
3465 radeon_emit(cs, (y << 0) | (tile_split << 21) | (nbanks << 25) | (non_disp_tiling << 28));
3466 radeon_emit(cs, addr & 0xfffffffc);
3467 radeon_emit(cs, (addr >> 32UL) & 0xff);
3468 copy_height -= cheight;
3469 addr += cheight * pitch;
3470 y += cheight;
3471 }
3472 r600_dma_emit_wait_idle(&rctx->b);
3473 }
3474
3475 static void evergreen_dma_copy(struct pipe_context *ctx,
3476 struct pipe_resource *dst,
3477 unsigned dst_level,
3478 unsigned dstx, unsigned dsty, unsigned dstz,
3479 struct pipe_resource *src,
3480 unsigned src_level,
3481 const struct pipe_box *src_box)
3482 {
3483 struct r600_context *rctx = (struct r600_context *)ctx;
3484 struct r600_texture *rsrc = (struct r600_texture*)src;
3485 struct r600_texture *rdst = (struct r600_texture*)dst;
3486 unsigned dst_pitch, src_pitch, bpp, dst_mode, src_mode, copy_height;
3487 unsigned src_w, dst_w;
3488 unsigned src_x, src_y;
3489 unsigned dst_x = dstx, dst_y = dsty, dst_z = dstz;
3490
3491 if (rctx->b.dma.cs == NULL) {
3492 goto fallback;
3493 }
3494
3495 if (dst->target == PIPE_BUFFER && src->target == PIPE_BUFFER) {
3496 evergreen_dma_copy_buffer(rctx, dst, src, dst_x, src_box->x, src_box->width);
3497 return;
3498 }
3499
3500 if (src_box->depth > 1 ||
3501 !r600_prepare_for_dma_blit(&rctx->b, rdst, dst_level, dstx, dsty,
3502 dstz, rsrc, src_level, src_box))
3503 goto fallback;
3504
3505 src_x = util_format_get_nblocksx(src->format, src_box->x);
3506 dst_x = util_format_get_nblocksx(src->format, dst_x);
3507 src_y = util_format_get_nblocksy(src->format, src_box->y);
3508 dst_y = util_format_get_nblocksy(src->format, dst_y);
3509
3510 bpp = rdst->surface.bpe;
3511 dst_pitch = rdst->surface.level[dst_level].pitch_bytes;
3512 src_pitch = rsrc->surface.level[src_level].pitch_bytes;
3513 src_w = rsrc->surface.level[src_level].npix_x;
3514 dst_w = rdst->surface.level[dst_level].npix_x;
3515 copy_height = src_box->height / rsrc->surface.blk_h;
3516
3517 dst_mode = rdst->surface.level[dst_level].mode;
3518 src_mode = rsrc->surface.level[src_level].mode;
3519
3520 if (src_pitch != dst_pitch || src_box->x || dst_x || src_w != dst_w) {
3521 /* FIXME evergreen can do partial blit */
3522 goto fallback;
3523 }
3524 /* the x test here are currently useless (because we don't support partial blit)
3525 * but keep them around so we don't forget about those
3526 */
3527 if (src_pitch % 8 || src_box->x % 8 || dst_x % 8 || src_box->y % 8 || dst_y % 8) {
3528 goto fallback;
3529 }
3530
3531 /* 128 bpp surfaces require non_disp_tiling for both
3532 * tiled and linear buffers on cayman. However, async
3533 * DMA only supports it on the tiled side. As such
3534 * the tile order is backwards after a L2T/T2L packet.
3535 */
3536 if ((rctx->b.chip_class == CAYMAN) &&
3537 (src_mode != dst_mode) &&
3538 (util_format_get_blocksize(src->format) >= 16)) {
3539 goto fallback;
3540 }
3541
3542 if (src_mode == dst_mode) {
3543 uint64_t dst_offset, src_offset;
3544 /* simple dma blit would do NOTE code here assume :
3545 * src_box.x/y == 0
3546 * dst_x/y == 0
3547 * dst_pitch == src_pitch
3548 */
3549 src_offset= rsrc->surface.level[src_level].offset;
3550 src_offset += rsrc->surface.level[src_level].slice_size * src_box->z;
3551 src_offset += src_y * src_pitch + src_x * bpp;
3552 dst_offset = rdst->surface.level[dst_level].offset;
3553 dst_offset += rdst->surface.level[dst_level].slice_size * dst_z;
3554 dst_offset += dst_y * dst_pitch + dst_x * bpp;
3555 evergreen_dma_copy_buffer(rctx, dst, src, dst_offset, src_offset,
3556 src_box->height * src_pitch);
3557 } else {
3558 evergreen_dma_copy_tile(rctx, dst, dst_level, dst_x, dst_y, dst_z,
3559 src, src_level, src_x, src_y, src_box->z,
3560 copy_height, dst_pitch, bpp);
3561 }
3562 return;
3563
3564 fallback:
3565 r600_resource_copy_region(ctx, dst, dst_level, dstx, dsty, dstz,
3566 src, src_level, src_box);
3567 }
3568
3569 static void evergreen_set_tess_state(struct pipe_context *ctx,
3570 const float default_outer_level[4],
3571 const float default_inner_level[2])
3572 {
3573 struct r600_context *rctx = (struct r600_context *)ctx;
3574
3575 memcpy(rctx->tess_state, default_outer_level, sizeof(float) * 4);
3576 memcpy(rctx->tess_state+4, default_inner_level, sizeof(float) * 2);
3577 rctx->tess_state_dirty = true;
3578 }
3579
3580 void evergreen_init_state_functions(struct r600_context *rctx)
3581 {
3582 unsigned id = 1;
3583 unsigned i;
3584 /* !!!
3585 * To avoid GPU lockup registers must be emitted in a specific order
3586 * (no kidding ...). The order below is important and have been
3587 * partially inferred from analyzing fglrx command stream.
3588 *
3589 * Don't reorder atom without carefully checking the effect (GPU lockup
3590 * or piglit regression).
3591 * !!!
3592 */
3593 if (rctx->b.chip_class == EVERGREEN) {
3594 r600_init_atom(rctx, &rctx->config_state.atom, id++, evergreen_emit_config_state, 11);
3595 rctx->config_state.dyn_gpr_enabled = true;
3596 }
3597 r600_init_atom(rctx, &rctx->framebuffer.atom, id++, evergreen_emit_framebuffer_state, 0);
3598 /* shader const */
3599 r600_init_atom(rctx, &rctx->constbuf_state[PIPE_SHADER_VERTEX].atom, id++, evergreen_emit_vs_constant_buffers, 0);
3600 r600_init_atom(rctx, &rctx->constbuf_state[PIPE_SHADER_GEOMETRY].atom, id++, evergreen_emit_gs_constant_buffers, 0);
3601 r600_init_atom(rctx, &rctx->constbuf_state[PIPE_SHADER_FRAGMENT].atom, id++, evergreen_emit_ps_constant_buffers, 0);
3602 r600_init_atom(rctx, &rctx->constbuf_state[PIPE_SHADER_TESS_CTRL].atom, id++, evergreen_emit_tcs_constant_buffers, 0);
3603 r600_init_atom(rctx, &rctx->constbuf_state[PIPE_SHADER_TESS_EVAL].atom, id++, evergreen_emit_tes_constant_buffers, 0);
3604 r600_init_atom(rctx, &rctx->constbuf_state[PIPE_SHADER_COMPUTE].atom, id++, evergreen_emit_cs_constant_buffers, 0);
3605 /* shader program */
3606 r600_init_atom(rctx, &rctx->cs_shader_state.atom, id++, evergreen_emit_cs_shader, 0);
3607 /* sampler */
3608 r600_init_atom(rctx, &rctx->samplers[PIPE_SHADER_VERTEX].states.atom, id++, evergreen_emit_vs_sampler_states, 0);
3609 r600_init_atom(rctx, &rctx->samplers[PIPE_SHADER_GEOMETRY].states.atom, id++, evergreen_emit_gs_sampler_states, 0);
3610 r600_init_atom(rctx, &rctx->samplers[PIPE_SHADER_TESS_CTRL].states.atom, id++, evergreen_emit_tcs_sampler_states, 0);
3611 r600_init_atom(rctx, &rctx->samplers[PIPE_SHADER_TESS_EVAL].states.atom, id++, evergreen_emit_tes_sampler_states, 0);
3612 r600_init_atom(rctx, &rctx->samplers[PIPE_SHADER_FRAGMENT].states.atom, id++, evergreen_emit_ps_sampler_states, 0);
3613 r600_init_atom(rctx, &rctx->samplers[PIPE_SHADER_COMPUTE].states.atom, id++, evergreen_emit_cs_sampler_states, 0);
3614 /* resources */
3615 r600_init_atom(rctx, &rctx->vertex_buffer_state.atom, id++, evergreen_fs_emit_vertex_buffers, 0);
3616 r600_init_atom(rctx, &rctx->cs_vertex_buffer_state.atom, id++, evergreen_cs_emit_vertex_buffers, 0);
3617 r600_init_atom(rctx, &rctx->samplers[PIPE_SHADER_VERTEX].views.atom, id++, evergreen_emit_vs_sampler_views, 0);
3618 r600_init_atom(rctx, &rctx->samplers[PIPE_SHADER_GEOMETRY].views.atom, id++, evergreen_emit_gs_sampler_views, 0);
3619 r600_init_atom(rctx, &rctx->samplers[PIPE_SHADER_TESS_CTRL].views.atom, id++, evergreen_emit_tcs_sampler_views, 0);
3620 r600_init_atom(rctx, &rctx->samplers[PIPE_SHADER_TESS_EVAL].views.atom, id++, evergreen_emit_tes_sampler_views, 0);
3621 r600_init_atom(rctx, &rctx->samplers[PIPE_SHADER_FRAGMENT].views.atom, id++, evergreen_emit_ps_sampler_views, 0);
3622 r600_init_atom(rctx, &rctx->samplers[PIPE_SHADER_COMPUTE].views.atom, id++, evergreen_emit_cs_sampler_views, 0);
3623
3624 r600_init_atom(rctx, &rctx->vgt_state.atom, id++, r600_emit_vgt_state, 10);
3625
3626 if (rctx->b.chip_class == EVERGREEN) {
3627 r600_init_atom(rctx, &rctx->sample_mask.atom, id++, evergreen_emit_sample_mask, 3);
3628 } else {
3629 r600_init_atom(rctx, &rctx->sample_mask.atom, id++, cayman_emit_sample_mask, 4);
3630 }
3631 rctx->sample_mask.sample_mask = ~0;
3632
3633 r600_init_atom(rctx, &rctx->alphatest_state.atom, id++, r600_emit_alphatest_state, 6);
3634 r600_init_atom(rctx, &rctx->blend_color.atom, id++, r600_emit_blend_color, 6);
3635 r600_init_atom(rctx, &rctx->blend_state.atom, id++, r600_emit_cso_state, 0);
3636 r600_init_atom(rctx, &rctx->cb_misc_state.atom, id++, evergreen_emit_cb_misc_state, 4);
3637 r600_init_atom(rctx, &rctx->clip_misc_state.atom, id++, r600_emit_clip_misc_state, 9);
3638 r600_init_atom(rctx, &rctx->clip_state.atom, id++, evergreen_emit_clip_state, 26);
3639 r600_init_atom(rctx, &rctx->db_misc_state.atom, id++, evergreen_emit_db_misc_state, 10);
3640 r600_init_atom(rctx, &rctx->db_state.atom, id++, evergreen_emit_db_state, 14);
3641 r600_init_atom(rctx, &rctx->dsa_state.atom, id++, r600_emit_cso_state, 0);
3642 r600_init_atom(rctx, &rctx->poly_offset_state.atom, id++, evergreen_emit_polygon_offset, 9);
3643 r600_init_atom(rctx, &rctx->rasterizer_state.atom, id++, r600_emit_cso_state, 0);
3644 r600_add_atom(rctx, &rctx->b.scissors.atom, id++);
3645 r600_add_atom(rctx, &rctx->b.viewports.atom, id++);
3646 r600_init_atom(rctx, &rctx->stencil_ref.atom, id++, r600_emit_stencil_ref, 4);
3647 r600_init_atom(rctx, &rctx->vertex_fetch_shader.atom, id++, evergreen_emit_vertex_fetch_shader, 5);
3648 r600_add_atom(rctx, &rctx->b.render_cond_atom, id++);
3649 r600_add_atom(rctx, &rctx->b.streamout.begin_atom, id++);
3650 r600_add_atom(rctx, &rctx->b.streamout.enable_atom, id++);
3651 for (i = 0; i < EG_NUM_HW_STAGES; i++)
3652 r600_init_atom(rctx, &rctx->hw_shader_stages[i].atom, id++, r600_emit_shader, 0);
3653 r600_init_atom(rctx, &rctx->shader_stages.atom, id++, evergreen_emit_shader_stages, 15);
3654 r600_init_atom(rctx, &rctx->gs_rings.atom, id++, evergreen_emit_gs_rings, 26);
3655
3656 rctx->b.b.create_blend_state = evergreen_create_blend_state;
3657 rctx->b.b.create_depth_stencil_alpha_state = evergreen_create_dsa_state;
3658 rctx->b.b.create_rasterizer_state = evergreen_create_rs_state;
3659 rctx->b.b.create_sampler_state = evergreen_create_sampler_state;
3660 rctx->b.b.create_sampler_view = evergreen_create_sampler_view;
3661 rctx->b.b.set_framebuffer_state = evergreen_set_framebuffer_state;
3662 rctx->b.b.set_polygon_stipple = evergreen_set_polygon_stipple;
3663 rctx->b.b.set_min_samples = evergreen_set_min_samples;
3664 rctx->b.b.set_tess_state = evergreen_set_tess_state;
3665 if (rctx->b.chip_class == EVERGREEN)
3666 rctx->b.b.get_sample_position = evergreen_get_sample_position;
3667 else
3668 rctx->b.b.get_sample_position = cayman_get_sample_position;
3669 rctx->b.dma_copy = evergreen_dma_copy;
3670
3671 evergreen_init_compute_state_functions(rctx);
3672 }
3673
3674 /**
3675 * This calculates the LDS size for tessellation shaders (VS, TCS, TES).
3676 *
3677 * The information about LDS and other non-compile-time parameters is then
3678 * written to the const buffer.
3679
3680 * const buffer contains -
3681 * uint32_t input_patch_size
3682 * uint32_t input_vertex_size
3683 * uint32_t num_tcs_input_cp
3684 * uint32_t num_tcs_output_cp;
3685 * uint32_t output_patch_size
3686 * uint32_t output_vertex_size
3687 * uint32_t output_patch0_offset
3688 * uint32_t perpatch_output_offset
3689 * and the same constbuf is bound to LS/HS/VS(ES).
3690 */
3691 void evergreen_setup_tess_constants(struct r600_context *rctx, const struct pipe_draw_info *info, unsigned *num_patches)
3692 {
3693 struct pipe_constant_buffer constbuf = {0};
3694 struct r600_pipe_shader_selector *tcs = rctx->tcs_shader ? rctx->tcs_shader : rctx->tes_shader;
3695 struct r600_pipe_shader_selector *ls = rctx->vs_shader;
3696 unsigned num_tcs_input_cp = info->vertices_per_patch;
3697 unsigned num_tcs_outputs;
3698 unsigned num_tcs_output_cp;
3699 unsigned num_tcs_patch_outputs;
3700 unsigned num_tcs_inputs;
3701 unsigned input_vertex_size, output_vertex_size;
3702 unsigned input_patch_size, pervertex_output_patch_size, output_patch_size;
3703 unsigned output_patch0_offset, perpatch_output_offset, lds_size;
3704 uint32_t values[16];
3705 unsigned num_waves;
3706 unsigned num_pipes = rctx->screen->b.info.r600_max_quad_pipes;
3707 unsigned wave_divisor = (16 * num_pipes);
3708
3709 *num_patches = 1;
3710
3711 if (!rctx->tes_shader) {
3712 rctx->lds_alloc = 0;
3713 rctx->b.b.set_constant_buffer(&rctx->b.b, PIPE_SHADER_VERTEX,
3714 R600_LDS_INFO_CONST_BUFFER, NULL);
3715 rctx->b.b.set_constant_buffer(&rctx->b.b, PIPE_SHADER_TESS_CTRL,
3716 R600_LDS_INFO_CONST_BUFFER, NULL);
3717 rctx->b.b.set_constant_buffer(&rctx->b.b, PIPE_SHADER_TESS_EVAL,
3718 R600_LDS_INFO_CONST_BUFFER, NULL);
3719 return;
3720 }
3721
3722 if (rctx->lds_alloc != 0 &&
3723 rctx->last_ls == ls &&
3724 !rctx->tess_state_dirty &&
3725 rctx->last_num_tcs_input_cp == num_tcs_input_cp &&
3726 rctx->last_tcs == tcs)
3727 return;
3728
3729 num_tcs_inputs = util_last_bit64(ls->lds_outputs_written_mask);
3730
3731 if (rctx->tcs_shader) {
3732 num_tcs_outputs = util_last_bit64(tcs->lds_outputs_written_mask);
3733 num_tcs_output_cp = tcs->info.properties[TGSI_PROPERTY_TCS_VERTICES_OUT];
3734 num_tcs_patch_outputs = util_last_bit64(tcs->lds_patch_outputs_written_mask);
3735 } else {
3736 num_tcs_outputs = num_tcs_inputs;
3737 num_tcs_output_cp = num_tcs_input_cp;
3738 num_tcs_patch_outputs = 2; /* TESSINNER + TESSOUTER */
3739 }
3740
3741 /* size in bytes */
3742 input_vertex_size = num_tcs_inputs * 16;
3743 output_vertex_size = num_tcs_outputs * 16;
3744
3745 input_patch_size = num_tcs_input_cp * input_vertex_size;
3746
3747 pervertex_output_patch_size = num_tcs_output_cp * output_vertex_size;
3748 output_patch_size = pervertex_output_patch_size + num_tcs_patch_outputs * 16;
3749
3750 output_patch0_offset = rctx->tcs_shader ? input_patch_size * *num_patches : 0;
3751 perpatch_output_offset = output_patch0_offset + pervertex_output_patch_size;
3752
3753 lds_size = output_patch0_offset + output_patch_size * *num_patches;
3754
3755 values[0] = input_patch_size;
3756 values[1] = input_vertex_size;
3757 values[2] = num_tcs_input_cp;
3758 values[3] = num_tcs_output_cp;
3759
3760 values[4] = output_patch_size;
3761 values[5] = output_vertex_size;
3762 values[6] = output_patch0_offset;
3763 values[7] = perpatch_output_offset;
3764
3765 /* docs say HS_NUM_WAVES - CEIL((LS_HS_CONFIG.NUM_PATCHES *
3766 LS_HS_CONFIG.HS_NUM_OUTPUT_CP) / (NUM_GOOD_PIPES * 16)) */
3767 num_waves = ceilf((float)(*num_patches * num_tcs_output_cp) / (float)wave_divisor);
3768
3769 rctx->lds_alloc = (lds_size | (num_waves << 14));
3770
3771 memcpy(&values[8], rctx->tess_state, 6 * sizeof(float));
3772 values[14] = 0;
3773 values[15] = 0;
3774
3775 rctx->tess_state_dirty = false;
3776 rctx->last_ls = ls;
3777 rctx->last_tcs = tcs;
3778 rctx->last_num_tcs_input_cp = num_tcs_input_cp;
3779
3780 constbuf.user_buffer = values;
3781 constbuf.buffer_size = 16 * 4;
3782
3783 rctx->b.b.set_constant_buffer(&rctx->b.b, PIPE_SHADER_VERTEX,
3784 R600_LDS_INFO_CONST_BUFFER, &constbuf);
3785 rctx->b.b.set_constant_buffer(&rctx->b.b, PIPE_SHADER_TESS_CTRL,
3786 R600_LDS_INFO_CONST_BUFFER, &constbuf);
3787 rctx->b.b.set_constant_buffer(&rctx->b.b, PIPE_SHADER_TESS_EVAL,
3788 R600_LDS_INFO_CONST_BUFFER, &constbuf);
3789 pipe_resource_reference(&constbuf.buffer, NULL);
3790 }
3791
3792 uint32_t evergreen_get_ls_hs_config(struct r600_context *rctx,
3793 const struct pipe_draw_info *info,
3794 unsigned num_patches)
3795 {
3796 unsigned num_output_cp;
3797
3798 if (!rctx->tes_shader)
3799 return 0;
3800
3801 num_output_cp = rctx->tcs_shader ?
3802 rctx->tcs_shader->info.properties[TGSI_PROPERTY_TCS_VERTICES_OUT] :
3803 info->vertices_per_patch;
3804
3805 return S_028B58_NUM_PATCHES(num_patches) |
3806 S_028B58_HS_NUM_INPUT_CP(info->vertices_per_patch) |
3807 S_028B58_HS_NUM_OUTPUT_CP(num_output_cp);
3808 }
3809
3810 void evergreen_set_ls_hs_config(struct r600_context *rctx,
3811 struct radeon_winsys_cs *cs,
3812 uint32_t ls_hs_config)
3813 {
3814 radeon_set_context_reg(cs, R_028B58_VGT_LS_HS_CONFIG, ls_hs_config);
3815 }
3816
3817 void evergreen_set_lds_alloc(struct r600_context *rctx,
3818 struct radeon_winsys_cs *cs,
3819 uint32_t lds_alloc)
3820 {
3821 radeon_set_context_reg(cs, R_0288E8_SQ_LDS_ALLOC, lds_alloc);
3822 }
3823
3824 /* on evergreen if you are running tessellation you need to disable dynamic
3825 GPRs to workaround a hardware bug.*/
3826 bool evergreen_adjust_gprs(struct r600_context *rctx)
3827 {
3828 unsigned num_gprs[EG_NUM_HW_STAGES];
3829 unsigned def_gprs[EG_NUM_HW_STAGES];
3830 unsigned cur_gprs[EG_NUM_HW_STAGES];
3831 unsigned new_gprs[EG_NUM_HW_STAGES];
3832 unsigned def_num_clause_temp_gprs = rctx->r6xx_num_clause_temp_gprs;
3833 unsigned max_gprs;
3834 unsigned i;
3835 unsigned total_gprs;
3836 unsigned tmp[3];
3837 bool rework = false, set_default = false, set_dirty = false;
3838 max_gprs = 0;
3839 for (i = 0; i < EG_NUM_HW_STAGES; i++) {
3840 def_gprs[i] = rctx->default_gprs[i];
3841 max_gprs += def_gprs[i];
3842 }
3843 max_gprs += def_num_clause_temp_gprs * 2;
3844
3845 /* if we have no TESS and dyn gpr is enabled then do nothing. */
3846 if (!rctx->hw_shader_stages[EG_HW_STAGE_HS].shader) {
3847 if (rctx->config_state.dyn_gpr_enabled)
3848 return true;
3849
3850 /* transition back to dyn gpr enabled state */
3851 rctx->config_state.dyn_gpr_enabled = true;
3852 r600_mark_atom_dirty(rctx, &rctx->config_state.atom);
3853 rctx->b.flags |= R600_CONTEXT_WAIT_3D_IDLE;
3854 return true;
3855 }
3856
3857
3858 /* gather required shader gprs */
3859 for (i = 0; i < EG_NUM_HW_STAGES; i++) {
3860 if (rctx->hw_shader_stages[i].shader)
3861 num_gprs[i] = rctx->hw_shader_stages[i].shader->shader.bc.ngpr;
3862 else
3863 num_gprs[i] = 0;
3864 }
3865
3866 cur_gprs[R600_HW_STAGE_PS] = G_008C04_NUM_PS_GPRS(rctx->config_state.sq_gpr_resource_mgmt_1);
3867 cur_gprs[R600_HW_STAGE_VS] = G_008C04_NUM_VS_GPRS(rctx->config_state.sq_gpr_resource_mgmt_1);
3868 cur_gprs[R600_HW_STAGE_GS] = G_008C08_NUM_GS_GPRS(rctx->config_state.sq_gpr_resource_mgmt_2);
3869 cur_gprs[R600_HW_STAGE_ES] = G_008C08_NUM_ES_GPRS(rctx->config_state.sq_gpr_resource_mgmt_2);
3870 cur_gprs[EG_HW_STAGE_LS] = G_008C0C_NUM_LS_GPRS(rctx->config_state.sq_gpr_resource_mgmt_3);
3871 cur_gprs[EG_HW_STAGE_HS] = G_008C0C_NUM_HS_GPRS(rctx->config_state.sq_gpr_resource_mgmt_3);
3872
3873 total_gprs = 0;
3874 for (i = 0; i < EG_NUM_HW_STAGES; i++) {
3875 new_gprs[i] = num_gprs[i];
3876 total_gprs += num_gprs[i];
3877 }
3878
3879 if (total_gprs > (max_gprs - (2 * def_num_clause_temp_gprs)))
3880 return false;
3881
3882 for (i = 0; i < EG_NUM_HW_STAGES; i++) {
3883 if (new_gprs[i] > cur_gprs[i]) {
3884 rework = true;
3885 break;
3886 }
3887 }
3888
3889 if (rctx->config_state.dyn_gpr_enabled) {
3890 set_dirty = true;
3891 rctx->config_state.dyn_gpr_enabled = false;
3892 }
3893
3894 if (rework) {
3895 set_default = true;
3896 for (i = 0; i < EG_NUM_HW_STAGES; i++) {
3897 if (new_gprs[i] > def_gprs[i])
3898 set_default = false;
3899 }
3900
3901 if (set_default) {
3902 for (i = 0; i < EG_NUM_HW_STAGES; i++) {
3903 new_gprs[i] = def_gprs[i];
3904 }
3905 } else {
3906 unsigned ps_value = max_gprs;
3907
3908 ps_value -= (def_num_clause_temp_gprs * 2);
3909 for (i = R600_HW_STAGE_VS; i < EG_NUM_HW_STAGES; i++)
3910 ps_value -= new_gprs[i];
3911
3912 new_gprs[R600_HW_STAGE_PS] = ps_value;
3913 }
3914
3915 tmp[0] = S_008C04_NUM_PS_GPRS(new_gprs[R600_HW_STAGE_PS]) |
3916 S_008C04_NUM_VS_GPRS(new_gprs[R600_HW_STAGE_VS]) |
3917 S_008C04_NUM_CLAUSE_TEMP_GPRS(def_num_clause_temp_gprs);
3918
3919 tmp[1] = S_008C08_NUM_ES_GPRS(new_gprs[R600_HW_STAGE_ES]) |
3920 S_008C08_NUM_GS_GPRS(new_gprs[R600_HW_STAGE_GS]);
3921
3922 tmp[2] = S_008C0C_NUM_HS_GPRS(new_gprs[EG_HW_STAGE_HS]) |
3923 S_008C0C_NUM_LS_GPRS(new_gprs[EG_HW_STAGE_LS]);
3924
3925 if (rctx->config_state.sq_gpr_resource_mgmt_1 != tmp[0] ||
3926 rctx->config_state.sq_gpr_resource_mgmt_2 != tmp[1] ||
3927 rctx->config_state.sq_gpr_resource_mgmt_3 != tmp[2]) {
3928 rctx->config_state.sq_gpr_resource_mgmt_1 = tmp[0];
3929 rctx->config_state.sq_gpr_resource_mgmt_2 = tmp[1];
3930 rctx->config_state.sq_gpr_resource_mgmt_3 = tmp[2];
3931 set_dirty = true;
3932 }
3933 }
3934
3935
3936 if (set_dirty) {
3937 r600_mark_atom_dirty(rctx, &rctx->config_state.atom);
3938 rctx->b.flags |= R600_CONTEXT_WAIT_3D_IDLE;
3939 }
3940 return true;
3941 }