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r600g: remove bpt and start using pitch_in_bytes/pixels.
[mesa.git] / src / gallium / drivers / r600 / evergreen_state.c
1 /*
2 * Copyright 2010 Jerome Glisse <glisse@freedesktop.org>
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * on the rights to use, copy, modify, merge, publish, distribute, sub
8 * license, and/or sell copies of the Software, and to permit persons to whom
9 * the Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
13 * Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHOR(S) AND/OR THEIR SUPPLIERS BE LIABLE FOR ANY CLAIM,
19 * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
20 * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
21 * USE OR OTHER DEALINGS IN THE SOFTWARE.
22 */
23
24 /* TODO:
25 * - fix mask for depth control & cull for query
26 */
27 #include <stdio.h>
28 #include <errno.h>
29 #include <pipe/p_defines.h>
30 #include <pipe/p_state.h>
31 #include <pipe/p_context.h>
32 #include <tgsi/tgsi_scan.h>
33 #include <tgsi/tgsi_parse.h>
34 #include <tgsi/tgsi_util.h>
35 #include <util/u_blitter.h>
36 #include <util/u_double_list.h>
37 #include <util/u_transfer.h>
38 #include <util/u_surface.h>
39 #include <util/u_pack_color.h>
40 #include <util/u_memory.h>
41 #include <util/u_inlines.h>
42 #include <util/u_framebuffer.h>
43 #include <pipebuffer/pb_buffer.h>
44 #include "r600.h"
45 #include "evergreend.h"
46 #include "r600_resource.h"
47 #include "r600_shader.h"
48 #include "r600_pipe.h"
49 #include "eg_state_inlines.h"
50
51 static void evergreen_set_blend_color(struct pipe_context *ctx,
52 const struct pipe_blend_color *state)
53 {
54 struct r600_pipe_context *rctx = (struct r600_pipe_context *)ctx;
55 struct r600_pipe_state *rstate = CALLOC_STRUCT(r600_pipe_state);
56
57 if (rstate == NULL)
58 return;
59
60 rstate->id = R600_PIPE_STATE_BLEND_COLOR;
61 r600_pipe_state_add_reg(rstate, R_028414_CB_BLEND_RED, fui(state->color[0]), 0xFFFFFFFF, NULL);
62 r600_pipe_state_add_reg(rstate, R_028418_CB_BLEND_GREEN, fui(state->color[1]), 0xFFFFFFFF, NULL);
63 r600_pipe_state_add_reg(rstate, R_02841C_CB_BLEND_BLUE, fui(state->color[2]), 0xFFFFFFFF, NULL);
64 r600_pipe_state_add_reg(rstate, R_028420_CB_BLEND_ALPHA, fui(state->color[3]), 0xFFFFFFFF, NULL);
65
66 free(rctx->states[R600_PIPE_STATE_BLEND_COLOR]);
67 rctx->states[R600_PIPE_STATE_BLEND_COLOR] = rstate;
68 r600_context_pipe_state_set(&rctx->ctx, rstate);
69 }
70
71 static void *evergreen_create_blend_state(struct pipe_context *ctx,
72 const struct pipe_blend_state *state)
73 {
74 struct r600_pipe_blend *blend = CALLOC_STRUCT(r600_pipe_blend);
75 struct r600_pipe_state *rstate;
76 u32 color_control, target_mask;
77 /* FIXME there is more then 8 framebuffer */
78 unsigned blend_cntl[8];
79
80 if (blend == NULL) {
81 return NULL;
82 }
83 rstate = &blend->rstate;
84
85 rstate->id = R600_PIPE_STATE_BLEND;
86
87 target_mask = 0;
88 color_control = S_028808_MODE(1);
89 if (state->logicop_enable) {
90 color_control |= (state->logicop_func << 16) | (state->logicop_func << 20);
91 } else {
92 color_control |= (0xcc << 16);
93 }
94 /* we pretend 8 buffer are used, CB_SHADER_MASK will disable unused one */
95 if (state->independent_blend_enable) {
96 for (int i = 0; i < 8; i++) {
97 target_mask |= (state->rt[i].colormask << (4 * i));
98 }
99 } else {
100 for (int i = 0; i < 8; i++) {
101 target_mask |= (state->rt[0].colormask << (4 * i));
102 }
103 }
104 blend->cb_target_mask = target_mask;
105 r600_pipe_state_add_reg(rstate, R_028808_CB_COLOR_CONTROL,
106 color_control, 0xFFFFFFFF, NULL);
107 r600_pipe_state_add_reg(rstate, R_028C3C_PA_SC_AA_MASK, 0xFFFFFFFF, 0xFFFFFFFF, NULL);
108
109 for (int i = 0; i < 8; i++) {
110 unsigned eqRGB = state->rt[i].rgb_func;
111 unsigned srcRGB = state->rt[i].rgb_src_factor;
112 unsigned dstRGB = state->rt[i].rgb_dst_factor;
113 unsigned eqA = state->rt[i].alpha_func;
114 unsigned srcA = state->rt[i].alpha_src_factor;
115 unsigned dstA = state->rt[i].alpha_dst_factor;
116
117 blend_cntl[i] = 0;
118 if (!state->rt[i].blend_enable)
119 continue;
120
121 blend_cntl[i] |= S_028780_BLEND_CONTROL_ENABLE(1);
122 blend_cntl[i] |= S_028780_COLOR_COMB_FCN(r600_translate_blend_function(eqRGB));
123 blend_cntl[i] |= S_028780_COLOR_SRCBLEND(r600_translate_blend_factor(srcRGB));
124 blend_cntl[i] |= S_028780_COLOR_DESTBLEND(r600_translate_blend_factor(dstRGB));
125
126 if (srcA != srcRGB || dstA != dstRGB || eqA != eqRGB) {
127 blend_cntl[i] |= S_028780_SEPARATE_ALPHA_BLEND(1);
128 blend_cntl[i] |= S_028780_ALPHA_COMB_FCN(r600_translate_blend_function(eqA));
129 blend_cntl[i] |= S_028780_ALPHA_SRCBLEND(r600_translate_blend_factor(srcA));
130 blend_cntl[i] |= S_028780_ALPHA_DESTBLEND(r600_translate_blend_factor(dstA));
131 }
132 }
133 for (int i = 0; i < 8; i++) {
134 r600_pipe_state_add_reg(rstate, R_028780_CB_BLEND0_CONTROL + i * 4, blend_cntl[i], 0xFFFFFFFF, NULL);
135 }
136
137 return rstate;
138 }
139
140 static void evergreen_bind_blend_state(struct pipe_context *ctx, void *state)
141 {
142 struct r600_pipe_context *rctx = (struct r600_pipe_context *)ctx;
143 struct r600_pipe_blend *blend = (struct r600_pipe_blend *)state;
144 struct r600_pipe_state *rstate;
145
146 if (state == NULL)
147 return;
148 rstate = &blend->rstate;
149 rctx->states[rstate->id] = rstate;
150 rctx->cb_target_mask = blend->cb_target_mask;
151 r600_context_pipe_state_set(&rctx->ctx, rstate);
152 }
153
154 static void *evergreen_create_dsa_state(struct pipe_context *ctx,
155 const struct pipe_depth_stencil_alpha_state *state)
156 {
157 struct r600_pipe_state *rstate = CALLOC_STRUCT(r600_pipe_state);
158 unsigned db_depth_control, alpha_test_control, alpha_ref, db_shader_control;
159 unsigned stencil_ref_mask, stencil_ref_mask_bf, db_render_override, db_render_control;
160
161 if (rstate == NULL) {
162 return NULL;
163 }
164
165 rstate->id = R600_PIPE_STATE_DSA;
166 /* depth TODO some of those db_shader_control field depend on shader adjust mask & add it to shader */
167 /* db_shader_control is 0xFFFFFFBE as Z_EXPORT_ENABLE (bit 0) will be
168 * set by fragment shader if it export Z and KILL_ENABLE (bit 6) will
169 * be set if shader use texkill instruction
170 */
171 db_shader_control = S_02880C_Z_ORDER(V_02880C_EARLY_Z_THEN_LATE_Z);
172 stencil_ref_mask = 0;
173 stencil_ref_mask_bf = 0;
174 db_depth_control = S_028800_Z_ENABLE(state->depth.enabled) |
175 S_028800_Z_WRITE_ENABLE(state->depth.writemask) |
176 S_028800_ZFUNC(state->depth.func);
177
178 /* stencil */
179 if (state->stencil[0].enabled) {
180 db_depth_control |= S_028800_STENCIL_ENABLE(1);
181 db_depth_control |= S_028800_STENCILFUNC(r600_translate_ds_func(state->stencil[0].func));
182 db_depth_control |= S_028800_STENCILFAIL(r600_translate_stencil_op(state->stencil[0].fail_op));
183 db_depth_control |= S_028800_STENCILZPASS(r600_translate_stencil_op(state->stencil[0].zpass_op));
184 db_depth_control |= S_028800_STENCILZFAIL(r600_translate_stencil_op(state->stencil[0].zfail_op));
185
186
187 stencil_ref_mask = S_028430_STENCILMASK(state->stencil[0].valuemask) |
188 S_028430_STENCILWRITEMASK(state->stencil[0].writemask);
189 if (state->stencil[1].enabled) {
190 db_depth_control |= S_028800_BACKFACE_ENABLE(1);
191 db_depth_control |= S_028800_STENCILFUNC_BF(r600_translate_ds_func(state->stencil[1].func));
192 db_depth_control |= S_028800_STENCILFAIL_BF(r600_translate_stencil_op(state->stencil[1].fail_op));
193 db_depth_control |= S_028800_STENCILZPASS_BF(r600_translate_stencil_op(state->stencil[1].zpass_op));
194 db_depth_control |= S_028800_STENCILZFAIL_BF(r600_translate_stencil_op(state->stencil[1].zfail_op));
195 stencil_ref_mask_bf = S_028434_STENCILMASK_BF(state->stencil[1].valuemask) |
196 S_028434_STENCILWRITEMASK_BF(state->stencil[1].writemask);
197 }
198 }
199
200 /* alpha */
201 alpha_test_control = 0;
202 alpha_ref = 0;
203 if (state->alpha.enabled) {
204 alpha_test_control = S_028410_ALPHA_FUNC(state->alpha.func);
205 alpha_test_control |= S_028410_ALPHA_TEST_ENABLE(1);
206 alpha_ref = fui(state->alpha.ref_value);
207 }
208
209 /* misc */
210 db_render_control = 0;
211 db_render_override = S_02800C_FORCE_HIZ_ENABLE(V_02800C_FORCE_DISABLE) |
212 S_02800C_FORCE_HIS_ENABLE0(V_02800C_FORCE_DISABLE) |
213 S_02800C_FORCE_HIS_ENABLE1(V_02800C_FORCE_DISABLE);
214 /* TODO db_render_override depends on query */
215 r600_pipe_state_add_reg(rstate, R_028028_DB_STENCIL_CLEAR, 0x00000000, 0xFFFFFFFF, NULL);
216 r600_pipe_state_add_reg(rstate, R_02802C_DB_DEPTH_CLEAR, 0x3F800000, 0xFFFFFFFF, NULL);
217 r600_pipe_state_add_reg(rstate, R_028410_SX_ALPHA_TEST_CONTROL, alpha_test_control, 0xFFFFFFFF, NULL);
218 r600_pipe_state_add_reg(rstate,
219 R_028430_DB_STENCILREFMASK, stencil_ref_mask,
220 0xFFFFFFFF & C_028430_STENCILREF, NULL);
221 r600_pipe_state_add_reg(rstate,
222 R_028434_DB_STENCILREFMASK_BF, stencil_ref_mask_bf,
223 0xFFFFFFFF & C_028434_STENCILREF_BF, NULL);
224 r600_pipe_state_add_reg(rstate, R_028438_SX_ALPHA_REF, alpha_ref, 0xFFFFFFFF, NULL);
225 r600_pipe_state_add_reg(rstate, R_0286DC_SPI_FOG_CNTL, 0x00000000, 0xFFFFFFFF, NULL);
226 r600_pipe_state_add_reg(rstate, R_028800_DB_DEPTH_CONTROL, db_depth_control, 0xFFFFFFFF, NULL);
227 r600_pipe_state_add_reg(rstate, R_02880C_DB_SHADER_CONTROL, db_shader_control, 0xFFFFFFBE, NULL);
228 r600_pipe_state_add_reg(rstate, R_028000_DB_RENDER_CONTROL, db_render_control, 0xFFFFFFFF, NULL);
229 r600_pipe_state_add_reg(rstate, R_02800C_DB_RENDER_OVERRIDE, db_render_override, 0xFFFFFFFF, NULL);
230 r600_pipe_state_add_reg(rstate, R_028AC0_DB_SRESULTS_COMPARE_STATE0, 0x0, 0xFFFFFFFF, NULL);
231 r600_pipe_state_add_reg(rstate, R_028AC4_DB_SRESULTS_COMPARE_STATE1, 0x0, 0xFFFFFFFF, NULL);
232 r600_pipe_state_add_reg(rstate, R_028AC8_DB_PRELOAD_CONTROL, 0x0, 0xFFFFFFFF, NULL);
233 r600_pipe_state_add_reg(rstate, R_028B70_DB_ALPHA_TO_MASK, 0x0000AA00, 0xFFFFFFFF, NULL);
234
235 return rstate;
236 }
237
238 static void *evergreen_create_rs_state(struct pipe_context *ctx,
239 const struct pipe_rasterizer_state *state)
240 {
241 struct r600_pipe_rasterizer *rs = CALLOC_STRUCT(r600_pipe_rasterizer);
242 struct r600_pipe_state *rstate;
243 unsigned tmp;
244 unsigned prov_vtx = 1, polygon_dual_mode;
245 unsigned clip_rule;
246
247 if (rs == NULL) {
248 return NULL;
249 }
250
251 rstate = &rs->rstate;
252 rs->flatshade = state->flatshade;
253 rs->sprite_coord_enable = state->sprite_coord_enable;
254
255 clip_rule = state->scissor ? 0xAAAA : 0xFFFF;
256
257 /* offset */
258 rs->offset_units = state->offset_units;
259 rs->offset_scale = state->offset_scale * 12.0f;
260
261 rstate->id = R600_PIPE_STATE_RASTERIZER;
262 if (state->flatshade_first)
263 prov_vtx = 0;
264 tmp = 0x00000001;
265 if (state->sprite_coord_enable) {
266 tmp |= S_0286D4_PNT_SPRITE_ENA(1) |
267 S_0286D4_PNT_SPRITE_OVRD_X(2) |
268 S_0286D4_PNT_SPRITE_OVRD_Y(3) |
269 S_0286D4_PNT_SPRITE_OVRD_Z(0) |
270 S_0286D4_PNT_SPRITE_OVRD_W(1);
271 if (state->sprite_coord_mode != PIPE_SPRITE_COORD_UPPER_LEFT) {
272 tmp |= S_0286D4_PNT_SPRITE_TOP_1(1);
273 }
274 }
275 r600_pipe_state_add_reg(rstate, R_0286D4_SPI_INTERP_CONTROL_0, tmp, 0xFFFFFFFF, NULL);
276
277 polygon_dual_mode = (state->fill_front != PIPE_POLYGON_MODE_FILL ||
278 state->fill_back != PIPE_POLYGON_MODE_FILL);
279 r600_pipe_state_add_reg(rstate, R_028814_PA_SU_SC_MODE_CNTL,
280 S_028814_PROVOKING_VTX_LAST(prov_vtx) |
281 S_028814_CULL_FRONT((state->cull_face & PIPE_FACE_FRONT) ? 1 : 0) |
282 S_028814_CULL_BACK((state->cull_face & PIPE_FACE_BACK) ? 1 : 0) |
283 S_028814_FACE(!state->front_ccw) |
284 S_028814_POLY_OFFSET_FRONT_ENABLE(state->offset_tri) |
285 S_028814_POLY_OFFSET_BACK_ENABLE(state->offset_tri) |
286 S_028814_POLY_OFFSET_PARA_ENABLE(state->offset_tri) |
287 S_028814_POLY_MODE(polygon_dual_mode) |
288 S_028814_POLYMODE_FRONT_PTYPE(r600_translate_fill(state->fill_front)) |
289 S_028814_POLYMODE_BACK_PTYPE(r600_translate_fill(state->fill_back)), 0xFFFFFFFF, NULL);
290 r600_pipe_state_add_reg(rstate, R_02881C_PA_CL_VS_OUT_CNTL,
291 S_02881C_USE_VTX_POINT_SIZE(state->point_size_per_vertex) |
292 S_02881C_VS_OUT_MISC_VEC_ENA(state->point_size_per_vertex), 0xFFFFFFFF, NULL);
293 r600_pipe_state_add_reg(rstate, R_028820_PA_CL_NANINF_CNTL, 0x00000000, 0xFFFFFFFF, NULL);
294 /* point size 12.4 fixed point */
295 tmp = (unsigned)(state->point_size * 8.0);
296 r600_pipe_state_add_reg(rstate, R_028A00_PA_SU_POINT_SIZE, S_028A00_HEIGHT(tmp) | S_028A00_WIDTH(tmp), 0xFFFFFFFF, NULL);
297 r600_pipe_state_add_reg(rstate, R_028A04_PA_SU_POINT_MINMAX, 0x80000000, 0xFFFFFFFF, NULL);
298 r600_pipe_state_add_reg(rstate, R_028A08_PA_SU_LINE_CNTL, 0x00000008, 0xFFFFFFFF, NULL);
299 r600_pipe_state_add_reg(rstate, R_028C00_PA_SC_LINE_CNTL, 0x00000400, 0xFFFFFFFF, NULL);
300 r600_pipe_state_add_reg(rstate, R_028C0C_PA_CL_GB_VERT_CLIP_ADJ, 0x3F800000, 0xFFFFFFFF, NULL);
301 r600_pipe_state_add_reg(rstate, R_028C10_PA_CL_GB_VERT_DISC_ADJ, 0x3F800000, 0xFFFFFFFF, NULL);
302 r600_pipe_state_add_reg(rstate, R_028C14_PA_CL_GB_HORZ_CLIP_ADJ, 0x3F800000, 0xFFFFFFFF, NULL);
303 r600_pipe_state_add_reg(rstate, R_028C18_PA_CL_GB_HORZ_DISC_ADJ, 0x3F800000, 0xFFFFFFFF, NULL);
304 r600_pipe_state_add_reg(rstate, R_028B7C_PA_SU_POLY_OFFSET_CLAMP, 0x0, 0xFFFFFFFF, NULL);
305 r600_pipe_state_add_reg(rstate, R_028C08_PA_SU_VTX_CNTL, 0x00000005, 0xFFFFFFFF, NULL);
306 r600_pipe_state_add_reg(rstate, R_02820C_PA_SC_CLIPRECT_RULE, clip_rule, 0xFFFFFFFF, NULL);
307 return rstate;
308 }
309
310 static void evergreen_bind_rs_state(struct pipe_context *ctx, void *state)
311 {
312 struct r600_pipe_rasterizer *rs = (struct r600_pipe_rasterizer *)state;
313 struct r600_pipe_context *rctx = (struct r600_pipe_context *)ctx;
314
315 if (state == NULL)
316 return;
317
318 rctx->flatshade = rs->flatshade;
319 rctx->sprite_coord_enable = rs->sprite_coord_enable;
320 rctx->rasterizer = rs;
321
322 rctx->states[rs->rstate.id] = &rs->rstate;
323 r600_context_pipe_state_set(&rctx->ctx, &rs->rstate);
324 }
325
326 static void evergreen_delete_rs_state(struct pipe_context *ctx, void *state)
327 {
328 struct r600_pipe_context *rctx = (struct r600_pipe_context *)ctx;
329 struct r600_pipe_rasterizer *rs = (struct r600_pipe_rasterizer *)state;
330
331 if (rctx->rasterizer == rs) {
332 rctx->rasterizer = NULL;
333 }
334 if (rctx->states[rs->rstate.id] == &rs->rstate) {
335 rctx->states[rs->rstate.id] = NULL;
336 }
337 free(rs);
338 }
339
340 static void *evergreen_create_sampler_state(struct pipe_context *ctx,
341 const struct pipe_sampler_state *state)
342 {
343 struct r600_pipe_state *rstate = CALLOC_STRUCT(r600_pipe_state);
344 union util_color uc;
345
346 if (rstate == NULL) {
347 return NULL;
348 }
349
350 rstate->id = R600_PIPE_STATE_SAMPLER;
351 util_pack_color(state->border_color, PIPE_FORMAT_B8G8R8A8_UNORM, &uc);
352 r600_pipe_state_add_reg(rstate, R_03C000_SQ_TEX_SAMPLER_WORD0_0,
353 S_03C000_CLAMP_X(r600_tex_wrap(state->wrap_s)) |
354 S_03C000_CLAMP_Y(r600_tex_wrap(state->wrap_t)) |
355 S_03C000_CLAMP_Z(r600_tex_wrap(state->wrap_r)) |
356 S_03C000_XY_MAG_FILTER(r600_tex_filter(state->mag_img_filter)) |
357 S_03C000_XY_MIN_FILTER(r600_tex_filter(state->min_img_filter)) |
358 S_03C000_MIP_FILTER(r600_tex_mipfilter(state->min_mip_filter)) |
359 S_03C000_DEPTH_COMPARE_FUNCTION(r600_tex_compare(state->compare_func)) |
360 S_03C000_BORDER_COLOR_TYPE(uc.ui ? V_03C000_SQ_TEX_BORDER_COLOR_REGISTER : 0), 0xFFFFFFFF, NULL);
361 /* FIXME LOD it depends on texture base level ... */
362 r600_pipe_state_add_reg(rstate, R_03C004_SQ_TEX_SAMPLER_WORD1_0,
363 S_03C004_MIN_LOD(S_FIXED(CLAMP(state->min_lod, 0, 15), 6)) |
364 S_03C004_MAX_LOD(S_FIXED(CLAMP(state->max_lod, 0, 15), 6)),
365 0xFFFFFFFF, NULL);
366 r600_pipe_state_add_reg(rstate, R_03C008_SQ_TEX_SAMPLER_WORD2_0,
367 S_03C008_LOD_BIAS(S_FIXED(CLAMP(state->lod_bias, -16, 16), 6)) |
368 S_03C008_TYPE(1),
369 0xFFFFFFFF, NULL);
370
371 if (uc.ui) {
372 r600_pipe_state_add_reg(rstate, R_00A404_TD_PS_SAMPLER0_BORDER_RED, fui(state->border_color[0]), 0xFFFFFFFF, NULL);
373 r600_pipe_state_add_reg(rstate, R_00A408_TD_PS_SAMPLER0_BORDER_GREEN, fui(state->border_color[1]), 0xFFFFFFFF, NULL);
374 r600_pipe_state_add_reg(rstate, R_00A40C_TD_PS_SAMPLER0_BORDER_BLUE, fui(state->border_color[2]), 0xFFFFFFFF, NULL);
375 r600_pipe_state_add_reg(rstate, R_00A410_TD_PS_SAMPLER0_BORDER_ALPHA, fui(state->border_color[3]), 0xFFFFFFFF, NULL);
376 }
377 return rstate;
378 }
379
380 static void *evergreen_create_vertex_elements(struct pipe_context *ctx,
381 unsigned count,
382 const struct pipe_vertex_element *elements)
383 {
384 struct r600_vertex_element *v = CALLOC_STRUCT(r600_vertex_element);
385
386 assert(count < 32);
387 v->count = count;
388 v->refcount = 1;
389 memcpy(v->elements, elements, count * sizeof(struct pipe_vertex_element));
390 return v;
391 }
392
393 static void evergreen_sampler_view_destroy(struct pipe_context *ctx,
394 struct pipe_sampler_view *state)
395 {
396 struct r600_pipe_sampler_view *resource = (struct r600_pipe_sampler_view *)state;
397
398 pipe_resource_reference(&state->texture, NULL);
399 FREE(resource);
400 }
401
402 static struct pipe_sampler_view *evergreen_create_sampler_view(struct pipe_context *ctx,
403 struct pipe_resource *texture,
404 const struct pipe_sampler_view *state)
405 {
406 struct r600_pipe_sampler_view *resource = CALLOC_STRUCT(r600_pipe_sampler_view);
407 struct r600_pipe_state *rstate;
408 const struct util_format_description *desc;
409 struct r600_resource_texture *tmp;
410 struct r600_resource *rbuffer;
411 unsigned format;
412 uint32_t word4 = 0, yuv_format = 0, pitch = 0;
413 unsigned char swizzle[4];
414 struct r600_bo *bo[2];
415
416 if (resource == NULL)
417 return NULL;
418 rstate = &resource->state;
419
420 /* initialize base object */
421 resource->base = *state;
422 resource->base.texture = NULL;
423 pipe_reference(NULL, &texture->reference);
424 resource->base.texture = texture;
425 resource->base.reference.count = 1;
426 resource->base.context = ctx;
427
428 swizzle[0] = state->swizzle_r;
429 swizzle[1] = state->swizzle_g;
430 swizzle[2] = state->swizzle_b;
431 swizzle[3] = state->swizzle_a;
432 format = r600_translate_texformat(state->format,
433 swizzle,
434 &word4, &yuv_format);
435 if (format == ~0) {
436 format = 0;
437 }
438 desc = util_format_description(state->format);
439 if (desc == NULL) {
440 R600_ERR("unknow format %d\n", state->format);
441 }
442 tmp = (struct r600_resource_texture*)texture;
443 rbuffer = &tmp->resource;
444 bo[0] = rbuffer->bo;
445 bo[1] = rbuffer->bo;
446 /* FIXME depth texture decompression */
447 if (tmp->depth) {
448 r600_texture_depth_flush(ctx, texture);
449 tmp = (struct r600_resource_texture*)texture;
450 rbuffer = &tmp->flushed_depth_texture->resource;
451 bo[0] = rbuffer->bo;
452 bo[1] = rbuffer->bo;
453 }
454 pitch = align(tmp->pitch_in_pixels[0], 8);
455
456 /* FIXME properly handle first level != 0 */
457 r600_pipe_state_add_reg(rstate, R_030000_RESOURCE0_WORD0,
458 S_030000_DIM(r600_tex_dim(texture->target)) |
459 S_030000_PITCH((pitch / 8) - 1) |
460 S_030000_TEX_WIDTH(texture->width0 - 1), 0xFFFFFFFF, NULL);
461 r600_pipe_state_add_reg(rstate, R_030004_RESOURCE0_WORD1,
462 S_030004_TEX_HEIGHT(texture->height0 - 1) |
463 S_030004_TEX_DEPTH(texture->depth0 - 1),
464 0xFFFFFFFF, NULL);
465 r600_pipe_state_add_reg(rstate, R_030008_RESOURCE0_WORD2,
466 (tmp->offset[0] + r600_bo_offset(bo[0])) >> 8, 0xFFFFFFFF, bo[0]);
467 r600_pipe_state_add_reg(rstate, R_03000C_RESOURCE0_WORD3,
468 (tmp->offset[1] + r600_bo_offset(bo[1])) >> 8, 0xFFFFFFFF, bo[1]);
469 r600_pipe_state_add_reg(rstate, R_030010_RESOURCE0_WORD4,
470 word4 | S_030010_NUM_FORMAT_ALL(V_030010_SQ_NUM_FORMAT_NORM) |
471 S_030010_SRF_MODE_ALL(V_030010_SFR_MODE_NO_ZERO) |
472 S_030010_BASE_LEVEL(state->first_level), 0xFFFFFFFF, NULL);
473 r600_pipe_state_add_reg(rstate, R_030014_RESOURCE0_WORD5,
474 S_030014_LAST_LEVEL(state->last_level) |
475 S_030014_BASE_ARRAY(0) |
476 S_030014_LAST_ARRAY(0), 0xffffffff, NULL);
477 r600_pipe_state_add_reg(rstate, R_030018_RESOURCE0_WORD6, 0x0, 0xFFFFFFFF, NULL);
478 r600_pipe_state_add_reg(rstate, R_03001C_RESOURCE0_WORD7,
479 S_03001C_DATA_FORMAT(format) |
480 S_03001C_TYPE(V_03001C_SQ_TEX_VTX_VALID_TEXTURE), 0xFFFFFFFF, NULL);
481
482 return &resource->base;
483 }
484
485 static void evergreen_set_vs_sampler_view(struct pipe_context *ctx, unsigned count,
486 struct pipe_sampler_view **views)
487 {
488 struct r600_pipe_context *rctx = (struct r600_pipe_context *)ctx;
489 struct r600_pipe_sampler_view **resource = (struct r600_pipe_sampler_view **)views;
490
491 for (int i = 0; i < count; i++) {
492 if (resource[i]) {
493 evergreen_context_pipe_state_set_vs_resource(&rctx->ctx, &resource[i]->state, i + PIPE_MAX_ATTRIBS);
494 }
495 }
496 }
497
498 static void evergreen_set_ps_sampler_view(struct pipe_context *ctx, unsigned count,
499 struct pipe_sampler_view **views)
500 {
501 struct r600_pipe_context *rctx = (struct r600_pipe_context *)ctx;
502 struct r600_pipe_sampler_view **resource = (struct r600_pipe_sampler_view **)views;
503
504 rctx->ps_samplers.views = resource;
505 rctx->ps_samplers.n_views = count;
506
507 for (int i = 0; i < count; i++) {
508 if (resource[i]) {
509 evergreen_context_pipe_state_set_ps_resource(&rctx->ctx, &resource[i]->state, i);
510 }
511 }
512 }
513
514 static void evergreen_bind_state(struct pipe_context *ctx, void *state)
515 {
516 struct r600_pipe_context *rctx = (struct r600_pipe_context *)ctx;
517 struct r600_pipe_state *rstate = (struct r600_pipe_state *)state;
518
519 if (state == NULL)
520 return;
521 rctx->states[rstate->id] = rstate;
522 r600_context_pipe_state_set(&rctx->ctx, rstate);
523 }
524
525 static void evergreen_bind_ps_sampler(struct pipe_context *ctx, unsigned count, void **states)
526 {
527 struct r600_pipe_context *rctx = (struct r600_pipe_context *)ctx;
528 struct r600_pipe_state **rstates = (struct r600_pipe_state **)states;
529
530 rctx->ps_samplers.samplers = states;
531 rctx->ps_samplers.n_samplers = count;
532
533 for (int i = 0; i < count; i++) {
534 evergreen_context_pipe_state_set_ps_sampler(&rctx->ctx, rstates[i], i);
535 }
536 }
537
538 static void evergreen_bind_vs_sampler(struct pipe_context *ctx, unsigned count, void **states)
539 {
540 struct r600_pipe_context *rctx = (struct r600_pipe_context *)ctx;
541 struct r600_pipe_state **rstates = (struct r600_pipe_state **)states;
542
543 for (int i = 0; i < count; i++) {
544 evergreen_context_pipe_state_set_vs_sampler(&rctx->ctx, rstates[i], i);
545 }
546 }
547
548 static void evergreen_delete_state(struct pipe_context *ctx, void *state)
549 {
550 struct r600_pipe_context *rctx = (struct r600_pipe_context *)ctx;
551 struct r600_pipe_state *rstate = (struct r600_pipe_state *)state;
552
553 if (rctx->states[rstate->id] == rstate) {
554 rctx->states[rstate->id] = NULL;
555 }
556 for (int i = 0; i < rstate->nregs; i++) {
557 r600_bo_reference(rctx->radeon, &rstate->regs[i].bo, NULL);
558 }
559 free(rstate);
560 }
561
562 static void evergreen_delete_vertex_element(struct pipe_context *ctx, void *state)
563 {
564 struct r600_vertex_element *v = (struct r600_vertex_element*)state;
565
566 if (v == NULL)
567 return;
568 if (--v->refcount)
569 return;
570 free(v);
571 }
572
573 static void evergreen_set_clip_state(struct pipe_context *ctx,
574 const struct pipe_clip_state *state)
575 {
576 struct r600_pipe_context *rctx = (struct r600_pipe_context *)ctx;
577 struct r600_pipe_state *rstate = CALLOC_STRUCT(r600_pipe_state);
578
579 if (rstate == NULL)
580 return;
581
582 rctx->clip = *state;
583 rstate->id = R600_PIPE_STATE_CLIP;
584 for (int i = 0; i < state->nr; i++) {
585 r600_pipe_state_add_reg(rstate,
586 R_0285BC_PA_CL_UCP0_X + i * 4,
587 fui(state->ucp[i][0]), 0xFFFFFFFF, NULL);
588 r600_pipe_state_add_reg(rstate,
589 R_0285C0_PA_CL_UCP0_Y + i * 4,
590 fui(state->ucp[i][1]) , 0xFFFFFFFF, NULL);
591 r600_pipe_state_add_reg(rstate,
592 R_0285C4_PA_CL_UCP0_Z + i * 4,
593 fui(state->ucp[i][2]), 0xFFFFFFFF, NULL);
594 r600_pipe_state_add_reg(rstate,
595 R_0285C8_PA_CL_UCP0_W + i * 4,
596 fui(state->ucp[i][3]), 0xFFFFFFFF, NULL);
597 }
598 r600_pipe_state_add_reg(rstate, R_028810_PA_CL_CLIP_CNTL,
599 S_028810_PS_UCP_MODE(3) | ((1 << state->nr) - 1) |
600 S_028810_ZCLIP_NEAR_DISABLE(state->depth_clamp) |
601 S_028810_ZCLIP_FAR_DISABLE(state->depth_clamp), 0xFFFFFFFF, NULL);
602
603 free(rctx->states[R600_PIPE_STATE_CLIP]);
604 rctx->states[R600_PIPE_STATE_CLIP] = rstate;
605 r600_context_pipe_state_set(&rctx->ctx, rstate);
606 }
607
608 static void evergreen_bind_vertex_elements(struct pipe_context *ctx, void *state)
609 {
610 struct r600_pipe_context *rctx = (struct r600_pipe_context *)ctx;
611 struct r600_vertex_element *v = (struct r600_vertex_element*)state;
612
613 evergreen_delete_vertex_element(ctx, rctx->vertex_elements);
614 rctx->vertex_elements = v;
615 if (v) {
616 v->refcount++;
617 // rctx->vs_rebuild = TRUE;
618 }
619 }
620
621 static void evergreen_set_polygon_stipple(struct pipe_context *ctx,
622 const struct pipe_poly_stipple *state)
623 {
624 }
625
626 static void evergreen_set_sample_mask(struct pipe_context *pipe, unsigned sample_mask)
627 {
628 }
629
630 static void evergreen_set_scissor_state(struct pipe_context *ctx,
631 const struct pipe_scissor_state *state)
632 {
633 struct r600_pipe_context *rctx = (struct r600_pipe_context *)ctx;
634 struct r600_pipe_state *rstate = CALLOC_STRUCT(r600_pipe_state);
635 u32 tl, br;
636
637 if (rstate == NULL)
638 return;
639
640 rstate->id = R600_PIPE_STATE_SCISSOR;
641 tl = S_028240_TL_X(state->minx) | S_028240_TL_Y(state->miny);
642 br = S_028244_BR_X(state->maxx) | S_028244_BR_Y(state->maxy);
643 r600_pipe_state_add_reg(rstate,
644 R_028210_PA_SC_CLIPRECT_0_TL, tl,
645 0xFFFFFFFF, NULL);
646 r600_pipe_state_add_reg(rstate,
647 R_028214_PA_SC_CLIPRECT_0_BR, br,
648 0xFFFFFFFF, NULL);
649 r600_pipe_state_add_reg(rstate,
650 R_028218_PA_SC_CLIPRECT_1_TL, tl,
651 0xFFFFFFFF, NULL);
652 r600_pipe_state_add_reg(rstate,
653 R_02821C_PA_SC_CLIPRECT_1_BR, br,
654 0xFFFFFFFF, NULL);
655 r600_pipe_state_add_reg(rstate,
656 R_028220_PA_SC_CLIPRECT_2_TL, tl,
657 0xFFFFFFFF, NULL);
658 r600_pipe_state_add_reg(rstate,
659 R_028224_PA_SC_CLIPRECT_2_BR, br,
660 0xFFFFFFFF, NULL);
661 r600_pipe_state_add_reg(rstate,
662 R_028228_PA_SC_CLIPRECT_3_TL, tl,
663 0xFFFFFFFF, NULL);
664 r600_pipe_state_add_reg(rstate,
665 R_02822C_PA_SC_CLIPRECT_3_BR, br,
666 0xFFFFFFFF, NULL);
667
668 free(rctx->states[R600_PIPE_STATE_SCISSOR]);
669 rctx->states[R600_PIPE_STATE_SCISSOR] = rstate;
670 r600_context_pipe_state_set(&rctx->ctx, rstate);
671 }
672
673 static void evergreen_set_stencil_ref(struct pipe_context *ctx,
674 const struct pipe_stencil_ref *state)
675 {
676 struct r600_pipe_context *rctx = (struct r600_pipe_context *)ctx;
677 struct r600_pipe_state *rstate = CALLOC_STRUCT(r600_pipe_state);
678 u32 tmp;
679
680 if (rstate == NULL)
681 return;
682
683 rctx->stencil_ref = *state;
684 rstate->id = R600_PIPE_STATE_STENCIL_REF;
685 tmp = S_028430_STENCILREF(state->ref_value[0]);
686 r600_pipe_state_add_reg(rstate,
687 R_028430_DB_STENCILREFMASK, tmp,
688 ~C_028430_STENCILREF, NULL);
689 tmp = S_028434_STENCILREF_BF(state->ref_value[1]);
690 r600_pipe_state_add_reg(rstate,
691 R_028434_DB_STENCILREFMASK_BF, tmp,
692 ~C_028434_STENCILREF_BF, NULL);
693
694 free(rctx->states[R600_PIPE_STATE_STENCIL_REF]);
695 rctx->states[R600_PIPE_STATE_STENCIL_REF] = rstate;
696 r600_context_pipe_state_set(&rctx->ctx, rstate);
697 }
698
699 static void evergreen_set_viewport_state(struct pipe_context *ctx,
700 const struct pipe_viewport_state *state)
701 {
702 struct r600_pipe_context *rctx = (struct r600_pipe_context *)ctx;
703 struct r600_pipe_state *rstate = CALLOC_STRUCT(r600_pipe_state);
704
705 if (rstate == NULL)
706 return;
707
708 rctx->viewport = *state;
709 rstate->id = R600_PIPE_STATE_VIEWPORT;
710 r600_pipe_state_add_reg(rstate, R_0282D0_PA_SC_VPORT_ZMIN_0, 0x00000000, 0xFFFFFFFF, NULL);
711 r600_pipe_state_add_reg(rstate, R_0282D4_PA_SC_VPORT_ZMAX_0, 0x3F800000, 0xFFFFFFFF, NULL);
712 r600_pipe_state_add_reg(rstate, R_02843C_PA_CL_VPORT_XSCALE_0, fui(state->scale[0]), 0xFFFFFFFF, NULL);
713 r600_pipe_state_add_reg(rstate, R_028444_PA_CL_VPORT_YSCALE_0, fui(state->scale[1]), 0xFFFFFFFF, NULL);
714 r600_pipe_state_add_reg(rstate, R_02844C_PA_CL_VPORT_ZSCALE_0, fui(state->scale[2]), 0xFFFFFFFF, NULL);
715 r600_pipe_state_add_reg(rstate, R_028440_PA_CL_VPORT_XOFFSET_0, fui(state->translate[0]), 0xFFFFFFFF, NULL);
716 r600_pipe_state_add_reg(rstate, R_028448_PA_CL_VPORT_YOFFSET_0, fui(state->translate[1]), 0xFFFFFFFF, NULL);
717 r600_pipe_state_add_reg(rstate, R_028450_PA_CL_VPORT_ZOFFSET_0, fui(state->translate[2]), 0xFFFFFFFF, NULL);
718 r600_pipe_state_add_reg(rstate, R_028818_PA_CL_VTE_CNTL, 0x0000043F, 0xFFFFFFFF, NULL);
719
720 free(rctx->states[R600_PIPE_STATE_VIEWPORT]);
721 rctx->states[R600_PIPE_STATE_VIEWPORT] = rstate;
722 r600_context_pipe_state_set(&rctx->ctx, rstate);
723 }
724
725 static void evergreen_cb(struct r600_pipe_context *rctx, struct r600_pipe_state *rstate,
726 const struct pipe_framebuffer_state *state, int cb)
727 {
728 struct r600_resource_texture *rtex;
729 struct r600_resource *rbuffer;
730 unsigned level = state->cbufs[cb]->level;
731 unsigned pitch, slice;
732 unsigned color_info;
733 unsigned format, swap, ntype;
734 const struct util_format_description *desc;
735 struct r600_bo *bo[3];
736
737 rtex = (struct r600_resource_texture*)state->cbufs[cb]->texture;
738 rbuffer = &rtex->resource;
739 bo[0] = rbuffer->bo;
740 bo[1] = rbuffer->bo;
741 bo[2] = rbuffer->bo;
742
743 pitch = rtex->pitch_in_pixels[level] / 8 - 1;
744 slice = rtex->pitch_in_pixels[level] * state->cbufs[cb]->height / 64 - 1;
745 ntype = 0;
746 desc = util_format_description(rtex->resource.base.b.format);
747 if (desc->colorspace == UTIL_FORMAT_COLORSPACE_SRGB)
748 ntype = V_028C70_NUMBER_SRGB;
749
750 format = r600_translate_colorformat(rtex->resource.base.b.format);
751 swap = r600_translate_colorswap(rtex->resource.base.b.format);
752 color_info = S_028C70_FORMAT(format) |
753 S_028C70_COMP_SWAP(swap) |
754 S_028C70_BLEND_CLAMP(1) |
755 S_028C70_NUMBER_TYPE(ntype);
756 if (desc->colorspace != UTIL_FORMAT_COLORSPACE_ZS)
757 color_info |= S_028C70_SOURCE_FORMAT(1);
758
759 /* FIXME handle enabling of CB beyond BASE8 which has different offset */
760 r600_pipe_state_add_reg(rstate,
761 R_028C60_CB_COLOR0_BASE + cb * 0x3C,
762 (state->cbufs[cb]->offset + r600_bo_offset(bo[0])) >> 8, 0xFFFFFFFF, bo[0]);
763 r600_pipe_state_add_reg(rstate,
764 R_028C78_CB_COLOR0_DIM + cb * 0x3C,
765 0x0, 0xFFFFFFFF, NULL);
766 r600_pipe_state_add_reg(rstate,
767 R_028C70_CB_COLOR0_INFO + cb * 0x3C,
768 color_info, 0xFFFFFFFF, bo[0]);
769 r600_pipe_state_add_reg(rstate,
770 R_028C64_CB_COLOR0_PITCH + cb * 0x3C,
771 S_028C64_PITCH_TILE_MAX(pitch),
772 0xFFFFFFFF, NULL);
773 r600_pipe_state_add_reg(rstate,
774 R_028C68_CB_COLOR0_SLICE + cb * 0x3C,
775 S_028C68_SLICE_TILE_MAX(slice),
776 0xFFFFFFFF, NULL);
777 r600_pipe_state_add_reg(rstate,
778 R_028C6C_CB_COLOR0_VIEW + cb * 0x3C,
779 0x00000000, 0xFFFFFFFF, NULL);
780 r600_pipe_state_add_reg(rstate,
781 R_028C74_CB_COLOR0_ATTRIB + cb * 0x3C,
782 S_028C74_NON_DISP_TILING_ORDER(1),
783 0xFFFFFFFF, bo[0]);
784 }
785
786 static void evergreen_db(struct r600_pipe_context *rctx, struct r600_pipe_state *rstate,
787 const struct pipe_framebuffer_state *state)
788 {
789 struct r600_resource_texture *rtex;
790 struct r600_resource *rbuffer;
791 unsigned level;
792 unsigned pitch, slice, format, stencil_format;
793
794 if (state->zsbuf == NULL)
795 return;
796
797 rtex = (struct r600_resource_texture*)state->zsbuf->texture;
798 rtex->tiled = 1;
799 rtex->array_mode = 2;
800 rtex->tile_type = 1;
801 rtex->depth = 1;
802 rbuffer = &rtex->resource;
803
804 level = state->zsbuf->level;
805 pitch = rtex->pitch_in_pixels[level] / 8 - 1;
806 slice = rtex->pitch_in_pixels[level] * state->zsbuf->height / 64 - 1;
807 format = r600_translate_dbformat(state->zsbuf->texture->format);
808 stencil_format = r600_translate_stencilformat(state->zsbuf->texture->format);
809
810 r600_pipe_state_add_reg(rstate, R_028048_DB_Z_READ_BASE,
811 (state->zsbuf->offset + r600_bo_offset(rbuffer->bo)) >> 8, 0xFFFFFFFF, rbuffer->bo);
812 r600_pipe_state_add_reg(rstate, R_028050_DB_Z_WRITE_BASE,
813 (state->zsbuf->offset + r600_bo_offset(rbuffer->bo)) >> 8, 0xFFFFFFFF, rbuffer->bo);
814
815 if (stencil_format) {
816 uint32_t stencil_offset;
817
818 stencil_offset = ((state->zsbuf->height * rtex->pitch_in_bytes[level]) + 255) & ~255;
819 r600_pipe_state_add_reg(rstate, R_02804C_DB_STENCIL_READ_BASE,
820 (state->zsbuf->offset + stencil_offset + r600_bo_offset(rbuffer->bo)) >> 8, 0xFFFFFFFF, rbuffer->bo);
821 r600_pipe_state_add_reg(rstate, R_028054_DB_STENCIL_WRITE_BASE,
822 (state->zsbuf->offset + stencil_offset + r600_bo_offset(rbuffer->bo)) >> 8, 0xFFFFFFFF, rbuffer->bo);
823 }
824
825 r600_pipe_state_add_reg(rstate, R_028008_DB_DEPTH_VIEW, 0x00000000, 0xFFFFFFFF, NULL);
826 r600_pipe_state_add_reg(rstate, R_028044_DB_STENCIL_INFO,
827 S_028044_FORMAT(stencil_format), 0xFFFFFFFF, rbuffer->bo);
828
829 r600_pipe_state_add_reg(rstate, R_028040_DB_Z_INFO,
830 S_028040_ARRAY_MODE(rtex->array_mode) | S_028040_FORMAT(format),
831 0xFFFFFFFF, rbuffer->bo);
832 r600_pipe_state_add_reg(rstate, R_028058_DB_DEPTH_SIZE,
833 S_028058_PITCH_TILE_MAX(pitch),
834 0xFFFFFFFF, NULL);
835 r600_pipe_state_add_reg(rstate, R_02805C_DB_DEPTH_SLICE,
836 S_02805C_SLICE_TILE_MAX(slice),
837 0xFFFFFFFF, NULL);
838 }
839
840 static void evergreen_set_framebuffer_state(struct pipe_context *ctx,
841 const struct pipe_framebuffer_state *state)
842 {
843 struct r600_pipe_context *rctx = (struct r600_pipe_context *)ctx;
844 struct r600_pipe_state *rstate = CALLOC_STRUCT(r600_pipe_state);
845 u32 shader_mask, tl, br, target_mask;
846
847 if (rstate == NULL)
848 return;
849
850 /* unreference old buffer and reference new one */
851 rstate->id = R600_PIPE_STATE_FRAMEBUFFER;
852
853 util_copy_framebuffer_state(&rctx->framebuffer, state);
854
855 rctx->pframebuffer = &rctx->framebuffer;
856
857 /* build states */
858 for (int i = 0; i < state->nr_cbufs; i++) {
859 evergreen_cb(rctx, rstate, state, i);
860 }
861 if (state->zsbuf) {
862 evergreen_db(rctx, rstate, state);
863 }
864
865 target_mask = 0x00000000;
866 target_mask = 0xFFFFFFFF;
867 shader_mask = 0;
868 for (int i = 0; i < state->nr_cbufs; i++) {
869 target_mask ^= 0xf << (i * 4);
870 shader_mask |= 0xf << (i * 4);
871 }
872 tl = S_028240_TL_X(0) | S_028240_TL_Y(0);
873 br = S_028244_BR_X(state->width) | S_028244_BR_Y(state->height);
874
875 r600_pipe_state_add_reg(rstate,
876 R_028240_PA_SC_GENERIC_SCISSOR_TL, tl,
877 0xFFFFFFFF, NULL);
878 r600_pipe_state_add_reg(rstate,
879 R_028244_PA_SC_GENERIC_SCISSOR_BR, br,
880 0xFFFFFFFF, NULL);
881 r600_pipe_state_add_reg(rstate,
882 R_028250_PA_SC_VPORT_SCISSOR_0_TL, tl,
883 0xFFFFFFFF, NULL);
884 r600_pipe_state_add_reg(rstate,
885 R_028254_PA_SC_VPORT_SCISSOR_0_BR, br,
886 0xFFFFFFFF, NULL);
887 r600_pipe_state_add_reg(rstate,
888 R_028030_PA_SC_SCREEN_SCISSOR_TL, tl,
889 0xFFFFFFFF, NULL);
890 r600_pipe_state_add_reg(rstate,
891 R_028034_PA_SC_SCREEN_SCISSOR_BR, br,
892 0xFFFFFFFF, NULL);
893 r600_pipe_state_add_reg(rstate,
894 R_028204_PA_SC_WINDOW_SCISSOR_TL, tl,
895 0xFFFFFFFF, NULL);
896 r600_pipe_state_add_reg(rstate,
897 R_028208_PA_SC_WINDOW_SCISSOR_BR, br,
898 0xFFFFFFFF, NULL);
899 r600_pipe_state_add_reg(rstate,
900 R_028200_PA_SC_WINDOW_OFFSET, 0x00000000,
901 0xFFFFFFFF, NULL);
902 r600_pipe_state_add_reg(rstate,
903 R_028230_PA_SC_EDGERULE, 0xAAAAAAAA,
904 0xFFFFFFFF, NULL);
905
906 r600_pipe_state_add_reg(rstate, R_028238_CB_TARGET_MASK,
907 0x00000000, target_mask, NULL);
908 r600_pipe_state_add_reg(rstate, R_02823C_CB_SHADER_MASK,
909 shader_mask, 0xFFFFFFFF, NULL);
910 r600_pipe_state_add_reg(rstate, R_028C04_PA_SC_AA_CONFIG,
911 0x00000000, 0xFFFFFFFF, NULL);
912 r600_pipe_state_add_reg(rstate, R_028C1C_PA_SC_AA_SAMPLE_LOCS_MCTX,
913 0x00000000, 0xFFFFFFFF, NULL);
914
915 free(rctx->states[R600_PIPE_STATE_FRAMEBUFFER]);
916 rctx->states[R600_PIPE_STATE_FRAMEBUFFER] = rstate;
917 r600_context_pipe_state_set(&rctx->ctx, rstate);
918 }
919
920 static void evergreen_set_index_buffer(struct pipe_context *ctx,
921 const struct pipe_index_buffer *ib)
922 {
923 struct r600_pipe_context *rctx = (struct r600_pipe_context *)ctx;
924
925 if (ib) {
926 pipe_resource_reference(&rctx->index_buffer.buffer, ib->buffer);
927 memcpy(&rctx->index_buffer, ib, sizeof(rctx->index_buffer));
928 } else {
929 pipe_resource_reference(&rctx->index_buffer.buffer, NULL);
930 memset(&rctx->index_buffer, 0, sizeof(rctx->index_buffer));
931 }
932
933 /* TODO make this more like a state */
934 }
935
936 static void evergreen_set_vertex_buffers(struct pipe_context *ctx, unsigned count,
937 const struct pipe_vertex_buffer *buffers)
938 {
939 struct r600_pipe_context *rctx = (struct r600_pipe_context *)ctx;
940
941 for (int i = 0; i < rctx->nvertex_buffer; i++) {
942 pipe_resource_reference(&rctx->vertex_buffer[i].buffer, NULL);
943 }
944 memcpy(rctx->vertex_buffer, buffers, sizeof(struct pipe_vertex_buffer) * count);
945 for (int i = 0; i < count; i++) {
946 rctx->vertex_buffer[i].buffer = NULL;
947 if (r600_buffer_is_user_buffer(buffers[i].buffer))
948 rctx->any_user_vbs = TRUE;
949 pipe_resource_reference(&rctx->vertex_buffer[i].buffer, buffers[i].buffer);
950 }
951 rctx->nvertex_buffer = count;
952 }
953
954 static void evergreen_set_constant_buffer(struct pipe_context *ctx, uint shader, uint index,
955 struct pipe_resource *buffer)
956 {
957 struct r600_pipe_context *rctx = (struct r600_pipe_context *)ctx;
958 struct r600_resource *rbuffer = (struct r600_resource*)buffer;
959
960 switch (shader) {
961 case PIPE_SHADER_VERTEX:
962 rctx->vs_const_buffer.nregs = 0;
963 r600_pipe_state_add_reg(&rctx->vs_const_buffer,
964 R_028180_ALU_CONST_BUFFER_SIZE_VS_0,
965 ALIGN_DIVUP(buffer->width0 >> 4, 16),
966 0xFFFFFFFF, NULL);
967 r600_pipe_state_add_reg(&rctx->vs_const_buffer,
968 R_028980_ALU_CONST_CACHE_VS_0,
969 (r600_bo_offset(rbuffer->bo)) >> 8, 0xFFFFFFFF, rbuffer->bo);
970 r600_context_pipe_state_set(&rctx->ctx, &rctx->vs_const_buffer);
971 break;
972 case PIPE_SHADER_FRAGMENT:
973 rctx->ps_const_buffer.nregs = 0;
974 r600_pipe_state_add_reg(&rctx->ps_const_buffer,
975 R_028140_ALU_CONST_BUFFER_SIZE_PS_0,
976 ALIGN_DIVUP(buffer->width0 >> 4, 16),
977 0xFFFFFFFF, NULL);
978 r600_pipe_state_add_reg(&rctx->ps_const_buffer,
979 R_028940_ALU_CONST_CACHE_PS_0,
980 (r600_bo_offset(rbuffer->bo)) >> 8, 0xFFFFFFFF, rbuffer->bo);
981 r600_context_pipe_state_set(&rctx->ctx, &rctx->ps_const_buffer);
982 break;
983 default:
984 R600_ERR("unsupported %d\n", shader);
985 return;
986 }
987 }
988
989 static void *evergreen_create_shader_state(struct pipe_context *ctx,
990 const struct pipe_shader_state *state)
991 {
992 struct r600_pipe_shader *shader = CALLOC_STRUCT(r600_pipe_shader);
993 int r;
994
995 r = r600_pipe_shader_create(ctx, shader, state->tokens);
996 if (r) {
997 return NULL;
998 }
999 return shader;
1000 }
1001
1002 static void evergreen_bind_ps_shader(struct pipe_context *ctx, void *state)
1003 {
1004 struct r600_pipe_context *rctx = (struct r600_pipe_context *)ctx;
1005
1006 /* TODO delete old shader */
1007 rctx->ps_shader = (struct r600_pipe_shader *)state;
1008 }
1009
1010 static void evergreen_bind_vs_shader(struct pipe_context *ctx, void *state)
1011 {
1012 struct r600_pipe_context *rctx = (struct r600_pipe_context *)ctx;
1013
1014 /* TODO delete old shader */
1015 rctx->vs_shader = (struct r600_pipe_shader *)state;
1016 }
1017
1018 static void evergreen_delete_ps_shader(struct pipe_context *ctx, void *state)
1019 {
1020 struct r600_pipe_context *rctx = (struct r600_pipe_context *)ctx;
1021 struct r600_pipe_shader *shader = (struct r600_pipe_shader *)state;
1022
1023 if (rctx->ps_shader == shader) {
1024 rctx->ps_shader = NULL;
1025 }
1026 /* TODO proper delete */
1027 free(shader);
1028 }
1029
1030 static void evergreen_delete_vs_shader(struct pipe_context *ctx, void *state)
1031 {
1032 struct r600_pipe_context *rctx = (struct r600_pipe_context *)ctx;
1033 struct r600_pipe_shader *shader = (struct r600_pipe_shader *)state;
1034
1035 if (rctx->vs_shader == shader) {
1036 rctx->vs_shader = NULL;
1037 }
1038 /* TODO proper delete */
1039 free(shader);
1040 }
1041
1042 void evergreen_init_state_functions(struct r600_pipe_context *rctx)
1043 {
1044 rctx->context.create_blend_state = evergreen_create_blend_state;
1045 rctx->context.create_depth_stencil_alpha_state = evergreen_create_dsa_state;
1046 rctx->context.create_fs_state = evergreen_create_shader_state;
1047 rctx->context.create_rasterizer_state = evergreen_create_rs_state;
1048 rctx->context.create_sampler_state = evergreen_create_sampler_state;
1049 rctx->context.create_sampler_view = evergreen_create_sampler_view;
1050 rctx->context.create_vertex_elements_state = evergreen_create_vertex_elements;
1051 rctx->context.create_vs_state = evergreen_create_shader_state;
1052 rctx->context.bind_blend_state = evergreen_bind_blend_state;
1053 rctx->context.bind_depth_stencil_alpha_state = evergreen_bind_state;
1054 rctx->context.bind_fragment_sampler_states = evergreen_bind_ps_sampler;
1055 rctx->context.bind_fs_state = evergreen_bind_ps_shader;
1056 rctx->context.bind_rasterizer_state = evergreen_bind_rs_state;
1057 rctx->context.bind_vertex_elements_state = evergreen_bind_vertex_elements;
1058 rctx->context.bind_vertex_sampler_states = evergreen_bind_vs_sampler;
1059 rctx->context.bind_vs_state = evergreen_bind_vs_shader;
1060 rctx->context.delete_blend_state = evergreen_delete_state;
1061 rctx->context.delete_depth_stencil_alpha_state = evergreen_delete_state;
1062 rctx->context.delete_fs_state = evergreen_delete_ps_shader;
1063 rctx->context.delete_rasterizer_state = evergreen_delete_rs_state;
1064 rctx->context.delete_sampler_state = evergreen_delete_state;
1065 rctx->context.delete_vertex_elements_state = evergreen_delete_vertex_element;
1066 rctx->context.delete_vs_state = evergreen_delete_vs_shader;
1067 rctx->context.set_blend_color = evergreen_set_blend_color;
1068 rctx->context.set_clip_state = evergreen_set_clip_state;
1069 rctx->context.set_constant_buffer = evergreen_set_constant_buffer;
1070 rctx->context.set_fragment_sampler_views = evergreen_set_ps_sampler_view;
1071 rctx->context.set_framebuffer_state = evergreen_set_framebuffer_state;
1072 rctx->context.set_polygon_stipple = evergreen_set_polygon_stipple;
1073 rctx->context.set_sample_mask = evergreen_set_sample_mask;
1074 rctx->context.set_scissor_state = evergreen_set_scissor_state;
1075 rctx->context.set_stencil_ref = evergreen_set_stencil_ref;
1076 rctx->context.set_vertex_buffers = evergreen_set_vertex_buffers;
1077 rctx->context.set_index_buffer = evergreen_set_index_buffer;
1078 rctx->context.set_vertex_sampler_views = evergreen_set_vs_sampler_view;
1079 rctx->context.set_viewport_state = evergreen_set_viewport_state;
1080 rctx->context.sampler_view_destroy = evergreen_sampler_view_destroy;
1081 }
1082
1083 void evergreen_init_config(struct r600_pipe_context *rctx)
1084 {
1085 struct r600_pipe_state *rstate = &rctx->config;
1086 int ps_prio;
1087 int vs_prio;
1088 int gs_prio;
1089 int es_prio;
1090 int hs_prio, cs_prio, ls_prio;
1091 int num_ps_gprs;
1092 int num_vs_gprs;
1093 int num_gs_gprs;
1094 int num_es_gprs;
1095 int num_hs_gprs;
1096 int num_ls_gprs;
1097 int num_temp_gprs;
1098 int num_ps_threads;
1099 int num_vs_threads;
1100 int num_gs_threads;
1101 int num_es_threads;
1102 int num_hs_threads;
1103 int num_ls_threads;
1104 int num_ps_stack_entries;
1105 int num_vs_stack_entries;
1106 int num_gs_stack_entries;
1107 int num_es_stack_entries;
1108 int num_hs_stack_entries;
1109 int num_ls_stack_entries;
1110 enum radeon_family family;
1111 unsigned tmp;
1112
1113 family = r600_get_family(rctx->radeon);
1114 ps_prio = 0;
1115 vs_prio = 1;
1116 gs_prio = 2;
1117 es_prio = 3;
1118 hs_prio = 0;
1119 ls_prio = 0;
1120 cs_prio = 0;
1121
1122 switch (family) {
1123 case CHIP_CEDAR:
1124 default:
1125 num_ps_gprs = 93;
1126 num_vs_gprs = 46;
1127 num_temp_gprs = 4;
1128 num_gs_gprs = 31;
1129 num_es_gprs = 31;
1130 num_hs_gprs = 23;
1131 num_ls_gprs = 23;
1132 num_ps_threads = 96;
1133 num_vs_threads = 16;
1134 num_gs_threads = 16;
1135 num_es_threads = 16;
1136 num_hs_threads = 16;
1137 num_ls_threads = 16;
1138 num_ps_stack_entries = 42;
1139 num_vs_stack_entries = 42;
1140 num_gs_stack_entries = 42;
1141 num_es_stack_entries = 42;
1142 num_hs_stack_entries = 42;
1143 num_ls_stack_entries = 42;
1144 break;
1145 case CHIP_REDWOOD:
1146 num_ps_gprs = 93;
1147 num_vs_gprs = 46;
1148 num_temp_gprs = 4;
1149 num_gs_gprs = 31;
1150 num_es_gprs = 31;
1151 num_hs_gprs = 23;
1152 num_ls_gprs = 23;
1153 num_ps_threads = 128;
1154 num_vs_threads = 20;
1155 num_gs_threads = 20;
1156 num_es_threads = 20;
1157 num_hs_threads = 20;
1158 num_ls_threads = 20;
1159 num_ps_stack_entries = 42;
1160 num_vs_stack_entries = 42;
1161 num_gs_stack_entries = 42;
1162 num_es_stack_entries = 42;
1163 num_hs_stack_entries = 42;
1164 num_ls_stack_entries = 42;
1165 break;
1166 case CHIP_JUNIPER:
1167 num_ps_gprs = 93;
1168 num_vs_gprs = 46;
1169 num_temp_gprs = 4;
1170 num_gs_gprs = 31;
1171 num_es_gprs = 31;
1172 num_hs_gprs = 23;
1173 num_ls_gprs = 23;
1174 num_ps_threads = 128;
1175 num_vs_threads = 20;
1176 num_gs_threads = 20;
1177 num_es_threads = 20;
1178 num_hs_threads = 20;
1179 num_ls_threads = 20;
1180 num_ps_stack_entries = 85;
1181 num_vs_stack_entries = 85;
1182 num_gs_stack_entries = 85;
1183 num_es_stack_entries = 85;
1184 num_hs_stack_entries = 85;
1185 num_ls_stack_entries = 85;
1186 break;
1187 case CHIP_CYPRESS:
1188 case CHIP_HEMLOCK:
1189 num_ps_gprs = 93;
1190 num_vs_gprs = 46;
1191 num_temp_gprs = 4;
1192 num_gs_gprs = 31;
1193 num_es_gprs = 31;
1194 num_hs_gprs = 23;
1195 num_ls_gprs = 23;
1196 num_ps_threads = 128;
1197 num_vs_threads = 20;
1198 num_gs_threads = 20;
1199 num_es_threads = 20;
1200 num_hs_threads = 20;
1201 num_ls_threads = 20;
1202 num_ps_stack_entries = 85;
1203 num_vs_stack_entries = 85;
1204 num_gs_stack_entries = 85;
1205 num_es_stack_entries = 85;
1206 num_hs_stack_entries = 85;
1207 num_ls_stack_entries = 85;
1208 break;
1209 }
1210
1211 tmp = 0x00000000;
1212 switch (family) {
1213 case CHIP_CEDAR:
1214 break;
1215 default:
1216 tmp |= S_008C00_VC_ENABLE(1);
1217 break;
1218 }
1219 tmp |= S_008C00_EXPORT_SRC_C(1);
1220 tmp |= S_008C00_CS_PRIO(cs_prio);
1221 tmp |= S_008C00_LS_PRIO(ls_prio);
1222 tmp |= S_008C00_HS_PRIO(hs_prio);
1223 tmp |= S_008C00_PS_PRIO(ps_prio);
1224 tmp |= S_008C00_VS_PRIO(vs_prio);
1225 tmp |= S_008C00_GS_PRIO(gs_prio);
1226 tmp |= S_008C00_ES_PRIO(es_prio);
1227 r600_pipe_state_add_reg(rstate, R_008C00_SQ_CONFIG, tmp, 0xFFFFFFFF, NULL);
1228
1229 tmp = 0;
1230 tmp |= S_008C04_NUM_PS_GPRS(num_ps_gprs);
1231 tmp |= S_008C04_NUM_VS_GPRS(num_vs_gprs);
1232 tmp |= S_008C04_NUM_CLAUSE_TEMP_GPRS(num_temp_gprs);
1233 r600_pipe_state_add_reg(rstate, R_008C04_SQ_GPR_RESOURCE_MGMT_1, tmp, 0xFFFFFFFF, NULL);
1234
1235 tmp = 0;
1236 tmp |= S_008C08_NUM_GS_GPRS(num_gs_gprs);
1237 tmp |= S_008C08_NUM_ES_GPRS(num_es_gprs);
1238 r600_pipe_state_add_reg(rstate, R_008C08_SQ_GPR_RESOURCE_MGMT_2, tmp, 0xFFFFFFFF, NULL);
1239
1240 tmp = 0;
1241 tmp |= S_008C0C_NUM_HS_GPRS(num_hs_gprs);
1242 tmp |= S_008C0C_NUM_LS_GPRS(num_ls_gprs);
1243 r600_pipe_state_add_reg(rstate, R_008C0C_SQ_GPR_RESOURCE_MGMT_3, tmp, 0xFFFFFFFF, NULL);
1244
1245 tmp = 0;
1246 tmp |= S_008C18_NUM_PS_THREADS(num_ps_threads);
1247 tmp |= S_008C18_NUM_VS_THREADS(num_vs_threads);
1248 tmp |= S_008C18_NUM_GS_THREADS(num_gs_threads);
1249 tmp |= S_008C18_NUM_ES_THREADS(num_es_threads);
1250 r600_pipe_state_add_reg(rstate, R_008C18_SQ_THREAD_RESOURCE_MGMT_1, tmp, 0xFFFFFFFF, NULL);
1251
1252 tmp = 0;
1253 tmp |= S_008C1C_NUM_HS_THREADS(num_hs_threads);
1254 tmp |= S_008C1C_NUM_LS_THREADS(num_ls_threads);
1255 r600_pipe_state_add_reg(rstate, R_008C1C_SQ_THREAD_RESOURCE_MGMT_2, tmp, 0xFFFFFFFF, NULL);
1256
1257 tmp = 0;
1258 tmp |= S_008C20_NUM_PS_STACK_ENTRIES(num_ps_stack_entries);
1259 tmp |= S_008C20_NUM_VS_STACK_ENTRIES(num_vs_stack_entries);
1260 r600_pipe_state_add_reg(rstate, R_008C20_SQ_STACK_RESOURCE_MGMT_1, tmp, 0xFFFFFFFF, NULL);
1261
1262 tmp = 0;
1263 tmp |= S_008C24_NUM_GS_STACK_ENTRIES(num_gs_stack_entries);
1264 tmp |= S_008C24_NUM_ES_STACK_ENTRIES(num_es_stack_entries);
1265 r600_pipe_state_add_reg(rstate, R_008C24_SQ_STACK_RESOURCE_MGMT_2, tmp, 0xFFFFFFFF, NULL);
1266
1267 tmp = 0;
1268 tmp |= S_008C28_NUM_HS_STACK_ENTRIES(num_hs_stack_entries);
1269 tmp |= S_008C28_NUM_LS_STACK_ENTRIES(num_ls_stack_entries);
1270 r600_pipe_state_add_reg(rstate, R_008C28_SQ_STACK_RESOURCE_MGMT_3, tmp, 0xFFFFFFFF, NULL);
1271
1272 r600_pipe_state_add_reg(rstate, R_009100_SPI_CONFIG_CNTL, 0x0, 0xFFFFFFFF, NULL);
1273 r600_pipe_state_add_reg(rstate, R_00913C_SPI_CONFIG_CNTL_1, S_00913C_VTX_DONE_DELAY(4), 0xFFFFFFFF, NULL);
1274
1275 // r600_pipe_state_add_reg(rstate, R_028350_SX_MISC, 0x0, 0xFFFFFFFF, NULL);
1276
1277 // r600_pipe_state_add_reg(rstate, R_008D8C_SQ_DYN_GPR_CNTL_PS_FLUSH_REQ, 0x0, 0xFFFFFFFF, NULL);
1278 r600_pipe_state_add_reg(rstate, R_028A48_PA_SC_MODE_CNTL_0, 0x0, 0xFFFFFFFF, NULL);
1279 r600_pipe_state_add_reg(rstate, R_028A4C_PA_SC_MODE_CNTL_1, 0x0, 0xFFFFFFFF, NULL);
1280
1281 r600_pipe_state_add_reg(rstate, R_028900_SQ_ESGS_RING_ITEMSIZE, 0x0, 0xFFFFFFFF, NULL);
1282 r600_pipe_state_add_reg(rstate, R_028904_SQ_GSVS_RING_ITEMSIZE, 0x0, 0xFFFFFFFF, NULL);
1283 r600_pipe_state_add_reg(rstate, R_028908_SQ_ESTMP_RING_ITEMSIZE, 0x0, 0xFFFFFFFF, NULL);
1284 r600_pipe_state_add_reg(rstate, R_02890C_SQ_GSTMP_RING_ITEMSIZE, 0x0, 0xFFFFFFFF, NULL);
1285 r600_pipe_state_add_reg(rstate, R_028910_SQ_VSTMP_RING_ITEMSIZE, 0x0, 0xFFFFFFFF, NULL);
1286 r600_pipe_state_add_reg(rstate, R_028914_SQ_PSTMP_RING_ITEMSIZE, 0x0, 0xFFFFFFFF, NULL);
1287
1288 r600_pipe_state_add_reg(rstate, R_02891C_SQ_GS_VERT_ITEMSIZE, 0x0, 0xFFFFFFFF, NULL);
1289 r600_pipe_state_add_reg(rstate, R_028920_SQ_GS_VERT_ITEMSIZE_1, 0x0, 0xFFFFFFFF, NULL);
1290 r600_pipe_state_add_reg(rstate, R_028924_SQ_GS_VERT_ITEMSIZE_2, 0x0, 0xFFFFFFFF, NULL);
1291 r600_pipe_state_add_reg(rstate, R_028928_SQ_GS_VERT_ITEMSIZE_3, 0x0, 0xFFFFFFFF, NULL);
1292
1293 r600_pipe_state_add_reg(rstate, R_028A10_VGT_OUTPUT_PATH_CNTL, 0x0, 0xFFFFFFFF, NULL);
1294 r600_pipe_state_add_reg(rstate, R_028A14_VGT_HOS_CNTL, 0x0, 0xFFFFFFFF, NULL);
1295 r600_pipe_state_add_reg(rstate, R_028A18_VGT_HOS_MAX_TESS_LEVEL, 0x0, 0xFFFFFFFF, NULL);
1296 r600_pipe_state_add_reg(rstate, R_028A1C_VGT_HOS_MIN_TESS_LEVEL, 0x0, 0xFFFFFFFF, NULL);
1297 r600_pipe_state_add_reg(rstate, R_028A20_VGT_HOS_REUSE_DEPTH, 0x0, 0xFFFFFFFF, NULL);
1298 r600_pipe_state_add_reg(rstate, R_028A24_VGT_GROUP_PRIM_TYPE, 0x0, 0xFFFFFFFF, NULL);
1299 r600_pipe_state_add_reg(rstate, R_028A28_VGT_GROUP_FIRST_DECR, 0x0, 0xFFFFFFFF, NULL);
1300 r600_pipe_state_add_reg(rstate, R_028A2C_VGT_GROUP_DECR, 0x0, 0xFFFFFFFF, NULL);
1301 r600_pipe_state_add_reg(rstate, R_028A30_VGT_GROUP_VECT_0_CNTL, 0x0, 0xFFFFFFFF, NULL);
1302 r600_pipe_state_add_reg(rstate, R_028A34_VGT_GROUP_VECT_1_CNTL, 0x0, 0xFFFFFFFF, NULL);
1303 r600_pipe_state_add_reg(rstate, R_028A38_VGT_GROUP_VECT_0_FMT_CNTL, 0x0, 0xFFFFFFFF, NULL);
1304 r600_pipe_state_add_reg(rstate, R_028A3C_VGT_GROUP_VECT_1_FMT_CNTL, 0x0, 0xFFFFFFFF, NULL);
1305 r600_pipe_state_add_reg(rstate, R_028A40_VGT_GS_MODE, 0x0, 0xFFFFFFFF, NULL);
1306 r600_pipe_state_add_reg(rstate, R_028B94_VGT_STRMOUT_CONFIG, 0x0, 0xFFFFFFFF, NULL);
1307 r600_pipe_state_add_reg(rstate, R_028B98_VGT_STRMOUT_BUFFER_CONFIG, 0x0, 0xFFFFFFFF, NULL);
1308 r600_pipe_state_add_reg(rstate, R_028AB4_VGT_REUSE_OFF, 0x00000000, 0xFFFFFFFF, NULL);
1309 r600_pipe_state_add_reg(rstate, R_028AB8_VGT_VTX_CNT_EN, 0x0, 0xFFFFFFFF, NULL);
1310 r600_pipe_state_add_reg(rstate, R_008A14_PA_CL_ENHANCE, (3 << 1) | 1, 0xFFFFFFFF, NULL);
1311
1312 r600_pipe_state_add_reg(rstate, R_028380_SQ_VTX_SEMANTIC_0, 0x0, 0xFFFFFFFF, NULL);
1313 r600_pipe_state_add_reg(rstate, R_028384_SQ_VTX_SEMANTIC_1, 0x0, 0xFFFFFFFF, NULL);
1314 r600_pipe_state_add_reg(rstate, R_028388_SQ_VTX_SEMANTIC_2, 0x0, 0xFFFFFFFF, NULL);
1315 r600_pipe_state_add_reg(rstate, R_02838C_SQ_VTX_SEMANTIC_3, 0x0, 0xFFFFFFFF, NULL);
1316 r600_pipe_state_add_reg(rstate, R_028390_SQ_VTX_SEMANTIC_4, 0x0, 0xFFFFFFFF, NULL);
1317 r600_pipe_state_add_reg(rstate, R_028394_SQ_VTX_SEMANTIC_5, 0x0, 0xFFFFFFFF, NULL);
1318 r600_pipe_state_add_reg(rstate, R_028398_SQ_VTX_SEMANTIC_6, 0x0, 0xFFFFFFFF, NULL);
1319 r600_pipe_state_add_reg(rstate, R_02839C_SQ_VTX_SEMANTIC_7, 0x0, 0xFFFFFFFF, NULL);
1320 r600_pipe_state_add_reg(rstate, R_0283A0_SQ_VTX_SEMANTIC_8, 0x0, 0xFFFFFFFF, NULL);
1321 r600_pipe_state_add_reg(rstate, R_0283A4_SQ_VTX_SEMANTIC_9, 0x0, 0xFFFFFFFF, NULL);
1322 r600_pipe_state_add_reg(rstate, R_0283A8_SQ_VTX_SEMANTIC_10, 0x0, 0xFFFFFFFF, NULL);
1323 r600_pipe_state_add_reg(rstate, R_0283AC_SQ_VTX_SEMANTIC_11, 0x0, 0xFFFFFFFF, NULL);
1324 r600_pipe_state_add_reg(rstate, R_0283B0_SQ_VTX_SEMANTIC_12, 0x0, 0xFFFFFFFF, NULL);
1325 r600_pipe_state_add_reg(rstate, R_0283B4_SQ_VTX_SEMANTIC_13, 0x0, 0xFFFFFFFF, NULL);
1326 r600_pipe_state_add_reg(rstate, R_0283B8_SQ_VTX_SEMANTIC_14, 0x0, 0xFFFFFFFF, NULL);
1327 r600_pipe_state_add_reg(rstate, R_0283BC_SQ_VTX_SEMANTIC_15, 0x0, 0xFFFFFFFF, NULL);
1328 r600_pipe_state_add_reg(rstate, R_0283C0_SQ_VTX_SEMANTIC_16, 0x0, 0xFFFFFFFF, NULL);
1329 r600_pipe_state_add_reg(rstate, R_0283C4_SQ_VTX_SEMANTIC_17, 0x0, 0xFFFFFFFF, NULL);
1330 r600_pipe_state_add_reg(rstate, R_0283C8_SQ_VTX_SEMANTIC_18, 0x0, 0xFFFFFFFF, NULL);
1331 r600_pipe_state_add_reg(rstate, R_0283CC_SQ_VTX_SEMANTIC_19, 0x0, 0xFFFFFFFF, NULL);
1332 r600_pipe_state_add_reg(rstate, R_0283D0_SQ_VTX_SEMANTIC_20, 0x0, 0xFFFFFFFF, NULL);
1333 r600_pipe_state_add_reg(rstate, R_0283D4_SQ_VTX_SEMANTIC_21, 0x0, 0xFFFFFFFF, NULL);
1334 r600_pipe_state_add_reg(rstate, R_0283D8_SQ_VTX_SEMANTIC_22, 0x0, 0xFFFFFFFF, NULL);
1335 r600_pipe_state_add_reg(rstate, R_0283DC_SQ_VTX_SEMANTIC_23, 0x0, 0xFFFFFFFF, NULL);
1336 r600_pipe_state_add_reg(rstate, R_0283E0_SQ_VTX_SEMANTIC_24, 0x0, 0xFFFFFFFF, NULL);
1337 r600_pipe_state_add_reg(rstate, R_0283E4_SQ_VTX_SEMANTIC_25, 0x0, 0xFFFFFFFF, NULL);
1338 r600_pipe_state_add_reg(rstate, R_0283E8_SQ_VTX_SEMANTIC_26, 0x0, 0xFFFFFFFF, NULL);
1339 r600_pipe_state_add_reg(rstate, R_0283EC_SQ_VTX_SEMANTIC_27, 0x0, 0xFFFFFFFF, NULL);
1340 r600_pipe_state_add_reg(rstate, R_0283F0_SQ_VTX_SEMANTIC_28, 0x0, 0xFFFFFFFF, NULL);
1341 r600_pipe_state_add_reg(rstate, R_0283F4_SQ_VTX_SEMANTIC_29, 0x0, 0xFFFFFFFF, NULL);
1342 r600_pipe_state_add_reg(rstate, R_0283F8_SQ_VTX_SEMANTIC_30, 0x0, 0xFFFFFFFF, NULL);
1343 r600_pipe_state_add_reg(rstate, R_0283FC_SQ_VTX_SEMANTIC_31, 0x0, 0xFFFFFFFF, NULL);
1344
1345 r600_pipe_state_add_reg(rstate, R_028810_PA_CL_CLIP_CNTL,
1346 0x0, 0xFFFFFFFF, NULL);
1347
1348 r600_context_pipe_state_set(&rctx->ctx, rstate);
1349 }
1350
1351 int r600_conv_pipe_prim(unsigned pprim, unsigned *prim);
1352 void evergreen_draw(struct pipe_context *ctx, const struct pipe_draw_info *info)
1353 {
1354 struct r600_pipe_context *rctx = (struct r600_pipe_context *)ctx;
1355 struct r600_pipe_state *rstate;
1356 struct r600_resource *rbuffer;
1357 unsigned i, j, offset, prim;
1358 u32 vgt_dma_index_type, vgt_draw_initiator, mask;
1359 struct pipe_vertex_buffer *vertex_buffer;
1360 struct r600_draw rdraw;
1361 struct r600_pipe_state vgt;
1362 struct r600_drawl draw;
1363
1364 if (rctx->any_user_vbs) {
1365 r600_upload_user_buffers(rctx);
1366 rctx->any_user_vbs = FALSE;
1367 }
1368
1369 memset(&draw, 0, sizeof(struct r600_drawl));
1370 draw.ctx = ctx;
1371 draw.mode = info->mode;
1372 draw.start = info->start;
1373 draw.count = info->count;
1374 if (info->indexed && rctx->index_buffer.buffer) {
1375 draw.start += rctx->index_buffer.offset / rctx->index_buffer.index_size;
1376 draw.min_index = info->min_index;
1377 draw.max_index = info->max_index;
1378 draw.index_bias = info->index_bias;
1379
1380 r600_translate_index_buffer(rctx, &rctx->index_buffer.buffer,
1381 &rctx->index_buffer.index_size,
1382 &draw.start,
1383 info->count);
1384
1385 draw.index_size = rctx->index_buffer.index_size;
1386 pipe_resource_reference(&draw.index_buffer, rctx->index_buffer.buffer);
1387 draw.index_buffer_offset = draw.start * draw.index_size;
1388 draw.start = 0;
1389 r600_upload_index_buffer(rctx, &draw);
1390 } else {
1391 draw.index_size = 0;
1392 draw.index_buffer = NULL;
1393 draw.min_index = info->min_index;
1394 draw.max_index = info->max_index;
1395 draw.index_bias = info->start;
1396 }
1397
1398 switch (draw.index_size) {
1399 case 2:
1400 vgt_draw_initiator = 0;
1401 vgt_dma_index_type = 0;
1402 break;
1403 case 4:
1404 vgt_draw_initiator = 0;
1405 vgt_dma_index_type = 1;
1406 break;
1407 case 0:
1408 vgt_draw_initiator = 2;
1409 vgt_dma_index_type = 0;
1410 break;
1411 default:
1412 R600_ERR("unsupported index size %d\n", draw.index_size);
1413 return;
1414 }
1415 if (r600_conv_pipe_prim(draw.mode, &prim))
1416 return;
1417
1418 /* rebuild vertex shader if input format changed */
1419 if (r600_pipe_shader_update(&rctx->context, rctx->vs_shader))
1420 return;
1421 if (r600_pipe_shader_update(&rctx->context, rctx->ps_shader))
1422 return;
1423
1424 for (i = 0 ; i < rctx->vertex_elements->count; i++) {
1425 uint32_t word3, word2;
1426 uint32_t format;
1427 rstate = &rctx->vs_resource[i];
1428
1429 rstate->id = R600_PIPE_STATE_RESOURCE;
1430 rstate->nregs = 0;
1431
1432 j = rctx->vertex_elements->elements[i].vertex_buffer_index;
1433 vertex_buffer = &rctx->vertex_buffer[j];
1434 rbuffer = (struct r600_resource*)vertex_buffer->buffer;
1435 offset = rctx->vertex_elements->elements[i].src_offset +
1436 vertex_buffer->buffer_offset +
1437 r600_bo_offset(rbuffer->bo);
1438
1439 format = r600_translate_vertex_data_type(rctx->vertex_elements->elements[i].src_format);
1440
1441 word2 = format | S_030008_STRIDE(vertex_buffer->stride);
1442
1443 word3 = r600_translate_vertex_data_swizzle(rctx->vertex_elements->elements[i].src_format);
1444
1445 r600_pipe_state_add_reg(rstate, R_030000_RESOURCE0_WORD0, offset, 0xFFFFFFFF, rbuffer->bo);
1446 r600_pipe_state_add_reg(rstate, R_030004_RESOURCE0_WORD1, rbuffer->size - offset - 1, 0xFFFFFFFF, NULL);
1447 r600_pipe_state_add_reg(rstate, R_030008_RESOURCE0_WORD2, word2, 0xFFFFFFFF, NULL);
1448 r600_pipe_state_add_reg(rstate, R_03000C_RESOURCE0_WORD3, word3, 0xFFFFFFFF, NULL);
1449 r600_pipe_state_add_reg(rstate, R_030010_RESOURCE0_WORD4, 0x00000000, 0xFFFFFFFF, NULL);
1450 r600_pipe_state_add_reg(rstate, R_030014_RESOURCE0_WORD5, 0x00000000, 0xFFFFFFFF, NULL);
1451 r600_pipe_state_add_reg(rstate, R_030018_RESOURCE0_WORD6, 0x00000000, 0xFFFFFFFF, NULL);
1452 r600_pipe_state_add_reg(rstate, R_03001C_RESOURCE0_WORD7, 0xC0000000, 0xFFFFFFFF, NULL);
1453 evergreen_vs_resource_set(&rctx->ctx, rstate, i);
1454 }
1455
1456 mask = 0;
1457 for (int i = 0; i < rctx->framebuffer.nr_cbufs; i++) {
1458 mask |= (0xF << (i * 4));
1459 }
1460
1461 vgt.id = R600_PIPE_STATE_VGT;
1462 vgt.nregs = 0;
1463 r600_pipe_state_add_reg(&vgt, R_008958_VGT_PRIMITIVE_TYPE, prim, 0xFFFFFFFF, NULL);
1464 r600_pipe_state_add_reg(&vgt, R_028408_VGT_INDX_OFFSET, draw.index_bias, 0xFFFFFFFF, NULL);
1465 r600_pipe_state_add_reg(&vgt, R_028238_CB_TARGET_MASK, rctx->cb_target_mask & mask, 0xFFFFFFFF, NULL);
1466 r600_pipe_state_add_reg(&vgt, R_028400_VGT_MAX_VTX_INDX, draw.max_index, 0xFFFFFFFF, NULL);
1467 r600_pipe_state_add_reg(&vgt, R_028404_VGT_MIN_VTX_INDX, draw.min_index, 0xFFFFFFFF, NULL);
1468 r600_pipe_state_add_reg(&vgt, R_03CFF0_SQ_VTX_BASE_VTX_LOC, 0, 0xFFFFFFFF, NULL);
1469 r600_pipe_state_add_reg(&vgt, R_03CFF4_SQ_VTX_START_INST_LOC, 0, 0xFFFFFFFF, NULL);
1470
1471 if (rctx->rasterizer && rctx->framebuffer.zsbuf) {
1472 float offset_units = rctx->rasterizer->offset_units;
1473 unsigned offset_db_fmt_cntl = 0, depth;
1474
1475 switch (rctx->framebuffer.zsbuf->texture->format) {
1476 case PIPE_FORMAT_Z24X8_UNORM:
1477 case PIPE_FORMAT_Z24_UNORM_S8_USCALED:
1478 depth = -24;
1479 offset_units *= 2.0f;
1480 break;
1481 case PIPE_FORMAT_Z32_FLOAT:
1482 depth = -23;
1483 offset_units *= 1.0f;
1484 offset_db_fmt_cntl |= S_028B78_POLY_OFFSET_DB_IS_FLOAT_FMT(1);
1485 break;
1486 case PIPE_FORMAT_Z16_UNORM:
1487 depth = -16;
1488 offset_units *= 4.0f;
1489 break;
1490 default:
1491 return;
1492 }
1493 offset_db_fmt_cntl |= S_028B78_POLY_OFFSET_NEG_NUM_DB_BITS(depth);
1494 r600_pipe_state_add_reg(&vgt,
1495 R_028B80_PA_SU_POLY_OFFSET_FRONT_SCALE,
1496 fui(rctx->rasterizer->offset_scale), 0xFFFFFFFF, NULL);
1497 r600_pipe_state_add_reg(&vgt,
1498 R_028B84_PA_SU_POLY_OFFSET_FRONT_OFFSET,
1499 fui(offset_units), 0xFFFFFFFF, NULL);
1500 r600_pipe_state_add_reg(&vgt,
1501 R_028B88_PA_SU_POLY_OFFSET_BACK_SCALE,
1502 fui(rctx->rasterizer->offset_scale), 0xFFFFFFFF, NULL);
1503 r600_pipe_state_add_reg(&vgt,
1504 R_028B8C_PA_SU_POLY_OFFSET_BACK_OFFSET,
1505 fui(offset_units), 0xFFFFFFFF, NULL);
1506 r600_pipe_state_add_reg(&vgt,
1507 R_028B78_PA_SU_POLY_OFFSET_DB_FMT_CNTL,
1508 offset_db_fmt_cntl, 0xFFFFFFFF, NULL);
1509 }
1510 r600_context_pipe_state_set(&rctx->ctx, &vgt);
1511
1512 rdraw.vgt_num_indices = draw.count;
1513 rdraw.vgt_num_instances = 1;
1514 rdraw.vgt_index_type = vgt_dma_index_type;
1515 rdraw.vgt_draw_initiator = vgt_draw_initiator;
1516 rdraw.indices = NULL;
1517 if (draw.index_buffer) {
1518 rbuffer = (struct r600_resource*)draw.index_buffer;
1519 rdraw.indices = rbuffer->bo;
1520 rdraw.indices_bo_offset = draw.index_buffer_offset;
1521 }
1522 evergreen_context_draw(&rctx->ctx, &rdraw);
1523
1524 pipe_resource_reference(&draw.index_buffer, NULL);
1525 }
1526
1527 void evergreen_pipe_shader_ps(struct pipe_context *ctx, struct r600_pipe_shader *shader)
1528 {
1529 struct r600_pipe_context *rctx = (struct r600_pipe_context *)ctx;
1530 struct r600_pipe_state *rstate = &shader->rstate;
1531 struct r600_shader *rshader = &shader->shader;
1532 unsigned i, tmp, exports_ps, num_cout, spi_ps_in_control_0, spi_input_z;
1533 boolean have_pos = FALSE, have_face = FALSE;
1534
1535 /* clear previous register */
1536 rstate->nregs = 0;
1537
1538 for (i = 0; i < rshader->ninput; i++) {
1539 tmp = S_028644_SEMANTIC(r600_find_vs_semantic_index(&rctx->vs_shader->shader, rshader, i));
1540 if (rshader->input[i].name == TGSI_SEMANTIC_POSITION)
1541 have_pos = TRUE;
1542 if (rshader->input[i].name == TGSI_SEMANTIC_COLOR ||
1543 rshader->input[i].name == TGSI_SEMANTIC_BCOLOR ||
1544 rshader->input[i].name == TGSI_SEMANTIC_POSITION) {
1545 tmp |= S_028644_FLAT_SHADE(rshader->flat_shade);
1546 }
1547 if (rshader->input[i].name == TGSI_SEMANTIC_FACE)
1548 have_face = TRUE;
1549 if (rshader->input[i].name == TGSI_SEMANTIC_GENERIC &&
1550 rctx->sprite_coord_enable & (1 << rshader->input[i].sid)) {
1551 tmp |= S_028644_PT_SPRITE_TEX(1);
1552 }
1553 r600_pipe_state_add_reg(rstate, R_028644_SPI_PS_INPUT_CNTL_0 + i * 4, tmp, 0xFFFFFFFF, NULL);
1554 }
1555 for (i = 0; i < rshader->noutput; i++) {
1556 if (rshader->output[i].name == TGSI_SEMANTIC_POSITION)
1557 r600_pipe_state_add_reg(rstate,
1558 R_02880C_DB_SHADER_CONTROL,
1559 S_02880C_Z_EXPORT_ENABLE(1),
1560 S_02880C_Z_EXPORT_ENABLE(1), NULL);
1561 }
1562
1563 exports_ps = 0;
1564 num_cout = 0;
1565 for (i = 0; i < rshader->noutput; i++) {
1566 if (rshader->output[i].name == TGSI_SEMANTIC_POSITION)
1567 exports_ps |= 1;
1568 else if (rshader->output[i].name == TGSI_SEMANTIC_COLOR) {
1569 num_cout++;
1570 }
1571 }
1572 exports_ps |= S_02884C_EXPORT_COLORS(num_cout);
1573 if (!exports_ps) {
1574 /* always at least export 1 component per pixel */
1575 exports_ps = 2;
1576 }
1577
1578 spi_ps_in_control_0 = S_0286CC_NUM_INTERP(rshader->ninput) |
1579 S_0286CC_PERSP_GRADIENT_ENA(1);
1580 spi_input_z = 0;
1581 if (have_pos) {
1582 spi_ps_in_control_0 |= S_0286CC_POSITION_ENA(1);
1583 spi_input_z |= 1;
1584 }
1585 r600_pipe_state_add_reg(rstate, R_0286CC_SPI_PS_IN_CONTROL_0,
1586 spi_ps_in_control_0, 0xFFFFFFFF, NULL);
1587 r600_pipe_state_add_reg(rstate, R_0286D0_SPI_PS_IN_CONTROL_1,
1588 S_0286D0_FRONT_FACE_ENA(have_face), 0xFFFFFFFF, NULL);
1589 r600_pipe_state_add_reg(rstate, R_0286D8_SPI_INPUT_Z, spi_input_z, 0xFFFFFFFF, NULL);
1590 r600_pipe_state_add_reg(rstate,
1591 R_028840_SQ_PGM_START_PS,
1592 (r600_bo_offset(shader->bo)) >> 8, 0xFFFFFFFF, shader->bo);
1593 r600_pipe_state_add_reg(rstate,
1594 R_028844_SQ_PGM_RESOURCES_PS,
1595 S_028844_NUM_GPRS(rshader->bc.ngpr) |
1596 S_028844_PRIME_CACHE_ON_DRAW(1) |
1597 S_028844_STACK_SIZE(rshader->bc.nstack),
1598 0xFFFFFFFF, NULL);
1599 r600_pipe_state_add_reg(rstate,
1600 R_028848_SQ_PGM_RESOURCES_2_PS,
1601 0x0, 0xFFFFFFFF, NULL);
1602 r600_pipe_state_add_reg(rstate,
1603 R_02884C_SQ_PGM_EXPORTS_PS,
1604 exports_ps, 0xFFFFFFFF, NULL);
1605 r600_pipe_state_add_reg(rstate,
1606 R_0286E0_SPI_BARYC_CNTL,
1607 S_0286E0_PERSP_CENTROID_ENA(1) |
1608 S_0286E0_LINEAR_CENTROID_ENA(1),
1609 0xFFFFFFFF, NULL);
1610
1611 if (rshader->uses_kill) {
1612 /* only set some bits here, the other bits are set in the dsa state */
1613 r600_pipe_state_add_reg(rstate,
1614 R_02880C_DB_SHADER_CONTROL,
1615 S_02880C_KILL_ENABLE(1),
1616 S_02880C_KILL_ENABLE(1), NULL);
1617 }
1618
1619 r600_pipe_state_add_reg(rstate,
1620 R_03A200_SQ_LOOP_CONST_0, 0x01000FFF,
1621 0xFFFFFFFF, NULL);
1622 }
1623
1624 void evergreen_pipe_shader_vs(struct pipe_context *ctx, struct r600_pipe_shader *shader)
1625 {
1626 struct r600_pipe_state *rstate = &shader->rstate;
1627 struct r600_shader *rshader = &shader->shader;
1628 unsigned spi_vs_out_id[10];
1629 unsigned i, tmp;
1630
1631 /* clear previous register */
1632 rstate->nregs = 0;
1633
1634 /* so far never got proper semantic id from tgsi */
1635 for (i = 0; i < 10; i++) {
1636 spi_vs_out_id[i] = 0;
1637 }
1638 for (i = 0; i < 32; i++) {
1639 tmp = i << ((i & 3) * 8);
1640 spi_vs_out_id[i / 4] |= tmp;
1641 }
1642 for (i = 0; i < 10; i++) {
1643 r600_pipe_state_add_reg(rstate,
1644 R_02861C_SPI_VS_OUT_ID_0 + i * 4,
1645 spi_vs_out_id[i], 0xFFFFFFFF, NULL);
1646 }
1647
1648 r600_pipe_state_add_reg(rstate,
1649 R_0286C4_SPI_VS_OUT_CONFIG,
1650 S_0286C4_VS_EXPORT_COUNT(rshader->noutput - 2),
1651 0xFFFFFFFF, NULL);
1652 r600_pipe_state_add_reg(rstate,
1653 R_028860_SQ_PGM_RESOURCES_VS,
1654 S_028860_NUM_GPRS(rshader->bc.ngpr) |
1655 S_028860_STACK_SIZE(rshader->bc.nstack),
1656 0xFFFFFFFF, NULL);
1657 r600_pipe_state_add_reg(rstate,
1658 R_028864_SQ_PGM_RESOURCES_2_VS,
1659 0x0, 0xFFFFFFFF, NULL);
1660 r600_pipe_state_add_reg(rstate,
1661 R_0288A8_SQ_PGM_RESOURCES_FS,
1662 0x00000000, 0xFFFFFFFF, NULL);
1663 r600_pipe_state_add_reg(rstate,
1664 R_02885C_SQ_PGM_START_VS,
1665 (r600_bo_offset(shader->bo)) >> 8, 0xFFFFFFFF, shader->bo);
1666 r600_pipe_state_add_reg(rstate,
1667 R_0288A4_SQ_PGM_START_FS,
1668 (r600_bo_offset(shader->bo)) >> 8, 0xFFFFFFFF, shader->bo);
1669
1670 r600_pipe_state_add_reg(rstate,
1671 R_03A200_SQ_LOOP_CONST_0 + (32 * 4), 0x01000FFF,
1672 0xFFFFFFFF, NULL);
1673 }
1674
1675 void *evergreen_create_db_flush_dsa(struct r600_pipe_context *rctx)
1676 {
1677 struct pipe_depth_stencil_alpha_state dsa;
1678 struct r600_pipe_state *rstate;
1679
1680 memset(&dsa, 0, sizeof(dsa));
1681
1682 rstate = rctx->context.create_depth_stencil_alpha_state(&rctx->context, &dsa);
1683 r600_pipe_state_add_reg(rstate,
1684 R_02880C_DB_SHADER_CONTROL,
1685 0x0,
1686 S_02880C_DUAL_EXPORT_ENABLE(1), NULL);
1687 r600_pipe_state_add_reg(rstate,
1688 R_028000_DB_RENDER_CONTROL,
1689 S_028000_DEPTH_COPY_ENABLE(1) |
1690 S_028000_STENCIL_COPY_ENABLE(1) |
1691 S_028000_COPY_CENTROID(1),
1692 S_028000_DEPTH_COPY_ENABLE(1) |
1693 S_028000_STENCIL_COPY_ENABLE(1) |
1694 S_028000_COPY_CENTROID(1), NULL);
1695 return rstate;
1696 }