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r600g: set round_mode to truncate and get rid of tgsi_f2i on evergreen
[mesa.git] / src / gallium / drivers / r600 / evergreen_state.c
1 /*
2 * Copyright 2010 Jerome Glisse <glisse@freedesktop.org>
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * on the rights to use, copy, modify, merge, publish, distribute, sub
8 * license, and/or sell copies of the Software, and to permit persons to whom
9 * the Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
13 * Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHOR(S) AND/OR THEIR SUPPLIERS BE LIABLE FOR ANY CLAIM,
19 * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
20 * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
21 * USE OR OTHER DEALINGS IN THE SOFTWARE.
22 */
23
24 /* TODO:
25 * - fix mask for depth control & cull for query
26 */
27 #include <stdio.h>
28 #include <errno.h>
29 #include "pipe/p_defines.h"
30 #include "pipe/p_state.h"
31 #include "pipe/p_context.h"
32 #include "tgsi/tgsi_scan.h"
33 #include "tgsi/tgsi_parse.h"
34 #include "tgsi/tgsi_util.h"
35 #include "util/u_blitter.h"
36 #include "util/u_double_list.h"
37 #include "util/u_transfer.h"
38 #include "util/u_surface.h"
39 #include "util/u_pack_color.h"
40 #include "util/u_memory.h"
41 #include "util/u_inlines.h"
42 #include "util/u_framebuffer.h"
43 #include "pipebuffer/pb_buffer.h"
44 #include "r600.h"
45 #include "evergreend.h"
46 #include "r600_resource.h"
47 #include "r600_shader.h"
48 #include "r600_pipe.h"
49 #include "r600_formats.h"
50
51 static uint32_t r600_translate_blend_function(int blend_func)
52 {
53 switch (blend_func) {
54 case PIPE_BLEND_ADD:
55 return V_028780_COMB_DST_PLUS_SRC;
56 case PIPE_BLEND_SUBTRACT:
57 return V_028780_COMB_SRC_MINUS_DST;
58 case PIPE_BLEND_REVERSE_SUBTRACT:
59 return V_028780_COMB_DST_MINUS_SRC;
60 case PIPE_BLEND_MIN:
61 return V_028780_COMB_MIN_DST_SRC;
62 case PIPE_BLEND_MAX:
63 return V_028780_COMB_MAX_DST_SRC;
64 default:
65 R600_ERR("Unknown blend function %d\n", blend_func);
66 assert(0);
67 break;
68 }
69 return 0;
70 }
71
72 static uint32_t r600_translate_blend_factor(int blend_fact)
73 {
74 switch (blend_fact) {
75 case PIPE_BLENDFACTOR_ONE:
76 return V_028780_BLEND_ONE;
77 case PIPE_BLENDFACTOR_SRC_COLOR:
78 return V_028780_BLEND_SRC_COLOR;
79 case PIPE_BLENDFACTOR_SRC_ALPHA:
80 return V_028780_BLEND_SRC_ALPHA;
81 case PIPE_BLENDFACTOR_DST_ALPHA:
82 return V_028780_BLEND_DST_ALPHA;
83 case PIPE_BLENDFACTOR_DST_COLOR:
84 return V_028780_BLEND_DST_COLOR;
85 case PIPE_BLENDFACTOR_SRC_ALPHA_SATURATE:
86 return V_028780_BLEND_SRC_ALPHA_SATURATE;
87 case PIPE_BLENDFACTOR_CONST_COLOR:
88 return V_028780_BLEND_CONST_COLOR;
89 case PIPE_BLENDFACTOR_CONST_ALPHA:
90 return V_028780_BLEND_CONST_ALPHA;
91 case PIPE_BLENDFACTOR_ZERO:
92 return V_028780_BLEND_ZERO;
93 case PIPE_BLENDFACTOR_INV_SRC_COLOR:
94 return V_028780_BLEND_ONE_MINUS_SRC_COLOR;
95 case PIPE_BLENDFACTOR_INV_SRC_ALPHA:
96 return V_028780_BLEND_ONE_MINUS_SRC_ALPHA;
97 case PIPE_BLENDFACTOR_INV_DST_ALPHA:
98 return V_028780_BLEND_ONE_MINUS_DST_ALPHA;
99 case PIPE_BLENDFACTOR_INV_DST_COLOR:
100 return V_028780_BLEND_ONE_MINUS_DST_COLOR;
101 case PIPE_BLENDFACTOR_INV_CONST_COLOR:
102 return V_028780_BLEND_ONE_MINUS_CONST_COLOR;
103 case PIPE_BLENDFACTOR_INV_CONST_ALPHA:
104 return V_028780_BLEND_ONE_MINUS_CONST_ALPHA;
105 case PIPE_BLENDFACTOR_SRC1_COLOR:
106 return V_028780_BLEND_SRC1_COLOR;
107 case PIPE_BLENDFACTOR_SRC1_ALPHA:
108 return V_028780_BLEND_SRC1_ALPHA;
109 case PIPE_BLENDFACTOR_INV_SRC1_COLOR:
110 return V_028780_BLEND_INV_SRC1_COLOR;
111 case PIPE_BLENDFACTOR_INV_SRC1_ALPHA:
112 return V_028780_BLEND_INV_SRC1_ALPHA;
113 default:
114 R600_ERR("Bad blend factor %d not supported!\n", blend_fact);
115 assert(0);
116 break;
117 }
118 return 0;
119 }
120
121 static uint32_t r600_translate_stencil_op(int s_op)
122 {
123 switch (s_op) {
124 case PIPE_STENCIL_OP_KEEP:
125 return V_028800_STENCIL_KEEP;
126 case PIPE_STENCIL_OP_ZERO:
127 return V_028800_STENCIL_ZERO;
128 case PIPE_STENCIL_OP_REPLACE:
129 return V_028800_STENCIL_REPLACE;
130 case PIPE_STENCIL_OP_INCR:
131 return V_028800_STENCIL_INCR;
132 case PIPE_STENCIL_OP_DECR:
133 return V_028800_STENCIL_DECR;
134 case PIPE_STENCIL_OP_INCR_WRAP:
135 return V_028800_STENCIL_INCR_WRAP;
136 case PIPE_STENCIL_OP_DECR_WRAP:
137 return V_028800_STENCIL_DECR_WRAP;
138 case PIPE_STENCIL_OP_INVERT:
139 return V_028800_STENCIL_INVERT;
140 default:
141 R600_ERR("Unknown stencil op %d", s_op);
142 assert(0);
143 break;
144 }
145 return 0;
146 }
147
148 static uint32_t r600_translate_fill(uint32_t func)
149 {
150 switch(func) {
151 case PIPE_POLYGON_MODE_FILL:
152 return 2;
153 case PIPE_POLYGON_MODE_LINE:
154 return 1;
155 case PIPE_POLYGON_MODE_POINT:
156 return 0;
157 default:
158 assert(0);
159 return 0;
160 }
161 }
162
163 /* translates straight */
164 static uint32_t r600_translate_ds_func(int func)
165 {
166 return func;
167 }
168
169 static unsigned r600_tex_wrap(unsigned wrap)
170 {
171 switch (wrap) {
172 default:
173 case PIPE_TEX_WRAP_REPEAT:
174 return V_03C000_SQ_TEX_WRAP;
175 case PIPE_TEX_WRAP_CLAMP:
176 return V_03C000_SQ_TEX_CLAMP_HALF_BORDER;
177 case PIPE_TEX_WRAP_CLAMP_TO_EDGE:
178 return V_03C000_SQ_TEX_CLAMP_LAST_TEXEL;
179 case PIPE_TEX_WRAP_CLAMP_TO_BORDER:
180 return V_03C000_SQ_TEX_CLAMP_BORDER;
181 case PIPE_TEX_WRAP_MIRROR_REPEAT:
182 return V_03C000_SQ_TEX_MIRROR;
183 case PIPE_TEX_WRAP_MIRROR_CLAMP:
184 return V_03C000_SQ_TEX_MIRROR_ONCE_HALF_BORDER;
185 case PIPE_TEX_WRAP_MIRROR_CLAMP_TO_EDGE:
186 return V_03C000_SQ_TEX_MIRROR_ONCE_LAST_TEXEL;
187 case PIPE_TEX_WRAP_MIRROR_CLAMP_TO_BORDER:
188 return V_03C000_SQ_TEX_MIRROR_ONCE_BORDER;
189 }
190 }
191
192 static unsigned r600_tex_filter(unsigned filter)
193 {
194 switch (filter) {
195 default:
196 case PIPE_TEX_FILTER_NEAREST:
197 return V_03C000_SQ_TEX_XY_FILTER_POINT;
198 case PIPE_TEX_FILTER_LINEAR:
199 return V_03C000_SQ_TEX_XY_FILTER_BILINEAR;
200 }
201 }
202
203 static unsigned r600_tex_mipfilter(unsigned filter)
204 {
205 switch (filter) {
206 case PIPE_TEX_MIPFILTER_NEAREST:
207 return V_03C000_SQ_TEX_Z_FILTER_POINT;
208 case PIPE_TEX_MIPFILTER_LINEAR:
209 return V_03C000_SQ_TEX_Z_FILTER_LINEAR;
210 default:
211 case PIPE_TEX_MIPFILTER_NONE:
212 return V_03C000_SQ_TEX_Z_FILTER_NONE;
213 }
214 }
215
216 static unsigned r600_tex_compare(unsigned compare)
217 {
218 switch (compare) {
219 default:
220 case PIPE_FUNC_NEVER:
221 return V_03C000_SQ_TEX_DEPTH_COMPARE_NEVER;
222 case PIPE_FUNC_LESS:
223 return V_03C000_SQ_TEX_DEPTH_COMPARE_LESS;
224 case PIPE_FUNC_EQUAL:
225 return V_03C000_SQ_TEX_DEPTH_COMPARE_EQUAL;
226 case PIPE_FUNC_LEQUAL:
227 return V_03C000_SQ_TEX_DEPTH_COMPARE_LESSEQUAL;
228 case PIPE_FUNC_GREATER:
229 return V_03C000_SQ_TEX_DEPTH_COMPARE_GREATER;
230 case PIPE_FUNC_NOTEQUAL:
231 return V_03C000_SQ_TEX_DEPTH_COMPARE_NOTEQUAL;
232 case PIPE_FUNC_GEQUAL:
233 return V_03C000_SQ_TEX_DEPTH_COMPARE_GREATEREQUAL;
234 case PIPE_FUNC_ALWAYS:
235 return V_03C000_SQ_TEX_DEPTH_COMPARE_ALWAYS;
236 }
237 }
238
239 static unsigned r600_tex_dim(unsigned dim)
240 {
241 switch (dim) {
242 default:
243 case PIPE_TEXTURE_1D:
244 return V_030000_SQ_TEX_DIM_1D;
245 case PIPE_TEXTURE_1D_ARRAY:
246 return V_030000_SQ_TEX_DIM_1D_ARRAY;
247 case PIPE_TEXTURE_2D:
248 case PIPE_TEXTURE_RECT:
249 return V_030000_SQ_TEX_DIM_2D;
250 case PIPE_TEXTURE_2D_ARRAY:
251 return V_030000_SQ_TEX_DIM_2D_ARRAY;
252 case PIPE_TEXTURE_3D:
253 return V_030000_SQ_TEX_DIM_3D;
254 case PIPE_TEXTURE_CUBE:
255 return V_030000_SQ_TEX_DIM_CUBEMAP;
256 }
257 }
258
259 static uint32_t r600_translate_dbformat(enum pipe_format format)
260 {
261 switch (format) {
262 case PIPE_FORMAT_Z16_UNORM:
263 return V_028040_Z_16;
264 case PIPE_FORMAT_Z24X8_UNORM:
265 case PIPE_FORMAT_Z24_UNORM_S8_UINT:
266 return V_028040_Z_24;
267 case PIPE_FORMAT_Z32_FLOAT:
268 case PIPE_FORMAT_Z32_FLOAT_S8X24_UINT:
269 return V_028040_Z_32_FLOAT;
270 default:
271 return ~0U;
272 }
273 }
274
275 static uint32_t r600_translate_colorswap(enum pipe_format format)
276 {
277 switch (format) {
278 /* 8-bit buffers. */
279 case PIPE_FORMAT_L4A4_UNORM:
280 case PIPE_FORMAT_A4R4_UNORM:
281 return V_028C70_SWAP_ALT;
282
283 case PIPE_FORMAT_A8_UNORM:
284 case PIPE_FORMAT_A8_UINT:
285 case PIPE_FORMAT_A8_SINT:
286 case PIPE_FORMAT_R4A4_UNORM:
287 return V_028C70_SWAP_ALT_REV;
288 case PIPE_FORMAT_I8_UNORM:
289 case PIPE_FORMAT_L8_UNORM:
290 case PIPE_FORMAT_I8_UINT:
291 case PIPE_FORMAT_I8_SINT:
292 case PIPE_FORMAT_L8_UINT:
293 case PIPE_FORMAT_L8_SINT:
294 case PIPE_FORMAT_L8_SRGB:
295 case PIPE_FORMAT_R8_UNORM:
296 case PIPE_FORMAT_R8_SNORM:
297 case PIPE_FORMAT_R8_UINT:
298 case PIPE_FORMAT_R8_SINT:
299 return V_028C70_SWAP_STD;
300
301 /* 16-bit buffers. */
302 case PIPE_FORMAT_B5G6R5_UNORM:
303 return V_028C70_SWAP_STD_REV;
304
305 case PIPE_FORMAT_B5G5R5A1_UNORM:
306 case PIPE_FORMAT_B5G5R5X1_UNORM:
307 return V_028C70_SWAP_ALT;
308
309 case PIPE_FORMAT_B4G4R4A4_UNORM:
310 case PIPE_FORMAT_B4G4R4X4_UNORM:
311 return V_028C70_SWAP_ALT;
312
313 case PIPE_FORMAT_Z16_UNORM:
314 return V_028C70_SWAP_STD;
315
316 case PIPE_FORMAT_L8A8_UNORM:
317 case PIPE_FORMAT_L8A8_UINT:
318 case PIPE_FORMAT_L8A8_SINT:
319 case PIPE_FORMAT_L8A8_SRGB:
320 return V_028C70_SWAP_ALT;
321 case PIPE_FORMAT_R8G8_UNORM:
322 case PIPE_FORMAT_R8G8_UINT:
323 case PIPE_FORMAT_R8G8_SINT:
324 return V_028C70_SWAP_STD;
325
326 case PIPE_FORMAT_R16_UNORM:
327 case PIPE_FORMAT_R16_UINT:
328 case PIPE_FORMAT_R16_SINT:
329 case PIPE_FORMAT_R16_FLOAT:
330 return V_028C70_SWAP_STD;
331
332 /* 32-bit buffers. */
333 case PIPE_FORMAT_A8B8G8R8_SRGB:
334 return V_028C70_SWAP_STD_REV;
335 case PIPE_FORMAT_B8G8R8A8_SRGB:
336 return V_028C70_SWAP_ALT;
337
338 case PIPE_FORMAT_B8G8R8A8_UNORM:
339 case PIPE_FORMAT_B8G8R8X8_UNORM:
340 return V_028C70_SWAP_ALT;
341
342 case PIPE_FORMAT_A8R8G8B8_UNORM:
343 case PIPE_FORMAT_X8R8G8B8_UNORM:
344 return V_028C70_SWAP_ALT_REV;
345 case PIPE_FORMAT_R8G8B8A8_SNORM:
346 case PIPE_FORMAT_R8G8B8A8_UNORM:
347 case PIPE_FORMAT_R8G8B8A8_SSCALED:
348 case PIPE_FORMAT_R8G8B8A8_USCALED:
349 case PIPE_FORMAT_R8G8B8A8_SINT:
350 case PIPE_FORMAT_R8G8B8A8_UINT:
351 case PIPE_FORMAT_R8G8B8X8_UNORM:
352 return V_028C70_SWAP_STD;
353
354 case PIPE_FORMAT_A8B8G8R8_UNORM:
355 case PIPE_FORMAT_X8B8G8R8_UNORM:
356 /* case PIPE_FORMAT_R8SG8SB8UX8U_NORM: */
357 return V_028C70_SWAP_STD_REV;
358
359 case PIPE_FORMAT_Z24X8_UNORM:
360 case PIPE_FORMAT_Z24_UNORM_S8_UINT:
361 return V_028C70_SWAP_STD;
362
363 case PIPE_FORMAT_X8Z24_UNORM:
364 case PIPE_FORMAT_S8_UINT_Z24_UNORM:
365 return V_028C70_SWAP_STD;
366
367 case PIPE_FORMAT_R10G10B10A2_UNORM:
368 case PIPE_FORMAT_R10G10B10X2_SNORM:
369 case PIPE_FORMAT_R10SG10SB10SA2U_NORM:
370 return V_028C70_SWAP_STD;
371
372 case PIPE_FORMAT_B10G10R10A2_UNORM:
373 case PIPE_FORMAT_B10G10R10A2_UINT:
374 return V_028C70_SWAP_ALT;
375
376 case PIPE_FORMAT_R11G11B10_FLOAT:
377 case PIPE_FORMAT_R32_FLOAT:
378 case PIPE_FORMAT_R32_UINT:
379 case PIPE_FORMAT_R32_SINT:
380 case PIPE_FORMAT_Z32_FLOAT:
381 case PIPE_FORMAT_R16G16_FLOAT:
382 case PIPE_FORMAT_R16G16_UNORM:
383 case PIPE_FORMAT_R16G16_UINT:
384 case PIPE_FORMAT_R16G16_SINT:
385 return V_028C70_SWAP_STD;
386
387 /* 64-bit buffers. */
388 case PIPE_FORMAT_R32G32_FLOAT:
389 case PIPE_FORMAT_R32G32_UINT:
390 case PIPE_FORMAT_R32G32_SINT:
391 case PIPE_FORMAT_R16G16B16A16_UNORM:
392 case PIPE_FORMAT_R16G16B16A16_SNORM:
393 case PIPE_FORMAT_R16G16B16A16_USCALED:
394 case PIPE_FORMAT_R16G16B16A16_SSCALED:
395 case PIPE_FORMAT_R16G16B16A16_UINT:
396 case PIPE_FORMAT_R16G16B16A16_SINT:
397 case PIPE_FORMAT_R16G16B16A16_FLOAT:
398 case PIPE_FORMAT_Z32_FLOAT_S8X24_UINT:
399
400 /* 128-bit buffers. */
401 case PIPE_FORMAT_R32G32B32A32_FLOAT:
402 case PIPE_FORMAT_R32G32B32A32_SNORM:
403 case PIPE_FORMAT_R32G32B32A32_UNORM:
404 case PIPE_FORMAT_R32G32B32A32_SSCALED:
405 case PIPE_FORMAT_R32G32B32A32_USCALED:
406 case PIPE_FORMAT_R32G32B32A32_SINT:
407 case PIPE_FORMAT_R32G32B32A32_UINT:
408 return V_028C70_SWAP_STD;
409 default:
410 R600_ERR("unsupported colorswap format %d\n", format);
411 return ~0U;
412 }
413 return ~0U;
414 }
415
416 static uint32_t r600_translate_colorformat(enum pipe_format format)
417 {
418 switch (format) {
419 /* 8-bit buffers. */
420 case PIPE_FORMAT_L4A4_UNORM:
421 case PIPE_FORMAT_R4A4_UNORM:
422 case PIPE_FORMAT_A4R4_UNORM:
423 return V_028C70_COLOR_4_4;
424
425 case PIPE_FORMAT_A8_UNORM:
426 case PIPE_FORMAT_A8_UINT:
427 case PIPE_FORMAT_A8_SINT:
428 case PIPE_FORMAT_I8_UNORM:
429 case PIPE_FORMAT_I8_UINT:
430 case PIPE_FORMAT_I8_SINT:
431 case PIPE_FORMAT_L8_UNORM:
432 case PIPE_FORMAT_L8_UINT:
433 case PIPE_FORMAT_L8_SINT:
434 case PIPE_FORMAT_L8_SRGB:
435 case PIPE_FORMAT_R8_UNORM:
436 case PIPE_FORMAT_R8_SNORM:
437 case PIPE_FORMAT_R8_UINT:
438 case PIPE_FORMAT_R8_SINT:
439 return V_028C70_COLOR_8;
440
441 /* 16-bit buffers. */
442 case PIPE_FORMAT_B5G6R5_UNORM:
443 return V_028C70_COLOR_5_6_5;
444
445 case PIPE_FORMAT_B5G5R5A1_UNORM:
446 case PIPE_FORMAT_B5G5R5X1_UNORM:
447 return V_028C70_COLOR_1_5_5_5;
448
449 case PIPE_FORMAT_B4G4R4A4_UNORM:
450 case PIPE_FORMAT_B4G4R4X4_UNORM:
451 return V_028C70_COLOR_4_4_4_4;
452
453 case PIPE_FORMAT_Z16_UNORM:
454 return V_028C70_COLOR_16;
455
456 case PIPE_FORMAT_L8A8_UNORM:
457 case PIPE_FORMAT_L8A8_UINT:
458 case PIPE_FORMAT_L8A8_SINT:
459 case PIPE_FORMAT_L8A8_SRGB:
460 case PIPE_FORMAT_R8G8_UNORM:
461 case PIPE_FORMAT_R8G8_UINT:
462 case PIPE_FORMAT_R8G8_SINT:
463 return V_028C70_COLOR_8_8;
464
465 case PIPE_FORMAT_R16_UNORM:
466 case PIPE_FORMAT_R16_UINT:
467 case PIPE_FORMAT_R16_SINT:
468 return V_028C70_COLOR_16;
469
470 case PIPE_FORMAT_R16_FLOAT:
471 return V_028C70_COLOR_16_FLOAT;
472
473 /* 32-bit buffers. */
474 case PIPE_FORMAT_A8B8G8R8_SRGB:
475 case PIPE_FORMAT_A8B8G8R8_UNORM:
476 case PIPE_FORMAT_A8R8G8B8_UNORM:
477 case PIPE_FORMAT_B8G8R8A8_SRGB:
478 case PIPE_FORMAT_B8G8R8A8_UNORM:
479 case PIPE_FORMAT_B8G8R8X8_UNORM:
480 case PIPE_FORMAT_R8G8B8A8_SNORM:
481 case PIPE_FORMAT_R8G8B8A8_UNORM:
482 case PIPE_FORMAT_R8G8B8X8_UNORM:
483 case PIPE_FORMAT_R8SG8SB8UX8U_NORM:
484 case PIPE_FORMAT_X8B8G8R8_UNORM:
485 case PIPE_FORMAT_X8R8G8B8_UNORM:
486 case PIPE_FORMAT_R8G8B8_UNORM:
487 case PIPE_FORMAT_R8G8B8A8_SSCALED:
488 case PIPE_FORMAT_R8G8B8A8_USCALED:
489 case PIPE_FORMAT_R8G8B8A8_SINT:
490 case PIPE_FORMAT_R8G8B8A8_UINT:
491 return V_028C70_COLOR_8_8_8_8;
492
493 case PIPE_FORMAT_R10G10B10A2_UNORM:
494 case PIPE_FORMAT_R10G10B10X2_SNORM:
495 case PIPE_FORMAT_B10G10R10A2_UNORM:
496 case PIPE_FORMAT_B10G10R10A2_UINT:
497 case PIPE_FORMAT_R10SG10SB10SA2U_NORM:
498 return V_028C70_COLOR_2_10_10_10;
499
500 case PIPE_FORMAT_Z24X8_UNORM:
501 case PIPE_FORMAT_Z24_UNORM_S8_UINT:
502 return V_028C70_COLOR_8_24;
503
504 case PIPE_FORMAT_X8Z24_UNORM:
505 case PIPE_FORMAT_S8_UINT_Z24_UNORM:
506 return V_028C70_COLOR_24_8;
507
508 case PIPE_FORMAT_Z32_FLOAT_S8X24_UINT:
509 return V_028C70_COLOR_X24_8_32_FLOAT;
510
511 case PIPE_FORMAT_R32_UINT:
512 case PIPE_FORMAT_R32_SINT:
513 return V_028C70_COLOR_32;
514
515 case PIPE_FORMAT_R32_FLOAT:
516 case PIPE_FORMAT_Z32_FLOAT:
517 return V_028C70_COLOR_32_FLOAT;
518
519 case PIPE_FORMAT_R16G16_FLOAT:
520 return V_028C70_COLOR_16_16_FLOAT;
521
522 case PIPE_FORMAT_R16G16_SSCALED:
523 case PIPE_FORMAT_R16G16_UNORM:
524 case PIPE_FORMAT_R16G16_UINT:
525 case PIPE_FORMAT_R16G16_SINT:
526 return V_028C70_COLOR_16_16;
527
528 case PIPE_FORMAT_R11G11B10_FLOAT:
529 return V_028C70_COLOR_10_11_11_FLOAT;
530
531 /* 64-bit buffers. */
532 case PIPE_FORMAT_R16G16B16_USCALED:
533 case PIPE_FORMAT_R16G16B16_SSCALED:
534 case PIPE_FORMAT_R16G16B16A16_UINT:
535 case PIPE_FORMAT_R16G16B16A16_SINT:
536 case PIPE_FORMAT_R16G16B16A16_USCALED:
537 case PIPE_FORMAT_R16G16B16A16_SSCALED:
538 case PIPE_FORMAT_R16G16B16A16_UNORM:
539 case PIPE_FORMAT_R16G16B16A16_SNORM:
540 return V_028C70_COLOR_16_16_16_16;
541
542 case PIPE_FORMAT_R16G16B16_FLOAT:
543 case PIPE_FORMAT_R16G16B16A16_FLOAT:
544 return V_028C70_COLOR_16_16_16_16_FLOAT;
545
546 case PIPE_FORMAT_R32G32_FLOAT:
547 return V_028C70_COLOR_32_32_FLOAT;
548
549 case PIPE_FORMAT_R32G32_USCALED:
550 case PIPE_FORMAT_R32G32_SSCALED:
551 case PIPE_FORMAT_R32G32_SINT:
552 case PIPE_FORMAT_R32G32_UINT:
553 return V_028C70_COLOR_32_32;
554
555 /* 96-bit buffers. */
556 case PIPE_FORMAT_R32G32B32_FLOAT:
557 return V_028C70_COLOR_32_32_32_FLOAT;
558
559 /* 128-bit buffers. */
560 case PIPE_FORMAT_R32G32B32A32_SNORM:
561 case PIPE_FORMAT_R32G32B32A32_UNORM:
562 case PIPE_FORMAT_R32G32B32A32_SSCALED:
563 case PIPE_FORMAT_R32G32B32A32_USCALED:
564 case PIPE_FORMAT_R32G32B32A32_SINT:
565 case PIPE_FORMAT_R32G32B32A32_UINT:
566 return V_028C70_COLOR_32_32_32_32;
567 case PIPE_FORMAT_R32G32B32A32_FLOAT:
568 return V_028C70_COLOR_32_32_32_32_FLOAT;
569
570 /* YUV buffers. */
571 case PIPE_FORMAT_UYVY:
572 case PIPE_FORMAT_YUYV:
573 default:
574 return ~0U; /* Unsupported. */
575 }
576 }
577
578 static uint32_t r600_colorformat_endian_swap(uint32_t colorformat)
579 {
580 if (R600_BIG_ENDIAN) {
581 switch(colorformat) {
582 case V_028C70_COLOR_4_4:
583 return ENDIAN_NONE;
584
585 /* 8-bit buffers. */
586 case V_028C70_COLOR_8:
587 return ENDIAN_NONE;
588
589 /* 16-bit buffers. */
590 case V_028C70_COLOR_5_6_5:
591 case V_028C70_COLOR_1_5_5_5:
592 case V_028C70_COLOR_4_4_4_4:
593 case V_028C70_COLOR_16:
594 case V_028C70_COLOR_8_8:
595 return ENDIAN_8IN16;
596
597 /* 32-bit buffers. */
598 case V_028C70_COLOR_8_8_8_8:
599 case V_028C70_COLOR_2_10_10_10:
600 case V_028C70_COLOR_8_24:
601 case V_028C70_COLOR_24_8:
602 case V_028C70_COLOR_32_FLOAT:
603 case V_028C70_COLOR_16_16_FLOAT:
604 case V_028C70_COLOR_16_16:
605 return ENDIAN_8IN32;
606
607 /* 64-bit buffers. */
608 case V_028C70_COLOR_16_16_16_16:
609 case V_028C70_COLOR_16_16_16_16_FLOAT:
610 return ENDIAN_8IN16;
611
612 case V_028C70_COLOR_32_32_FLOAT:
613 case V_028C70_COLOR_32_32:
614 case V_028C70_COLOR_X24_8_32_FLOAT:
615 return ENDIAN_8IN32;
616
617 /* 96-bit buffers. */
618 case V_028C70_COLOR_32_32_32_FLOAT:
619 /* 128-bit buffers. */
620 case V_028C70_COLOR_32_32_32_32_FLOAT:
621 case V_028C70_COLOR_32_32_32_32:
622 return ENDIAN_8IN32;
623 default:
624 return ENDIAN_NONE; /* Unsupported. */
625 }
626 } else {
627 return ENDIAN_NONE;
628 }
629 }
630
631 static bool r600_is_sampler_format_supported(struct pipe_screen *screen, enum pipe_format format)
632 {
633 return r600_translate_texformat(screen, format, NULL, NULL, NULL) != ~0U;
634 }
635
636 static bool r600_is_colorbuffer_format_supported(enum pipe_format format)
637 {
638 return r600_translate_colorformat(format) != ~0U &&
639 r600_translate_colorswap(format) != ~0U;
640 }
641
642 static bool r600_is_zs_format_supported(enum pipe_format format)
643 {
644 return r600_translate_dbformat(format) != ~0U;
645 }
646
647 boolean evergreen_is_format_supported(struct pipe_screen *screen,
648 enum pipe_format format,
649 enum pipe_texture_target target,
650 unsigned sample_count,
651 unsigned usage)
652 {
653 unsigned retval = 0;
654
655 if (target >= PIPE_MAX_TEXTURE_TYPES) {
656 R600_ERR("r600: unsupported texture type %d\n", target);
657 return FALSE;
658 }
659
660 if (!util_format_is_supported(format, usage))
661 return FALSE;
662
663 /* Multisample */
664 if (sample_count > 1)
665 return FALSE;
666
667 if ((usage & PIPE_BIND_SAMPLER_VIEW) &&
668 r600_is_sampler_format_supported(screen, format)) {
669 retval |= PIPE_BIND_SAMPLER_VIEW;
670 }
671
672 if ((usage & (PIPE_BIND_RENDER_TARGET |
673 PIPE_BIND_DISPLAY_TARGET |
674 PIPE_BIND_SCANOUT |
675 PIPE_BIND_SHARED)) &&
676 r600_is_colorbuffer_format_supported(format)) {
677 retval |= usage &
678 (PIPE_BIND_RENDER_TARGET |
679 PIPE_BIND_DISPLAY_TARGET |
680 PIPE_BIND_SCANOUT |
681 PIPE_BIND_SHARED);
682 }
683
684 if ((usage & PIPE_BIND_DEPTH_STENCIL) &&
685 r600_is_zs_format_supported(format)) {
686 retval |= PIPE_BIND_DEPTH_STENCIL;
687 }
688
689 if ((usage & PIPE_BIND_VERTEX_BUFFER) &&
690 r600_is_vertex_format_supported(format)) {
691 retval |= PIPE_BIND_VERTEX_BUFFER;
692 }
693
694 if (usage & PIPE_BIND_TRANSFER_READ)
695 retval |= PIPE_BIND_TRANSFER_READ;
696 if (usage & PIPE_BIND_TRANSFER_WRITE)
697 retval |= PIPE_BIND_TRANSFER_WRITE;
698
699 return retval == usage;
700 }
701
702 static void evergreen_set_blend_color(struct pipe_context *ctx,
703 const struct pipe_blend_color *state)
704 {
705 struct r600_pipe_context *rctx = (struct r600_pipe_context *)ctx;
706 struct r600_pipe_state *rstate = CALLOC_STRUCT(r600_pipe_state);
707
708 if (rstate == NULL)
709 return;
710
711 rstate->id = R600_PIPE_STATE_BLEND_COLOR;
712 r600_pipe_state_add_reg(rstate, R_028414_CB_BLEND_RED, fui(state->color[0]), 0xFFFFFFFF, NULL, 0);
713 r600_pipe_state_add_reg(rstate, R_028418_CB_BLEND_GREEN, fui(state->color[1]), 0xFFFFFFFF, NULL, 0);
714 r600_pipe_state_add_reg(rstate, R_02841C_CB_BLEND_BLUE, fui(state->color[2]), 0xFFFFFFFF, NULL, 0);
715 r600_pipe_state_add_reg(rstate, R_028420_CB_BLEND_ALPHA, fui(state->color[3]), 0xFFFFFFFF, NULL, 0);
716
717 free(rctx->states[R600_PIPE_STATE_BLEND_COLOR]);
718 rctx->states[R600_PIPE_STATE_BLEND_COLOR] = rstate;
719 r600_context_pipe_state_set(&rctx->ctx, rstate);
720 }
721
722 static void *evergreen_create_blend_state(struct pipe_context *ctx,
723 const struct pipe_blend_state *state)
724 {
725 struct r600_pipe_context *rctx = (struct r600_pipe_context *)ctx;
726 struct r600_pipe_blend *blend = CALLOC_STRUCT(r600_pipe_blend);
727 struct r600_pipe_state *rstate;
728 u32 color_control, target_mask;
729 /* FIXME there is more then 8 framebuffer */
730 unsigned blend_cntl[8];
731
732 if (blend == NULL) {
733 return NULL;
734 }
735
736 rstate = &blend->rstate;
737
738 rstate->id = R600_PIPE_STATE_BLEND;
739
740 target_mask = 0;
741 color_control = S_028808_MODE(1);
742 if (state->logicop_enable) {
743 color_control |= (state->logicop_func << 16) | (state->logicop_func << 20);
744 } else {
745 color_control |= (0xcc << 16);
746 }
747 /* we pretend 8 buffer are used, CB_SHADER_MASK will disable unused one */
748 if (state->independent_blend_enable) {
749 for (int i = 0; i < 8; i++) {
750 target_mask |= (state->rt[i].colormask << (4 * i));
751 }
752 } else {
753 for (int i = 0; i < 8; i++) {
754 target_mask |= (state->rt[0].colormask << (4 * i));
755 }
756 }
757 blend->cb_target_mask = target_mask;
758
759 r600_pipe_state_add_reg(rstate, R_028808_CB_COLOR_CONTROL,
760 color_control, 0xFFFFFFFD, NULL, 0);
761
762 if (rctx->chip_class != CAYMAN)
763 r600_pipe_state_add_reg(rstate, R_028C3C_PA_SC_AA_MASK, 0xFFFFFFFF, 0xFFFFFFFF, NULL, 0);
764 else {
765 r600_pipe_state_add_reg(rstate, CM_R_028C38_PA_SC_AA_MASK_X0Y0_X1Y0, 0xFFFFFFFF, 0xFFFFFFFF, NULL, 0);
766 r600_pipe_state_add_reg(rstate, CM_R_028C3C_PA_SC_AA_MASK_X0Y1_X1Y1, 0xFFFFFFFF, 0xFFFFFFFF, NULL, 0);
767 }
768
769 for (int i = 0; i < 8; i++) {
770 /* state->rt entries > 0 only written if independent blending */
771 const int j = state->independent_blend_enable ? i : 0;
772
773 unsigned eqRGB = state->rt[j].rgb_func;
774 unsigned srcRGB = state->rt[j].rgb_src_factor;
775 unsigned dstRGB = state->rt[j].rgb_dst_factor;
776 unsigned eqA = state->rt[j].alpha_func;
777 unsigned srcA = state->rt[j].alpha_src_factor;
778 unsigned dstA = state->rt[j].alpha_dst_factor;
779
780 blend_cntl[i] = 0;
781 if (!state->rt[j].blend_enable)
782 continue;
783
784 blend_cntl[i] |= S_028780_BLEND_CONTROL_ENABLE(1);
785 blend_cntl[i] |= S_028780_COLOR_COMB_FCN(r600_translate_blend_function(eqRGB));
786 blend_cntl[i] |= S_028780_COLOR_SRCBLEND(r600_translate_blend_factor(srcRGB));
787 blend_cntl[i] |= S_028780_COLOR_DESTBLEND(r600_translate_blend_factor(dstRGB));
788
789 if (srcA != srcRGB || dstA != dstRGB || eqA != eqRGB) {
790 blend_cntl[i] |= S_028780_SEPARATE_ALPHA_BLEND(1);
791 blend_cntl[i] |= S_028780_ALPHA_COMB_FCN(r600_translate_blend_function(eqA));
792 blend_cntl[i] |= S_028780_ALPHA_SRCBLEND(r600_translate_blend_factor(srcA));
793 blend_cntl[i] |= S_028780_ALPHA_DESTBLEND(r600_translate_blend_factor(dstA));
794 }
795 }
796 for (int i = 0; i < 8; i++) {
797 r600_pipe_state_add_reg(rstate, R_028780_CB_BLEND0_CONTROL + i * 4, blend_cntl[i], 0xFFFFFFFF, NULL, 0);
798 }
799
800 return rstate;
801 }
802
803 static void *evergreen_create_dsa_state(struct pipe_context *ctx,
804 const struct pipe_depth_stencil_alpha_state *state)
805 {
806 struct r600_pipe_context *rctx = (struct r600_pipe_context *)ctx;
807 struct r600_pipe_dsa *dsa = CALLOC_STRUCT(r600_pipe_dsa);
808 unsigned db_depth_control, alpha_test_control, alpha_ref, db_shader_control;
809 unsigned stencil_ref_mask, stencil_ref_mask_bf, db_render_override, db_render_control;
810 struct r600_pipe_state *rstate;
811
812 if (dsa == NULL) {
813 return NULL;
814 }
815
816 rstate = &dsa->rstate;
817
818 rstate->id = R600_PIPE_STATE_DSA;
819 /* depth TODO some of those db_shader_control field depend on shader adjust mask & add it to shader */
820 db_shader_control = S_02880C_Z_ORDER(V_02880C_EARLY_Z_THEN_LATE_Z);
821 stencil_ref_mask = 0;
822 stencil_ref_mask_bf = 0;
823 db_depth_control = S_028800_Z_ENABLE(state->depth.enabled) |
824 S_028800_Z_WRITE_ENABLE(state->depth.writemask) |
825 S_028800_ZFUNC(state->depth.func);
826
827 /* stencil */
828 if (state->stencil[0].enabled) {
829 db_depth_control |= S_028800_STENCIL_ENABLE(1);
830 db_depth_control |= S_028800_STENCILFUNC(r600_translate_ds_func(state->stencil[0].func));
831 db_depth_control |= S_028800_STENCILFAIL(r600_translate_stencil_op(state->stencil[0].fail_op));
832 db_depth_control |= S_028800_STENCILZPASS(r600_translate_stencil_op(state->stencil[0].zpass_op));
833 db_depth_control |= S_028800_STENCILZFAIL(r600_translate_stencil_op(state->stencil[0].zfail_op));
834
835
836 stencil_ref_mask = S_028430_STENCILMASK(state->stencil[0].valuemask) |
837 S_028430_STENCILWRITEMASK(state->stencil[0].writemask);
838 if (state->stencil[1].enabled) {
839 db_depth_control |= S_028800_BACKFACE_ENABLE(1);
840 db_depth_control |= S_028800_STENCILFUNC_BF(r600_translate_ds_func(state->stencil[1].func));
841 db_depth_control |= S_028800_STENCILFAIL_BF(r600_translate_stencil_op(state->stencil[1].fail_op));
842 db_depth_control |= S_028800_STENCILZPASS_BF(r600_translate_stencil_op(state->stencil[1].zpass_op));
843 db_depth_control |= S_028800_STENCILZFAIL_BF(r600_translate_stencil_op(state->stencil[1].zfail_op));
844 stencil_ref_mask_bf = S_028434_STENCILMASK_BF(state->stencil[1].valuemask) |
845 S_028434_STENCILWRITEMASK_BF(state->stencil[1].writemask);
846 }
847 }
848
849 /* alpha */
850 alpha_test_control = 0;
851 alpha_ref = 0;
852 if (state->alpha.enabled) {
853 alpha_test_control = S_028410_ALPHA_FUNC(state->alpha.func);
854 alpha_test_control |= S_028410_ALPHA_TEST_ENABLE(1);
855 alpha_ref = fui(state->alpha.ref_value);
856 }
857 dsa->alpha_ref = alpha_ref;
858
859 /* misc */
860 db_render_control = 0;
861 db_render_override = S_02800C_FORCE_HIZ_ENABLE(V_02800C_FORCE_DISABLE) |
862 S_02800C_FORCE_HIS_ENABLE0(V_02800C_FORCE_DISABLE) |
863 S_02800C_FORCE_HIS_ENABLE1(V_02800C_FORCE_DISABLE);
864 /* TODO db_render_override depends on query */
865 r600_pipe_state_add_reg(rstate, R_028028_DB_STENCIL_CLEAR, 0x00000000, 0xFFFFFFFF, NULL, 0);
866 r600_pipe_state_add_reg(rstate, R_02802C_DB_DEPTH_CLEAR, 0x3F800000, 0xFFFFFFFF, NULL, 0);
867 r600_pipe_state_add_reg(rstate, R_028410_SX_ALPHA_TEST_CONTROL, alpha_test_control, 0xFFFFFFFF, NULL, 0);
868 r600_pipe_state_add_reg(rstate,
869 R_028430_DB_STENCILREFMASK, stencil_ref_mask,
870 0xFFFFFFFF & C_028430_STENCILREF, NULL, 0);
871 r600_pipe_state_add_reg(rstate,
872 R_028434_DB_STENCILREFMASK_BF, stencil_ref_mask_bf,
873 0xFFFFFFFF & C_028434_STENCILREF_BF, NULL, 0);
874 r600_pipe_state_add_reg(rstate, R_0286DC_SPI_FOG_CNTL, 0x00000000, 0xFFFFFFFF, NULL, 0);
875 r600_pipe_state_add_reg(rstate, R_028800_DB_DEPTH_CONTROL, db_depth_control, 0xFFFFFFFF, NULL, 0);
876 /* The DB_SHADER_CONTROL mask is 0xFFFFFFBC since Z_EXPORT_ENABLE,
877 * STENCIL_EXPORT_ENABLE and KILL_ENABLE are controlled by
878 * evergreen_pipe_shader_ps().*/
879 r600_pipe_state_add_reg(rstate, R_02880C_DB_SHADER_CONTROL, db_shader_control, 0xFFFFFFBC, NULL, 0);
880 r600_pipe_state_add_reg(rstate, R_028000_DB_RENDER_CONTROL, db_render_control, 0xFFFFFFFF, NULL, 0);
881 r600_pipe_state_add_reg(rstate, R_02800C_DB_RENDER_OVERRIDE, db_render_override, 0xFFFFFFFF, NULL, 0);
882 r600_pipe_state_add_reg(rstate, R_028AC0_DB_SRESULTS_COMPARE_STATE0, 0x0, 0xFFFFFFFF, NULL, 0);
883 r600_pipe_state_add_reg(rstate, R_028AC4_DB_SRESULTS_COMPARE_STATE1, 0x0, 0xFFFFFFFF, NULL, 0);
884 r600_pipe_state_add_reg(rstate, R_028AC8_DB_PRELOAD_CONTROL, 0x0, 0xFFFFFFFF, NULL, 0);
885 r600_pipe_state_add_reg(rstate, R_028B70_DB_ALPHA_TO_MASK, 0x0000AA00, 0xFFFFFFFF, NULL, 0);
886
887 return rstate;
888 }
889
890 static void *evergreen_create_rs_state(struct pipe_context *ctx,
891 const struct pipe_rasterizer_state *state)
892 {
893 struct r600_pipe_context *rctx = (struct r600_pipe_context *)ctx;
894 struct r600_pipe_rasterizer *rs = CALLOC_STRUCT(r600_pipe_rasterizer);
895 struct r600_pipe_state *rstate;
896 unsigned tmp;
897 unsigned prov_vtx = 1, polygon_dual_mode;
898 unsigned clip_rule;
899
900 if (rs == NULL) {
901 return NULL;
902 }
903
904 rstate = &rs->rstate;
905 rs->clamp_vertex_color = state->clamp_vertex_color;
906 rs->clamp_fragment_color = state->clamp_fragment_color;
907 rs->flatshade = state->flatshade;
908 rs->sprite_coord_enable = state->sprite_coord_enable;
909 rs->two_side = state->light_twoside;
910 rs->clip_plane_enable = state->clip_plane_enable;
911
912 clip_rule = state->scissor ? 0xAAAA : 0xFFFF;
913
914 /* offset */
915 rs->offset_units = state->offset_units;
916 rs->offset_scale = state->offset_scale * 12.0f;
917
918 rstate->id = R600_PIPE_STATE_RASTERIZER;
919 if (state->flatshade_first)
920 prov_vtx = 0;
921 tmp = S_0286D4_FLAT_SHADE_ENA(state->flatshade);
922 if (state->sprite_coord_enable) {
923 tmp |= S_0286D4_PNT_SPRITE_ENA(1) |
924 S_0286D4_PNT_SPRITE_OVRD_X(2) |
925 S_0286D4_PNT_SPRITE_OVRD_Y(3) |
926 S_0286D4_PNT_SPRITE_OVRD_Z(0) |
927 S_0286D4_PNT_SPRITE_OVRD_W(1);
928 if (state->sprite_coord_mode != PIPE_SPRITE_COORD_UPPER_LEFT) {
929 tmp |= S_0286D4_PNT_SPRITE_TOP_1(1);
930 }
931 }
932 r600_pipe_state_add_reg(rstate, R_0286D4_SPI_INTERP_CONTROL_0, tmp, 0xFFFFFFFF, NULL, 0);
933
934 polygon_dual_mode = (state->fill_front != PIPE_POLYGON_MODE_FILL ||
935 state->fill_back != PIPE_POLYGON_MODE_FILL);
936 r600_pipe_state_add_reg(rstate, R_028814_PA_SU_SC_MODE_CNTL,
937 S_028814_PROVOKING_VTX_LAST(prov_vtx) |
938 S_028814_CULL_FRONT(state->rasterizer_discard || (state->cull_face & PIPE_FACE_FRONT) ? 1 : 0) |
939 S_028814_CULL_BACK(state->rasterizer_discard || (state->cull_face & PIPE_FACE_BACK) ? 1 : 0) |
940 S_028814_FACE(!state->front_ccw) |
941 S_028814_POLY_OFFSET_FRONT_ENABLE(state->offset_tri) |
942 S_028814_POLY_OFFSET_BACK_ENABLE(state->offset_tri) |
943 S_028814_POLY_OFFSET_PARA_ENABLE(state->offset_tri) |
944 S_028814_POLY_MODE(polygon_dual_mode) |
945 S_028814_POLYMODE_FRONT_PTYPE(r600_translate_fill(state->fill_front)) |
946 S_028814_POLYMODE_BACK_PTYPE(r600_translate_fill(state->fill_back)), 0xFFFFFFFF, NULL, 0);
947 r600_pipe_state_add_reg(rstate, R_02881C_PA_CL_VS_OUT_CNTL,
948 S_02881C_USE_VTX_POINT_SIZE(state->point_size_per_vertex),
949 S_02881C_USE_VTX_POINT_SIZE(1), NULL, 0);
950 r600_pipe_state_add_reg(rstate, R_028820_PA_CL_NANINF_CNTL, 0x00000000, 0xFFFFFFFF, NULL, 0);
951 /* point size 12.4 fixed point */
952 tmp = (unsigned)(state->point_size * 8.0);
953 r600_pipe_state_add_reg(rstate, R_028A00_PA_SU_POINT_SIZE, S_028A00_HEIGHT(tmp) | S_028A00_WIDTH(tmp), 0xFFFFFFFF, NULL, 0);
954 r600_pipe_state_add_reg(rstate, R_028A04_PA_SU_POINT_MINMAX, 0x80000000, 0xFFFFFFFF, NULL, 0);
955
956 tmp = (unsigned)state->line_width * 8;
957 r600_pipe_state_add_reg(rstate, R_028A08_PA_SU_LINE_CNTL, S_028A08_WIDTH(tmp), 0xFFFFFFFF, NULL, 0);
958
959 if (state->line_stipple_enable) {
960 r600_pipe_state_add_reg(rstate, R_028A0C_PA_SC_LINE_STIPPLE,
961 S_028A0C_LINE_PATTERN(state->line_stipple_pattern) |
962 S_028A0C_REPEAT_COUNT(state->line_stipple_factor),
963 0x9FFFFFFF, NULL, 0);
964 }
965
966 r600_pipe_state_add_reg(rstate, R_028A48_PA_SC_MODE_CNTL_0,
967 S_028A48_LINE_STIPPLE_ENABLE(state->line_stipple_enable),
968 0xFFFFFFFF, NULL, 0);
969
970 if (rctx->chip_class == CAYMAN) {
971 r600_pipe_state_add_reg(rstate, CM_R_028BDC_PA_SC_LINE_CNTL, 0x00000400, 0xFFFFFFFF, NULL, 0);
972 r600_pipe_state_add_reg(rstate, CM_R_028BE4_PA_SU_VTX_CNTL,
973 S_028C08_PIX_CENTER_HALF(state->gl_rasterization_rules),
974 0xFFFFFFFF, NULL, 0);
975 r600_pipe_state_add_reg(rstate, CM_R_028BE8_PA_CL_GB_VERT_CLIP_ADJ, 0x3F800000, 0xFFFFFFFF, NULL, 0);
976 r600_pipe_state_add_reg(rstate, CM_R_028BEC_PA_CL_GB_VERT_DISC_ADJ, 0x3F800000, 0xFFFFFFFF, NULL, 0);
977 r600_pipe_state_add_reg(rstate, CM_R_028BF0_PA_CL_GB_HORZ_CLIP_ADJ, 0x3F800000, 0xFFFFFFFF, NULL, 0);
978 r600_pipe_state_add_reg(rstate, CM_R_028BF4_PA_CL_GB_HORZ_DISC_ADJ, 0x3F800000, 0xFFFFFFFF, NULL, 0);
979
980
981 } else {
982 r600_pipe_state_add_reg(rstate, R_028C00_PA_SC_LINE_CNTL, 0x00000400, 0xFFFFFFFF, NULL, 0);
983
984 r600_pipe_state_add_reg(rstate, R_028C0C_PA_CL_GB_VERT_CLIP_ADJ, 0x3F800000, 0xFFFFFFFF, NULL, 0);
985 r600_pipe_state_add_reg(rstate, R_028C10_PA_CL_GB_VERT_DISC_ADJ, 0x3F800000, 0xFFFFFFFF, NULL, 0);
986 r600_pipe_state_add_reg(rstate, R_028C14_PA_CL_GB_HORZ_CLIP_ADJ, 0x3F800000, 0xFFFFFFFF, NULL, 0);
987 r600_pipe_state_add_reg(rstate, R_028C18_PA_CL_GB_HORZ_DISC_ADJ, 0x3F800000, 0xFFFFFFFF, NULL, 0);
988
989 r600_pipe_state_add_reg(rstate, R_028C08_PA_SU_VTX_CNTL,
990 S_028C08_PIX_CENTER_HALF(state->gl_rasterization_rules),
991 0xFFFFFFFF, NULL, 0);
992 }
993 r600_pipe_state_add_reg(rstate, R_028B7C_PA_SU_POLY_OFFSET_CLAMP, fui(state->offset_clamp), 0xFFFFFFFF, NULL, 0);
994 r600_pipe_state_add_reg(rstate, R_02820C_PA_SC_CLIPRECT_RULE, clip_rule, 0xFFFFFFFF, NULL, 0);
995 r600_pipe_state_add_reg(rstate, R_028810_PA_CL_CLIP_CNTL,
996 S_028810_PS_UCP_MODE(3) | S_028810_ZCLIP_NEAR_DISABLE(!state->depth_clip) |
997 S_028810_ZCLIP_FAR_DISABLE(!state->depth_clip),
998 S_028810_PS_UCP_MODE(3) | S_028810_ZCLIP_NEAR_DISABLE(1) |
999 S_028810_ZCLIP_FAR_DISABLE(1), NULL, 0);
1000 return rstate;
1001 }
1002
1003 static void *evergreen_create_sampler_state(struct pipe_context *ctx,
1004 const struct pipe_sampler_state *state)
1005 {
1006 struct r600_pipe_state *rstate = CALLOC_STRUCT(r600_pipe_state);
1007 union util_color uc;
1008 unsigned aniso_flag_offset = state->max_anisotropy > 1 ? 2 : 0;
1009
1010 if (rstate == NULL) {
1011 return NULL;
1012 }
1013
1014 rstate->id = R600_PIPE_STATE_SAMPLER;
1015 util_pack_color(state->border_color.f, PIPE_FORMAT_B8G8R8A8_UNORM, &uc);
1016 r600_pipe_state_add_reg_noblock(rstate, R_03C000_SQ_TEX_SAMPLER_WORD0_0,
1017 S_03C000_CLAMP_X(r600_tex_wrap(state->wrap_s)) |
1018 S_03C000_CLAMP_Y(r600_tex_wrap(state->wrap_t)) |
1019 S_03C000_CLAMP_Z(r600_tex_wrap(state->wrap_r)) |
1020 S_03C000_XY_MAG_FILTER(r600_tex_filter(state->mag_img_filter) | aniso_flag_offset) |
1021 S_03C000_XY_MIN_FILTER(r600_tex_filter(state->min_img_filter) | aniso_flag_offset) |
1022 S_03C000_MIP_FILTER(r600_tex_mipfilter(state->min_mip_filter)) |
1023 S_03C000_MAX_ANISO(r600_tex_aniso_filter(state->max_anisotropy)) |
1024 S_03C000_DEPTH_COMPARE_FUNCTION(r600_tex_compare(state->compare_func)) |
1025 S_03C000_BORDER_COLOR_TYPE(uc.ui ? V_03C000_SQ_TEX_BORDER_COLOR_REGISTER : 0), 0xFFFFFFFF, NULL, 0);
1026 r600_pipe_state_add_reg_noblock(rstate, R_03C004_SQ_TEX_SAMPLER_WORD1_0,
1027 S_03C004_MIN_LOD(S_FIXED(CLAMP(state->min_lod, 0, 15), 8)) |
1028 S_03C004_MAX_LOD(S_FIXED(CLAMP(state->max_lod, 0, 15), 8)),
1029 0xFFFFFFFF, NULL, 0);
1030 r600_pipe_state_add_reg_noblock(rstate, R_03C008_SQ_TEX_SAMPLER_WORD2_0,
1031 S_03C008_LOD_BIAS(S_FIXED(CLAMP(state->lod_bias, -16, 16), 8)) |
1032 (state->seamless_cube_map ? 0 : S_03C008_DISABLE_CUBE_WRAP(1)) |
1033 S_03C008_TYPE(1),
1034 0xFFFFFFFF, NULL, 0);
1035
1036 if (uc.ui) {
1037 r600_pipe_state_add_reg_noblock(rstate, R_00A404_TD_PS_SAMPLER0_BORDER_RED, fui(state->border_color.f[0]), 0xFFFFFFFF, NULL, 0);
1038 r600_pipe_state_add_reg_noblock(rstate, R_00A408_TD_PS_SAMPLER0_BORDER_GREEN, fui(state->border_color.f[1]), 0xFFFFFFFF, NULL, 0);
1039 r600_pipe_state_add_reg_noblock(rstate, R_00A40C_TD_PS_SAMPLER0_BORDER_BLUE, fui(state->border_color.f[2]), 0xFFFFFFFF, NULL, 0);
1040 r600_pipe_state_add_reg_noblock(rstate, R_00A410_TD_PS_SAMPLER0_BORDER_ALPHA, fui(state->border_color.f[3]), 0xFFFFFFFF, NULL, 0);
1041 }
1042 return rstate;
1043 }
1044
1045 static struct pipe_sampler_view *evergreen_create_sampler_view(struct pipe_context *ctx,
1046 struct pipe_resource *texture,
1047 const struct pipe_sampler_view *state)
1048 {
1049 struct r600_pipe_sampler_view *view = CALLOC_STRUCT(r600_pipe_sampler_view);
1050 struct r600_pipe_resource_state *rstate;
1051 struct r600_resource_texture *tmp = (struct r600_resource_texture*)texture;
1052 unsigned format, endian;
1053 uint32_t word4 = 0, yuv_format = 0, pitch = 0;
1054 unsigned char swizzle[4], array_mode = 0, tile_type = 0;
1055 unsigned height, depth;
1056
1057 if (view == NULL)
1058 return NULL;
1059 rstate = &view->state;
1060
1061 /* initialize base object */
1062 view->base = *state;
1063 view->base.texture = NULL;
1064 pipe_reference(NULL, &texture->reference);
1065 view->base.texture = texture;
1066 view->base.reference.count = 1;
1067 view->base.context = ctx;
1068
1069 swizzle[0] = state->swizzle_r;
1070 swizzle[1] = state->swizzle_g;
1071 swizzle[2] = state->swizzle_b;
1072 swizzle[3] = state->swizzle_a;
1073
1074 format = r600_translate_texformat(ctx->screen, state->format,
1075 swizzle,
1076 &word4, &yuv_format);
1077 if (format == ~0) {
1078 format = 0;
1079 }
1080
1081 if (tmp->depth && !tmp->is_flushing_texture) {
1082 r600_texture_depth_flush(ctx, texture, TRUE);
1083 tmp = tmp->flushed_depth_texture;
1084 }
1085
1086 endian = r600_colorformat_endian_swap(format);
1087
1088 height = texture->height0;
1089 depth = texture->depth0;
1090
1091 pitch = align(tmp->pitch_in_blocks[0] *
1092 util_format_get_blockwidth(state->format), 8);
1093 array_mode = tmp->array_mode[0];
1094 tile_type = tmp->tile_type;
1095
1096 if (texture->target == PIPE_TEXTURE_1D_ARRAY) {
1097 height = 1;
1098 depth = texture->array_size;
1099 } else if (texture->target == PIPE_TEXTURE_2D_ARRAY) {
1100 depth = texture->array_size;
1101 }
1102
1103 rstate->bo[0] = &tmp->resource;
1104 rstate->bo[1] = &tmp->resource;
1105 rstate->bo_usage[0] = RADEON_USAGE_READ;
1106 rstate->bo_usage[1] = RADEON_USAGE_READ;
1107
1108 rstate->val[0] = (S_030000_DIM(r600_tex_dim(texture->target)) |
1109 S_030000_PITCH((pitch / 8) - 1) |
1110 S_030000_NON_DISP_TILING_ORDER(tile_type) |
1111 S_030000_TEX_WIDTH(texture->width0 - 1));
1112 rstate->val[1] = (S_030004_TEX_HEIGHT(height - 1) |
1113 S_030004_TEX_DEPTH(depth - 1) |
1114 S_030004_ARRAY_MODE(array_mode));
1115 rstate->val[2] = (tmp->offset[0] + r600_resource_va(ctx->screen, texture)) >> 8;
1116 rstate->val[3] = (tmp->offset[1] + r600_resource_va(ctx->screen, texture)) >> 8;
1117 rstate->val[4] = (word4 |
1118 S_030010_SRF_MODE_ALL(V_030010_SRF_MODE_ZERO_CLAMP_MINUS_ONE) |
1119 S_030010_ENDIAN_SWAP(endian) |
1120 S_030010_BASE_LEVEL(state->u.tex.first_level));
1121 rstate->val[5] = (S_030014_LAST_LEVEL(state->u.tex.last_level) |
1122 S_030014_BASE_ARRAY(state->u.tex.first_layer) |
1123 S_030014_LAST_ARRAY(state->u.tex.last_layer));
1124 rstate->val[6] = (S_030018_MAX_ANISO(4 /* max 16 samples */));
1125 rstate->val[7] = (S_03001C_DATA_FORMAT(format) |
1126 S_03001C_TYPE(V_03001C_SQ_TEX_VTX_VALID_TEXTURE));
1127
1128 return &view->base;
1129 }
1130
1131 static void evergreen_set_vs_sampler_view(struct pipe_context *ctx, unsigned count,
1132 struct pipe_sampler_view **views)
1133 {
1134 struct r600_pipe_context *rctx = (struct r600_pipe_context *)ctx;
1135 struct r600_pipe_sampler_view **resource = (struct r600_pipe_sampler_view **)views;
1136
1137 for (int i = 0; i < count; i++) {
1138 if (resource[i]) {
1139 evergreen_context_pipe_state_set_vs_resource(&rctx->ctx, &resource[i]->state,
1140 i + R600_MAX_CONST_BUFFERS);
1141 }
1142 }
1143 }
1144
1145 static void evergreen_set_ps_sampler_view(struct pipe_context *ctx, unsigned count,
1146 struct pipe_sampler_view **views)
1147 {
1148 struct r600_pipe_context *rctx = (struct r600_pipe_context *)ctx;
1149 struct r600_pipe_sampler_view **resource = (struct r600_pipe_sampler_view **)views;
1150 int i;
1151 int has_depth = 0;
1152
1153 for (i = 0; i < count; i++) {
1154 if (&rctx->ps_samplers.views[i]->base != views[i]) {
1155 if (resource[i]) {
1156 if (((struct r600_resource_texture *)resource[i]->base.texture)->depth)
1157 has_depth = 1;
1158 evergreen_context_pipe_state_set_ps_resource(&rctx->ctx, &resource[i]->state,
1159 i + R600_MAX_CONST_BUFFERS);
1160 } else
1161 evergreen_context_pipe_state_set_ps_resource(&rctx->ctx, NULL,
1162 i + R600_MAX_CONST_BUFFERS);
1163
1164 pipe_sampler_view_reference(
1165 (struct pipe_sampler_view **)&rctx->ps_samplers.views[i],
1166 views[i]);
1167 } else {
1168 if (resource[i]) {
1169 if (((struct r600_resource_texture *)resource[i]->base.texture)->depth)
1170 has_depth = 1;
1171 }
1172 }
1173 }
1174 for (i = count; i < NUM_TEX_UNITS; i++) {
1175 if (rctx->ps_samplers.views[i]) {
1176 evergreen_context_pipe_state_set_ps_resource(&rctx->ctx, NULL,
1177 i + R600_MAX_CONST_BUFFERS);
1178 pipe_sampler_view_reference((struct pipe_sampler_view **)&rctx->ps_samplers.views[i], NULL);
1179 }
1180 }
1181 rctx->have_depth_texture = has_depth;
1182 rctx->ps_samplers.n_views = count;
1183 }
1184
1185 static void evergreen_bind_ps_sampler(struct pipe_context *ctx, unsigned count, void **states)
1186 {
1187 struct r600_pipe_context *rctx = (struct r600_pipe_context *)ctx;
1188 struct r600_pipe_state **rstates = (struct r600_pipe_state **)states;
1189
1190
1191 memcpy(rctx->ps_samplers.samplers, states, sizeof(void*) * count);
1192 rctx->ps_samplers.n_samplers = count;
1193
1194 for (int i = 0; i < count; i++) {
1195 evergreen_context_pipe_state_set_ps_sampler(&rctx->ctx, rstates[i], i);
1196 }
1197 }
1198
1199 static void evergreen_bind_vs_sampler(struct pipe_context *ctx, unsigned count, void **states)
1200 {
1201 struct r600_pipe_context *rctx = (struct r600_pipe_context *)ctx;
1202 struct r600_pipe_state **rstates = (struct r600_pipe_state **)states;
1203
1204 for (int i = 0; i < count; i++) {
1205 evergreen_context_pipe_state_set_vs_sampler(&rctx->ctx, rstates[i], i);
1206 }
1207 }
1208
1209 static void evergreen_set_clip_state(struct pipe_context *ctx,
1210 const struct pipe_clip_state *state)
1211 {
1212 struct r600_pipe_context *rctx = (struct r600_pipe_context *)ctx;
1213 struct r600_pipe_state *rstate = CALLOC_STRUCT(r600_pipe_state);
1214 struct pipe_resource *cbuf;
1215
1216 if (rstate == NULL)
1217 return;
1218
1219 rctx->clip = *state;
1220 rstate->id = R600_PIPE_STATE_CLIP;
1221 for (int i = 0; i < 6; i++) {
1222 r600_pipe_state_add_reg(rstate,
1223 R_0285BC_PA_CL_UCP0_X + i * 16,
1224 fui(state->ucp[i][0]), 0xFFFFFFFF, NULL, 0);
1225 r600_pipe_state_add_reg(rstate,
1226 R_0285C0_PA_CL_UCP0_Y + i * 16,
1227 fui(state->ucp[i][1]) , 0xFFFFFFFF, NULL, 0);
1228 r600_pipe_state_add_reg(rstate,
1229 R_0285C4_PA_CL_UCP0_Z + i * 16,
1230 fui(state->ucp[i][2]), 0xFFFFFFFF, NULL, 0);
1231 r600_pipe_state_add_reg(rstate,
1232 R_0285C8_PA_CL_UCP0_W + i * 16,
1233 fui(state->ucp[i][3]), 0xFFFFFFFF, NULL, 0);
1234 }
1235
1236 free(rctx->states[R600_PIPE_STATE_CLIP]);
1237 rctx->states[R600_PIPE_STATE_CLIP] = rstate;
1238 r600_context_pipe_state_set(&rctx->ctx, rstate);
1239
1240 cbuf = pipe_user_buffer_create(ctx->screen,
1241 state->ucp,
1242 4*4*8, /* 8*4 floats */
1243 PIPE_BIND_CONSTANT_BUFFER);
1244 r600_set_constant_buffer(ctx, PIPE_SHADER_VERTEX, 1, cbuf);
1245 pipe_resource_reference(&cbuf, NULL);
1246 }
1247
1248 static void evergreen_set_polygon_stipple(struct pipe_context *ctx,
1249 const struct pipe_poly_stipple *state)
1250 {
1251 }
1252
1253 static void evergreen_set_sample_mask(struct pipe_context *pipe, unsigned sample_mask)
1254 {
1255 }
1256
1257 static void evergreen_set_scissor_state(struct pipe_context *ctx,
1258 const struct pipe_scissor_state *state)
1259 {
1260 struct r600_pipe_context *rctx = (struct r600_pipe_context *)ctx;
1261 struct r600_pipe_state *rstate = CALLOC_STRUCT(r600_pipe_state);
1262 u32 tl, br;
1263
1264 if (rstate == NULL)
1265 return;
1266
1267 rstate->id = R600_PIPE_STATE_SCISSOR;
1268 tl = S_028240_TL_X(state->minx) | S_028240_TL_Y(state->miny);
1269 br = S_028244_BR_X(state->maxx) | S_028244_BR_Y(state->maxy);
1270 r600_pipe_state_add_reg(rstate,
1271 R_028210_PA_SC_CLIPRECT_0_TL, tl,
1272 0xFFFFFFFF, NULL, 0);
1273 r600_pipe_state_add_reg(rstate,
1274 R_028214_PA_SC_CLIPRECT_0_BR, br,
1275 0xFFFFFFFF, NULL, 0);
1276 r600_pipe_state_add_reg(rstate,
1277 R_028218_PA_SC_CLIPRECT_1_TL, tl,
1278 0xFFFFFFFF, NULL, 0);
1279 r600_pipe_state_add_reg(rstate,
1280 R_02821C_PA_SC_CLIPRECT_1_BR, br,
1281 0xFFFFFFFF, NULL, 0);
1282 r600_pipe_state_add_reg(rstate,
1283 R_028220_PA_SC_CLIPRECT_2_TL, tl,
1284 0xFFFFFFFF, NULL, 0);
1285 r600_pipe_state_add_reg(rstate,
1286 R_028224_PA_SC_CLIPRECT_2_BR, br,
1287 0xFFFFFFFF, NULL, 0);
1288 r600_pipe_state_add_reg(rstate,
1289 R_028228_PA_SC_CLIPRECT_3_TL, tl,
1290 0xFFFFFFFF, NULL, 0);
1291 r600_pipe_state_add_reg(rstate,
1292 R_02822C_PA_SC_CLIPRECT_3_BR, br,
1293 0xFFFFFFFF, NULL, 0);
1294
1295 free(rctx->states[R600_PIPE_STATE_SCISSOR]);
1296 rctx->states[R600_PIPE_STATE_SCISSOR] = rstate;
1297 r600_context_pipe_state_set(&rctx->ctx, rstate);
1298 }
1299
1300 static void evergreen_set_stencil_ref(struct pipe_context *ctx,
1301 const struct pipe_stencil_ref *state)
1302 {
1303 struct r600_pipe_context *rctx = (struct r600_pipe_context *)ctx;
1304 struct r600_pipe_state *rstate = CALLOC_STRUCT(r600_pipe_state);
1305 u32 tmp;
1306
1307 if (rstate == NULL)
1308 return;
1309
1310 rctx->stencil_ref = *state;
1311 rstate->id = R600_PIPE_STATE_STENCIL_REF;
1312 tmp = S_028430_STENCILREF(state->ref_value[0]);
1313 r600_pipe_state_add_reg(rstate,
1314 R_028430_DB_STENCILREFMASK, tmp,
1315 ~C_028430_STENCILREF, NULL, 0);
1316 tmp = S_028434_STENCILREF_BF(state->ref_value[1]);
1317 r600_pipe_state_add_reg(rstate,
1318 R_028434_DB_STENCILREFMASK_BF, tmp,
1319 ~C_028434_STENCILREF_BF, NULL, 0);
1320
1321 free(rctx->states[R600_PIPE_STATE_STENCIL_REF]);
1322 rctx->states[R600_PIPE_STATE_STENCIL_REF] = rstate;
1323 r600_context_pipe_state_set(&rctx->ctx, rstate);
1324 }
1325
1326 static void evergreen_set_viewport_state(struct pipe_context *ctx,
1327 const struct pipe_viewport_state *state)
1328 {
1329 struct r600_pipe_context *rctx = (struct r600_pipe_context *)ctx;
1330 struct r600_pipe_state *rstate = CALLOC_STRUCT(r600_pipe_state);
1331
1332 if (rstate == NULL)
1333 return;
1334
1335 rctx->viewport = *state;
1336 rstate->id = R600_PIPE_STATE_VIEWPORT;
1337 r600_pipe_state_add_reg(rstate, R_0282D0_PA_SC_VPORT_ZMIN_0, 0x00000000, 0xFFFFFFFF, NULL, 0);
1338 r600_pipe_state_add_reg(rstate, R_0282D4_PA_SC_VPORT_ZMAX_0, 0x3F800000, 0xFFFFFFFF, NULL, 0);
1339 r600_pipe_state_add_reg(rstate, R_02843C_PA_CL_VPORT_XSCALE_0, fui(state->scale[0]), 0xFFFFFFFF, NULL, 0);
1340 r600_pipe_state_add_reg(rstate, R_028444_PA_CL_VPORT_YSCALE_0, fui(state->scale[1]), 0xFFFFFFFF, NULL, 0);
1341 r600_pipe_state_add_reg(rstate, R_02844C_PA_CL_VPORT_ZSCALE_0, fui(state->scale[2]), 0xFFFFFFFF, NULL, 0);
1342 r600_pipe_state_add_reg(rstate, R_028440_PA_CL_VPORT_XOFFSET_0, fui(state->translate[0]), 0xFFFFFFFF, NULL, 0);
1343 r600_pipe_state_add_reg(rstate, R_028448_PA_CL_VPORT_YOFFSET_0, fui(state->translate[1]), 0xFFFFFFFF, NULL, 0);
1344 r600_pipe_state_add_reg(rstate, R_028450_PA_CL_VPORT_ZOFFSET_0, fui(state->translate[2]), 0xFFFFFFFF, NULL, 0);
1345 r600_pipe_state_add_reg(rstate, R_028818_PA_CL_VTE_CNTL, 0x0000043F, 0xFFFFFFFF, NULL, 0);
1346
1347 free(rctx->states[R600_PIPE_STATE_VIEWPORT]);
1348 rctx->states[R600_PIPE_STATE_VIEWPORT] = rstate;
1349 r600_context_pipe_state_set(&rctx->ctx, rstate);
1350 }
1351
1352 static void evergreen_cb(struct r600_pipe_context *rctx, struct r600_pipe_state *rstate,
1353 const struct pipe_framebuffer_state *state, int cb)
1354 {
1355 struct r600_resource_texture *rtex;
1356 struct r600_surface *surf;
1357 unsigned level = state->cbufs[cb]->u.tex.level;
1358 unsigned pitch, slice;
1359 unsigned color_info;
1360 unsigned format, swap, ntype, endian;
1361 uint64_t offset;
1362 unsigned tile_type;
1363 const struct util_format_description *desc;
1364 int i;
1365 unsigned blend_clamp = 0, blend_bypass = 0;
1366
1367 surf = (struct r600_surface *)state->cbufs[cb];
1368 rtex = (struct r600_resource_texture*)state->cbufs[cb]->texture;
1369
1370 if (rtex->depth)
1371 rctx->have_depth_fb = TRUE;
1372
1373 if (rtex->depth && !rtex->is_flushing_texture) {
1374 r600_texture_depth_flush(&rctx->context, state->cbufs[cb]->texture, TRUE);
1375 rtex = rtex->flushed_depth_texture;
1376 }
1377
1378 /* XXX quite sure for dx10+ hw don't need any offset hacks */
1379 offset = r600_texture_get_offset(rtex,
1380 level, state->cbufs[cb]->u.tex.first_layer);
1381 pitch = rtex->pitch_in_blocks[level] / 8 - 1;
1382 slice = rtex->pitch_in_blocks[level] * surf->aligned_height / 64 - 1;
1383 desc = util_format_description(surf->base.format);
1384 for (i = 0; i < 4; i++) {
1385 if (desc->channel[i].type != UTIL_FORMAT_TYPE_VOID) {
1386 break;
1387 }
1388 }
1389
1390 ntype = V_028C70_NUMBER_UNORM;
1391 if (desc->colorspace == UTIL_FORMAT_COLORSPACE_SRGB)
1392 ntype = V_028C70_NUMBER_SRGB;
1393 else if (desc->channel[i].type == UTIL_FORMAT_TYPE_SIGNED) {
1394 if (desc->channel[i].normalized)
1395 ntype = V_028C70_NUMBER_SNORM;
1396 else if (desc->channel[i].pure_integer)
1397 ntype = V_028C70_NUMBER_SINT;
1398 } else if (desc->channel[i].type == UTIL_FORMAT_TYPE_UNSIGNED) {
1399 if (desc->channel[i].normalized)
1400 ntype = V_028C70_NUMBER_UNORM;
1401 else if (desc->channel[i].pure_integer)
1402 ntype = V_028C70_NUMBER_UINT;
1403 }
1404
1405 format = r600_translate_colorformat(surf->base.format);
1406 swap = r600_translate_colorswap(surf->base.format);
1407 if (rtex->resource.b.b.b.usage == PIPE_USAGE_STAGING) {
1408 endian = ENDIAN_NONE;
1409 } else {
1410 endian = r600_colorformat_endian_swap(format);
1411 }
1412
1413 /* blend clamp should be set for all NORM/SRGB types */
1414 if (ntype == V_028C70_NUMBER_UNORM || ntype == V_028C70_NUMBER_SNORM ||
1415 ntype == V_028C70_NUMBER_SRGB)
1416 blend_clamp = 1;
1417
1418 /* set blend bypass according to docs if SINT/UINT or
1419 8/24 COLOR variants */
1420 if (ntype == V_028C70_NUMBER_UINT || ntype == V_028C70_NUMBER_SINT ||
1421 format == V_028C70_COLOR_8_24 || format == V_028C70_COLOR_24_8 ||
1422 format == V_028C70_COLOR_X24_8_32_FLOAT) {
1423 blend_clamp = 0;
1424 blend_bypass = 1;
1425 }
1426
1427 color_info = S_028C70_FORMAT(format) |
1428 S_028C70_COMP_SWAP(swap) |
1429 S_028C70_ARRAY_MODE(rtex->array_mode[level]) |
1430 S_028C70_BLEND_CLAMP(blend_clamp) |
1431 S_028C70_BLEND_BYPASS(blend_bypass) |
1432 S_028C70_NUMBER_TYPE(ntype) |
1433 S_028C70_ENDIAN(endian);
1434
1435 /* EXPORT_NORM is an optimzation that can be enabled for better
1436 * performance in certain cases.
1437 * EXPORT_NORM can be enabled if:
1438 * - 11-bit or smaller UNORM/SNORM/SRGB
1439 * - 16-bit or smaller FLOAT
1440 */
1441 /* FIXME: This should probably be the same for all CBs if we want
1442 * useful alpha tests. */
1443 if (desc->colorspace != UTIL_FORMAT_COLORSPACE_ZS &&
1444 ((desc->channel[i].size < 12 &&
1445 desc->channel[i].type != UTIL_FORMAT_TYPE_FLOAT &&
1446 ntype != V_028C70_NUMBER_UINT && ntype != V_028C70_NUMBER_SINT) ||
1447 (desc->channel[i].size < 17 &&
1448 desc->channel[i].type == UTIL_FORMAT_TYPE_FLOAT))) {
1449 color_info |= S_028C70_SOURCE_FORMAT(V_028C70_EXPORT_4C_16BPC);
1450 rctx->export_16bpc = true;
1451 } else {
1452 rctx->export_16bpc = false;
1453 }
1454 rctx->alpha_ref_dirty = true;
1455
1456 if (rtex->array_mode[level] > V_028C70_ARRAY_LINEAR_ALIGNED) {
1457 tile_type = rtex->tile_type;
1458 } else /* workaround for linear buffers */
1459 tile_type = 1;
1460
1461 offset += r600_resource_va(rctx->context.screen, state->cbufs[cb]->texture);
1462 offset >>= 8;
1463
1464 /* FIXME handle enabling of CB beyond BASE8 which has different offset */
1465 r600_pipe_state_add_reg(rstate,
1466 R_028C60_CB_COLOR0_BASE + cb * 0x3C,
1467 offset, 0xFFFFFFFF, &rtex->resource, RADEON_USAGE_READWRITE);
1468 r600_pipe_state_add_reg(rstate,
1469 R_028C78_CB_COLOR0_DIM + cb * 0x3C,
1470 0x0, 0xFFFFFFFF, NULL, 0);
1471 r600_pipe_state_add_reg(rstate,
1472 R_028C70_CB_COLOR0_INFO + cb * 0x3C,
1473 color_info, 0xFFFFFFFF, &rtex->resource, RADEON_USAGE_READWRITE);
1474 r600_pipe_state_add_reg(rstate,
1475 R_028C64_CB_COLOR0_PITCH + cb * 0x3C,
1476 S_028C64_PITCH_TILE_MAX(pitch),
1477 0xFFFFFFFF, NULL, 0);
1478 r600_pipe_state_add_reg(rstate,
1479 R_028C68_CB_COLOR0_SLICE + cb * 0x3C,
1480 S_028C68_SLICE_TILE_MAX(slice),
1481 0xFFFFFFFF, NULL, 0);
1482 r600_pipe_state_add_reg(rstate,
1483 R_028C6C_CB_COLOR0_VIEW + cb * 0x3C,
1484 0x00000000, 0xFFFFFFFF, NULL, 0);
1485 r600_pipe_state_add_reg(rstate,
1486 R_028C74_CB_COLOR0_ATTRIB + cb * 0x3C,
1487 S_028C74_NON_DISP_TILING_ORDER(tile_type),
1488 0xFFFFFFFF, &rtex->resource, RADEON_USAGE_READWRITE);
1489 }
1490
1491 static void evergreen_db(struct r600_pipe_context *rctx, struct r600_pipe_state *rstate,
1492 const struct pipe_framebuffer_state *state)
1493 {
1494 struct r600_resource_texture *rtex;
1495 struct r600_surface *surf;
1496 unsigned level, first_layer, pitch, slice, format, array_mode;
1497 uint64_t offset;
1498
1499 if (state->zsbuf == NULL)
1500 return;
1501
1502 surf = (struct r600_surface *)state->zsbuf;
1503 level = surf->base.u.tex.level;
1504 rtex = (struct r600_resource_texture*)surf->base.texture;
1505
1506 /* XXX remove this once tiling is properly supported */
1507 array_mode = rtex->array_mode[level] ? rtex->array_mode[level] :
1508 V_028C70_ARRAY_1D_TILED_THIN1;
1509
1510 first_layer = surf->base.u.tex.first_layer;
1511 offset = r600_texture_get_offset(rtex, level, first_layer);
1512 pitch = rtex->pitch_in_blocks[level] / 8 - 1;
1513 slice = rtex->pitch_in_blocks[level] * surf->aligned_height / 64 - 1;
1514 format = r600_translate_dbformat(rtex->real_format);
1515
1516 offset += r600_resource_va(rctx->context.screen, surf->base.texture);
1517 offset >>= 8;
1518
1519 r600_pipe_state_add_reg(rstate, R_028048_DB_Z_READ_BASE,
1520 offset, 0xFFFFFFFF, &rtex->resource, RADEON_USAGE_READWRITE);
1521 r600_pipe_state_add_reg(rstate, R_028050_DB_Z_WRITE_BASE,
1522 offset, 0xFFFFFFFF, &rtex->resource, RADEON_USAGE_READWRITE);
1523 r600_pipe_state_add_reg(rstate, R_028008_DB_DEPTH_VIEW, 0x00000000, 0xFFFFFFFF, NULL, 0);
1524
1525 if (rtex->stencil) {
1526 uint64_t stencil_offset =
1527 r600_texture_get_offset(rtex->stencil, level, first_layer);
1528
1529 stencil_offset += r600_resource_va(rctx->context.screen, (void*)rtex->stencil);
1530 stencil_offset >>= 8;
1531
1532 r600_pipe_state_add_reg(rstate, R_02804C_DB_STENCIL_READ_BASE,
1533 stencil_offset, 0xFFFFFFFF, &rtex->stencil->resource, RADEON_USAGE_READWRITE);
1534 r600_pipe_state_add_reg(rstate, R_028054_DB_STENCIL_WRITE_BASE,
1535 stencil_offset, 0xFFFFFFFF, &rtex->stencil->resource, RADEON_USAGE_READWRITE);
1536 r600_pipe_state_add_reg(rstate, R_028044_DB_STENCIL_INFO,
1537 1, 0xFFFFFFFF, &rtex->stencil->resource, RADEON_USAGE_READWRITE);
1538 } else {
1539 r600_pipe_state_add_reg(rstate, R_028044_DB_STENCIL_INFO,
1540 0, 0xFFFFFFFF, NULL, RADEON_USAGE_READWRITE);
1541 }
1542
1543 r600_pipe_state_add_reg(rstate, R_028040_DB_Z_INFO,
1544 S_028040_ARRAY_MODE(array_mode) | S_028040_FORMAT(format),
1545 0xFFFFFFFF, &rtex->resource, RADEON_USAGE_READWRITE);
1546 r600_pipe_state_add_reg(rstate, R_028058_DB_DEPTH_SIZE,
1547 S_028058_PITCH_TILE_MAX(pitch),
1548 0xFFFFFFFF, NULL, 0);
1549 r600_pipe_state_add_reg(rstate, R_02805C_DB_DEPTH_SLICE,
1550 S_02805C_SLICE_TILE_MAX(slice),
1551 0xFFFFFFFF, NULL, 0);
1552 }
1553
1554 static void evergreen_set_framebuffer_state(struct pipe_context *ctx,
1555 const struct pipe_framebuffer_state *state)
1556 {
1557 struct r600_pipe_context *rctx = (struct r600_pipe_context *)ctx;
1558 struct r600_pipe_state *rstate = CALLOC_STRUCT(r600_pipe_state);
1559 u32 shader_mask, tl, br, target_mask;
1560 int tl_x, tl_y, br_x, br_y;
1561
1562 if (rstate == NULL)
1563 return;
1564
1565 evergreen_context_flush_dest_caches(&rctx->ctx);
1566 rctx->ctx.num_dest_buffers = state->nr_cbufs;
1567
1568 /* unreference old buffer and reference new one */
1569 rstate->id = R600_PIPE_STATE_FRAMEBUFFER;
1570
1571 util_copy_framebuffer_state(&rctx->framebuffer, state);
1572
1573 /* build states */
1574 rctx->have_depth_fb = 0;
1575 rctx->nr_cbufs = state->nr_cbufs;
1576 for (int i = 0; i < state->nr_cbufs; i++) {
1577 evergreen_cb(rctx, rstate, state, i);
1578 }
1579 if (state->zsbuf) {
1580 evergreen_db(rctx, rstate, state);
1581 rctx->ctx.num_dest_buffers++;
1582 }
1583
1584 target_mask = 0x00000000;
1585 target_mask = 0xFFFFFFFF;
1586 shader_mask = 0;
1587 for (int i = 0; i < state->nr_cbufs; i++) {
1588 target_mask ^= 0xf << (i * 4);
1589 shader_mask |= 0xf << (i * 4);
1590 }
1591 tl_x = 0;
1592 tl_y = 0;
1593 br_x = state->width;
1594 br_y = state->height;
1595 /* EG hw workaround */
1596 if (br_x == 0)
1597 tl_x = 1;
1598 if (br_y == 0)
1599 tl_y = 1;
1600 /* cayman hw workaround */
1601 if (rctx->chip_class == CAYMAN) {
1602 if (br_x == 1 && br_y == 1)
1603 br_x = 2;
1604 }
1605 tl = S_028240_TL_X(tl_x) | S_028240_TL_Y(tl_y);
1606 br = S_028244_BR_X(br_x) | S_028244_BR_Y(br_y);
1607
1608 r600_pipe_state_add_reg(rstate,
1609 R_028240_PA_SC_GENERIC_SCISSOR_TL, tl,
1610 0xFFFFFFFF, NULL, 0);
1611 r600_pipe_state_add_reg(rstate,
1612 R_028244_PA_SC_GENERIC_SCISSOR_BR, br,
1613 0xFFFFFFFF, NULL, 0);
1614 r600_pipe_state_add_reg(rstate,
1615 R_028250_PA_SC_VPORT_SCISSOR_0_TL, tl,
1616 0xFFFFFFFF, NULL, 0);
1617 r600_pipe_state_add_reg(rstate,
1618 R_028254_PA_SC_VPORT_SCISSOR_0_BR, br,
1619 0xFFFFFFFF, NULL, 0);
1620 r600_pipe_state_add_reg(rstate,
1621 R_028030_PA_SC_SCREEN_SCISSOR_TL, tl,
1622 0xFFFFFFFF, NULL, 0);
1623 r600_pipe_state_add_reg(rstate,
1624 R_028034_PA_SC_SCREEN_SCISSOR_BR, br,
1625 0xFFFFFFFF, NULL, 0);
1626 r600_pipe_state_add_reg(rstate,
1627 R_028204_PA_SC_WINDOW_SCISSOR_TL, tl,
1628 0xFFFFFFFF, NULL, 0);
1629 r600_pipe_state_add_reg(rstate,
1630 R_028208_PA_SC_WINDOW_SCISSOR_BR, br,
1631 0xFFFFFFFF, NULL, 0);
1632 r600_pipe_state_add_reg(rstate,
1633 R_028200_PA_SC_WINDOW_OFFSET, 0x00000000,
1634 0xFFFFFFFF, NULL, 0);
1635 r600_pipe_state_add_reg(rstate,
1636 R_028230_PA_SC_EDGERULE, 0xAAAAAAAA,
1637 0xFFFFFFFF, NULL, 0);
1638
1639 r600_pipe_state_add_reg(rstate, R_028238_CB_TARGET_MASK,
1640 0x00000000, target_mask, NULL, 0);
1641 r600_pipe_state_add_reg(rstate, R_02823C_CB_SHADER_MASK,
1642 shader_mask, 0xFFFFFFFF, NULL, 0);
1643
1644
1645 if (rctx->chip_class == CAYMAN) {
1646 r600_pipe_state_add_reg(rstate, CM_R_028BE0_PA_SC_AA_CONFIG,
1647 0x00000000, 0xFFFFFFFF, NULL, 0);
1648 } else {
1649 r600_pipe_state_add_reg(rstate, R_028C04_PA_SC_AA_CONFIG,
1650 0x00000000, 0xFFFFFFFF, NULL, 0);
1651 r600_pipe_state_add_reg(rstate, R_028C1C_PA_SC_AA_SAMPLE_LOCS_MCTX,
1652 0x00000000, 0xFFFFFFFF, NULL, 0);
1653 }
1654
1655 free(rctx->states[R600_PIPE_STATE_FRAMEBUFFER]);
1656 rctx->states[R600_PIPE_STATE_FRAMEBUFFER] = rstate;
1657 r600_context_pipe_state_set(&rctx->ctx, rstate);
1658
1659 if (state->zsbuf) {
1660 evergreen_polygon_offset_update(rctx);
1661 }
1662 }
1663
1664 static void evergreen_texture_barrier(struct pipe_context *ctx)
1665 {
1666 struct r600_pipe_context *rctx = (struct r600_pipe_context *)ctx;
1667
1668 r600_context_flush_all(&rctx->ctx, S_0085F0_TC_ACTION_ENA(1) | S_0085F0_CB_ACTION_ENA(1) |
1669 S_0085F0_CB0_DEST_BASE_ENA(1) | S_0085F0_CB1_DEST_BASE_ENA(1) |
1670 S_0085F0_CB2_DEST_BASE_ENA(1) | S_0085F0_CB3_DEST_BASE_ENA(1) |
1671 S_0085F0_CB4_DEST_BASE_ENA(1) | S_0085F0_CB5_DEST_BASE_ENA(1) |
1672 S_0085F0_CB6_DEST_BASE_ENA(1) | S_0085F0_CB7_DEST_BASE_ENA(1) |
1673 S_0085F0_CB8_DEST_BASE_ENA(1) | S_0085F0_CB9_DEST_BASE_ENA(1) |
1674 S_0085F0_CB10_DEST_BASE_ENA(1) | S_0085F0_CB11_DEST_BASE_ENA(1));
1675 }
1676
1677 void evergreen_init_state_functions(struct r600_pipe_context *rctx)
1678 {
1679 rctx->context.create_blend_state = evergreen_create_blend_state;
1680 rctx->context.create_depth_stencil_alpha_state = evergreen_create_dsa_state;
1681 rctx->context.create_fs_state = r600_create_shader_state;
1682 rctx->context.create_rasterizer_state = evergreen_create_rs_state;
1683 rctx->context.create_sampler_state = evergreen_create_sampler_state;
1684 rctx->context.create_sampler_view = evergreen_create_sampler_view;
1685 rctx->context.create_vertex_elements_state = r600_create_vertex_elements;
1686 rctx->context.create_vs_state = r600_create_shader_state;
1687 rctx->context.bind_blend_state = r600_bind_blend_state;
1688 rctx->context.bind_depth_stencil_alpha_state = r600_bind_dsa_state;
1689 rctx->context.bind_fragment_sampler_states = evergreen_bind_ps_sampler;
1690 rctx->context.bind_fs_state = r600_bind_ps_shader;
1691 rctx->context.bind_rasterizer_state = r600_bind_rs_state;
1692 rctx->context.bind_vertex_elements_state = r600_bind_vertex_elements;
1693 rctx->context.bind_vertex_sampler_states = evergreen_bind_vs_sampler;
1694 rctx->context.bind_vs_state = r600_bind_vs_shader;
1695 rctx->context.delete_blend_state = r600_delete_state;
1696 rctx->context.delete_depth_stencil_alpha_state = r600_delete_state;
1697 rctx->context.delete_fs_state = r600_delete_ps_shader;
1698 rctx->context.delete_rasterizer_state = r600_delete_rs_state;
1699 rctx->context.delete_sampler_state = r600_delete_state;
1700 rctx->context.delete_vertex_elements_state = r600_delete_vertex_element;
1701 rctx->context.delete_vs_state = r600_delete_vs_shader;
1702 rctx->context.set_blend_color = evergreen_set_blend_color;
1703 rctx->context.set_clip_state = evergreen_set_clip_state;
1704 rctx->context.set_constant_buffer = r600_set_constant_buffer;
1705 rctx->context.set_fragment_sampler_views = evergreen_set_ps_sampler_view;
1706 rctx->context.set_framebuffer_state = evergreen_set_framebuffer_state;
1707 rctx->context.set_polygon_stipple = evergreen_set_polygon_stipple;
1708 rctx->context.set_sample_mask = evergreen_set_sample_mask;
1709 rctx->context.set_scissor_state = evergreen_set_scissor_state;
1710 rctx->context.set_stencil_ref = evergreen_set_stencil_ref;
1711 rctx->context.set_vertex_buffers = r600_set_vertex_buffers;
1712 rctx->context.set_index_buffer = r600_set_index_buffer;
1713 rctx->context.set_vertex_sampler_views = evergreen_set_vs_sampler_view;
1714 rctx->context.set_viewport_state = evergreen_set_viewport_state;
1715 rctx->context.sampler_view_destroy = r600_sampler_view_destroy;
1716 rctx->context.redefine_user_buffer = u_default_redefine_user_buffer;
1717 rctx->context.texture_barrier = evergreen_texture_barrier;
1718 rctx->context.create_stream_output_target = r600_create_so_target;
1719 rctx->context.stream_output_target_destroy = r600_so_target_destroy;
1720 rctx->context.set_stream_output_targets = r600_set_so_targets;
1721 }
1722
1723 static void cayman_init_config(struct r600_pipe_context *rctx)
1724 {
1725 struct r600_pipe_state *rstate = &rctx->config;
1726 unsigned tmp;
1727
1728 tmp = 0x00000000;
1729 tmp |= S_008C00_EXPORT_SRC_C(1);
1730 r600_pipe_state_add_reg(rstate, R_008C00_SQ_CONFIG, tmp, 0xFFFFFFFF, NULL, 0);
1731
1732 /* always set the temp clauses */
1733 r600_pipe_state_add_reg(rstate, R_008C04_SQ_GPR_RESOURCE_MGMT_1, S_008C04_NUM_CLAUSE_TEMP_GPRS(4), 0xFFFFFFFF, NULL, 0);
1734 r600_pipe_state_add_reg(rstate, R_008C10_SQ_GLOBAL_GPR_RESOURCE_MGMT_1, 0, 0xFFFFFFFF, NULL, 0);
1735 r600_pipe_state_add_reg(rstate, R_008C14_SQ_GLOBAL_GPR_RESOURCE_MGMT_2, 0, 0xFFFFFFFF, NULL, 0);
1736 r600_pipe_state_add_reg(rstate, R_008D8C_SQ_DYN_GPR_CNTL_PS_FLUSH_REQ, (1 << 8), 0xFFFFFFFF, NULL, 0);
1737
1738 r600_pipe_state_add_reg(rstate, R_028A4C_PA_SC_MODE_CNTL_1, 0x0, 0xFFFFFFFF, NULL, 0);
1739
1740 r600_pipe_state_add_reg(rstate, R_028A10_VGT_OUTPUT_PATH_CNTL, 0x0, 0xFFFFFFFF, NULL, 0);
1741 r600_pipe_state_add_reg(rstate, R_028A14_VGT_HOS_CNTL, 0x0, 0xFFFFFFFF, NULL, 0);
1742 r600_pipe_state_add_reg(rstate, R_028A18_VGT_HOS_MAX_TESS_LEVEL, 0x0, 0xFFFFFFFF, NULL, 0);
1743 r600_pipe_state_add_reg(rstate, R_028A1C_VGT_HOS_MIN_TESS_LEVEL, 0x0, 0xFFFFFFFF, NULL, 0);
1744 r600_pipe_state_add_reg(rstate, R_028A20_VGT_HOS_REUSE_DEPTH, 0x0, 0xFFFFFFFF, NULL, 0);
1745 r600_pipe_state_add_reg(rstate, R_028A24_VGT_GROUP_PRIM_TYPE, 0x0, 0xFFFFFFFF, NULL, 0);
1746 r600_pipe_state_add_reg(rstate, R_028A28_VGT_GROUP_FIRST_DECR, 0x0, 0xFFFFFFFF, NULL, 0);
1747 r600_pipe_state_add_reg(rstate, R_028A2C_VGT_GROUP_DECR, 0x0, 0xFFFFFFFF, NULL, 0);
1748 r600_pipe_state_add_reg(rstate, R_028A30_VGT_GROUP_VECT_0_CNTL, 0x0, 0xFFFFFFFF, NULL, 0);
1749 r600_pipe_state_add_reg(rstate, R_028A34_VGT_GROUP_VECT_1_CNTL, 0x0, 0xFFFFFFFF, NULL, 0);
1750 r600_pipe_state_add_reg(rstate, R_028A38_VGT_GROUP_VECT_0_FMT_CNTL, 0x0, 0xFFFFFFFF, NULL, 0);
1751 r600_pipe_state_add_reg(rstate, R_028A3C_VGT_GROUP_VECT_1_FMT_CNTL, 0x0, 0xFFFFFFFF, NULL, 0);
1752 r600_pipe_state_add_reg(rstate, R_028A40_VGT_GS_MODE, 0x0, 0xFFFFFFFF, NULL, 0);
1753 r600_pipe_state_add_reg(rstate, R_028B94_VGT_STRMOUT_CONFIG, 0x0, 0xFFFFFFFF, NULL, 0);
1754 r600_pipe_state_add_reg(rstate, R_028B98_VGT_STRMOUT_BUFFER_CONFIG, 0x0, 0xFFFFFFFF, NULL, 0);
1755 r600_pipe_state_add_reg(rstate, R_028AA8_IA_MULTI_VGT_PARAM, S_028AA8_SWITCH_ON_EOP(1) | S_028AA8_PARTIAL_VS_WAVE_ON(1) | S_028AA8_PRIMGROUP_SIZE(63), 0xFFFFFFFF, NULL, 0);
1756 r600_pipe_state_add_reg(rstate, R_028AB4_VGT_REUSE_OFF, 0x00000000, 0xFFFFFFFF, NULL, 0);
1757 r600_pipe_state_add_reg(rstate, R_028AB8_VGT_VTX_CNT_EN, 0x0, 0xFFFFFFFF, NULL, 0);
1758 r600_pipe_state_add_reg(rstate, R_008A14_PA_CL_ENHANCE, (3 << 1) | 1, 0xFFFFFFFF, NULL, 0);
1759
1760 r600_pipe_state_add_reg(rstate, R_028380_SQ_VTX_SEMANTIC_0, 0x0, 0xFFFFFFFF, NULL, 0);
1761 r600_pipe_state_add_reg(rstate, R_028384_SQ_VTX_SEMANTIC_1, 0x0, 0xFFFFFFFF, NULL, 0);
1762 r600_pipe_state_add_reg(rstate, R_028388_SQ_VTX_SEMANTIC_2, 0x0, 0xFFFFFFFF, NULL, 0);
1763 r600_pipe_state_add_reg(rstate, R_02838C_SQ_VTX_SEMANTIC_3, 0x0, 0xFFFFFFFF, NULL, 0);
1764 r600_pipe_state_add_reg(rstate, R_028390_SQ_VTX_SEMANTIC_4, 0x0, 0xFFFFFFFF, NULL, 0);
1765 r600_pipe_state_add_reg(rstate, R_028394_SQ_VTX_SEMANTIC_5, 0x0, 0xFFFFFFFF, NULL, 0);
1766 r600_pipe_state_add_reg(rstate, R_028398_SQ_VTX_SEMANTIC_6, 0x0, 0xFFFFFFFF, NULL, 0);
1767 r600_pipe_state_add_reg(rstate, R_02839C_SQ_VTX_SEMANTIC_7, 0x0, 0xFFFFFFFF, NULL, 0);
1768 r600_pipe_state_add_reg(rstate, R_0283A0_SQ_VTX_SEMANTIC_8, 0x0, 0xFFFFFFFF, NULL, 0);
1769 r600_pipe_state_add_reg(rstate, R_0283A4_SQ_VTX_SEMANTIC_9, 0x0, 0xFFFFFFFF, NULL, 0);
1770 r600_pipe_state_add_reg(rstate, R_0283A8_SQ_VTX_SEMANTIC_10, 0x0, 0xFFFFFFFF, NULL, 0);
1771 r600_pipe_state_add_reg(rstate, R_0283AC_SQ_VTX_SEMANTIC_11, 0x0, 0xFFFFFFFF, NULL, 0);
1772 r600_pipe_state_add_reg(rstate, R_0283B0_SQ_VTX_SEMANTIC_12, 0x0, 0xFFFFFFFF, NULL, 0);
1773 r600_pipe_state_add_reg(rstate, R_0283B4_SQ_VTX_SEMANTIC_13, 0x0, 0xFFFFFFFF, NULL, 0);
1774 r600_pipe_state_add_reg(rstate, R_0283B8_SQ_VTX_SEMANTIC_14, 0x0, 0xFFFFFFFF, NULL, 0);
1775 r600_pipe_state_add_reg(rstate, R_0283BC_SQ_VTX_SEMANTIC_15, 0x0, 0xFFFFFFFF, NULL, 0);
1776 r600_pipe_state_add_reg(rstate, R_0283C0_SQ_VTX_SEMANTIC_16, 0x0, 0xFFFFFFFF, NULL, 0);
1777 r600_pipe_state_add_reg(rstate, R_0283C4_SQ_VTX_SEMANTIC_17, 0x0, 0xFFFFFFFF, NULL, 0);
1778 r600_pipe_state_add_reg(rstate, R_0283C8_SQ_VTX_SEMANTIC_18, 0x0, 0xFFFFFFFF, NULL, 0);
1779 r600_pipe_state_add_reg(rstate, R_0283CC_SQ_VTX_SEMANTIC_19, 0x0, 0xFFFFFFFF, NULL, 0);
1780 r600_pipe_state_add_reg(rstate, R_0283D0_SQ_VTX_SEMANTIC_20, 0x0, 0xFFFFFFFF, NULL, 0);
1781 r600_pipe_state_add_reg(rstate, R_0283D4_SQ_VTX_SEMANTIC_21, 0x0, 0xFFFFFFFF, NULL, 0);
1782 r600_pipe_state_add_reg(rstate, R_0283D8_SQ_VTX_SEMANTIC_22, 0x0, 0xFFFFFFFF, NULL, 0);
1783 r600_pipe_state_add_reg(rstate, R_0283DC_SQ_VTX_SEMANTIC_23, 0x0, 0xFFFFFFFF, NULL, 0);
1784 r600_pipe_state_add_reg(rstate, R_0283E0_SQ_VTX_SEMANTIC_24, 0x0, 0xFFFFFFFF, NULL, 0);
1785 r600_pipe_state_add_reg(rstate, R_0283E4_SQ_VTX_SEMANTIC_25, 0x0, 0xFFFFFFFF, NULL, 0);
1786 r600_pipe_state_add_reg(rstate, R_0283E8_SQ_VTX_SEMANTIC_26, 0x0, 0xFFFFFFFF, NULL, 0);
1787 r600_pipe_state_add_reg(rstate, R_0283EC_SQ_VTX_SEMANTIC_27, 0x0, 0xFFFFFFFF, NULL, 0);
1788 r600_pipe_state_add_reg(rstate, R_0283F0_SQ_VTX_SEMANTIC_28, 0x0, 0xFFFFFFFF, NULL, 0);
1789 r600_pipe_state_add_reg(rstate, R_0283F4_SQ_VTX_SEMANTIC_29, 0x0, 0xFFFFFFFF, NULL, 0);
1790 r600_pipe_state_add_reg(rstate, R_0283F8_SQ_VTX_SEMANTIC_30, 0x0, 0xFFFFFFFF, NULL, 0);
1791 r600_pipe_state_add_reg(rstate, R_0283FC_SQ_VTX_SEMANTIC_31, 0x0, 0xFFFFFFFF, NULL, 0);
1792
1793 r600_pipe_state_add_reg(rstate, R_028810_PA_CL_CLIP_CNTL, 0x0, 0xFFFFFFFF, NULL, 0);
1794
1795 r600_pipe_state_add_reg(rstate, CM_R_028BD4_PA_SC_CENTROID_PRIORITY_0, 0x76543210, 0xffffffff, NULL, 0);
1796 r600_pipe_state_add_reg(rstate, CM_R_028BD8_PA_SC_CENTROID_PRIORITY_1, 0xfedcba98, 0xffffffff, NULL, 0);
1797
1798 r600_pipe_state_add_reg(rstate, CM_R_0288E8_SQ_LDS_ALLOC, 0, 0xFFFFFFFF, NULL, 0);
1799 r600_pipe_state_add_reg(rstate, R_0288EC_SQ_LDS_ALLOC_PS, 0, 0xFFFFFFFF, NULL, 0);
1800
1801 r600_pipe_state_add_reg(rstate, CM_R_028804_DB_EQAA, 0x110000, 0xFFFFFFFF, NULL, 0);
1802 r600_context_pipe_state_set(&rctx->ctx, rstate);
1803 }
1804
1805 void evergreen_init_config(struct r600_pipe_context *rctx)
1806 {
1807 struct r600_pipe_state *rstate = &rctx->config;
1808 int ps_prio;
1809 int vs_prio;
1810 int gs_prio;
1811 int es_prio;
1812 int hs_prio, cs_prio, ls_prio;
1813 int num_ps_gprs;
1814 int num_vs_gprs;
1815 int num_gs_gprs;
1816 int num_es_gprs;
1817 int num_hs_gprs;
1818 int num_ls_gprs;
1819 int num_temp_gprs;
1820 int num_ps_threads;
1821 int num_vs_threads;
1822 int num_gs_threads;
1823 int num_es_threads;
1824 int num_hs_threads;
1825 int num_ls_threads;
1826 int num_ps_stack_entries;
1827 int num_vs_stack_entries;
1828 int num_gs_stack_entries;
1829 int num_es_stack_entries;
1830 int num_hs_stack_entries;
1831 int num_ls_stack_entries;
1832 enum radeon_family family;
1833 unsigned tmp;
1834
1835 family = rctx->family;
1836
1837 if (rctx->chip_class == CAYMAN) {
1838 cayman_init_config(rctx);
1839 return;
1840 }
1841
1842 ps_prio = 0;
1843 vs_prio = 1;
1844 gs_prio = 2;
1845 es_prio = 3;
1846 hs_prio = 0;
1847 ls_prio = 0;
1848 cs_prio = 0;
1849
1850 switch (family) {
1851 case CHIP_CEDAR:
1852 default:
1853 num_ps_gprs = 93;
1854 num_vs_gprs = 46;
1855 num_temp_gprs = 4;
1856 num_gs_gprs = 31;
1857 num_es_gprs = 31;
1858 num_hs_gprs = 23;
1859 num_ls_gprs = 23;
1860 num_ps_threads = 96;
1861 num_vs_threads = 16;
1862 num_gs_threads = 16;
1863 num_es_threads = 16;
1864 num_hs_threads = 16;
1865 num_ls_threads = 16;
1866 num_ps_stack_entries = 42;
1867 num_vs_stack_entries = 42;
1868 num_gs_stack_entries = 42;
1869 num_es_stack_entries = 42;
1870 num_hs_stack_entries = 42;
1871 num_ls_stack_entries = 42;
1872 break;
1873 case CHIP_REDWOOD:
1874 num_ps_gprs = 93;
1875 num_vs_gprs = 46;
1876 num_temp_gprs = 4;
1877 num_gs_gprs = 31;
1878 num_es_gprs = 31;
1879 num_hs_gprs = 23;
1880 num_ls_gprs = 23;
1881 num_ps_threads = 128;
1882 num_vs_threads = 20;
1883 num_gs_threads = 20;
1884 num_es_threads = 20;
1885 num_hs_threads = 20;
1886 num_ls_threads = 20;
1887 num_ps_stack_entries = 42;
1888 num_vs_stack_entries = 42;
1889 num_gs_stack_entries = 42;
1890 num_es_stack_entries = 42;
1891 num_hs_stack_entries = 42;
1892 num_ls_stack_entries = 42;
1893 break;
1894 case CHIP_JUNIPER:
1895 num_ps_gprs = 93;
1896 num_vs_gprs = 46;
1897 num_temp_gprs = 4;
1898 num_gs_gprs = 31;
1899 num_es_gprs = 31;
1900 num_hs_gprs = 23;
1901 num_ls_gprs = 23;
1902 num_ps_threads = 128;
1903 num_vs_threads = 20;
1904 num_gs_threads = 20;
1905 num_es_threads = 20;
1906 num_hs_threads = 20;
1907 num_ls_threads = 20;
1908 num_ps_stack_entries = 85;
1909 num_vs_stack_entries = 85;
1910 num_gs_stack_entries = 85;
1911 num_es_stack_entries = 85;
1912 num_hs_stack_entries = 85;
1913 num_ls_stack_entries = 85;
1914 break;
1915 case CHIP_CYPRESS:
1916 case CHIP_HEMLOCK:
1917 num_ps_gprs = 93;
1918 num_vs_gprs = 46;
1919 num_temp_gprs = 4;
1920 num_gs_gprs = 31;
1921 num_es_gprs = 31;
1922 num_hs_gprs = 23;
1923 num_ls_gprs = 23;
1924 num_ps_threads = 128;
1925 num_vs_threads = 20;
1926 num_gs_threads = 20;
1927 num_es_threads = 20;
1928 num_hs_threads = 20;
1929 num_ls_threads = 20;
1930 num_ps_stack_entries = 85;
1931 num_vs_stack_entries = 85;
1932 num_gs_stack_entries = 85;
1933 num_es_stack_entries = 85;
1934 num_hs_stack_entries = 85;
1935 num_ls_stack_entries = 85;
1936 break;
1937 case CHIP_PALM:
1938 num_ps_gprs = 93;
1939 num_vs_gprs = 46;
1940 num_temp_gprs = 4;
1941 num_gs_gprs = 31;
1942 num_es_gprs = 31;
1943 num_hs_gprs = 23;
1944 num_ls_gprs = 23;
1945 num_ps_threads = 96;
1946 num_vs_threads = 16;
1947 num_gs_threads = 16;
1948 num_es_threads = 16;
1949 num_hs_threads = 16;
1950 num_ls_threads = 16;
1951 num_ps_stack_entries = 42;
1952 num_vs_stack_entries = 42;
1953 num_gs_stack_entries = 42;
1954 num_es_stack_entries = 42;
1955 num_hs_stack_entries = 42;
1956 num_ls_stack_entries = 42;
1957 break;
1958 case CHIP_SUMO:
1959 num_ps_gprs = 93;
1960 num_vs_gprs = 46;
1961 num_temp_gprs = 4;
1962 num_gs_gprs = 31;
1963 num_es_gprs = 31;
1964 num_hs_gprs = 23;
1965 num_ls_gprs = 23;
1966 num_ps_threads = 96;
1967 num_vs_threads = 25;
1968 num_gs_threads = 25;
1969 num_es_threads = 25;
1970 num_hs_threads = 25;
1971 num_ls_threads = 25;
1972 num_ps_stack_entries = 42;
1973 num_vs_stack_entries = 42;
1974 num_gs_stack_entries = 42;
1975 num_es_stack_entries = 42;
1976 num_hs_stack_entries = 42;
1977 num_ls_stack_entries = 42;
1978 break;
1979 case CHIP_SUMO2:
1980 num_ps_gprs = 93;
1981 num_vs_gprs = 46;
1982 num_temp_gprs = 4;
1983 num_gs_gprs = 31;
1984 num_es_gprs = 31;
1985 num_hs_gprs = 23;
1986 num_ls_gprs = 23;
1987 num_ps_threads = 96;
1988 num_vs_threads = 25;
1989 num_gs_threads = 25;
1990 num_es_threads = 25;
1991 num_hs_threads = 25;
1992 num_ls_threads = 25;
1993 num_ps_stack_entries = 85;
1994 num_vs_stack_entries = 85;
1995 num_gs_stack_entries = 85;
1996 num_es_stack_entries = 85;
1997 num_hs_stack_entries = 85;
1998 num_ls_stack_entries = 85;
1999 break;
2000 case CHIP_BARTS:
2001 num_ps_gprs = 93;
2002 num_vs_gprs = 46;
2003 num_temp_gprs = 4;
2004 num_gs_gprs = 31;
2005 num_es_gprs = 31;
2006 num_hs_gprs = 23;
2007 num_ls_gprs = 23;
2008 num_ps_threads = 128;
2009 num_vs_threads = 20;
2010 num_gs_threads = 20;
2011 num_es_threads = 20;
2012 num_hs_threads = 20;
2013 num_ls_threads = 20;
2014 num_ps_stack_entries = 85;
2015 num_vs_stack_entries = 85;
2016 num_gs_stack_entries = 85;
2017 num_es_stack_entries = 85;
2018 num_hs_stack_entries = 85;
2019 num_ls_stack_entries = 85;
2020 break;
2021 case CHIP_TURKS:
2022 num_ps_gprs = 93;
2023 num_vs_gprs = 46;
2024 num_temp_gprs = 4;
2025 num_gs_gprs = 31;
2026 num_es_gprs = 31;
2027 num_hs_gprs = 23;
2028 num_ls_gprs = 23;
2029 num_ps_threads = 128;
2030 num_vs_threads = 20;
2031 num_gs_threads = 20;
2032 num_es_threads = 20;
2033 num_hs_threads = 20;
2034 num_ls_threads = 20;
2035 num_ps_stack_entries = 42;
2036 num_vs_stack_entries = 42;
2037 num_gs_stack_entries = 42;
2038 num_es_stack_entries = 42;
2039 num_hs_stack_entries = 42;
2040 num_ls_stack_entries = 42;
2041 break;
2042 case CHIP_CAICOS:
2043 num_ps_gprs = 93;
2044 num_vs_gprs = 46;
2045 num_temp_gprs = 4;
2046 num_gs_gprs = 31;
2047 num_es_gprs = 31;
2048 num_hs_gprs = 23;
2049 num_ls_gprs = 23;
2050 num_ps_threads = 128;
2051 num_vs_threads = 10;
2052 num_gs_threads = 10;
2053 num_es_threads = 10;
2054 num_hs_threads = 10;
2055 num_ls_threads = 10;
2056 num_ps_stack_entries = 42;
2057 num_vs_stack_entries = 42;
2058 num_gs_stack_entries = 42;
2059 num_es_stack_entries = 42;
2060 num_hs_stack_entries = 42;
2061 num_ls_stack_entries = 42;
2062 break;
2063 }
2064
2065 tmp = 0x00000000;
2066 switch (family) {
2067 case CHIP_CEDAR:
2068 case CHIP_PALM:
2069 case CHIP_SUMO:
2070 case CHIP_SUMO2:
2071 case CHIP_CAICOS:
2072 break;
2073 default:
2074 tmp |= S_008C00_VC_ENABLE(1);
2075 break;
2076 }
2077 tmp |= S_008C00_EXPORT_SRC_C(1);
2078 tmp |= S_008C00_CS_PRIO(cs_prio);
2079 tmp |= S_008C00_LS_PRIO(ls_prio);
2080 tmp |= S_008C00_HS_PRIO(hs_prio);
2081 tmp |= S_008C00_PS_PRIO(ps_prio);
2082 tmp |= S_008C00_VS_PRIO(vs_prio);
2083 tmp |= S_008C00_GS_PRIO(gs_prio);
2084 tmp |= S_008C00_ES_PRIO(es_prio);
2085 r600_pipe_state_add_reg(rstate, R_008C00_SQ_CONFIG, tmp, 0xFFFFFFFF, NULL, 0);
2086
2087 /* enable dynamic GPR resource management */
2088 if (rctx->screen->info.drm_minor >= 7) {
2089 /* always set temp clauses */
2090 r600_pipe_state_add_reg(rstate, R_008C04_SQ_GPR_RESOURCE_MGMT_1,
2091 S_008C04_NUM_CLAUSE_TEMP_GPRS(num_temp_gprs), 0xFFFFFFFF, NULL, 0);
2092 r600_pipe_state_add_reg(rstate, R_008C10_SQ_GLOBAL_GPR_RESOURCE_MGMT_1, 0, 0xFFFFFFFF, NULL, 0);
2093 r600_pipe_state_add_reg(rstate, R_008C14_SQ_GLOBAL_GPR_RESOURCE_MGMT_2, 0, 0xFFFFFFFF, NULL, 0);
2094 r600_pipe_state_add_reg(rstate, R_008D8C_SQ_DYN_GPR_CNTL_PS_FLUSH_REQ, (1 << 8), 0xFFFFFFFF, NULL, 0);
2095 r600_pipe_state_add_reg(rstate, R_028838_SQ_DYN_GPR_RESOURCE_LIMIT_1,
2096 S_028838_PS_GPRS(0x1e) |
2097 S_028838_VS_GPRS(0x1e) |
2098 S_028838_GS_GPRS(0x1e) |
2099 S_028838_ES_GPRS(0x1e) |
2100 S_028838_HS_GPRS(0x1e) |
2101 S_028838_LS_GPRS(0x1e), 0xFFFFFFFF, NULL, 0); /* workaround for hw issues with dyn gpr - must set all limits to 240 instead of 0, 0x1e == 240 / 8*/
2102 } else {
2103 tmp = 0;
2104 tmp |= S_008C04_NUM_PS_GPRS(num_ps_gprs);
2105 tmp |= S_008C04_NUM_VS_GPRS(num_vs_gprs);
2106 tmp |= S_008C04_NUM_CLAUSE_TEMP_GPRS(num_temp_gprs);
2107 r600_pipe_state_add_reg(rstate, R_008C04_SQ_GPR_RESOURCE_MGMT_1, tmp, 0xFFFFFFFF, NULL, 0);
2108
2109 tmp = 0;
2110 tmp |= S_008C08_NUM_GS_GPRS(num_gs_gprs);
2111 tmp |= S_008C08_NUM_ES_GPRS(num_es_gprs);
2112 r600_pipe_state_add_reg(rstate, R_008C08_SQ_GPR_RESOURCE_MGMT_2, tmp, 0xFFFFFFFF, NULL, 0);
2113
2114 tmp = 0;
2115 tmp |= S_008C0C_NUM_HS_GPRS(num_hs_gprs);
2116 tmp |= S_008C0C_NUM_HS_GPRS(num_ls_gprs);
2117 r600_pipe_state_add_reg(rstate, R_008C0C_SQ_GPR_RESOURCE_MGMT_3, tmp, 0xFFFFFFFF, NULL, 0);
2118 }
2119
2120 tmp = 0;
2121 tmp |= S_008C18_NUM_PS_THREADS(num_ps_threads);
2122 tmp |= S_008C18_NUM_VS_THREADS(num_vs_threads);
2123 tmp |= S_008C18_NUM_GS_THREADS(num_gs_threads);
2124 tmp |= S_008C18_NUM_ES_THREADS(num_es_threads);
2125 r600_pipe_state_add_reg(rstate, R_008C18_SQ_THREAD_RESOURCE_MGMT_1, tmp, 0xFFFFFFFF, NULL, 0);
2126
2127 tmp = 0;
2128 tmp |= S_008C1C_NUM_HS_THREADS(num_hs_threads);
2129 tmp |= S_008C1C_NUM_LS_THREADS(num_ls_threads);
2130 r600_pipe_state_add_reg(rstate, R_008C1C_SQ_THREAD_RESOURCE_MGMT_2, tmp, 0xFFFFFFFF, NULL, 0);
2131
2132 tmp = 0;
2133 tmp |= S_008C20_NUM_PS_STACK_ENTRIES(num_ps_stack_entries);
2134 tmp |= S_008C20_NUM_VS_STACK_ENTRIES(num_vs_stack_entries);
2135 r600_pipe_state_add_reg(rstate, R_008C20_SQ_STACK_RESOURCE_MGMT_1, tmp, 0xFFFFFFFF, NULL, 0);
2136
2137 tmp = 0;
2138 tmp |= S_008C24_NUM_GS_STACK_ENTRIES(num_gs_stack_entries);
2139 tmp |= S_008C24_NUM_ES_STACK_ENTRIES(num_es_stack_entries);
2140 r600_pipe_state_add_reg(rstate, R_008C24_SQ_STACK_RESOURCE_MGMT_2, tmp, 0xFFFFFFFF, NULL, 0);
2141
2142 tmp = 0;
2143 tmp |= S_008C28_NUM_HS_STACK_ENTRIES(num_hs_stack_entries);
2144 tmp |= S_008C28_NUM_LS_STACK_ENTRIES(num_ls_stack_entries);
2145 r600_pipe_state_add_reg(rstate, R_008C28_SQ_STACK_RESOURCE_MGMT_3, tmp, 0xFFFFFFFF, NULL, 0);
2146
2147 tmp = 0;
2148 tmp |= S_008E2C_NUM_PS_LDS(0x1000);
2149 tmp |= S_008E2C_NUM_LS_LDS(0x1000);
2150 r600_pipe_state_add_reg(rstate, R_008E2C_SQ_LDS_RESOURCE_MGMT, tmp, 0xFFFFFFFF, NULL, 0);
2151
2152 r600_pipe_state_add_reg(rstate, R_009100_SPI_CONFIG_CNTL, 0x0, 0xFFFFFFFF, NULL, 0);
2153 r600_pipe_state_add_reg(rstate, R_00913C_SPI_CONFIG_CNTL_1, S_00913C_VTX_DONE_DELAY(4), 0xFFFFFFFF, NULL, 0);
2154
2155 #if 0
2156 r600_pipe_state_add_reg(rstate, R_028350_SX_MISC, 0x0, 0xFFFFFFFF, NULL, 0);
2157
2158 r600_pipe_state_add_reg(rstate, R_008D8C_SQ_DYN_GPR_CNTL_PS_FLUSH_REQ, 0x0, 0xFFFFFFFF, NULL, 0);
2159 #endif
2160 r600_pipe_state_add_reg(rstate, R_028A4C_PA_SC_MODE_CNTL_1, 0x0, 0xFFFFFFFF, NULL, 0);
2161
2162 r600_pipe_state_add_reg(rstate, R_028900_SQ_ESGS_RING_ITEMSIZE, 0x0, 0xFFFFFFFF, NULL, 0);
2163 r600_pipe_state_add_reg(rstate, R_028904_SQ_GSVS_RING_ITEMSIZE, 0x0, 0xFFFFFFFF, NULL, 0);
2164 r600_pipe_state_add_reg(rstate, R_028908_SQ_ESTMP_RING_ITEMSIZE, 0x0, 0xFFFFFFFF, NULL, 0);
2165 r600_pipe_state_add_reg(rstate, R_02890C_SQ_GSTMP_RING_ITEMSIZE, 0x0, 0xFFFFFFFF, NULL, 0);
2166 r600_pipe_state_add_reg(rstate, R_028910_SQ_VSTMP_RING_ITEMSIZE, 0x0, 0xFFFFFFFF, NULL, 0);
2167 r600_pipe_state_add_reg(rstate, R_028914_SQ_PSTMP_RING_ITEMSIZE, 0x0, 0xFFFFFFFF, NULL, 0);
2168
2169 r600_pipe_state_add_reg(rstate, R_02891C_SQ_GS_VERT_ITEMSIZE, 0x0, 0xFFFFFFFF, NULL, 0);
2170 r600_pipe_state_add_reg(rstate, R_028920_SQ_GS_VERT_ITEMSIZE_1, 0x0, 0xFFFFFFFF, NULL, 0);
2171 r600_pipe_state_add_reg(rstate, R_028924_SQ_GS_VERT_ITEMSIZE_2, 0x0, 0xFFFFFFFF, NULL, 0);
2172 r600_pipe_state_add_reg(rstate, R_028928_SQ_GS_VERT_ITEMSIZE_3, 0x0, 0xFFFFFFFF, NULL, 0);
2173
2174 r600_pipe_state_add_reg(rstate, R_028A10_VGT_OUTPUT_PATH_CNTL, 0x0, 0xFFFFFFFF, NULL, 0);
2175 r600_pipe_state_add_reg(rstate, R_028A14_VGT_HOS_CNTL, 0x0, 0xFFFFFFFF, NULL, 0);
2176 r600_pipe_state_add_reg(rstate, R_028A18_VGT_HOS_MAX_TESS_LEVEL, 0x0, 0xFFFFFFFF, NULL, 0);
2177 r600_pipe_state_add_reg(rstate, R_028A1C_VGT_HOS_MIN_TESS_LEVEL, 0x0, 0xFFFFFFFF, NULL, 0);
2178 r600_pipe_state_add_reg(rstate, R_028A20_VGT_HOS_REUSE_DEPTH, 0x0, 0xFFFFFFFF, NULL, 0);
2179 r600_pipe_state_add_reg(rstate, R_028A24_VGT_GROUP_PRIM_TYPE, 0x0, 0xFFFFFFFF, NULL, 0);
2180 r600_pipe_state_add_reg(rstate, R_028A28_VGT_GROUP_FIRST_DECR, 0x0, 0xFFFFFFFF, NULL, 0);
2181 r600_pipe_state_add_reg(rstate, R_028A2C_VGT_GROUP_DECR, 0x0, 0xFFFFFFFF, NULL, 0);
2182 r600_pipe_state_add_reg(rstate, R_028A30_VGT_GROUP_VECT_0_CNTL, 0x0, 0xFFFFFFFF, NULL, 0);
2183 r600_pipe_state_add_reg(rstate, R_028A34_VGT_GROUP_VECT_1_CNTL, 0x0, 0xFFFFFFFF, NULL, 0);
2184 r600_pipe_state_add_reg(rstate, R_028A38_VGT_GROUP_VECT_0_FMT_CNTL, 0x0, 0xFFFFFFFF, NULL, 0);
2185 r600_pipe_state_add_reg(rstate, R_028A3C_VGT_GROUP_VECT_1_FMT_CNTL, 0x0, 0xFFFFFFFF, NULL, 0);
2186 r600_pipe_state_add_reg(rstate, R_028A40_VGT_GS_MODE, 0x0, 0xFFFFFFFF, NULL, 0);
2187 r600_pipe_state_add_reg(rstate, R_028B94_VGT_STRMOUT_CONFIG, 0x0, 0xFFFFFFFF, NULL, 0);
2188 r600_pipe_state_add_reg(rstate, R_028B98_VGT_STRMOUT_BUFFER_CONFIG, 0x0, 0xFFFFFFFF, NULL, 0);
2189 r600_pipe_state_add_reg(rstate, R_028AB4_VGT_REUSE_OFF, 0x00000000, 0xFFFFFFFF, NULL, 0);
2190 r600_pipe_state_add_reg(rstate, R_028AB8_VGT_VTX_CNT_EN, 0x0, 0xFFFFFFFF, NULL, 0);
2191 r600_pipe_state_add_reg(rstate, R_008A14_PA_CL_ENHANCE, (3 << 1) | 1, 0xFFFFFFFF, NULL, 0);
2192
2193 r600_pipe_state_add_reg(rstate, R_028380_SQ_VTX_SEMANTIC_0, 0x0, 0xFFFFFFFF, NULL, 0);
2194 r600_pipe_state_add_reg(rstate, R_028384_SQ_VTX_SEMANTIC_1, 0x0, 0xFFFFFFFF, NULL, 0);
2195 r600_pipe_state_add_reg(rstate, R_028388_SQ_VTX_SEMANTIC_2, 0x0, 0xFFFFFFFF, NULL, 0);
2196 r600_pipe_state_add_reg(rstate, R_02838C_SQ_VTX_SEMANTIC_3, 0x0, 0xFFFFFFFF, NULL, 0);
2197 r600_pipe_state_add_reg(rstate, R_028390_SQ_VTX_SEMANTIC_4, 0x0, 0xFFFFFFFF, NULL, 0);
2198 r600_pipe_state_add_reg(rstate, R_028394_SQ_VTX_SEMANTIC_5, 0x0, 0xFFFFFFFF, NULL, 0);
2199 r600_pipe_state_add_reg(rstate, R_028398_SQ_VTX_SEMANTIC_6, 0x0, 0xFFFFFFFF, NULL, 0);
2200 r600_pipe_state_add_reg(rstate, R_02839C_SQ_VTX_SEMANTIC_7, 0x0, 0xFFFFFFFF, NULL, 0);
2201 r600_pipe_state_add_reg(rstate, R_0283A0_SQ_VTX_SEMANTIC_8, 0x0, 0xFFFFFFFF, NULL, 0);
2202 r600_pipe_state_add_reg(rstate, R_0283A4_SQ_VTX_SEMANTIC_9, 0x0, 0xFFFFFFFF, NULL, 0);
2203 r600_pipe_state_add_reg(rstate, R_0283A8_SQ_VTX_SEMANTIC_10, 0x0, 0xFFFFFFFF, NULL, 0);
2204 r600_pipe_state_add_reg(rstate, R_0283AC_SQ_VTX_SEMANTIC_11, 0x0, 0xFFFFFFFF, NULL, 0);
2205 r600_pipe_state_add_reg(rstate, R_0283B0_SQ_VTX_SEMANTIC_12, 0x0, 0xFFFFFFFF, NULL, 0);
2206 r600_pipe_state_add_reg(rstate, R_0283B4_SQ_VTX_SEMANTIC_13, 0x0, 0xFFFFFFFF, NULL, 0);
2207 r600_pipe_state_add_reg(rstate, R_0283B8_SQ_VTX_SEMANTIC_14, 0x0, 0xFFFFFFFF, NULL, 0);
2208 r600_pipe_state_add_reg(rstate, R_0283BC_SQ_VTX_SEMANTIC_15, 0x0, 0xFFFFFFFF, NULL, 0);
2209 r600_pipe_state_add_reg(rstate, R_0283C0_SQ_VTX_SEMANTIC_16, 0x0, 0xFFFFFFFF, NULL, 0);
2210 r600_pipe_state_add_reg(rstate, R_0283C4_SQ_VTX_SEMANTIC_17, 0x0, 0xFFFFFFFF, NULL, 0);
2211 r600_pipe_state_add_reg(rstate, R_0283C8_SQ_VTX_SEMANTIC_18, 0x0, 0xFFFFFFFF, NULL, 0);
2212 r600_pipe_state_add_reg(rstate, R_0283CC_SQ_VTX_SEMANTIC_19, 0x0, 0xFFFFFFFF, NULL, 0);
2213 r600_pipe_state_add_reg(rstate, R_0283D0_SQ_VTX_SEMANTIC_20, 0x0, 0xFFFFFFFF, NULL, 0);
2214 r600_pipe_state_add_reg(rstate, R_0283D4_SQ_VTX_SEMANTIC_21, 0x0, 0xFFFFFFFF, NULL, 0);
2215 r600_pipe_state_add_reg(rstate, R_0283D8_SQ_VTX_SEMANTIC_22, 0x0, 0xFFFFFFFF, NULL, 0);
2216 r600_pipe_state_add_reg(rstate, R_0283DC_SQ_VTX_SEMANTIC_23, 0x0, 0xFFFFFFFF, NULL, 0);
2217 r600_pipe_state_add_reg(rstate, R_0283E0_SQ_VTX_SEMANTIC_24, 0x0, 0xFFFFFFFF, NULL, 0);
2218 r600_pipe_state_add_reg(rstate, R_0283E4_SQ_VTX_SEMANTIC_25, 0x0, 0xFFFFFFFF, NULL, 0);
2219 r600_pipe_state_add_reg(rstate, R_0283E8_SQ_VTX_SEMANTIC_26, 0x0, 0xFFFFFFFF, NULL, 0);
2220 r600_pipe_state_add_reg(rstate, R_0283EC_SQ_VTX_SEMANTIC_27, 0x0, 0xFFFFFFFF, NULL, 0);
2221 r600_pipe_state_add_reg(rstate, R_0283F0_SQ_VTX_SEMANTIC_28, 0x0, 0xFFFFFFFF, NULL, 0);
2222 r600_pipe_state_add_reg(rstate, R_0283F4_SQ_VTX_SEMANTIC_29, 0x0, 0xFFFFFFFF, NULL, 0);
2223 r600_pipe_state_add_reg(rstate, R_0283F8_SQ_VTX_SEMANTIC_30, 0x0, 0xFFFFFFFF, NULL, 0);
2224 r600_pipe_state_add_reg(rstate, R_0283FC_SQ_VTX_SEMANTIC_31, 0x0, 0xFFFFFFFF, NULL, 0);
2225
2226 r600_pipe_state_add_reg(rstate, R_028810_PA_CL_CLIP_CNTL, 0x0, 0xFFFFFFFF, NULL, 0);
2227
2228 r600_context_pipe_state_set(&rctx->ctx, rstate);
2229 }
2230
2231 void evergreen_polygon_offset_update(struct r600_pipe_context *rctx)
2232 {
2233 struct r600_pipe_state state;
2234
2235 state.id = R600_PIPE_STATE_POLYGON_OFFSET;
2236 state.nregs = 0;
2237 if (rctx->rasterizer && rctx->framebuffer.zsbuf) {
2238 float offset_units = rctx->rasterizer->offset_units;
2239 unsigned offset_db_fmt_cntl = 0, depth;
2240
2241 switch (rctx->framebuffer.zsbuf->texture->format) {
2242 case PIPE_FORMAT_Z24X8_UNORM:
2243 case PIPE_FORMAT_Z24_UNORM_S8_UINT:
2244 depth = -24;
2245 offset_units *= 2.0f;
2246 break;
2247 case PIPE_FORMAT_Z32_FLOAT:
2248 case PIPE_FORMAT_Z32_FLOAT_S8X24_UINT:
2249 depth = -23;
2250 offset_units *= 1.0f;
2251 offset_db_fmt_cntl |= S_028B78_POLY_OFFSET_DB_IS_FLOAT_FMT(1);
2252 break;
2253 case PIPE_FORMAT_Z16_UNORM:
2254 depth = -16;
2255 offset_units *= 4.0f;
2256 break;
2257 default:
2258 return;
2259 }
2260 /* FIXME some of those reg can be computed with cso */
2261 offset_db_fmt_cntl |= S_028B78_POLY_OFFSET_NEG_NUM_DB_BITS(depth);
2262 r600_pipe_state_add_reg(&state,
2263 R_028B80_PA_SU_POLY_OFFSET_FRONT_SCALE,
2264 fui(rctx->rasterizer->offset_scale), 0xFFFFFFFF, NULL, 0);
2265 r600_pipe_state_add_reg(&state,
2266 R_028B84_PA_SU_POLY_OFFSET_FRONT_OFFSET,
2267 fui(offset_units), 0xFFFFFFFF, NULL, 0);
2268 r600_pipe_state_add_reg(&state,
2269 R_028B88_PA_SU_POLY_OFFSET_BACK_SCALE,
2270 fui(rctx->rasterizer->offset_scale), 0xFFFFFFFF, NULL, 0);
2271 r600_pipe_state_add_reg(&state,
2272 R_028B8C_PA_SU_POLY_OFFSET_BACK_OFFSET,
2273 fui(offset_units), 0xFFFFFFFF, NULL, 0);
2274 r600_pipe_state_add_reg(&state,
2275 R_028B78_PA_SU_POLY_OFFSET_DB_FMT_CNTL,
2276 offset_db_fmt_cntl, 0xFFFFFFFF, NULL, 0);
2277 r600_context_pipe_state_set(&rctx->ctx, &state);
2278 }
2279 }
2280
2281 void evergreen_pipe_shader_ps(struct pipe_context *ctx, struct r600_pipe_shader *shader)
2282 {
2283 struct r600_pipe_context *rctx = (struct r600_pipe_context *)ctx;
2284 struct r600_pipe_state *rstate = &shader->rstate;
2285 struct r600_shader *rshader = &shader->shader;
2286 unsigned i, exports_ps, num_cout, spi_ps_in_control_0, spi_input_z, spi_ps_in_control_1, db_shader_control;
2287 int pos_index = -1, face_index = -1;
2288 int ninterp = 0;
2289 boolean have_linear = FALSE, have_centroid = FALSE, have_perspective = FALSE;
2290 unsigned spi_baryc_cntl, sid, tmp, idx = 0;
2291
2292 rstate->nregs = 0;
2293
2294 db_shader_control = 0;
2295 for (i = 0; i < rshader->ninput; i++) {
2296 /* evergreen NUM_INTERP only contains values interpolated into the LDS,
2297 POSITION goes via GPRs from the SC so isn't counted */
2298 if (rshader->input[i].name == TGSI_SEMANTIC_POSITION)
2299 pos_index = i;
2300 else if (rshader->input[i].name == TGSI_SEMANTIC_FACE)
2301 face_index = i;
2302 else {
2303 ninterp++;
2304 if (rshader->input[i].interpolate == TGSI_INTERPOLATE_LINEAR)
2305 have_linear = TRUE;
2306 if (rshader->input[i].interpolate == TGSI_INTERPOLATE_PERSPECTIVE)
2307 have_perspective = TRUE;
2308 if (rshader->input[i].centroid)
2309 have_centroid = TRUE;
2310 }
2311
2312 sid = rshader->input[i].spi_sid;
2313
2314 if (sid) {
2315
2316 tmp = S_028644_SEMANTIC(sid);
2317
2318 if (rshader->input[i].name == TGSI_SEMANTIC_POSITION ||
2319 rshader->input[i].interpolate == TGSI_INTERPOLATE_COLOR ||
2320 rshader->input[i].interpolate == TGSI_INTERPOLATE_CONSTANT) {
2321 tmp |= S_028644_FLAT_SHADE(1);
2322 }
2323
2324 if (rshader->input[i].name == TGSI_SEMANTIC_GENERIC &&
2325 (rctx->sprite_coord_enable & (1 << rshader->input[i].sid))) {
2326 tmp |= S_028644_PT_SPRITE_TEX(1);
2327 }
2328
2329 r600_pipe_state_add_reg(rstate, R_028644_SPI_PS_INPUT_CNTL_0 + idx * 4,
2330 tmp, 0xFFFFFFFF, NULL, 0);
2331
2332 idx++;
2333 }
2334 }
2335
2336 for (i = 0; i < rshader->noutput; i++) {
2337 if (rshader->output[i].name == TGSI_SEMANTIC_POSITION)
2338 db_shader_control |= S_02880C_Z_EXPORT_ENABLE(1);
2339 if (rshader->output[i].name == TGSI_SEMANTIC_STENCIL)
2340 db_shader_control |= S_02880C_STENCIL_EXPORT_ENABLE(1);
2341 }
2342 if (rshader->uses_kill)
2343 db_shader_control |= S_02880C_KILL_ENABLE(1);
2344
2345 exports_ps = 0;
2346 num_cout = 0;
2347 for (i = 0; i < rshader->noutput; i++) {
2348 if (rshader->output[i].name == TGSI_SEMANTIC_POSITION ||
2349 rshader->output[i].name == TGSI_SEMANTIC_STENCIL)
2350 exports_ps |= 1;
2351 else if (rshader->output[i].name == TGSI_SEMANTIC_COLOR) {
2352 if (rshader->fs_write_all)
2353 num_cout = rshader->nr_cbufs;
2354 else
2355 num_cout++;
2356 }
2357 }
2358 exports_ps |= S_02884C_EXPORT_COLORS(num_cout);
2359 if (!exports_ps) {
2360 /* always at least export 1 component per pixel */
2361 exports_ps = 2;
2362 }
2363
2364 if (ninterp == 0) {
2365 ninterp = 1;
2366 have_perspective = TRUE;
2367 }
2368
2369 if (!have_perspective && !have_linear)
2370 have_perspective = TRUE;
2371
2372 spi_ps_in_control_0 = S_0286CC_NUM_INTERP(ninterp) |
2373 S_0286CC_PERSP_GRADIENT_ENA(have_perspective) |
2374 S_0286CC_LINEAR_GRADIENT_ENA(have_linear);
2375 spi_input_z = 0;
2376 if (pos_index != -1) {
2377 spi_ps_in_control_0 |= S_0286CC_POSITION_ENA(1) |
2378 S_0286CC_POSITION_CENTROID(rshader->input[pos_index].centroid) |
2379 S_0286CC_POSITION_ADDR(rshader->input[pos_index].gpr);
2380 spi_input_z |= 1;
2381 }
2382
2383 spi_ps_in_control_1 = 0;
2384 if (face_index != -1) {
2385 spi_ps_in_control_1 |= S_0286D0_FRONT_FACE_ENA(1) |
2386 S_0286D0_FRONT_FACE_ADDR(rshader->input[face_index].gpr);
2387 }
2388
2389 spi_baryc_cntl = 0;
2390 if (have_perspective)
2391 spi_baryc_cntl |= S_0286E0_PERSP_CENTER_ENA(1) |
2392 S_0286E0_PERSP_CENTROID_ENA(have_centroid);
2393 if (have_linear)
2394 spi_baryc_cntl |= S_0286E0_LINEAR_CENTER_ENA(1) |
2395 S_0286E0_LINEAR_CENTROID_ENA(have_centroid);
2396
2397 r600_pipe_state_add_reg(rstate, R_0286CC_SPI_PS_IN_CONTROL_0,
2398 spi_ps_in_control_0, 0xFFFFFFFF, NULL, 0);
2399 r600_pipe_state_add_reg(rstate, R_0286D0_SPI_PS_IN_CONTROL_1,
2400 spi_ps_in_control_1, 0xFFFFFFFF, NULL, 0);
2401 r600_pipe_state_add_reg(rstate, R_0286E4_SPI_PS_IN_CONTROL_2,
2402 0, 0xFFFFFFFF, NULL, 0);
2403 r600_pipe_state_add_reg(rstate, R_0286D8_SPI_INPUT_Z, spi_input_z, 0xFFFFFFFF, NULL, 0);
2404 r600_pipe_state_add_reg(rstate,
2405 R_0286E0_SPI_BARYC_CNTL,
2406 spi_baryc_cntl,
2407 0xFFFFFFFF, NULL, 0);
2408
2409 r600_pipe_state_add_reg(rstate,
2410 R_028840_SQ_PGM_START_PS,
2411 r600_resource_va(ctx->screen, (void *)shader->bo) >> 8,
2412 0xFFFFFFFF, shader->bo, RADEON_USAGE_READ);
2413 r600_pipe_state_add_reg(rstate,
2414 R_028844_SQ_PGM_RESOURCES_PS,
2415 S_028844_NUM_GPRS(rshader->bc.ngpr) |
2416 S_028844_PRIME_CACHE_ON_DRAW(1) |
2417 S_028844_STACK_SIZE(rshader->bc.nstack),
2418 0xFFFFFFFF, NULL, 0);
2419 r600_pipe_state_add_reg(rstate,
2420 R_028848_SQ_PGM_RESOURCES_2_PS,
2421 S_028848_SINGLE_ROUND(V_SQ_ROUND_TO_ZERO),
2422 0xFFFFFFFF, NULL, 0);
2423 r600_pipe_state_add_reg(rstate,
2424 R_02884C_SQ_PGM_EXPORTS_PS,
2425 exports_ps, 0xFFFFFFFF, NULL, 0);
2426 /* only set some bits here, the other bits are set in the dsa state */
2427 r600_pipe_state_add_reg(rstate,
2428 R_02880C_DB_SHADER_CONTROL,
2429 db_shader_control,
2430 S_02880C_Z_EXPORT_ENABLE(1) |
2431 S_02880C_STENCIL_EXPORT_ENABLE(1) |
2432 S_02880C_KILL_ENABLE(1),
2433 NULL, 0);
2434 r600_pipe_state_add_reg(rstate,
2435 R_03A200_SQ_LOOP_CONST_0, 0x01000FFF,
2436 0xFFFFFFFF, NULL, 0);
2437
2438 shader->sprite_coord_enable = rctx->sprite_coord_enable;
2439 }
2440
2441 void evergreen_pipe_shader_vs(struct pipe_context *ctx, struct r600_pipe_shader *shader)
2442 {
2443 struct r600_pipe_context *rctx = (struct r600_pipe_context *)ctx;
2444 struct r600_pipe_state *rstate = &shader->rstate;
2445 struct r600_shader *rshader = &shader->shader;
2446 unsigned spi_vs_out_id[10] = {};
2447 unsigned i, tmp, nparams = 0;
2448
2449 /* clear previous register */
2450 rstate->nregs = 0;
2451
2452 for (i = 0; i < rshader->noutput; i++) {
2453 if (rshader->output[i].spi_sid) {
2454 tmp = rshader->output[i].spi_sid << ((nparams & 3) * 8);
2455 spi_vs_out_id[nparams / 4] |= tmp;
2456 nparams++;
2457 }
2458 }
2459
2460 for (i = 0; i < 10; i++) {
2461 r600_pipe_state_add_reg(rstate,
2462 R_02861C_SPI_VS_OUT_ID_0 + i * 4,
2463 spi_vs_out_id[i], 0xFFFFFFFF, NULL, 0);
2464 }
2465
2466 /* Certain attributes (position, psize, etc.) don't count as params.
2467 * VS is required to export at least one param and r600_shader_from_tgsi()
2468 * takes care of adding a dummy export.
2469 */
2470 if (nparams < 1)
2471 nparams = 1;
2472
2473 r600_pipe_state_add_reg(rstate,
2474 R_0286C4_SPI_VS_OUT_CONFIG,
2475 S_0286C4_VS_EXPORT_COUNT(nparams - 1),
2476 0xFFFFFFFF, NULL, 0);
2477 r600_pipe_state_add_reg(rstate,
2478 R_028860_SQ_PGM_RESOURCES_VS,
2479 S_028860_NUM_GPRS(rshader->bc.ngpr) |
2480 S_028860_STACK_SIZE(rshader->bc.nstack),
2481 0xFFFFFFFF, NULL, 0);
2482 r600_pipe_state_add_reg(rstate,
2483 R_028864_SQ_PGM_RESOURCES_2_VS,
2484 S_028864_SINGLE_ROUND(V_SQ_ROUND_TO_ZERO),
2485 0xFFFFFFFF, NULL, 0);
2486 r600_pipe_state_add_reg(rstate,
2487 R_02885C_SQ_PGM_START_VS,
2488 r600_resource_va(ctx->screen, (void *)shader->bo) >> 8,
2489 0xFFFFFFFF, shader->bo, RADEON_USAGE_READ);
2490
2491 r600_pipe_state_add_reg(rstate,
2492 R_03A200_SQ_LOOP_CONST_0 + (32 * 4), 0x01000FFF,
2493 0xFFFFFFFF, NULL, 0);
2494
2495 r600_pipe_state_add_reg(rstate,
2496 R_02881C_PA_CL_VS_OUT_CNTL,
2497 S_02881C_VS_OUT_CCDIST0_VEC_ENA((rshader->clip_dist_write & 0x0F) != 0) |
2498 S_02881C_VS_OUT_CCDIST1_VEC_ENA((rshader->clip_dist_write & 0xF0) != 0) |
2499 S_02881C_VS_OUT_MISC_VEC_ENA(rshader->vs_out_misc_write),
2500 S_02881C_VS_OUT_CCDIST0_VEC_ENA(1) |
2501 S_02881C_VS_OUT_CCDIST1_VEC_ENA(1) |
2502 S_02881C_VS_OUT_MISC_VEC_ENA(1),
2503 NULL, 0);
2504 }
2505
2506 void evergreen_fetch_shader(struct pipe_context *ctx,
2507 struct r600_vertex_element *ve)
2508 {
2509 struct r600_pipe_context *rctx = (struct r600_pipe_context *)ctx;
2510 struct r600_pipe_state *rstate = &ve->rstate;
2511 rstate->id = R600_PIPE_STATE_FETCH_SHADER;
2512 rstate->nregs = 0;
2513 r600_pipe_state_add_reg(rstate, R_0288A8_SQ_PGM_RESOURCES_FS,
2514 0x00000000, 0xFFFFFFFF, NULL, 0);
2515 r600_pipe_state_add_reg(rstate, R_0288A4_SQ_PGM_START_FS,
2516 r600_resource_va(ctx->screen, (void *)ve->fetch_shader) >> 8,
2517 0xFFFFFFFF, ve->fetch_shader, RADEON_USAGE_READ);
2518 }
2519
2520 void *evergreen_create_db_flush_dsa(struct r600_pipe_context *rctx)
2521 {
2522 struct pipe_depth_stencil_alpha_state dsa;
2523 struct r600_pipe_state *rstate;
2524
2525 memset(&dsa, 0, sizeof(dsa));
2526
2527 rstate = rctx->context.create_depth_stencil_alpha_state(&rctx->context, &dsa);
2528 r600_pipe_state_add_reg(rstate,
2529 R_02880C_DB_SHADER_CONTROL,
2530 0x0,
2531 S_02880C_DUAL_EXPORT_ENABLE(1), NULL, 0);
2532 r600_pipe_state_add_reg(rstate,
2533 R_028000_DB_RENDER_CONTROL,
2534 S_028000_DEPTH_COPY_ENABLE(1) |
2535 S_028000_STENCIL_COPY_ENABLE(1) |
2536 S_028000_COPY_CENTROID(1),
2537 S_028000_DEPTH_COPY_ENABLE(1) |
2538 S_028000_STENCIL_COPY_ENABLE(1) |
2539 S_028000_COPY_CENTROID(1), NULL, 0);
2540 return rstate;
2541 }
2542
2543 void evergreen_pipe_init_buffer_resource(struct r600_pipe_context *rctx,
2544 struct r600_pipe_resource_state *rstate)
2545 {
2546 rstate->id = R600_PIPE_STATE_RESOURCE;
2547
2548 rstate->val[0] = 0;
2549 rstate->bo[0] = NULL;
2550 rstate->val[1] = 0;
2551 rstate->val[2] = S_030008_ENDIAN_SWAP(r600_endian_swap(32));
2552 rstate->val[3] = S_03000C_DST_SEL_X(V_03000C_SQ_SEL_X) |
2553 S_03000C_DST_SEL_Y(V_03000C_SQ_SEL_Y) |
2554 S_03000C_DST_SEL_Z(V_03000C_SQ_SEL_Z) |
2555 S_03000C_DST_SEL_W(V_03000C_SQ_SEL_W);
2556 rstate->val[4] = 0;
2557 rstate->val[5] = 0;
2558 rstate->val[6] = 0;
2559 rstate->val[7] = 0xc0000000;
2560 }
2561
2562
2563 void evergreen_pipe_mod_buffer_resource(struct pipe_context *ctx,
2564 struct r600_pipe_resource_state *rstate,
2565 struct r600_resource *rbuffer,
2566 unsigned offset, unsigned stride,
2567 enum radeon_bo_usage usage)
2568 {
2569 uint64_t va;
2570
2571 va = r600_resource_va(ctx->screen, (void *)rbuffer);
2572 rstate->bo[0] = rbuffer;
2573 rstate->bo_usage[0] = usage;
2574 rstate->val[0] = (offset + va) & 0xFFFFFFFFUL;
2575 rstate->val[1] = rbuffer->buf->size - offset - 1;
2576 rstate->val[2] = S_030008_ENDIAN_SWAP(r600_endian_swap(32)) |
2577 S_030008_STRIDE(stride) |
2578 (((va + offset) >> 32UL) & 0xFF);
2579 }