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vc4: Enable V3D 2.6.
[mesa.git] / src / gallium / drivers / r600 / evergreen_state.c
1 /*
2 * Copyright 2010 Jerome Glisse <glisse@freedesktop.org>
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * on the rights to use, copy, modify, merge, publish, distribute, sub
8 * license, and/or sell copies of the Software, and to permit persons to whom
9 * the Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
13 * Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHOR(S) AND/OR THEIR SUPPLIERS BE LIABLE FOR ANY CLAIM,
19 * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
20 * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
21 * USE OR OTHER DEALINGS IN THE SOFTWARE.
22 */
23 #include "r600_formats.h"
24 #include "r600_shader.h"
25 #include "evergreend.h"
26
27 #include "pipe/p_shader_tokens.h"
28 #include "util/u_pack_color.h"
29 #include "util/u_memory.h"
30 #include "util/u_framebuffer.h"
31 #include "util/u_dual_blend.h"
32 #include "evergreen_compute.h"
33 #include "util/u_math.h"
34
35 static inline unsigned evergreen_array_mode(unsigned mode)
36 {
37 switch (mode) {
38 default:
39 case RADEON_SURF_MODE_LINEAR_ALIGNED: return V_028C70_ARRAY_LINEAR_ALIGNED;
40 break;
41 case RADEON_SURF_MODE_1D: return V_028C70_ARRAY_1D_TILED_THIN1;
42 break;
43 case RADEON_SURF_MODE_2D: return V_028C70_ARRAY_2D_TILED_THIN1;
44 }
45 }
46
47 static uint32_t eg_num_banks(uint32_t nbanks)
48 {
49 switch (nbanks) {
50 case 2:
51 return 0;
52 case 4:
53 return 1;
54 case 8:
55 default:
56 return 2;
57 case 16:
58 return 3;
59 }
60 }
61
62
63 static unsigned eg_tile_split(unsigned tile_split)
64 {
65 switch (tile_split) {
66 case 64: tile_split = 0; break;
67 case 128: tile_split = 1; break;
68 case 256: tile_split = 2; break;
69 case 512: tile_split = 3; break;
70 default:
71 case 1024: tile_split = 4; break;
72 case 2048: tile_split = 5; break;
73 case 4096: tile_split = 6; break;
74 }
75 return tile_split;
76 }
77
78 static unsigned eg_macro_tile_aspect(unsigned macro_tile_aspect)
79 {
80 switch (macro_tile_aspect) {
81 default:
82 case 1: macro_tile_aspect = 0; break;
83 case 2: macro_tile_aspect = 1; break;
84 case 4: macro_tile_aspect = 2; break;
85 case 8: macro_tile_aspect = 3; break;
86 }
87 return macro_tile_aspect;
88 }
89
90 static unsigned eg_bank_wh(unsigned bankwh)
91 {
92 switch (bankwh) {
93 default:
94 case 1: bankwh = 0; break;
95 case 2: bankwh = 1; break;
96 case 4: bankwh = 2; break;
97 case 8: bankwh = 3; break;
98 }
99 return bankwh;
100 }
101
102 static uint32_t r600_translate_blend_function(int blend_func)
103 {
104 switch (blend_func) {
105 case PIPE_BLEND_ADD:
106 return V_028780_COMB_DST_PLUS_SRC;
107 case PIPE_BLEND_SUBTRACT:
108 return V_028780_COMB_SRC_MINUS_DST;
109 case PIPE_BLEND_REVERSE_SUBTRACT:
110 return V_028780_COMB_DST_MINUS_SRC;
111 case PIPE_BLEND_MIN:
112 return V_028780_COMB_MIN_DST_SRC;
113 case PIPE_BLEND_MAX:
114 return V_028780_COMB_MAX_DST_SRC;
115 default:
116 R600_ERR("Unknown blend function %d\n", blend_func);
117 assert(0);
118 break;
119 }
120 return 0;
121 }
122
123 static uint32_t r600_translate_blend_factor(int blend_fact)
124 {
125 switch (blend_fact) {
126 case PIPE_BLENDFACTOR_ONE:
127 return V_028780_BLEND_ONE;
128 case PIPE_BLENDFACTOR_SRC_COLOR:
129 return V_028780_BLEND_SRC_COLOR;
130 case PIPE_BLENDFACTOR_SRC_ALPHA:
131 return V_028780_BLEND_SRC_ALPHA;
132 case PIPE_BLENDFACTOR_DST_ALPHA:
133 return V_028780_BLEND_DST_ALPHA;
134 case PIPE_BLENDFACTOR_DST_COLOR:
135 return V_028780_BLEND_DST_COLOR;
136 case PIPE_BLENDFACTOR_SRC_ALPHA_SATURATE:
137 return V_028780_BLEND_SRC_ALPHA_SATURATE;
138 case PIPE_BLENDFACTOR_CONST_COLOR:
139 return V_028780_BLEND_CONST_COLOR;
140 case PIPE_BLENDFACTOR_CONST_ALPHA:
141 return V_028780_BLEND_CONST_ALPHA;
142 case PIPE_BLENDFACTOR_ZERO:
143 return V_028780_BLEND_ZERO;
144 case PIPE_BLENDFACTOR_INV_SRC_COLOR:
145 return V_028780_BLEND_ONE_MINUS_SRC_COLOR;
146 case PIPE_BLENDFACTOR_INV_SRC_ALPHA:
147 return V_028780_BLEND_ONE_MINUS_SRC_ALPHA;
148 case PIPE_BLENDFACTOR_INV_DST_ALPHA:
149 return V_028780_BLEND_ONE_MINUS_DST_ALPHA;
150 case PIPE_BLENDFACTOR_INV_DST_COLOR:
151 return V_028780_BLEND_ONE_MINUS_DST_COLOR;
152 case PIPE_BLENDFACTOR_INV_CONST_COLOR:
153 return V_028780_BLEND_ONE_MINUS_CONST_COLOR;
154 case PIPE_BLENDFACTOR_INV_CONST_ALPHA:
155 return V_028780_BLEND_ONE_MINUS_CONST_ALPHA;
156 case PIPE_BLENDFACTOR_SRC1_COLOR:
157 return V_028780_BLEND_SRC1_COLOR;
158 case PIPE_BLENDFACTOR_SRC1_ALPHA:
159 return V_028780_BLEND_SRC1_ALPHA;
160 case PIPE_BLENDFACTOR_INV_SRC1_COLOR:
161 return V_028780_BLEND_INV_SRC1_COLOR;
162 case PIPE_BLENDFACTOR_INV_SRC1_ALPHA:
163 return V_028780_BLEND_INV_SRC1_ALPHA;
164 default:
165 R600_ERR("Bad blend factor %d not supported!\n", blend_fact);
166 assert(0);
167 break;
168 }
169 return 0;
170 }
171
172 static unsigned r600_tex_dim(unsigned dim, unsigned nr_samples)
173 {
174 switch (dim) {
175 default:
176 case PIPE_TEXTURE_1D:
177 return V_030000_SQ_TEX_DIM_1D;
178 case PIPE_TEXTURE_1D_ARRAY:
179 return V_030000_SQ_TEX_DIM_1D_ARRAY;
180 case PIPE_TEXTURE_2D:
181 case PIPE_TEXTURE_RECT:
182 return nr_samples > 1 ? V_030000_SQ_TEX_DIM_2D_MSAA :
183 V_030000_SQ_TEX_DIM_2D;
184 case PIPE_TEXTURE_2D_ARRAY:
185 return nr_samples > 1 ? V_030000_SQ_TEX_DIM_2D_ARRAY_MSAA :
186 V_030000_SQ_TEX_DIM_2D_ARRAY;
187 case PIPE_TEXTURE_3D:
188 return V_030000_SQ_TEX_DIM_3D;
189 case PIPE_TEXTURE_CUBE:
190 case PIPE_TEXTURE_CUBE_ARRAY:
191 return V_030000_SQ_TEX_DIM_CUBEMAP;
192 }
193 }
194
195 static uint32_t r600_translate_dbformat(enum pipe_format format)
196 {
197 switch (format) {
198 case PIPE_FORMAT_Z16_UNORM:
199 return V_028040_Z_16;
200 case PIPE_FORMAT_Z24X8_UNORM:
201 case PIPE_FORMAT_Z24_UNORM_S8_UINT:
202 case PIPE_FORMAT_X8Z24_UNORM:
203 case PIPE_FORMAT_S8_UINT_Z24_UNORM:
204 return V_028040_Z_24;
205 case PIPE_FORMAT_Z32_FLOAT:
206 case PIPE_FORMAT_Z32_FLOAT_S8X24_UINT:
207 return V_028040_Z_32_FLOAT;
208 default:
209 return ~0U;
210 }
211 }
212
213 static bool r600_is_sampler_format_supported(struct pipe_screen *screen, enum pipe_format format)
214 {
215 return r600_translate_texformat(screen, format, NULL, NULL, NULL,
216 FALSE) != ~0U;
217 }
218
219 static bool r600_is_colorbuffer_format_supported(enum chip_class chip, enum pipe_format format)
220 {
221 return r600_translate_colorformat(chip, format, FALSE) != ~0U &&
222 r600_translate_colorswap(format, FALSE) != ~0U;
223 }
224
225 static bool r600_is_zs_format_supported(enum pipe_format format)
226 {
227 return r600_translate_dbformat(format) != ~0U;
228 }
229
230 boolean evergreen_is_format_supported(struct pipe_screen *screen,
231 enum pipe_format format,
232 enum pipe_texture_target target,
233 unsigned sample_count,
234 unsigned usage)
235 {
236 struct r600_screen *rscreen = (struct r600_screen*)screen;
237 unsigned retval = 0;
238
239 if (target >= PIPE_MAX_TEXTURE_TYPES) {
240 R600_ERR("r600: unsupported texture type %d\n", target);
241 return FALSE;
242 }
243
244 if (!util_format_is_supported(format, usage))
245 return FALSE;
246
247 if (sample_count > 1) {
248 if (!rscreen->has_msaa)
249 return FALSE;
250
251 switch (sample_count) {
252 case 2:
253 case 4:
254 case 8:
255 break;
256 default:
257 return FALSE;
258 }
259 }
260
261 if (usage & PIPE_BIND_SAMPLER_VIEW) {
262 if (target == PIPE_BUFFER) {
263 if (r600_is_vertex_format_supported(format))
264 retval |= PIPE_BIND_SAMPLER_VIEW;
265 } else {
266 if (r600_is_sampler_format_supported(screen, format))
267 retval |= PIPE_BIND_SAMPLER_VIEW;
268 }
269 }
270
271 if ((usage & (PIPE_BIND_RENDER_TARGET |
272 PIPE_BIND_DISPLAY_TARGET |
273 PIPE_BIND_SCANOUT |
274 PIPE_BIND_SHARED |
275 PIPE_BIND_BLENDABLE)) &&
276 r600_is_colorbuffer_format_supported(rscreen->b.chip_class, format)) {
277 retval |= usage &
278 (PIPE_BIND_RENDER_TARGET |
279 PIPE_BIND_DISPLAY_TARGET |
280 PIPE_BIND_SCANOUT |
281 PIPE_BIND_SHARED);
282 if (!util_format_is_pure_integer(format) &&
283 !util_format_is_depth_or_stencil(format))
284 retval |= usage & PIPE_BIND_BLENDABLE;
285 }
286
287 if ((usage & PIPE_BIND_DEPTH_STENCIL) &&
288 r600_is_zs_format_supported(format)) {
289 retval |= PIPE_BIND_DEPTH_STENCIL;
290 }
291
292 if ((usage & PIPE_BIND_VERTEX_BUFFER) &&
293 r600_is_vertex_format_supported(format)) {
294 retval |= PIPE_BIND_VERTEX_BUFFER;
295 }
296
297 if ((usage & PIPE_BIND_LINEAR) &&
298 !util_format_is_compressed(format) &&
299 !(usage & PIPE_BIND_DEPTH_STENCIL))
300 retval |= PIPE_BIND_LINEAR;
301
302 return retval == usage;
303 }
304
305 static void *evergreen_create_blend_state_mode(struct pipe_context *ctx,
306 const struct pipe_blend_state *state, int mode)
307 {
308 uint32_t color_control = 0, target_mask = 0;
309 struct r600_blend_state *blend = CALLOC_STRUCT(r600_blend_state);
310
311 if (!blend) {
312 return NULL;
313 }
314
315 r600_init_command_buffer(&blend->buffer, 20);
316 r600_init_command_buffer(&blend->buffer_no_blend, 20);
317
318 if (state->logicop_enable) {
319 color_control |= (state->logicop_func << 16) | (state->logicop_func << 20);
320 } else {
321 color_control |= (0xcc << 16);
322 }
323 /* we pretend 8 buffer are used, CB_SHADER_MASK will disable unused one */
324 if (state->independent_blend_enable) {
325 for (int i = 0; i < 8; i++) {
326 target_mask |= (state->rt[i].colormask << (4 * i));
327 }
328 } else {
329 for (int i = 0; i < 8; i++) {
330 target_mask |= (state->rt[0].colormask << (4 * i));
331 }
332 }
333
334 /* only have dual source on MRT0 */
335 blend->dual_src_blend = util_blend_state_is_dual(state, 0);
336 blend->cb_target_mask = target_mask;
337 blend->alpha_to_one = state->alpha_to_one;
338
339 if (target_mask)
340 color_control |= S_028808_MODE(mode);
341 else
342 color_control |= S_028808_MODE(V_028808_CB_DISABLE);
343
344
345 r600_store_context_reg(&blend->buffer, R_028808_CB_COLOR_CONTROL, color_control);
346 r600_store_context_reg(&blend->buffer, R_028B70_DB_ALPHA_TO_MASK,
347 S_028B70_ALPHA_TO_MASK_ENABLE(state->alpha_to_coverage) |
348 S_028B70_ALPHA_TO_MASK_OFFSET0(2) |
349 S_028B70_ALPHA_TO_MASK_OFFSET1(2) |
350 S_028B70_ALPHA_TO_MASK_OFFSET2(2) |
351 S_028B70_ALPHA_TO_MASK_OFFSET3(2));
352 r600_store_context_reg_seq(&blend->buffer, R_028780_CB_BLEND0_CONTROL, 8);
353
354 /* Copy over the dwords set so far into buffer_no_blend.
355 * Only the CB_BLENDi_CONTROL registers must be set after this. */
356 memcpy(blend->buffer_no_blend.buf, blend->buffer.buf, blend->buffer.num_dw * 4);
357 blend->buffer_no_blend.num_dw = blend->buffer.num_dw;
358
359 for (int i = 0; i < 8; i++) {
360 /* state->rt entries > 0 only written if independent blending */
361 const int j = state->independent_blend_enable ? i : 0;
362
363 unsigned eqRGB = state->rt[j].rgb_func;
364 unsigned srcRGB = state->rt[j].rgb_src_factor;
365 unsigned dstRGB = state->rt[j].rgb_dst_factor;
366 unsigned eqA = state->rt[j].alpha_func;
367 unsigned srcA = state->rt[j].alpha_src_factor;
368 unsigned dstA = state->rt[j].alpha_dst_factor;
369 uint32_t bc = 0;
370
371 r600_store_value(&blend->buffer_no_blend, 0);
372
373 if (!state->rt[j].blend_enable) {
374 r600_store_value(&blend->buffer, 0);
375 continue;
376 }
377
378 bc |= S_028780_BLEND_CONTROL_ENABLE(1);
379 bc |= S_028780_COLOR_COMB_FCN(r600_translate_blend_function(eqRGB));
380 bc |= S_028780_COLOR_SRCBLEND(r600_translate_blend_factor(srcRGB));
381 bc |= S_028780_COLOR_DESTBLEND(r600_translate_blend_factor(dstRGB));
382
383 if (srcA != srcRGB || dstA != dstRGB || eqA != eqRGB) {
384 bc |= S_028780_SEPARATE_ALPHA_BLEND(1);
385 bc |= S_028780_ALPHA_COMB_FCN(r600_translate_blend_function(eqA));
386 bc |= S_028780_ALPHA_SRCBLEND(r600_translate_blend_factor(srcA));
387 bc |= S_028780_ALPHA_DESTBLEND(r600_translate_blend_factor(dstA));
388 }
389 r600_store_value(&blend->buffer, bc);
390 }
391 return blend;
392 }
393
394 static void *evergreen_create_blend_state(struct pipe_context *ctx,
395 const struct pipe_blend_state *state)
396 {
397
398 return evergreen_create_blend_state_mode(ctx, state, V_028808_CB_NORMAL);
399 }
400
401 static void *evergreen_create_dsa_state(struct pipe_context *ctx,
402 const struct pipe_depth_stencil_alpha_state *state)
403 {
404 unsigned db_depth_control, alpha_test_control, alpha_ref;
405 struct r600_dsa_state *dsa = CALLOC_STRUCT(r600_dsa_state);
406
407 if (!dsa) {
408 return NULL;
409 }
410
411 r600_init_command_buffer(&dsa->buffer, 3);
412
413 dsa->valuemask[0] = state->stencil[0].valuemask;
414 dsa->valuemask[1] = state->stencil[1].valuemask;
415 dsa->writemask[0] = state->stencil[0].writemask;
416 dsa->writemask[1] = state->stencil[1].writemask;
417 dsa->zwritemask = state->depth.writemask;
418
419 db_depth_control = S_028800_Z_ENABLE(state->depth.enabled) |
420 S_028800_Z_WRITE_ENABLE(state->depth.writemask) |
421 S_028800_ZFUNC(state->depth.func);
422
423 /* stencil */
424 if (state->stencil[0].enabled) {
425 db_depth_control |= S_028800_STENCIL_ENABLE(1);
426 db_depth_control |= S_028800_STENCILFUNC(state->stencil[0].func); /* translates straight */
427 db_depth_control |= S_028800_STENCILFAIL(r600_translate_stencil_op(state->stencil[0].fail_op));
428 db_depth_control |= S_028800_STENCILZPASS(r600_translate_stencil_op(state->stencil[0].zpass_op));
429 db_depth_control |= S_028800_STENCILZFAIL(r600_translate_stencil_op(state->stencil[0].zfail_op));
430
431 if (state->stencil[1].enabled) {
432 db_depth_control |= S_028800_BACKFACE_ENABLE(1);
433 db_depth_control |= S_028800_STENCILFUNC_BF(state->stencil[1].func); /* translates straight */
434 db_depth_control |= S_028800_STENCILFAIL_BF(r600_translate_stencil_op(state->stencil[1].fail_op));
435 db_depth_control |= S_028800_STENCILZPASS_BF(r600_translate_stencil_op(state->stencil[1].zpass_op));
436 db_depth_control |= S_028800_STENCILZFAIL_BF(r600_translate_stencil_op(state->stencil[1].zfail_op));
437 }
438 }
439
440 /* alpha */
441 alpha_test_control = 0;
442 alpha_ref = 0;
443 if (state->alpha.enabled) {
444 alpha_test_control = S_028410_ALPHA_FUNC(state->alpha.func);
445 alpha_test_control |= S_028410_ALPHA_TEST_ENABLE(1);
446 alpha_ref = fui(state->alpha.ref_value);
447 }
448 dsa->sx_alpha_test_control = alpha_test_control & 0xff;
449 dsa->alpha_ref = alpha_ref;
450
451 /* misc */
452 r600_store_context_reg(&dsa->buffer, R_028800_DB_DEPTH_CONTROL, db_depth_control);
453 return dsa;
454 }
455
456 static void *evergreen_create_rs_state(struct pipe_context *ctx,
457 const struct pipe_rasterizer_state *state)
458 {
459 struct r600_context *rctx = (struct r600_context *)ctx;
460 unsigned tmp, spi_interp;
461 float psize_min, psize_max;
462 struct r600_rasterizer_state *rs = CALLOC_STRUCT(r600_rasterizer_state);
463
464 if (!rs) {
465 return NULL;
466 }
467
468 r600_init_command_buffer(&rs->buffer, 30);
469
470 rs->scissor_enable = state->scissor;
471 rs->clip_halfz = state->clip_halfz;
472 rs->flatshade = state->flatshade;
473 rs->sprite_coord_enable = state->sprite_coord_enable;
474 rs->rasterizer_discard = state->rasterizer_discard;
475 rs->two_side = state->light_twoside;
476 rs->clip_plane_enable = state->clip_plane_enable;
477 rs->pa_sc_line_stipple = state->line_stipple_enable ?
478 S_028A0C_LINE_PATTERN(state->line_stipple_pattern) |
479 S_028A0C_REPEAT_COUNT(state->line_stipple_factor) : 0;
480 rs->pa_cl_clip_cntl =
481 S_028810_DX_CLIP_SPACE_DEF(state->clip_halfz) |
482 S_028810_ZCLIP_NEAR_DISABLE(!state->depth_clip) |
483 S_028810_ZCLIP_FAR_DISABLE(!state->depth_clip) |
484 S_028810_DX_LINEAR_ATTR_CLIP_ENA(1) |
485 S_028810_DX_RASTERIZATION_KILL(state->rasterizer_discard);
486 rs->multisample_enable = state->multisample;
487
488 /* offset */
489 rs->offset_units = state->offset_units;
490 rs->offset_scale = state->offset_scale * 16.0f;
491 rs->offset_enable = state->offset_point || state->offset_line || state->offset_tri;
492 rs->offset_units_unscaled = state->offset_units_unscaled;
493
494 if (state->point_size_per_vertex) {
495 psize_min = util_get_min_point_size(state);
496 psize_max = 8192;
497 } else {
498 /* Force the point size to be as if the vertex output was disabled. */
499 psize_min = state->point_size;
500 psize_max = state->point_size;
501 }
502
503 spi_interp = S_0286D4_FLAT_SHADE_ENA(1);
504 if (state->sprite_coord_enable) {
505 spi_interp |= S_0286D4_PNT_SPRITE_ENA(1) |
506 S_0286D4_PNT_SPRITE_OVRD_X(2) |
507 S_0286D4_PNT_SPRITE_OVRD_Y(3) |
508 S_0286D4_PNT_SPRITE_OVRD_Z(0) |
509 S_0286D4_PNT_SPRITE_OVRD_W(1);
510 if (state->sprite_coord_mode != PIPE_SPRITE_COORD_UPPER_LEFT) {
511 spi_interp |= S_0286D4_PNT_SPRITE_TOP_1(1);
512 }
513 }
514
515 r600_store_context_reg_seq(&rs->buffer, R_028A00_PA_SU_POINT_SIZE, 3);
516 /* point size 12.4 fixed point (divide by two, because 0.5 = 1 pixel) */
517 tmp = r600_pack_float_12p4(state->point_size/2);
518 r600_store_value(&rs->buffer, /* R_028A00_PA_SU_POINT_SIZE */
519 S_028A00_HEIGHT(tmp) | S_028A00_WIDTH(tmp));
520 r600_store_value(&rs->buffer, /* R_028A04_PA_SU_POINT_MINMAX */
521 S_028A04_MIN_SIZE(r600_pack_float_12p4(psize_min/2)) |
522 S_028A04_MAX_SIZE(r600_pack_float_12p4(psize_max/2)));
523 r600_store_value(&rs->buffer, /* R_028A08_PA_SU_LINE_CNTL */
524 S_028A08_WIDTH((unsigned)(state->line_width * 8)));
525
526 r600_store_context_reg(&rs->buffer, R_0286D4_SPI_INTERP_CONTROL_0, spi_interp);
527 r600_store_context_reg(&rs->buffer, R_028A48_PA_SC_MODE_CNTL_0,
528 S_028A48_MSAA_ENABLE(state->multisample) |
529 S_028A48_VPORT_SCISSOR_ENABLE(1) |
530 S_028A48_LINE_STIPPLE_ENABLE(state->line_stipple_enable));
531
532 if (rctx->b.chip_class == CAYMAN) {
533 r600_store_context_reg(&rs->buffer, CM_R_028BE4_PA_SU_VTX_CNTL,
534 S_028C08_PIX_CENTER_HALF(state->half_pixel_center) |
535 S_028C08_QUANT_MODE(V_028C08_X_1_256TH));
536 } else {
537 r600_store_context_reg(&rs->buffer, R_028C08_PA_SU_VTX_CNTL,
538 S_028C08_PIX_CENTER_HALF(state->half_pixel_center) |
539 S_028C08_QUANT_MODE(V_028C08_X_1_256TH));
540 }
541
542 r600_store_context_reg(&rs->buffer, R_028B7C_PA_SU_POLY_OFFSET_CLAMP, fui(state->offset_clamp));
543 r600_store_context_reg(&rs->buffer, R_028814_PA_SU_SC_MODE_CNTL,
544 S_028814_PROVOKING_VTX_LAST(!state->flatshade_first) |
545 S_028814_CULL_FRONT((state->cull_face & PIPE_FACE_FRONT) ? 1 : 0) |
546 S_028814_CULL_BACK((state->cull_face & PIPE_FACE_BACK) ? 1 : 0) |
547 S_028814_FACE(!state->front_ccw) |
548 S_028814_POLY_OFFSET_FRONT_ENABLE(util_get_offset(state, state->fill_front)) |
549 S_028814_POLY_OFFSET_BACK_ENABLE(util_get_offset(state, state->fill_back)) |
550 S_028814_POLY_OFFSET_PARA_ENABLE(state->offset_point || state->offset_line) |
551 S_028814_POLY_MODE(state->fill_front != PIPE_POLYGON_MODE_FILL ||
552 state->fill_back != PIPE_POLYGON_MODE_FILL) |
553 S_028814_POLYMODE_FRONT_PTYPE(r600_translate_fill(state->fill_front)) |
554 S_028814_POLYMODE_BACK_PTYPE(r600_translate_fill(state->fill_back)));
555 return rs;
556 }
557
558 static void *evergreen_create_sampler_state(struct pipe_context *ctx,
559 const struct pipe_sampler_state *state)
560 {
561 struct r600_common_screen *rscreen = (struct r600_common_screen*)ctx->screen;
562 struct r600_pipe_sampler_state *ss = CALLOC_STRUCT(r600_pipe_sampler_state);
563 unsigned max_aniso = rscreen->force_aniso >= 0 ? rscreen->force_aniso
564 : state->max_anisotropy;
565 unsigned max_aniso_ratio = r600_tex_aniso_filter(max_aniso);
566
567 if (!ss) {
568 return NULL;
569 }
570
571 ss->border_color_use = sampler_state_needs_border_color(state);
572
573 /* R_03C000_SQ_TEX_SAMPLER_WORD0_0 */
574 ss->tex_sampler_words[0] =
575 S_03C000_CLAMP_X(r600_tex_wrap(state->wrap_s)) |
576 S_03C000_CLAMP_Y(r600_tex_wrap(state->wrap_t)) |
577 S_03C000_CLAMP_Z(r600_tex_wrap(state->wrap_r)) |
578 S_03C000_XY_MAG_FILTER(eg_tex_filter(state->mag_img_filter, max_aniso)) |
579 S_03C000_XY_MIN_FILTER(eg_tex_filter(state->min_img_filter, max_aniso)) |
580 S_03C000_MIP_FILTER(r600_tex_mipfilter(state->min_mip_filter)) |
581 S_03C000_MAX_ANISO_RATIO(max_aniso_ratio) |
582 S_03C000_DEPTH_COMPARE_FUNCTION(r600_tex_compare(state->compare_func)) |
583 S_03C000_BORDER_COLOR_TYPE(ss->border_color_use ? V_03C000_SQ_TEX_BORDER_COLOR_REGISTER : 0);
584 /* R_03C004_SQ_TEX_SAMPLER_WORD1_0 */
585 ss->tex_sampler_words[1] =
586 S_03C004_MIN_LOD(S_FIXED(CLAMP(state->min_lod, 0, 15), 8)) |
587 S_03C004_MAX_LOD(S_FIXED(CLAMP(state->max_lod, 0, 15), 8));
588 /* R_03C008_SQ_TEX_SAMPLER_WORD2_0 */
589 ss->tex_sampler_words[2] =
590 S_03C008_LOD_BIAS(S_FIXED(CLAMP(state->lod_bias, -16, 16), 8)) |
591 (state->seamless_cube_map ? 0 : S_03C008_DISABLE_CUBE_WRAP(1)) |
592 S_03C008_TYPE(1);
593
594 if (ss->border_color_use) {
595 memcpy(&ss->border_color, &state->border_color, sizeof(state->border_color));
596 }
597 return ss;
598 }
599
600 struct eg_buf_res_params {
601 enum pipe_format pipe_format;
602 unsigned offset;
603 unsigned size;
604 unsigned char swizzle[4];
605 bool uncached;
606 };
607
608 static void evergreen_fill_buffer_resource_words(struct r600_context *rctx,
609 struct pipe_resource *buffer,
610 struct eg_buf_res_params *params,
611 bool *skip_mip_address_reloc,
612 unsigned tex_resource_words[8])
613 {
614 struct r600_texture *tmp = (struct r600_texture*)buffer;
615 uint64_t va;
616 int stride = util_format_get_blocksize(params->pipe_format);
617 unsigned format, num_format, format_comp, endian;
618 unsigned swizzle_res;
619 const struct util_format_description *desc;
620
621 r600_vertex_data_type(params->pipe_format,
622 &format, &num_format, &format_comp,
623 &endian);
624
625 desc = util_format_description(params->pipe_format);
626
627 swizzle_res = r600_get_swizzle_combined(desc->swizzle, params->swizzle, TRUE);
628
629 va = tmp->resource.gpu_address + params->offset;
630 *skip_mip_address_reloc = true;
631 tex_resource_words[0] = va;
632 tex_resource_words[1] = params->size - 1;
633 tex_resource_words[2] = S_030008_BASE_ADDRESS_HI(va >> 32UL) |
634 S_030008_STRIDE(stride) |
635 S_030008_DATA_FORMAT(format) |
636 S_030008_NUM_FORMAT_ALL(num_format) |
637 S_030008_FORMAT_COMP_ALL(format_comp) |
638 S_030008_ENDIAN_SWAP(endian);
639 tex_resource_words[3] = swizzle_res | S_03000C_UNCACHED(params->uncached);
640 /*
641 * in theory dword 4 is for number of elements, for use with resinfo,
642 * but it seems to utterly fail to work, the amd gpu shader analyser
643 * uses a const buffer to store the element sizes for buffer txq
644 */
645 tex_resource_words[4] = 0;
646 tex_resource_words[5] = tex_resource_words[6] = 0;
647 tex_resource_words[7] = S_03001C_TYPE(V_03001C_SQ_TEX_VTX_VALID_BUFFER);
648 }
649
650 static struct pipe_sampler_view *
651 texture_buffer_sampler_view(struct r600_context *rctx,
652 struct r600_pipe_sampler_view *view,
653 unsigned width0, unsigned height0)
654 {
655 struct r600_texture *tmp = (struct r600_texture*)view->base.texture;
656 struct eg_buf_res_params params;
657
658 memset(&params, 0, sizeof(params));
659
660 params.pipe_format = view->base.format;
661 params.offset = view->base.u.buf.offset;
662 params.size = view->base.u.buf.size;
663 params.swizzle[0] = view->base.swizzle_r;
664 params.swizzle[1] = view->base.swizzle_g;
665 params.swizzle[2] = view->base.swizzle_b;
666 params.swizzle[3] = view->base.swizzle_a;
667
668 evergreen_fill_buffer_resource_words(rctx, view->base.texture,
669 &params, &view->skip_mip_address_reloc,
670 view->tex_resource_words);
671 view->tex_resource = &tmp->resource;
672
673 if (tmp->resource.gpu_address)
674 LIST_ADDTAIL(&view->list, &rctx->texture_buffers);
675 return &view->base;
676 }
677
678 struct eg_tex_res_params {
679 enum pipe_format pipe_format;
680 int force_level;
681 unsigned width0;
682 unsigned height0;
683 unsigned first_level;
684 unsigned last_level;
685 unsigned first_layer;
686 unsigned last_layer;
687 unsigned target;
688 unsigned char swizzle[4];
689 };
690
691 static int evergreen_fill_tex_resource_words(struct r600_context *rctx,
692 struct pipe_resource *texture,
693 struct eg_tex_res_params *params,
694 bool *skip_mip_address_reloc,
695 unsigned tex_resource_words[8])
696 {
697 struct r600_screen *rscreen = (struct r600_screen*)rctx->b.b.screen;
698 struct r600_texture *tmp = (struct r600_texture*)texture;
699 unsigned format, endian;
700 uint32_t word4 = 0, yuv_format = 0, pitch = 0;
701 unsigned char array_mode = 0, non_disp_tiling = 0;
702 unsigned height, depth, width;
703 unsigned macro_aspect, tile_split, bankh, bankw, nbanks, fmask_bankh;
704 struct legacy_surf_level *surflevel;
705 unsigned base_level, first_level, last_level;
706 unsigned dim, last_layer;
707 uint64_t va;
708 bool do_endian_swap = FALSE;
709
710 tile_split = tmp->surface.u.legacy.tile_split;
711 surflevel = tmp->surface.u.legacy.level;
712
713 /* Texturing with separate depth and stencil. */
714 if (tmp->db_compatible) {
715 switch (params->pipe_format) {
716 case PIPE_FORMAT_Z32_FLOAT_S8X24_UINT:
717 params->pipe_format = PIPE_FORMAT_Z32_FLOAT;
718 break;
719 case PIPE_FORMAT_X8Z24_UNORM:
720 case PIPE_FORMAT_S8_UINT_Z24_UNORM:
721 /* Z24 is always stored like this for DB
722 * compatibility.
723 */
724 params->pipe_format = PIPE_FORMAT_Z24X8_UNORM;
725 break;
726 case PIPE_FORMAT_X24S8_UINT:
727 case PIPE_FORMAT_S8X24_UINT:
728 case PIPE_FORMAT_X32_S8X24_UINT:
729 params->pipe_format = PIPE_FORMAT_S8_UINT;
730 tile_split = tmp->surface.u.legacy.stencil_tile_split;
731 surflevel = tmp->surface.u.legacy.stencil_level;
732 break;
733 default:;
734 }
735 }
736
737 if (R600_BIG_ENDIAN)
738 do_endian_swap = !tmp->db_compatible;
739
740 format = r600_translate_texformat(rctx->b.b.screen, params->pipe_format,
741 params->swizzle,
742 &word4, &yuv_format, do_endian_swap);
743 assert(format != ~0);
744 if (format == ~0) {
745 return -1;
746 }
747
748 endian = r600_colorformat_endian_swap(format, do_endian_swap);
749
750 base_level = 0;
751 first_level = params->first_level;
752 last_level = params->last_level;
753 width = params->width0;
754 height = params->height0;
755 depth = texture->depth0;
756
757 if (params->force_level) {
758 base_level = params->force_level;
759 first_level = 0;
760 last_level = 0;
761 width = u_minify(width, params->force_level);
762 height = u_minify(height, params->force_level);
763 depth = u_minify(depth, params->force_level);
764 }
765
766 pitch = surflevel[base_level].nblk_x * util_format_get_blockwidth(params->pipe_format);
767 non_disp_tiling = tmp->non_disp_tiling;
768
769 switch (surflevel[base_level].mode) {
770 default:
771 case RADEON_SURF_MODE_LINEAR_ALIGNED:
772 array_mode = V_028C70_ARRAY_LINEAR_ALIGNED;
773 break;
774 case RADEON_SURF_MODE_2D:
775 array_mode = V_028C70_ARRAY_2D_TILED_THIN1;
776 break;
777 case RADEON_SURF_MODE_1D:
778 array_mode = V_028C70_ARRAY_1D_TILED_THIN1;
779 break;
780 }
781 macro_aspect = tmp->surface.u.legacy.mtilea;
782 bankw = tmp->surface.u.legacy.bankw;
783 bankh = tmp->surface.u.legacy.bankh;
784 tile_split = eg_tile_split(tile_split);
785 macro_aspect = eg_macro_tile_aspect(macro_aspect);
786 bankw = eg_bank_wh(bankw);
787 bankh = eg_bank_wh(bankh);
788 fmask_bankh = eg_bank_wh(tmp->fmask.bank_height);
789
790 /* 128 bit formats require tile type = 1 */
791 if (rscreen->b.chip_class == CAYMAN) {
792 if (util_format_get_blocksize(params->pipe_format) >= 16)
793 non_disp_tiling = 1;
794 }
795 nbanks = eg_num_banks(rscreen->b.info.r600_num_banks);
796
797 if (params->target == PIPE_TEXTURE_1D_ARRAY) {
798 height = 1;
799 depth = texture->array_size;
800 } else if (params->target == PIPE_TEXTURE_2D_ARRAY) {
801 depth = texture->array_size;
802 } else if (params->target == PIPE_TEXTURE_CUBE_ARRAY)
803 depth = texture->array_size / 6;
804
805 va = tmp->resource.gpu_address;
806
807 /* array type views and views into array types need to use layer offset */
808 dim = params->target;
809 if (params->target != PIPE_TEXTURE_CUBE)
810 dim = MAX2(params->target, texture->target);
811
812 tex_resource_words[0] = (S_030000_DIM(r600_tex_dim(dim, texture->nr_samples)) |
813 S_030000_PITCH((pitch / 8) - 1) |
814 S_030000_TEX_WIDTH(width - 1));
815 if (rscreen->b.chip_class == CAYMAN)
816 tex_resource_words[0] |= CM_S_030000_NON_DISP_TILING_ORDER(non_disp_tiling);
817 else
818 tex_resource_words[0] |= S_030000_NON_DISP_TILING_ORDER(non_disp_tiling);
819 tex_resource_words[1] = (S_030004_TEX_HEIGHT(height - 1) |
820 S_030004_TEX_DEPTH(depth - 1) |
821 S_030004_ARRAY_MODE(array_mode));
822 tex_resource_words[2] = (surflevel[base_level].offset + va) >> 8;
823
824 *skip_mip_address_reloc = false;
825 /* TEX_RESOURCE_WORD3.MIP_ADDRESS */
826 if (texture->nr_samples > 1 && rscreen->has_compressed_msaa_texturing) {
827 if (tmp->is_depth) {
828 /* disable FMASK (0 = disabled) */
829 tex_resource_words[3] = 0;
830 *skip_mip_address_reloc = true;
831 } else {
832 /* FMASK should be in MIP_ADDRESS for multisample textures */
833 tex_resource_words[3] = (tmp->fmask.offset + va) >> 8;
834 }
835 } else if (last_level && texture->nr_samples <= 1) {
836 tex_resource_words[3] = (surflevel[1].offset + va) >> 8;
837 } else {
838 tex_resource_words[3] = (surflevel[base_level].offset + va) >> 8;
839 }
840
841 last_layer = params->last_layer;
842 if (params->target != texture->target && depth == 1) {
843 last_layer = params->first_layer;
844 }
845 tex_resource_words[4] = (word4 |
846 S_030010_ENDIAN_SWAP(endian));
847 tex_resource_words[5] = S_030014_BASE_ARRAY(params->first_layer) |
848 S_030014_LAST_ARRAY(last_layer);
849 tex_resource_words[6] = S_030018_TILE_SPLIT(tile_split);
850
851 if (texture->nr_samples > 1) {
852 unsigned log_samples = util_logbase2(texture->nr_samples);
853 if (rscreen->b.chip_class == CAYMAN) {
854 tex_resource_words[4] |= S_030010_LOG2_NUM_FRAGMENTS(log_samples);
855 }
856 /* LAST_LEVEL holds log2(nr_samples) for multisample textures */
857 tex_resource_words[5] |= S_030014_LAST_LEVEL(log_samples);
858 tex_resource_words[6] |= S_030018_FMASK_BANK_HEIGHT(fmask_bankh);
859 } else {
860 bool no_mip = first_level == last_level;
861
862 tex_resource_words[4] |= S_030010_BASE_LEVEL(first_level);
863 tex_resource_words[5] |= S_030014_LAST_LEVEL(last_level);
864 /* aniso max 16 samples */
865 tex_resource_words[6] |= S_030018_MAX_ANISO_RATIO(no_mip ? 0 : 4);
866 }
867
868 tex_resource_words[7] = S_03001C_DATA_FORMAT(format) |
869 S_03001C_TYPE(V_03001C_SQ_TEX_VTX_VALID_TEXTURE) |
870 S_03001C_BANK_WIDTH(bankw) |
871 S_03001C_BANK_HEIGHT(bankh) |
872 S_03001C_MACRO_TILE_ASPECT(macro_aspect) |
873 S_03001C_NUM_BANKS(nbanks) |
874 S_03001C_DEPTH_SAMPLE_ORDER(tmp->db_compatible);
875 return 0;
876 }
877
878 struct pipe_sampler_view *
879 evergreen_create_sampler_view_custom(struct pipe_context *ctx,
880 struct pipe_resource *texture,
881 const struct pipe_sampler_view *state,
882 unsigned width0, unsigned height0,
883 unsigned force_level)
884 {
885 struct r600_context *rctx = (struct r600_context*)ctx;
886 struct r600_pipe_sampler_view *view = CALLOC_STRUCT(r600_pipe_sampler_view);
887 struct r600_texture *tmp = (struct r600_texture*)texture;
888 struct eg_tex_res_params params;
889 int ret;
890
891 if (!view)
892 return NULL;
893
894 /* initialize base object */
895 view->base = *state;
896 view->base.texture = NULL;
897 pipe_reference(NULL, &texture->reference);
898 view->base.texture = texture;
899 view->base.reference.count = 1;
900 view->base.context = ctx;
901
902 if (state->target == PIPE_BUFFER)
903 return texture_buffer_sampler_view(rctx, view, width0, height0);
904
905 memset(&params, 0, sizeof(params));
906 params.pipe_format = state->format;
907 params.force_level = force_level;
908 params.width0 = width0;
909 params.height0 = height0;
910 params.first_level = state->u.tex.first_level;
911 params.last_level = state->u.tex.last_level;
912 params.first_layer = state->u.tex.first_layer;
913 params.last_layer = state->u.tex.last_layer;
914 params.target = state->target;
915 params.swizzle[0] = state->swizzle_r;
916 params.swizzle[1] = state->swizzle_g;
917 params.swizzle[2] = state->swizzle_b;
918 params.swizzle[3] = state->swizzle_a;
919
920 ret = evergreen_fill_tex_resource_words(rctx, texture, &params,
921 &view->skip_mip_address_reloc,
922 view->tex_resource_words);
923 if (ret != 0) {
924 FREE(view);
925 return NULL;
926 }
927
928 if (state->format == PIPE_FORMAT_X24S8_UINT ||
929 state->format == PIPE_FORMAT_S8X24_UINT ||
930 state->format == PIPE_FORMAT_X32_S8X24_UINT ||
931 state->format == PIPE_FORMAT_S8_UINT)
932 view->is_stencil_sampler = true;
933
934 view->tex_resource = &tmp->resource;
935
936 return &view->base;
937 }
938
939 static struct pipe_sampler_view *
940 evergreen_create_sampler_view(struct pipe_context *ctx,
941 struct pipe_resource *tex,
942 const struct pipe_sampler_view *state)
943 {
944 return evergreen_create_sampler_view_custom(ctx, tex, state,
945 tex->width0, tex->height0, 0);
946 }
947
948 static void evergreen_emit_config_state(struct r600_context *rctx, struct r600_atom *atom)
949 {
950 struct radeon_winsys_cs *cs = rctx->b.gfx.cs;
951 struct r600_config_state *a = (struct r600_config_state*)atom;
952
953 radeon_set_config_reg_seq(cs, R_008C04_SQ_GPR_RESOURCE_MGMT_1, 3);
954 if (a->dyn_gpr_enabled) {
955 radeon_emit(cs, S_008C04_NUM_CLAUSE_TEMP_GPRS(rctx->r6xx_num_clause_temp_gprs));
956 radeon_emit(cs, 0);
957 radeon_emit(cs, 0);
958 } else {
959 radeon_emit(cs, a->sq_gpr_resource_mgmt_1);
960 radeon_emit(cs, a->sq_gpr_resource_mgmt_2);
961 radeon_emit(cs, a->sq_gpr_resource_mgmt_3);
962 }
963 radeon_set_config_reg(cs, R_008D8C_SQ_DYN_GPR_CNTL_PS_FLUSH_REQ, (a->dyn_gpr_enabled << 8));
964 if (a->dyn_gpr_enabled) {
965 radeon_set_context_reg(cs, R_028838_SQ_DYN_GPR_RESOURCE_LIMIT_1,
966 S_028838_PS_GPRS(0x1e) |
967 S_028838_VS_GPRS(0x1e) |
968 S_028838_GS_GPRS(0x1e) |
969 S_028838_ES_GPRS(0x1e) |
970 S_028838_HS_GPRS(0x1e) |
971 S_028838_LS_GPRS(0x1e)); /* workaround for hw issues with dyn gpr - must set all limits to 240 instead of 0, 0x1e == 240 / 8*/
972 }
973 }
974
975 static void evergreen_emit_clip_state(struct r600_context *rctx, struct r600_atom *atom)
976 {
977 struct radeon_winsys_cs *cs = rctx->b.gfx.cs;
978 struct pipe_clip_state *state = &rctx->clip_state.state;
979
980 radeon_set_context_reg_seq(cs, R_0285BC_PA_CL_UCP0_X, 6*4);
981 radeon_emit_array(cs, (unsigned*)state, 6*4);
982 }
983
984 static void evergreen_set_polygon_stipple(struct pipe_context *ctx,
985 const struct pipe_poly_stipple *state)
986 {
987 }
988
989 static void evergreen_get_scissor_rect(struct r600_context *rctx,
990 unsigned tl_x, unsigned tl_y, unsigned br_x, unsigned br_y,
991 uint32_t *tl, uint32_t *br)
992 {
993 struct pipe_scissor_state scissor = {tl_x, tl_y, br_x, br_y};
994
995 evergreen_apply_scissor_bug_workaround(&rctx->b, &scissor);
996
997 *tl = S_028240_TL_X(scissor.minx) | S_028240_TL_Y(scissor.miny);
998 *br = S_028244_BR_X(scissor.maxx) | S_028244_BR_Y(scissor.maxy);
999 }
1000
1001 struct r600_tex_color_info {
1002 unsigned info;
1003 unsigned view;
1004 unsigned dim;
1005 unsigned pitch;
1006 unsigned slice;
1007 unsigned attrib;
1008 unsigned ntype;
1009 unsigned fmask;
1010 unsigned fmask_slice;
1011 uint64_t offset;
1012 boolean export_16bpc;
1013 };
1014
1015 static void evergreen_set_color_surface_buffer(struct r600_context *rctx,
1016 struct r600_resource *res,
1017 enum pipe_format pformat,
1018 unsigned first_element,
1019 unsigned last_element,
1020 struct r600_tex_color_info *color)
1021 {
1022 unsigned format, swap, ntype, endian;
1023 const struct util_format_description *desc;
1024 unsigned block_size = align(util_format_get_blocksize(res->b.b.format), 4);
1025 unsigned pitch_alignment =
1026 MAX2(64, rctx->screen->b.info.pipe_interleave_bytes / block_size);
1027 unsigned pitch = align(res->b.b.width0, pitch_alignment);
1028 int i;
1029 unsigned width_elements;
1030
1031 width_elements = last_element - first_element + 1;
1032
1033 format = r600_translate_colorformat(rctx->b.chip_class, pformat, FALSE);
1034 swap = r600_translate_colorswap(pformat, FALSE);
1035
1036 endian = r600_colorformat_endian_swap(format, FALSE);
1037
1038 desc = util_format_description(pformat);
1039 for (i = 0; i < 4; i++) {
1040 if (desc->channel[i].type != UTIL_FORMAT_TYPE_VOID) {
1041 break;
1042 }
1043 }
1044 ntype = V_028C70_NUMBER_UNORM;
1045 if (desc->colorspace == UTIL_FORMAT_COLORSPACE_SRGB)
1046 ntype = V_028C70_NUMBER_SRGB;
1047 else if (desc->channel[i].type == UTIL_FORMAT_TYPE_SIGNED) {
1048 if (desc->channel[i].normalized)
1049 ntype = V_028C70_NUMBER_SNORM;
1050 else if (desc->channel[i].pure_integer)
1051 ntype = V_028C70_NUMBER_SINT;
1052 } else if (desc->channel[i].type == UTIL_FORMAT_TYPE_UNSIGNED) {
1053 if (desc->channel[i].normalized)
1054 ntype = V_028C70_NUMBER_UNORM;
1055 else if (desc->channel[i].pure_integer)
1056 ntype = V_028C70_NUMBER_UINT;
1057 }
1058 pitch = (pitch / 8) - 1;
1059 color->pitch = S_028C64_PITCH_TILE_MAX(pitch);
1060
1061 color->info = S_028C70_ARRAY_MODE(V_028C70_ARRAY_LINEAR_ALIGNED);
1062 color->info |= S_028C70_FORMAT(format) |
1063 S_028C70_COMP_SWAP(swap) |
1064 S_028C70_BLEND_CLAMP(0) |
1065 S_028C70_BLEND_BYPASS(1) |
1066 S_028C70_NUMBER_TYPE(ntype) |
1067 S_028C70_ENDIAN(endian);
1068 color->attrib = S_028C74_NON_DISP_TILING_ORDER(1);
1069 color->ntype = ntype;
1070 color->export_16bpc = false;
1071 color->dim = width_elements - 1;
1072 color->slice = 0; /* (width_elements / 64) - 1;*/
1073 color->view = 0;
1074 color->offset = res->gpu_address >> 8;
1075
1076 color->fmask = color->offset;
1077 color->fmask_slice = 0;
1078 }
1079
1080 static void evergreen_set_color_surface_common(struct r600_context *rctx,
1081 struct r600_texture *rtex,
1082 unsigned level,
1083 unsigned first_layer,
1084 unsigned last_layer,
1085 enum pipe_format pformat,
1086 struct r600_tex_color_info *color)
1087 {
1088 struct r600_screen *rscreen = rctx->screen;
1089 unsigned pitch, slice;
1090 unsigned non_disp_tiling, macro_aspect, tile_split, bankh, bankw, fmask_bankh, nbanks;
1091 unsigned format, swap, ntype, endian;
1092 const struct util_format_description *desc;
1093 bool blend_clamp = 0, blend_bypass = 0, do_endian_swap = FALSE;
1094 int i;
1095
1096 color->offset = rtex->surface.u.legacy.level[level].offset;
1097 color->view = S_028C6C_SLICE_START(first_layer) |
1098 S_028C6C_SLICE_MAX(last_layer);
1099
1100 color->offset += rtex->resource.gpu_address;
1101 color->offset >>= 8;
1102
1103 color->dim = 0;
1104 pitch = (rtex->surface.u.legacy.level[level].nblk_x) / 8 - 1;
1105 slice = (rtex->surface.u.legacy.level[level].nblk_x * rtex->surface.u.legacy.level[level].nblk_y) / 64;
1106 if (slice) {
1107 slice = slice - 1;
1108 }
1109
1110 color->info = 0;
1111 switch (rtex->surface.u.legacy.level[level].mode) {
1112 default:
1113 case RADEON_SURF_MODE_LINEAR_ALIGNED:
1114 color->info = S_028C70_ARRAY_MODE(V_028C70_ARRAY_LINEAR_ALIGNED);
1115 non_disp_tiling = 1;
1116 break;
1117 case RADEON_SURF_MODE_1D:
1118 color->info = S_028C70_ARRAY_MODE(V_028C70_ARRAY_1D_TILED_THIN1);
1119 non_disp_tiling = rtex->non_disp_tiling;
1120 break;
1121 case RADEON_SURF_MODE_2D:
1122 color->info = S_028C70_ARRAY_MODE(V_028C70_ARRAY_2D_TILED_THIN1);
1123 non_disp_tiling = rtex->non_disp_tiling;
1124 break;
1125 }
1126 tile_split = rtex->surface.u.legacy.tile_split;
1127 macro_aspect = rtex->surface.u.legacy.mtilea;
1128 bankw = rtex->surface.u.legacy.bankw;
1129 bankh = rtex->surface.u.legacy.bankh;
1130 if (rtex->fmask.size)
1131 fmask_bankh = rtex->fmask.bank_height;
1132 else
1133 fmask_bankh = rtex->surface.u.legacy.bankh;
1134 tile_split = eg_tile_split(tile_split);
1135 macro_aspect = eg_macro_tile_aspect(macro_aspect);
1136 bankw = eg_bank_wh(bankw);
1137 bankh = eg_bank_wh(bankh);
1138 fmask_bankh = eg_bank_wh(fmask_bankh);
1139
1140 if (rscreen->b.chip_class == CAYMAN) {
1141 if (util_format_get_blocksize(pformat) >= 16)
1142 non_disp_tiling = 1;
1143 }
1144 nbanks = eg_num_banks(rscreen->b.info.r600_num_banks);
1145 desc = util_format_description(pformat);
1146 for (i = 0; i < 4; i++) {
1147 if (desc->channel[i].type != UTIL_FORMAT_TYPE_VOID) {
1148 break;
1149 }
1150 }
1151 color->attrib = S_028C74_TILE_SPLIT(tile_split)|
1152 S_028C74_NUM_BANKS(nbanks) |
1153 S_028C74_BANK_WIDTH(bankw) |
1154 S_028C74_BANK_HEIGHT(bankh) |
1155 S_028C74_MACRO_TILE_ASPECT(macro_aspect) |
1156 S_028C74_NON_DISP_TILING_ORDER(non_disp_tiling) |
1157 S_028C74_FMASK_BANK_HEIGHT(fmask_bankh);
1158
1159 if (rctx->b.chip_class == CAYMAN) {
1160 color->attrib |= S_028C74_FORCE_DST_ALPHA_1(desc->swizzle[3] ==
1161 PIPE_SWIZZLE_1);
1162
1163 if (rtex->resource.b.b.nr_samples > 1) {
1164 unsigned log_samples = util_logbase2(rtex->resource.b.b.nr_samples);
1165 color->attrib |= S_028C74_NUM_SAMPLES(log_samples) |
1166 S_028C74_NUM_FRAGMENTS(log_samples);
1167 }
1168 }
1169
1170 ntype = V_028C70_NUMBER_UNORM;
1171 if (desc->colorspace == UTIL_FORMAT_COLORSPACE_SRGB)
1172 ntype = V_028C70_NUMBER_SRGB;
1173 else if (desc->channel[i].type == UTIL_FORMAT_TYPE_SIGNED) {
1174 if (desc->channel[i].normalized)
1175 ntype = V_028C70_NUMBER_SNORM;
1176 else if (desc->channel[i].pure_integer)
1177 ntype = V_028C70_NUMBER_SINT;
1178 } else if (desc->channel[i].type == UTIL_FORMAT_TYPE_UNSIGNED) {
1179 if (desc->channel[i].normalized)
1180 ntype = V_028C70_NUMBER_UNORM;
1181 else if (desc->channel[i].pure_integer)
1182 ntype = V_028C70_NUMBER_UINT;
1183 }
1184
1185 if (R600_BIG_ENDIAN)
1186 do_endian_swap = !rtex->db_compatible;
1187
1188 format = r600_translate_colorformat(rctx->b.chip_class, pformat, do_endian_swap);
1189 assert(format != ~0);
1190 swap = r600_translate_colorswap(pformat, do_endian_swap);
1191 assert(swap != ~0);
1192
1193 endian = r600_colorformat_endian_swap(format, do_endian_swap);
1194
1195 /* blend clamp should be set for all NORM/SRGB types */
1196 if (ntype == V_028C70_NUMBER_UNORM || ntype == V_028C70_NUMBER_SNORM ||
1197 ntype == V_028C70_NUMBER_SRGB)
1198 blend_clamp = 1;
1199
1200 /* set blend bypass according to docs if SINT/UINT or
1201 8/24 COLOR variants */
1202 if (ntype == V_028C70_NUMBER_UINT || ntype == V_028C70_NUMBER_SINT ||
1203 format == V_028C70_COLOR_8_24 || format == V_028C70_COLOR_24_8 ||
1204 format == V_028C70_COLOR_X24_8_32_FLOAT) {
1205 blend_clamp = 0;
1206 blend_bypass = 1;
1207 }
1208
1209 color->ntype = ntype;
1210 color->info |= S_028C70_FORMAT(format) |
1211 S_028C70_COMP_SWAP(swap) |
1212 S_028C70_BLEND_CLAMP(blend_clamp) |
1213 S_028C70_BLEND_BYPASS(blend_bypass) |
1214 S_028C70_NUMBER_TYPE(ntype) |
1215 S_028C70_ENDIAN(endian);
1216
1217 if (rtex->fmask.size) {
1218 color->info |= S_028C70_COMPRESSION(1);
1219 }
1220
1221 /* EXPORT_NORM is an optimzation that can be enabled for better
1222 * performance in certain cases.
1223 * EXPORT_NORM can be enabled if:
1224 * - 11-bit or smaller UNORM/SNORM/SRGB
1225 * - 16-bit or smaller FLOAT
1226 */
1227 color->export_16bpc = false;
1228 if (desc->colorspace != UTIL_FORMAT_COLORSPACE_ZS &&
1229 ((desc->channel[i].size < 12 &&
1230 desc->channel[i].type != UTIL_FORMAT_TYPE_FLOAT &&
1231 ntype != V_028C70_NUMBER_UINT && ntype != V_028C70_NUMBER_SINT) ||
1232 (desc->channel[i].size < 17 &&
1233 desc->channel[i].type == UTIL_FORMAT_TYPE_FLOAT))) {
1234 color->info |= S_028C70_SOURCE_FORMAT(V_028C70_EXPORT_4C_16BPC);
1235 color->export_16bpc = true;
1236 }
1237
1238 color->pitch = S_028C64_PITCH_TILE_MAX(pitch);
1239 color->slice = S_028C68_SLICE_TILE_MAX(slice);
1240
1241 if (rtex->fmask.size) {
1242 color->fmask = (rtex->resource.gpu_address + rtex->fmask.offset) >> 8;
1243 color->fmask_slice = S_028C88_TILE_MAX(rtex->fmask.slice_tile_max);
1244 } else {
1245 color->fmask = color->offset;
1246 color->fmask_slice = S_028C88_TILE_MAX(slice);
1247 }
1248 }
1249
1250 /**
1251 * This function intializes the CB* register values for RATs. It is meant
1252 * to be used for 1D aligned buffers that do not have an associated
1253 * radeon_surf.
1254 */
1255 void evergreen_init_color_surface_rat(struct r600_context *rctx,
1256 struct r600_surface *surf)
1257 {
1258 struct pipe_resource *pipe_buffer = surf->base.texture;
1259 struct r600_tex_color_info color;
1260
1261 evergreen_set_color_surface_buffer(rctx, (struct r600_resource *)surf->base.texture,
1262 surf->base.format, 0, pipe_buffer->width0,
1263 &color);
1264
1265 surf->cb_color_base = color.offset;
1266 surf->cb_color_dim = color.dim;
1267 surf->cb_color_info = color.info | S_028C70_RAT(1);
1268 surf->cb_color_pitch = color.pitch;
1269 surf->cb_color_slice = color.slice;
1270 surf->cb_color_view = color.view;
1271 surf->cb_color_attrib = color.attrib;
1272 surf->cb_color_fmask = color.fmask;
1273 surf->cb_color_fmask_slice = color.fmask_slice;
1274
1275 surf->cb_color_view = 0;
1276
1277 /* Set the buffer range the GPU will have access to: */
1278 util_range_add(&r600_resource(pipe_buffer)->valid_buffer_range,
1279 0, pipe_buffer->width0);
1280 }
1281
1282
1283 void evergreen_init_color_surface(struct r600_context *rctx,
1284 struct r600_surface *surf)
1285 {
1286 struct r600_texture *rtex = (struct r600_texture*)surf->base.texture;
1287 unsigned level = surf->base.u.tex.level;
1288 struct r600_tex_color_info color;
1289
1290 evergreen_set_color_surface_common(rctx, rtex, level,
1291 surf->base.u.tex.first_layer,
1292 surf->base.u.tex.last_layer,
1293 surf->base.format,
1294 &color);
1295
1296 surf->alphatest_bypass = color.ntype == V_028C70_NUMBER_UINT ||
1297 color.ntype == V_028C70_NUMBER_SINT;
1298 surf->export_16bpc = color.export_16bpc;
1299
1300 /* XXX handle enabling of CB beyond BASE8 which has different offset */
1301 surf->cb_color_base = color.offset;
1302 surf->cb_color_dim = color.dim;
1303 surf->cb_color_info = color.info;
1304 surf->cb_color_pitch = color.pitch;
1305 surf->cb_color_slice = color.slice;
1306 surf->cb_color_view = color.view;
1307 surf->cb_color_attrib = color.attrib;
1308 surf->cb_color_fmask = color.fmask;
1309 surf->cb_color_fmask_slice = color.fmask_slice;
1310
1311 surf->color_initialized = true;
1312 }
1313
1314 static void evergreen_init_depth_surface(struct r600_context *rctx,
1315 struct r600_surface *surf)
1316 {
1317 struct r600_screen *rscreen = rctx->screen;
1318 struct r600_texture *rtex = (struct r600_texture*)surf->base.texture;
1319 unsigned level = surf->base.u.tex.level;
1320 struct legacy_surf_level *levelinfo = &rtex->surface.u.legacy.level[level];
1321 uint64_t offset;
1322 unsigned format, array_mode;
1323 unsigned macro_aspect, tile_split, bankh, bankw, nbanks;
1324
1325
1326 format = r600_translate_dbformat(surf->base.format);
1327 assert(format != ~0);
1328
1329 offset = rtex->resource.gpu_address;
1330 offset += rtex->surface.u.legacy.level[level].offset;
1331
1332 switch (rtex->surface.u.legacy.level[level].mode) {
1333 case RADEON_SURF_MODE_2D:
1334 array_mode = V_028C70_ARRAY_2D_TILED_THIN1;
1335 break;
1336 case RADEON_SURF_MODE_1D:
1337 case RADEON_SURF_MODE_LINEAR_ALIGNED:
1338 default:
1339 array_mode = V_028C70_ARRAY_1D_TILED_THIN1;
1340 break;
1341 }
1342 tile_split = rtex->surface.u.legacy.tile_split;
1343 macro_aspect = rtex->surface.u.legacy.mtilea;
1344 bankw = rtex->surface.u.legacy.bankw;
1345 bankh = rtex->surface.u.legacy.bankh;
1346 tile_split = eg_tile_split(tile_split);
1347 macro_aspect = eg_macro_tile_aspect(macro_aspect);
1348 bankw = eg_bank_wh(bankw);
1349 bankh = eg_bank_wh(bankh);
1350 nbanks = eg_num_banks(rscreen->b.info.r600_num_banks);
1351 offset >>= 8;
1352
1353 surf->db_z_info = S_028040_ARRAY_MODE(array_mode) |
1354 S_028040_FORMAT(format) |
1355 S_028040_TILE_SPLIT(tile_split)|
1356 S_028040_NUM_BANKS(nbanks) |
1357 S_028040_BANK_WIDTH(bankw) |
1358 S_028040_BANK_HEIGHT(bankh) |
1359 S_028040_MACRO_TILE_ASPECT(macro_aspect);
1360 if (rscreen->b.chip_class == CAYMAN && rtex->resource.b.b.nr_samples > 1) {
1361 surf->db_z_info |= S_028040_NUM_SAMPLES(util_logbase2(rtex->resource.b.b.nr_samples));
1362 }
1363
1364 assert(levelinfo->nblk_x % 8 == 0 && levelinfo->nblk_y % 8 == 0);
1365
1366 surf->db_depth_base = offset;
1367 surf->db_depth_view = S_028008_SLICE_START(surf->base.u.tex.first_layer) |
1368 S_028008_SLICE_MAX(surf->base.u.tex.last_layer);
1369 surf->db_depth_size = S_028058_PITCH_TILE_MAX(levelinfo->nblk_x / 8 - 1) |
1370 S_028058_HEIGHT_TILE_MAX(levelinfo->nblk_y / 8 - 1);
1371 surf->db_depth_slice = S_02805C_SLICE_TILE_MAX(levelinfo->nblk_x *
1372 levelinfo->nblk_y / 64 - 1);
1373
1374 if (rtex->surface.flags & RADEON_SURF_SBUFFER) {
1375 uint64_t stencil_offset;
1376 unsigned stile_split = rtex->surface.u.legacy.stencil_tile_split;
1377
1378 stile_split = eg_tile_split(stile_split);
1379
1380 stencil_offset = rtex->surface.u.legacy.stencil_level[level].offset;
1381 stencil_offset += rtex->resource.gpu_address;
1382
1383 surf->db_stencil_base = stencil_offset >> 8;
1384 surf->db_stencil_info = S_028044_FORMAT(V_028044_STENCIL_8) |
1385 S_028044_TILE_SPLIT(stile_split);
1386 } else {
1387 surf->db_stencil_base = offset;
1388 /* DRM 2.6.18 allows the INVALID format to disable stencil.
1389 * Older kernels are out of luck. */
1390 surf->db_stencil_info = rctx->screen->b.info.drm_minor >= 18 ?
1391 S_028044_FORMAT(V_028044_STENCIL_INVALID) :
1392 S_028044_FORMAT(V_028044_STENCIL_8);
1393 }
1394
1395 /* use htile only for first level */
1396 if (rtex->htile_buffer && !level) {
1397 uint64_t va = rtex->htile_buffer->gpu_address;
1398 surf->db_htile_data_base = va >> 8;
1399 surf->db_htile_surface = S_028ABC_HTILE_WIDTH(1) |
1400 S_028ABC_HTILE_HEIGHT(1) |
1401 S_028ABC_FULL_CACHE(1);
1402 surf->db_z_info |= S_028040_TILE_SURFACE_ENABLE(1);
1403 surf->db_preload_control = 0;
1404 }
1405
1406 surf->depth_initialized = true;
1407 }
1408
1409 static void evergreen_set_framebuffer_state(struct pipe_context *ctx,
1410 const struct pipe_framebuffer_state *state)
1411 {
1412 struct r600_context *rctx = (struct r600_context *)ctx;
1413 struct r600_surface *surf;
1414 struct r600_texture *rtex;
1415 uint32_t i, log_samples;
1416
1417 /* Flush TC when changing the framebuffer state, because the only
1418 * client not using TC that can change textures is the framebuffer.
1419 * Other places don't typically have to flush TC.
1420 */
1421 rctx->b.flags |= R600_CONTEXT_WAIT_3D_IDLE |
1422 R600_CONTEXT_FLUSH_AND_INV |
1423 R600_CONTEXT_FLUSH_AND_INV_CB |
1424 R600_CONTEXT_FLUSH_AND_INV_CB_META |
1425 R600_CONTEXT_FLUSH_AND_INV_DB |
1426 R600_CONTEXT_FLUSH_AND_INV_DB_META |
1427 R600_CONTEXT_INV_TEX_CACHE;
1428
1429 util_copy_framebuffer_state(&rctx->framebuffer.state, state);
1430
1431 /* Colorbuffers. */
1432 rctx->framebuffer.export_16bpc = state->nr_cbufs != 0;
1433 rctx->framebuffer.cb0_is_integer = state->nr_cbufs && state->cbufs[0] &&
1434 util_format_is_pure_integer(state->cbufs[0]->format);
1435 rctx->framebuffer.compressed_cb_mask = 0;
1436 rctx->framebuffer.nr_samples = util_framebuffer_get_num_samples(state);
1437
1438 for (i = 0; i < state->nr_cbufs; i++) {
1439 surf = (struct r600_surface*)state->cbufs[i];
1440 if (!surf)
1441 continue;
1442
1443 rtex = (struct r600_texture*)surf->base.texture;
1444
1445 r600_context_add_resource_size(ctx, state->cbufs[i]->texture);
1446
1447 if (!surf->color_initialized) {
1448 evergreen_init_color_surface(rctx, surf);
1449 }
1450
1451 if (!surf->export_16bpc) {
1452 rctx->framebuffer.export_16bpc = false;
1453 }
1454
1455 if (rtex->fmask.size) {
1456 rctx->framebuffer.compressed_cb_mask |= 1 << i;
1457 }
1458 }
1459
1460 /* Update alpha-test state dependencies.
1461 * Alpha-test is done on the first colorbuffer only. */
1462 if (state->nr_cbufs) {
1463 bool alphatest_bypass = false;
1464 bool export_16bpc = true;
1465
1466 surf = (struct r600_surface*)state->cbufs[0];
1467 if (surf) {
1468 alphatest_bypass = surf->alphatest_bypass;
1469 export_16bpc = surf->export_16bpc;
1470 }
1471
1472 if (rctx->alphatest_state.bypass != alphatest_bypass) {
1473 rctx->alphatest_state.bypass = alphatest_bypass;
1474 r600_mark_atom_dirty(rctx, &rctx->alphatest_state.atom);
1475 }
1476 if (rctx->alphatest_state.cb0_export_16bpc != export_16bpc) {
1477 rctx->alphatest_state.cb0_export_16bpc = export_16bpc;
1478 r600_mark_atom_dirty(rctx, &rctx->alphatest_state.atom);
1479 }
1480 }
1481
1482 /* ZS buffer. */
1483 if (state->zsbuf) {
1484 surf = (struct r600_surface*)state->zsbuf;
1485
1486 r600_context_add_resource_size(ctx, state->zsbuf->texture);
1487
1488 if (!surf->depth_initialized) {
1489 evergreen_init_depth_surface(rctx, surf);
1490 }
1491
1492 if (state->zsbuf->format != rctx->poly_offset_state.zs_format) {
1493 rctx->poly_offset_state.zs_format = state->zsbuf->format;
1494 r600_mark_atom_dirty(rctx, &rctx->poly_offset_state.atom);
1495 }
1496
1497 if (rctx->db_state.rsurf != surf) {
1498 rctx->db_state.rsurf = surf;
1499 r600_mark_atom_dirty(rctx, &rctx->db_state.atom);
1500 r600_mark_atom_dirty(rctx, &rctx->db_misc_state.atom);
1501 }
1502 } else if (rctx->db_state.rsurf) {
1503 rctx->db_state.rsurf = NULL;
1504 r600_mark_atom_dirty(rctx, &rctx->db_state.atom);
1505 r600_mark_atom_dirty(rctx, &rctx->db_misc_state.atom);
1506 }
1507
1508 if (rctx->cb_misc_state.nr_cbufs != state->nr_cbufs) {
1509 rctx->cb_misc_state.nr_cbufs = state->nr_cbufs;
1510 r600_mark_atom_dirty(rctx, &rctx->cb_misc_state.atom);
1511 }
1512
1513 if (state->nr_cbufs == 0 && rctx->alphatest_state.bypass) {
1514 rctx->alphatest_state.bypass = false;
1515 r600_mark_atom_dirty(rctx, &rctx->alphatest_state.atom);
1516 }
1517
1518 log_samples = util_logbase2(rctx->framebuffer.nr_samples);
1519 /* This is for Cayman to program SAMPLE_RATE, and for RV770 to fix a hw bug. */
1520 if ((rctx->b.chip_class == CAYMAN ||
1521 rctx->b.family == CHIP_RV770) &&
1522 rctx->db_misc_state.log_samples != log_samples) {
1523 rctx->db_misc_state.log_samples = log_samples;
1524 r600_mark_atom_dirty(rctx, &rctx->db_misc_state.atom);
1525 }
1526
1527
1528 /* Calculate the CS size. */
1529 rctx->framebuffer.atom.num_dw = 4; /* SCISSOR */
1530
1531 /* MSAA. */
1532 if (rctx->b.chip_class == EVERGREEN)
1533 rctx->framebuffer.atom.num_dw += 17; /* Evergreen */
1534 else
1535 rctx->framebuffer.atom.num_dw += 28; /* Cayman */
1536
1537 /* Colorbuffers. */
1538 rctx->framebuffer.atom.num_dw += state->nr_cbufs * 23;
1539 rctx->framebuffer.atom.num_dw += state->nr_cbufs * 2;
1540 rctx->framebuffer.atom.num_dw += (12 - state->nr_cbufs) * 3;
1541
1542 /* ZS buffer. */
1543 if (state->zsbuf) {
1544 rctx->framebuffer.atom.num_dw += 24;
1545 rctx->framebuffer.atom.num_dw += 2;
1546 } else if (rctx->screen->b.info.drm_minor >= 18) {
1547 rctx->framebuffer.atom.num_dw += 4;
1548 }
1549
1550 r600_mark_atom_dirty(rctx, &rctx->framebuffer.atom);
1551
1552 r600_set_sample_locations_constant_buffer(rctx);
1553 }
1554
1555 static void evergreen_set_min_samples(struct pipe_context *ctx, unsigned min_samples)
1556 {
1557 struct r600_context *rctx = (struct r600_context *)ctx;
1558
1559 if (rctx->ps_iter_samples == min_samples)
1560 return;
1561
1562 rctx->ps_iter_samples = min_samples;
1563 if (rctx->framebuffer.nr_samples > 1) {
1564 r600_mark_atom_dirty(rctx, &rctx->framebuffer.atom);
1565 }
1566 }
1567
1568 /* 8xMSAA */
1569 static uint32_t sample_locs_8x[] = {
1570 FILL_SREG(-1, 1, 1, 5, 3, -5, 5, 3),
1571 FILL_SREG(-7, -1, -3, -7, 7, -3, -5, 7),
1572 FILL_SREG(-1, 1, 1, 5, 3, -5, 5, 3),
1573 FILL_SREG(-7, -1, -3, -7, 7, -3, -5, 7),
1574 FILL_SREG(-1, 1, 1, 5, 3, -5, 5, 3),
1575 FILL_SREG(-7, -1, -3, -7, 7, -3, -5, 7),
1576 FILL_SREG(-1, 1, 1, 5, 3, -5, 5, 3),
1577 FILL_SREG(-7, -1, -3, -7, 7, -3, -5, 7),
1578 };
1579 static unsigned max_dist_8x = 7;
1580
1581 static void evergreen_get_sample_position(struct pipe_context *ctx,
1582 unsigned sample_count,
1583 unsigned sample_index,
1584 float *out_value)
1585 {
1586 int offset, index;
1587 struct {
1588 int idx:4;
1589 } val;
1590 switch (sample_count) {
1591 case 1:
1592 default:
1593 out_value[0] = out_value[1] = 0.5;
1594 break;
1595 case 2:
1596 offset = 4 * (sample_index * 2);
1597 val.idx = (eg_sample_locs_2x[0] >> offset) & 0xf;
1598 out_value[0] = (float)(val.idx + 8) / 16.0f;
1599 val.idx = (eg_sample_locs_2x[0] >> (offset + 4)) & 0xf;
1600 out_value[1] = (float)(val.idx + 8) / 16.0f;
1601 break;
1602 case 4:
1603 offset = 4 * (sample_index * 2);
1604 val.idx = (eg_sample_locs_4x[0] >> offset) & 0xf;
1605 out_value[0] = (float)(val.idx + 8) / 16.0f;
1606 val.idx = (eg_sample_locs_4x[0] >> (offset + 4)) & 0xf;
1607 out_value[1] = (float)(val.idx + 8) / 16.0f;
1608 break;
1609 case 8:
1610 offset = 4 * (sample_index % 4 * 2);
1611 index = (sample_index / 4);
1612 val.idx = (sample_locs_8x[index] >> offset) & 0xf;
1613 out_value[0] = (float)(val.idx + 8) / 16.0f;
1614 val.idx = (sample_locs_8x[index] >> (offset + 4)) & 0xf;
1615 out_value[1] = (float)(val.idx + 8) / 16.0f;
1616 break;
1617 }
1618 }
1619
1620 static void evergreen_emit_msaa_state(struct r600_context *rctx, int nr_samples, int ps_iter_samples)
1621 {
1622
1623 struct radeon_winsys_cs *cs = rctx->b.gfx.cs;
1624 unsigned max_dist = 0;
1625
1626 switch (nr_samples) {
1627 default:
1628 nr_samples = 0;
1629 break;
1630 case 2:
1631 radeon_set_context_reg_seq(cs, R_028C1C_PA_SC_AA_SAMPLE_LOCS_0, ARRAY_SIZE(eg_sample_locs_2x));
1632 radeon_emit_array(cs, eg_sample_locs_2x, ARRAY_SIZE(eg_sample_locs_2x));
1633 max_dist = eg_max_dist_2x;
1634 break;
1635 case 4:
1636 radeon_set_context_reg_seq(cs, R_028C1C_PA_SC_AA_SAMPLE_LOCS_0, ARRAY_SIZE(eg_sample_locs_4x));
1637 radeon_emit_array(cs, eg_sample_locs_4x, ARRAY_SIZE(eg_sample_locs_4x));
1638 max_dist = eg_max_dist_4x;
1639 break;
1640 case 8:
1641 radeon_set_context_reg_seq(cs, R_028C1C_PA_SC_AA_SAMPLE_LOCS_0, ARRAY_SIZE(sample_locs_8x));
1642 radeon_emit_array(cs, sample_locs_8x, ARRAY_SIZE(sample_locs_8x));
1643 max_dist = max_dist_8x;
1644 break;
1645 }
1646
1647 if (nr_samples > 1) {
1648 radeon_set_context_reg_seq(cs, R_028C00_PA_SC_LINE_CNTL, 2);
1649 radeon_emit(cs, S_028C00_LAST_PIXEL(1) |
1650 S_028C00_EXPAND_LINE_WIDTH(1)); /* R_028C00_PA_SC_LINE_CNTL */
1651 radeon_emit(cs, S_028C04_MSAA_NUM_SAMPLES(util_logbase2(nr_samples)) |
1652 S_028C04_MAX_SAMPLE_DIST(max_dist)); /* R_028C04_PA_SC_AA_CONFIG */
1653 radeon_set_context_reg(cs, EG_R_028A4C_PA_SC_MODE_CNTL_1,
1654 EG_S_028A4C_PS_ITER_SAMPLE(ps_iter_samples > 1) |
1655 EG_S_028A4C_FORCE_EOV_CNTDWN_ENABLE(1) |
1656 EG_S_028A4C_FORCE_EOV_REZ_ENABLE(1));
1657 } else {
1658 radeon_set_context_reg_seq(cs, R_028C00_PA_SC_LINE_CNTL, 2);
1659 radeon_emit(cs, S_028C00_LAST_PIXEL(1)); /* R_028C00_PA_SC_LINE_CNTL */
1660 radeon_emit(cs, 0); /* R_028C04_PA_SC_AA_CONFIG */
1661 radeon_set_context_reg(cs, EG_R_028A4C_PA_SC_MODE_CNTL_1,
1662 EG_S_028A4C_FORCE_EOV_CNTDWN_ENABLE(1) |
1663 EG_S_028A4C_FORCE_EOV_REZ_ENABLE(1));
1664 }
1665 }
1666
1667 static void evergreen_emit_framebuffer_state(struct r600_context *rctx, struct r600_atom *atom)
1668 {
1669 struct radeon_winsys_cs *cs = rctx->b.gfx.cs;
1670 struct pipe_framebuffer_state *state = &rctx->framebuffer.state;
1671 unsigned nr_cbufs = state->nr_cbufs;
1672 unsigned i, tl, br;
1673 struct r600_texture *tex = NULL;
1674 struct r600_surface *cb = NULL;
1675
1676 /* XXX support more colorbuffers once we need them */
1677 assert(nr_cbufs <= 8);
1678 if (nr_cbufs > 8)
1679 nr_cbufs = 8;
1680
1681 /* Colorbuffers. */
1682 for (i = 0; i < nr_cbufs; i++) {
1683 unsigned reloc, cmask_reloc;
1684
1685 cb = (struct r600_surface*)state->cbufs[i];
1686 if (!cb) {
1687 radeon_set_context_reg(cs, R_028C70_CB_COLOR0_INFO + i * 0x3C,
1688 S_028C70_FORMAT(V_028C70_COLOR_INVALID));
1689 continue;
1690 }
1691
1692 tex = (struct r600_texture *)cb->base.texture;
1693 reloc = radeon_add_to_buffer_list(&rctx->b,
1694 &rctx->b.gfx,
1695 (struct r600_resource*)cb->base.texture,
1696 RADEON_USAGE_READWRITE,
1697 tex->resource.b.b.nr_samples > 1 ?
1698 RADEON_PRIO_COLOR_BUFFER_MSAA :
1699 RADEON_PRIO_COLOR_BUFFER);
1700
1701 if (tex->cmask_buffer && tex->cmask_buffer != &tex->resource) {
1702 cmask_reloc = radeon_add_to_buffer_list(&rctx->b, &rctx->b.gfx,
1703 tex->cmask_buffer, RADEON_USAGE_READWRITE,
1704 RADEON_PRIO_CMASK);
1705 } else {
1706 cmask_reloc = reloc;
1707 }
1708
1709 radeon_set_context_reg_seq(cs, R_028C60_CB_COLOR0_BASE + i * 0x3C, 13);
1710 radeon_emit(cs, cb->cb_color_base); /* R_028C60_CB_COLOR0_BASE */
1711 radeon_emit(cs, cb->cb_color_pitch); /* R_028C64_CB_COLOR0_PITCH */
1712 radeon_emit(cs, cb->cb_color_slice); /* R_028C68_CB_COLOR0_SLICE */
1713 radeon_emit(cs, cb->cb_color_view); /* R_028C6C_CB_COLOR0_VIEW */
1714 radeon_emit(cs, cb->cb_color_info | tex->cb_color_info); /* R_028C70_CB_COLOR0_INFO */
1715 radeon_emit(cs, cb->cb_color_attrib); /* R_028C74_CB_COLOR0_ATTRIB */
1716 radeon_emit(cs, cb->cb_color_dim); /* R_028C78_CB_COLOR0_DIM */
1717 radeon_emit(cs, tex->cmask.base_address_reg); /* R_028C7C_CB_COLOR0_CMASK */
1718 radeon_emit(cs, tex->cmask.slice_tile_max); /* R_028C80_CB_COLOR0_CMASK_SLICE */
1719 radeon_emit(cs, cb->cb_color_fmask); /* R_028C84_CB_COLOR0_FMASK */
1720 radeon_emit(cs, cb->cb_color_fmask_slice); /* R_028C88_CB_COLOR0_FMASK_SLICE */
1721 radeon_emit(cs, tex->color_clear_value[0]); /* R_028C8C_CB_COLOR0_CLEAR_WORD0 */
1722 radeon_emit(cs, tex->color_clear_value[1]); /* R_028C90_CB_COLOR0_CLEAR_WORD1 */
1723
1724 radeon_emit(cs, PKT3(PKT3_NOP, 0, 0)); /* R_028C60_CB_COLOR0_BASE */
1725 radeon_emit(cs, reloc);
1726
1727 radeon_emit(cs, PKT3(PKT3_NOP, 0, 0)); /* R_028C74_CB_COLOR0_ATTRIB */
1728 radeon_emit(cs, reloc);
1729
1730 radeon_emit(cs, PKT3(PKT3_NOP, 0, 0)); /* R_028C7C_CB_COLOR0_CMASK */
1731 radeon_emit(cs, cmask_reloc);
1732
1733 radeon_emit(cs, PKT3(PKT3_NOP, 0, 0)); /* R_028C84_CB_COLOR0_FMASK */
1734 radeon_emit(cs, reloc);
1735 }
1736 /* set CB_COLOR1_INFO for possible dual-src blending */
1737 if (rctx->framebuffer.dual_src_blend && i == 1 && state->cbufs[0]) {
1738 radeon_set_context_reg(cs, R_028C70_CB_COLOR0_INFO + 1 * 0x3C,
1739 cb->cb_color_info | tex->cb_color_info);
1740 i++;
1741 }
1742 for (; i < 8 ; i++)
1743 radeon_set_context_reg(cs, R_028C70_CB_COLOR0_INFO + i * 0x3C, 0);
1744 for (; i < 12; i++)
1745 radeon_set_context_reg(cs, R_028E50_CB_COLOR8_INFO + (i - 8) * 0x1C, 0);
1746
1747 /* ZS buffer. */
1748 if (state->zsbuf) {
1749 struct r600_surface *zb = (struct r600_surface*)state->zsbuf;
1750 unsigned reloc = radeon_add_to_buffer_list(&rctx->b,
1751 &rctx->b.gfx,
1752 (struct r600_resource*)state->zsbuf->texture,
1753 RADEON_USAGE_READWRITE,
1754 zb->base.texture->nr_samples > 1 ?
1755 RADEON_PRIO_DEPTH_BUFFER_MSAA :
1756 RADEON_PRIO_DEPTH_BUFFER);
1757
1758 radeon_set_context_reg(cs, R_028008_DB_DEPTH_VIEW, zb->db_depth_view);
1759
1760 radeon_set_context_reg_seq(cs, R_028040_DB_Z_INFO, 8);
1761 radeon_emit(cs, zb->db_z_info); /* R_028040_DB_Z_INFO */
1762 radeon_emit(cs, zb->db_stencil_info); /* R_028044_DB_STENCIL_INFO */
1763 radeon_emit(cs, zb->db_depth_base); /* R_028048_DB_Z_READ_BASE */
1764 radeon_emit(cs, zb->db_stencil_base); /* R_02804C_DB_STENCIL_READ_BASE */
1765 radeon_emit(cs, zb->db_depth_base); /* R_028050_DB_Z_WRITE_BASE */
1766 radeon_emit(cs, zb->db_stencil_base); /* R_028054_DB_STENCIL_WRITE_BASE */
1767 radeon_emit(cs, zb->db_depth_size); /* R_028058_DB_DEPTH_SIZE */
1768 radeon_emit(cs, zb->db_depth_slice); /* R_02805C_DB_DEPTH_SLICE */
1769
1770 radeon_emit(cs, PKT3(PKT3_NOP, 0, 0)); /* R_028048_DB_Z_READ_BASE */
1771 radeon_emit(cs, reloc);
1772
1773 radeon_emit(cs, PKT3(PKT3_NOP, 0, 0)); /* R_02804C_DB_STENCIL_READ_BASE */
1774 radeon_emit(cs, reloc);
1775
1776 radeon_emit(cs, PKT3(PKT3_NOP, 0, 0)); /* R_028050_DB_Z_WRITE_BASE */
1777 radeon_emit(cs, reloc);
1778
1779 radeon_emit(cs, PKT3(PKT3_NOP, 0, 0)); /* R_028054_DB_STENCIL_WRITE_BASE */
1780 radeon_emit(cs, reloc);
1781 } else if (rctx->screen->b.info.drm_minor >= 18) {
1782 /* DRM 2.6.18 allows the INVALID format to disable depth/stencil.
1783 * Older kernels are out of luck. */
1784 radeon_set_context_reg_seq(cs, R_028040_DB_Z_INFO, 2);
1785 radeon_emit(cs, S_028040_FORMAT(V_028040_Z_INVALID)); /* R_028040_DB_Z_INFO */
1786 radeon_emit(cs, S_028044_FORMAT(V_028044_STENCIL_INVALID)); /* R_028044_DB_STENCIL_INFO */
1787 }
1788
1789 /* Framebuffer dimensions. */
1790 evergreen_get_scissor_rect(rctx, 0, 0, state->width, state->height, &tl, &br);
1791
1792 radeon_set_context_reg_seq(cs, R_028204_PA_SC_WINDOW_SCISSOR_TL, 2);
1793 radeon_emit(cs, tl); /* R_028204_PA_SC_WINDOW_SCISSOR_TL */
1794 radeon_emit(cs, br); /* R_028208_PA_SC_WINDOW_SCISSOR_BR */
1795
1796 if (rctx->b.chip_class == EVERGREEN) {
1797 evergreen_emit_msaa_state(rctx, rctx->framebuffer.nr_samples, rctx->ps_iter_samples);
1798 } else {
1799 unsigned sc_mode_cntl_1 =
1800 EG_S_028A4C_FORCE_EOV_CNTDWN_ENABLE(1) |
1801 EG_S_028A4C_FORCE_EOV_REZ_ENABLE(1);
1802
1803 if (rctx->framebuffer.nr_samples > 1)
1804 cayman_emit_msaa_sample_locs(cs, rctx->framebuffer.nr_samples);
1805 cayman_emit_msaa_config(cs, rctx->framebuffer.nr_samples,
1806 rctx->ps_iter_samples, 0, sc_mode_cntl_1);
1807 }
1808 }
1809
1810 static void evergreen_emit_polygon_offset(struct r600_context *rctx, struct r600_atom *a)
1811 {
1812 struct radeon_winsys_cs *cs = rctx->b.gfx.cs;
1813 struct r600_poly_offset_state *state = (struct r600_poly_offset_state*)a;
1814 float offset_units = state->offset_units;
1815 float offset_scale = state->offset_scale;
1816 uint32_t pa_su_poly_offset_db_fmt_cntl = 0;
1817
1818 if (!state->offset_units_unscaled) {
1819 switch (state->zs_format) {
1820 case PIPE_FORMAT_Z24X8_UNORM:
1821 case PIPE_FORMAT_Z24_UNORM_S8_UINT:
1822 case PIPE_FORMAT_X8Z24_UNORM:
1823 case PIPE_FORMAT_S8_UINT_Z24_UNORM:
1824 offset_units *= 2.0f;
1825 pa_su_poly_offset_db_fmt_cntl =
1826 S_028B78_POLY_OFFSET_NEG_NUM_DB_BITS((char)-24);
1827 break;
1828 case PIPE_FORMAT_Z16_UNORM:
1829 offset_units *= 4.0f;
1830 pa_su_poly_offset_db_fmt_cntl =
1831 S_028B78_POLY_OFFSET_NEG_NUM_DB_BITS((char)-16);
1832 break;
1833 default:
1834 pa_su_poly_offset_db_fmt_cntl =
1835 S_028B78_POLY_OFFSET_NEG_NUM_DB_BITS((char)-23) |
1836 S_028B78_POLY_OFFSET_DB_IS_FLOAT_FMT(1);
1837 }
1838 }
1839
1840 radeon_set_context_reg_seq(cs, R_028B80_PA_SU_POLY_OFFSET_FRONT_SCALE, 4);
1841 radeon_emit(cs, fui(offset_scale));
1842 radeon_emit(cs, fui(offset_units));
1843 radeon_emit(cs, fui(offset_scale));
1844 radeon_emit(cs, fui(offset_units));
1845
1846 radeon_set_context_reg(cs, R_028B78_PA_SU_POLY_OFFSET_DB_FMT_CNTL,
1847 pa_su_poly_offset_db_fmt_cntl);
1848 }
1849
1850 static void evergreen_emit_cb_misc_state(struct r600_context *rctx, struct r600_atom *atom)
1851 {
1852 struct radeon_winsys_cs *cs = rctx->b.gfx.cs;
1853 struct r600_cb_misc_state *a = (struct r600_cb_misc_state*)atom;
1854 unsigned fb_colormask = (1ULL << ((unsigned)a->nr_cbufs * 4)) - 1;
1855 unsigned ps_colormask = (1ULL << ((unsigned)a->nr_ps_color_outputs * 4)) - 1;
1856
1857 radeon_set_context_reg_seq(cs, R_028238_CB_TARGET_MASK, 2);
1858 radeon_emit(cs, a->blend_colormask & fb_colormask); /* R_028238_CB_TARGET_MASK */
1859 /* This must match the used export instructions exactly.
1860 * Other values may lead to undefined behavior and hangs.
1861 */
1862 radeon_emit(cs, ps_colormask); /* R_02823C_CB_SHADER_MASK */
1863 }
1864
1865 static void evergreen_emit_db_state(struct r600_context *rctx, struct r600_atom *atom)
1866 {
1867 struct radeon_winsys_cs *cs = rctx->b.gfx.cs;
1868 struct r600_db_state *a = (struct r600_db_state*)atom;
1869
1870 if (a->rsurf && a->rsurf->db_htile_surface) {
1871 struct r600_texture *rtex = (struct r600_texture *)a->rsurf->base.texture;
1872 unsigned reloc_idx;
1873
1874 radeon_set_context_reg(cs, R_02802C_DB_DEPTH_CLEAR, fui(rtex->depth_clear_value));
1875 radeon_set_context_reg(cs, R_028ABC_DB_HTILE_SURFACE, a->rsurf->db_htile_surface);
1876 radeon_set_context_reg(cs, R_028AC8_DB_PRELOAD_CONTROL, a->rsurf->db_preload_control);
1877 radeon_set_context_reg(cs, R_028014_DB_HTILE_DATA_BASE, a->rsurf->db_htile_data_base);
1878 reloc_idx = radeon_add_to_buffer_list(&rctx->b, &rctx->b.gfx, rtex->htile_buffer,
1879 RADEON_USAGE_READWRITE, RADEON_PRIO_HTILE);
1880 radeon_emit(cs, PKT3(PKT3_NOP, 0, 0));
1881 radeon_emit(cs, reloc_idx);
1882 } else {
1883 radeon_set_context_reg(cs, R_028ABC_DB_HTILE_SURFACE, 0);
1884 radeon_set_context_reg(cs, R_028AC8_DB_PRELOAD_CONTROL, 0);
1885 }
1886 }
1887
1888 static void evergreen_emit_db_misc_state(struct r600_context *rctx, struct r600_atom *atom)
1889 {
1890 struct radeon_winsys_cs *cs = rctx->b.gfx.cs;
1891 struct r600_db_misc_state *a = (struct r600_db_misc_state*)atom;
1892 unsigned db_render_control = 0;
1893 unsigned db_count_control = 0;
1894 unsigned db_render_override =
1895 S_02800C_FORCE_HIS_ENABLE0(V_02800C_FORCE_DISABLE) |
1896 S_02800C_FORCE_HIS_ENABLE1(V_02800C_FORCE_DISABLE);
1897
1898 if (rctx->b.num_occlusion_queries > 0 &&
1899 !a->occlusion_queries_disabled) {
1900 db_count_control |= S_028004_PERFECT_ZPASS_COUNTS(1);
1901 if (rctx->b.chip_class == CAYMAN) {
1902 db_count_control |= S_028004_SAMPLE_RATE(a->log_samples);
1903 }
1904 db_render_override |= S_02800C_NOOP_CULL_DISABLE(1);
1905 } else {
1906 db_count_control |= S_028004_ZPASS_INCREMENT_DISABLE(1);
1907 }
1908
1909 /* This is to fix a lockup when hyperz and alpha test are enabled at
1910 * the same time somehow GPU get confuse on which order to pick for
1911 * z test
1912 */
1913 if (rctx->alphatest_state.sx_alpha_test_control)
1914 db_render_override |= S_02800C_FORCE_SHADER_Z_ORDER(1);
1915
1916 if (a->flush_depthstencil_through_cb) {
1917 assert(a->copy_depth || a->copy_stencil);
1918
1919 db_render_control |= S_028000_DEPTH_COPY_ENABLE(a->copy_depth) |
1920 S_028000_STENCIL_COPY_ENABLE(a->copy_stencil) |
1921 S_028000_COPY_CENTROID(1) |
1922 S_028000_COPY_SAMPLE(a->copy_sample);
1923 } else if (a->flush_depth_inplace || a->flush_stencil_inplace) {
1924 db_render_control |= S_028000_DEPTH_COMPRESS_DISABLE(a->flush_depth_inplace) |
1925 S_028000_STENCIL_COMPRESS_DISABLE(a->flush_stencil_inplace);
1926 db_render_override |= S_02800C_DISABLE_PIXEL_RATE_TILES(1);
1927 }
1928 if (a->htile_clear) {
1929 /* FIXME we might want to disable cliprect here */
1930 db_render_control |= S_028000_DEPTH_CLEAR_ENABLE(1);
1931 }
1932
1933 radeon_set_context_reg_seq(cs, R_028000_DB_RENDER_CONTROL, 2);
1934 radeon_emit(cs, db_render_control); /* R_028000_DB_RENDER_CONTROL */
1935 radeon_emit(cs, db_count_control); /* R_028004_DB_COUNT_CONTROL */
1936 radeon_set_context_reg(cs, R_02800C_DB_RENDER_OVERRIDE, db_render_override);
1937 radeon_set_context_reg(cs, R_02880C_DB_SHADER_CONTROL, a->db_shader_control);
1938 }
1939
1940 static void evergreen_emit_vertex_buffers(struct r600_context *rctx,
1941 struct r600_vertexbuf_state *state,
1942 unsigned resource_offset,
1943 unsigned pkt_flags)
1944 {
1945 struct radeon_winsys_cs *cs = rctx->b.gfx.cs;
1946 uint32_t dirty_mask = state->dirty_mask;
1947
1948 while (dirty_mask) {
1949 struct pipe_vertex_buffer *vb;
1950 struct r600_resource *rbuffer;
1951 uint64_t va;
1952 unsigned buffer_index = u_bit_scan(&dirty_mask);
1953
1954 vb = &state->vb[buffer_index];
1955 rbuffer = (struct r600_resource*)vb->buffer;
1956 assert(rbuffer);
1957
1958 va = rbuffer->gpu_address + vb->buffer_offset;
1959
1960 /* fetch resources start at index 992 */
1961 radeon_emit(cs, PKT3(PKT3_SET_RESOURCE, 8, 0) | pkt_flags);
1962 radeon_emit(cs, (resource_offset + buffer_index) * 8);
1963 radeon_emit(cs, va); /* RESOURCEi_WORD0 */
1964 radeon_emit(cs, rbuffer->b.b.width0 - vb->buffer_offset - 1); /* RESOURCEi_WORD1 */
1965 radeon_emit(cs, /* RESOURCEi_WORD2 */
1966 S_030008_ENDIAN_SWAP(r600_endian_swap(32)) |
1967 S_030008_STRIDE(vb->stride) |
1968 S_030008_BASE_ADDRESS_HI(va >> 32UL));
1969 radeon_emit(cs, /* RESOURCEi_WORD3 */
1970 S_03000C_DST_SEL_X(V_03000C_SQ_SEL_X) |
1971 S_03000C_DST_SEL_Y(V_03000C_SQ_SEL_Y) |
1972 S_03000C_DST_SEL_Z(V_03000C_SQ_SEL_Z) |
1973 S_03000C_DST_SEL_W(V_03000C_SQ_SEL_W));
1974 radeon_emit(cs, 0); /* RESOURCEi_WORD4 */
1975 radeon_emit(cs, 0); /* RESOURCEi_WORD5 */
1976 radeon_emit(cs, 0); /* RESOURCEi_WORD6 */
1977 radeon_emit(cs, 0xc0000000); /* RESOURCEi_WORD7 */
1978
1979 radeon_emit(cs, PKT3(PKT3_NOP, 0, 0) | pkt_flags);
1980 radeon_emit(cs, radeon_add_to_buffer_list(&rctx->b, &rctx->b.gfx, rbuffer,
1981 RADEON_USAGE_READ, RADEON_PRIO_VERTEX_BUFFER));
1982 }
1983 state->dirty_mask = 0;
1984 }
1985
1986 static void evergreen_fs_emit_vertex_buffers(struct r600_context *rctx, struct r600_atom * atom)
1987 {
1988 evergreen_emit_vertex_buffers(rctx, &rctx->vertex_buffer_state, EG_FETCH_CONSTANTS_OFFSET_FS, 0);
1989 }
1990
1991 static void evergreen_cs_emit_vertex_buffers(struct r600_context *rctx, struct r600_atom * atom)
1992 {
1993 evergreen_emit_vertex_buffers(rctx, &rctx->cs_vertex_buffer_state, EG_FETCH_CONSTANTS_OFFSET_CS,
1994 RADEON_CP_PACKET3_COMPUTE_MODE);
1995 }
1996
1997 static void evergreen_emit_constant_buffers(struct r600_context *rctx,
1998 struct r600_constbuf_state *state,
1999 unsigned buffer_id_base,
2000 unsigned reg_alu_constbuf_size,
2001 unsigned reg_alu_const_cache,
2002 unsigned pkt_flags)
2003 {
2004 struct radeon_winsys_cs *cs = rctx->b.gfx.cs;
2005 uint32_t dirty_mask = state->dirty_mask;
2006
2007 while (dirty_mask) {
2008 struct pipe_constant_buffer *cb;
2009 struct r600_resource *rbuffer;
2010 uint64_t va;
2011 unsigned buffer_index = ffs(dirty_mask) - 1;
2012 unsigned gs_ring_buffer = (buffer_index == R600_GS_RING_CONST_BUFFER);
2013
2014 cb = &state->cb[buffer_index];
2015 rbuffer = (struct r600_resource*)cb->buffer;
2016 assert(rbuffer);
2017
2018 va = rbuffer->gpu_address + cb->buffer_offset;
2019
2020 if (!gs_ring_buffer) {
2021 radeon_set_context_reg_flag(cs, reg_alu_constbuf_size + buffer_index * 4,
2022 DIV_ROUND_UP(cb->buffer_size, 256), pkt_flags);
2023 radeon_set_context_reg_flag(cs, reg_alu_const_cache + buffer_index * 4, va >> 8,
2024 pkt_flags);
2025 }
2026
2027 radeon_emit(cs, PKT3(PKT3_NOP, 0, 0) | pkt_flags);
2028 radeon_emit(cs, radeon_add_to_buffer_list(&rctx->b, &rctx->b.gfx, rbuffer,
2029 RADEON_USAGE_READ, RADEON_PRIO_CONST_BUFFER));
2030
2031 radeon_emit(cs, PKT3(PKT3_SET_RESOURCE, 8, 0) | pkt_flags);
2032 radeon_emit(cs, (buffer_id_base + buffer_index) * 8);
2033 radeon_emit(cs, va); /* RESOURCEi_WORD0 */
2034 radeon_emit(cs, rbuffer->b.b.width0 - cb->buffer_offset - 1); /* RESOURCEi_WORD1 */
2035 radeon_emit(cs, /* RESOURCEi_WORD2 */
2036 S_030008_ENDIAN_SWAP(gs_ring_buffer ? ENDIAN_NONE : r600_endian_swap(32)) |
2037 S_030008_STRIDE(gs_ring_buffer ? 4 : 16) |
2038 S_030008_BASE_ADDRESS_HI(va >> 32UL) |
2039 S_030008_DATA_FORMAT(FMT_32_32_32_32_FLOAT));
2040 radeon_emit(cs, /* RESOURCEi_WORD3 */
2041 S_03000C_UNCACHED(gs_ring_buffer ? 1 : 0) |
2042 S_03000C_DST_SEL_X(V_03000C_SQ_SEL_X) |
2043 S_03000C_DST_SEL_Y(V_03000C_SQ_SEL_Y) |
2044 S_03000C_DST_SEL_Z(V_03000C_SQ_SEL_Z) |
2045 S_03000C_DST_SEL_W(V_03000C_SQ_SEL_W));
2046 radeon_emit(cs, 0); /* RESOURCEi_WORD4 */
2047 radeon_emit(cs, 0); /* RESOURCEi_WORD5 */
2048 radeon_emit(cs, 0); /* RESOURCEi_WORD6 */
2049 radeon_emit(cs, /* RESOURCEi_WORD7 */
2050 S_03001C_TYPE(V_03001C_SQ_TEX_VTX_VALID_BUFFER));
2051
2052 radeon_emit(cs, PKT3(PKT3_NOP, 0, 0) | pkt_flags);
2053 radeon_emit(cs, radeon_add_to_buffer_list(&rctx->b, &rctx->b.gfx, rbuffer,
2054 RADEON_USAGE_READ, RADEON_PRIO_CONST_BUFFER));
2055
2056 dirty_mask &= ~(1 << buffer_index);
2057 }
2058 state->dirty_mask = 0;
2059 }
2060
2061 /* VS constants can be in VS/ES (same space) or LS if tess is enabled */
2062 static void evergreen_emit_vs_constant_buffers(struct r600_context *rctx, struct r600_atom *atom)
2063 {
2064 if (rctx->vs_shader->current->shader.vs_as_ls) {
2065 evergreen_emit_constant_buffers(rctx, &rctx->constbuf_state[PIPE_SHADER_VERTEX],
2066 EG_FETCH_CONSTANTS_OFFSET_LS,
2067 R_028FC0_ALU_CONST_BUFFER_SIZE_LS_0,
2068 R_028F40_ALU_CONST_CACHE_LS_0,
2069 0 /* PKT3 flags */);
2070 } else {
2071 evergreen_emit_constant_buffers(rctx, &rctx->constbuf_state[PIPE_SHADER_VERTEX],
2072 EG_FETCH_CONSTANTS_OFFSET_VS,
2073 R_028180_ALU_CONST_BUFFER_SIZE_VS_0,
2074 R_028980_ALU_CONST_CACHE_VS_0,
2075 0 /* PKT3 flags */);
2076 }
2077 }
2078
2079 static void evergreen_emit_gs_constant_buffers(struct r600_context *rctx, struct r600_atom *atom)
2080 {
2081 evergreen_emit_constant_buffers(rctx, &rctx->constbuf_state[PIPE_SHADER_GEOMETRY],
2082 EG_FETCH_CONSTANTS_OFFSET_GS,
2083 R_0281C0_ALU_CONST_BUFFER_SIZE_GS_0,
2084 R_0289C0_ALU_CONST_CACHE_GS_0,
2085 0 /* PKT3 flags */);
2086 }
2087
2088 static void evergreen_emit_ps_constant_buffers(struct r600_context *rctx, struct r600_atom *atom)
2089 {
2090 evergreen_emit_constant_buffers(rctx, &rctx->constbuf_state[PIPE_SHADER_FRAGMENT],
2091 EG_FETCH_CONSTANTS_OFFSET_PS,
2092 R_028140_ALU_CONST_BUFFER_SIZE_PS_0,
2093 R_028940_ALU_CONST_CACHE_PS_0,
2094 0 /* PKT3 flags */);
2095 }
2096
2097 static void evergreen_emit_cs_constant_buffers(struct r600_context *rctx, struct r600_atom *atom)
2098 {
2099 evergreen_emit_constant_buffers(rctx, &rctx->constbuf_state[PIPE_SHADER_COMPUTE],
2100 EG_FETCH_CONSTANTS_OFFSET_CS,
2101 R_028FC0_ALU_CONST_BUFFER_SIZE_LS_0,
2102 R_028F40_ALU_CONST_CACHE_LS_0,
2103 RADEON_CP_PACKET3_COMPUTE_MODE);
2104 }
2105
2106 /* tes constants can be emitted to VS or ES - which are common */
2107 static void evergreen_emit_tes_constant_buffers(struct r600_context *rctx, struct r600_atom *atom)
2108 {
2109 if (!rctx->tes_shader)
2110 return;
2111 evergreen_emit_constant_buffers(rctx, &rctx->constbuf_state[PIPE_SHADER_TESS_EVAL],
2112 EG_FETCH_CONSTANTS_OFFSET_VS,
2113 R_028180_ALU_CONST_BUFFER_SIZE_VS_0,
2114 R_028980_ALU_CONST_CACHE_VS_0,
2115 0);
2116 }
2117
2118 static void evergreen_emit_tcs_constant_buffers(struct r600_context *rctx, struct r600_atom *atom)
2119 {
2120 if (!rctx->tes_shader)
2121 return;
2122 evergreen_emit_constant_buffers(rctx, &rctx->constbuf_state[PIPE_SHADER_TESS_CTRL],
2123 EG_FETCH_CONSTANTS_OFFSET_HS,
2124 R_028F80_ALU_CONST_BUFFER_SIZE_HS_0,
2125 R_028F00_ALU_CONST_CACHE_HS_0,
2126 0);
2127 }
2128
2129 static void evergreen_emit_sampler_views(struct r600_context *rctx,
2130 struct r600_samplerview_state *state,
2131 unsigned resource_id_base, unsigned pkt_flags)
2132 {
2133 struct radeon_winsys_cs *cs = rctx->b.gfx.cs;
2134 uint32_t dirty_mask = state->dirty_mask;
2135
2136 while (dirty_mask) {
2137 struct r600_pipe_sampler_view *rview;
2138 unsigned resource_index = u_bit_scan(&dirty_mask);
2139 unsigned reloc;
2140
2141 rview = state->views[resource_index];
2142 assert(rview);
2143
2144 radeon_emit(cs, PKT3(PKT3_SET_RESOURCE, 8, 0) | pkt_flags);
2145 radeon_emit(cs, (resource_id_base + resource_index) * 8);
2146 radeon_emit_array(cs, rview->tex_resource_words, 8);
2147
2148 reloc = radeon_add_to_buffer_list(&rctx->b, &rctx->b.gfx, rview->tex_resource,
2149 RADEON_USAGE_READ,
2150 r600_get_sampler_view_priority(rview->tex_resource));
2151 radeon_emit(cs, PKT3(PKT3_NOP, 0, 0) | pkt_flags);
2152 radeon_emit(cs, reloc);
2153
2154 if (!rview->skip_mip_address_reloc) {
2155 radeon_emit(cs, PKT3(PKT3_NOP, 0, 0) | pkt_flags);
2156 radeon_emit(cs, reloc);
2157 }
2158 }
2159 state->dirty_mask = 0;
2160 }
2161
2162 static void evergreen_emit_vs_sampler_views(struct r600_context *rctx, struct r600_atom *atom)
2163 {
2164 if (rctx->vs_shader->current->shader.vs_as_ls) {
2165 evergreen_emit_sampler_views(rctx, &rctx->samplers[PIPE_SHADER_VERTEX].views,
2166 EG_FETCH_CONSTANTS_OFFSET_LS + R600_MAX_CONST_BUFFERS, 0);
2167 } else {
2168 evergreen_emit_sampler_views(rctx, &rctx->samplers[PIPE_SHADER_VERTEX].views,
2169 EG_FETCH_CONSTANTS_OFFSET_VS + R600_MAX_CONST_BUFFERS, 0);
2170 }
2171 }
2172
2173 static void evergreen_emit_gs_sampler_views(struct r600_context *rctx, struct r600_atom *atom)
2174 {
2175 evergreen_emit_sampler_views(rctx, &rctx->samplers[PIPE_SHADER_GEOMETRY].views,
2176 EG_FETCH_CONSTANTS_OFFSET_GS + R600_MAX_CONST_BUFFERS, 0);
2177 }
2178
2179 static void evergreen_emit_tcs_sampler_views(struct r600_context *rctx, struct r600_atom *atom)
2180 {
2181 evergreen_emit_sampler_views(rctx, &rctx->samplers[PIPE_SHADER_TESS_CTRL].views,
2182 EG_FETCH_CONSTANTS_OFFSET_HS + R600_MAX_CONST_BUFFERS, 0);
2183 }
2184
2185 static void evergreen_emit_tes_sampler_views(struct r600_context *rctx, struct r600_atom *atom)
2186 {
2187 evergreen_emit_sampler_views(rctx, &rctx->samplers[PIPE_SHADER_TESS_EVAL].views,
2188 EG_FETCH_CONSTANTS_OFFSET_VS + R600_MAX_CONST_BUFFERS, 0);
2189 }
2190
2191 static void evergreen_emit_ps_sampler_views(struct r600_context *rctx, struct r600_atom *atom)
2192 {
2193 evergreen_emit_sampler_views(rctx, &rctx->samplers[PIPE_SHADER_FRAGMENT].views,
2194 EG_FETCH_CONSTANTS_OFFSET_PS + R600_MAX_CONST_BUFFERS, 0);
2195 }
2196
2197 static void evergreen_emit_cs_sampler_views(struct r600_context *rctx, struct r600_atom *atom)
2198 {
2199 evergreen_emit_sampler_views(rctx, &rctx->samplers[PIPE_SHADER_COMPUTE].views,
2200 EG_FETCH_CONSTANTS_OFFSET_CS + 2, RADEON_CP_PACKET3_COMPUTE_MODE);
2201 }
2202
2203 static void evergreen_emit_sampler_states(struct r600_context *rctx,
2204 struct r600_textures_info *texinfo,
2205 unsigned resource_id_base,
2206 unsigned border_index_reg,
2207 unsigned pkt_flags)
2208 {
2209 struct radeon_winsys_cs *cs = rctx->b.gfx.cs;
2210 uint32_t dirty_mask = texinfo->states.dirty_mask;
2211
2212 while (dirty_mask) {
2213 struct r600_pipe_sampler_state *rstate;
2214 unsigned i = u_bit_scan(&dirty_mask);
2215
2216 rstate = texinfo->states.states[i];
2217 assert(rstate);
2218
2219 radeon_emit(cs, PKT3(PKT3_SET_SAMPLER, 3, 0) | pkt_flags);
2220 radeon_emit(cs, (resource_id_base + i) * 3);
2221 radeon_emit_array(cs, rstate->tex_sampler_words, 3);
2222
2223 if (rstate->border_color_use) {
2224 radeon_set_config_reg_seq(cs, border_index_reg, 5);
2225 radeon_emit(cs, i);
2226 radeon_emit_array(cs, rstate->border_color.ui, 4);
2227 }
2228 }
2229 texinfo->states.dirty_mask = 0;
2230 }
2231
2232 static void evergreen_emit_vs_sampler_states(struct r600_context *rctx, struct r600_atom *atom)
2233 {
2234 if (rctx->vs_shader->current->shader.vs_as_ls) {
2235 evergreen_emit_sampler_states(rctx, &rctx->samplers[PIPE_SHADER_VERTEX], 72,
2236 R_00A450_TD_LS_SAMPLER0_BORDER_COLOR_INDEX, 0);
2237 } else {
2238 evergreen_emit_sampler_states(rctx, &rctx->samplers[PIPE_SHADER_VERTEX], 18,
2239 R_00A414_TD_VS_SAMPLER0_BORDER_INDEX, 0);
2240 }
2241 }
2242
2243 static void evergreen_emit_gs_sampler_states(struct r600_context *rctx, struct r600_atom *atom)
2244 {
2245 evergreen_emit_sampler_states(rctx, &rctx->samplers[PIPE_SHADER_GEOMETRY], 36,
2246 R_00A428_TD_GS_SAMPLER0_BORDER_INDEX, 0);
2247 }
2248
2249 static void evergreen_emit_tcs_sampler_states(struct r600_context *rctx, struct r600_atom *atom)
2250 {
2251 evergreen_emit_sampler_states(rctx, &rctx->samplers[PIPE_SHADER_TESS_CTRL], 54,
2252 R_00A43C_TD_HS_SAMPLER0_BORDER_COLOR_INDEX, 0);
2253 }
2254
2255 static void evergreen_emit_tes_sampler_states(struct r600_context *rctx, struct r600_atom *atom)
2256 {
2257 evergreen_emit_sampler_states(rctx, &rctx->samplers[PIPE_SHADER_TESS_EVAL], 18,
2258 R_00A414_TD_VS_SAMPLER0_BORDER_INDEX, 0);
2259 }
2260
2261 static void evergreen_emit_ps_sampler_states(struct r600_context *rctx, struct r600_atom *atom)
2262 {
2263 evergreen_emit_sampler_states(rctx, &rctx->samplers[PIPE_SHADER_FRAGMENT], 0,
2264 R_00A400_TD_PS_SAMPLER0_BORDER_INDEX, 0);
2265 }
2266
2267 static void evergreen_emit_cs_sampler_states(struct r600_context *rctx, struct r600_atom *atom)
2268 {
2269 evergreen_emit_sampler_states(rctx, &rctx->samplers[PIPE_SHADER_COMPUTE], 90,
2270 R_00A464_TD_CS_SAMPLER0_BORDER_INDEX,
2271 RADEON_CP_PACKET3_COMPUTE_MODE);
2272 }
2273
2274 static void evergreen_emit_sample_mask(struct r600_context *rctx, struct r600_atom *a)
2275 {
2276 struct r600_sample_mask *s = (struct r600_sample_mask*)a;
2277 uint8_t mask = s->sample_mask;
2278
2279 radeon_set_context_reg(rctx->b.gfx.cs, R_028C3C_PA_SC_AA_MASK,
2280 mask | (mask << 8) | (mask << 16) | (mask << 24));
2281 }
2282
2283 static void cayman_emit_sample_mask(struct r600_context *rctx, struct r600_atom *a)
2284 {
2285 struct r600_sample_mask *s = (struct r600_sample_mask*)a;
2286 struct radeon_winsys_cs *cs = rctx->b.gfx.cs;
2287 uint16_t mask = s->sample_mask;
2288
2289 radeon_set_context_reg_seq(cs, CM_R_028C38_PA_SC_AA_MASK_X0Y0_X1Y0, 2);
2290 radeon_emit(cs, mask | (mask << 16)); /* X0Y0_X1Y0 */
2291 radeon_emit(cs, mask | (mask << 16)); /* X0Y1_X1Y1 */
2292 }
2293
2294 static void evergreen_emit_vertex_fetch_shader(struct r600_context *rctx, struct r600_atom *a)
2295 {
2296 struct radeon_winsys_cs *cs = rctx->b.gfx.cs;
2297 struct r600_cso_state *state = (struct r600_cso_state*)a;
2298 struct r600_fetch_shader *shader = (struct r600_fetch_shader*)state->cso;
2299
2300 radeon_set_context_reg(cs, R_0288A4_SQ_PGM_START_FS,
2301 (shader->buffer->gpu_address + shader->offset) >> 8);
2302 radeon_emit(cs, PKT3(PKT3_NOP, 0, 0));
2303 radeon_emit(cs, radeon_add_to_buffer_list(&rctx->b, &rctx->b.gfx, shader->buffer,
2304 RADEON_USAGE_READ,
2305 RADEON_PRIO_SHADER_BINARY));
2306 }
2307
2308 static void evergreen_emit_shader_stages(struct r600_context *rctx, struct r600_atom *a)
2309 {
2310 struct radeon_winsys_cs *cs = rctx->b.gfx.cs;
2311 struct r600_shader_stages_state *state = (struct r600_shader_stages_state*)a;
2312
2313 uint32_t v = 0, v2 = 0, primid = 0, tf_param = 0;
2314
2315 if (rctx->vs_shader->current->shader.vs_as_gs_a) {
2316 v2 = S_028A40_MODE(V_028A40_GS_SCENARIO_A);
2317 primid = 1;
2318 }
2319
2320 if (state->geom_enable) {
2321 uint32_t cut_val;
2322
2323 if (rctx->gs_shader->gs_max_out_vertices <= 128)
2324 cut_val = V_028A40_GS_CUT_128;
2325 else if (rctx->gs_shader->gs_max_out_vertices <= 256)
2326 cut_val = V_028A40_GS_CUT_256;
2327 else if (rctx->gs_shader->gs_max_out_vertices <= 512)
2328 cut_val = V_028A40_GS_CUT_512;
2329 else
2330 cut_val = V_028A40_GS_CUT_1024;
2331
2332 v = S_028B54_GS_EN(1) |
2333 S_028B54_VS_EN(V_028B54_VS_STAGE_COPY_SHADER);
2334 if (!rctx->tes_shader)
2335 v |= S_028B54_ES_EN(V_028B54_ES_STAGE_REAL);
2336
2337 v2 = S_028A40_MODE(V_028A40_GS_SCENARIO_G) |
2338 S_028A40_CUT_MODE(cut_val);
2339
2340 if (rctx->gs_shader->current->shader.gs_prim_id_input)
2341 primid = 1;
2342 }
2343
2344 if (rctx->tes_shader) {
2345 uint32_t type, partitioning, topology;
2346 struct tgsi_shader_info *info = &rctx->tes_shader->current->selector->info;
2347 unsigned tes_prim_mode = info->properties[TGSI_PROPERTY_TES_PRIM_MODE];
2348 unsigned tes_spacing = info->properties[TGSI_PROPERTY_TES_SPACING];
2349 bool tes_vertex_order_cw = info->properties[TGSI_PROPERTY_TES_VERTEX_ORDER_CW];
2350 bool tes_point_mode = info->properties[TGSI_PROPERTY_TES_POINT_MODE];
2351 switch (tes_prim_mode) {
2352 case PIPE_PRIM_LINES:
2353 type = V_028B6C_TESS_ISOLINE;
2354 break;
2355 case PIPE_PRIM_TRIANGLES:
2356 type = V_028B6C_TESS_TRIANGLE;
2357 break;
2358 case PIPE_PRIM_QUADS:
2359 type = V_028B6C_TESS_QUAD;
2360 break;
2361 default:
2362 assert(0);
2363 return;
2364 }
2365
2366 switch (tes_spacing) {
2367 case PIPE_TESS_SPACING_FRACTIONAL_ODD:
2368 partitioning = V_028B6C_PART_FRAC_ODD;
2369 break;
2370 case PIPE_TESS_SPACING_FRACTIONAL_EVEN:
2371 partitioning = V_028B6C_PART_FRAC_EVEN;
2372 break;
2373 case PIPE_TESS_SPACING_EQUAL:
2374 partitioning = V_028B6C_PART_INTEGER;
2375 break;
2376 default:
2377 assert(0);
2378 return;
2379 }
2380
2381 if (tes_point_mode)
2382 topology = V_028B6C_OUTPUT_POINT;
2383 else if (tes_prim_mode == PIPE_PRIM_LINES)
2384 topology = V_028B6C_OUTPUT_LINE;
2385 else if (tes_vertex_order_cw)
2386 /* XXX follow radeonsi and invert */
2387 topology = V_028B6C_OUTPUT_TRIANGLE_CCW;
2388 else
2389 topology = V_028B6C_OUTPUT_TRIANGLE_CW;
2390
2391 tf_param = S_028B6C_TYPE(type) |
2392 S_028B6C_PARTITIONING(partitioning) |
2393 S_028B6C_TOPOLOGY(topology);
2394 }
2395
2396 if (rctx->tes_shader) {
2397 v |= S_028B54_LS_EN(V_028B54_LS_STAGE_ON) |
2398 S_028B54_HS_EN(1);
2399 if (!state->geom_enable)
2400 v |= S_028B54_VS_EN(V_028B54_VS_STAGE_DS);
2401 else
2402 v |= S_028B54_ES_EN(V_028B54_ES_STAGE_DS);
2403 }
2404
2405 radeon_set_context_reg(cs, R_028AB8_VGT_VTX_CNT_EN, v ? 1 : 0 );
2406 radeon_set_context_reg(cs, R_028B54_VGT_SHADER_STAGES_EN, v);
2407 radeon_set_context_reg(cs, R_028A40_VGT_GS_MODE, v2);
2408 radeon_set_context_reg(cs, R_028A84_VGT_PRIMITIVEID_EN, primid);
2409 radeon_set_context_reg(cs, R_028B6C_VGT_TF_PARAM, tf_param);
2410 }
2411
2412 static void evergreen_emit_gs_rings(struct r600_context *rctx, struct r600_atom *a)
2413 {
2414 struct radeon_winsys_cs *cs = rctx->b.gfx.cs;
2415 struct r600_gs_rings_state *state = (struct r600_gs_rings_state*)a;
2416 struct r600_resource *rbuffer;
2417
2418 radeon_set_config_reg(cs, R_008040_WAIT_UNTIL, S_008040_WAIT_3D_IDLE(1));
2419 radeon_emit(cs, PKT3(PKT3_EVENT_WRITE, 0, 0));
2420 radeon_emit(cs, EVENT_TYPE(EVENT_TYPE_VGT_FLUSH));
2421
2422 if (state->enable) {
2423 rbuffer =(struct r600_resource*)state->esgs_ring.buffer;
2424 radeon_set_config_reg(cs, R_008C40_SQ_ESGS_RING_BASE,
2425 rbuffer->gpu_address >> 8);
2426 radeon_emit(cs, PKT3(PKT3_NOP, 0, 0));
2427 radeon_emit(cs, radeon_add_to_buffer_list(&rctx->b, &rctx->b.gfx, rbuffer,
2428 RADEON_USAGE_READWRITE,
2429 RADEON_PRIO_SHADER_RINGS));
2430 radeon_set_config_reg(cs, R_008C44_SQ_ESGS_RING_SIZE,
2431 state->esgs_ring.buffer_size >> 8);
2432
2433 rbuffer =(struct r600_resource*)state->gsvs_ring.buffer;
2434 radeon_set_config_reg(cs, R_008C48_SQ_GSVS_RING_BASE,
2435 rbuffer->gpu_address >> 8);
2436 radeon_emit(cs, PKT3(PKT3_NOP, 0, 0));
2437 radeon_emit(cs, radeon_add_to_buffer_list(&rctx->b, &rctx->b.gfx, rbuffer,
2438 RADEON_USAGE_READWRITE,
2439 RADEON_PRIO_SHADER_RINGS));
2440 radeon_set_config_reg(cs, R_008C4C_SQ_GSVS_RING_SIZE,
2441 state->gsvs_ring.buffer_size >> 8);
2442 } else {
2443 radeon_set_config_reg(cs, R_008C44_SQ_ESGS_RING_SIZE, 0);
2444 radeon_set_config_reg(cs, R_008C4C_SQ_GSVS_RING_SIZE, 0);
2445 }
2446
2447 radeon_set_config_reg(cs, R_008040_WAIT_UNTIL, S_008040_WAIT_3D_IDLE(1));
2448 radeon_emit(cs, PKT3(PKT3_EVENT_WRITE, 0, 0));
2449 radeon_emit(cs, EVENT_TYPE(EVENT_TYPE_VGT_FLUSH));
2450 }
2451
2452 void cayman_init_common_regs(struct r600_command_buffer *cb,
2453 enum chip_class ctx_chip_class,
2454 enum radeon_family ctx_family,
2455 int ctx_drm_minor)
2456 {
2457 r600_store_config_reg_seq(cb, R_008C00_SQ_CONFIG, 2);
2458 r600_store_value(cb, S_008C00_EXPORT_SRC_C(1)); /* R_008C00_SQ_CONFIG */
2459 /* always set the temp clauses */
2460 r600_store_value(cb, S_008C04_NUM_CLAUSE_TEMP_GPRS(4)); /* R_008C04_SQ_GPR_RESOURCE_MGMT_1 */
2461
2462 r600_store_config_reg_seq(cb, R_008C10_SQ_GLOBAL_GPR_RESOURCE_MGMT_1, 2);
2463 r600_store_value(cb, 0); /* R_008C10_SQ_GLOBAL_GPR_RESOURCE_MGMT_1 */
2464 r600_store_value(cb, 0); /* R_008C14_SQ_GLOBAL_GPR_RESOURCE_MGMT_2 */
2465
2466 r600_store_config_reg(cb, R_008D8C_SQ_DYN_GPR_CNTL_PS_FLUSH_REQ, (1 << 8));
2467
2468 r600_store_context_reg_seq(cb, R_028350_SX_MISC, 2);
2469 r600_store_value(cb, 0);
2470 r600_store_value(cb, S_028354_SURFACE_SYNC_MASK(0xf));
2471
2472 r600_store_context_reg(cb, R_028800_DB_DEPTH_CONTROL, 0);
2473 }
2474
2475 static void cayman_init_atom_start_cs(struct r600_context *rctx)
2476 {
2477 struct r600_command_buffer *cb = &rctx->start_cs_cmd;
2478 int i;
2479
2480 r600_init_command_buffer(cb, 338);
2481
2482 /* This must be first. */
2483 r600_store_value(cb, PKT3(PKT3_CONTEXT_CONTROL, 1, 0));
2484 r600_store_value(cb, 0x80000000);
2485 r600_store_value(cb, 0x80000000);
2486
2487 /* We're setting config registers here. */
2488 r600_store_value(cb, PKT3(PKT3_EVENT_WRITE, 0, 0));
2489 r600_store_value(cb, EVENT_TYPE(EVENT_TYPE_PS_PARTIAL_FLUSH) | EVENT_INDEX(4));
2490
2491 /* This enables pipeline stat & streamout queries.
2492 * They are only disabled by blits.
2493 */
2494 r600_store_value(cb, PKT3(PKT3_EVENT_WRITE, 0, 0));
2495 r600_store_value(cb, EVENT_TYPE(EVENT_TYPE_PIPELINESTAT_START) | EVENT_INDEX(0));
2496
2497 cayman_init_common_regs(cb, rctx->b.chip_class,
2498 rctx->b.family, rctx->screen->b.info.drm_minor);
2499
2500 r600_store_config_reg(cb, R_009100_SPI_CONFIG_CNTL, 0);
2501 r600_store_config_reg(cb, R_00913C_SPI_CONFIG_CNTL_1, S_00913C_VTX_DONE_DELAY(4));
2502
2503 /* remove LS/HS from one SIMD for hw workaround */
2504 r600_store_config_reg_seq(cb, R_008E20_SQ_STATIC_THREAD_MGMT1, 3);
2505 r600_store_value(cb, 0xffffffff);
2506 r600_store_value(cb, 0xffffffff);
2507 r600_store_value(cb, 0xfffffffe);
2508
2509 r600_store_context_reg_seq(cb, R_028900_SQ_ESGS_RING_ITEMSIZE, 6);
2510 r600_store_value(cb, 0); /* R_028900_SQ_ESGS_RING_ITEMSIZE */
2511 r600_store_value(cb, 0); /* R_028904_SQ_GSVS_RING_ITEMSIZE */
2512 r600_store_value(cb, 0); /* R_028908_SQ_ESTMP_RING_ITEMSIZE */
2513 r600_store_value(cb, 0); /* R_02890C_SQ_GSTMP_RING_ITEMSIZE */
2514 r600_store_value(cb, 0); /* R_028910_SQ_VSTMP_RING_ITEMSIZE */
2515 r600_store_value(cb, 0); /* R_028914_SQ_PSTMP_RING_ITEMSIZE */
2516
2517 r600_store_context_reg_seq(cb, R_02891C_SQ_GS_VERT_ITEMSIZE, 4);
2518 r600_store_value(cb, 0); /* R_02891C_SQ_GS_VERT_ITEMSIZE */
2519 r600_store_value(cb, 0); /* R_028920_SQ_GS_VERT_ITEMSIZE_1 */
2520 r600_store_value(cb, 0); /* R_028924_SQ_GS_VERT_ITEMSIZE_2 */
2521 r600_store_value(cb, 0); /* R_028928_SQ_GS_VERT_ITEMSIZE_3 */
2522
2523 r600_store_context_reg_seq(cb, R_028A10_VGT_OUTPUT_PATH_CNTL, 13);
2524 r600_store_value(cb, 0); /* R_028A10_VGT_OUTPUT_PATH_CNTL */
2525 r600_store_value(cb, 0); /* R_028A14_VGT_HOS_CNTL */
2526 r600_store_value(cb, fui(64)); /* R_028A18_VGT_HOS_MAX_TESS_LEVEL */
2527 r600_store_value(cb, fui(0)); /* R_028A1C_VGT_HOS_MIN_TESS_LEVEL */
2528 r600_store_value(cb, 16); /* R_028A20_VGT_HOS_REUSE_DEPTH */
2529 r600_store_value(cb, 0); /* R_028A24_VGT_GROUP_PRIM_TYPE */
2530 r600_store_value(cb, 0); /* R_028A28_VGT_GROUP_FIRST_DECR */
2531 r600_store_value(cb, 0); /* R_028A2C_VGT_GROUP_DECR */
2532 r600_store_value(cb, 0); /* R_028A30_VGT_GROUP_VECT_0_CNTL */
2533 r600_store_value(cb, 0); /* R_028A34_VGT_GROUP_VECT_1_CNTL */
2534 r600_store_value(cb, 0); /* R_028A38_VGT_GROUP_VECT_0_FMT_CNTL */
2535 r600_store_value(cb, 0); /* R_028A3C_VGT_GROUP_VECT_1_FMT_CNTL */
2536 r600_store_value(cb, 0); /* R_028A40_VGT_GS_MODE */
2537
2538 r600_store_context_reg(cb, R_028B98_VGT_STRMOUT_BUFFER_CONFIG, 0);
2539
2540 r600_store_config_reg(cb, R_008A14_PA_CL_ENHANCE, (3 << 1) | 1);
2541
2542 r600_store_context_reg_seq(cb, CM_R_028BD4_PA_SC_CENTROID_PRIORITY_0, 2);
2543 r600_store_value(cb, 0x76543210); /* CM_R_028BD4_PA_SC_CENTROID_PRIORITY_0 */
2544 r600_store_value(cb, 0xfedcba98); /* CM_R_028BD8_PA_SC_CENTROID_PRIORITY_1 */
2545
2546 r600_store_context_reg_seq(cb, R_0288E8_SQ_LDS_ALLOC, 2);
2547 r600_store_value(cb, 0); /* R_0288E8_SQ_LDS_ALLOC */
2548 r600_store_value(cb, 0); /* R_0288EC_SQ_LDS_ALLOC_PS */
2549
2550 r600_store_context_reg(cb, R_0288F0_SQ_VTX_SEMANTIC_CLEAR, ~0);
2551
2552 r600_store_context_reg_seq(cb, R_028400_VGT_MAX_VTX_INDX, 2);
2553 r600_store_value(cb, ~0); /* R_028400_VGT_MAX_VTX_INDX */
2554 r600_store_value(cb, 0); /* R_028404_VGT_MIN_VTX_INDX */
2555
2556 r600_store_ctl_const(cb, R_03CFF0_SQ_VTX_BASE_VTX_LOC, 0);
2557
2558 r600_store_context_reg(cb, R_028028_DB_STENCIL_CLEAR, 0);
2559
2560 r600_store_context_reg(cb, R_0286DC_SPI_FOG_CNTL, 0);
2561
2562 r600_store_context_reg_seq(cb, R_028AC0_DB_SRESULTS_COMPARE_STATE0, 3);
2563 r600_store_value(cb, 0); /* R_028AC0_DB_SRESULTS_COMPARE_STATE0 */
2564 r600_store_value(cb, 0); /* R_028AC4_DB_SRESULTS_COMPARE_STATE1 */
2565 r600_store_value(cb, 0); /* R_028AC8_DB_PRELOAD_CONTROL */
2566
2567 r600_store_context_reg(cb, R_028200_PA_SC_WINDOW_OFFSET, 0);
2568 r600_store_context_reg(cb, R_02820C_PA_SC_CLIPRECT_RULE, 0xFFFF);
2569
2570 r600_store_context_reg(cb, R_028230_PA_SC_EDGERULE, 0xAAAAAAAA);
2571 r600_store_context_reg(cb, R_028820_PA_CL_NANINF_CNTL, 0);
2572
2573 r600_store_context_reg_seq(cb, R_028240_PA_SC_GENERIC_SCISSOR_TL, 2);
2574 r600_store_value(cb, 0); /* R_028240_PA_SC_GENERIC_SCISSOR_TL */
2575 r600_store_value(cb, S_028244_BR_X(16384) | S_028244_BR_Y(16384)); /* R_028244_PA_SC_GENERIC_SCISSOR_BR */
2576
2577 r600_store_context_reg_seq(cb, R_028030_PA_SC_SCREEN_SCISSOR_TL, 2);
2578 r600_store_value(cb, 0); /* R_028030_PA_SC_SCREEN_SCISSOR_TL */
2579 r600_store_value(cb, S_028034_BR_X(16384) | S_028034_BR_Y(16384)); /* R_028034_PA_SC_SCREEN_SCISSOR_BR */
2580
2581 r600_store_context_reg(cb, R_028848_SQ_PGM_RESOURCES_2_PS, S_028848_SINGLE_ROUND(V_SQ_ROUND_NEAREST_EVEN));
2582 r600_store_context_reg(cb, R_028864_SQ_PGM_RESOURCES_2_VS, S_028864_SINGLE_ROUND(V_SQ_ROUND_NEAREST_EVEN));
2583 r600_store_context_reg(cb, R_02887C_SQ_PGM_RESOURCES_2_GS, S_028848_SINGLE_ROUND(V_SQ_ROUND_NEAREST_EVEN));
2584 r600_store_context_reg(cb, R_028894_SQ_PGM_RESOURCES_2_ES, S_028848_SINGLE_ROUND(V_SQ_ROUND_NEAREST_EVEN));
2585 r600_store_context_reg(cb, R_0288C0_SQ_PGM_RESOURCES_2_HS, S_028848_SINGLE_ROUND(V_SQ_ROUND_NEAREST_EVEN));
2586 r600_store_context_reg(cb, R_0288D8_SQ_PGM_RESOURCES_2_LS, S_028848_SINGLE_ROUND(V_SQ_ROUND_NEAREST_EVEN));
2587
2588 r600_store_context_reg(cb, R_0288A8_SQ_PGM_RESOURCES_FS, 0);
2589
2590 /* to avoid GPU doing any preloading of constant from random address */
2591 r600_store_context_reg_seq(cb, R_028140_ALU_CONST_BUFFER_SIZE_PS_0, 16);
2592 for (i = 0; i < 16; i++)
2593 r600_store_value(cb, 0);
2594
2595 r600_store_context_reg_seq(cb, R_028180_ALU_CONST_BUFFER_SIZE_VS_0, 16);
2596 for (i = 0; i < 16; i++)
2597 r600_store_value(cb, 0);
2598
2599 r600_store_context_reg_seq(cb, R_0281C0_ALU_CONST_BUFFER_SIZE_GS_0, 16);
2600 for (i = 0; i < 16; i++)
2601 r600_store_value(cb, 0);
2602
2603 r600_store_context_reg_seq(cb, R_028FC0_ALU_CONST_BUFFER_SIZE_LS_0, 16);
2604 for (i = 0; i < 16; i++)
2605 r600_store_value(cb, 0);
2606
2607 r600_store_context_reg_seq(cb, R_028F80_ALU_CONST_BUFFER_SIZE_HS_0, 16);
2608 for (i = 0; i < 16; i++)
2609 r600_store_value(cb, 0);
2610
2611 if (rctx->screen->b.has_streamout) {
2612 r600_store_context_reg(cb, R_028B28_VGT_STRMOUT_DRAW_OPAQUE_OFFSET, 0);
2613 }
2614
2615 r600_store_context_reg(cb, R_028010_DB_RENDER_OVERRIDE2, 0);
2616 r600_store_context_reg(cb, R_028234_PA_SU_HARDWARE_SCREEN_OFFSET, 0);
2617 r600_store_context_reg(cb, R_0286C8_SPI_THREAD_GROUPING, 0);
2618 r600_store_context_reg_seq(cb, R_0286E4_SPI_PS_IN_CONTROL_2, 2);
2619 r600_store_value(cb, 0); /* R_0286E4_SPI_PS_IN_CONTROL_2 */
2620 r600_store_value(cb, 0); /* R_0286E8_SPI_COMPUTE_INPUT_CNTL */
2621
2622 r600_store_context_reg_seq(cb, R_028B54_VGT_SHADER_STAGES_EN, 2);
2623 r600_store_value(cb, 0); /* R028B54_VGT_SHADER_STAGES_EN */
2624 r600_store_value(cb, 0); /* R028B58_VGT_LS_HS_CONFIG */
2625 r600_store_context_reg(cb, R_028B6C_VGT_TF_PARAM, 0);
2626 eg_store_loop_const(cb, R_03A200_SQ_LOOP_CONST_0, 0x01000FFF);
2627 eg_store_loop_const(cb, R_03A200_SQ_LOOP_CONST_0 + (32 * 4), 0x01000FFF);
2628 eg_store_loop_const(cb, R_03A200_SQ_LOOP_CONST_0 + (64 * 4), 0x01000FFF);
2629 eg_store_loop_const(cb, R_03A200_SQ_LOOP_CONST_0 + (96 * 4), 0x01000FFF);
2630 eg_store_loop_const(cb, R_03A200_SQ_LOOP_CONST_0 + (128 * 4), 0x01000FFF);
2631 }
2632
2633 void evergreen_init_common_regs(struct r600_context *rctx, struct r600_command_buffer *cb,
2634 enum chip_class ctx_chip_class,
2635 enum radeon_family ctx_family,
2636 int ctx_drm_minor)
2637 {
2638 int ps_prio;
2639 int vs_prio;
2640 int gs_prio;
2641 int es_prio;
2642
2643 int hs_prio;
2644 int cs_prio;
2645 int ls_prio;
2646
2647 unsigned tmp;
2648
2649 ps_prio = 0;
2650 vs_prio = 1;
2651 gs_prio = 2;
2652 es_prio = 3;
2653 hs_prio = 3;
2654 ls_prio = 3;
2655 cs_prio = 0;
2656
2657 rctx->default_gprs[R600_HW_STAGE_PS] = 93;
2658 rctx->default_gprs[R600_HW_STAGE_VS] = 46;
2659 rctx->r6xx_num_clause_temp_gprs = 4;
2660 rctx->default_gprs[R600_HW_STAGE_GS] = 31;
2661 rctx->default_gprs[R600_HW_STAGE_ES] = 31;
2662 rctx->default_gprs[EG_HW_STAGE_HS] = 23;
2663 rctx->default_gprs[EG_HW_STAGE_LS] = 23;
2664
2665 tmp = 0;
2666 switch (ctx_family) {
2667 case CHIP_CEDAR:
2668 case CHIP_PALM:
2669 case CHIP_SUMO:
2670 case CHIP_SUMO2:
2671 case CHIP_CAICOS:
2672 break;
2673 default:
2674 tmp |= S_008C00_VC_ENABLE(1);
2675 break;
2676 }
2677 tmp |= S_008C00_EXPORT_SRC_C(1);
2678 tmp |= S_008C00_CS_PRIO(cs_prio);
2679 tmp |= S_008C00_LS_PRIO(ls_prio);
2680 tmp |= S_008C00_HS_PRIO(hs_prio);
2681 tmp |= S_008C00_PS_PRIO(ps_prio);
2682 tmp |= S_008C00_VS_PRIO(vs_prio);
2683 tmp |= S_008C00_GS_PRIO(gs_prio);
2684 tmp |= S_008C00_ES_PRIO(es_prio);
2685
2686 r600_store_config_reg_seq(cb, R_008C00_SQ_CONFIG, 1);
2687 r600_store_value(cb, tmp); /* R_008C00_SQ_CONFIG */
2688
2689 r600_store_config_reg_seq(cb, R_008C10_SQ_GLOBAL_GPR_RESOURCE_MGMT_1, 2);
2690 r600_store_value(cb, 0); /* R_008C10_SQ_GLOBAL_GPR_RESOURCE_MGMT_1 */
2691 r600_store_value(cb, 0); /* R_008C14_SQ_GLOBAL_GPR_RESOURCE_MGMT_2 */
2692
2693 /* The cs checker requires this register to be set. */
2694 r600_store_context_reg(cb, R_028800_DB_DEPTH_CONTROL, 0);
2695
2696 r600_store_context_reg_seq(cb, R_028350_SX_MISC, 2);
2697 r600_store_value(cb, 0);
2698 r600_store_value(cb, S_028354_SURFACE_SYNC_MASK(0xf));
2699
2700 return;
2701 }
2702
2703 void evergreen_init_atom_start_cs(struct r600_context *rctx)
2704 {
2705 struct r600_command_buffer *cb = &rctx->start_cs_cmd;
2706 int num_ps_threads;
2707 int num_vs_threads;
2708 int num_gs_threads;
2709 int num_es_threads;
2710 int num_hs_threads;
2711 int num_ls_threads;
2712
2713 int num_ps_stack_entries;
2714 int num_vs_stack_entries;
2715 int num_gs_stack_entries;
2716 int num_es_stack_entries;
2717 int num_hs_stack_entries;
2718 int num_ls_stack_entries;
2719 enum radeon_family family;
2720 unsigned tmp, i;
2721
2722 if (rctx->b.chip_class == CAYMAN) {
2723 cayman_init_atom_start_cs(rctx);
2724 return;
2725 }
2726
2727 r600_init_command_buffer(cb, 338);
2728
2729 /* This must be first. */
2730 r600_store_value(cb, PKT3(PKT3_CONTEXT_CONTROL, 1, 0));
2731 r600_store_value(cb, 0x80000000);
2732 r600_store_value(cb, 0x80000000);
2733
2734 /* We're setting config registers here. */
2735 r600_store_value(cb, PKT3(PKT3_EVENT_WRITE, 0, 0));
2736 r600_store_value(cb, EVENT_TYPE(EVENT_TYPE_PS_PARTIAL_FLUSH) | EVENT_INDEX(4));
2737
2738 /* This enables pipeline stat & streamout queries.
2739 * They are only disabled by blits.
2740 */
2741 r600_store_value(cb, PKT3(PKT3_EVENT_WRITE, 0, 0));
2742 r600_store_value(cb, EVENT_TYPE(EVENT_TYPE_PIPELINESTAT_START) | EVENT_INDEX(0));
2743
2744 evergreen_init_common_regs(rctx, cb, rctx->b.chip_class,
2745 rctx->b.family, rctx->screen->b.info.drm_minor);
2746
2747 family = rctx->b.family;
2748 switch (family) {
2749 case CHIP_CEDAR:
2750 default:
2751 num_ps_threads = 96;
2752 num_vs_threads = 16;
2753 num_gs_threads = 16;
2754 num_es_threads = 16;
2755 num_hs_threads = 16;
2756 num_ls_threads = 16;
2757 num_ps_stack_entries = 42;
2758 num_vs_stack_entries = 42;
2759 num_gs_stack_entries = 42;
2760 num_es_stack_entries = 42;
2761 num_hs_stack_entries = 42;
2762 num_ls_stack_entries = 42;
2763 break;
2764 case CHIP_REDWOOD:
2765 num_ps_threads = 128;
2766 num_vs_threads = 20;
2767 num_gs_threads = 20;
2768 num_es_threads = 20;
2769 num_hs_threads = 20;
2770 num_ls_threads = 20;
2771 num_ps_stack_entries = 42;
2772 num_vs_stack_entries = 42;
2773 num_gs_stack_entries = 42;
2774 num_es_stack_entries = 42;
2775 num_hs_stack_entries = 42;
2776 num_ls_stack_entries = 42;
2777 break;
2778 case CHIP_JUNIPER:
2779 num_ps_threads = 128;
2780 num_vs_threads = 20;
2781 num_gs_threads = 20;
2782 num_es_threads = 20;
2783 num_hs_threads = 20;
2784 num_ls_threads = 20;
2785 num_ps_stack_entries = 85;
2786 num_vs_stack_entries = 85;
2787 num_gs_stack_entries = 85;
2788 num_es_stack_entries = 85;
2789 num_hs_stack_entries = 85;
2790 num_ls_stack_entries = 85;
2791 break;
2792 case CHIP_CYPRESS:
2793 case CHIP_HEMLOCK:
2794 num_ps_threads = 128;
2795 num_vs_threads = 20;
2796 num_gs_threads = 20;
2797 num_es_threads = 20;
2798 num_hs_threads = 20;
2799 num_ls_threads = 20;
2800 num_ps_stack_entries = 85;
2801 num_vs_stack_entries = 85;
2802 num_gs_stack_entries = 85;
2803 num_es_stack_entries = 85;
2804 num_hs_stack_entries = 85;
2805 num_ls_stack_entries = 85;
2806 break;
2807 case CHIP_PALM:
2808 num_ps_threads = 96;
2809 num_vs_threads = 16;
2810 num_gs_threads = 16;
2811 num_es_threads = 16;
2812 num_hs_threads = 16;
2813 num_ls_threads = 16;
2814 num_ps_stack_entries = 42;
2815 num_vs_stack_entries = 42;
2816 num_gs_stack_entries = 42;
2817 num_es_stack_entries = 42;
2818 num_hs_stack_entries = 42;
2819 num_ls_stack_entries = 42;
2820 break;
2821 case CHIP_SUMO:
2822 num_ps_threads = 96;
2823 num_vs_threads = 25;
2824 num_gs_threads = 25;
2825 num_es_threads = 25;
2826 num_hs_threads = 16;
2827 num_ls_threads = 16;
2828 num_ps_stack_entries = 42;
2829 num_vs_stack_entries = 42;
2830 num_gs_stack_entries = 42;
2831 num_es_stack_entries = 42;
2832 num_hs_stack_entries = 42;
2833 num_ls_stack_entries = 42;
2834 break;
2835 case CHIP_SUMO2:
2836 num_ps_threads = 96;
2837 num_vs_threads = 25;
2838 num_gs_threads = 25;
2839 num_es_threads = 25;
2840 num_hs_threads = 16;
2841 num_ls_threads = 16;
2842 num_ps_stack_entries = 85;
2843 num_vs_stack_entries = 85;
2844 num_gs_stack_entries = 85;
2845 num_es_stack_entries = 85;
2846 num_hs_stack_entries = 85;
2847 num_ls_stack_entries = 85;
2848 break;
2849 case CHIP_BARTS:
2850 num_ps_threads = 128;
2851 num_vs_threads = 20;
2852 num_gs_threads = 20;
2853 num_es_threads = 20;
2854 num_hs_threads = 20;
2855 num_ls_threads = 20;
2856 num_ps_stack_entries = 85;
2857 num_vs_stack_entries = 85;
2858 num_gs_stack_entries = 85;
2859 num_es_stack_entries = 85;
2860 num_hs_stack_entries = 85;
2861 num_ls_stack_entries = 85;
2862 break;
2863 case CHIP_TURKS:
2864 num_ps_threads = 128;
2865 num_vs_threads = 20;
2866 num_gs_threads = 20;
2867 num_es_threads = 20;
2868 num_hs_threads = 20;
2869 num_ls_threads = 20;
2870 num_ps_stack_entries = 42;
2871 num_vs_stack_entries = 42;
2872 num_gs_stack_entries = 42;
2873 num_es_stack_entries = 42;
2874 num_hs_stack_entries = 42;
2875 num_ls_stack_entries = 42;
2876 break;
2877 case CHIP_CAICOS:
2878 num_ps_threads = 96;
2879 num_vs_threads = 10;
2880 num_gs_threads = 10;
2881 num_es_threads = 10;
2882 num_hs_threads = 10;
2883 num_ls_threads = 10;
2884 num_ps_stack_entries = 42;
2885 num_vs_stack_entries = 42;
2886 num_gs_stack_entries = 42;
2887 num_es_stack_entries = 42;
2888 num_hs_stack_entries = 42;
2889 num_ls_stack_entries = 42;
2890 break;
2891 }
2892
2893 tmp = S_008C18_NUM_PS_THREADS(num_ps_threads);
2894 tmp |= S_008C18_NUM_VS_THREADS(num_vs_threads);
2895 tmp |= S_008C18_NUM_GS_THREADS(num_gs_threads);
2896 tmp |= S_008C18_NUM_ES_THREADS(num_es_threads);
2897
2898 r600_store_config_reg_seq(cb, R_008C18_SQ_THREAD_RESOURCE_MGMT_1, 5);
2899 r600_store_value(cb, tmp); /* R_008C18_SQ_THREAD_RESOURCE_MGMT_1 */
2900
2901 tmp = S_008C1C_NUM_HS_THREADS(num_hs_threads);
2902 tmp |= S_008C1C_NUM_LS_THREADS(num_ls_threads);
2903 r600_store_value(cb, tmp); /* R_008C1C_SQ_THREAD_RESOURCE_MGMT_2 */
2904
2905 tmp = S_008C20_NUM_PS_STACK_ENTRIES(num_ps_stack_entries);
2906 tmp |= S_008C20_NUM_VS_STACK_ENTRIES(num_vs_stack_entries);
2907 r600_store_value(cb, tmp); /* R_008C20_SQ_STACK_RESOURCE_MGMT_1 */
2908
2909 tmp = S_008C24_NUM_GS_STACK_ENTRIES(num_gs_stack_entries);
2910 tmp |= S_008C24_NUM_ES_STACK_ENTRIES(num_es_stack_entries);
2911 r600_store_value(cb, tmp); /* R_008C24_SQ_STACK_RESOURCE_MGMT_2 */
2912
2913 tmp = S_008C28_NUM_HS_STACK_ENTRIES(num_hs_stack_entries);
2914 tmp |= S_008C28_NUM_LS_STACK_ENTRIES(num_ls_stack_entries);
2915 r600_store_value(cb, tmp); /* R_008C28_SQ_STACK_RESOURCE_MGMT_3 */
2916
2917 r600_store_config_reg(cb, R_008E2C_SQ_LDS_RESOURCE_MGMT,
2918 S_008E2C_NUM_PS_LDS(0x1000) | S_008E2C_NUM_LS_LDS(0x1000));
2919
2920 /* remove LS/HS from one SIMD for hw workaround */
2921 r600_store_config_reg_seq(cb, R_008E20_SQ_STATIC_THREAD_MGMT1, 3);
2922 r600_store_value(cb, 0xffffffff);
2923 r600_store_value(cb, 0xffffffff);
2924 r600_store_value(cb, 0xfffffffe);
2925
2926 r600_store_config_reg(cb, R_009100_SPI_CONFIG_CNTL, 0);
2927 r600_store_config_reg(cb, R_00913C_SPI_CONFIG_CNTL_1, S_00913C_VTX_DONE_DELAY(4));
2928
2929 r600_store_context_reg_seq(cb, R_028900_SQ_ESGS_RING_ITEMSIZE, 6);
2930 r600_store_value(cb, 0); /* R_028900_SQ_ESGS_RING_ITEMSIZE */
2931 r600_store_value(cb, 0); /* R_028904_SQ_GSVS_RING_ITEMSIZE */
2932 r600_store_value(cb, 0); /* R_028908_SQ_ESTMP_RING_ITEMSIZE */
2933 r600_store_value(cb, 0); /* R_02890C_SQ_GSTMP_RING_ITEMSIZE */
2934 r600_store_value(cb, 0); /* R_028910_SQ_VSTMP_RING_ITEMSIZE */
2935 r600_store_value(cb, 0); /* R_028914_SQ_PSTMP_RING_ITEMSIZE */
2936
2937 r600_store_context_reg_seq(cb, R_02891C_SQ_GS_VERT_ITEMSIZE, 4);
2938 r600_store_value(cb, 0); /* R_02891C_SQ_GS_VERT_ITEMSIZE */
2939 r600_store_value(cb, 0); /* R_028920_SQ_GS_VERT_ITEMSIZE_1 */
2940 r600_store_value(cb, 0); /* R_028924_SQ_GS_VERT_ITEMSIZE_2 */
2941 r600_store_value(cb, 0); /* R_028928_SQ_GS_VERT_ITEMSIZE_3 */
2942
2943 r600_store_context_reg_seq(cb, R_028A10_VGT_OUTPUT_PATH_CNTL, 13);
2944 r600_store_value(cb, 0); /* R_028A10_VGT_OUTPUT_PATH_CNTL */
2945 r600_store_value(cb, 0); /* R_028A14_VGT_HOS_CNTL */
2946 r600_store_value(cb, fui(64)); /* R_028A18_VGT_HOS_MAX_TESS_LEVEL */
2947 r600_store_value(cb, fui(1.0)); /* R_028A1C_VGT_HOS_MIN_TESS_LEVEL */
2948 r600_store_value(cb, 16); /* R_028A20_VGT_HOS_REUSE_DEPTH */
2949 r600_store_value(cb, 0); /* R_028A24_VGT_GROUP_PRIM_TYPE */
2950 r600_store_value(cb, 0); /* R_028A28_VGT_GROUP_FIRST_DECR */
2951 r600_store_value(cb, 0); /* R_028A2C_VGT_GROUP_DECR */
2952 r600_store_value(cb, 0); /* R_028A30_VGT_GROUP_VECT_0_CNTL */
2953 r600_store_value(cb, 0); /* R_028A34_VGT_GROUP_VECT_1_CNTL */
2954 r600_store_value(cb, 0); /* R_028A38_VGT_GROUP_VECT_0_FMT_CNTL */
2955 r600_store_value(cb, 0); /* R_028A3C_VGT_GROUP_VECT_1_FMT_CNTL */
2956 r600_store_value(cb, 0); /* R_028A40_VGT_GS_MODE */
2957
2958 r600_store_config_reg(cb, R_008A14_PA_CL_ENHANCE, (3 << 1) | 1);
2959
2960 r600_store_context_reg(cb, R_0288F0_SQ_VTX_SEMANTIC_CLEAR, ~0);
2961
2962 r600_store_context_reg_seq(cb, R_028400_VGT_MAX_VTX_INDX, 2);
2963 r600_store_value(cb, ~0); /* R_028400_VGT_MAX_VTX_INDX */
2964 r600_store_value(cb, 0); /* R_028404_VGT_MIN_VTX_INDX */
2965
2966 r600_store_ctl_const(cb, R_03CFF0_SQ_VTX_BASE_VTX_LOC, 0);
2967
2968 r600_store_context_reg(cb, R_028028_DB_STENCIL_CLEAR, 0);
2969
2970 r600_store_context_reg(cb, R_028200_PA_SC_WINDOW_OFFSET, 0);
2971 r600_store_context_reg(cb, R_02820C_PA_SC_CLIPRECT_RULE, 0xFFFF);
2972 r600_store_context_reg(cb, R_028230_PA_SC_EDGERULE, 0xAAAAAAAA);
2973
2974 r600_store_context_reg(cb, R_0286DC_SPI_FOG_CNTL, 0);
2975 r600_store_context_reg(cb, R_028820_PA_CL_NANINF_CNTL, 0);
2976
2977 r600_store_context_reg_seq(cb, R_028AC0_DB_SRESULTS_COMPARE_STATE0, 3);
2978 r600_store_value(cb, 0); /* R_028AC0_DB_SRESULTS_COMPARE_STATE0 */
2979 r600_store_value(cb, 0); /* R_028AC4_DB_SRESULTS_COMPARE_STATE1 */
2980 r600_store_value(cb, 0); /* R_028AC8_DB_PRELOAD_CONTROL */
2981
2982 r600_store_context_reg_seq(cb, R_028240_PA_SC_GENERIC_SCISSOR_TL, 2);
2983 r600_store_value(cb, 0); /* R_028240_PA_SC_GENERIC_SCISSOR_TL */
2984 r600_store_value(cb, S_028244_BR_X(16384) | S_028244_BR_Y(16384)); /* R_028244_PA_SC_GENERIC_SCISSOR_BR */
2985
2986 r600_store_context_reg_seq(cb, R_028030_PA_SC_SCREEN_SCISSOR_TL, 2);
2987 r600_store_value(cb, 0); /* R_028030_PA_SC_SCREEN_SCISSOR_TL */
2988 r600_store_value(cb, S_028034_BR_X(16384) | S_028034_BR_Y(16384)); /* R_028034_PA_SC_SCREEN_SCISSOR_BR */
2989
2990 r600_store_context_reg(cb, R_028848_SQ_PGM_RESOURCES_2_PS, S_028848_SINGLE_ROUND(V_SQ_ROUND_NEAREST_EVEN));
2991 r600_store_context_reg(cb, R_028864_SQ_PGM_RESOURCES_2_VS, S_028864_SINGLE_ROUND(V_SQ_ROUND_NEAREST_EVEN));
2992 r600_store_context_reg(cb, R_02887C_SQ_PGM_RESOURCES_2_GS, S_028848_SINGLE_ROUND(V_SQ_ROUND_NEAREST_EVEN));
2993 r600_store_context_reg(cb, R_028894_SQ_PGM_RESOURCES_2_ES, S_028848_SINGLE_ROUND(V_SQ_ROUND_NEAREST_EVEN));
2994 r600_store_context_reg(cb, R_0288A8_SQ_PGM_RESOURCES_FS, 0);
2995 r600_store_context_reg(cb, R_0288C0_SQ_PGM_RESOURCES_2_HS, S_028848_SINGLE_ROUND(V_SQ_ROUND_NEAREST_EVEN));
2996 r600_store_context_reg(cb, R_0288D8_SQ_PGM_RESOURCES_2_LS, S_028848_SINGLE_ROUND(V_SQ_ROUND_NEAREST_EVEN));
2997
2998 /* to avoid GPU doing any preloading of constant from random address */
2999 r600_store_context_reg_seq(cb, R_028140_ALU_CONST_BUFFER_SIZE_PS_0, 16);
3000 for (i = 0; i < 16; i++)
3001 r600_store_value(cb, 0);
3002
3003 r600_store_context_reg_seq(cb, R_028180_ALU_CONST_BUFFER_SIZE_VS_0, 16);
3004 for (i = 0; i < 16; i++)
3005 r600_store_value(cb, 0);
3006
3007 r600_store_context_reg_seq(cb, R_0281C0_ALU_CONST_BUFFER_SIZE_GS_0, 16);
3008 for (i = 0; i < 16; i++)
3009 r600_store_value(cb, 0);
3010
3011 r600_store_context_reg_seq(cb, R_028FC0_ALU_CONST_BUFFER_SIZE_LS_0, 16);
3012 for (i = 0; i < 16; i++)
3013 r600_store_value(cb, 0);
3014
3015 r600_store_context_reg_seq(cb, R_028F80_ALU_CONST_BUFFER_SIZE_HS_0, 16);
3016 for (i = 0; i < 16; i++)
3017 r600_store_value(cb, 0);
3018
3019 r600_store_context_reg(cb, R_028B98_VGT_STRMOUT_BUFFER_CONFIG, 0);
3020
3021 if (rctx->screen->b.has_streamout) {
3022 r600_store_context_reg(cb, R_028B28_VGT_STRMOUT_DRAW_OPAQUE_OFFSET, 0);
3023 }
3024
3025 r600_store_context_reg(cb, R_028010_DB_RENDER_OVERRIDE2, 0);
3026 r600_store_context_reg(cb, R_028234_PA_SU_HARDWARE_SCREEN_OFFSET, 0);
3027 r600_store_context_reg(cb, R_0286C8_SPI_THREAD_GROUPING, 0);
3028 r600_store_context_reg_seq(cb, R_0286E4_SPI_PS_IN_CONTROL_2, 2);
3029 r600_store_value(cb, 0); /* R_0286E4_SPI_PS_IN_CONTROL_2 */
3030 r600_store_value(cb, 0); /* R_0286E8_SPI_COMPUTE_INPUT_CNTL */
3031
3032 r600_store_context_reg_seq(cb, R_0288E8_SQ_LDS_ALLOC, 2);
3033 r600_store_value(cb, 0); /* R_0288E8_SQ_LDS_ALLOC */
3034 r600_store_value(cb, 0); /* R_0288EC_SQ_LDS_ALLOC_PS */
3035
3036 if (rctx->b.family == CHIP_CAICOS) {
3037 r600_store_context_reg_seq(cb, R_028B54_VGT_SHADER_STAGES_EN, 2);
3038 r600_store_value(cb, 0); /* R028B54_VGT_SHADER_STAGES_EN */
3039 r600_store_value(cb, 0); /* R028B58_VGT_LS_HS_CONFIG */
3040 r600_store_context_reg(cb, R_028B6C_VGT_TF_PARAM, 0);
3041 } else {
3042 r600_store_context_reg_seq(cb, R_028B54_VGT_SHADER_STAGES_EN, 7);
3043 r600_store_value(cb, 0); /* R028B54_VGT_SHADER_STAGES_EN */
3044 r600_store_value(cb, 0); /* R028B58_VGT_LS_HS_CONFIG */
3045 r600_store_value(cb, 0); /* R028B5C_VGT_LS_SIZE */
3046 r600_store_value(cb, 0); /* R028B60_VGT_HS_SIZE */
3047 r600_store_value(cb, 0); /* R028B64_VGT_LS_HS_ALLOC */
3048 r600_store_value(cb, 0); /* R028B68_VGT_HS_PATCH_CONST */
3049 r600_store_value(cb, 0); /* R028B68_VGT_TF_PARAM */
3050 }
3051
3052 eg_store_loop_const(cb, R_03A200_SQ_LOOP_CONST_0, 0x01000FFF);
3053 eg_store_loop_const(cb, R_03A200_SQ_LOOP_CONST_0 + (32 * 4), 0x01000FFF);
3054 eg_store_loop_const(cb, R_03A200_SQ_LOOP_CONST_0 + (64 * 4), 0x01000FFF);
3055 eg_store_loop_const(cb, R_03A200_SQ_LOOP_CONST_0 + (96 * 4), 0x01000FFF);
3056 eg_store_loop_const(cb, R_03A200_SQ_LOOP_CONST_0 + (128 * 4), 0x01000FFF);
3057 }
3058
3059 void evergreen_update_ps_state(struct pipe_context *ctx, struct r600_pipe_shader *shader)
3060 {
3061 struct r600_context *rctx = (struct r600_context *)ctx;
3062 struct r600_command_buffer *cb = &shader->command_buffer;
3063 struct r600_shader *rshader = &shader->shader;
3064 unsigned i, exports_ps, num_cout, spi_ps_in_control_0, spi_input_z, spi_ps_in_control_1, db_shader_control = 0;
3065 int pos_index = -1, face_index = -1, fixed_pt_position_index = -1;
3066 int ninterp = 0;
3067 boolean have_perspective = FALSE, have_linear = FALSE;
3068 static const unsigned spi_baryc_enable_bit[6] = {
3069 S_0286E0_PERSP_SAMPLE_ENA(1),
3070 S_0286E0_PERSP_CENTER_ENA(1),
3071 S_0286E0_PERSP_CENTROID_ENA(1),
3072 S_0286E0_LINEAR_SAMPLE_ENA(1),
3073 S_0286E0_LINEAR_CENTER_ENA(1),
3074 S_0286E0_LINEAR_CENTROID_ENA(1)
3075 };
3076 unsigned spi_baryc_cntl = 0, sid, tmp, num = 0;
3077 unsigned z_export = 0, stencil_export = 0, mask_export = 0;
3078 unsigned sprite_coord_enable = rctx->rasterizer ? rctx->rasterizer->sprite_coord_enable : 0;
3079 uint32_t spi_ps_input_cntl[32];
3080
3081 if (!cb->buf) {
3082 r600_init_command_buffer(cb, 64);
3083 } else {
3084 cb->num_dw = 0;
3085 }
3086
3087 for (i = 0; i < rshader->ninput; i++) {
3088 /* evergreen NUM_INTERP only contains values interpolated into the LDS,
3089 POSITION goes via GPRs from the SC so isn't counted */
3090 if (rshader->input[i].name == TGSI_SEMANTIC_POSITION)
3091 pos_index = i;
3092 else if (rshader->input[i].name == TGSI_SEMANTIC_FACE) {
3093 if (face_index == -1)
3094 face_index = i;
3095 }
3096 else if (rshader->input[i].name == TGSI_SEMANTIC_SAMPLEMASK) {
3097 if (face_index == -1)
3098 face_index = i; /* lives in same register, same enable bit */
3099 }
3100 else if (rshader->input[i].name == TGSI_SEMANTIC_SAMPLEID) {
3101 fixed_pt_position_index = i;
3102 }
3103 else {
3104 ninterp++;
3105 int k = eg_get_interpolator_index(
3106 rshader->input[i].interpolate,
3107 rshader->input[i].interpolate_location);
3108 if (k >= 0) {
3109 spi_baryc_cntl |= spi_baryc_enable_bit[k];
3110 have_perspective |= k < 3;
3111 have_linear |= !(k < 3);
3112 }
3113 }
3114
3115 sid = rshader->input[i].spi_sid;
3116
3117 if (sid) {
3118 tmp = S_028644_SEMANTIC(sid);
3119
3120 /* D3D 9 behaviour. GL is undefined */
3121 if (rshader->input[i].name == TGSI_SEMANTIC_COLOR && rshader->input[i].sid == 0)
3122 tmp |= S_028644_DEFAULT_VAL(3);
3123
3124 if (rshader->input[i].name == TGSI_SEMANTIC_POSITION ||
3125 rshader->input[i].interpolate == TGSI_INTERPOLATE_CONSTANT ||
3126 (rshader->input[i].interpolate == TGSI_INTERPOLATE_COLOR &&
3127 rctx->rasterizer && rctx->rasterizer->flatshade)) {
3128 tmp |= S_028644_FLAT_SHADE(1);
3129 }
3130
3131 if (rshader->input[i].name == TGSI_SEMANTIC_GENERIC &&
3132 (sprite_coord_enable & (1 << rshader->input[i].sid))) {
3133 tmp |= S_028644_PT_SPRITE_TEX(1);
3134 }
3135
3136 spi_ps_input_cntl[num++] = tmp;
3137 }
3138 }
3139
3140 r600_store_context_reg_seq(cb, R_028644_SPI_PS_INPUT_CNTL_0, num);
3141 r600_store_array(cb, num, spi_ps_input_cntl);
3142
3143 for (i = 0; i < rshader->noutput; i++) {
3144 if (rshader->output[i].name == TGSI_SEMANTIC_POSITION)
3145 z_export = 1;
3146 if (rshader->output[i].name == TGSI_SEMANTIC_STENCIL)
3147 stencil_export = 1;
3148 if (rshader->output[i].name == TGSI_SEMANTIC_SAMPLEMASK &&
3149 rctx->framebuffer.nr_samples > 1 && rctx->ps_iter_samples > 0)
3150 mask_export = 1;
3151 }
3152 if (rshader->uses_kill)
3153 db_shader_control |= S_02880C_KILL_ENABLE(1);
3154
3155 db_shader_control |= S_02880C_Z_EXPORT_ENABLE(z_export);
3156 db_shader_control |= S_02880C_STENCIL_EXPORT_ENABLE(stencil_export);
3157 db_shader_control |= S_02880C_MASK_EXPORT_ENABLE(mask_export);
3158
3159 switch (rshader->ps_conservative_z) {
3160 default: /* fall through */
3161 case TGSI_FS_DEPTH_LAYOUT_ANY:
3162 db_shader_control |= S_02880C_CONSERVATIVE_Z_EXPORT(V_02880C_EXPORT_ANY_Z);
3163 break;
3164 case TGSI_FS_DEPTH_LAYOUT_GREATER:
3165 db_shader_control |= S_02880C_CONSERVATIVE_Z_EXPORT(V_02880C_EXPORT_GREATER_THAN_Z);
3166 break;
3167 case TGSI_FS_DEPTH_LAYOUT_LESS:
3168 db_shader_control |= S_02880C_CONSERVATIVE_Z_EXPORT(V_02880C_EXPORT_LESS_THAN_Z);
3169 break;
3170 }
3171
3172 exports_ps = 0;
3173 for (i = 0; i < rshader->noutput; i++) {
3174 if (rshader->output[i].name == TGSI_SEMANTIC_POSITION ||
3175 rshader->output[i].name == TGSI_SEMANTIC_STENCIL ||
3176 rshader->output[i].name == TGSI_SEMANTIC_SAMPLEMASK)
3177 exports_ps |= 1;
3178 }
3179
3180 num_cout = rshader->nr_ps_color_exports;
3181
3182 exports_ps |= S_02884C_EXPORT_COLORS(num_cout);
3183 if (!exports_ps) {
3184 /* always at least export 1 component per pixel */
3185 exports_ps = 2;
3186 }
3187 shader->nr_ps_color_outputs = num_cout;
3188 if (ninterp == 0) {
3189 ninterp = 1;
3190 have_perspective = TRUE;
3191 }
3192 if (!spi_baryc_cntl)
3193 spi_baryc_cntl |= spi_baryc_enable_bit[0];
3194
3195 if (!have_perspective && !have_linear)
3196 have_perspective = TRUE;
3197
3198 spi_ps_in_control_0 = S_0286CC_NUM_INTERP(ninterp) |
3199 S_0286CC_PERSP_GRADIENT_ENA(have_perspective) |
3200 S_0286CC_LINEAR_GRADIENT_ENA(have_linear);
3201 spi_input_z = 0;
3202 if (pos_index != -1) {
3203 spi_ps_in_control_0 |= S_0286CC_POSITION_ENA(1) |
3204 S_0286CC_POSITION_CENTROID(rshader->input[pos_index].interpolate_location == TGSI_INTERPOLATE_LOC_CENTROID) |
3205 S_0286CC_POSITION_ADDR(rshader->input[pos_index].gpr);
3206 spi_input_z |= S_0286D8_PROVIDE_Z_TO_SPI(1);
3207 }
3208
3209 spi_ps_in_control_1 = 0;
3210 if (face_index != -1) {
3211 spi_ps_in_control_1 |= S_0286D0_FRONT_FACE_ENA(1) |
3212 S_0286D0_FRONT_FACE_ADDR(rshader->input[face_index].gpr);
3213 }
3214 if (fixed_pt_position_index != -1) {
3215 spi_ps_in_control_1 |= S_0286D0_FIXED_PT_POSITION_ENA(1) |
3216 S_0286D0_FIXED_PT_POSITION_ADDR(rshader->input[fixed_pt_position_index].gpr);
3217 }
3218
3219 r600_store_context_reg_seq(cb, R_0286CC_SPI_PS_IN_CONTROL_0, 2);
3220 r600_store_value(cb, spi_ps_in_control_0); /* R_0286CC_SPI_PS_IN_CONTROL_0 */
3221 r600_store_value(cb, spi_ps_in_control_1); /* R_0286D0_SPI_PS_IN_CONTROL_1 */
3222
3223 r600_store_context_reg(cb, R_0286E0_SPI_BARYC_CNTL, spi_baryc_cntl);
3224 r600_store_context_reg(cb, R_0286D8_SPI_INPUT_Z, spi_input_z);
3225 r600_store_context_reg(cb, R_02884C_SQ_PGM_EXPORTS_PS, exports_ps);
3226
3227 r600_store_context_reg_seq(cb, R_028840_SQ_PGM_START_PS, 2);
3228 r600_store_value(cb, shader->bo->gpu_address >> 8);
3229 r600_store_value(cb, /* R_028844_SQ_PGM_RESOURCES_PS */
3230 S_028844_NUM_GPRS(rshader->bc.ngpr) |
3231 S_028844_PRIME_CACHE_ON_DRAW(1) |
3232 S_028844_STACK_SIZE(rshader->bc.nstack));
3233 /* After that, the NOP relocation packet must be emitted (shader->bo, RADEON_USAGE_READ). */
3234
3235 shader->db_shader_control = db_shader_control;
3236 shader->ps_depth_export = z_export | stencil_export | mask_export;
3237
3238 shader->sprite_coord_enable = sprite_coord_enable;
3239 if (rctx->rasterizer)
3240 shader->flatshade = rctx->rasterizer->flatshade;
3241 }
3242
3243 void evergreen_update_es_state(struct pipe_context *ctx, struct r600_pipe_shader *shader)
3244 {
3245 struct r600_command_buffer *cb = &shader->command_buffer;
3246 struct r600_shader *rshader = &shader->shader;
3247
3248 r600_init_command_buffer(cb, 32);
3249
3250 r600_store_context_reg(cb, R_028890_SQ_PGM_RESOURCES_ES,
3251 S_028890_NUM_GPRS(rshader->bc.ngpr) |
3252 S_028890_STACK_SIZE(rshader->bc.nstack));
3253 r600_store_context_reg(cb, R_02888C_SQ_PGM_START_ES,
3254 shader->bo->gpu_address >> 8);
3255 /* After that, the NOP relocation packet must be emitted (shader->bo, RADEON_USAGE_READ). */
3256 }
3257
3258 void evergreen_update_gs_state(struct pipe_context *ctx, struct r600_pipe_shader *shader)
3259 {
3260 struct r600_context *rctx = (struct r600_context *)ctx;
3261 struct r600_command_buffer *cb = &shader->command_buffer;
3262 struct r600_shader *rshader = &shader->shader;
3263 struct r600_shader *cp_shader = &shader->gs_copy_shader->shader;
3264 unsigned gsvs_itemsizes[4] = {
3265 (cp_shader->ring_item_sizes[0] * shader->selector->gs_max_out_vertices) >> 2,
3266 (cp_shader->ring_item_sizes[1] * shader->selector->gs_max_out_vertices) >> 2,
3267 (cp_shader->ring_item_sizes[2] * shader->selector->gs_max_out_vertices) >> 2,
3268 (cp_shader->ring_item_sizes[3] * shader->selector->gs_max_out_vertices) >> 2
3269 };
3270
3271 r600_init_command_buffer(cb, 64);
3272
3273 /* VGT_GS_MODE is written by evergreen_emit_shader_stages */
3274
3275
3276 r600_store_context_reg(cb, R_028B38_VGT_GS_MAX_VERT_OUT,
3277 S_028B38_MAX_VERT_OUT(shader->selector->gs_max_out_vertices));
3278 r600_store_context_reg(cb, R_028A6C_VGT_GS_OUT_PRIM_TYPE,
3279 r600_conv_prim_to_gs_out(shader->selector->gs_output_prim));
3280
3281 if (rctx->screen->b.info.drm_minor >= 35) {
3282 r600_store_context_reg(cb, R_028B90_VGT_GS_INSTANCE_CNT,
3283 S_028B90_CNT(MIN2(shader->selector->gs_num_invocations, 127)) |
3284 S_028B90_ENABLE(shader->selector->gs_num_invocations > 0));
3285 }
3286 r600_store_context_reg_seq(cb, R_02891C_SQ_GS_VERT_ITEMSIZE, 4);
3287 r600_store_value(cb, cp_shader->ring_item_sizes[0] >> 2);
3288 r600_store_value(cb, cp_shader->ring_item_sizes[1] >> 2);
3289 r600_store_value(cb, cp_shader->ring_item_sizes[2] >> 2);
3290 r600_store_value(cb, cp_shader->ring_item_sizes[3] >> 2);
3291
3292 r600_store_context_reg(cb, R_028900_SQ_ESGS_RING_ITEMSIZE,
3293 (rshader->ring_item_sizes[0]) >> 2);
3294
3295 r600_store_context_reg(cb, R_028904_SQ_GSVS_RING_ITEMSIZE,
3296 gsvs_itemsizes[0] +
3297 gsvs_itemsizes[1] +
3298 gsvs_itemsizes[2] +
3299 gsvs_itemsizes[3]);
3300
3301 r600_store_context_reg_seq(cb, R_02892C_SQ_GSVS_RING_OFFSET_1, 3);
3302 r600_store_value(cb, gsvs_itemsizes[0]);
3303 r600_store_value(cb, gsvs_itemsizes[0] + gsvs_itemsizes[1]);
3304 r600_store_value(cb, gsvs_itemsizes[0] + gsvs_itemsizes[1] + gsvs_itemsizes[2]);
3305
3306 /* FIXME calculate these values somehow ??? */
3307 r600_store_context_reg_seq(cb, R_028A54_GS_PER_ES, 3);
3308 r600_store_value(cb, 0x80); /* GS_PER_ES */
3309 r600_store_value(cb, 0x100); /* ES_PER_GS */
3310 r600_store_value(cb, 0x2); /* GS_PER_VS */
3311
3312 r600_store_context_reg(cb, R_028878_SQ_PGM_RESOURCES_GS,
3313 S_028878_NUM_GPRS(rshader->bc.ngpr) |
3314 S_028878_STACK_SIZE(rshader->bc.nstack));
3315 r600_store_context_reg(cb, R_028874_SQ_PGM_START_GS,
3316 shader->bo->gpu_address >> 8);
3317 /* After that, the NOP relocation packet must be emitted (shader->bo, RADEON_USAGE_READ). */
3318 }
3319
3320
3321 void evergreen_update_vs_state(struct pipe_context *ctx, struct r600_pipe_shader *shader)
3322 {
3323 struct r600_command_buffer *cb = &shader->command_buffer;
3324 struct r600_shader *rshader = &shader->shader;
3325 unsigned spi_vs_out_id[10] = {};
3326 unsigned i, tmp, nparams = 0;
3327
3328 for (i = 0; i < rshader->noutput; i++) {
3329 if (rshader->output[i].spi_sid) {
3330 tmp = rshader->output[i].spi_sid << ((nparams & 3) * 8);
3331 spi_vs_out_id[nparams / 4] |= tmp;
3332 nparams++;
3333 }
3334 }
3335
3336 r600_init_command_buffer(cb, 32);
3337
3338 r600_store_context_reg_seq(cb, R_02861C_SPI_VS_OUT_ID_0, 10);
3339 for (i = 0; i < 10; i++) {
3340 r600_store_value(cb, spi_vs_out_id[i]);
3341 }
3342
3343 /* Certain attributes (position, psize, etc.) don't count as params.
3344 * VS is required to export at least one param and r600_shader_from_tgsi()
3345 * takes care of adding a dummy export.
3346 */
3347 if (nparams < 1)
3348 nparams = 1;
3349
3350 r600_store_context_reg(cb, R_0286C4_SPI_VS_OUT_CONFIG,
3351 S_0286C4_VS_EXPORT_COUNT(nparams - 1));
3352 r600_store_context_reg(cb, R_028860_SQ_PGM_RESOURCES_VS,
3353 S_028860_NUM_GPRS(rshader->bc.ngpr) |
3354 S_028860_STACK_SIZE(rshader->bc.nstack));
3355 if (rshader->vs_position_window_space) {
3356 r600_store_context_reg(cb, R_028818_PA_CL_VTE_CNTL,
3357 S_028818_VTX_XY_FMT(1) | S_028818_VTX_Z_FMT(1));
3358 } else {
3359 r600_store_context_reg(cb, R_028818_PA_CL_VTE_CNTL,
3360 S_028818_VTX_W0_FMT(1) |
3361 S_028818_VPORT_X_SCALE_ENA(1) | S_028818_VPORT_X_OFFSET_ENA(1) |
3362 S_028818_VPORT_Y_SCALE_ENA(1) | S_028818_VPORT_Y_OFFSET_ENA(1) |
3363 S_028818_VPORT_Z_SCALE_ENA(1) | S_028818_VPORT_Z_OFFSET_ENA(1));
3364
3365 }
3366 r600_store_context_reg(cb, R_02885C_SQ_PGM_START_VS,
3367 shader->bo->gpu_address >> 8);
3368 /* After that, the NOP relocation packet must be emitted (shader->bo, RADEON_USAGE_READ). */
3369
3370 shader->pa_cl_vs_out_cntl =
3371 S_02881C_VS_OUT_CCDIST0_VEC_ENA((rshader->clip_dist_write & 0x0F) != 0) |
3372 S_02881C_VS_OUT_CCDIST1_VEC_ENA((rshader->clip_dist_write & 0xF0) != 0) |
3373 S_02881C_VS_OUT_MISC_VEC_ENA(rshader->vs_out_misc_write) |
3374 S_02881C_USE_VTX_POINT_SIZE(rshader->vs_out_point_size) |
3375 S_02881C_USE_VTX_EDGE_FLAG(rshader->vs_out_edgeflag) |
3376 S_02881C_USE_VTX_VIEWPORT_INDX(rshader->vs_out_viewport) |
3377 S_02881C_USE_VTX_RENDER_TARGET_INDX(rshader->vs_out_layer);
3378 }
3379
3380 void evergreen_update_hs_state(struct pipe_context *ctx, struct r600_pipe_shader *shader)
3381 {
3382 struct r600_command_buffer *cb = &shader->command_buffer;
3383 struct r600_shader *rshader = &shader->shader;
3384
3385 r600_init_command_buffer(cb, 32);
3386 r600_store_context_reg(cb, R_0288BC_SQ_PGM_RESOURCES_HS,
3387 S_0288BC_NUM_GPRS(rshader->bc.ngpr) |
3388 S_0288BC_STACK_SIZE(rshader->bc.nstack));
3389 r600_store_context_reg(cb, R_0288B8_SQ_PGM_START_HS,
3390 shader->bo->gpu_address >> 8);
3391 }
3392
3393 void evergreen_update_ls_state(struct pipe_context *ctx, struct r600_pipe_shader *shader)
3394 {
3395 struct r600_command_buffer *cb = &shader->command_buffer;
3396 struct r600_shader *rshader = &shader->shader;
3397
3398 r600_init_command_buffer(cb, 32);
3399 r600_store_context_reg(cb, R_0288D4_SQ_PGM_RESOURCES_LS,
3400 S_0288D4_NUM_GPRS(rshader->bc.ngpr) |
3401 S_0288D4_STACK_SIZE(rshader->bc.nstack));
3402 r600_store_context_reg(cb, R_0288D0_SQ_PGM_START_LS,
3403 shader->bo->gpu_address >> 8);
3404 }
3405 void *evergreen_create_resolve_blend(struct r600_context *rctx)
3406 {
3407 struct pipe_blend_state blend;
3408
3409 memset(&blend, 0, sizeof(blend));
3410 blend.independent_blend_enable = true;
3411 blend.rt[0].colormask = 0xf;
3412 return evergreen_create_blend_state_mode(&rctx->b.b, &blend, V_028808_CB_RESOLVE);
3413 }
3414
3415 void *evergreen_create_decompress_blend(struct r600_context *rctx)
3416 {
3417 struct pipe_blend_state blend;
3418 unsigned mode = rctx->screen->has_compressed_msaa_texturing ?
3419 V_028808_CB_FMASK_DECOMPRESS : V_028808_CB_DECOMPRESS;
3420
3421 memset(&blend, 0, sizeof(blend));
3422 blend.independent_blend_enable = true;
3423 blend.rt[0].colormask = 0xf;
3424 return evergreen_create_blend_state_mode(&rctx->b.b, &blend, mode);
3425 }
3426
3427 void *evergreen_create_fastclear_blend(struct r600_context *rctx)
3428 {
3429 struct pipe_blend_state blend;
3430 unsigned mode = V_028808_CB_ELIMINATE_FAST_CLEAR;
3431
3432 memset(&blend, 0, sizeof(blend));
3433 blend.independent_blend_enable = true;
3434 blend.rt[0].colormask = 0xf;
3435 return evergreen_create_blend_state_mode(&rctx->b.b, &blend, mode);
3436 }
3437
3438 void *evergreen_create_db_flush_dsa(struct r600_context *rctx)
3439 {
3440 struct pipe_depth_stencil_alpha_state dsa = {{0}};
3441
3442 return rctx->b.b.create_depth_stencil_alpha_state(&rctx->b.b, &dsa);
3443 }
3444
3445 void evergreen_update_db_shader_control(struct r600_context * rctx)
3446 {
3447 bool dual_export;
3448 unsigned db_shader_control;
3449
3450 if (!rctx->ps_shader) {
3451 return;
3452 }
3453
3454 dual_export = rctx->framebuffer.export_16bpc &&
3455 !rctx->ps_shader->current->ps_depth_export;
3456
3457 db_shader_control = rctx->ps_shader->current->db_shader_control |
3458 S_02880C_DUAL_EXPORT_ENABLE(dual_export) |
3459 S_02880C_DB_SOURCE_FORMAT(dual_export ? V_02880C_EXPORT_DB_TWO :
3460 V_02880C_EXPORT_DB_FULL) |
3461 S_02880C_ALPHA_TO_MASK_DISABLE(rctx->framebuffer.cb0_is_integer);
3462
3463 /* When alpha test is enabled we can't trust the hw to make the proper
3464 * decision on the order in which ztest should be run related to fragment
3465 * shader execution.
3466 *
3467 * If alpha test is enabled perform early z rejection (RE_Z) but don't early
3468 * write to the zbuffer. Write to zbuffer is delayed after fragment shader
3469 * execution and thus after alpha test so if discarded by the alpha test
3470 * the z value is not written.
3471 * If ReZ is enabled, and the zfunc/zenable/zwrite values change you can
3472 * get a hang unless you flush the DB in between. For now just use
3473 * LATE_Z.
3474 */
3475 if (rctx->alphatest_state.sx_alpha_test_control) {
3476 db_shader_control |= S_02880C_Z_ORDER(V_02880C_LATE_Z);
3477 } else {
3478 db_shader_control |= S_02880C_Z_ORDER(V_02880C_EARLY_Z_THEN_LATE_Z);
3479 }
3480
3481 if (db_shader_control != rctx->db_misc_state.db_shader_control) {
3482 rctx->db_misc_state.db_shader_control = db_shader_control;
3483 r600_mark_atom_dirty(rctx, &rctx->db_misc_state.atom);
3484 }
3485 }
3486
3487 static void evergreen_dma_copy_tile(struct r600_context *rctx,
3488 struct pipe_resource *dst,
3489 unsigned dst_level,
3490 unsigned dst_x,
3491 unsigned dst_y,
3492 unsigned dst_z,
3493 struct pipe_resource *src,
3494 unsigned src_level,
3495 unsigned src_x,
3496 unsigned src_y,
3497 unsigned src_z,
3498 unsigned copy_height,
3499 unsigned pitch,
3500 unsigned bpp)
3501 {
3502 struct radeon_winsys_cs *cs = rctx->b.dma.cs;
3503 struct r600_texture *rsrc = (struct r600_texture*)src;
3504 struct r600_texture *rdst = (struct r600_texture*)dst;
3505 unsigned array_mode, lbpp, pitch_tile_max, slice_tile_max, size;
3506 unsigned ncopy, height, cheight, detile, i, x, y, z, src_mode, dst_mode;
3507 unsigned sub_cmd, bank_h, bank_w, mt_aspect, nbanks, tile_split, non_disp_tiling = 0;
3508 uint64_t base, addr;
3509
3510 dst_mode = rdst->surface.u.legacy.level[dst_level].mode;
3511 src_mode = rsrc->surface.u.legacy.level[src_level].mode;
3512 assert(dst_mode != src_mode);
3513
3514 /* non_disp_tiling bit needs to be set for depth, stencil, and fmask surfaces */
3515 if (util_format_has_depth(util_format_description(src->format)))
3516 non_disp_tiling = 1;
3517
3518 y = 0;
3519 sub_cmd = EG_DMA_COPY_TILED;
3520 lbpp = util_logbase2(bpp);
3521 pitch_tile_max = ((pitch / bpp) / 8) - 1;
3522 nbanks = eg_num_banks(rctx->screen->b.info.r600_num_banks);
3523
3524 if (dst_mode == RADEON_SURF_MODE_LINEAR_ALIGNED) {
3525 /* T2L */
3526 array_mode = evergreen_array_mode(src_mode);
3527 slice_tile_max = (rsrc->surface.u.legacy.level[src_level].nblk_x * rsrc->surface.u.legacy.level[src_level].nblk_y) / (8*8);
3528 slice_tile_max = slice_tile_max ? slice_tile_max - 1 : 0;
3529 /* linear height must be the same as the slice tile max height, it's ok even
3530 * if the linear destination/source have smaller heigh as the size of the
3531 * dma packet will be using the copy_height which is always smaller or equal
3532 * to the linear height
3533 */
3534 height = u_minify(rsrc->resource.b.b.height0, src_level);
3535 detile = 1;
3536 x = src_x;
3537 y = src_y;
3538 z = src_z;
3539 base = rsrc->surface.u.legacy.level[src_level].offset;
3540 addr = rdst->surface.u.legacy.level[dst_level].offset;
3541 addr += rdst->surface.u.legacy.level[dst_level].slice_size * dst_z;
3542 addr += dst_y * pitch + dst_x * bpp;
3543 bank_h = eg_bank_wh(rsrc->surface.u.legacy.bankh);
3544 bank_w = eg_bank_wh(rsrc->surface.u.legacy.bankw);
3545 mt_aspect = eg_macro_tile_aspect(rsrc->surface.u.legacy.mtilea);
3546 tile_split = eg_tile_split(rsrc->surface.u.legacy.tile_split);
3547 base += rsrc->resource.gpu_address;
3548 addr += rdst->resource.gpu_address;
3549 } else {
3550 /* L2T */
3551 array_mode = evergreen_array_mode(dst_mode);
3552 slice_tile_max = (rdst->surface.u.legacy.level[dst_level].nblk_x * rdst->surface.u.legacy.level[dst_level].nblk_y) / (8*8);
3553 slice_tile_max = slice_tile_max ? slice_tile_max - 1 : 0;
3554 /* linear height must be the same as the slice tile max height, it's ok even
3555 * if the linear destination/source have smaller heigh as the size of the
3556 * dma packet will be using the copy_height which is always smaller or equal
3557 * to the linear height
3558 */
3559 height = u_minify(rdst->resource.b.b.height0, dst_level);
3560 detile = 0;
3561 x = dst_x;
3562 y = dst_y;
3563 z = dst_z;
3564 base = rdst->surface.u.legacy.level[dst_level].offset;
3565 addr = rsrc->surface.u.legacy.level[src_level].offset;
3566 addr += rsrc->surface.u.legacy.level[src_level].slice_size * src_z;
3567 addr += src_y * pitch + src_x * bpp;
3568 bank_h = eg_bank_wh(rdst->surface.u.legacy.bankh);
3569 bank_w = eg_bank_wh(rdst->surface.u.legacy.bankw);
3570 mt_aspect = eg_macro_tile_aspect(rdst->surface.u.legacy.mtilea);
3571 tile_split = eg_tile_split(rdst->surface.u.legacy.tile_split);
3572 base += rdst->resource.gpu_address;
3573 addr += rsrc->resource.gpu_address;
3574 }
3575
3576 size = (copy_height * pitch) / 4;
3577 ncopy = (size / EG_DMA_COPY_MAX_SIZE) + !!(size % EG_DMA_COPY_MAX_SIZE);
3578 r600_need_dma_space(&rctx->b, ncopy * 9, &rdst->resource, &rsrc->resource);
3579
3580 for (i = 0; i < ncopy; i++) {
3581 cheight = copy_height;
3582 if (((cheight * pitch) / 4) > EG_DMA_COPY_MAX_SIZE) {
3583 cheight = (EG_DMA_COPY_MAX_SIZE * 4) / pitch;
3584 }
3585 size = (cheight * pitch) / 4;
3586 /* emit reloc before writing cs so that cs is always in consistent state */
3587 radeon_add_to_buffer_list(&rctx->b, &rctx->b.dma, &rsrc->resource,
3588 RADEON_USAGE_READ, RADEON_PRIO_SDMA_TEXTURE);
3589 radeon_add_to_buffer_list(&rctx->b, &rctx->b.dma, &rdst->resource,
3590 RADEON_USAGE_WRITE, RADEON_PRIO_SDMA_TEXTURE);
3591 radeon_emit(cs, DMA_PACKET(DMA_PACKET_COPY, sub_cmd, size));
3592 radeon_emit(cs, base >> 8);
3593 radeon_emit(cs, (detile << 31) | (array_mode << 27) |
3594 (lbpp << 24) | (bank_h << 21) |
3595 (bank_w << 18) | (mt_aspect << 16));
3596 radeon_emit(cs, (pitch_tile_max << 0) | ((height - 1) << 16));
3597 radeon_emit(cs, (slice_tile_max << 0));
3598 radeon_emit(cs, (x << 0) | (z << 18));
3599 radeon_emit(cs, (y << 0) | (tile_split << 21) | (nbanks << 25) | (non_disp_tiling << 28));
3600 radeon_emit(cs, addr & 0xfffffffc);
3601 radeon_emit(cs, (addr >> 32UL) & 0xff);
3602 copy_height -= cheight;
3603 addr += cheight * pitch;
3604 y += cheight;
3605 }
3606 }
3607
3608 static void evergreen_dma_copy(struct pipe_context *ctx,
3609 struct pipe_resource *dst,
3610 unsigned dst_level,
3611 unsigned dstx, unsigned dsty, unsigned dstz,
3612 struct pipe_resource *src,
3613 unsigned src_level,
3614 const struct pipe_box *src_box)
3615 {
3616 struct r600_context *rctx = (struct r600_context *)ctx;
3617 struct r600_texture *rsrc = (struct r600_texture*)src;
3618 struct r600_texture *rdst = (struct r600_texture*)dst;
3619 unsigned dst_pitch, src_pitch, bpp, dst_mode, src_mode, copy_height;
3620 unsigned src_w, dst_w;
3621 unsigned src_x, src_y;
3622 unsigned dst_x = dstx, dst_y = dsty, dst_z = dstz;
3623
3624 if (rctx->b.dma.cs == NULL) {
3625 goto fallback;
3626 }
3627
3628 if (dst->target == PIPE_BUFFER && src->target == PIPE_BUFFER) {
3629 evergreen_dma_copy_buffer(rctx, dst, src, dst_x, src_box->x, src_box->width);
3630 return;
3631 }
3632
3633 if (src_box->depth > 1 ||
3634 !r600_prepare_for_dma_blit(&rctx->b, rdst, dst_level, dstx, dsty,
3635 dstz, rsrc, src_level, src_box))
3636 goto fallback;
3637
3638 src_x = util_format_get_nblocksx(src->format, src_box->x);
3639 dst_x = util_format_get_nblocksx(src->format, dst_x);
3640 src_y = util_format_get_nblocksy(src->format, src_box->y);
3641 dst_y = util_format_get_nblocksy(src->format, dst_y);
3642
3643 bpp = rdst->surface.bpe;
3644 dst_pitch = rdst->surface.u.legacy.level[dst_level].nblk_x * rdst->surface.bpe;
3645 src_pitch = rsrc->surface.u.legacy.level[src_level].nblk_x * rsrc->surface.bpe;
3646 src_w = u_minify(rsrc->resource.b.b.width0, src_level);
3647 dst_w = u_minify(rdst->resource.b.b.width0, dst_level);
3648 copy_height = src_box->height / rsrc->surface.blk_h;
3649
3650 dst_mode = rdst->surface.u.legacy.level[dst_level].mode;
3651 src_mode = rsrc->surface.u.legacy.level[src_level].mode;
3652
3653 if (src_pitch != dst_pitch || src_box->x || dst_x || src_w != dst_w) {
3654 /* FIXME evergreen can do partial blit */
3655 goto fallback;
3656 }
3657 /* the x test here are currently useless (because we don't support partial blit)
3658 * but keep them around so we don't forget about those
3659 */
3660 if (src_pitch % 8 || src_box->x % 8 || dst_x % 8 || src_box->y % 8 || dst_y % 8) {
3661 goto fallback;
3662 }
3663
3664 /* 128 bpp surfaces require non_disp_tiling for both
3665 * tiled and linear buffers on cayman. However, async
3666 * DMA only supports it on the tiled side. As such
3667 * the tile order is backwards after a L2T/T2L packet.
3668 */
3669 if ((rctx->b.chip_class == CAYMAN) &&
3670 (src_mode != dst_mode) &&
3671 (util_format_get_blocksize(src->format) >= 16)) {
3672 goto fallback;
3673 }
3674
3675 if (src_mode == dst_mode) {
3676 uint64_t dst_offset, src_offset;
3677 /* simple dma blit would do NOTE code here assume :
3678 * src_box.x/y == 0
3679 * dst_x/y == 0
3680 * dst_pitch == src_pitch
3681 */
3682 src_offset= rsrc->surface.u.legacy.level[src_level].offset;
3683 src_offset += rsrc->surface.u.legacy.level[src_level].slice_size * src_box->z;
3684 src_offset += src_y * src_pitch + src_x * bpp;
3685 dst_offset = rdst->surface.u.legacy.level[dst_level].offset;
3686 dst_offset += rdst->surface.u.legacy.level[dst_level].slice_size * dst_z;
3687 dst_offset += dst_y * dst_pitch + dst_x * bpp;
3688 evergreen_dma_copy_buffer(rctx, dst, src, dst_offset, src_offset,
3689 src_box->height * src_pitch);
3690 } else {
3691 evergreen_dma_copy_tile(rctx, dst, dst_level, dst_x, dst_y, dst_z,
3692 src, src_level, src_x, src_y, src_box->z,
3693 copy_height, dst_pitch, bpp);
3694 }
3695 return;
3696
3697 fallback:
3698 r600_resource_copy_region(ctx, dst, dst_level, dstx, dsty, dstz,
3699 src, src_level, src_box);
3700 }
3701
3702 static void evergreen_set_tess_state(struct pipe_context *ctx,
3703 const float default_outer_level[4],
3704 const float default_inner_level[2])
3705 {
3706 struct r600_context *rctx = (struct r600_context *)ctx;
3707
3708 memcpy(rctx->tess_state, default_outer_level, sizeof(float) * 4);
3709 memcpy(rctx->tess_state+4, default_inner_level, sizeof(float) * 2);
3710 rctx->tess_state_dirty = true;
3711 }
3712
3713 void evergreen_init_state_functions(struct r600_context *rctx)
3714 {
3715 unsigned id = 1;
3716 unsigned i;
3717 /* !!!
3718 * To avoid GPU lockup registers must be emitted in a specific order
3719 * (no kidding ...). The order below is important and have been
3720 * partially inferred from analyzing fglrx command stream.
3721 *
3722 * Don't reorder atom without carefully checking the effect (GPU lockup
3723 * or piglit regression).
3724 * !!!
3725 */
3726 if (rctx->b.chip_class == EVERGREEN) {
3727 r600_init_atom(rctx, &rctx->config_state.atom, id++, evergreen_emit_config_state, 11);
3728 rctx->config_state.dyn_gpr_enabled = true;
3729 }
3730 r600_init_atom(rctx, &rctx->framebuffer.atom, id++, evergreen_emit_framebuffer_state, 0);
3731 /* shader const */
3732 r600_init_atom(rctx, &rctx->constbuf_state[PIPE_SHADER_VERTEX].atom, id++, evergreen_emit_vs_constant_buffers, 0);
3733 r600_init_atom(rctx, &rctx->constbuf_state[PIPE_SHADER_GEOMETRY].atom, id++, evergreen_emit_gs_constant_buffers, 0);
3734 r600_init_atom(rctx, &rctx->constbuf_state[PIPE_SHADER_FRAGMENT].atom, id++, evergreen_emit_ps_constant_buffers, 0);
3735 r600_init_atom(rctx, &rctx->constbuf_state[PIPE_SHADER_TESS_CTRL].atom, id++, evergreen_emit_tcs_constant_buffers, 0);
3736 r600_init_atom(rctx, &rctx->constbuf_state[PIPE_SHADER_TESS_EVAL].atom, id++, evergreen_emit_tes_constant_buffers, 0);
3737 r600_init_atom(rctx, &rctx->constbuf_state[PIPE_SHADER_COMPUTE].atom, id++, evergreen_emit_cs_constant_buffers, 0);
3738 /* shader program */
3739 r600_init_atom(rctx, &rctx->cs_shader_state.atom, id++, evergreen_emit_cs_shader, 0);
3740 /* sampler */
3741 r600_init_atom(rctx, &rctx->samplers[PIPE_SHADER_VERTEX].states.atom, id++, evergreen_emit_vs_sampler_states, 0);
3742 r600_init_atom(rctx, &rctx->samplers[PIPE_SHADER_GEOMETRY].states.atom, id++, evergreen_emit_gs_sampler_states, 0);
3743 r600_init_atom(rctx, &rctx->samplers[PIPE_SHADER_TESS_CTRL].states.atom, id++, evergreen_emit_tcs_sampler_states, 0);
3744 r600_init_atom(rctx, &rctx->samplers[PIPE_SHADER_TESS_EVAL].states.atom, id++, evergreen_emit_tes_sampler_states, 0);
3745 r600_init_atom(rctx, &rctx->samplers[PIPE_SHADER_FRAGMENT].states.atom, id++, evergreen_emit_ps_sampler_states, 0);
3746 r600_init_atom(rctx, &rctx->samplers[PIPE_SHADER_COMPUTE].states.atom, id++, evergreen_emit_cs_sampler_states, 0);
3747 /* resources */
3748 r600_init_atom(rctx, &rctx->vertex_buffer_state.atom, id++, evergreen_fs_emit_vertex_buffers, 0);
3749 r600_init_atom(rctx, &rctx->cs_vertex_buffer_state.atom, id++, evergreen_cs_emit_vertex_buffers, 0);
3750 r600_init_atom(rctx, &rctx->samplers[PIPE_SHADER_VERTEX].views.atom, id++, evergreen_emit_vs_sampler_views, 0);
3751 r600_init_atom(rctx, &rctx->samplers[PIPE_SHADER_GEOMETRY].views.atom, id++, evergreen_emit_gs_sampler_views, 0);
3752 r600_init_atom(rctx, &rctx->samplers[PIPE_SHADER_TESS_CTRL].views.atom, id++, evergreen_emit_tcs_sampler_views, 0);
3753 r600_init_atom(rctx, &rctx->samplers[PIPE_SHADER_TESS_EVAL].views.atom, id++, evergreen_emit_tes_sampler_views, 0);
3754 r600_init_atom(rctx, &rctx->samplers[PIPE_SHADER_FRAGMENT].views.atom, id++, evergreen_emit_ps_sampler_views, 0);
3755 r600_init_atom(rctx, &rctx->samplers[PIPE_SHADER_COMPUTE].views.atom, id++, evergreen_emit_cs_sampler_views, 0);
3756
3757 r600_init_atom(rctx, &rctx->vgt_state.atom, id++, r600_emit_vgt_state, 10);
3758
3759 if (rctx->b.chip_class == EVERGREEN) {
3760 r600_init_atom(rctx, &rctx->sample_mask.atom, id++, evergreen_emit_sample_mask, 3);
3761 } else {
3762 r600_init_atom(rctx, &rctx->sample_mask.atom, id++, cayman_emit_sample_mask, 4);
3763 }
3764 rctx->sample_mask.sample_mask = ~0;
3765
3766 r600_init_atom(rctx, &rctx->alphatest_state.atom, id++, r600_emit_alphatest_state, 6);
3767 r600_init_atom(rctx, &rctx->blend_color.atom, id++, r600_emit_blend_color, 6);
3768 r600_init_atom(rctx, &rctx->blend_state.atom, id++, r600_emit_cso_state, 0);
3769 r600_init_atom(rctx, &rctx->cb_misc_state.atom, id++, evergreen_emit_cb_misc_state, 4);
3770 r600_init_atom(rctx, &rctx->clip_misc_state.atom, id++, r600_emit_clip_misc_state, 9);
3771 r600_init_atom(rctx, &rctx->clip_state.atom, id++, evergreen_emit_clip_state, 26);
3772 r600_init_atom(rctx, &rctx->db_misc_state.atom, id++, evergreen_emit_db_misc_state, 10);
3773 r600_init_atom(rctx, &rctx->db_state.atom, id++, evergreen_emit_db_state, 14);
3774 r600_init_atom(rctx, &rctx->dsa_state.atom, id++, r600_emit_cso_state, 0);
3775 r600_init_atom(rctx, &rctx->poly_offset_state.atom, id++, evergreen_emit_polygon_offset, 9);
3776 r600_init_atom(rctx, &rctx->rasterizer_state.atom, id++, r600_emit_cso_state, 0);
3777 r600_add_atom(rctx, &rctx->b.scissors.atom, id++);
3778 r600_add_atom(rctx, &rctx->b.viewports.atom, id++);
3779 r600_init_atom(rctx, &rctx->stencil_ref.atom, id++, r600_emit_stencil_ref, 4);
3780 r600_init_atom(rctx, &rctx->vertex_fetch_shader.atom, id++, evergreen_emit_vertex_fetch_shader, 5);
3781 r600_add_atom(rctx, &rctx->b.render_cond_atom, id++);
3782 r600_add_atom(rctx, &rctx->b.streamout.begin_atom, id++);
3783 r600_add_atom(rctx, &rctx->b.streamout.enable_atom, id++);
3784 for (i = 0; i < EG_NUM_HW_STAGES; i++)
3785 r600_init_atom(rctx, &rctx->hw_shader_stages[i].atom, id++, r600_emit_shader, 0);
3786 r600_init_atom(rctx, &rctx->shader_stages.atom, id++, evergreen_emit_shader_stages, 15);
3787 r600_init_atom(rctx, &rctx->gs_rings.atom, id++, evergreen_emit_gs_rings, 26);
3788
3789 rctx->b.b.create_blend_state = evergreen_create_blend_state;
3790 rctx->b.b.create_depth_stencil_alpha_state = evergreen_create_dsa_state;
3791 rctx->b.b.create_rasterizer_state = evergreen_create_rs_state;
3792 rctx->b.b.create_sampler_state = evergreen_create_sampler_state;
3793 rctx->b.b.create_sampler_view = evergreen_create_sampler_view;
3794 rctx->b.b.set_framebuffer_state = evergreen_set_framebuffer_state;
3795 rctx->b.b.set_polygon_stipple = evergreen_set_polygon_stipple;
3796 rctx->b.b.set_min_samples = evergreen_set_min_samples;
3797 rctx->b.b.set_tess_state = evergreen_set_tess_state;
3798 if (rctx->b.chip_class == EVERGREEN)
3799 rctx->b.b.get_sample_position = evergreen_get_sample_position;
3800 else
3801 rctx->b.b.get_sample_position = cayman_get_sample_position;
3802 rctx->b.dma_copy = evergreen_dma_copy;
3803
3804 evergreen_init_compute_state_functions(rctx);
3805 }
3806
3807 /**
3808 * This calculates the LDS size for tessellation shaders (VS, TCS, TES).
3809 *
3810 * The information about LDS and other non-compile-time parameters is then
3811 * written to the const buffer.
3812
3813 * const buffer contains -
3814 * uint32_t input_patch_size
3815 * uint32_t input_vertex_size
3816 * uint32_t num_tcs_input_cp
3817 * uint32_t num_tcs_output_cp;
3818 * uint32_t output_patch_size
3819 * uint32_t output_vertex_size
3820 * uint32_t output_patch0_offset
3821 * uint32_t perpatch_output_offset
3822 * and the same constbuf is bound to LS/HS/VS(ES).
3823 */
3824 void evergreen_setup_tess_constants(struct r600_context *rctx, const struct pipe_draw_info *info, unsigned *num_patches)
3825 {
3826 struct pipe_constant_buffer constbuf = {0};
3827 struct r600_pipe_shader_selector *tcs = rctx->tcs_shader ? rctx->tcs_shader : rctx->tes_shader;
3828 struct r600_pipe_shader_selector *ls = rctx->vs_shader;
3829 unsigned num_tcs_input_cp = info->vertices_per_patch;
3830 unsigned num_tcs_outputs;
3831 unsigned num_tcs_output_cp;
3832 unsigned num_tcs_patch_outputs;
3833 unsigned num_tcs_inputs;
3834 unsigned input_vertex_size, output_vertex_size;
3835 unsigned input_patch_size, pervertex_output_patch_size, output_patch_size;
3836 unsigned output_patch0_offset, perpatch_output_offset, lds_size;
3837 uint32_t values[16];
3838 unsigned num_waves;
3839 unsigned num_pipes = rctx->screen->b.info.r600_max_quad_pipes;
3840 unsigned wave_divisor = (16 * num_pipes);
3841
3842 *num_patches = 1;
3843
3844 if (!rctx->tes_shader) {
3845 rctx->lds_alloc = 0;
3846 rctx->b.b.set_constant_buffer(&rctx->b.b, PIPE_SHADER_VERTEX,
3847 R600_LDS_INFO_CONST_BUFFER, NULL);
3848 rctx->b.b.set_constant_buffer(&rctx->b.b, PIPE_SHADER_TESS_CTRL,
3849 R600_LDS_INFO_CONST_BUFFER, NULL);
3850 rctx->b.b.set_constant_buffer(&rctx->b.b, PIPE_SHADER_TESS_EVAL,
3851 R600_LDS_INFO_CONST_BUFFER, NULL);
3852 return;
3853 }
3854
3855 if (rctx->lds_alloc != 0 &&
3856 rctx->last_ls == ls &&
3857 !rctx->tess_state_dirty &&
3858 rctx->last_num_tcs_input_cp == num_tcs_input_cp &&
3859 rctx->last_tcs == tcs)
3860 return;
3861
3862 num_tcs_inputs = util_last_bit64(ls->lds_outputs_written_mask);
3863
3864 if (rctx->tcs_shader) {
3865 num_tcs_outputs = util_last_bit64(tcs->lds_outputs_written_mask);
3866 num_tcs_output_cp = tcs->info.properties[TGSI_PROPERTY_TCS_VERTICES_OUT];
3867 num_tcs_patch_outputs = util_last_bit64(tcs->lds_patch_outputs_written_mask);
3868 } else {
3869 num_tcs_outputs = num_tcs_inputs;
3870 num_tcs_output_cp = num_tcs_input_cp;
3871 num_tcs_patch_outputs = 2; /* TESSINNER + TESSOUTER */
3872 }
3873
3874 /* size in bytes */
3875 input_vertex_size = num_tcs_inputs * 16;
3876 output_vertex_size = num_tcs_outputs * 16;
3877
3878 input_patch_size = num_tcs_input_cp * input_vertex_size;
3879
3880 pervertex_output_patch_size = num_tcs_output_cp * output_vertex_size;
3881 output_patch_size = pervertex_output_patch_size + num_tcs_patch_outputs * 16;
3882
3883 output_patch0_offset = rctx->tcs_shader ? input_patch_size * *num_patches : 0;
3884 perpatch_output_offset = output_patch0_offset + pervertex_output_patch_size;
3885
3886 lds_size = output_patch0_offset + output_patch_size * *num_patches;
3887
3888 values[0] = input_patch_size;
3889 values[1] = input_vertex_size;
3890 values[2] = num_tcs_input_cp;
3891 values[3] = num_tcs_output_cp;
3892
3893 values[4] = output_patch_size;
3894 values[5] = output_vertex_size;
3895 values[6] = output_patch0_offset;
3896 values[7] = perpatch_output_offset;
3897
3898 /* docs say HS_NUM_WAVES - CEIL((LS_HS_CONFIG.NUM_PATCHES *
3899 LS_HS_CONFIG.HS_NUM_OUTPUT_CP) / (NUM_GOOD_PIPES * 16)) */
3900 num_waves = ceilf((float)(*num_patches * num_tcs_output_cp) / (float)wave_divisor);
3901
3902 rctx->lds_alloc = (lds_size | (num_waves << 14));
3903
3904 memcpy(&values[8], rctx->tess_state, 6 * sizeof(float));
3905 values[14] = 0;
3906 values[15] = 0;
3907
3908 rctx->tess_state_dirty = false;
3909 rctx->last_ls = ls;
3910 rctx->last_tcs = tcs;
3911 rctx->last_num_tcs_input_cp = num_tcs_input_cp;
3912
3913 constbuf.user_buffer = values;
3914 constbuf.buffer_size = 16 * 4;
3915
3916 rctx->b.b.set_constant_buffer(&rctx->b.b, PIPE_SHADER_VERTEX,
3917 R600_LDS_INFO_CONST_BUFFER, &constbuf);
3918 rctx->b.b.set_constant_buffer(&rctx->b.b, PIPE_SHADER_TESS_CTRL,
3919 R600_LDS_INFO_CONST_BUFFER, &constbuf);
3920 rctx->b.b.set_constant_buffer(&rctx->b.b, PIPE_SHADER_TESS_EVAL,
3921 R600_LDS_INFO_CONST_BUFFER, &constbuf);
3922 pipe_resource_reference(&constbuf.buffer, NULL);
3923 }
3924
3925 uint32_t evergreen_get_ls_hs_config(struct r600_context *rctx,
3926 const struct pipe_draw_info *info,
3927 unsigned num_patches)
3928 {
3929 unsigned num_output_cp;
3930
3931 if (!rctx->tes_shader)
3932 return 0;
3933
3934 num_output_cp = rctx->tcs_shader ?
3935 rctx->tcs_shader->info.properties[TGSI_PROPERTY_TCS_VERTICES_OUT] :
3936 info->vertices_per_patch;
3937
3938 return S_028B58_NUM_PATCHES(num_patches) |
3939 S_028B58_HS_NUM_INPUT_CP(info->vertices_per_patch) |
3940 S_028B58_HS_NUM_OUTPUT_CP(num_output_cp);
3941 }
3942
3943 void evergreen_set_ls_hs_config(struct r600_context *rctx,
3944 struct radeon_winsys_cs *cs,
3945 uint32_t ls_hs_config)
3946 {
3947 radeon_set_context_reg(cs, R_028B58_VGT_LS_HS_CONFIG, ls_hs_config);
3948 }
3949
3950 void evergreen_set_lds_alloc(struct r600_context *rctx,
3951 struct radeon_winsys_cs *cs,
3952 uint32_t lds_alloc)
3953 {
3954 radeon_set_context_reg(cs, R_0288E8_SQ_LDS_ALLOC, lds_alloc);
3955 }
3956
3957 /* on evergreen if you are running tessellation you need to disable dynamic
3958 GPRs to workaround a hardware bug.*/
3959 bool evergreen_adjust_gprs(struct r600_context *rctx)
3960 {
3961 unsigned num_gprs[EG_NUM_HW_STAGES];
3962 unsigned def_gprs[EG_NUM_HW_STAGES];
3963 unsigned cur_gprs[EG_NUM_HW_STAGES];
3964 unsigned new_gprs[EG_NUM_HW_STAGES];
3965 unsigned def_num_clause_temp_gprs = rctx->r6xx_num_clause_temp_gprs;
3966 unsigned max_gprs;
3967 unsigned i;
3968 unsigned total_gprs;
3969 unsigned tmp[3];
3970 bool rework = false, set_default = false, set_dirty = false;
3971 max_gprs = 0;
3972 for (i = 0; i < EG_NUM_HW_STAGES; i++) {
3973 def_gprs[i] = rctx->default_gprs[i];
3974 max_gprs += def_gprs[i];
3975 }
3976 max_gprs += def_num_clause_temp_gprs * 2;
3977
3978 /* if we have no TESS and dyn gpr is enabled then do nothing. */
3979 if (!rctx->hw_shader_stages[EG_HW_STAGE_HS].shader) {
3980 if (rctx->config_state.dyn_gpr_enabled)
3981 return true;
3982
3983 /* transition back to dyn gpr enabled state */
3984 rctx->config_state.dyn_gpr_enabled = true;
3985 r600_mark_atom_dirty(rctx, &rctx->config_state.atom);
3986 rctx->b.flags |= R600_CONTEXT_WAIT_3D_IDLE;
3987 return true;
3988 }
3989
3990
3991 /* gather required shader gprs */
3992 for (i = 0; i < EG_NUM_HW_STAGES; i++) {
3993 if (rctx->hw_shader_stages[i].shader)
3994 num_gprs[i] = rctx->hw_shader_stages[i].shader->shader.bc.ngpr;
3995 else
3996 num_gprs[i] = 0;
3997 }
3998
3999 cur_gprs[R600_HW_STAGE_PS] = G_008C04_NUM_PS_GPRS(rctx->config_state.sq_gpr_resource_mgmt_1);
4000 cur_gprs[R600_HW_STAGE_VS] = G_008C04_NUM_VS_GPRS(rctx->config_state.sq_gpr_resource_mgmt_1);
4001 cur_gprs[R600_HW_STAGE_GS] = G_008C08_NUM_GS_GPRS(rctx->config_state.sq_gpr_resource_mgmt_2);
4002 cur_gprs[R600_HW_STAGE_ES] = G_008C08_NUM_ES_GPRS(rctx->config_state.sq_gpr_resource_mgmt_2);
4003 cur_gprs[EG_HW_STAGE_LS] = G_008C0C_NUM_LS_GPRS(rctx->config_state.sq_gpr_resource_mgmt_3);
4004 cur_gprs[EG_HW_STAGE_HS] = G_008C0C_NUM_HS_GPRS(rctx->config_state.sq_gpr_resource_mgmt_3);
4005
4006 total_gprs = 0;
4007 for (i = 0; i < EG_NUM_HW_STAGES; i++) {
4008 new_gprs[i] = num_gprs[i];
4009 total_gprs += num_gprs[i];
4010 }
4011
4012 if (total_gprs > (max_gprs - (2 * def_num_clause_temp_gprs)))
4013 return false;
4014
4015 for (i = 0; i < EG_NUM_HW_STAGES; i++) {
4016 if (new_gprs[i] > cur_gprs[i]) {
4017 rework = true;
4018 break;
4019 }
4020 }
4021
4022 if (rctx->config_state.dyn_gpr_enabled) {
4023 set_dirty = true;
4024 rctx->config_state.dyn_gpr_enabled = false;
4025 }
4026
4027 if (rework) {
4028 set_default = true;
4029 for (i = 0; i < EG_NUM_HW_STAGES; i++) {
4030 if (new_gprs[i] > def_gprs[i])
4031 set_default = false;
4032 }
4033
4034 if (set_default) {
4035 for (i = 0; i < EG_NUM_HW_STAGES; i++) {
4036 new_gprs[i] = def_gprs[i];
4037 }
4038 } else {
4039 unsigned ps_value = max_gprs;
4040
4041 ps_value -= (def_num_clause_temp_gprs * 2);
4042 for (i = R600_HW_STAGE_VS; i < EG_NUM_HW_STAGES; i++)
4043 ps_value -= new_gprs[i];
4044
4045 new_gprs[R600_HW_STAGE_PS] = ps_value;
4046 }
4047
4048 tmp[0] = S_008C04_NUM_PS_GPRS(new_gprs[R600_HW_STAGE_PS]) |
4049 S_008C04_NUM_VS_GPRS(new_gprs[R600_HW_STAGE_VS]) |
4050 S_008C04_NUM_CLAUSE_TEMP_GPRS(def_num_clause_temp_gprs);
4051
4052 tmp[1] = S_008C08_NUM_ES_GPRS(new_gprs[R600_HW_STAGE_ES]) |
4053 S_008C08_NUM_GS_GPRS(new_gprs[R600_HW_STAGE_GS]);
4054
4055 tmp[2] = S_008C0C_NUM_HS_GPRS(new_gprs[EG_HW_STAGE_HS]) |
4056 S_008C0C_NUM_LS_GPRS(new_gprs[EG_HW_STAGE_LS]);
4057
4058 if (rctx->config_state.sq_gpr_resource_mgmt_1 != tmp[0] ||
4059 rctx->config_state.sq_gpr_resource_mgmt_2 != tmp[1] ||
4060 rctx->config_state.sq_gpr_resource_mgmt_3 != tmp[2]) {
4061 rctx->config_state.sq_gpr_resource_mgmt_1 = tmp[0];
4062 rctx->config_state.sq_gpr_resource_mgmt_2 = tmp[1];
4063 rctx->config_state.sq_gpr_resource_mgmt_3 = tmp[2];
4064 set_dirty = true;
4065 }
4066 }
4067
4068
4069 if (set_dirty) {
4070 r600_mark_atom_dirty(rctx, &rctx->config_state.atom);
4071 rctx->b.flags |= R600_CONTEXT_WAIT_3D_IDLE;
4072 }
4073 return true;
4074 }