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[mesa.git] / src / gallium / drivers / r600 / evergreen_state.c
1 /*
2 * Copyright 2010 Jerome Glisse <glisse@freedesktop.org>
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * on the rights to use, copy, modify, merge, publish, distribute, sub
8 * license, and/or sell copies of the Software, and to permit persons to whom
9 * the Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
13 * Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHOR(S) AND/OR THEIR SUPPLIERS BE LIABLE FOR ANY CLAIM,
19 * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
20 * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
21 * USE OR OTHER DEALINGS IN THE SOFTWARE.
22 */
23
24 /* TODO:
25 * - fix mask for depth control & cull for query
26 */
27 #include <stdio.h>
28 #include <errno.h>
29 #include <pipe/p_defines.h>
30 #include <pipe/p_state.h>
31 #include <pipe/p_context.h>
32 #include <tgsi/tgsi_scan.h>
33 #include <tgsi/tgsi_parse.h>
34 #include <tgsi/tgsi_util.h>
35 #include <util/u_blitter.h>
36 #include <util/u_double_list.h>
37 #include <util/u_transfer.h>
38 #include <util/u_surface.h>
39 #include <util/u_pack_color.h>
40 #include <util/u_memory.h>
41 #include <util/u_inlines.h>
42 #include <pipebuffer/pb_buffer.h>
43 #include "r600.h"
44 #include "evergreend.h"
45 #include "r600_resource.h"
46 #include "r600_shader.h"
47 #include "r600_pipe.h"
48 #include "eg_state_inlines.h"
49
50 static void evergreen_set_blend_color(struct pipe_context *ctx,
51 const struct pipe_blend_color *state)
52 {
53 struct r600_pipe_context *rctx = (struct r600_pipe_context *)ctx;
54 struct r600_pipe_state *rstate = CALLOC_STRUCT(r600_pipe_state);
55
56 if (rstate == NULL)
57 return;
58
59 rstate->id = R600_PIPE_STATE_BLEND_COLOR;
60 r600_pipe_state_add_reg(rstate, R_028414_CB_BLEND_RED, fui(state->color[0]), 0xFFFFFFFF, NULL);
61 r600_pipe_state_add_reg(rstate, R_028418_CB_BLEND_GREEN, fui(state->color[1]), 0xFFFFFFFF, NULL);
62 r600_pipe_state_add_reg(rstate, R_02841C_CB_BLEND_BLUE, fui(state->color[2]), 0xFFFFFFFF, NULL);
63 r600_pipe_state_add_reg(rstate, R_028420_CB_BLEND_ALPHA, fui(state->color[3]), 0xFFFFFFFF, NULL);
64
65 free(rctx->states[R600_PIPE_STATE_BLEND_COLOR]);
66 rctx->states[R600_PIPE_STATE_BLEND_COLOR] = rstate;
67 r600_context_pipe_state_set(&rctx->ctx, rstate);
68 }
69
70 static void *evergreen_create_blend_state(struct pipe_context *ctx,
71 const struct pipe_blend_state *state)
72 {
73 struct r600_pipe_blend *blend = CALLOC_STRUCT(r600_pipe_blend);
74 struct r600_pipe_state *rstate;
75 u32 color_control, target_mask;
76 /* FIXME there is more then 8 framebuffer */
77 unsigned blend_cntl[8];
78
79 if (blend == NULL) {
80 return NULL;
81 }
82 rstate = &blend->rstate;
83
84 rstate->id = R600_PIPE_STATE_BLEND;
85
86 target_mask = 0;
87 color_control = S_028808_MODE(1);
88 if (state->logicop_enable) {
89 color_control |= (state->logicop_func << 16) | (state->logicop_func << 20);
90 } else {
91 color_control |= (0xcc << 16);
92 }
93 /* we pretend 8 buffer are used, CB_SHADER_MASK will disable unused one */
94 if (state->independent_blend_enable) {
95 for (int i = 0; i < 8; i++) {
96 target_mask |= (state->rt[i].colormask << (4 * i));
97 }
98 } else {
99 for (int i = 0; i < 8; i++) {
100 target_mask |= (state->rt[0].colormask << (4 * i));
101 }
102 }
103 blend->cb_target_mask = target_mask;
104 r600_pipe_state_add_reg(rstate, R_028808_CB_COLOR_CONTROL,
105 color_control, 0xFFFFFFFF, NULL);
106 r600_pipe_state_add_reg(rstate, R_028C3C_PA_SC_AA_MASK, 0xFFFFFFFF, 0xFFFFFFFF, NULL);
107
108 for (int i = 0; i < 8; i++) {
109 unsigned eqRGB = state->rt[i].rgb_func;
110 unsigned srcRGB = state->rt[i].rgb_src_factor;
111 unsigned dstRGB = state->rt[i].rgb_dst_factor;
112 unsigned eqA = state->rt[i].alpha_func;
113 unsigned srcA = state->rt[i].alpha_src_factor;
114 unsigned dstA = state->rt[i].alpha_dst_factor;
115
116 blend_cntl[i] = 0;
117 if (!state->rt[i].blend_enable)
118 continue;
119
120 blend_cntl[i] |= S_028780_BLEND_CONTROL_ENABLE(1);
121 blend_cntl[i] |= S_028780_COLOR_COMB_FCN(r600_translate_blend_function(eqRGB));
122 blend_cntl[i] |= S_028780_COLOR_SRCBLEND(r600_translate_blend_factor(srcRGB));
123 blend_cntl[i] |= S_028780_COLOR_DESTBLEND(r600_translate_blend_factor(dstRGB));
124
125 if (srcA != srcRGB || dstA != dstRGB || eqA != eqRGB) {
126 blend_cntl[i] |= S_028780_SEPARATE_ALPHA_BLEND(1);
127 blend_cntl[i] |= S_028780_ALPHA_COMB_FCN(r600_translate_blend_function(eqA));
128 blend_cntl[i] |= S_028780_ALPHA_SRCBLEND(r600_translate_blend_factor(srcA));
129 blend_cntl[i] |= S_028780_ALPHA_DESTBLEND(r600_translate_blend_factor(dstA));
130 }
131 }
132 for (int i = 0; i < 8; i++) {
133 r600_pipe_state_add_reg(rstate, R_028780_CB_BLEND0_CONTROL + i * 4, blend_cntl[i], 0xFFFFFFFF, NULL);
134 }
135
136 return rstate;
137 }
138
139 static void evergreen_bind_blend_state(struct pipe_context *ctx, void *state)
140 {
141 struct r600_pipe_context *rctx = (struct r600_pipe_context *)ctx;
142 struct r600_pipe_blend *blend = (struct r600_pipe_blend *)state;
143 struct r600_pipe_state *rstate;
144
145 if (state == NULL)
146 return;
147 rstate = &blend->rstate;
148 rctx->states[rstate->id] = rstate;
149 rctx->cb_target_mask = blend->cb_target_mask;
150 r600_context_pipe_state_set(&rctx->ctx, rstate);
151 }
152
153 static void *evergreen_create_dsa_state(struct pipe_context *ctx,
154 const struct pipe_depth_stencil_alpha_state *state)
155 {
156 struct r600_pipe_state *rstate = CALLOC_STRUCT(r600_pipe_state);
157 unsigned db_depth_control, alpha_test_control, alpha_ref, db_shader_control;
158 unsigned stencil_ref_mask, stencil_ref_mask_bf, db_render_override, db_render_control;
159
160 if (rstate == NULL) {
161 return NULL;
162 }
163
164 rstate->id = R600_PIPE_STATE_DSA;
165 /* depth TODO some of those db_shader_control field depend on shader adjust mask & add it to shader */
166 /* db_shader_control is 0xFFFFFFBE as Z_EXPORT_ENABLE (bit 0) will be
167 * set by fragment shader if it export Z and KILL_ENABLE (bit 6) will
168 * be set if shader use texkill instruction
169 */
170 db_shader_control = S_02880C_Z_ORDER(V_02880C_EARLY_Z_THEN_LATE_Z);
171 stencil_ref_mask = 0;
172 stencil_ref_mask_bf = 0;
173 db_depth_control = S_028800_Z_ENABLE(state->depth.enabled) |
174 S_028800_Z_WRITE_ENABLE(state->depth.writemask) |
175 S_028800_ZFUNC(state->depth.func);
176
177 /* stencil */
178 if (state->stencil[0].enabled) {
179 db_depth_control |= S_028800_STENCIL_ENABLE(1);
180 db_depth_control |= S_028800_STENCILFUNC(r600_translate_ds_func(state->stencil[0].func));
181 db_depth_control |= S_028800_STENCILFAIL(r600_translate_stencil_op(state->stencil[0].fail_op));
182 db_depth_control |= S_028800_STENCILZPASS(r600_translate_stencil_op(state->stencil[0].zpass_op));
183 db_depth_control |= S_028800_STENCILZFAIL(r600_translate_stencil_op(state->stencil[0].zfail_op));
184
185
186 stencil_ref_mask = S_028430_STENCILMASK(state->stencil[0].valuemask) |
187 S_028430_STENCILWRITEMASK(state->stencil[0].writemask);
188 if (state->stencil[1].enabled) {
189 db_depth_control |= S_028800_BACKFACE_ENABLE(1);
190 db_depth_control |= S_028800_STENCILFUNC_BF(r600_translate_ds_func(state->stencil[1].func));
191 db_depth_control |= S_028800_STENCILFAIL_BF(r600_translate_stencil_op(state->stencil[1].fail_op));
192 db_depth_control |= S_028800_STENCILZPASS_BF(r600_translate_stencil_op(state->stencil[1].zpass_op));
193 db_depth_control |= S_028800_STENCILZFAIL_BF(r600_translate_stencil_op(state->stencil[1].zfail_op));
194 stencil_ref_mask_bf = S_028434_STENCILMASK_BF(state->stencil[1].valuemask) |
195 S_028434_STENCILWRITEMASK_BF(state->stencil[1].writemask);
196 }
197 }
198
199 /* alpha */
200 alpha_test_control = 0;
201 alpha_ref = 0;
202 if (state->alpha.enabled) {
203 alpha_test_control = S_028410_ALPHA_FUNC(state->alpha.func);
204 alpha_test_control |= S_028410_ALPHA_TEST_ENABLE(1);
205 alpha_ref = fui(state->alpha.ref_value);
206 }
207
208 /* misc */
209 db_render_control = 0;
210 db_render_override = S_02800C_FORCE_HIZ_ENABLE(V_02800C_FORCE_DISABLE) |
211 S_02800C_FORCE_HIS_ENABLE0(V_02800C_FORCE_DISABLE) |
212 S_02800C_FORCE_HIS_ENABLE1(V_02800C_FORCE_DISABLE);
213 /* TODO db_render_override depends on query */
214 r600_pipe_state_add_reg(rstate, R_028028_DB_STENCIL_CLEAR, 0x00000000, 0xFFFFFFFF, NULL);
215 r600_pipe_state_add_reg(rstate, R_02802C_DB_DEPTH_CLEAR, 0x3F800000, 0xFFFFFFFF, NULL);
216 r600_pipe_state_add_reg(rstate, R_028410_SX_ALPHA_TEST_CONTROL, alpha_test_control, 0xFFFFFFFF, NULL);
217 r600_pipe_state_add_reg(rstate,
218 R_028430_DB_STENCILREFMASK, stencil_ref_mask,
219 0xFFFFFFFF & C_028430_STENCILREF, NULL);
220 r600_pipe_state_add_reg(rstate,
221 R_028434_DB_STENCILREFMASK_BF, stencil_ref_mask_bf,
222 0xFFFFFFFF & C_028434_STENCILREF_BF, NULL);
223 r600_pipe_state_add_reg(rstate, R_028438_SX_ALPHA_REF, alpha_ref, 0xFFFFFFFF, NULL);
224 r600_pipe_state_add_reg(rstate, R_0286DC_SPI_FOG_CNTL, 0x00000000, 0xFFFFFFFF, NULL);
225 r600_pipe_state_add_reg(rstate, R_028800_DB_DEPTH_CONTROL, db_depth_control, 0xFFFFFFFF, NULL);
226 r600_pipe_state_add_reg(rstate, R_02880C_DB_SHADER_CONTROL, db_shader_control, 0xFFFFFFBE, NULL);
227 r600_pipe_state_add_reg(rstate, R_028000_DB_RENDER_CONTROL, db_render_control, 0xFFFFFFFF, NULL);
228 r600_pipe_state_add_reg(rstate, R_02800C_DB_RENDER_OVERRIDE, db_render_override, 0xFFFFFFFF, NULL);
229 r600_pipe_state_add_reg(rstate, R_028AC0_DB_SRESULTS_COMPARE_STATE0, 0x0, 0xFFFFFFFF, NULL);
230 r600_pipe_state_add_reg(rstate, R_028AC4_DB_SRESULTS_COMPARE_STATE1, 0x0, 0xFFFFFFFF, NULL);
231 r600_pipe_state_add_reg(rstate, R_028AC8_DB_PRELOAD_CONTROL, 0x0, 0xFFFFFFFF, NULL);
232 r600_pipe_state_add_reg(rstate, R_028B70_DB_ALPHA_TO_MASK, 0x0000AA00, 0xFFFFFFFF, NULL);
233
234 return rstate;
235 }
236
237 static void *evergreen_create_rs_state(struct pipe_context *ctx,
238 const struct pipe_rasterizer_state *state)
239 {
240 struct r600_pipe_rasterizer *rs = CALLOC_STRUCT(r600_pipe_rasterizer);
241 struct r600_pipe_state *rstate;
242 unsigned tmp;
243 unsigned prov_vtx = 1, polygon_dual_mode;
244
245 if (rs == NULL) {
246 return NULL;
247 }
248
249 rstate = &rs->rstate;
250 rs->flatshade = state->flatshade;
251 rs->sprite_coord_enable = state->sprite_coord_enable;
252
253 /* offset */
254 rs->offset_units = state->offset_units;
255 rs->offset_scale = state->offset_scale * 12.0f;
256
257 rstate->id = R600_PIPE_STATE_RASTERIZER;
258 if (state->flatshade_first)
259 prov_vtx = 0;
260 tmp = 0x00000001;
261 if (state->sprite_coord_enable) {
262 tmp |= S_0286D4_PNT_SPRITE_ENA(1) |
263 S_0286D4_PNT_SPRITE_OVRD_X(2) |
264 S_0286D4_PNT_SPRITE_OVRD_Y(3) |
265 S_0286D4_PNT_SPRITE_OVRD_Z(0) |
266 S_0286D4_PNT_SPRITE_OVRD_W(1);
267 if (state->sprite_coord_mode != PIPE_SPRITE_COORD_UPPER_LEFT) {
268 tmp |= S_0286D4_PNT_SPRITE_TOP_1(1);
269 }
270 }
271 r600_pipe_state_add_reg(rstate, R_0286D4_SPI_INTERP_CONTROL_0, tmp, 0xFFFFFFFF, NULL);
272
273 polygon_dual_mode = (state->fill_front != PIPE_POLYGON_MODE_FILL ||
274 state->fill_back != PIPE_POLYGON_MODE_FILL);
275 r600_pipe_state_add_reg(rstate, R_028814_PA_SU_SC_MODE_CNTL,
276 S_028814_PROVOKING_VTX_LAST(prov_vtx) |
277 S_028814_CULL_FRONT((state->cull_face & PIPE_FACE_FRONT) ? 1 : 0) |
278 S_028814_CULL_BACK((state->cull_face & PIPE_FACE_BACK) ? 1 : 0) |
279 S_028814_FACE(!state->front_ccw) |
280 S_028814_POLY_OFFSET_FRONT_ENABLE(state->offset_tri) |
281 S_028814_POLY_OFFSET_BACK_ENABLE(state->offset_tri) |
282 S_028814_POLY_OFFSET_PARA_ENABLE(state->offset_tri) |
283 S_028814_POLY_MODE(polygon_dual_mode) |
284 S_028814_POLYMODE_FRONT_PTYPE(r600_translate_fill(state->fill_front)) |
285 S_028814_POLYMODE_BACK_PTYPE(r600_translate_fill(state->fill_back)), 0xFFFFFFFF, NULL);
286 r600_pipe_state_add_reg(rstate, R_02881C_PA_CL_VS_OUT_CNTL,
287 S_02881C_USE_VTX_POINT_SIZE(state->point_size_per_vertex) |
288 S_02881C_VS_OUT_MISC_VEC_ENA(state->point_size_per_vertex), 0xFFFFFFFF, NULL);
289 r600_pipe_state_add_reg(rstate, R_028820_PA_CL_NANINF_CNTL, 0x00000000, 0xFFFFFFFF, NULL);
290 /* point size 12.4 fixed point */
291 tmp = (unsigned)(state->point_size * 8.0);
292 r600_pipe_state_add_reg(rstate, R_028A00_PA_SU_POINT_SIZE, S_028A00_HEIGHT(tmp) | S_028A00_WIDTH(tmp), 0xFFFFFFFF, NULL);
293 r600_pipe_state_add_reg(rstate, R_028A04_PA_SU_POINT_MINMAX, 0x80000000, 0xFFFFFFFF, NULL);
294 r600_pipe_state_add_reg(rstate, R_028A08_PA_SU_LINE_CNTL, 0x00000008, 0xFFFFFFFF, NULL);
295 r600_pipe_state_add_reg(rstate, R_028C00_PA_SC_LINE_CNTL, 0x00000400, 0xFFFFFFFF, NULL);
296 r600_pipe_state_add_reg(rstate, R_028C0C_PA_CL_GB_VERT_CLIP_ADJ, 0x3F800000, 0xFFFFFFFF, NULL);
297 r600_pipe_state_add_reg(rstate, R_028C10_PA_CL_GB_VERT_DISC_ADJ, 0x3F800000, 0xFFFFFFFF, NULL);
298 r600_pipe_state_add_reg(rstate, R_028C14_PA_CL_GB_HORZ_CLIP_ADJ, 0x3F800000, 0xFFFFFFFF, NULL);
299 r600_pipe_state_add_reg(rstate, R_028C18_PA_CL_GB_HORZ_DISC_ADJ, 0x3F800000, 0xFFFFFFFF, NULL);
300 r600_pipe_state_add_reg(rstate, R_028B7C_PA_SU_POLY_OFFSET_CLAMP, 0x0, 0xFFFFFFFF, NULL);
301 r600_pipe_state_add_reg(rstate, R_028C08_PA_SU_VTX_CNTL, 0x00000005, 0xFFFFFFFF, NULL);
302 return rstate;
303 }
304
305 static void evergreen_bind_rs_state(struct pipe_context *ctx, void *state)
306 {
307 struct r600_pipe_rasterizer *rs = (struct r600_pipe_rasterizer *)state;
308 struct r600_pipe_context *rctx = (struct r600_pipe_context *)ctx;
309
310 if (state == NULL)
311 return;
312
313 rctx->flatshade = rs->flatshade;
314 rctx->sprite_coord_enable = rs->sprite_coord_enable;
315 rctx->rasterizer = rs;
316
317 rctx->states[rs->rstate.id] = &rs->rstate;
318 r600_context_pipe_state_set(&rctx->ctx, &rs->rstate);
319 }
320
321 static void evergreen_delete_rs_state(struct pipe_context *ctx, void *state)
322 {
323 struct r600_pipe_context *rctx = (struct r600_pipe_context *)ctx;
324 struct r600_pipe_rasterizer *rs = (struct r600_pipe_rasterizer *)state;
325
326 if (rctx->rasterizer == rs) {
327 rctx->rasterizer = NULL;
328 }
329 if (rctx->states[rs->rstate.id] == &rs->rstate) {
330 rctx->states[rs->rstate.id] = NULL;
331 }
332 free(rs);
333 }
334
335 static void *evergreen_create_sampler_state(struct pipe_context *ctx,
336 const struct pipe_sampler_state *state)
337 {
338 struct r600_pipe_state *rstate = CALLOC_STRUCT(r600_pipe_state);
339 union util_color uc;
340
341 if (rstate == NULL) {
342 return NULL;
343 }
344
345 rstate->id = R600_PIPE_STATE_SAMPLER;
346 util_pack_color(state->border_color, PIPE_FORMAT_B8G8R8A8_UNORM, &uc);
347 r600_pipe_state_add_reg(rstate, R_03C000_SQ_TEX_SAMPLER_WORD0_0,
348 S_03C000_CLAMP_X(r600_tex_wrap(state->wrap_s)) |
349 S_03C000_CLAMP_Y(r600_tex_wrap(state->wrap_t)) |
350 S_03C000_CLAMP_Z(r600_tex_wrap(state->wrap_r)) |
351 S_03C000_XY_MAG_FILTER(r600_tex_filter(state->mag_img_filter)) |
352 S_03C000_XY_MIN_FILTER(r600_tex_filter(state->min_img_filter)) |
353 S_03C000_MIP_FILTER(r600_tex_mipfilter(state->min_mip_filter)) |
354 S_03C000_DEPTH_COMPARE_FUNCTION(r600_tex_compare(state->compare_func)) |
355 S_03C000_BORDER_COLOR_TYPE(uc.ui ? V_03C000_SQ_TEX_BORDER_COLOR_REGISTER : 0), 0xFFFFFFFF, NULL);
356 /* FIXME LOD it depends on texture base level ... */
357 r600_pipe_state_add_reg(rstate, R_03C004_SQ_TEX_SAMPLER_WORD1_0,
358 S_03C004_MIN_LOD(S_FIXED(CLAMP(state->min_lod, 0, 15), 6)) |
359 S_03C004_MAX_LOD(S_FIXED(CLAMP(state->max_lod, 0, 15), 6)),
360 0xFFFFFFFF, NULL);
361 r600_pipe_state_add_reg(rstate, R_03C008_SQ_TEX_SAMPLER_WORD2_0,
362 S_03C008_LOD_BIAS(S_FIXED(CLAMP(state->lod_bias, -16, 16), 6)) |
363 S_03C008_TYPE(1),
364 0xFFFFFFFF, NULL);
365
366 if (uc.ui) {
367 r600_pipe_state_add_reg(rstate, R_00A404_TD_PS_SAMPLER0_BORDER_RED, fui(state->border_color[0]), 0xFFFFFFFF, NULL);
368 r600_pipe_state_add_reg(rstate, R_00A408_TD_PS_SAMPLER0_BORDER_GREEN, fui(state->border_color[1]), 0xFFFFFFFF, NULL);
369 r600_pipe_state_add_reg(rstate, R_00A40C_TD_PS_SAMPLER0_BORDER_BLUE, fui(state->border_color[2]), 0xFFFFFFFF, NULL);
370 r600_pipe_state_add_reg(rstate, R_00A410_TD_PS_SAMPLER0_BORDER_ALPHA, fui(state->border_color[3]), 0xFFFFFFFF, NULL);
371 }
372 return rstate;
373 }
374
375 static void *evergreen_create_vertex_elements(struct pipe_context *ctx,
376 unsigned count,
377 const struct pipe_vertex_element *elements)
378 {
379 struct r600_vertex_element *v = CALLOC_STRUCT(r600_vertex_element);
380
381 assert(count < 32);
382 v->count = count;
383 v->refcount = 1;
384 memcpy(v->elements, elements, count * sizeof(struct pipe_vertex_element));
385 return v;
386 }
387
388 static void evergreen_sampler_view_destroy(struct pipe_context *ctx,
389 struct pipe_sampler_view *state)
390 {
391 struct r600_pipe_sampler_view *resource = (struct r600_pipe_sampler_view *)state;
392
393 pipe_resource_reference(&state->texture, NULL);
394 FREE(resource);
395 }
396
397 static struct pipe_sampler_view *evergreen_create_sampler_view(struct pipe_context *ctx,
398 struct pipe_resource *texture,
399 const struct pipe_sampler_view *state)
400 {
401 struct r600_pipe_sampler_view *resource = CALLOC_STRUCT(r600_pipe_sampler_view);
402 struct r600_pipe_state *rstate;
403 const struct util_format_description *desc;
404 struct r600_resource_texture *tmp;
405 struct r600_resource *rbuffer;
406 unsigned format;
407 uint32_t word4 = 0, yuv_format = 0, pitch = 0;
408 unsigned char swizzle[4];
409 struct radeon_ws_bo *bo[2];
410
411 if (resource == NULL)
412 return NULL;
413 rstate = &resource->state;
414
415 /* initialize base object */
416 resource->base = *state;
417 resource->base.texture = NULL;
418 pipe_reference(NULL, &texture->reference);
419 resource->base.texture = texture;
420 resource->base.reference.count = 1;
421 resource->base.context = ctx;
422
423 swizzle[0] = state->swizzle_r;
424 swizzle[1] = state->swizzle_g;
425 swizzle[2] = state->swizzle_b;
426 swizzle[3] = state->swizzle_a;
427 format = r600_translate_texformat(texture->format,
428 swizzle,
429 &word4, &yuv_format);
430 if (format == ~0) {
431 format = 0;
432 }
433 desc = util_format_description(texture->format);
434 if (desc == NULL) {
435 R600_ERR("unknow format %d\n", texture->format);
436 }
437 tmp = (struct r600_resource_texture*)texture;
438 rbuffer = &tmp->resource;
439 bo[0] = rbuffer->bo;
440 bo[1] = rbuffer->bo;
441 /* FIXME depth texture decompression */
442 if (tmp->depth) {
443 r600_texture_depth_flush(ctx, texture);
444 tmp = (struct r600_resource_texture*)texture;
445 rbuffer = &tmp->flushed_depth_texture->resource;
446 bo[0] = rbuffer->bo;
447 bo[1] = rbuffer->bo;
448 }
449 pitch = align(tmp->pitch[0] / tmp->bpt, 8);
450
451 /* FIXME properly handle first level != 0 */
452 r600_pipe_state_add_reg(rstate, R_030000_RESOURCE0_WORD0,
453 S_030000_DIM(r600_tex_dim(texture->target)) |
454 S_030000_PITCH((pitch / 8) - 1) |
455 S_030000_TEX_WIDTH(texture->width0 - 1), 0xFFFFFFFF, NULL);
456 r600_pipe_state_add_reg(rstate, R_030004_RESOURCE0_WORD1,
457 S_030004_TEX_HEIGHT(texture->height0 - 1) |
458 S_030004_TEX_DEPTH(texture->depth0 - 1),
459 0xFFFFFFFF, NULL);
460 r600_pipe_state_add_reg(rstate, R_030008_RESOURCE0_WORD2,
461 tmp->offset[0] >> 8, 0xFFFFFFFF, bo[0]);
462 r600_pipe_state_add_reg(rstate, R_03000C_RESOURCE0_WORD3,
463 tmp->offset[1] >> 8, 0xFFFFFFFF, bo[1]);
464 r600_pipe_state_add_reg(rstate, R_030010_RESOURCE0_WORD4,
465 word4 | S_030010_NUM_FORMAT_ALL(V_030010_SQ_NUM_FORMAT_NORM) |
466 S_030010_SRF_MODE_ALL(V_030010_SFR_MODE_NO_ZERO) |
467 S_030010_REQUEST_SIZE(1) |
468 S_030010_BASE_LEVEL(state->first_level), 0xFFFFFFFF, NULL);
469 r600_pipe_state_add_reg(rstate, R_030014_RESOURCE0_WORD5,
470 S_030014_LAST_LEVEL(state->last_level) |
471 S_030014_BASE_ARRAY(0) |
472 S_030014_LAST_ARRAY(0), 0xffffffff, NULL);
473 r600_pipe_state_add_reg(rstate, R_030018_RESOURCE0_WORD6, 0x0, 0xFFFFFFFF, NULL);
474 r600_pipe_state_add_reg(rstate, R_03001C_RESOURCE0_WORD7,
475 S_03001C_DATA_FORMAT(format) |
476 S_03001C_TYPE(V_03001C_SQ_TEX_VTX_VALID_TEXTURE), 0xFFFFFFFF, NULL);
477
478 return &resource->base;
479 }
480
481 static void evergreen_set_vs_sampler_view(struct pipe_context *ctx, unsigned count,
482 struct pipe_sampler_view **views)
483 {
484 /* TODO */
485 assert(1);
486 }
487
488 static void evergreen_set_ps_sampler_view(struct pipe_context *ctx, unsigned count,
489 struct pipe_sampler_view **views)
490 {
491 struct r600_pipe_context *rctx = (struct r600_pipe_context *)ctx;
492 struct r600_pipe_sampler_view **resource = (struct r600_pipe_sampler_view **)views;
493
494 for (int i = 0; i < count; i++) {
495 if (resource[i]) {
496 evergreen_context_pipe_state_set_ps_resource(&rctx->ctx, &resource[i]->state, i);
497 }
498 }
499 }
500
501 static void evergreen_bind_state(struct pipe_context *ctx, void *state)
502 {
503 struct r600_pipe_context *rctx = (struct r600_pipe_context *)ctx;
504 struct r600_pipe_state *rstate = (struct r600_pipe_state *)state;
505
506 if (state == NULL)
507 return;
508 rctx->states[rstate->id] = rstate;
509 r600_context_pipe_state_set(&rctx->ctx, rstate);
510 }
511
512 static void evergreen_bind_ps_sampler(struct pipe_context *ctx, unsigned count, void **states)
513 {
514 struct r600_pipe_context *rctx = (struct r600_pipe_context *)ctx;
515 struct r600_pipe_state **rstates = (struct r600_pipe_state **)states;
516
517 for (int i = 0; i < count; i++) {
518 evergreen_context_pipe_state_set_ps_sampler(&rctx->ctx, rstates[i], i);
519 }
520 }
521
522 static void evergreen_bind_vs_sampler(struct pipe_context *ctx, unsigned count, void **states)
523 {
524 struct r600_pipe_context *rctx = (struct r600_pipe_context *)ctx;
525 struct r600_pipe_state **rstates = (struct r600_pipe_state **)states;
526
527 /* TODO implement */
528 for (int i = 0; i < count; i++) {
529 evergreen_context_pipe_state_set_vs_sampler(&rctx->ctx, rstates[i], i);
530 }
531 }
532
533 static void evergreen_delete_state(struct pipe_context *ctx, void *state)
534 {
535 struct r600_pipe_context *rctx = (struct r600_pipe_context *)ctx;
536 struct r600_pipe_state *rstate = (struct r600_pipe_state *)state;
537
538 if (rctx->states[rstate->id] == rstate) {
539 rctx->states[rstate->id] = NULL;
540 }
541 for (int i = 0; i < rstate->nregs; i++) {
542 radeon_ws_bo_reference(rctx->radeon, &rstate->regs[i].bo, NULL);
543 }
544 free(rstate);
545 }
546
547 static void evergreen_delete_vertex_element(struct pipe_context *ctx, void *state)
548 {
549 struct r600_vertex_element *v = (struct r600_vertex_element*)state;
550
551 if (v == NULL)
552 return;
553 if (--v->refcount)
554 return;
555 free(v);
556 }
557
558 static void evergreen_set_clip_state(struct pipe_context *ctx,
559 const struct pipe_clip_state *state)
560 {
561 struct r600_pipe_context *rctx = (struct r600_pipe_context *)ctx;
562 struct r600_pipe_state *rstate = CALLOC_STRUCT(r600_pipe_state);
563
564 if (rstate == NULL)
565 return;
566
567 rctx->clip = *state;
568 rstate->id = R600_PIPE_STATE_CLIP;
569 for (int i = 0; i < state->nr; i++) {
570 r600_pipe_state_add_reg(rstate,
571 R_0285BC_PA_CL_UCP0_X + i * 4,
572 fui(state->ucp[i][0]), 0xFFFFFFFF, NULL);
573 r600_pipe_state_add_reg(rstate,
574 R_0285C0_PA_CL_UCP0_Y + i * 4,
575 fui(state->ucp[i][1]) , 0xFFFFFFFF, NULL);
576 r600_pipe_state_add_reg(rstate,
577 R_0285C4_PA_CL_UCP0_Z + i * 4,
578 fui(state->ucp[i][2]), 0xFFFFFFFF, NULL);
579 r600_pipe_state_add_reg(rstate,
580 R_0285C8_PA_CL_UCP0_W + i * 4,
581 fui(state->ucp[i][3]), 0xFFFFFFFF, NULL);
582 }
583 r600_pipe_state_add_reg(rstate, R_028810_PA_CL_CLIP_CNTL,
584 S_028810_PS_UCP_MODE(3) | ((1 << state->nr) - 1) |
585 S_028810_ZCLIP_NEAR_DISABLE(state->depth_clamp) |
586 S_028810_ZCLIP_FAR_DISABLE(state->depth_clamp), 0xFFFFFFFF, NULL);
587
588 free(rctx->states[R600_PIPE_STATE_CLIP]);
589 rctx->states[R600_PIPE_STATE_CLIP] = rstate;
590 r600_context_pipe_state_set(&rctx->ctx, rstate);
591 }
592
593 static void evergreen_bind_vertex_elements(struct pipe_context *ctx, void *state)
594 {
595 struct r600_pipe_context *rctx = (struct r600_pipe_context *)ctx;
596 struct r600_vertex_element *v = (struct r600_vertex_element*)state;
597
598 evergreen_delete_vertex_element(ctx, rctx->vertex_elements);
599 rctx->vertex_elements = v;
600 if (v) {
601 v->refcount++;
602 // rctx->vs_rebuild = TRUE;
603 }
604 }
605
606 static void evergreen_set_polygon_stipple(struct pipe_context *ctx,
607 const struct pipe_poly_stipple *state)
608 {
609 }
610
611 static void evergreen_set_sample_mask(struct pipe_context *pipe, unsigned sample_mask)
612 {
613 }
614
615 static void evergreen_set_scissor_state(struct pipe_context *ctx,
616 const struct pipe_scissor_state *state)
617 {
618 struct r600_pipe_context *rctx = (struct r600_pipe_context *)ctx;
619 struct r600_pipe_state *rstate = CALLOC_STRUCT(r600_pipe_state);
620 u32 tl, br;
621
622 if (rstate == NULL)
623 return;
624
625 rstate->id = R600_PIPE_STATE_SCISSOR;
626 tl = S_028240_TL_X(state->minx) | S_028240_TL_Y(state->miny);
627 br = S_028244_BR_X(state->maxx) | S_028244_BR_Y(state->maxy);
628 r600_pipe_state_add_reg(rstate,
629 R_028030_PA_SC_SCREEN_SCISSOR_TL, tl,
630 0xFFFFFFFF, NULL);
631 r600_pipe_state_add_reg(rstate,
632 R_028034_PA_SC_SCREEN_SCISSOR_BR, br,
633 0xFFFFFFFF, NULL);
634 r600_pipe_state_add_reg(rstate,
635 R_028204_PA_SC_WINDOW_SCISSOR_TL, tl,
636 0xFFFFFFFF, NULL);
637 r600_pipe_state_add_reg(rstate,
638 R_028208_PA_SC_WINDOW_SCISSOR_BR, br,
639 0xFFFFFFFF, NULL);
640 r600_pipe_state_add_reg(rstate,
641 R_028210_PA_SC_CLIPRECT_0_TL, tl,
642 0xFFFFFFFF, NULL);
643 r600_pipe_state_add_reg(rstate,
644 R_028214_PA_SC_CLIPRECT_0_BR, br,
645 0xFFFFFFFF, NULL);
646 r600_pipe_state_add_reg(rstate,
647 R_028218_PA_SC_CLIPRECT_1_TL, tl,
648 0xFFFFFFFF, NULL);
649 r600_pipe_state_add_reg(rstate,
650 R_02821C_PA_SC_CLIPRECT_1_BR, br,
651 0xFFFFFFFF, NULL);
652 r600_pipe_state_add_reg(rstate,
653 R_028220_PA_SC_CLIPRECT_2_TL, tl,
654 0xFFFFFFFF, NULL);
655 r600_pipe_state_add_reg(rstate,
656 R_028224_PA_SC_CLIPRECT_2_BR, br,
657 0xFFFFFFFF, NULL);
658 r600_pipe_state_add_reg(rstate,
659 R_028228_PA_SC_CLIPRECT_3_TL, tl,
660 0xFFFFFFFF, NULL);
661 r600_pipe_state_add_reg(rstate,
662 R_02822C_PA_SC_CLIPRECT_3_BR, br,
663 0xFFFFFFFF, NULL);
664 r600_pipe_state_add_reg(rstate,
665 R_028200_PA_SC_WINDOW_OFFSET, 0x00000000,
666 0xFFFFFFFF, NULL);
667 r600_pipe_state_add_reg(rstate,
668 R_02820C_PA_SC_CLIPRECT_RULE, 0x0000FFFF,
669 0xFFFFFFFF, NULL);
670 r600_pipe_state_add_reg(rstate,
671 R_028230_PA_SC_EDGERULE, 0xAAAAAAAA,
672 0xFFFFFFFF, NULL);
673
674 free(rctx->states[R600_PIPE_STATE_SCISSOR]);
675 rctx->states[R600_PIPE_STATE_SCISSOR] = rstate;
676 r600_context_pipe_state_set(&rctx->ctx, rstate);
677 }
678
679 static void evergreen_set_stencil_ref(struct pipe_context *ctx,
680 const struct pipe_stencil_ref *state)
681 {
682 struct r600_pipe_context *rctx = (struct r600_pipe_context *)ctx;
683 struct r600_pipe_state *rstate = CALLOC_STRUCT(r600_pipe_state);
684 u32 tmp;
685
686 if (rstate == NULL)
687 return;
688
689 rctx->stencil_ref = *state;
690 rstate->id = R600_PIPE_STATE_STENCIL_REF;
691 tmp = S_028430_STENCILREF(state->ref_value[0]);
692 r600_pipe_state_add_reg(rstate,
693 R_028430_DB_STENCILREFMASK, tmp,
694 ~C_028430_STENCILREF, NULL);
695 tmp = S_028434_STENCILREF_BF(state->ref_value[1]);
696 r600_pipe_state_add_reg(rstate,
697 R_028434_DB_STENCILREFMASK_BF, tmp,
698 ~C_028434_STENCILREF_BF, NULL);
699
700 free(rctx->states[R600_PIPE_STATE_STENCIL_REF]);
701 rctx->states[R600_PIPE_STATE_STENCIL_REF] = rstate;
702 r600_context_pipe_state_set(&rctx->ctx, rstate);
703 }
704
705 static void evergreen_set_viewport_state(struct pipe_context *ctx,
706 const struct pipe_viewport_state *state)
707 {
708 struct r600_pipe_context *rctx = (struct r600_pipe_context *)ctx;
709 struct r600_pipe_state *rstate = CALLOC_STRUCT(r600_pipe_state);
710
711 if (rstate == NULL)
712 return;
713
714 rctx->viewport = *state;
715 rstate->id = R600_PIPE_STATE_VIEWPORT;
716 r600_pipe_state_add_reg(rstate, R_0282D0_PA_SC_VPORT_ZMIN_0, 0x00000000, 0xFFFFFFFF, NULL);
717 r600_pipe_state_add_reg(rstate, R_0282D4_PA_SC_VPORT_ZMAX_0, 0x3F800000, 0xFFFFFFFF, NULL);
718 r600_pipe_state_add_reg(rstate, R_02843C_PA_CL_VPORT_XSCALE_0, fui(state->scale[0]), 0xFFFFFFFF, NULL);
719 r600_pipe_state_add_reg(rstate, R_028444_PA_CL_VPORT_YSCALE_0, fui(state->scale[1]), 0xFFFFFFFF, NULL);
720 r600_pipe_state_add_reg(rstate, R_02844C_PA_CL_VPORT_ZSCALE_0, fui(state->scale[2]), 0xFFFFFFFF, NULL);
721 r600_pipe_state_add_reg(rstate, R_028440_PA_CL_VPORT_XOFFSET_0, fui(state->translate[0]), 0xFFFFFFFF, NULL);
722 r600_pipe_state_add_reg(rstate, R_028448_PA_CL_VPORT_YOFFSET_0, fui(state->translate[1]), 0xFFFFFFFF, NULL);
723 r600_pipe_state_add_reg(rstate, R_028450_PA_CL_VPORT_ZOFFSET_0, fui(state->translate[2]), 0xFFFFFFFF, NULL);
724 r600_pipe_state_add_reg(rstate, R_028818_PA_CL_VTE_CNTL, 0x0000043F, 0xFFFFFFFF, NULL);
725
726 free(rctx->states[R600_PIPE_STATE_VIEWPORT]);
727 rctx->states[R600_PIPE_STATE_VIEWPORT] = rstate;
728 r600_context_pipe_state_set(&rctx->ctx, rstate);
729 }
730
731 static void evergreen_cb(struct r600_pipe_context *rctx, struct r600_pipe_state *rstate,
732 const struct pipe_framebuffer_state *state, int cb)
733 {
734 struct r600_resource_texture *rtex;
735 struct r600_resource *rbuffer;
736 unsigned level = state->cbufs[cb]->level;
737 unsigned pitch, slice;
738 unsigned color_info;
739 unsigned format, swap, ntype;
740 const struct util_format_description *desc;
741 struct radeon_ws_bo *bo[3];
742
743 rtex = (struct r600_resource_texture*)state->cbufs[cb]->texture;
744 rbuffer = &rtex->resource;
745 bo[0] = rbuffer->bo;
746 bo[1] = rbuffer->bo;
747 bo[2] = rbuffer->bo;
748
749 pitch = (rtex->pitch[level] / rtex->bpt) / 8 - 1;
750 slice = (rtex->pitch[level] / rtex->bpt) * state->cbufs[cb]->height / 64 - 1;
751 ntype = 0;
752 desc = util_format_description(rtex->resource.base.b.format);
753 if (desc->colorspace == UTIL_FORMAT_COLORSPACE_SRGB)
754 ntype = V_028C70_NUMBER_SRGB;
755
756 format = r600_translate_colorformat(rtex->resource.base.b.format);
757 swap = r600_translate_colorswap(rtex->resource.base.b.format);
758 color_info = S_028C70_FORMAT(format) |
759 S_028C70_COMP_SWAP(swap) |
760 S_028C70_BLEND_CLAMP(1) |
761 S_028C70_NUMBER_TYPE(ntype);
762 if (desc->colorspace != UTIL_FORMAT_COLORSPACE_ZS)
763 color_info |= S_028C70_SOURCE_FORMAT(1);
764
765 /* FIXME handle enabling of CB beyond BASE8 which has different offset */
766 r600_pipe_state_add_reg(rstate,
767 R_028C60_CB_COLOR0_BASE + cb * 0x3C,
768 state->cbufs[cb]->offset >> 8, 0xFFFFFFFF, bo[0]);
769 r600_pipe_state_add_reg(rstate,
770 R_028C78_CB_COLOR0_DIM + cb * 0x3C,
771 0x0, 0xFFFFFFFF, NULL);
772 r600_pipe_state_add_reg(rstate,
773 R_028C70_CB_COLOR0_INFO + cb * 0x3C,
774 color_info, 0xFFFFFFFF, bo[0]);
775 r600_pipe_state_add_reg(rstate,
776 R_028C64_CB_COLOR0_PITCH + cb * 0x3C,
777 S_028C64_PITCH_TILE_MAX(pitch),
778 0xFFFFFFFF, NULL);
779 r600_pipe_state_add_reg(rstate,
780 R_028C68_CB_COLOR0_SLICE + cb * 0x3C,
781 S_028C68_SLICE_TILE_MAX(slice),
782 0xFFFFFFFF, NULL);
783 r600_pipe_state_add_reg(rstate,
784 R_028C6C_CB_COLOR0_VIEW + cb * 0x3C,
785 0x00000000, 0xFFFFFFFF, NULL);
786 r600_pipe_state_add_reg(rstate,
787 R_028C74_CB_COLOR0_ATTRIB + cb * 0x3C,
788 S_028C74_NON_DISP_TILING_ORDER(1),
789 0xFFFFFFFF, NULL);
790 }
791
792 static void evergreen_db(struct r600_pipe_context *rctx, struct r600_pipe_state *rstate,
793 const struct pipe_framebuffer_state *state)
794 {
795 struct r600_resource_texture *rtex;
796 struct r600_resource *rbuffer;
797 unsigned level;
798 unsigned pitch, slice, format;
799
800 if (state->zsbuf == NULL)
801 return;
802
803 rtex = (struct r600_resource_texture*)state->zsbuf->texture;
804 rtex->tiled = 1;
805 rtex->array_mode = 2;
806 rtex->tile_type = 1;
807 rtex->depth = 1;
808 rbuffer = &rtex->resource;
809
810 level = state->zsbuf->level;
811 pitch = (rtex->pitch[level] / rtex->bpt) / 8 - 1;
812 slice = (rtex->pitch[level] / rtex->bpt) * state->zsbuf->height / 64 - 1;
813 format = r600_translate_dbformat(state->zsbuf->texture->format);
814
815 r600_pipe_state_add_reg(rstate, R_028048_DB_Z_READ_BASE,
816 state->zsbuf->offset >> 8, 0xFFFFFFFF, rbuffer->bo);
817 r600_pipe_state_add_reg(rstate, R_028050_DB_Z_WRITE_BASE,
818 state->zsbuf->offset >> 8, 0xFFFFFFFF, rbuffer->bo);
819 // r600_pipe_state_add_reg(rstate, R_028014_DB_HTILE_DATA_BASE, state->zsbuf->offset >> 8, 0xFFFFFFFF, rbuffer->bo);
820 r600_pipe_state_add_reg(rstate, R_028008_DB_DEPTH_VIEW, 0x00000000, 0xFFFFFFFF, NULL);
821 r600_pipe_state_add_reg(rstate, R_028040_DB_Z_INFO,
822 S_028040_ARRAY_MODE(rtex->array_mode) | S_028040_FORMAT(format),
823 0xFFFFFFFF, rbuffer->bo);
824 r600_pipe_state_add_reg(rstate, R_028058_DB_DEPTH_SIZE,
825 S_028058_PITCH_TILE_MAX(pitch),
826 0xFFFFFFFF, NULL);
827 r600_pipe_state_add_reg(rstate, R_02805C_DB_DEPTH_SLICE,
828 S_02805C_SLICE_TILE_MAX(slice),
829 0xFFFFFFFF, NULL);
830 }
831
832 static void evergreen_set_framebuffer_state(struct pipe_context *ctx,
833 const struct pipe_framebuffer_state *state)
834 {
835 struct r600_pipe_context *rctx = (struct r600_pipe_context *)ctx;
836 struct r600_pipe_state *rstate = CALLOC_STRUCT(r600_pipe_state);
837 u32 shader_mask, tl, br, target_mask;
838
839 if (rstate == NULL)
840 return;
841
842 /* unreference old buffer and reference new one */
843 rstate->id = R600_PIPE_STATE_FRAMEBUFFER;
844 for (int i = 0; i < rctx->framebuffer.nr_cbufs; i++) {
845 pipe_surface_reference(&rctx->framebuffer.cbufs[i], NULL);
846 }
847 for (int i = 0; i < state->nr_cbufs; i++) {
848 pipe_surface_reference(&rctx->framebuffer.cbufs[i], state->cbufs[i]);
849 }
850 pipe_surface_reference(&rctx->framebuffer.zsbuf, state->zsbuf);
851 rctx->framebuffer = *state;
852 rctx->pframebuffer = &rctx->framebuffer;
853
854 /* build states */
855 for (int i = 0; i < state->nr_cbufs; i++) {
856 evergreen_cb(rctx, rstate, state, i);
857 }
858 if (state->zsbuf) {
859 evergreen_db(rctx, rstate, state);
860 }
861
862 target_mask = 0x00000000;
863 target_mask = 0xFFFFFFFF;
864 shader_mask = 0;
865 for (int i = 0; i < state->nr_cbufs; i++) {
866 target_mask ^= 0xf << (i * 4);
867 shader_mask |= 0xf << (i * 4);
868 }
869 tl = S_028240_TL_X(0) | S_028240_TL_Y(0);
870 br = S_028244_BR_X(state->width) | S_028244_BR_Y(state->height);
871
872 r600_pipe_state_add_reg(rstate,
873 R_028240_PA_SC_GENERIC_SCISSOR_TL, tl,
874 0xFFFFFFFF, NULL);
875 r600_pipe_state_add_reg(rstate,
876 R_028244_PA_SC_GENERIC_SCISSOR_BR, br,
877 0xFFFFFFFF, NULL);
878 r600_pipe_state_add_reg(rstate,
879 R_028250_PA_SC_VPORT_SCISSOR_0_TL, tl,
880 0xFFFFFFFF, NULL);
881 r600_pipe_state_add_reg(rstate,
882 R_028254_PA_SC_VPORT_SCISSOR_0_BR, br,
883 0xFFFFFFFF, NULL);
884
885 r600_pipe_state_add_reg(rstate, R_028238_CB_TARGET_MASK,
886 0x00000000, target_mask, NULL);
887 r600_pipe_state_add_reg(rstate, R_02823C_CB_SHADER_MASK,
888 shader_mask, 0xFFFFFFFF, NULL);
889 r600_pipe_state_add_reg(rstate, R_028C04_PA_SC_AA_CONFIG,
890 0x00000000, 0xFFFFFFFF, NULL);
891 r600_pipe_state_add_reg(rstate, R_028C1C_PA_SC_AA_SAMPLE_LOCS_MCTX,
892 0x00000000, 0xFFFFFFFF, NULL);
893
894 free(rctx->states[R600_PIPE_STATE_FRAMEBUFFER]);
895 rctx->states[R600_PIPE_STATE_FRAMEBUFFER] = rstate;
896 r600_context_pipe_state_set(&rctx->ctx, rstate);
897 }
898
899 static void evergreen_set_index_buffer(struct pipe_context *ctx,
900 const struct pipe_index_buffer *ib)
901 {
902 struct r600_pipe_context *rctx = (struct r600_pipe_context *)ctx;
903
904 if (ib) {
905 pipe_resource_reference(&rctx->index_buffer.buffer, ib->buffer);
906 memcpy(&rctx->index_buffer, ib, sizeof(rctx->index_buffer));
907 } else {
908 pipe_resource_reference(&rctx->index_buffer.buffer, NULL);
909 memset(&rctx->index_buffer, 0, sizeof(rctx->index_buffer));
910 }
911
912 /* TODO make this more like a state */
913 }
914
915 static void evergreen_set_vertex_buffers(struct pipe_context *ctx, unsigned count,
916 const struct pipe_vertex_buffer *buffers)
917 {
918 struct r600_pipe_context *rctx = (struct r600_pipe_context *)ctx;
919
920 for (int i = 0; i < rctx->nvertex_buffer; i++) {
921 pipe_resource_reference(&rctx->vertex_buffer[i].buffer, NULL);
922 }
923 memcpy(rctx->vertex_buffer, buffers, sizeof(struct pipe_vertex_buffer) * count);
924 for (int i = 0; i < count; i++) {
925 rctx->vertex_buffer[i].buffer = NULL;
926 if (r600_buffer_is_user_buffer(buffers[i].buffer))
927 rctx->any_user_vbs = TRUE;
928 pipe_resource_reference(&rctx->vertex_buffer[i].buffer, buffers[i].buffer);
929 }
930 rctx->nvertex_buffer = count;
931 }
932
933 static void evergreen_set_constant_buffer(struct pipe_context *ctx, uint shader, uint index,
934 struct pipe_resource *buffer)
935 {
936 struct r600_pipe_context *rctx = (struct r600_pipe_context *)ctx;
937 struct r600_resource *rbuffer = (struct r600_resource*)buffer;
938
939 switch (shader) {
940 case PIPE_SHADER_VERTEX:
941 rctx->vs_const_buffer.nregs = 0;
942 r600_pipe_state_add_reg(&rctx->vs_const_buffer,
943 R_028180_ALU_CONST_BUFFER_SIZE_VS_0,
944 ALIGN_DIVUP(buffer->width0 >> 4, 16),
945 0xFFFFFFFF, NULL);
946 r600_pipe_state_add_reg(&rctx->vs_const_buffer,
947 R_028980_ALU_CONST_CACHE_VS_0,
948 0, 0xFFFFFFFF, rbuffer->bo);
949 r600_context_pipe_state_set(&rctx->ctx, &rctx->vs_const_buffer);
950 break;
951 case PIPE_SHADER_FRAGMENT:
952 rctx->ps_const_buffer.nregs = 0;
953 r600_pipe_state_add_reg(&rctx->ps_const_buffer,
954 R_028140_ALU_CONST_BUFFER_SIZE_PS_0,
955 ALIGN_DIVUP(buffer->width0 >> 4, 16),
956 0xFFFFFFFF, NULL);
957 r600_pipe_state_add_reg(&rctx->ps_const_buffer,
958 R_028940_ALU_CONST_CACHE_PS_0,
959 0, 0xFFFFFFFF, rbuffer->bo);
960 r600_context_pipe_state_set(&rctx->ctx, &rctx->ps_const_buffer);
961 break;
962 default:
963 R600_ERR("unsupported %d\n", shader);
964 return;
965 }
966 }
967
968 static void *evergreen_create_shader_state(struct pipe_context *ctx,
969 const struct pipe_shader_state *state)
970 {
971 struct r600_pipe_shader *shader = CALLOC_STRUCT(r600_pipe_shader);
972 int r;
973
974 shader->shader.use_mem_constant = TRUE;
975 r = r600_pipe_shader_create(ctx, shader, state->tokens);
976 if (r) {
977 return NULL;
978 }
979 return shader;
980 }
981
982 static void evergreen_bind_ps_shader(struct pipe_context *ctx, void *state)
983 {
984 struct r600_pipe_context *rctx = (struct r600_pipe_context *)ctx;
985
986 /* TODO delete old shader */
987 rctx->ps_shader = (struct r600_pipe_shader *)state;
988 }
989
990 static void evergreen_bind_vs_shader(struct pipe_context *ctx, void *state)
991 {
992 struct r600_pipe_context *rctx = (struct r600_pipe_context *)ctx;
993
994 /* TODO delete old shader */
995 rctx->vs_shader = (struct r600_pipe_shader *)state;
996 }
997
998 static void evergreen_delete_ps_shader(struct pipe_context *ctx, void *state)
999 {
1000 struct r600_pipe_context *rctx = (struct r600_pipe_context *)ctx;
1001 struct r600_pipe_shader *shader = (struct r600_pipe_shader *)state;
1002
1003 if (rctx->ps_shader == shader) {
1004 rctx->ps_shader = NULL;
1005 }
1006 /* TODO proper delete */
1007 free(shader);
1008 }
1009
1010 static void evergreen_delete_vs_shader(struct pipe_context *ctx, void *state)
1011 {
1012 struct r600_pipe_context *rctx = (struct r600_pipe_context *)ctx;
1013 struct r600_pipe_shader *shader = (struct r600_pipe_shader *)state;
1014
1015 if (rctx->vs_shader == shader) {
1016 rctx->vs_shader = NULL;
1017 }
1018 /* TODO proper delete */
1019 free(shader);
1020 }
1021
1022 void evergreen_init_state_functions(struct r600_pipe_context *rctx)
1023 {
1024 rctx->context.create_blend_state = evergreen_create_blend_state;
1025 rctx->context.create_depth_stencil_alpha_state = evergreen_create_dsa_state;
1026 rctx->context.create_fs_state = evergreen_create_shader_state;
1027 rctx->context.create_rasterizer_state = evergreen_create_rs_state;
1028 rctx->context.create_sampler_state = evergreen_create_sampler_state;
1029 rctx->context.create_sampler_view = evergreen_create_sampler_view;
1030 rctx->context.create_vertex_elements_state = evergreen_create_vertex_elements;
1031 rctx->context.create_vs_state = evergreen_create_shader_state;
1032 rctx->context.bind_blend_state = evergreen_bind_blend_state;
1033 rctx->context.bind_depth_stencil_alpha_state = evergreen_bind_state;
1034 rctx->context.bind_fragment_sampler_states = evergreen_bind_ps_sampler;
1035 rctx->context.bind_fs_state = evergreen_bind_ps_shader;
1036 rctx->context.bind_rasterizer_state = evergreen_bind_rs_state;
1037 rctx->context.bind_vertex_elements_state = evergreen_bind_vertex_elements;
1038 rctx->context.bind_vertex_sampler_states = evergreen_bind_vs_sampler;
1039 rctx->context.bind_vs_state = evergreen_bind_vs_shader;
1040 rctx->context.delete_blend_state = evergreen_delete_state;
1041 rctx->context.delete_depth_stencil_alpha_state = evergreen_delete_state;
1042 rctx->context.delete_fs_state = evergreen_delete_ps_shader;
1043 rctx->context.delete_rasterizer_state = evergreen_delete_rs_state;
1044 rctx->context.delete_sampler_state = evergreen_delete_state;
1045 rctx->context.delete_vertex_elements_state = evergreen_delete_vertex_element;
1046 rctx->context.delete_vs_state = evergreen_delete_vs_shader;
1047 rctx->context.set_blend_color = evergreen_set_blend_color;
1048 rctx->context.set_clip_state = evergreen_set_clip_state;
1049 rctx->context.set_constant_buffer = evergreen_set_constant_buffer;
1050 rctx->context.set_fragment_sampler_views = evergreen_set_ps_sampler_view;
1051 rctx->context.set_framebuffer_state = evergreen_set_framebuffer_state;
1052 rctx->context.set_polygon_stipple = evergreen_set_polygon_stipple;
1053 rctx->context.set_sample_mask = evergreen_set_sample_mask;
1054 rctx->context.set_scissor_state = evergreen_set_scissor_state;
1055 rctx->context.set_stencil_ref = evergreen_set_stencil_ref;
1056 rctx->context.set_vertex_buffers = evergreen_set_vertex_buffers;
1057 rctx->context.set_index_buffer = evergreen_set_index_buffer;
1058 rctx->context.set_vertex_sampler_views = evergreen_set_vs_sampler_view;
1059 rctx->context.set_viewport_state = evergreen_set_viewport_state;
1060 rctx->context.sampler_view_destroy = evergreen_sampler_view_destroy;
1061 }
1062
1063 void evergreen_init_config(struct r600_pipe_context *rctx)
1064 {
1065 struct r600_pipe_state *rstate = &rctx->config;
1066 int ps_prio;
1067 int vs_prio;
1068 int gs_prio;
1069 int es_prio;
1070 int hs_prio, cs_prio, ls_prio;
1071 int num_ps_gprs;
1072 int num_vs_gprs;
1073 int num_gs_gprs;
1074 int num_es_gprs;
1075 int num_hs_gprs;
1076 int num_ls_gprs;
1077 int num_temp_gprs;
1078 int num_ps_threads;
1079 int num_vs_threads;
1080 int num_gs_threads;
1081 int num_es_threads;
1082 int num_hs_threads;
1083 int num_ls_threads;
1084 int num_ps_stack_entries;
1085 int num_vs_stack_entries;
1086 int num_gs_stack_entries;
1087 int num_es_stack_entries;
1088 int num_hs_stack_entries;
1089 int num_ls_stack_entries;
1090 enum radeon_family family;
1091 unsigned tmp;
1092
1093 family = r600_get_family(rctx->radeon);
1094 ps_prio = 0;
1095 vs_prio = 1;
1096 gs_prio = 2;
1097 es_prio = 3;
1098 hs_prio = 0;
1099 ls_prio = 0;
1100 cs_prio = 0;
1101
1102 switch (family) {
1103 case CHIP_CEDAR:
1104 default:
1105 num_ps_gprs = 93;
1106 num_vs_gprs = 46;
1107 num_temp_gprs = 4;
1108 num_gs_gprs = 31;
1109 num_es_gprs = 31;
1110 num_hs_gprs = 23;
1111 num_ls_gprs = 23;
1112 num_ps_threads = 96;
1113 num_vs_threads = 16;
1114 num_gs_threads = 16;
1115 num_es_threads = 16;
1116 num_hs_threads = 16;
1117 num_ls_threads = 16;
1118 num_ps_stack_entries = 42;
1119 num_vs_stack_entries = 42;
1120 num_gs_stack_entries = 42;
1121 num_es_stack_entries = 42;
1122 num_hs_stack_entries = 42;
1123 num_ls_stack_entries = 42;
1124 break;
1125 case CHIP_REDWOOD:
1126 num_ps_gprs = 93;
1127 num_vs_gprs = 46;
1128 num_temp_gprs = 4;
1129 num_gs_gprs = 31;
1130 num_es_gprs = 31;
1131 num_hs_gprs = 23;
1132 num_ls_gprs = 23;
1133 num_ps_threads = 128;
1134 num_vs_threads = 20;
1135 num_gs_threads = 20;
1136 num_es_threads = 20;
1137 num_hs_threads = 20;
1138 num_ls_threads = 20;
1139 num_ps_stack_entries = 42;
1140 num_vs_stack_entries = 42;
1141 num_gs_stack_entries = 42;
1142 num_es_stack_entries = 42;
1143 num_hs_stack_entries = 42;
1144 num_ls_stack_entries = 42;
1145 break;
1146 case CHIP_JUNIPER:
1147 num_ps_gprs = 93;
1148 num_vs_gprs = 46;
1149 num_temp_gprs = 4;
1150 num_gs_gprs = 31;
1151 num_es_gprs = 31;
1152 num_hs_gprs = 23;
1153 num_ls_gprs = 23;
1154 num_ps_threads = 128;
1155 num_vs_threads = 20;
1156 num_gs_threads = 20;
1157 num_es_threads = 20;
1158 num_hs_threads = 20;
1159 num_ls_threads = 20;
1160 num_ps_stack_entries = 85;
1161 num_vs_stack_entries = 85;
1162 num_gs_stack_entries = 85;
1163 num_es_stack_entries = 85;
1164 num_hs_stack_entries = 85;
1165 num_ls_stack_entries = 85;
1166 break;
1167 case CHIP_CYPRESS:
1168 case CHIP_HEMLOCK:
1169 num_ps_gprs = 93;
1170 num_vs_gprs = 46;
1171 num_temp_gprs = 4;
1172 num_gs_gprs = 31;
1173 num_es_gprs = 31;
1174 num_hs_gprs = 23;
1175 num_ls_gprs = 23;
1176 num_ps_threads = 128;
1177 num_vs_threads = 20;
1178 num_gs_threads = 20;
1179 num_es_threads = 20;
1180 num_hs_threads = 20;
1181 num_ls_threads = 20;
1182 num_ps_stack_entries = 85;
1183 num_vs_stack_entries = 85;
1184 num_gs_stack_entries = 85;
1185 num_es_stack_entries = 85;
1186 num_hs_stack_entries = 85;
1187 num_ls_stack_entries = 85;
1188 break;
1189 }
1190
1191 tmp = 0x00000000;
1192 switch (family) {
1193 case CHIP_CEDAR:
1194 break;
1195 default:
1196 tmp |= S_008C00_VC_ENABLE(1);
1197 break;
1198 }
1199 tmp |= S_008C00_EXPORT_SRC_C(1);
1200 tmp |= S_008C00_CS_PRIO(cs_prio);
1201 tmp |= S_008C00_LS_PRIO(ls_prio);
1202 tmp |= S_008C00_HS_PRIO(hs_prio);
1203 tmp |= S_008C00_PS_PRIO(ps_prio);
1204 tmp |= S_008C00_VS_PRIO(vs_prio);
1205 tmp |= S_008C00_GS_PRIO(gs_prio);
1206 tmp |= S_008C00_ES_PRIO(es_prio);
1207 r600_pipe_state_add_reg(rstate, R_008C00_SQ_CONFIG, tmp, 0xFFFFFFFF, NULL);
1208
1209 tmp = 0;
1210 tmp |= S_008C04_NUM_PS_GPRS(num_ps_gprs);
1211 tmp |= S_008C04_NUM_VS_GPRS(num_vs_gprs);
1212 tmp |= S_008C04_NUM_CLAUSE_TEMP_GPRS(num_temp_gprs);
1213 r600_pipe_state_add_reg(rstate, R_008C04_SQ_GPR_RESOURCE_MGMT_1, tmp, 0xFFFFFFFF, NULL);
1214
1215 tmp = 0;
1216 tmp |= S_008C08_NUM_GS_GPRS(num_gs_gprs);
1217 tmp |= S_008C08_NUM_ES_GPRS(num_es_gprs);
1218 r600_pipe_state_add_reg(rstate, R_008C08_SQ_GPR_RESOURCE_MGMT_2, tmp, 0xFFFFFFFF, NULL);
1219
1220 tmp = 0;
1221 tmp |= S_008C0C_NUM_HS_GPRS(num_hs_gprs);
1222 tmp |= S_008C0C_NUM_LS_GPRS(num_ls_gprs);
1223 r600_pipe_state_add_reg(rstate, R_008C0C_SQ_GPR_RESOURCE_MGMT_3, tmp, 0xFFFFFFFF, NULL);
1224
1225 tmp = 0;
1226 tmp |= S_008C18_NUM_PS_THREADS(num_ps_threads);
1227 tmp |= S_008C18_NUM_VS_THREADS(num_vs_threads);
1228 tmp |= S_008C18_NUM_GS_THREADS(num_gs_threads);
1229 tmp |= S_008C18_NUM_ES_THREADS(num_es_threads);
1230 r600_pipe_state_add_reg(rstate, R_008C18_SQ_THREAD_RESOURCE_MGMT_1, tmp, 0xFFFFFFFF, NULL);
1231
1232 tmp = 0;
1233 tmp |= S_008C1C_NUM_HS_THREADS(num_hs_threads);
1234 tmp |= S_008C1C_NUM_LS_THREADS(num_ls_threads);
1235 r600_pipe_state_add_reg(rstate, R_008C1C_SQ_THREAD_RESOURCE_MGMT_2, tmp, 0xFFFFFFFF, NULL);
1236
1237 tmp = 0;
1238 tmp |= S_008C20_NUM_PS_STACK_ENTRIES(num_ps_stack_entries);
1239 tmp |= S_008C20_NUM_VS_STACK_ENTRIES(num_vs_stack_entries);
1240 r600_pipe_state_add_reg(rstate, R_008C20_SQ_STACK_RESOURCE_MGMT_1, tmp, 0xFFFFFFFF, NULL);
1241
1242 tmp = 0;
1243 tmp |= S_008C24_NUM_GS_STACK_ENTRIES(num_gs_stack_entries);
1244 tmp |= S_008C24_NUM_ES_STACK_ENTRIES(num_es_stack_entries);
1245 r600_pipe_state_add_reg(rstate, R_008C24_SQ_STACK_RESOURCE_MGMT_2, tmp, 0xFFFFFFFF, NULL);
1246
1247 tmp = 0;
1248 tmp |= S_008C28_NUM_HS_STACK_ENTRIES(num_hs_stack_entries);
1249 tmp |= S_008C28_NUM_LS_STACK_ENTRIES(num_ls_stack_entries);
1250 r600_pipe_state_add_reg(rstate, R_008C28_SQ_STACK_RESOURCE_MGMT_3, tmp, 0xFFFFFFFF, NULL);
1251
1252 r600_pipe_state_add_reg(rstate, R_009100_SPI_CONFIG_CNTL, 0x0, 0xFFFFFFFF, NULL);
1253 r600_pipe_state_add_reg(rstate, R_00913C_SPI_CONFIG_CNTL_1, S_00913C_VTX_DONE_DELAY(4), 0xFFFFFFFF, NULL);
1254
1255 // r600_pipe_state_add_reg(rstate, R_028350_SX_MISC, 0x0, 0xFFFFFFFF, NULL);
1256
1257 // r600_pipe_state_add_reg(rstate, R_008D8C_SQ_DYN_GPR_CNTL_PS_FLUSH_REQ, 0x0, 0xFFFFFFFF, NULL);
1258 r600_pipe_state_add_reg(rstate, R_028A48_PA_SC_MODE_CNTL_0, 0x0, 0xFFFFFFFF, NULL);
1259 r600_pipe_state_add_reg(rstate, R_028A4C_PA_SC_MODE_CNTL_1, 0x0, 0xFFFFFFFF, NULL);
1260
1261 r600_pipe_state_add_reg(rstate, R_028900_SQ_ESGS_RING_ITEMSIZE, 0x0, 0xFFFFFFFF, NULL);
1262 r600_pipe_state_add_reg(rstate, R_028904_SQ_GSVS_RING_ITEMSIZE, 0x0, 0xFFFFFFFF, NULL);
1263 r600_pipe_state_add_reg(rstate, R_028908_SQ_ESTMP_RING_ITEMSIZE, 0x0, 0xFFFFFFFF, NULL);
1264 r600_pipe_state_add_reg(rstate, R_02890C_SQ_GSTMP_RING_ITEMSIZE, 0x0, 0xFFFFFFFF, NULL);
1265 r600_pipe_state_add_reg(rstate, R_028910_SQ_VSTMP_RING_ITEMSIZE, 0x0, 0xFFFFFFFF, NULL);
1266 r600_pipe_state_add_reg(rstate, R_028914_SQ_PSTMP_RING_ITEMSIZE, 0x0, 0xFFFFFFFF, NULL);
1267
1268 r600_pipe_state_add_reg(rstate, R_02891C_SQ_GS_VERT_ITEMSIZE, 0x0, 0xFFFFFFFF, NULL);
1269 r600_pipe_state_add_reg(rstate, R_028920_SQ_GS_VERT_ITEMSIZE_1, 0x0, 0xFFFFFFFF, NULL);
1270 r600_pipe_state_add_reg(rstate, R_028924_SQ_GS_VERT_ITEMSIZE_2, 0x0, 0xFFFFFFFF, NULL);
1271 r600_pipe_state_add_reg(rstate, R_028928_SQ_GS_VERT_ITEMSIZE_3, 0x0, 0xFFFFFFFF, NULL);
1272
1273 r600_pipe_state_add_reg(rstate, R_028A10_VGT_OUTPUT_PATH_CNTL, 0x0, 0xFFFFFFFF, NULL);
1274 r600_pipe_state_add_reg(rstate, R_028A14_VGT_HOS_CNTL, 0x0, 0xFFFFFFFF, NULL);
1275 r600_pipe_state_add_reg(rstate, R_028A18_VGT_HOS_MAX_TESS_LEVEL, 0x0, 0xFFFFFFFF, NULL);
1276 r600_pipe_state_add_reg(rstate, R_028A1C_VGT_HOS_MIN_TESS_LEVEL, 0x0, 0xFFFFFFFF, NULL);
1277 r600_pipe_state_add_reg(rstate, R_028A20_VGT_HOS_REUSE_DEPTH, 0x0, 0xFFFFFFFF, NULL);
1278 r600_pipe_state_add_reg(rstate, R_028A24_VGT_GROUP_PRIM_TYPE, 0x0, 0xFFFFFFFF, NULL);
1279 r600_pipe_state_add_reg(rstate, R_028A28_VGT_GROUP_FIRST_DECR, 0x0, 0xFFFFFFFF, NULL);
1280 r600_pipe_state_add_reg(rstate, R_028A2C_VGT_GROUP_DECR, 0x0, 0xFFFFFFFF, NULL);
1281 r600_pipe_state_add_reg(rstate, R_028A30_VGT_GROUP_VECT_0_CNTL, 0x0, 0xFFFFFFFF, NULL);
1282 r600_pipe_state_add_reg(rstate, R_028A34_VGT_GROUP_VECT_1_CNTL, 0x0, 0xFFFFFFFF, NULL);
1283 r600_pipe_state_add_reg(rstate, R_028A38_VGT_GROUP_VECT_0_FMT_CNTL, 0x0, 0xFFFFFFFF, NULL);
1284 r600_pipe_state_add_reg(rstate, R_028A3C_VGT_GROUP_VECT_1_FMT_CNTL, 0x0, 0xFFFFFFFF, NULL);
1285 r600_pipe_state_add_reg(rstate, R_028A40_VGT_GS_MODE, 0x0, 0xFFFFFFFF, NULL);
1286 r600_pipe_state_add_reg(rstate, R_028B94_VGT_STRMOUT_CONFIG, 0x0, 0xFFFFFFFF, NULL);
1287 r600_pipe_state_add_reg(rstate, R_028B98_VGT_STRMOUT_BUFFER_CONFIG, 0x0, 0xFFFFFFFF, NULL);
1288 r600_pipe_state_add_reg(rstate, R_028AB4_VGT_REUSE_OFF, 0x00000000, 0xFFFFFFFF, NULL);
1289 r600_pipe_state_add_reg(rstate, R_028AB8_VGT_VTX_CNT_EN, 0x0, 0xFFFFFFFF, NULL);
1290 r600_pipe_state_add_reg(rstate, R_008A14_PA_CL_ENHANCE, (3 << 1) | 1, 0xFFFFFFFF, NULL);
1291
1292 r600_pipe_state_add_reg(rstate, R_028380_SQ_VTX_SEMANTIC_0, 0x0, 0xFFFFFFFF, NULL);
1293 r600_pipe_state_add_reg(rstate, R_028384_SQ_VTX_SEMANTIC_1, 0x0, 0xFFFFFFFF, NULL);
1294 r600_pipe_state_add_reg(rstate, R_028388_SQ_VTX_SEMANTIC_2, 0x0, 0xFFFFFFFF, NULL);
1295 r600_pipe_state_add_reg(rstate, R_02838C_SQ_VTX_SEMANTIC_3, 0x0, 0xFFFFFFFF, NULL);
1296 r600_pipe_state_add_reg(rstate, R_028390_SQ_VTX_SEMANTIC_4, 0x0, 0xFFFFFFFF, NULL);
1297 r600_pipe_state_add_reg(rstate, R_028394_SQ_VTX_SEMANTIC_5, 0x0, 0xFFFFFFFF, NULL);
1298 r600_pipe_state_add_reg(rstate, R_028398_SQ_VTX_SEMANTIC_6, 0x0, 0xFFFFFFFF, NULL);
1299 r600_pipe_state_add_reg(rstate, R_02839C_SQ_VTX_SEMANTIC_7, 0x0, 0xFFFFFFFF, NULL);
1300 r600_pipe_state_add_reg(rstate, R_0283A0_SQ_VTX_SEMANTIC_8, 0x0, 0xFFFFFFFF, NULL);
1301 r600_pipe_state_add_reg(rstate, R_0283A4_SQ_VTX_SEMANTIC_9, 0x0, 0xFFFFFFFF, NULL);
1302 r600_pipe_state_add_reg(rstate, R_0283A8_SQ_VTX_SEMANTIC_10, 0x0, 0xFFFFFFFF, NULL);
1303 r600_pipe_state_add_reg(rstate, R_0283AC_SQ_VTX_SEMANTIC_11, 0x0, 0xFFFFFFFF, NULL);
1304 r600_pipe_state_add_reg(rstate, R_0283B0_SQ_VTX_SEMANTIC_12, 0x0, 0xFFFFFFFF, NULL);
1305 r600_pipe_state_add_reg(rstate, R_0283B4_SQ_VTX_SEMANTIC_13, 0x0, 0xFFFFFFFF, NULL);
1306 r600_pipe_state_add_reg(rstate, R_0283B8_SQ_VTX_SEMANTIC_14, 0x0, 0xFFFFFFFF, NULL);
1307 r600_pipe_state_add_reg(rstate, R_0283BC_SQ_VTX_SEMANTIC_15, 0x0, 0xFFFFFFFF, NULL);
1308 r600_pipe_state_add_reg(rstate, R_0283C0_SQ_VTX_SEMANTIC_16, 0x0, 0xFFFFFFFF, NULL);
1309 r600_pipe_state_add_reg(rstate, R_0283C4_SQ_VTX_SEMANTIC_17, 0x0, 0xFFFFFFFF, NULL);
1310 r600_pipe_state_add_reg(rstate, R_0283C8_SQ_VTX_SEMANTIC_18, 0x0, 0xFFFFFFFF, NULL);
1311 r600_pipe_state_add_reg(rstate, R_0283CC_SQ_VTX_SEMANTIC_19, 0x0, 0xFFFFFFFF, NULL);
1312 r600_pipe_state_add_reg(rstate, R_0283D0_SQ_VTX_SEMANTIC_20, 0x0, 0xFFFFFFFF, NULL);
1313 r600_pipe_state_add_reg(rstate, R_0283D4_SQ_VTX_SEMANTIC_21, 0x0, 0xFFFFFFFF, NULL);
1314 r600_pipe_state_add_reg(rstate, R_0283D8_SQ_VTX_SEMANTIC_22, 0x0, 0xFFFFFFFF, NULL);
1315 r600_pipe_state_add_reg(rstate, R_0283DC_SQ_VTX_SEMANTIC_23, 0x0, 0xFFFFFFFF, NULL);
1316 r600_pipe_state_add_reg(rstate, R_0283E0_SQ_VTX_SEMANTIC_24, 0x0, 0xFFFFFFFF, NULL);
1317 r600_pipe_state_add_reg(rstate, R_0283E4_SQ_VTX_SEMANTIC_25, 0x0, 0xFFFFFFFF, NULL);
1318 r600_pipe_state_add_reg(rstate, R_0283E8_SQ_VTX_SEMANTIC_26, 0x0, 0xFFFFFFFF, NULL);
1319 r600_pipe_state_add_reg(rstate, R_0283EC_SQ_VTX_SEMANTIC_27, 0x0, 0xFFFFFFFF, NULL);
1320 r600_pipe_state_add_reg(rstate, R_0283F0_SQ_VTX_SEMANTIC_28, 0x0, 0xFFFFFFFF, NULL);
1321 r600_pipe_state_add_reg(rstate, R_0283F4_SQ_VTX_SEMANTIC_29, 0x0, 0xFFFFFFFF, NULL);
1322 r600_pipe_state_add_reg(rstate, R_0283F8_SQ_VTX_SEMANTIC_30, 0x0, 0xFFFFFFFF, NULL);
1323 r600_pipe_state_add_reg(rstate, R_0283FC_SQ_VTX_SEMANTIC_31, 0x0, 0xFFFFFFFF, NULL);
1324
1325 r600_pipe_state_add_reg(rstate, R_028810_PA_CL_CLIP_CNTL,
1326 0x0, 0xFFFFFFFF, NULL);
1327
1328 r600_context_pipe_state_set(&rctx->ctx, rstate);
1329 }
1330
1331 int r600_conv_pipe_prim(unsigned pprim, unsigned *prim);
1332 void evergreen_draw(struct pipe_context *ctx, const struct pipe_draw_info *info)
1333 {
1334 struct r600_pipe_context *rctx = (struct r600_pipe_context *)ctx;
1335 struct r600_pipe_state *rstate;
1336 struct r600_resource *rbuffer;
1337 unsigned i, j, offset, format, prim;
1338 u32 vgt_dma_index_type, vgt_draw_initiator, mask;
1339 struct pipe_vertex_buffer *vertex_buffer;
1340 struct r600_draw rdraw;
1341 struct r600_pipe_state vgt;
1342 struct r600_drawl draw;
1343
1344 assert(info->index_bias == 0);
1345
1346 if (rctx->any_user_vbs) {
1347 r600_upload_user_buffers(rctx);
1348 rctx->any_user_vbs = FALSE;
1349 }
1350
1351 memset(&draw, 0, sizeof(struct r600_drawl));
1352 draw.mode = info->mode;
1353 draw.start = info->start;
1354 draw.count = info->count;
1355 if (info->indexed && rctx->index_buffer.buffer) {
1356 draw.start += rctx->index_buffer.offset / rctx->index_buffer.index_size;
1357 draw.min_index = info->min_index;
1358 draw.max_index = info->max_index;
1359 draw.index_bias = info->index_bias;
1360
1361 r600_translate_index_buffer(rctx, &rctx->index_buffer.buffer,
1362 &rctx->index_buffer.index_size,
1363 &draw.start,
1364 info->count);
1365
1366 draw.index_size = rctx->index_buffer.index_size;
1367 draw.index_buffer = rctx->index_buffer.buffer;
1368 draw.index_buffer_offset = draw.start * draw.index_size;
1369 draw.start = 0;
1370 r600_upload_index_buffer(rctx, &draw);
1371 } else {
1372 draw.index_size = 0;
1373 draw.index_buffer = NULL;
1374 draw.min_index = info->min_index;
1375 draw.max_index = info->max_index;
1376 draw.index_bias = info->start;
1377 }
1378
1379 switch (draw.index_size) {
1380 case 2:
1381 vgt_draw_initiator = 0;
1382 vgt_dma_index_type = 0;
1383 break;
1384 case 4:
1385 vgt_draw_initiator = 0;
1386 vgt_dma_index_type = 1;
1387 break;
1388 case 0:
1389 vgt_draw_initiator = 2;
1390 vgt_dma_index_type = 0;
1391 break;
1392 default:
1393 R600_ERR("unsupported index size %d\n", draw.index_size);
1394 return;
1395 }
1396 if (r600_conv_pipe_prim(draw.mode, &prim))
1397 return;
1398
1399 /* rebuild vertex shader if input format changed */
1400 if (r600_pipe_shader_update(&rctx->context, rctx->vs_shader))
1401 return;
1402 if (r600_pipe_shader_update(&rctx->context, rctx->ps_shader))
1403 return;
1404
1405 for (i = 0 ; i < rctx->vertex_elements->count; i++) {
1406 unsigned num_format = 0, format_comp = 0;
1407
1408 rstate = &rctx->vs_resource[i];
1409 j = rctx->vertex_elements->elements[i].vertex_buffer_index;
1410 vertex_buffer = &rctx->vertex_buffer[j];
1411 rbuffer = (struct r600_resource*)vertex_buffer->buffer;
1412 offset = rctx->vertex_elements->elements[i].src_offset + vertex_buffer->buffer_offset;
1413 format = r600_translate_colorformat(rctx->vertex_elements->elements[i].src_format);
1414 rstate->id = R600_PIPE_STATE_RESOURCE;
1415 rstate->nregs = 0;
1416
1417 r600_translate_vertex_num_format(rctx->vertex_elements->elements[i].src_format, &num_format, &format_comp);
1418 r600_pipe_state_add_reg(rstate, R_030000_RESOURCE0_WORD0, offset, 0xFFFFFFFF, rbuffer->bo);
1419 r600_pipe_state_add_reg(rstate, R_030004_RESOURCE0_WORD1, rbuffer->size - offset - 1, 0xFFFFFFFF, NULL);
1420 r600_pipe_state_add_reg(rstate,
1421 R_030008_RESOURCE0_WORD2,
1422 S_030008_STRIDE(vertex_buffer->stride) |
1423 S_030008_DATA_FORMAT(format) |
1424 S_030008_NUM_FORMAT_ALL(num_format) |
1425 S_030008_FORMAT_COMP_ALL(format_comp),
1426 0xFFFFFFFF, NULL);
1427 r600_pipe_state_add_reg(rstate,
1428 R_03000C_RESOURCE0_WORD3,
1429 S_03000C_DST_SEL_X(V_03000C_SQ_SEL_X) |
1430 S_03000C_DST_SEL_Y(V_03000C_SQ_SEL_Y) |
1431 S_03000C_DST_SEL_Z(V_03000C_SQ_SEL_Z) |
1432 S_03000C_DST_SEL_W(V_03000C_SQ_SEL_W),
1433 0xFFFFFFFF, NULL);
1434 r600_pipe_state_add_reg(rstate, R_030010_RESOURCE0_WORD4, 0x00000000, 0xFFFFFFFF, NULL);
1435 r600_pipe_state_add_reg(rstate, R_030014_RESOURCE0_WORD5, 0x00000000, 0xFFFFFFFF, NULL);
1436 r600_pipe_state_add_reg(rstate, R_030018_RESOURCE0_WORD6, 0x00000000, 0xFFFFFFFF, NULL);
1437 r600_pipe_state_add_reg(rstate, R_03001C_RESOURCE0_WORD7, 0xC0000000, 0xFFFFFFFF, NULL);
1438 evergreen_vs_resource_set(&rctx->ctx, rstate, i);
1439 }
1440
1441 mask = 0;
1442 for (int i = 0; i < rctx->framebuffer.nr_cbufs; i++) {
1443 mask |= (0xF << (i * 4));
1444 }
1445
1446 vgt.id = R600_PIPE_STATE_VGT;
1447 vgt.nregs = 0;
1448 r600_pipe_state_add_reg(&vgt, R_008958_VGT_PRIMITIVE_TYPE, prim, 0xFFFFFFFF, NULL);
1449 r600_pipe_state_add_reg(&vgt, R_028408_VGT_INDX_OFFSET, draw.index_bias, 0xFFFFFFFF, NULL);
1450 r600_pipe_state_add_reg(&vgt, R_028238_CB_TARGET_MASK, rctx->cb_target_mask & mask, 0xFFFFFFFF, NULL);
1451 r600_pipe_state_add_reg(&vgt, R_028400_VGT_MAX_VTX_INDX, draw.max_index, 0xFFFFFFFF, NULL);
1452 r600_pipe_state_add_reg(&vgt, R_028404_VGT_MIN_VTX_INDX, draw.min_index, 0xFFFFFFFF, NULL);
1453
1454 if (rctx->rasterizer && rctx->framebuffer.zsbuf) {
1455 float offset_units = rctx->rasterizer->offset_units;
1456 unsigned offset_db_fmt_cntl = 0, depth;
1457
1458 switch (rctx->framebuffer.zsbuf->texture->format) {
1459 case PIPE_FORMAT_Z24X8_UNORM:
1460 case PIPE_FORMAT_Z24_UNORM_S8_USCALED:
1461 depth = -24;
1462 offset_units *= 2.0f;
1463 break;
1464 case PIPE_FORMAT_Z32_FLOAT:
1465 depth = -23;
1466 offset_units *= 1.0f;
1467 offset_db_fmt_cntl |= S_028B78_POLY_OFFSET_DB_IS_FLOAT_FMT(1);
1468 break;
1469 case PIPE_FORMAT_Z16_UNORM:
1470 depth = -16;
1471 offset_units *= 4.0f;
1472 break;
1473 default:
1474 return;
1475 }
1476 offset_db_fmt_cntl |= S_028B78_POLY_OFFSET_NEG_NUM_DB_BITS(depth);
1477 r600_pipe_state_add_reg(&vgt,
1478 R_028B80_PA_SU_POLY_OFFSET_FRONT_SCALE,
1479 fui(rctx->rasterizer->offset_scale), 0xFFFFFFFF, NULL);
1480 r600_pipe_state_add_reg(&vgt,
1481 R_028B84_PA_SU_POLY_OFFSET_FRONT_OFFSET,
1482 fui(offset_units), 0xFFFFFFFF, NULL);
1483 r600_pipe_state_add_reg(&vgt,
1484 R_028B88_PA_SU_POLY_OFFSET_BACK_SCALE,
1485 fui(rctx->rasterizer->offset_scale), 0xFFFFFFFF, NULL);
1486 r600_pipe_state_add_reg(&vgt,
1487 R_028B8C_PA_SU_POLY_OFFSET_BACK_OFFSET,
1488 fui(offset_units), 0xFFFFFFFF, NULL);
1489 r600_pipe_state_add_reg(&vgt,
1490 R_028B78_PA_SU_POLY_OFFSET_DB_FMT_CNTL,
1491 offset_db_fmt_cntl, 0xFFFFFFFF, NULL);
1492 }
1493 r600_context_pipe_state_set(&rctx->ctx, &vgt);
1494
1495 rdraw.vgt_num_indices = draw.count;
1496 rdraw.vgt_num_instances = 1;
1497 rdraw.vgt_index_type = vgt_dma_index_type;
1498 rdraw.vgt_draw_initiator = vgt_draw_initiator;
1499 rdraw.indices = NULL;
1500 if (draw.index_buffer) {
1501 rbuffer = (struct r600_resource*)draw.index_buffer;
1502 rdraw.indices = rbuffer->bo;
1503 rdraw.indices_bo_offset = draw.index_buffer_offset;
1504 }
1505 evergreen_context_draw(&rctx->ctx, &rdraw);
1506 }
1507
1508 void evergreen_pipe_shader_ps(struct pipe_context *ctx, struct r600_pipe_shader *shader)
1509 {
1510 struct r600_pipe_context *rctx = (struct r600_pipe_context *)ctx;
1511 struct r600_pipe_state *rstate = &shader->rstate;
1512 struct r600_shader *rshader = &shader->shader;
1513 unsigned i, tmp, exports_ps, num_cout, spi_ps_in_control_0, spi_input_z;
1514 boolean have_pos = FALSE, have_face = FALSE;
1515
1516 /* clear previous register */
1517 rstate->nregs = 0;
1518
1519 for (i = 0; i < rshader->ninput; i++) {
1520 tmp = S_028644_SEMANTIC(r600_find_vs_semantic_index(&rctx->vs_shader->shader, rshader, i));
1521 if (rshader->input[i].name == TGSI_SEMANTIC_POSITION)
1522 have_pos = TRUE;
1523 if (rshader->input[i].name == TGSI_SEMANTIC_COLOR ||
1524 rshader->input[i].name == TGSI_SEMANTIC_BCOLOR ||
1525 rshader->input[i].name == TGSI_SEMANTIC_POSITION) {
1526 tmp |= S_028644_FLAT_SHADE(rshader->flat_shade);
1527 }
1528 if (rshader->input[i].name == TGSI_SEMANTIC_FACE)
1529 have_face = TRUE;
1530 if (rshader->input[i].name == TGSI_SEMANTIC_GENERIC &&
1531 rctx->sprite_coord_enable & (1 << rshader->input[i].sid)) {
1532 tmp |= S_028644_PT_SPRITE_TEX(1);
1533 }
1534 r600_pipe_state_add_reg(rstate, R_028644_SPI_PS_INPUT_CNTL_0 + i * 4, tmp, 0xFFFFFFFF, NULL);
1535 }
1536 for (i = 0; i < rshader->noutput; i++) {
1537 r600_pipe_state_add_reg(rstate,
1538 R_02880C_DB_SHADER_CONTROL,
1539 S_02880C_Z_EXPORT_ENABLE(1),
1540 S_02880C_Z_EXPORT_ENABLE(1), NULL);
1541 }
1542
1543 exports_ps = 0;
1544 num_cout = 0;
1545 for (i = 0; i < rshader->noutput; i++) {
1546 if (rshader->output[i].name == TGSI_SEMANTIC_POSITION)
1547 exports_ps |= 1;
1548 else if (rshader->output[i].name == TGSI_SEMANTIC_COLOR) {
1549 num_cout++;
1550 }
1551 }
1552 exports_ps |= S_02884C_EXPORT_COLORS(num_cout);
1553 if (!exports_ps) {
1554 /* always at least export 1 component per pixel */
1555 exports_ps = 2;
1556 }
1557
1558 spi_ps_in_control_0 = S_0286CC_NUM_INTERP(rshader->ninput) |
1559 S_0286CC_PERSP_GRADIENT_ENA(1);
1560 spi_input_z = 0;
1561 if (have_pos) {
1562 spi_ps_in_control_0 |= S_0286CC_POSITION_ENA(1);
1563 spi_input_z |= 1;
1564 }
1565 r600_pipe_state_add_reg(rstate, R_0286CC_SPI_PS_IN_CONTROL_0,
1566 spi_ps_in_control_0, 0xFFFFFFFF, NULL);
1567 r600_pipe_state_add_reg(rstate, R_0286D0_SPI_PS_IN_CONTROL_1,
1568 S_0286D0_FRONT_FACE_ENA(have_face), 0xFFFFFFFF, NULL);
1569 r600_pipe_state_add_reg(rstate, R_0286D8_SPI_INPUT_Z, spi_input_z, 0xFFFFFFFF, NULL);
1570 r600_pipe_state_add_reg(rstate,
1571 R_028840_SQ_PGM_START_PS,
1572 0x00000000, 0xFFFFFFFF, shader->bo);
1573 r600_pipe_state_add_reg(rstate,
1574 R_028844_SQ_PGM_RESOURCES_PS,
1575 S_028844_NUM_GPRS(rshader->bc.ngpr) |
1576 S_028844_PRIME_CACHE_ON_DRAW(1) |
1577 S_028844_STACK_SIZE(rshader->bc.nstack),
1578 0xFFFFFFFF, NULL);
1579 r600_pipe_state_add_reg(rstate,
1580 R_028848_SQ_PGM_RESOURCES_2_PS,
1581 0x0, 0xFFFFFFFF, NULL);
1582 r600_pipe_state_add_reg(rstate,
1583 R_02884C_SQ_PGM_EXPORTS_PS,
1584 exports_ps, 0xFFFFFFFF, NULL);
1585 r600_pipe_state_add_reg(rstate,
1586 R_0286E0_SPI_BARYC_CNTL,
1587 S_0286E0_PERSP_CENTROID_ENA(1) |
1588 S_0286E0_LINEAR_CENTROID_ENA(1),
1589 0xFFFFFFFF, NULL);
1590
1591 if (rshader->uses_kill) {
1592 /* only set some bits here, the other bits are set in the dsa state */
1593 r600_pipe_state_add_reg(rstate,
1594 R_02880C_DB_SHADER_CONTROL,
1595 S_02880C_KILL_ENABLE(1),
1596 S_02880C_KILL_ENABLE(1), NULL);
1597 }
1598 }
1599
1600 void evergreen_pipe_shader_vs(struct pipe_context *ctx, struct r600_pipe_shader *shader)
1601 {
1602 struct r600_pipe_state *rstate = &shader->rstate;
1603 struct r600_shader *rshader = &shader->shader;
1604 unsigned spi_vs_out_id[10];
1605 unsigned i, tmp;
1606
1607 /* clear previous register */
1608 rstate->nregs = 0;
1609
1610 /* so far never got proper semantic id from tgsi */
1611 for (i = 0; i < 10; i++) {
1612 spi_vs_out_id[i] = 0;
1613 }
1614 for (i = 0; i < 32; i++) {
1615 tmp = i << ((i & 3) * 8);
1616 spi_vs_out_id[i / 4] |= tmp;
1617 }
1618 for (i = 0; i < 10; i++) {
1619 r600_pipe_state_add_reg(rstate,
1620 R_02861C_SPI_VS_OUT_ID_0 + i * 4,
1621 spi_vs_out_id[i], 0xFFFFFFFF, NULL);
1622 }
1623
1624 r600_pipe_state_add_reg(rstate,
1625 R_0286C4_SPI_VS_OUT_CONFIG,
1626 S_0286C4_VS_EXPORT_COUNT(rshader->noutput - 2),
1627 0xFFFFFFFF, NULL);
1628 r600_pipe_state_add_reg(rstate,
1629 R_028860_SQ_PGM_RESOURCES_VS,
1630 S_028860_NUM_GPRS(rshader->bc.ngpr) |
1631 S_028860_STACK_SIZE(rshader->bc.nstack),
1632 0xFFFFFFFF, NULL);
1633 r600_pipe_state_add_reg(rstate,
1634 R_028864_SQ_PGM_RESOURCES_2_VS,
1635 0x0, 0xFFFFFFFF, NULL);
1636 r600_pipe_state_add_reg(rstate,
1637 R_0288A8_SQ_PGM_RESOURCES_FS,
1638 0x00000000, 0xFFFFFFFF, NULL);
1639 r600_pipe_state_add_reg(rstate,
1640 R_02885C_SQ_PGM_START_VS,
1641 0x00000000, 0xFFFFFFFF, shader->bo);
1642 r600_pipe_state_add_reg(rstate,
1643 R_0288A4_SQ_PGM_START_FS,
1644 0x00000000, 0xFFFFFFFF, shader->bo);
1645 }
1646
1647 void *evergreen_create_db_flush_dsa(struct r600_pipe_context *rctx)
1648 {
1649 struct pipe_depth_stencil_alpha_state dsa;
1650 struct r600_pipe_state *rstate;
1651 boolean quirk = false;
1652
1653 if (rctx->family == CHIP_RV610 || rctx->family == CHIP_RV630 ||
1654 rctx->family == CHIP_RV620 || rctx->family == CHIP_RV635)
1655 quirk = true;
1656
1657 memset(&dsa, 0, sizeof(dsa));
1658
1659 if (quirk) {
1660 dsa.depth.enabled = 1;
1661 dsa.depth.func = PIPE_FUNC_LEQUAL;
1662 dsa.stencil[0].enabled = 1;
1663 dsa.stencil[0].func = PIPE_FUNC_ALWAYS;
1664 dsa.stencil[0].zpass_op = PIPE_STENCIL_OP_KEEP;
1665 dsa.stencil[0].zfail_op = PIPE_STENCIL_OP_INCR;
1666 dsa.stencil[0].writemask = 0xff;
1667 }
1668
1669 rstate = rctx->context.create_depth_stencil_alpha_state(&rctx->context, &dsa);
1670 r600_pipe_state_add_reg(rstate,
1671 R_02880C_DB_SHADER_CONTROL,
1672 0x0,
1673 S_02880C_DUAL_EXPORT_ENABLE(1), NULL);
1674 r600_pipe_state_add_reg(rstate,
1675 R_028000_DB_RENDER_CONTROL,
1676 S_028000_DEPTH_COPY_ENABLE(1) |
1677 S_028000_STENCIL_COPY_ENABLE(1) |
1678 S_028000_COPY_CENTROID(1),
1679 S_028000_DEPTH_COPY_ENABLE(1) |
1680 S_028000_STENCIL_COPY_ENABLE(1) |
1681 S_028000_COPY_CENTROID(1), NULL);
1682 return rstate;
1683 }