2 * Copyright 2010 Jerome Glisse <glisse@freedesktop.org>
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * on the rights to use, copy, modify, merge, publish, distribute, sub
8 * license, and/or sell copies of the Software, and to permit persons to whom
9 * the Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHOR(S) AND/OR THEIR SUPPLIERS BE LIABLE FOR ANY CLAIM,
19 * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
20 * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
21 * USE OR OTHER DEALINGS IN THE SOFTWARE.
23 #include "r600_formats.h"
24 #include "r600_shader.h"
25 #include "evergreend.h"
27 #include "pipe/p_shader_tokens.h"
28 #include "util/u_pack_color.h"
29 #include "util/u_memory.h"
30 #include "util/u_framebuffer.h"
31 #include "util/u_dual_blend.h"
32 #include "evergreen_compute.h"
33 #include "util/u_math.h"
35 static inline unsigned evergreen_array_mode(unsigned mode
)
39 case RADEON_SURF_MODE_LINEAR_ALIGNED
: return V_028C70_ARRAY_LINEAR_ALIGNED
;
41 case RADEON_SURF_MODE_1D
: return V_028C70_ARRAY_1D_TILED_THIN1
;
43 case RADEON_SURF_MODE_2D
: return V_028C70_ARRAY_2D_TILED_THIN1
;
47 static uint32_t eg_num_banks(uint32_t nbanks
)
63 static unsigned eg_tile_split(unsigned tile_split
)
66 case 64: tile_split
= 0; break;
67 case 128: tile_split
= 1; break;
68 case 256: tile_split
= 2; break;
69 case 512: tile_split
= 3; break;
71 case 1024: tile_split
= 4; break;
72 case 2048: tile_split
= 5; break;
73 case 4096: tile_split
= 6; break;
78 static unsigned eg_macro_tile_aspect(unsigned macro_tile_aspect
)
80 switch (macro_tile_aspect
) {
82 case 1: macro_tile_aspect
= 0; break;
83 case 2: macro_tile_aspect
= 1; break;
84 case 4: macro_tile_aspect
= 2; break;
85 case 8: macro_tile_aspect
= 3; break;
87 return macro_tile_aspect
;
90 static unsigned eg_bank_wh(unsigned bankwh
)
94 case 1: bankwh
= 0; break;
95 case 2: bankwh
= 1; break;
96 case 4: bankwh
= 2; break;
97 case 8: bankwh
= 3; break;
102 static uint32_t r600_translate_blend_function(int blend_func
)
104 switch (blend_func
) {
106 return V_028780_COMB_DST_PLUS_SRC
;
107 case PIPE_BLEND_SUBTRACT
:
108 return V_028780_COMB_SRC_MINUS_DST
;
109 case PIPE_BLEND_REVERSE_SUBTRACT
:
110 return V_028780_COMB_DST_MINUS_SRC
;
112 return V_028780_COMB_MIN_DST_SRC
;
114 return V_028780_COMB_MAX_DST_SRC
;
116 R600_ERR("Unknown blend function %d\n", blend_func
);
123 static uint32_t r600_translate_blend_factor(int blend_fact
)
125 switch (blend_fact
) {
126 case PIPE_BLENDFACTOR_ONE
:
127 return V_028780_BLEND_ONE
;
128 case PIPE_BLENDFACTOR_SRC_COLOR
:
129 return V_028780_BLEND_SRC_COLOR
;
130 case PIPE_BLENDFACTOR_SRC_ALPHA
:
131 return V_028780_BLEND_SRC_ALPHA
;
132 case PIPE_BLENDFACTOR_DST_ALPHA
:
133 return V_028780_BLEND_DST_ALPHA
;
134 case PIPE_BLENDFACTOR_DST_COLOR
:
135 return V_028780_BLEND_DST_COLOR
;
136 case PIPE_BLENDFACTOR_SRC_ALPHA_SATURATE
:
137 return V_028780_BLEND_SRC_ALPHA_SATURATE
;
138 case PIPE_BLENDFACTOR_CONST_COLOR
:
139 return V_028780_BLEND_CONST_COLOR
;
140 case PIPE_BLENDFACTOR_CONST_ALPHA
:
141 return V_028780_BLEND_CONST_ALPHA
;
142 case PIPE_BLENDFACTOR_ZERO
:
143 return V_028780_BLEND_ZERO
;
144 case PIPE_BLENDFACTOR_INV_SRC_COLOR
:
145 return V_028780_BLEND_ONE_MINUS_SRC_COLOR
;
146 case PIPE_BLENDFACTOR_INV_SRC_ALPHA
:
147 return V_028780_BLEND_ONE_MINUS_SRC_ALPHA
;
148 case PIPE_BLENDFACTOR_INV_DST_ALPHA
:
149 return V_028780_BLEND_ONE_MINUS_DST_ALPHA
;
150 case PIPE_BLENDFACTOR_INV_DST_COLOR
:
151 return V_028780_BLEND_ONE_MINUS_DST_COLOR
;
152 case PIPE_BLENDFACTOR_INV_CONST_COLOR
:
153 return V_028780_BLEND_ONE_MINUS_CONST_COLOR
;
154 case PIPE_BLENDFACTOR_INV_CONST_ALPHA
:
155 return V_028780_BLEND_ONE_MINUS_CONST_ALPHA
;
156 case PIPE_BLENDFACTOR_SRC1_COLOR
:
157 return V_028780_BLEND_SRC1_COLOR
;
158 case PIPE_BLENDFACTOR_SRC1_ALPHA
:
159 return V_028780_BLEND_SRC1_ALPHA
;
160 case PIPE_BLENDFACTOR_INV_SRC1_COLOR
:
161 return V_028780_BLEND_INV_SRC1_COLOR
;
162 case PIPE_BLENDFACTOR_INV_SRC1_ALPHA
:
163 return V_028780_BLEND_INV_SRC1_ALPHA
;
165 R600_ERR("Bad blend factor %d not supported!\n", blend_fact
);
172 static unsigned r600_tex_dim(struct r600_texture
*rtex
,
173 unsigned view_target
, unsigned nr_samples
)
175 unsigned res_target
= rtex
->resource
.b
.b
.target
;
177 if (view_target
== PIPE_TEXTURE_CUBE
||
178 view_target
== PIPE_TEXTURE_CUBE_ARRAY
)
179 res_target
= view_target
;
180 /* If interpreting cubemaps as something else, set 2D_ARRAY. */
181 else if (res_target
== PIPE_TEXTURE_CUBE
||
182 res_target
== PIPE_TEXTURE_CUBE_ARRAY
)
183 res_target
= PIPE_TEXTURE_2D_ARRAY
;
185 switch (res_target
) {
187 case PIPE_TEXTURE_1D
:
188 return V_030000_SQ_TEX_DIM_1D
;
189 case PIPE_TEXTURE_1D_ARRAY
:
190 return V_030000_SQ_TEX_DIM_1D_ARRAY
;
191 case PIPE_TEXTURE_2D
:
192 case PIPE_TEXTURE_RECT
:
193 return nr_samples
> 1 ? V_030000_SQ_TEX_DIM_2D_MSAA
:
194 V_030000_SQ_TEX_DIM_2D
;
195 case PIPE_TEXTURE_2D_ARRAY
:
196 return nr_samples
> 1 ? V_030000_SQ_TEX_DIM_2D_ARRAY_MSAA
:
197 V_030000_SQ_TEX_DIM_2D_ARRAY
;
198 case PIPE_TEXTURE_3D
:
199 return V_030000_SQ_TEX_DIM_3D
;
200 case PIPE_TEXTURE_CUBE
:
201 case PIPE_TEXTURE_CUBE_ARRAY
:
202 return V_030000_SQ_TEX_DIM_CUBEMAP
;
206 static uint32_t r600_translate_dbformat(enum pipe_format format
)
209 case PIPE_FORMAT_Z16_UNORM
:
210 return V_028040_Z_16
;
211 case PIPE_FORMAT_Z24X8_UNORM
:
212 case PIPE_FORMAT_Z24_UNORM_S8_UINT
:
213 case PIPE_FORMAT_X8Z24_UNORM
:
214 case PIPE_FORMAT_S8_UINT_Z24_UNORM
:
215 return V_028040_Z_24
;
216 case PIPE_FORMAT_Z32_FLOAT
:
217 case PIPE_FORMAT_Z32_FLOAT_S8X24_UINT
:
218 return V_028040_Z_32_FLOAT
;
224 static bool r600_is_sampler_format_supported(struct pipe_screen
*screen
, enum pipe_format format
)
226 return r600_translate_texformat(screen
, format
, NULL
, NULL
, NULL
,
230 static bool r600_is_colorbuffer_format_supported(enum chip_class chip
, enum pipe_format format
)
232 return r600_translate_colorformat(chip
, format
, FALSE
) != ~0U &&
233 r600_translate_colorswap(format
, FALSE
) != ~0U;
236 static bool r600_is_zs_format_supported(enum pipe_format format
)
238 return r600_translate_dbformat(format
) != ~0U;
241 boolean
evergreen_is_format_supported(struct pipe_screen
*screen
,
242 enum pipe_format format
,
243 enum pipe_texture_target target
,
244 unsigned sample_count
,
247 struct r600_screen
*rscreen
= (struct r600_screen
*)screen
;
250 if (target
>= PIPE_MAX_TEXTURE_TYPES
) {
251 R600_ERR("r600: unsupported texture type %d\n", target
);
255 if (!util_format_is_supported(format
, usage
))
258 if (sample_count
> 1) {
259 if (!rscreen
->has_msaa
)
262 switch (sample_count
) {
272 if (usage
& PIPE_BIND_SAMPLER_VIEW
) {
273 if (target
== PIPE_BUFFER
) {
274 if (r600_is_vertex_format_supported(format
))
275 retval
|= PIPE_BIND_SAMPLER_VIEW
;
277 if (r600_is_sampler_format_supported(screen
, format
))
278 retval
|= PIPE_BIND_SAMPLER_VIEW
;
282 if ((usage
& (PIPE_BIND_RENDER_TARGET
|
283 PIPE_BIND_DISPLAY_TARGET
|
286 PIPE_BIND_BLENDABLE
)) &&
287 r600_is_colorbuffer_format_supported(rscreen
->b
.chip_class
, format
)) {
289 (PIPE_BIND_RENDER_TARGET
|
290 PIPE_BIND_DISPLAY_TARGET
|
293 if (!util_format_is_pure_integer(format
) &&
294 !util_format_is_depth_or_stencil(format
))
295 retval
|= usage
& PIPE_BIND_BLENDABLE
;
298 if ((usage
& PIPE_BIND_DEPTH_STENCIL
) &&
299 r600_is_zs_format_supported(format
)) {
300 retval
|= PIPE_BIND_DEPTH_STENCIL
;
303 if ((usage
& PIPE_BIND_VERTEX_BUFFER
) &&
304 r600_is_vertex_format_supported(format
)) {
305 retval
|= PIPE_BIND_VERTEX_BUFFER
;
308 if ((usage
& PIPE_BIND_LINEAR
) &&
309 !util_format_is_compressed(format
) &&
310 !(usage
& PIPE_BIND_DEPTH_STENCIL
))
311 retval
|= PIPE_BIND_LINEAR
;
313 return retval
== usage
;
316 static void *evergreen_create_blend_state_mode(struct pipe_context
*ctx
,
317 const struct pipe_blend_state
*state
, int mode
)
319 uint32_t color_control
= 0, target_mask
= 0;
320 struct r600_blend_state
*blend
= CALLOC_STRUCT(r600_blend_state
);
326 r600_init_command_buffer(&blend
->buffer
, 20);
327 r600_init_command_buffer(&blend
->buffer_no_blend
, 20);
329 if (state
->logicop_enable
) {
330 color_control
|= (state
->logicop_func
<< 16) | (state
->logicop_func
<< 20);
332 color_control
|= (0xcc << 16);
334 /* we pretend 8 buffer are used, CB_SHADER_MASK will disable unused one */
335 if (state
->independent_blend_enable
) {
336 for (int i
= 0; i
< 8; i
++) {
337 target_mask
|= (state
->rt
[i
].colormask
<< (4 * i
));
340 for (int i
= 0; i
< 8; i
++) {
341 target_mask
|= (state
->rt
[0].colormask
<< (4 * i
));
345 /* only have dual source on MRT0 */
346 blend
->dual_src_blend
= util_blend_state_is_dual(state
, 0);
347 blend
->cb_target_mask
= target_mask
;
348 blend
->alpha_to_one
= state
->alpha_to_one
;
351 color_control
|= S_028808_MODE(mode
);
353 color_control
|= S_028808_MODE(V_028808_CB_DISABLE
);
356 r600_store_context_reg(&blend
->buffer
, R_028808_CB_COLOR_CONTROL
, color_control
);
357 r600_store_context_reg(&blend
->buffer
, R_028B70_DB_ALPHA_TO_MASK
,
358 S_028B70_ALPHA_TO_MASK_ENABLE(state
->alpha_to_coverage
) |
359 S_028B70_ALPHA_TO_MASK_OFFSET0(2) |
360 S_028B70_ALPHA_TO_MASK_OFFSET1(2) |
361 S_028B70_ALPHA_TO_MASK_OFFSET2(2) |
362 S_028B70_ALPHA_TO_MASK_OFFSET3(2));
363 r600_store_context_reg_seq(&blend
->buffer
, R_028780_CB_BLEND0_CONTROL
, 8);
365 /* Copy over the dwords set so far into buffer_no_blend.
366 * Only the CB_BLENDi_CONTROL registers must be set after this. */
367 memcpy(blend
->buffer_no_blend
.buf
, blend
->buffer
.buf
, blend
->buffer
.num_dw
* 4);
368 blend
->buffer_no_blend
.num_dw
= blend
->buffer
.num_dw
;
370 for (int i
= 0; i
< 8; i
++) {
371 /* state->rt entries > 0 only written if independent blending */
372 const int j
= state
->independent_blend_enable
? i
: 0;
374 unsigned eqRGB
= state
->rt
[j
].rgb_func
;
375 unsigned srcRGB
= state
->rt
[j
].rgb_src_factor
;
376 unsigned dstRGB
= state
->rt
[j
].rgb_dst_factor
;
377 unsigned eqA
= state
->rt
[j
].alpha_func
;
378 unsigned srcA
= state
->rt
[j
].alpha_src_factor
;
379 unsigned dstA
= state
->rt
[j
].alpha_dst_factor
;
382 r600_store_value(&blend
->buffer_no_blend
, 0);
384 if (!state
->rt
[j
].blend_enable
) {
385 r600_store_value(&blend
->buffer
, 0);
389 bc
|= S_028780_BLEND_CONTROL_ENABLE(1);
390 bc
|= S_028780_COLOR_COMB_FCN(r600_translate_blend_function(eqRGB
));
391 bc
|= S_028780_COLOR_SRCBLEND(r600_translate_blend_factor(srcRGB
));
392 bc
|= S_028780_COLOR_DESTBLEND(r600_translate_blend_factor(dstRGB
));
394 if (srcA
!= srcRGB
|| dstA
!= dstRGB
|| eqA
!= eqRGB
) {
395 bc
|= S_028780_SEPARATE_ALPHA_BLEND(1);
396 bc
|= S_028780_ALPHA_COMB_FCN(r600_translate_blend_function(eqA
));
397 bc
|= S_028780_ALPHA_SRCBLEND(r600_translate_blend_factor(srcA
));
398 bc
|= S_028780_ALPHA_DESTBLEND(r600_translate_blend_factor(dstA
));
400 r600_store_value(&blend
->buffer
, bc
);
405 static void *evergreen_create_blend_state(struct pipe_context
*ctx
,
406 const struct pipe_blend_state
*state
)
409 return evergreen_create_blend_state_mode(ctx
, state
, V_028808_CB_NORMAL
);
412 static void *evergreen_create_dsa_state(struct pipe_context
*ctx
,
413 const struct pipe_depth_stencil_alpha_state
*state
)
415 unsigned db_depth_control
, alpha_test_control
, alpha_ref
;
416 struct r600_dsa_state
*dsa
= CALLOC_STRUCT(r600_dsa_state
);
422 r600_init_command_buffer(&dsa
->buffer
, 3);
424 dsa
->valuemask
[0] = state
->stencil
[0].valuemask
;
425 dsa
->valuemask
[1] = state
->stencil
[1].valuemask
;
426 dsa
->writemask
[0] = state
->stencil
[0].writemask
;
427 dsa
->writemask
[1] = state
->stencil
[1].writemask
;
428 dsa
->zwritemask
= state
->depth
.writemask
;
430 db_depth_control
= S_028800_Z_ENABLE(state
->depth
.enabled
) |
431 S_028800_Z_WRITE_ENABLE(state
->depth
.writemask
) |
432 S_028800_ZFUNC(state
->depth
.func
);
435 if (state
->stencil
[0].enabled
) {
436 db_depth_control
|= S_028800_STENCIL_ENABLE(1);
437 db_depth_control
|= S_028800_STENCILFUNC(state
->stencil
[0].func
); /* translates straight */
438 db_depth_control
|= S_028800_STENCILFAIL(r600_translate_stencil_op(state
->stencil
[0].fail_op
));
439 db_depth_control
|= S_028800_STENCILZPASS(r600_translate_stencil_op(state
->stencil
[0].zpass_op
));
440 db_depth_control
|= S_028800_STENCILZFAIL(r600_translate_stencil_op(state
->stencil
[0].zfail_op
));
442 if (state
->stencil
[1].enabled
) {
443 db_depth_control
|= S_028800_BACKFACE_ENABLE(1);
444 db_depth_control
|= S_028800_STENCILFUNC_BF(state
->stencil
[1].func
); /* translates straight */
445 db_depth_control
|= S_028800_STENCILFAIL_BF(r600_translate_stencil_op(state
->stencil
[1].fail_op
));
446 db_depth_control
|= S_028800_STENCILZPASS_BF(r600_translate_stencil_op(state
->stencil
[1].zpass_op
));
447 db_depth_control
|= S_028800_STENCILZFAIL_BF(r600_translate_stencil_op(state
->stencil
[1].zfail_op
));
452 alpha_test_control
= 0;
454 if (state
->alpha
.enabled
) {
455 alpha_test_control
= S_028410_ALPHA_FUNC(state
->alpha
.func
);
456 alpha_test_control
|= S_028410_ALPHA_TEST_ENABLE(1);
457 alpha_ref
= fui(state
->alpha
.ref_value
);
459 dsa
->sx_alpha_test_control
= alpha_test_control
& 0xff;
460 dsa
->alpha_ref
= alpha_ref
;
463 r600_store_context_reg(&dsa
->buffer
, R_028800_DB_DEPTH_CONTROL
, db_depth_control
);
467 static void *evergreen_create_rs_state(struct pipe_context
*ctx
,
468 const struct pipe_rasterizer_state
*state
)
470 struct r600_context
*rctx
= (struct r600_context
*)ctx
;
471 unsigned tmp
, spi_interp
;
472 float psize_min
, psize_max
;
473 struct r600_rasterizer_state
*rs
= CALLOC_STRUCT(r600_rasterizer_state
);
479 r600_init_command_buffer(&rs
->buffer
, 30);
481 rs
->scissor_enable
= state
->scissor
;
482 rs
->clip_halfz
= state
->clip_halfz
;
483 rs
->flatshade
= state
->flatshade
;
484 rs
->sprite_coord_enable
= state
->sprite_coord_enable
;
485 rs
->rasterizer_discard
= state
->rasterizer_discard
;
486 rs
->two_side
= state
->light_twoside
;
487 rs
->clip_plane_enable
= state
->clip_plane_enable
;
488 rs
->pa_sc_line_stipple
= state
->line_stipple_enable
?
489 S_028A0C_LINE_PATTERN(state
->line_stipple_pattern
) |
490 S_028A0C_REPEAT_COUNT(state
->line_stipple_factor
) : 0;
491 rs
->pa_cl_clip_cntl
=
492 S_028810_DX_CLIP_SPACE_DEF(state
->clip_halfz
) |
493 S_028810_ZCLIP_NEAR_DISABLE(!state
->depth_clip
) |
494 S_028810_ZCLIP_FAR_DISABLE(!state
->depth_clip
) |
495 S_028810_DX_LINEAR_ATTR_CLIP_ENA(1) |
496 S_028810_DX_RASTERIZATION_KILL(state
->rasterizer_discard
);
497 rs
->multisample_enable
= state
->multisample
;
500 rs
->offset_units
= state
->offset_units
;
501 rs
->offset_scale
= state
->offset_scale
* 16.0f
;
502 rs
->offset_enable
= state
->offset_point
|| state
->offset_line
|| state
->offset_tri
;
503 rs
->offset_units_unscaled
= state
->offset_units_unscaled
;
505 if (state
->point_size_per_vertex
) {
506 psize_min
= util_get_min_point_size(state
);
509 /* Force the point size to be as if the vertex output was disabled. */
510 psize_min
= state
->point_size
;
511 psize_max
= state
->point_size
;
514 spi_interp
= S_0286D4_FLAT_SHADE_ENA(1);
515 if (state
->sprite_coord_enable
) {
516 spi_interp
|= S_0286D4_PNT_SPRITE_ENA(1) |
517 S_0286D4_PNT_SPRITE_OVRD_X(2) |
518 S_0286D4_PNT_SPRITE_OVRD_Y(3) |
519 S_0286D4_PNT_SPRITE_OVRD_Z(0) |
520 S_0286D4_PNT_SPRITE_OVRD_W(1);
521 if (state
->sprite_coord_mode
!= PIPE_SPRITE_COORD_UPPER_LEFT
) {
522 spi_interp
|= S_0286D4_PNT_SPRITE_TOP_1(1);
526 r600_store_context_reg_seq(&rs
->buffer
, R_028A00_PA_SU_POINT_SIZE
, 3);
527 /* point size 12.4 fixed point (divide by two, because 0.5 = 1 pixel) */
528 tmp
= r600_pack_float_12p4(state
->point_size
/2);
529 r600_store_value(&rs
->buffer
, /* R_028A00_PA_SU_POINT_SIZE */
530 S_028A00_HEIGHT(tmp
) | S_028A00_WIDTH(tmp
));
531 r600_store_value(&rs
->buffer
, /* R_028A04_PA_SU_POINT_MINMAX */
532 S_028A04_MIN_SIZE(r600_pack_float_12p4(psize_min
/2)) |
533 S_028A04_MAX_SIZE(r600_pack_float_12p4(psize_max
/2)));
534 r600_store_value(&rs
->buffer
, /* R_028A08_PA_SU_LINE_CNTL */
535 S_028A08_WIDTH((unsigned)(state
->line_width
* 8)));
537 r600_store_context_reg(&rs
->buffer
, R_0286D4_SPI_INTERP_CONTROL_0
, spi_interp
);
538 r600_store_context_reg(&rs
->buffer
, R_028A48_PA_SC_MODE_CNTL_0
,
539 S_028A48_MSAA_ENABLE(state
->multisample
) |
540 S_028A48_VPORT_SCISSOR_ENABLE(1) |
541 S_028A48_LINE_STIPPLE_ENABLE(state
->line_stipple_enable
));
543 if (rctx
->b
.chip_class
== CAYMAN
) {
544 r600_store_context_reg(&rs
->buffer
, CM_R_028BE4_PA_SU_VTX_CNTL
,
545 S_028C08_PIX_CENTER_HALF(state
->half_pixel_center
) |
546 S_028C08_QUANT_MODE(V_028C08_X_1_256TH
));
548 r600_store_context_reg(&rs
->buffer
, R_028C08_PA_SU_VTX_CNTL
,
549 S_028C08_PIX_CENTER_HALF(state
->half_pixel_center
) |
550 S_028C08_QUANT_MODE(V_028C08_X_1_256TH
));
553 r600_store_context_reg(&rs
->buffer
, R_028B7C_PA_SU_POLY_OFFSET_CLAMP
, fui(state
->offset_clamp
));
554 r600_store_context_reg(&rs
->buffer
, R_028814_PA_SU_SC_MODE_CNTL
,
555 S_028814_PROVOKING_VTX_LAST(!state
->flatshade_first
) |
556 S_028814_CULL_FRONT((state
->cull_face
& PIPE_FACE_FRONT
) ? 1 : 0) |
557 S_028814_CULL_BACK((state
->cull_face
& PIPE_FACE_BACK
) ? 1 : 0) |
558 S_028814_FACE(!state
->front_ccw
) |
559 S_028814_POLY_OFFSET_FRONT_ENABLE(util_get_offset(state
, state
->fill_front
)) |
560 S_028814_POLY_OFFSET_BACK_ENABLE(util_get_offset(state
, state
->fill_back
)) |
561 S_028814_POLY_OFFSET_PARA_ENABLE(state
->offset_point
|| state
->offset_line
) |
562 S_028814_POLY_MODE(state
->fill_front
!= PIPE_POLYGON_MODE_FILL
||
563 state
->fill_back
!= PIPE_POLYGON_MODE_FILL
) |
564 S_028814_POLYMODE_FRONT_PTYPE(r600_translate_fill(state
->fill_front
)) |
565 S_028814_POLYMODE_BACK_PTYPE(r600_translate_fill(state
->fill_back
)));
569 static void *evergreen_create_sampler_state(struct pipe_context
*ctx
,
570 const struct pipe_sampler_state
*state
)
572 struct r600_common_screen
*rscreen
= (struct r600_common_screen
*)ctx
->screen
;
573 struct r600_pipe_sampler_state
*ss
= CALLOC_STRUCT(r600_pipe_sampler_state
);
574 unsigned max_aniso
= rscreen
->force_aniso
>= 0 ? rscreen
->force_aniso
575 : state
->max_anisotropy
;
576 unsigned max_aniso_ratio
= r600_tex_aniso_filter(max_aniso
);
582 ss
->border_color_use
= sampler_state_needs_border_color(state
);
584 /* R_03C000_SQ_TEX_SAMPLER_WORD0_0 */
585 ss
->tex_sampler_words
[0] =
586 S_03C000_CLAMP_X(r600_tex_wrap(state
->wrap_s
)) |
587 S_03C000_CLAMP_Y(r600_tex_wrap(state
->wrap_t
)) |
588 S_03C000_CLAMP_Z(r600_tex_wrap(state
->wrap_r
)) |
589 S_03C000_XY_MAG_FILTER(eg_tex_filter(state
->mag_img_filter
, max_aniso
)) |
590 S_03C000_XY_MIN_FILTER(eg_tex_filter(state
->min_img_filter
, max_aniso
)) |
591 S_03C000_MIP_FILTER(r600_tex_mipfilter(state
->min_mip_filter
)) |
592 S_03C000_MAX_ANISO_RATIO(max_aniso_ratio
) |
593 S_03C000_DEPTH_COMPARE_FUNCTION(r600_tex_compare(state
->compare_func
)) |
594 S_03C000_BORDER_COLOR_TYPE(ss
->border_color_use
? V_03C000_SQ_TEX_BORDER_COLOR_REGISTER
: 0);
595 /* R_03C004_SQ_TEX_SAMPLER_WORD1_0 */
596 ss
->tex_sampler_words
[1] =
597 S_03C004_MIN_LOD(S_FIXED(CLAMP(state
->min_lod
, 0, 15), 8)) |
598 S_03C004_MAX_LOD(S_FIXED(CLAMP(state
->max_lod
, 0, 15), 8));
599 /* R_03C008_SQ_TEX_SAMPLER_WORD2_0 */
600 ss
->tex_sampler_words
[2] =
601 S_03C008_LOD_BIAS(S_FIXED(CLAMP(state
->lod_bias
, -16, 16), 8)) |
602 (state
->seamless_cube_map
? 0 : S_03C008_DISABLE_CUBE_WRAP(1)) |
605 if (ss
->border_color_use
) {
606 memcpy(&ss
->border_color
, &state
->border_color
, sizeof(state
->border_color
));
611 struct eg_buf_res_params
{
612 enum pipe_format pipe_format
;
615 unsigned char swizzle
[4];
619 static void evergreen_fill_buffer_resource_words(struct r600_context
*rctx
,
620 struct pipe_resource
*buffer
,
621 struct eg_buf_res_params
*params
,
622 bool *skip_mip_address_reloc
,
623 unsigned tex_resource_words
[8])
625 struct r600_texture
*tmp
= (struct r600_texture
*)buffer
;
627 int stride
= util_format_get_blocksize(params
->pipe_format
);
628 unsigned format
, num_format
, format_comp
, endian
;
629 unsigned swizzle_res
;
630 const struct util_format_description
*desc
;
632 r600_vertex_data_type(params
->pipe_format
,
633 &format
, &num_format
, &format_comp
,
636 desc
= util_format_description(params
->pipe_format
);
638 swizzle_res
= r600_get_swizzle_combined(desc
->swizzle
, params
->swizzle
, TRUE
);
640 va
= tmp
->resource
.gpu_address
+ params
->offset
;
641 *skip_mip_address_reloc
= true;
642 tex_resource_words
[0] = va
;
643 tex_resource_words
[1] = params
->size
- 1;
644 tex_resource_words
[2] = S_030008_BASE_ADDRESS_HI(va
>> 32UL) |
645 S_030008_STRIDE(stride
) |
646 S_030008_DATA_FORMAT(format
) |
647 S_030008_NUM_FORMAT_ALL(num_format
) |
648 S_030008_FORMAT_COMP_ALL(format_comp
) |
649 S_030008_ENDIAN_SWAP(endian
);
650 tex_resource_words
[3] = swizzle_res
| S_03000C_UNCACHED(params
->uncached
);
652 * in theory dword 4 is for number of elements, for use with resinfo,
653 * but it seems to utterly fail to work, the amd gpu shader analyser
654 * uses a const buffer to store the element sizes for buffer txq
656 tex_resource_words
[4] = 0;
657 tex_resource_words
[5] = tex_resource_words
[6] = 0;
658 tex_resource_words
[7] = S_03001C_TYPE(V_03001C_SQ_TEX_VTX_VALID_BUFFER
);
661 static struct pipe_sampler_view
*
662 texture_buffer_sampler_view(struct r600_context
*rctx
,
663 struct r600_pipe_sampler_view
*view
,
664 unsigned width0
, unsigned height0
)
666 struct r600_texture
*tmp
= (struct r600_texture
*)view
->base
.texture
;
667 struct eg_buf_res_params params
;
669 memset(¶ms
, 0, sizeof(params
));
671 params
.pipe_format
= view
->base
.format
;
672 params
.offset
= view
->base
.u
.buf
.offset
;
673 params
.size
= view
->base
.u
.buf
.size
;
674 params
.swizzle
[0] = view
->base
.swizzle_r
;
675 params
.swizzle
[1] = view
->base
.swizzle_g
;
676 params
.swizzle
[2] = view
->base
.swizzle_b
;
677 params
.swizzle
[3] = view
->base
.swizzle_a
;
679 evergreen_fill_buffer_resource_words(rctx
, view
->base
.texture
,
680 ¶ms
, &view
->skip_mip_address_reloc
,
681 view
->tex_resource_words
);
682 view
->tex_resource
= &tmp
->resource
;
684 if (tmp
->resource
.gpu_address
)
685 LIST_ADDTAIL(&view
->list
, &rctx
->texture_buffers
);
689 struct eg_tex_res_params
{
690 enum pipe_format pipe_format
;
694 unsigned first_level
;
696 unsigned first_layer
;
699 unsigned char swizzle
[4];
702 static int evergreen_fill_tex_resource_words(struct r600_context
*rctx
,
703 struct pipe_resource
*texture
,
704 struct eg_tex_res_params
*params
,
705 bool *skip_mip_address_reloc
,
706 unsigned tex_resource_words
[8])
708 struct r600_screen
*rscreen
= (struct r600_screen
*)rctx
->b
.b
.screen
;
709 struct r600_texture
*tmp
= (struct r600_texture
*)texture
;
710 unsigned format
, endian
;
711 uint32_t word4
= 0, yuv_format
= 0, pitch
= 0;
712 unsigned char array_mode
= 0, non_disp_tiling
= 0;
713 unsigned height
, depth
, width
;
714 unsigned macro_aspect
, tile_split
, bankh
, bankw
, nbanks
, fmask_bankh
;
715 struct legacy_surf_level
*surflevel
;
716 unsigned base_level
, first_level
, last_level
;
717 unsigned dim
, last_layer
;
719 bool do_endian_swap
= FALSE
;
721 tile_split
= tmp
->surface
.u
.legacy
.tile_split
;
722 surflevel
= tmp
->surface
.u
.legacy
.level
;
724 /* Texturing with separate depth and stencil. */
725 if (tmp
->db_compatible
) {
726 switch (params
->pipe_format
) {
727 case PIPE_FORMAT_Z32_FLOAT_S8X24_UINT
:
728 params
->pipe_format
= PIPE_FORMAT_Z32_FLOAT
;
730 case PIPE_FORMAT_X8Z24_UNORM
:
731 case PIPE_FORMAT_S8_UINT_Z24_UNORM
:
732 /* Z24 is always stored like this for DB
735 params
->pipe_format
= PIPE_FORMAT_Z24X8_UNORM
;
737 case PIPE_FORMAT_X24S8_UINT
:
738 case PIPE_FORMAT_S8X24_UINT
:
739 case PIPE_FORMAT_X32_S8X24_UINT
:
740 params
->pipe_format
= PIPE_FORMAT_S8_UINT
;
741 tile_split
= tmp
->surface
.u
.legacy
.stencil_tile_split
;
742 surflevel
= tmp
->surface
.u
.legacy
.stencil_level
;
749 do_endian_swap
= !tmp
->db_compatible
;
751 format
= r600_translate_texformat(rctx
->b
.b
.screen
, params
->pipe_format
,
753 &word4
, &yuv_format
, do_endian_swap
);
754 assert(format
!= ~0);
759 endian
= r600_colorformat_endian_swap(format
, do_endian_swap
);
762 first_level
= params
->first_level
;
763 last_level
= params
->last_level
;
764 width
= params
->width0
;
765 height
= params
->height0
;
766 depth
= texture
->depth0
;
768 if (params
->force_level
) {
769 base_level
= params
->force_level
;
772 width
= u_minify(width
, params
->force_level
);
773 height
= u_minify(height
, params
->force_level
);
774 depth
= u_minify(depth
, params
->force_level
);
777 pitch
= surflevel
[base_level
].nblk_x
* util_format_get_blockwidth(params
->pipe_format
);
778 non_disp_tiling
= tmp
->non_disp_tiling
;
780 switch (surflevel
[base_level
].mode
) {
782 case RADEON_SURF_MODE_LINEAR_ALIGNED
:
783 array_mode
= V_028C70_ARRAY_LINEAR_ALIGNED
;
785 case RADEON_SURF_MODE_2D
:
786 array_mode
= V_028C70_ARRAY_2D_TILED_THIN1
;
788 case RADEON_SURF_MODE_1D
:
789 array_mode
= V_028C70_ARRAY_1D_TILED_THIN1
;
792 macro_aspect
= tmp
->surface
.u
.legacy
.mtilea
;
793 bankw
= tmp
->surface
.u
.legacy
.bankw
;
794 bankh
= tmp
->surface
.u
.legacy
.bankh
;
795 tile_split
= eg_tile_split(tile_split
);
796 macro_aspect
= eg_macro_tile_aspect(macro_aspect
);
797 bankw
= eg_bank_wh(bankw
);
798 bankh
= eg_bank_wh(bankh
);
799 fmask_bankh
= eg_bank_wh(tmp
->fmask
.bank_height
);
801 /* 128 bit formats require tile type = 1 */
802 if (rscreen
->b
.chip_class
== CAYMAN
) {
803 if (util_format_get_blocksize(params
->pipe_format
) >= 16)
806 nbanks
= eg_num_banks(rscreen
->b
.info
.r600_num_banks
);
808 if (params
->target
== PIPE_TEXTURE_1D_ARRAY
) {
810 depth
= texture
->array_size
;
811 } else if (params
->target
== PIPE_TEXTURE_2D_ARRAY
) {
812 depth
= texture
->array_size
;
813 } else if (params
->target
== PIPE_TEXTURE_CUBE_ARRAY
)
814 depth
= texture
->array_size
/ 6;
816 va
= tmp
->resource
.gpu_address
;
818 /* array type views and views into array types need to use layer offset */
819 dim
= r600_tex_dim(tmp
, params
->target
, texture
->nr_samples
);
820 tex_resource_words
[0] = (S_030000_DIM(dim
) |
821 S_030000_PITCH((pitch
/ 8) - 1) |
822 S_030000_TEX_WIDTH(width
- 1));
823 if (rscreen
->b
.chip_class
== CAYMAN
)
824 tex_resource_words
[0] |= CM_S_030000_NON_DISP_TILING_ORDER(non_disp_tiling
);
826 tex_resource_words
[0] |= S_030000_NON_DISP_TILING_ORDER(non_disp_tiling
);
827 tex_resource_words
[1] = (S_030004_TEX_HEIGHT(height
- 1) |
828 S_030004_TEX_DEPTH(depth
- 1) |
829 S_030004_ARRAY_MODE(array_mode
));
830 tex_resource_words
[2] = (surflevel
[base_level
].offset
+ va
) >> 8;
832 *skip_mip_address_reloc
= false;
833 /* TEX_RESOURCE_WORD3.MIP_ADDRESS */
834 if (texture
->nr_samples
> 1 && rscreen
->has_compressed_msaa_texturing
) {
836 /* disable FMASK (0 = disabled) */
837 tex_resource_words
[3] = 0;
838 *skip_mip_address_reloc
= true;
840 /* FMASK should be in MIP_ADDRESS for multisample textures */
841 tex_resource_words
[3] = (tmp
->fmask
.offset
+ va
) >> 8;
843 } else if (last_level
&& texture
->nr_samples
<= 1) {
844 tex_resource_words
[3] = (surflevel
[1].offset
+ va
) >> 8;
846 tex_resource_words
[3] = (surflevel
[base_level
].offset
+ va
) >> 8;
849 last_layer
= params
->last_layer
;
850 if (params
->target
!= texture
->target
&& depth
== 1) {
851 last_layer
= params
->first_layer
;
853 tex_resource_words
[4] = (word4
|
854 S_030010_ENDIAN_SWAP(endian
));
855 tex_resource_words
[5] = S_030014_BASE_ARRAY(params
->first_layer
) |
856 S_030014_LAST_ARRAY(last_layer
);
857 tex_resource_words
[6] = S_030018_TILE_SPLIT(tile_split
);
859 if (texture
->nr_samples
> 1) {
860 unsigned log_samples
= util_logbase2(texture
->nr_samples
);
861 if (rscreen
->b
.chip_class
== CAYMAN
) {
862 tex_resource_words
[4] |= S_030010_LOG2_NUM_FRAGMENTS(log_samples
);
864 /* LAST_LEVEL holds log2(nr_samples) for multisample textures */
865 tex_resource_words
[5] |= S_030014_LAST_LEVEL(log_samples
);
866 tex_resource_words
[6] |= S_030018_FMASK_BANK_HEIGHT(fmask_bankh
);
868 bool no_mip
= first_level
== last_level
;
870 tex_resource_words
[4] |= S_030010_BASE_LEVEL(first_level
);
871 tex_resource_words
[5] |= S_030014_LAST_LEVEL(last_level
);
872 /* aniso max 16 samples */
873 tex_resource_words
[6] |= S_030018_MAX_ANISO_RATIO(no_mip
? 0 : 4);
876 tex_resource_words
[7] = S_03001C_DATA_FORMAT(format
) |
877 S_03001C_TYPE(V_03001C_SQ_TEX_VTX_VALID_TEXTURE
) |
878 S_03001C_BANK_WIDTH(bankw
) |
879 S_03001C_BANK_HEIGHT(bankh
) |
880 S_03001C_MACRO_TILE_ASPECT(macro_aspect
) |
881 S_03001C_NUM_BANKS(nbanks
) |
882 S_03001C_DEPTH_SAMPLE_ORDER(tmp
->db_compatible
);
886 struct pipe_sampler_view
*
887 evergreen_create_sampler_view_custom(struct pipe_context
*ctx
,
888 struct pipe_resource
*texture
,
889 const struct pipe_sampler_view
*state
,
890 unsigned width0
, unsigned height0
,
891 unsigned force_level
)
893 struct r600_context
*rctx
= (struct r600_context
*)ctx
;
894 struct r600_pipe_sampler_view
*view
= CALLOC_STRUCT(r600_pipe_sampler_view
);
895 struct r600_texture
*tmp
= (struct r600_texture
*)texture
;
896 struct eg_tex_res_params params
;
902 /* initialize base object */
904 view
->base
.texture
= NULL
;
905 pipe_reference(NULL
, &texture
->reference
);
906 view
->base
.texture
= texture
;
907 view
->base
.reference
.count
= 1;
908 view
->base
.context
= ctx
;
910 if (state
->target
== PIPE_BUFFER
)
911 return texture_buffer_sampler_view(rctx
, view
, width0
, height0
);
913 memset(¶ms
, 0, sizeof(params
));
914 params
.pipe_format
= state
->format
;
915 params
.force_level
= force_level
;
916 params
.width0
= width0
;
917 params
.height0
= height0
;
918 params
.first_level
= state
->u
.tex
.first_level
;
919 params
.last_level
= state
->u
.tex
.last_level
;
920 params
.first_layer
= state
->u
.tex
.first_layer
;
921 params
.last_layer
= state
->u
.tex
.last_layer
;
922 params
.target
= state
->target
;
923 params
.swizzle
[0] = state
->swizzle_r
;
924 params
.swizzle
[1] = state
->swizzle_g
;
925 params
.swizzle
[2] = state
->swizzle_b
;
926 params
.swizzle
[3] = state
->swizzle_a
;
928 ret
= evergreen_fill_tex_resource_words(rctx
, texture
, ¶ms
,
929 &view
->skip_mip_address_reloc
,
930 view
->tex_resource_words
);
936 if (state
->format
== PIPE_FORMAT_X24S8_UINT
||
937 state
->format
== PIPE_FORMAT_S8X24_UINT
||
938 state
->format
== PIPE_FORMAT_X32_S8X24_UINT
||
939 state
->format
== PIPE_FORMAT_S8_UINT
)
940 view
->is_stencil_sampler
= true;
942 view
->tex_resource
= &tmp
->resource
;
947 static struct pipe_sampler_view
*
948 evergreen_create_sampler_view(struct pipe_context
*ctx
,
949 struct pipe_resource
*tex
,
950 const struct pipe_sampler_view
*state
)
952 return evergreen_create_sampler_view_custom(ctx
, tex
, state
,
953 tex
->width0
, tex
->height0
, 0);
956 static void evergreen_emit_config_state(struct r600_context
*rctx
, struct r600_atom
*atom
)
958 struct radeon_winsys_cs
*cs
= rctx
->b
.gfx
.cs
;
959 struct r600_config_state
*a
= (struct r600_config_state
*)atom
;
961 radeon_set_config_reg_seq(cs
, R_008C04_SQ_GPR_RESOURCE_MGMT_1
, 3);
962 if (a
->dyn_gpr_enabled
) {
963 radeon_emit(cs
, S_008C04_NUM_CLAUSE_TEMP_GPRS(rctx
->r6xx_num_clause_temp_gprs
));
967 radeon_emit(cs
, a
->sq_gpr_resource_mgmt_1
);
968 radeon_emit(cs
, a
->sq_gpr_resource_mgmt_2
);
969 radeon_emit(cs
, a
->sq_gpr_resource_mgmt_3
);
971 radeon_set_config_reg(cs
, R_008D8C_SQ_DYN_GPR_CNTL_PS_FLUSH_REQ
, (a
->dyn_gpr_enabled
<< 8));
972 if (a
->dyn_gpr_enabled
) {
973 radeon_set_context_reg(cs
, R_028838_SQ_DYN_GPR_RESOURCE_LIMIT_1
,
974 S_028838_PS_GPRS(0x1e) |
975 S_028838_VS_GPRS(0x1e) |
976 S_028838_GS_GPRS(0x1e) |
977 S_028838_ES_GPRS(0x1e) |
978 S_028838_HS_GPRS(0x1e) |
979 S_028838_LS_GPRS(0x1e)); /* workaround for hw issues with dyn gpr - must set all limits to 240 instead of 0, 0x1e == 240 / 8*/
983 static void evergreen_emit_clip_state(struct r600_context
*rctx
, struct r600_atom
*atom
)
985 struct radeon_winsys_cs
*cs
= rctx
->b
.gfx
.cs
;
986 struct pipe_clip_state
*state
= &rctx
->clip_state
.state
;
988 radeon_set_context_reg_seq(cs
, R_0285BC_PA_CL_UCP0_X
, 6*4);
989 radeon_emit_array(cs
, (unsigned*)state
, 6*4);
992 static void evergreen_set_polygon_stipple(struct pipe_context
*ctx
,
993 const struct pipe_poly_stipple
*state
)
997 static void evergreen_get_scissor_rect(struct r600_context
*rctx
,
998 unsigned tl_x
, unsigned tl_y
, unsigned br_x
, unsigned br_y
,
999 uint32_t *tl
, uint32_t *br
)
1001 struct pipe_scissor_state scissor
= {tl_x
, tl_y
, br_x
, br_y
};
1003 evergreen_apply_scissor_bug_workaround(&rctx
->b
, &scissor
);
1005 *tl
= S_028240_TL_X(scissor
.minx
) | S_028240_TL_Y(scissor
.miny
);
1006 *br
= S_028244_BR_X(scissor
.maxx
) | S_028244_BR_Y(scissor
.maxy
);
1009 struct r600_tex_color_info
{
1018 unsigned fmask_slice
;
1020 boolean export_16bpc
;
1023 static void evergreen_set_color_surface_buffer(struct r600_context
*rctx
,
1024 struct r600_resource
*res
,
1025 enum pipe_format pformat
,
1026 unsigned first_element
,
1027 unsigned last_element
,
1028 struct r600_tex_color_info
*color
)
1030 unsigned format
, swap
, ntype
, endian
;
1031 const struct util_format_description
*desc
;
1032 unsigned block_size
= align(util_format_get_blocksize(res
->b
.b
.format
), 4);
1033 unsigned pitch_alignment
=
1034 MAX2(64, rctx
->screen
->b
.info
.pipe_interleave_bytes
/ block_size
);
1035 unsigned pitch
= align(res
->b
.b
.width0
, pitch_alignment
);
1037 unsigned width_elements
;
1039 width_elements
= last_element
- first_element
+ 1;
1041 format
= r600_translate_colorformat(rctx
->b
.chip_class
, pformat
, FALSE
);
1042 swap
= r600_translate_colorswap(pformat
, FALSE
);
1044 endian
= r600_colorformat_endian_swap(format
, FALSE
);
1046 desc
= util_format_description(pformat
);
1047 for (i
= 0; i
< 4; i
++) {
1048 if (desc
->channel
[i
].type
!= UTIL_FORMAT_TYPE_VOID
) {
1052 ntype
= V_028C70_NUMBER_UNORM
;
1053 if (desc
->colorspace
== UTIL_FORMAT_COLORSPACE_SRGB
)
1054 ntype
= V_028C70_NUMBER_SRGB
;
1055 else if (desc
->channel
[i
].type
== UTIL_FORMAT_TYPE_SIGNED
) {
1056 if (desc
->channel
[i
].normalized
)
1057 ntype
= V_028C70_NUMBER_SNORM
;
1058 else if (desc
->channel
[i
].pure_integer
)
1059 ntype
= V_028C70_NUMBER_SINT
;
1060 } else if (desc
->channel
[i
].type
== UTIL_FORMAT_TYPE_UNSIGNED
) {
1061 if (desc
->channel
[i
].normalized
)
1062 ntype
= V_028C70_NUMBER_UNORM
;
1063 else if (desc
->channel
[i
].pure_integer
)
1064 ntype
= V_028C70_NUMBER_UINT
;
1065 } else if (desc
->channel
[i
].type
== UTIL_FORMAT_TYPE_FLOAT
) {
1066 ntype
= V_028C70_NUMBER_FLOAT
;
1069 pitch
= (pitch
/ 8) - 1;
1070 color
->pitch
= S_028C64_PITCH_TILE_MAX(pitch
);
1072 color
->info
= S_028C70_ARRAY_MODE(V_028C70_ARRAY_LINEAR_ALIGNED
);
1073 color
->info
|= S_028C70_FORMAT(format
) |
1074 S_028C70_COMP_SWAP(swap
) |
1075 S_028C70_BLEND_CLAMP(0) |
1076 S_028C70_BLEND_BYPASS(1) |
1077 S_028C70_NUMBER_TYPE(ntype
) |
1078 S_028C70_ENDIAN(endian
);
1079 color
->attrib
= S_028C74_NON_DISP_TILING_ORDER(1);
1080 color
->ntype
= ntype
;
1081 color
->export_16bpc
= false;
1082 color
->dim
= width_elements
- 1;
1083 color
->slice
= 0; /* (width_elements / 64) - 1;*/
1085 color
->offset
= res
->gpu_address
>> 8;
1087 color
->fmask
= color
->offset
;
1088 color
->fmask_slice
= 0;
1091 static void evergreen_set_color_surface_common(struct r600_context
*rctx
,
1092 struct r600_texture
*rtex
,
1094 unsigned first_layer
,
1095 unsigned last_layer
,
1096 enum pipe_format pformat
,
1097 struct r600_tex_color_info
*color
)
1099 struct r600_screen
*rscreen
= rctx
->screen
;
1100 unsigned pitch
, slice
;
1101 unsigned non_disp_tiling
, macro_aspect
, tile_split
, bankh
, bankw
, fmask_bankh
, nbanks
;
1102 unsigned format
, swap
, ntype
, endian
;
1103 const struct util_format_description
*desc
;
1104 bool blend_clamp
= 0, blend_bypass
= 0, do_endian_swap
= FALSE
;
1107 color
->offset
= rtex
->surface
.u
.legacy
.level
[level
].offset
;
1108 color
->view
= S_028C6C_SLICE_START(first_layer
) |
1109 S_028C6C_SLICE_MAX(last_layer
);
1111 color
->offset
+= rtex
->resource
.gpu_address
;
1112 color
->offset
>>= 8;
1115 pitch
= (rtex
->surface
.u
.legacy
.level
[level
].nblk_x
) / 8 - 1;
1116 slice
= (rtex
->surface
.u
.legacy
.level
[level
].nblk_x
* rtex
->surface
.u
.legacy
.level
[level
].nblk_y
) / 64;
1122 switch (rtex
->surface
.u
.legacy
.level
[level
].mode
) {
1124 case RADEON_SURF_MODE_LINEAR_ALIGNED
:
1125 color
->info
= S_028C70_ARRAY_MODE(V_028C70_ARRAY_LINEAR_ALIGNED
);
1126 non_disp_tiling
= 1;
1128 case RADEON_SURF_MODE_1D
:
1129 color
->info
= S_028C70_ARRAY_MODE(V_028C70_ARRAY_1D_TILED_THIN1
);
1130 non_disp_tiling
= rtex
->non_disp_tiling
;
1132 case RADEON_SURF_MODE_2D
:
1133 color
->info
= S_028C70_ARRAY_MODE(V_028C70_ARRAY_2D_TILED_THIN1
);
1134 non_disp_tiling
= rtex
->non_disp_tiling
;
1137 tile_split
= rtex
->surface
.u
.legacy
.tile_split
;
1138 macro_aspect
= rtex
->surface
.u
.legacy
.mtilea
;
1139 bankw
= rtex
->surface
.u
.legacy
.bankw
;
1140 bankh
= rtex
->surface
.u
.legacy
.bankh
;
1141 if (rtex
->fmask
.size
)
1142 fmask_bankh
= rtex
->fmask
.bank_height
;
1144 fmask_bankh
= rtex
->surface
.u
.legacy
.bankh
;
1145 tile_split
= eg_tile_split(tile_split
);
1146 macro_aspect
= eg_macro_tile_aspect(macro_aspect
);
1147 bankw
= eg_bank_wh(bankw
);
1148 bankh
= eg_bank_wh(bankh
);
1149 fmask_bankh
= eg_bank_wh(fmask_bankh
);
1151 if (rscreen
->b
.chip_class
== CAYMAN
) {
1152 if (util_format_get_blocksize(pformat
) >= 16)
1153 non_disp_tiling
= 1;
1155 nbanks
= eg_num_banks(rscreen
->b
.info
.r600_num_banks
);
1156 desc
= util_format_description(pformat
);
1157 for (i
= 0; i
< 4; i
++) {
1158 if (desc
->channel
[i
].type
!= UTIL_FORMAT_TYPE_VOID
) {
1162 color
->attrib
= S_028C74_TILE_SPLIT(tile_split
)|
1163 S_028C74_NUM_BANKS(nbanks
) |
1164 S_028C74_BANK_WIDTH(bankw
) |
1165 S_028C74_BANK_HEIGHT(bankh
) |
1166 S_028C74_MACRO_TILE_ASPECT(macro_aspect
) |
1167 S_028C74_NON_DISP_TILING_ORDER(non_disp_tiling
) |
1168 S_028C74_FMASK_BANK_HEIGHT(fmask_bankh
);
1170 if (rctx
->b
.chip_class
== CAYMAN
) {
1171 color
->attrib
|= S_028C74_FORCE_DST_ALPHA_1(desc
->swizzle
[3] ==
1174 if (rtex
->resource
.b
.b
.nr_samples
> 1) {
1175 unsigned log_samples
= util_logbase2(rtex
->resource
.b
.b
.nr_samples
);
1176 color
->attrib
|= S_028C74_NUM_SAMPLES(log_samples
) |
1177 S_028C74_NUM_FRAGMENTS(log_samples
);
1181 ntype
= V_028C70_NUMBER_UNORM
;
1182 if (desc
->colorspace
== UTIL_FORMAT_COLORSPACE_SRGB
)
1183 ntype
= V_028C70_NUMBER_SRGB
;
1184 else if (desc
->channel
[i
].type
== UTIL_FORMAT_TYPE_SIGNED
) {
1185 if (desc
->channel
[i
].normalized
)
1186 ntype
= V_028C70_NUMBER_SNORM
;
1187 else if (desc
->channel
[i
].pure_integer
)
1188 ntype
= V_028C70_NUMBER_SINT
;
1189 } else if (desc
->channel
[i
].type
== UTIL_FORMAT_TYPE_UNSIGNED
) {
1190 if (desc
->channel
[i
].normalized
)
1191 ntype
= V_028C70_NUMBER_UNORM
;
1192 else if (desc
->channel
[i
].pure_integer
)
1193 ntype
= V_028C70_NUMBER_UINT
;
1194 } else if (desc
->channel
[i
].type
== UTIL_FORMAT_TYPE_FLOAT
) {
1195 ntype
= V_028C70_NUMBER_FLOAT
;
1198 if (R600_BIG_ENDIAN
)
1199 do_endian_swap
= !rtex
->db_compatible
;
1201 format
= r600_translate_colorformat(rctx
->b
.chip_class
, pformat
, do_endian_swap
);
1202 assert(format
!= ~0);
1203 swap
= r600_translate_colorswap(pformat
, do_endian_swap
);
1206 endian
= r600_colorformat_endian_swap(format
, do_endian_swap
);
1208 /* blend clamp should be set for all NORM/SRGB types */
1209 if (ntype
== V_028C70_NUMBER_UNORM
|| ntype
== V_028C70_NUMBER_SNORM
||
1210 ntype
== V_028C70_NUMBER_SRGB
)
1213 /* set blend bypass according to docs if SINT/UINT or
1214 8/24 COLOR variants */
1215 if (ntype
== V_028C70_NUMBER_UINT
|| ntype
== V_028C70_NUMBER_SINT
||
1216 format
== V_028C70_COLOR_8_24
|| format
== V_028C70_COLOR_24_8
||
1217 format
== V_028C70_COLOR_X24_8_32_FLOAT
) {
1222 color
->ntype
= ntype
;
1223 color
->info
|= S_028C70_FORMAT(format
) |
1224 S_028C70_COMP_SWAP(swap
) |
1225 S_028C70_BLEND_CLAMP(blend_clamp
) |
1226 S_028C70_BLEND_BYPASS(blend_bypass
) |
1227 S_028C70_SIMPLE_FLOAT(1) |
1228 S_028C70_NUMBER_TYPE(ntype
) |
1229 S_028C70_ENDIAN(endian
);
1231 if (rtex
->fmask
.size
) {
1232 color
->info
|= S_028C70_COMPRESSION(1);
1235 /* EXPORT_NORM is an optimzation that can be enabled for better
1236 * performance in certain cases.
1237 * EXPORT_NORM can be enabled if:
1238 * - 11-bit or smaller UNORM/SNORM/SRGB
1239 * - 16-bit or smaller FLOAT
1241 color
->export_16bpc
= false;
1242 if (desc
->colorspace
!= UTIL_FORMAT_COLORSPACE_ZS
&&
1243 ((desc
->channel
[i
].size
< 12 &&
1244 desc
->channel
[i
].type
!= UTIL_FORMAT_TYPE_FLOAT
&&
1245 ntype
!= V_028C70_NUMBER_UINT
&& ntype
!= V_028C70_NUMBER_SINT
) ||
1246 (desc
->channel
[i
].size
< 17 &&
1247 desc
->channel
[i
].type
== UTIL_FORMAT_TYPE_FLOAT
))) {
1248 color
->info
|= S_028C70_SOURCE_FORMAT(V_028C70_EXPORT_4C_16BPC
);
1249 color
->export_16bpc
= true;
1252 color
->pitch
= S_028C64_PITCH_TILE_MAX(pitch
);
1253 color
->slice
= S_028C68_SLICE_TILE_MAX(slice
);
1255 if (rtex
->fmask
.size
) {
1256 color
->fmask
= (rtex
->resource
.gpu_address
+ rtex
->fmask
.offset
) >> 8;
1257 color
->fmask_slice
= S_028C88_TILE_MAX(rtex
->fmask
.slice_tile_max
);
1259 color
->fmask
= color
->offset
;
1260 color
->fmask_slice
= S_028C88_TILE_MAX(slice
);
1265 * This function intializes the CB* register values for RATs. It is meant
1266 * to be used for 1D aligned buffers that do not have an associated
1269 void evergreen_init_color_surface_rat(struct r600_context
*rctx
,
1270 struct r600_surface
*surf
)
1272 struct pipe_resource
*pipe_buffer
= surf
->base
.texture
;
1273 struct r600_tex_color_info color
;
1275 evergreen_set_color_surface_buffer(rctx
, (struct r600_resource
*)surf
->base
.texture
,
1276 surf
->base
.format
, 0, pipe_buffer
->width0
,
1279 surf
->cb_color_base
= color
.offset
;
1280 surf
->cb_color_dim
= color
.dim
;
1281 surf
->cb_color_info
= color
.info
| S_028C70_RAT(1);
1282 surf
->cb_color_pitch
= color
.pitch
;
1283 surf
->cb_color_slice
= color
.slice
;
1284 surf
->cb_color_view
= color
.view
;
1285 surf
->cb_color_attrib
= color
.attrib
;
1286 surf
->cb_color_fmask
= color
.fmask
;
1287 surf
->cb_color_fmask_slice
= color
.fmask_slice
;
1289 surf
->cb_color_view
= 0;
1291 /* Set the buffer range the GPU will have access to: */
1292 util_range_add(&r600_resource(pipe_buffer
)->valid_buffer_range
,
1293 0, pipe_buffer
->width0
);
1297 void evergreen_init_color_surface(struct r600_context
*rctx
,
1298 struct r600_surface
*surf
)
1300 struct r600_texture
*rtex
= (struct r600_texture
*)surf
->base
.texture
;
1301 unsigned level
= surf
->base
.u
.tex
.level
;
1302 struct r600_tex_color_info color
;
1304 evergreen_set_color_surface_common(rctx
, rtex
, level
,
1305 surf
->base
.u
.tex
.first_layer
,
1306 surf
->base
.u
.tex
.last_layer
,
1310 surf
->alphatest_bypass
= color
.ntype
== V_028C70_NUMBER_UINT
||
1311 color
.ntype
== V_028C70_NUMBER_SINT
;
1312 surf
->export_16bpc
= color
.export_16bpc
;
1314 /* XXX handle enabling of CB beyond BASE8 which has different offset */
1315 surf
->cb_color_base
= color
.offset
;
1316 surf
->cb_color_dim
= color
.dim
;
1317 surf
->cb_color_info
= color
.info
;
1318 surf
->cb_color_pitch
= color
.pitch
;
1319 surf
->cb_color_slice
= color
.slice
;
1320 surf
->cb_color_view
= color
.view
;
1321 surf
->cb_color_attrib
= color
.attrib
;
1322 surf
->cb_color_fmask
= color
.fmask
;
1323 surf
->cb_color_fmask_slice
= color
.fmask_slice
;
1325 surf
->color_initialized
= true;
1328 static void evergreen_init_depth_surface(struct r600_context
*rctx
,
1329 struct r600_surface
*surf
)
1331 struct r600_screen
*rscreen
= rctx
->screen
;
1332 struct r600_texture
*rtex
= (struct r600_texture
*)surf
->base
.texture
;
1333 unsigned level
= surf
->base
.u
.tex
.level
;
1334 struct legacy_surf_level
*levelinfo
= &rtex
->surface
.u
.legacy
.level
[level
];
1336 unsigned format
, array_mode
;
1337 unsigned macro_aspect
, tile_split
, bankh
, bankw
, nbanks
;
1340 format
= r600_translate_dbformat(surf
->base
.format
);
1341 assert(format
!= ~0);
1343 offset
= rtex
->resource
.gpu_address
;
1344 offset
+= rtex
->surface
.u
.legacy
.level
[level
].offset
;
1346 switch (rtex
->surface
.u
.legacy
.level
[level
].mode
) {
1347 case RADEON_SURF_MODE_2D
:
1348 array_mode
= V_028C70_ARRAY_2D_TILED_THIN1
;
1350 case RADEON_SURF_MODE_1D
:
1351 case RADEON_SURF_MODE_LINEAR_ALIGNED
:
1353 array_mode
= V_028C70_ARRAY_1D_TILED_THIN1
;
1356 tile_split
= rtex
->surface
.u
.legacy
.tile_split
;
1357 macro_aspect
= rtex
->surface
.u
.legacy
.mtilea
;
1358 bankw
= rtex
->surface
.u
.legacy
.bankw
;
1359 bankh
= rtex
->surface
.u
.legacy
.bankh
;
1360 tile_split
= eg_tile_split(tile_split
);
1361 macro_aspect
= eg_macro_tile_aspect(macro_aspect
);
1362 bankw
= eg_bank_wh(bankw
);
1363 bankh
= eg_bank_wh(bankh
);
1364 nbanks
= eg_num_banks(rscreen
->b
.info
.r600_num_banks
);
1367 surf
->db_z_info
= S_028040_ARRAY_MODE(array_mode
) |
1368 S_028040_FORMAT(format
) |
1369 S_028040_TILE_SPLIT(tile_split
)|
1370 S_028040_NUM_BANKS(nbanks
) |
1371 S_028040_BANK_WIDTH(bankw
) |
1372 S_028040_BANK_HEIGHT(bankh
) |
1373 S_028040_MACRO_TILE_ASPECT(macro_aspect
);
1374 if (rscreen
->b
.chip_class
== CAYMAN
&& rtex
->resource
.b
.b
.nr_samples
> 1) {
1375 surf
->db_z_info
|= S_028040_NUM_SAMPLES(util_logbase2(rtex
->resource
.b
.b
.nr_samples
));
1378 assert(levelinfo
->nblk_x
% 8 == 0 && levelinfo
->nblk_y
% 8 == 0);
1380 surf
->db_depth_base
= offset
;
1381 surf
->db_depth_view
= S_028008_SLICE_START(surf
->base
.u
.tex
.first_layer
) |
1382 S_028008_SLICE_MAX(surf
->base
.u
.tex
.last_layer
);
1383 surf
->db_depth_size
= S_028058_PITCH_TILE_MAX(levelinfo
->nblk_x
/ 8 - 1) |
1384 S_028058_HEIGHT_TILE_MAX(levelinfo
->nblk_y
/ 8 - 1);
1385 surf
->db_depth_slice
= S_02805C_SLICE_TILE_MAX(levelinfo
->nblk_x
*
1386 levelinfo
->nblk_y
/ 64 - 1);
1388 if (rtex
->surface
.has_stencil
) {
1389 uint64_t stencil_offset
;
1390 unsigned stile_split
= rtex
->surface
.u
.legacy
.stencil_tile_split
;
1392 stile_split
= eg_tile_split(stile_split
);
1394 stencil_offset
= rtex
->surface
.u
.legacy
.stencil_level
[level
].offset
;
1395 stencil_offset
+= rtex
->resource
.gpu_address
;
1397 surf
->db_stencil_base
= stencil_offset
>> 8;
1398 surf
->db_stencil_info
= S_028044_FORMAT(V_028044_STENCIL_8
) |
1399 S_028044_TILE_SPLIT(stile_split
);
1401 surf
->db_stencil_base
= offset
;
1402 /* DRM 2.6.18 allows the INVALID format to disable stencil.
1403 * Older kernels are out of luck. */
1404 surf
->db_stencil_info
= rctx
->screen
->b
.info
.drm_minor
>= 18 ?
1405 S_028044_FORMAT(V_028044_STENCIL_INVALID
) :
1406 S_028044_FORMAT(V_028044_STENCIL_8
);
1409 if (r600_htile_enabled(rtex
, level
)) {
1410 uint64_t va
= rtex
->resource
.gpu_address
+ rtex
->htile_offset
;
1411 surf
->db_htile_data_base
= va
>> 8;
1412 surf
->db_htile_surface
= S_028ABC_HTILE_WIDTH(1) |
1413 S_028ABC_HTILE_HEIGHT(1) |
1414 S_028ABC_FULL_CACHE(1);
1415 surf
->db_z_info
|= S_028040_TILE_SURFACE_ENABLE(1);
1416 surf
->db_preload_control
= 0;
1419 surf
->depth_initialized
= true;
1422 static void evergreen_set_framebuffer_state(struct pipe_context
*ctx
,
1423 const struct pipe_framebuffer_state
*state
)
1425 struct r600_context
*rctx
= (struct r600_context
*)ctx
;
1426 struct r600_surface
*surf
;
1427 struct r600_texture
*rtex
;
1428 uint32_t i
, log_samples
;
1430 /* Flush TC when changing the framebuffer state, because the only
1431 * client not using TC that can change textures is the framebuffer.
1432 * Other places don't typically have to flush TC.
1434 rctx
->b
.flags
|= R600_CONTEXT_WAIT_3D_IDLE
|
1435 R600_CONTEXT_FLUSH_AND_INV
|
1436 R600_CONTEXT_FLUSH_AND_INV_CB
|
1437 R600_CONTEXT_FLUSH_AND_INV_CB_META
|
1438 R600_CONTEXT_FLUSH_AND_INV_DB
|
1439 R600_CONTEXT_FLUSH_AND_INV_DB_META
|
1440 R600_CONTEXT_INV_TEX_CACHE
;
1442 util_copy_framebuffer_state(&rctx
->framebuffer
.state
, state
);
1445 rctx
->framebuffer
.export_16bpc
= state
->nr_cbufs
!= 0;
1446 rctx
->framebuffer
.cb0_is_integer
= state
->nr_cbufs
&& state
->cbufs
[0] &&
1447 util_format_is_pure_integer(state
->cbufs
[0]->format
);
1448 rctx
->framebuffer
.compressed_cb_mask
= 0;
1449 rctx
->framebuffer
.nr_samples
= util_framebuffer_get_num_samples(state
);
1451 for (i
= 0; i
< state
->nr_cbufs
; i
++) {
1452 surf
= (struct r600_surface
*)state
->cbufs
[i
];
1456 rtex
= (struct r600_texture
*)surf
->base
.texture
;
1458 r600_context_add_resource_size(ctx
, state
->cbufs
[i
]->texture
);
1460 if (!surf
->color_initialized
) {
1461 evergreen_init_color_surface(rctx
, surf
);
1464 if (!surf
->export_16bpc
) {
1465 rctx
->framebuffer
.export_16bpc
= false;
1468 if (rtex
->fmask
.size
) {
1469 rctx
->framebuffer
.compressed_cb_mask
|= 1 << i
;
1473 /* Update alpha-test state dependencies.
1474 * Alpha-test is done on the first colorbuffer only. */
1475 if (state
->nr_cbufs
) {
1476 bool alphatest_bypass
= false;
1477 bool export_16bpc
= true;
1479 surf
= (struct r600_surface
*)state
->cbufs
[0];
1481 alphatest_bypass
= surf
->alphatest_bypass
;
1482 export_16bpc
= surf
->export_16bpc
;
1485 if (rctx
->alphatest_state
.bypass
!= alphatest_bypass
) {
1486 rctx
->alphatest_state
.bypass
= alphatest_bypass
;
1487 r600_mark_atom_dirty(rctx
, &rctx
->alphatest_state
.atom
);
1489 if (rctx
->alphatest_state
.cb0_export_16bpc
!= export_16bpc
) {
1490 rctx
->alphatest_state
.cb0_export_16bpc
= export_16bpc
;
1491 r600_mark_atom_dirty(rctx
, &rctx
->alphatest_state
.atom
);
1497 surf
= (struct r600_surface
*)state
->zsbuf
;
1499 r600_context_add_resource_size(ctx
, state
->zsbuf
->texture
);
1501 if (!surf
->depth_initialized
) {
1502 evergreen_init_depth_surface(rctx
, surf
);
1505 if (state
->zsbuf
->format
!= rctx
->poly_offset_state
.zs_format
) {
1506 rctx
->poly_offset_state
.zs_format
= state
->zsbuf
->format
;
1507 r600_mark_atom_dirty(rctx
, &rctx
->poly_offset_state
.atom
);
1510 if (rctx
->db_state
.rsurf
!= surf
) {
1511 rctx
->db_state
.rsurf
= surf
;
1512 r600_mark_atom_dirty(rctx
, &rctx
->db_state
.atom
);
1513 r600_mark_atom_dirty(rctx
, &rctx
->db_misc_state
.atom
);
1515 } else if (rctx
->db_state
.rsurf
) {
1516 rctx
->db_state
.rsurf
= NULL
;
1517 r600_mark_atom_dirty(rctx
, &rctx
->db_state
.atom
);
1518 r600_mark_atom_dirty(rctx
, &rctx
->db_misc_state
.atom
);
1521 if (rctx
->cb_misc_state
.nr_cbufs
!= state
->nr_cbufs
) {
1522 rctx
->cb_misc_state
.nr_cbufs
= state
->nr_cbufs
;
1523 r600_mark_atom_dirty(rctx
, &rctx
->cb_misc_state
.atom
);
1526 if (state
->nr_cbufs
== 0 && rctx
->alphatest_state
.bypass
) {
1527 rctx
->alphatest_state
.bypass
= false;
1528 r600_mark_atom_dirty(rctx
, &rctx
->alphatest_state
.atom
);
1531 log_samples
= util_logbase2(rctx
->framebuffer
.nr_samples
);
1532 /* This is for Cayman to program SAMPLE_RATE, and for RV770 to fix a hw bug. */
1533 if ((rctx
->b
.chip_class
== CAYMAN
||
1534 rctx
->b
.family
== CHIP_RV770
) &&
1535 rctx
->db_misc_state
.log_samples
!= log_samples
) {
1536 rctx
->db_misc_state
.log_samples
= log_samples
;
1537 r600_mark_atom_dirty(rctx
, &rctx
->db_misc_state
.atom
);
1541 /* Calculate the CS size. */
1542 rctx
->framebuffer
.atom
.num_dw
= 4; /* SCISSOR */
1545 if (rctx
->b
.chip_class
== EVERGREEN
)
1546 rctx
->framebuffer
.atom
.num_dw
+= 17; /* Evergreen */
1548 rctx
->framebuffer
.atom
.num_dw
+= 28; /* Cayman */
1551 rctx
->framebuffer
.atom
.num_dw
+= state
->nr_cbufs
* 23;
1552 rctx
->framebuffer
.atom
.num_dw
+= state
->nr_cbufs
* 2;
1553 rctx
->framebuffer
.atom
.num_dw
+= (12 - state
->nr_cbufs
) * 3;
1557 rctx
->framebuffer
.atom
.num_dw
+= 24;
1558 rctx
->framebuffer
.atom
.num_dw
+= 2;
1559 } else if (rctx
->screen
->b
.info
.drm_minor
>= 18) {
1560 rctx
->framebuffer
.atom
.num_dw
+= 4;
1563 r600_mark_atom_dirty(rctx
, &rctx
->framebuffer
.atom
);
1565 r600_set_sample_locations_constant_buffer(rctx
);
1566 rctx
->framebuffer
.do_update_surf_dirtiness
= true;
1569 static void evergreen_set_min_samples(struct pipe_context
*ctx
, unsigned min_samples
)
1571 struct r600_context
*rctx
= (struct r600_context
*)ctx
;
1573 if (rctx
->ps_iter_samples
== min_samples
)
1576 rctx
->ps_iter_samples
= min_samples
;
1577 if (rctx
->framebuffer
.nr_samples
> 1) {
1578 r600_mark_atom_dirty(rctx
, &rctx
->framebuffer
.atom
);
1583 static uint32_t sample_locs_8x
[] = {
1584 FILL_SREG(-1, 1, 1, 5, 3, -5, 5, 3),
1585 FILL_SREG(-7, -1, -3, -7, 7, -3, -5, 7),
1586 FILL_SREG(-1, 1, 1, 5, 3, -5, 5, 3),
1587 FILL_SREG(-7, -1, -3, -7, 7, -3, -5, 7),
1588 FILL_SREG(-1, 1, 1, 5, 3, -5, 5, 3),
1589 FILL_SREG(-7, -1, -3, -7, 7, -3, -5, 7),
1590 FILL_SREG(-1, 1, 1, 5, 3, -5, 5, 3),
1591 FILL_SREG(-7, -1, -3, -7, 7, -3, -5, 7),
1593 static unsigned max_dist_8x
= 7;
1595 static void evergreen_get_sample_position(struct pipe_context
*ctx
,
1596 unsigned sample_count
,
1597 unsigned sample_index
,
1604 switch (sample_count
) {
1607 out_value
[0] = out_value
[1] = 0.5;
1610 offset
= 4 * (sample_index
* 2);
1611 val
.idx
= (eg_sample_locs_2x
[0] >> offset
) & 0xf;
1612 out_value
[0] = (float)(val
.idx
+ 8) / 16.0f
;
1613 val
.idx
= (eg_sample_locs_2x
[0] >> (offset
+ 4)) & 0xf;
1614 out_value
[1] = (float)(val
.idx
+ 8) / 16.0f
;
1617 offset
= 4 * (sample_index
* 2);
1618 val
.idx
= (eg_sample_locs_4x
[0] >> offset
) & 0xf;
1619 out_value
[0] = (float)(val
.idx
+ 8) / 16.0f
;
1620 val
.idx
= (eg_sample_locs_4x
[0] >> (offset
+ 4)) & 0xf;
1621 out_value
[1] = (float)(val
.idx
+ 8) / 16.0f
;
1624 offset
= 4 * (sample_index
% 4 * 2);
1625 index
= (sample_index
/ 4);
1626 val
.idx
= (sample_locs_8x
[index
] >> offset
) & 0xf;
1627 out_value
[0] = (float)(val
.idx
+ 8) / 16.0f
;
1628 val
.idx
= (sample_locs_8x
[index
] >> (offset
+ 4)) & 0xf;
1629 out_value
[1] = (float)(val
.idx
+ 8) / 16.0f
;
1634 static void evergreen_emit_msaa_state(struct r600_context
*rctx
, int nr_samples
, int ps_iter_samples
)
1637 struct radeon_winsys_cs
*cs
= rctx
->b
.gfx
.cs
;
1638 unsigned max_dist
= 0;
1640 switch (nr_samples
) {
1645 radeon_set_context_reg_seq(cs
, R_028C1C_PA_SC_AA_SAMPLE_LOCS_0
, ARRAY_SIZE(eg_sample_locs_2x
));
1646 radeon_emit_array(cs
, eg_sample_locs_2x
, ARRAY_SIZE(eg_sample_locs_2x
));
1647 max_dist
= eg_max_dist_2x
;
1650 radeon_set_context_reg_seq(cs
, R_028C1C_PA_SC_AA_SAMPLE_LOCS_0
, ARRAY_SIZE(eg_sample_locs_4x
));
1651 radeon_emit_array(cs
, eg_sample_locs_4x
, ARRAY_SIZE(eg_sample_locs_4x
));
1652 max_dist
= eg_max_dist_4x
;
1655 radeon_set_context_reg_seq(cs
, R_028C1C_PA_SC_AA_SAMPLE_LOCS_0
, ARRAY_SIZE(sample_locs_8x
));
1656 radeon_emit_array(cs
, sample_locs_8x
, ARRAY_SIZE(sample_locs_8x
));
1657 max_dist
= max_dist_8x
;
1661 if (nr_samples
> 1) {
1662 radeon_set_context_reg_seq(cs
, R_028C00_PA_SC_LINE_CNTL
, 2);
1663 radeon_emit(cs
, S_028C00_LAST_PIXEL(1) |
1664 S_028C00_EXPAND_LINE_WIDTH(1)); /* R_028C00_PA_SC_LINE_CNTL */
1665 radeon_emit(cs
, S_028C04_MSAA_NUM_SAMPLES(util_logbase2(nr_samples
)) |
1666 S_028C04_MAX_SAMPLE_DIST(max_dist
)); /* R_028C04_PA_SC_AA_CONFIG */
1667 radeon_set_context_reg(cs
, R_028A4C_PA_SC_MODE_CNTL_1
,
1668 EG_S_028A4C_PS_ITER_SAMPLE(ps_iter_samples
> 1) |
1669 EG_S_028A4C_FORCE_EOV_CNTDWN_ENABLE(1) |
1670 EG_S_028A4C_FORCE_EOV_REZ_ENABLE(1));
1672 radeon_set_context_reg_seq(cs
, R_028C00_PA_SC_LINE_CNTL
, 2);
1673 radeon_emit(cs
, S_028C00_LAST_PIXEL(1)); /* R_028C00_PA_SC_LINE_CNTL */
1674 radeon_emit(cs
, 0); /* R_028C04_PA_SC_AA_CONFIG */
1675 radeon_set_context_reg(cs
, R_028A4C_PA_SC_MODE_CNTL_1
,
1676 EG_S_028A4C_FORCE_EOV_CNTDWN_ENABLE(1) |
1677 EG_S_028A4C_FORCE_EOV_REZ_ENABLE(1));
1681 static void evergreen_emit_image_state(struct r600_context
*rctx
, struct r600_atom
*atom
,
1682 int immed_id_base
, int res_id_base
)
1684 struct r600_image_state
*state
= (struct r600_image_state
*)atom
;
1685 struct pipe_framebuffer_state
*fb_state
= &rctx
->framebuffer
.state
;
1686 struct radeon_winsys_cs
*cs
= rctx
->b
.gfx
.cs
;
1687 struct r600_texture
*rtex
;
1688 struct r600_resource
*resource
;
1689 uint32_t pkt_flags
= 0;
1692 for (i
= 0; i
< R600_MAX_IMAGES
; i
++) {
1693 struct r600_image_view
*image
= &state
->views
[i
];
1694 unsigned reloc
, immed_reloc
;
1697 idx
+= fb_state
->nr_cbufs
+ (rctx
->dual_src_blend
? 1 : 0);
1698 if (!image
->base
.resource
)
1701 resource
= (struct r600_resource
*)image
->base
.resource
;
1702 if (resource
->b
.b
.target
!= PIPE_BUFFER
)
1703 rtex
= (struct r600_texture
*)image
->base
.resource
;
1707 reloc
= radeon_add_to_buffer_list(&rctx
->b
,
1710 RADEON_USAGE_READWRITE
,
1711 RADEON_PRIO_SHADER_RW_BUFFER
);
1713 immed_reloc
= radeon_add_to_buffer_list(&rctx
->b
,
1715 resource
->immed_buffer
,
1716 RADEON_USAGE_READWRITE
,
1717 RADEON_PRIO_SHADER_RW_BUFFER
);
1719 radeon_set_context_reg_seq(cs
, R_028C60_CB_COLOR0_BASE
+ idx
* 0x3C, 13);
1721 radeon_emit(cs
, image
->cb_color_base
); /* R_028C60_CB_COLOR0_BASE */
1722 radeon_emit(cs
, image
->cb_color_pitch
); /* R_028C64_CB_COLOR0_PITCH */
1723 radeon_emit(cs
, image
->cb_color_slice
); /* R_028C68_CB_COLOR0_SLICE */
1724 radeon_emit(cs
, image
->cb_color_view
); /* R_028C6C_CB_COLOR0_VIEW */
1725 radeon_emit(cs
, image
->cb_color_info
); /* R_028C70_CB_COLOR0_INFO */
1726 radeon_emit(cs
, image
->cb_color_attrib
); /* R_028C74_CB_COLOR0_ATTRIB */
1727 radeon_emit(cs
, image
->cb_color_dim
); /* R_028C78_CB_COLOR0_DIM */
1728 radeon_emit(cs
, rtex
? rtex
->cmask
.base_address_reg
: image
->cb_color_base
); /* R_028C7C_CB_COLOR0_CMASK */
1729 radeon_emit(cs
, rtex
? rtex
->cmask
.slice_tile_max
: 0); /* R_028C80_CB_COLOR0_CMASK_SLICE */
1730 radeon_emit(cs
, image
->cb_color_fmask
); /* R_028C84_CB_COLOR0_FMASK */
1731 radeon_emit(cs
, image
->cb_color_fmask_slice
); /* R_028C88_CB_COLOR0_FMASK_SLICE */
1732 radeon_emit(cs
, rtex
? rtex
->color_clear_value
[0] : 0); /* R_028C8C_CB_COLOR0_CLEAR_WORD0 */
1733 radeon_emit(cs
, rtex
? rtex
->color_clear_value
[1] : 0); /* R_028C90_CB_COLOR0_CLEAR_WORD1 */
1735 radeon_emit(cs
, PKT3(PKT3_NOP
, 0, 0)); /* R_028C60_CB_COLOR0_BASE */
1736 radeon_emit(cs
, reloc
);
1738 radeon_emit(cs
, PKT3(PKT3_NOP
, 0, 0)); /* R_028C74_CB_COLOR0_ATTRIB */
1739 radeon_emit(cs
, reloc
);
1741 radeon_emit(cs
, PKT3(PKT3_NOP
, 0, 0)); /* R_028C7C_CB_COLOR0_CMASK */
1742 radeon_emit(cs
, reloc
);
1744 radeon_emit(cs
, PKT3(PKT3_NOP
, 0, 0)); /* R_028C84_CB_COLOR0_FMASK */
1745 radeon_emit(cs
, reloc
);
1747 radeon_set_context_reg(cs
, R_028B9C_CB_IMMED0_BASE
+ (idx
* 4), resource
->immed_buffer
->gpu_address
>> 8);
1748 radeon_emit(cs
, PKT3(PKT3_NOP
, 0, 0)); /**/
1749 radeon_emit(cs
, immed_reloc
);
1751 radeon_emit(cs
, PKT3(PKT3_SET_RESOURCE
, 8, 0) | pkt_flags
);
1752 radeon_emit(cs
, (immed_id_base
+ i
) * 8);
1753 radeon_emit_array(cs
, image
->immed_resource_words
, 8);
1755 radeon_emit(cs
, PKT3(PKT3_NOP
, 0, 0) | pkt_flags
);
1756 radeon_emit(cs
, immed_reloc
);
1758 radeon_emit(cs
, PKT3(PKT3_SET_RESOURCE
, 8, 0) | pkt_flags
);
1759 radeon_emit(cs
, (res_id_base
+ i
) * 8);
1760 radeon_emit_array(cs
, image
->resource_words
, 8);
1762 radeon_emit(cs
, PKT3(PKT3_NOP
, 0, 0) | pkt_flags
);
1763 radeon_emit(cs
, reloc
);
1765 if (!image
->skip_mip_address_reloc
) {
1766 radeon_emit(cs
, PKT3(PKT3_NOP
, 0, 0) | pkt_flags
);
1767 radeon_emit(cs
, reloc
);
1772 static void evergreen_emit_fragment_image_state(struct r600_context
*rctx
, struct r600_atom
*atom
)
1774 evergreen_emit_image_state(rctx
, atom
,
1775 R600_IMAGE_IMMED_RESOURCE_OFFSET
,
1776 R600_IMAGE_REAL_RESOURCE_OFFSET
);
1779 static void evergreen_emit_framebuffer_state(struct r600_context
*rctx
, struct r600_atom
*atom
)
1781 struct radeon_winsys_cs
*cs
= rctx
->b
.gfx
.cs
;
1782 struct pipe_framebuffer_state
*state
= &rctx
->framebuffer
.state
;
1783 unsigned nr_cbufs
= state
->nr_cbufs
;
1785 struct r600_texture
*tex
= NULL
;
1786 struct r600_surface
*cb
= NULL
;
1788 /* XXX support more colorbuffers once we need them */
1789 assert(nr_cbufs
<= 8);
1794 for (i
= 0; i
< nr_cbufs
; i
++) {
1795 unsigned reloc
, cmask_reloc
;
1797 cb
= (struct r600_surface
*)state
->cbufs
[i
];
1799 radeon_set_context_reg(cs
, R_028C70_CB_COLOR0_INFO
+ i
* 0x3C,
1800 S_028C70_FORMAT(V_028C70_COLOR_INVALID
));
1804 tex
= (struct r600_texture
*)cb
->base
.texture
;
1805 reloc
= radeon_add_to_buffer_list(&rctx
->b
,
1807 (struct r600_resource
*)cb
->base
.texture
,
1808 RADEON_USAGE_READWRITE
,
1809 tex
->resource
.b
.b
.nr_samples
> 1 ?
1810 RADEON_PRIO_COLOR_BUFFER_MSAA
:
1811 RADEON_PRIO_COLOR_BUFFER
);
1813 if (tex
->cmask_buffer
&& tex
->cmask_buffer
!= &tex
->resource
) {
1814 cmask_reloc
= radeon_add_to_buffer_list(&rctx
->b
, &rctx
->b
.gfx
,
1815 tex
->cmask_buffer
, RADEON_USAGE_READWRITE
,
1818 cmask_reloc
= reloc
;
1821 radeon_set_context_reg_seq(cs
, R_028C60_CB_COLOR0_BASE
+ i
* 0x3C, 13);
1822 radeon_emit(cs
, cb
->cb_color_base
); /* R_028C60_CB_COLOR0_BASE */
1823 radeon_emit(cs
, cb
->cb_color_pitch
); /* R_028C64_CB_COLOR0_PITCH */
1824 radeon_emit(cs
, cb
->cb_color_slice
); /* R_028C68_CB_COLOR0_SLICE */
1825 radeon_emit(cs
, cb
->cb_color_view
); /* R_028C6C_CB_COLOR0_VIEW */
1826 radeon_emit(cs
, cb
->cb_color_info
| tex
->cb_color_info
); /* R_028C70_CB_COLOR0_INFO */
1827 radeon_emit(cs
, cb
->cb_color_attrib
); /* R_028C74_CB_COLOR0_ATTRIB */
1828 radeon_emit(cs
, cb
->cb_color_dim
); /* R_028C78_CB_COLOR0_DIM */
1829 radeon_emit(cs
, tex
->cmask
.base_address_reg
); /* R_028C7C_CB_COLOR0_CMASK */
1830 radeon_emit(cs
, tex
->cmask
.slice_tile_max
); /* R_028C80_CB_COLOR0_CMASK_SLICE */
1831 radeon_emit(cs
, cb
->cb_color_fmask
); /* R_028C84_CB_COLOR0_FMASK */
1832 radeon_emit(cs
, cb
->cb_color_fmask_slice
); /* R_028C88_CB_COLOR0_FMASK_SLICE */
1833 radeon_emit(cs
, tex
->color_clear_value
[0]); /* R_028C8C_CB_COLOR0_CLEAR_WORD0 */
1834 radeon_emit(cs
, tex
->color_clear_value
[1]); /* R_028C90_CB_COLOR0_CLEAR_WORD1 */
1836 radeon_emit(cs
, PKT3(PKT3_NOP
, 0, 0)); /* R_028C60_CB_COLOR0_BASE */
1837 radeon_emit(cs
, reloc
);
1839 radeon_emit(cs
, PKT3(PKT3_NOP
, 0, 0)); /* R_028C74_CB_COLOR0_ATTRIB */
1840 radeon_emit(cs
, reloc
);
1842 radeon_emit(cs
, PKT3(PKT3_NOP
, 0, 0)); /* R_028C7C_CB_COLOR0_CMASK */
1843 radeon_emit(cs
, cmask_reloc
);
1845 radeon_emit(cs
, PKT3(PKT3_NOP
, 0, 0)); /* R_028C84_CB_COLOR0_FMASK */
1846 radeon_emit(cs
, reloc
);
1848 /* set CB_COLOR1_INFO for possible dual-src blending */
1849 if (rctx
->framebuffer
.dual_src_blend
&& i
== 1 && state
->cbufs
[0]) {
1850 radeon_set_context_reg(cs
, R_028C70_CB_COLOR0_INFO
+ 1 * 0x3C,
1851 cb
->cb_color_info
| tex
->cb_color_info
);
1854 i
+= util_bitcount(rctx
->fragment_images
.enabled_mask
);
1856 radeon_set_context_reg(cs
, R_028C70_CB_COLOR0_INFO
+ i
* 0x3C, 0);
1858 radeon_set_context_reg(cs
, R_028E50_CB_COLOR8_INFO
+ (i
- 8) * 0x1C, 0);
1862 struct r600_surface
*zb
= (struct r600_surface
*)state
->zsbuf
;
1863 unsigned reloc
= radeon_add_to_buffer_list(&rctx
->b
,
1865 (struct r600_resource
*)state
->zsbuf
->texture
,
1866 RADEON_USAGE_READWRITE
,
1867 zb
->base
.texture
->nr_samples
> 1 ?
1868 RADEON_PRIO_DEPTH_BUFFER_MSAA
:
1869 RADEON_PRIO_DEPTH_BUFFER
);
1871 radeon_set_context_reg(cs
, R_028008_DB_DEPTH_VIEW
, zb
->db_depth_view
);
1873 radeon_set_context_reg_seq(cs
, R_028040_DB_Z_INFO
, 8);
1874 radeon_emit(cs
, zb
->db_z_info
); /* R_028040_DB_Z_INFO */
1875 radeon_emit(cs
, zb
->db_stencil_info
); /* R_028044_DB_STENCIL_INFO */
1876 radeon_emit(cs
, zb
->db_depth_base
); /* R_028048_DB_Z_READ_BASE */
1877 radeon_emit(cs
, zb
->db_stencil_base
); /* R_02804C_DB_STENCIL_READ_BASE */
1878 radeon_emit(cs
, zb
->db_depth_base
); /* R_028050_DB_Z_WRITE_BASE */
1879 radeon_emit(cs
, zb
->db_stencil_base
); /* R_028054_DB_STENCIL_WRITE_BASE */
1880 radeon_emit(cs
, zb
->db_depth_size
); /* R_028058_DB_DEPTH_SIZE */
1881 radeon_emit(cs
, zb
->db_depth_slice
); /* R_02805C_DB_DEPTH_SLICE */
1883 radeon_emit(cs
, PKT3(PKT3_NOP
, 0, 0)); /* R_028048_DB_Z_READ_BASE */
1884 radeon_emit(cs
, reloc
);
1886 radeon_emit(cs
, PKT3(PKT3_NOP
, 0, 0)); /* R_02804C_DB_STENCIL_READ_BASE */
1887 radeon_emit(cs
, reloc
);
1889 radeon_emit(cs
, PKT3(PKT3_NOP
, 0, 0)); /* R_028050_DB_Z_WRITE_BASE */
1890 radeon_emit(cs
, reloc
);
1892 radeon_emit(cs
, PKT3(PKT3_NOP
, 0, 0)); /* R_028054_DB_STENCIL_WRITE_BASE */
1893 radeon_emit(cs
, reloc
);
1894 } else if (rctx
->screen
->b
.info
.drm_minor
>= 18) {
1895 /* DRM 2.6.18 allows the INVALID format to disable depth/stencil.
1896 * Older kernels are out of luck. */
1897 radeon_set_context_reg_seq(cs
, R_028040_DB_Z_INFO
, 2);
1898 radeon_emit(cs
, S_028040_FORMAT(V_028040_Z_INVALID
)); /* R_028040_DB_Z_INFO */
1899 radeon_emit(cs
, S_028044_FORMAT(V_028044_STENCIL_INVALID
)); /* R_028044_DB_STENCIL_INFO */
1902 /* Framebuffer dimensions. */
1903 evergreen_get_scissor_rect(rctx
, 0, 0, state
->width
, state
->height
, &tl
, &br
);
1905 radeon_set_context_reg_seq(cs
, R_028204_PA_SC_WINDOW_SCISSOR_TL
, 2);
1906 radeon_emit(cs
, tl
); /* R_028204_PA_SC_WINDOW_SCISSOR_TL */
1907 radeon_emit(cs
, br
); /* R_028208_PA_SC_WINDOW_SCISSOR_BR */
1909 if (rctx
->b
.chip_class
== EVERGREEN
) {
1910 evergreen_emit_msaa_state(rctx
, rctx
->framebuffer
.nr_samples
, rctx
->ps_iter_samples
);
1912 unsigned sc_mode_cntl_1
=
1913 EG_S_028A4C_FORCE_EOV_CNTDWN_ENABLE(1) |
1914 EG_S_028A4C_FORCE_EOV_REZ_ENABLE(1);
1916 if (rctx
->framebuffer
.nr_samples
> 1)
1917 cayman_emit_msaa_sample_locs(cs
, rctx
->framebuffer
.nr_samples
);
1918 cayman_emit_msaa_config(cs
, rctx
->framebuffer
.nr_samples
,
1919 rctx
->ps_iter_samples
, 0, sc_mode_cntl_1
);
1923 static void evergreen_emit_polygon_offset(struct r600_context
*rctx
, struct r600_atom
*a
)
1925 struct radeon_winsys_cs
*cs
= rctx
->b
.gfx
.cs
;
1926 struct r600_poly_offset_state
*state
= (struct r600_poly_offset_state
*)a
;
1927 float offset_units
= state
->offset_units
;
1928 float offset_scale
= state
->offset_scale
;
1929 uint32_t pa_su_poly_offset_db_fmt_cntl
= 0;
1931 if (!state
->offset_units_unscaled
) {
1932 switch (state
->zs_format
) {
1933 case PIPE_FORMAT_Z24X8_UNORM
:
1934 case PIPE_FORMAT_Z24_UNORM_S8_UINT
:
1935 case PIPE_FORMAT_X8Z24_UNORM
:
1936 case PIPE_FORMAT_S8_UINT_Z24_UNORM
:
1937 offset_units
*= 2.0f
;
1938 pa_su_poly_offset_db_fmt_cntl
=
1939 S_028B78_POLY_OFFSET_NEG_NUM_DB_BITS((char)-24);
1941 case PIPE_FORMAT_Z16_UNORM
:
1942 offset_units
*= 4.0f
;
1943 pa_su_poly_offset_db_fmt_cntl
=
1944 S_028B78_POLY_OFFSET_NEG_NUM_DB_BITS((char)-16);
1947 pa_su_poly_offset_db_fmt_cntl
=
1948 S_028B78_POLY_OFFSET_NEG_NUM_DB_BITS((char)-23) |
1949 S_028B78_POLY_OFFSET_DB_IS_FLOAT_FMT(1);
1953 radeon_set_context_reg_seq(cs
, R_028B80_PA_SU_POLY_OFFSET_FRONT_SCALE
, 4);
1954 radeon_emit(cs
, fui(offset_scale
));
1955 radeon_emit(cs
, fui(offset_units
));
1956 radeon_emit(cs
, fui(offset_scale
));
1957 radeon_emit(cs
, fui(offset_units
));
1959 radeon_set_context_reg(cs
, R_028B78_PA_SU_POLY_OFFSET_DB_FMT_CNTL
,
1960 pa_su_poly_offset_db_fmt_cntl
);
1963 static void evergreen_emit_cb_misc_state(struct r600_context
*rctx
, struct r600_atom
*atom
)
1965 struct radeon_winsys_cs
*cs
= rctx
->b
.gfx
.cs
;
1966 struct r600_cb_misc_state
*a
= (struct r600_cb_misc_state
*)atom
;
1967 unsigned fb_colormask
= (1ULL << ((unsigned)a
->nr_cbufs
* 4)) - 1;
1968 unsigned ps_colormask
= (1ULL << ((unsigned)a
->nr_ps_color_outputs
* 4)) - 1;
1969 unsigned rat_colormask
= ((1ULL << ((unsigned)a
->nr_image_rats
* 4)) - 1) << (a
->nr_cbufs
* 4);
1970 radeon_set_context_reg_seq(cs
, R_028238_CB_TARGET_MASK
, 2);
1971 radeon_emit(cs
, (a
->blend_colormask
& fb_colormask
) | rat_colormask
); /* R_028238_CB_TARGET_MASK */
1972 /* This must match the used export instructions exactly.
1973 * Other values may lead to undefined behavior and hangs.
1975 radeon_emit(cs
, ps_colormask
); /* R_02823C_CB_SHADER_MASK */
1978 static void evergreen_emit_db_state(struct r600_context
*rctx
, struct r600_atom
*atom
)
1980 struct radeon_winsys_cs
*cs
= rctx
->b
.gfx
.cs
;
1981 struct r600_db_state
*a
= (struct r600_db_state
*)atom
;
1983 if (a
->rsurf
&& a
->rsurf
->db_htile_surface
) {
1984 struct r600_texture
*rtex
= (struct r600_texture
*)a
->rsurf
->base
.texture
;
1987 radeon_set_context_reg(cs
, R_02802C_DB_DEPTH_CLEAR
, fui(rtex
->depth_clear_value
));
1988 radeon_set_context_reg(cs
, R_028ABC_DB_HTILE_SURFACE
, a
->rsurf
->db_htile_surface
);
1989 radeon_set_context_reg(cs
, R_028AC8_DB_PRELOAD_CONTROL
, a
->rsurf
->db_preload_control
);
1990 radeon_set_context_reg(cs
, R_028014_DB_HTILE_DATA_BASE
, a
->rsurf
->db_htile_data_base
);
1991 reloc_idx
= radeon_add_to_buffer_list(&rctx
->b
, &rctx
->b
.gfx
, &rtex
->resource
,
1992 RADEON_USAGE_READWRITE
, RADEON_PRIO_HTILE
);
1993 radeon_emit(cs
, PKT3(PKT3_NOP
, 0, 0));
1994 radeon_emit(cs
, reloc_idx
);
1996 radeon_set_context_reg(cs
, R_028ABC_DB_HTILE_SURFACE
, 0);
1997 radeon_set_context_reg(cs
, R_028AC8_DB_PRELOAD_CONTROL
, 0);
2001 static void evergreen_emit_db_misc_state(struct r600_context
*rctx
, struct r600_atom
*atom
)
2003 struct radeon_winsys_cs
*cs
= rctx
->b
.gfx
.cs
;
2004 struct r600_db_misc_state
*a
= (struct r600_db_misc_state
*)atom
;
2005 unsigned db_render_control
= 0;
2006 unsigned db_count_control
= 0;
2007 unsigned db_render_override
=
2008 S_02800C_FORCE_HIS_ENABLE0(V_02800C_FORCE_DISABLE
) |
2009 S_02800C_FORCE_HIS_ENABLE1(V_02800C_FORCE_DISABLE
);
2011 if (rctx
->b
.num_occlusion_queries
> 0 &&
2012 !a
->occlusion_queries_disabled
) {
2013 db_count_control
|= S_028004_PERFECT_ZPASS_COUNTS(1);
2014 if (rctx
->b
.chip_class
== CAYMAN
) {
2015 db_count_control
|= S_028004_SAMPLE_RATE(a
->log_samples
);
2017 db_render_override
|= S_02800C_NOOP_CULL_DISABLE(1);
2019 db_count_control
|= S_028004_ZPASS_INCREMENT_DISABLE(1);
2022 /* This is to fix a lockup when hyperz and alpha test are enabled at
2023 * the same time somehow GPU get confuse on which order to pick for
2026 if (rctx
->alphatest_state
.sx_alpha_test_control
)
2027 db_render_override
|= S_02800C_FORCE_SHADER_Z_ORDER(1);
2029 if (a
->flush_depthstencil_through_cb
) {
2030 assert(a
->copy_depth
|| a
->copy_stencil
);
2032 db_render_control
|= S_028000_DEPTH_COPY_ENABLE(a
->copy_depth
) |
2033 S_028000_STENCIL_COPY_ENABLE(a
->copy_stencil
) |
2034 S_028000_COPY_CENTROID(1) |
2035 S_028000_COPY_SAMPLE(a
->copy_sample
);
2036 } else if (a
->flush_depth_inplace
|| a
->flush_stencil_inplace
) {
2037 db_render_control
|= S_028000_DEPTH_COMPRESS_DISABLE(a
->flush_depth_inplace
) |
2038 S_028000_STENCIL_COMPRESS_DISABLE(a
->flush_stencil_inplace
);
2039 db_render_override
|= S_02800C_DISABLE_PIXEL_RATE_TILES(1);
2041 if (a
->htile_clear
) {
2042 /* FIXME we might want to disable cliprect here */
2043 db_render_control
|= S_028000_DEPTH_CLEAR_ENABLE(1);
2046 radeon_set_context_reg_seq(cs
, R_028000_DB_RENDER_CONTROL
, 2);
2047 radeon_emit(cs
, db_render_control
); /* R_028000_DB_RENDER_CONTROL */
2048 radeon_emit(cs
, db_count_control
); /* R_028004_DB_COUNT_CONTROL */
2049 radeon_set_context_reg(cs
, R_02800C_DB_RENDER_OVERRIDE
, db_render_override
);
2050 radeon_set_context_reg(cs
, R_02880C_DB_SHADER_CONTROL
, a
->db_shader_control
);
2053 static void evergreen_emit_vertex_buffers(struct r600_context
*rctx
,
2054 struct r600_vertexbuf_state
*state
,
2055 unsigned resource_offset
,
2058 struct radeon_winsys_cs
*cs
= rctx
->b
.gfx
.cs
;
2059 uint32_t dirty_mask
= state
->dirty_mask
;
2061 while (dirty_mask
) {
2062 struct pipe_vertex_buffer
*vb
;
2063 struct r600_resource
*rbuffer
;
2065 unsigned buffer_index
= u_bit_scan(&dirty_mask
);
2067 vb
= &state
->vb
[buffer_index
];
2068 rbuffer
= (struct r600_resource
*)vb
->buffer
.resource
;
2071 va
= rbuffer
->gpu_address
+ vb
->buffer_offset
;
2073 /* fetch resources start at index 992 */
2074 radeon_emit(cs
, PKT3(PKT3_SET_RESOURCE
, 8, 0) | pkt_flags
);
2075 radeon_emit(cs
, (resource_offset
+ buffer_index
) * 8);
2076 radeon_emit(cs
, va
); /* RESOURCEi_WORD0 */
2077 radeon_emit(cs
, rbuffer
->b
.b
.width0
- vb
->buffer_offset
- 1); /* RESOURCEi_WORD1 */
2078 radeon_emit(cs
, /* RESOURCEi_WORD2 */
2079 S_030008_ENDIAN_SWAP(r600_endian_swap(32)) |
2080 S_030008_STRIDE(vb
->stride
) |
2081 S_030008_BASE_ADDRESS_HI(va
>> 32UL));
2082 radeon_emit(cs
, /* RESOURCEi_WORD3 */
2083 S_03000C_DST_SEL_X(V_03000C_SQ_SEL_X
) |
2084 S_03000C_DST_SEL_Y(V_03000C_SQ_SEL_Y
) |
2085 S_03000C_DST_SEL_Z(V_03000C_SQ_SEL_Z
) |
2086 S_03000C_DST_SEL_W(V_03000C_SQ_SEL_W
));
2087 radeon_emit(cs
, 0); /* RESOURCEi_WORD4 */
2088 radeon_emit(cs
, 0); /* RESOURCEi_WORD5 */
2089 radeon_emit(cs
, 0); /* RESOURCEi_WORD6 */
2090 radeon_emit(cs
, 0xc0000000); /* RESOURCEi_WORD7 */
2092 radeon_emit(cs
, PKT3(PKT3_NOP
, 0, 0) | pkt_flags
);
2093 radeon_emit(cs
, radeon_add_to_buffer_list(&rctx
->b
, &rctx
->b
.gfx
, rbuffer
,
2094 RADEON_USAGE_READ
, RADEON_PRIO_VERTEX_BUFFER
));
2096 state
->dirty_mask
= 0;
2099 static void evergreen_fs_emit_vertex_buffers(struct r600_context
*rctx
, struct r600_atom
* atom
)
2101 evergreen_emit_vertex_buffers(rctx
, &rctx
->vertex_buffer_state
, EG_FETCH_CONSTANTS_OFFSET_FS
, 0);
2104 static void evergreen_cs_emit_vertex_buffers(struct r600_context
*rctx
, struct r600_atom
* atom
)
2106 evergreen_emit_vertex_buffers(rctx
, &rctx
->cs_vertex_buffer_state
, EG_FETCH_CONSTANTS_OFFSET_CS
,
2107 RADEON_CP_PACKET3_COMPUTE_MODE
);
2110 static void evergreen_emit_constant_buffers(struct r600_context
*rctx
,
2111 struct r600_constbuf_state
*state
,
2112 unsigned buffer_id_base
,
2113 unsigned reg_alu_constbuf_size
,
2114 unsigned reg_alu_const_cache
,
2117 struct radeon_winsys_cs
*cs
= rctx
->b
.gfx
.cs
;
2118 uint32_t dirty_mask
= state
->dirty_mask
;
2120 while (dirty_mask
) {
2121 struct pipe_constant_buffer
*cb
;
2122 struct r600_resource
*rbuffer
;
2124 unsigned buffer_index
= ffs(dirty_mask
) - 1;
2125 unsigned gs_ring_buffer
= (buffer_index
== R600_GS_RING_CONST_BUFFER
);
2127 cb
= &state
->cb
[buffer_index
];
2128 rbuffer
= (struct r600_resource
*)cb
->buffer
;
2131 va
= rbuffer
->gpu_address
+ cb
->buffer_offset
;
2133 if (!gs_ring_buffer
) {
2134 radeon_set_context_reg_flag(cs
, reg_alu_constbuf_size
+ buffer_index
* 4,
2135 DIV_ROUND_UP(cb
->buffer_size
, 256), pkt_flags
);
2136 radeon_set_context_reg_flag(cs
, reg_alu_const_cache
+ buffer_index
* 4, va
>> 8,
2140 radeon_emit(cs
, PKT3(PKT3_NOP
, 0, 0) | pkt_flags
);
2141 radeon_emit(cs
, radeon_add_to_buffer_list(&rctx
->b
, &rctx
->b
.gfx
, rbuffer
,
2142 RADEON_USAGE_READ
, RADEON_PRIO_CONST_BUFFER
));
2144 radeon_emit(cs
, PKT3(PKT3_SET_RESOURCE
, 8, 0) | pkt_flags
);
2145 radeon_emit(cs
, (buffer_id_base
+ buffer_index
) * 8);
2146 radeon_emit(cs
, va
); /* RESOURCEi_WORD0 */
2147 radeon_emit(cs
, rbuffer
->b
.b
.width0
- cb
->buffer_offset
- 1); /* RESOURCEi_WORD1 */
2148 radeon_emit(cs
, /* RESOURCEi_WORD2 */
2149 S_030008_ENDIAN_SWAP(gs_ring_buffer
? ENDIAN_NONE
: r600_endian_swap(32)) |
2150 S_030008_STRIDE(gs_ring_buffer
? 4 : 16) |
2151 S_030008_BASE_ADDRESS_HI(va
>> 32UL) |
2152 S_030008_DATA_FORMAT(FMT_32_32_32_32_FLOAT
));
2153 radeon_emit(cs
, /* RESOURCEi_WORD3 */
2154 S_03000C_UNCACHED(gs_ring_buffer
? 1 : 0) |
2155 S_03000C_DST_SEL_X(V_03000C_SQ_SEL_X
) |
2156 S_03000C_DST_SEL_Y(V_03000C_SQ_SEL_Y
) |
2157 S_03000C_DST_SEL_Z(V_03000C_SQ_SEL_Z
) |
2158 S_03000C_DST_SEL_W(V_03000C_SQ_SEL_W
));
2159 radeon_emit(cs
, 0); /* RESOURCEi_WORD4 */
2160 radeon_emit(cs
, 0); /* RESOURCEi_WORD5 */
2161 radeon_emit(cs
, 0); /* RESOURCEi_WORD6 */
2162 radeon_emit(cs
, /* RESOURCEi_WORD7 */
2163 S_03001C_TYPE(V_03001C_SQ_TEX_VTX_VALID_BUFFER
));
2165 radeon_emit(cs
, PKT3(PKT3_NOP
, 0, 0) | pkt_flags
);
2166 radeon_emit(cs
, radeon_add_to_buffer_list(&rctx
->b
, &rctx
->b
.gfx
, rbuffer
,
2167 RADEON_USAGE_READ
, RADEON_PRIO_CONST_BUFFER
));
2169 dirty_mask
&= ~(1 << buffer_index
);
2171 state
->dirty_mask
= 0;
2174 /* VS constants can be in VS/ES (same space) or LS if tess is enabled */
2175 static void evergreen_emit_vs_constant_buffers(struct r600_context
*rctx
, struct r600_atom
*atom
)
2177 if (rctx
->vs_shader
->current
->shader
.vs_as_ls
) {
2178 evergreen_emit_constant_buffers(rctx
, &rctx
->constbuf_state
[PIPE_SHADER_VERTEX
],
2179 EG_FETCH_CONSTANTS_OFFSET_LS
,
2180 R_028FC0_ALU_CONST_BUFFER_SIZE_LS_0
,
2181 R_028F40_ALU_CONST_CACHE_LS_0
,
2182 0 /* PKT3 flags */);
2184 evergreen_emit_constant_buffers(rctx
, &rctx
->constbuf_state
[PIPE_SHADER_VERTEX
],
2185 EG_FETCH_CONSTANTS_OFFSET_VS
,
2186 R_028180_ALU_CONST_BUFFER_SIZE_VS_0
,
2187 R_028980_ALU_CONST_CACHE_VS_0
,
2188 0 /* PKT3 flags */);
2192 static void evergreen_emit_gs_constant_buffers(struct r600_context
*rctx
, struct r600_atom
*atom
)
2194 evergreen_emit_constant_buffers(rctx
, &rctx
->constbuf_state
[PIPE_SHADER_GEOMETRY
],
2195 EG_FETCH_CONSTANTS_OFFSET_GS
,
2196 R_0281C0_ALU_CONST_BUFFER_SIZE_GS_0
,
2197 R_0289C0_ALU_CONST_CACHE_GS_0
,
2198 0 /* PKT3 flags */);
2201 static void evergreen_emit_ps_constant_buffers(struct r600_context
*rctx
, struct r600_atom
*atom
)
2203 evergreen_emit_constant_buffers(rctx
, &rctx
->constbuf_state
[PIPE_SHADER_FRAGMENT
],
2204 EG_FETCH_CONSTANTS_OFFSET_PS
,
2205 R_028140_ALU_CONST_BUFFER_SIZE_PS_0
,
2206 R_028940_ALU_CONST_CACHE_PS_0
,
2207 0 /* PKT3 flags */);
2210 static void evergreen_emit_cs_constant_buffers(struct r600_context
*rctx
, struct r600_atom
*atom
)
2212 evergreen_emit_constant_buffers(rctx
, &rctx
->constbuf_state
[PIPE_SHADER_COMPUTE
],
2213 EG_FETCH_CONSTANTS_OFFSET_CS
,
2214 R_028FC0_ALU_CONST_BUFFER_SIZE_LS_0
,
2215 R_028F40_ALU_CONST_CACHE_LS_0
,
2216 RADEON_CP_PACKET3_COMPUTE_MODE
);
2219 /* tes constants can be emitted to VS or ES - which are common */
2220 static void evergreen_emit_tes_constant_buffers(struct r600_context
*rctx
, struct r600_atom
*atom
)
2222 if (!rctx
->tes_shader
)
2224 evergreen_emit_constant_buffers(rctx
, &rctx
->constbuf_state
[PIPE_SHADER_TESS_EVAL
],
2225 EG_FETCH_CONSTANTS_OFFSET_VS
,
2226 R_028180_ALU_CONST_BUFFER_SIZE_VS_0
,
2227 R_028980_ALU_CONST_CACHE_VS_0
,
2231 static void evergreen_emit_tcs_constant_buffers(struct r600_context
*rctx
, struct r600_atom
*atom
)
2233 if (!rctx
->tes_shader
)
2235 evergreen_emit_constant_buffers(rctx
, &rctx
->constbuf_state
[PIPE_SHADER_TESS_CTRL
],
2236 EG_FETCH_CONSTANTS_OFFSET_HS
,
2237 R_028F80_ALU_CONST_BUFFER_SIZE_HS_0
,
2238 R_028F00_ALU_CONST_CACHE_HS_0
,
2242 static void evergreen_emit_sampler_views(struct r600_context
*rctx
,
2243 struct r600_samplerview_state
*state
,
2244 unsigned resource_id_base
, unsigned pkt_flags
)
2246 struct radeon_winsys_cs
*cs
= rctx
->b
.gfx
.cs
;
2247 uint32_t dirty_mask
= state
->dirty_mask
;
2249 while (dirty_mask
) {
2250 struct r600_pipe_sampler_view
*rview
;
2251 unsigned resource_index
= u_bit_scan(&dirty_mask
);
2254 rview
= state
->views
[resource_index
];
2257 radeon_emit(cs
, PKT3(PKT3_SET_RESOURCE
, 8, 0) | pkt_flags
);
2258 radeon_emit(cs
, (resource_id_base
+ resource_index
) * 8);
2259 radeon_emit_array(cs
, rview
->tex_resource_words
, 8);
2261 reloc
= radeon_add_to_buffer_list(&rctx
->b
, &rctx
->b
.gfx
, rview
->tex_resource
,
2263 r600_get_sampler_view_priority(rview
->tex_resource
));
2264 radeon_emit(cs
, PKT3(PKT3_NOP
, 0, 0) | pkt_flags
);
2265 radeon_emit(cs
, reloc
);
2267 if (!rview
->skip_mip_address_reloc
) {
2268 radeon_emit(cs
, PKT3(PKT3_NOP
, 0, 0) | pkt_flags
);
2269 radeon_emit(cs
, reloc
);
2272 state
->dirty_mask
= 0;
2275 static void evergreen_emit_vs_sampler_views(struct r600_context
*rctx
, struct r600_atom
*atom
)
2277 if (rctx
->vs_shader
->current
->shader
.vs_as_ls
) {
2278 evergreen_emit_sampler_views(rctx
, &rctx
->samplers
[PIPE_SHADER_VERTEX
].views
,
2279 EG_FETCH_CONSTANTS_OFFSET_LS
+ R600_MAX_CONST_BUFFERS
, 0);
2281 evergreen_emit_sampler_views(rctx
, &rctx
->samplers
[PIPE_SHADER_VERTEX
].views
,
2282 EG_FETCH_CONSTANTS_OFFSET_VS
+ R600_MAX_CONST_BUFFERS
, 0);
2286 static void evergreen_emit_gs_sampler_views(struct r600_context
*rctx
, struct r600_atom
*atom
)
2288 evergreen_emit_sampler_views(rctx
, &rctx
->samplers
[PIPE_SHADER_GEOMETRY
].views
,
2289 EG_FETCH_CONSTANTS_OFFSET_GS
+ R600_MAX_CONST_BUFFERS
, 0);
2292 static void evergreen_emit_tcs_sampler_views(struct r600_context
*rctx
, struct r600_atom
*atom
)
2294 evergreen_emit_sampler_views(rctx
, &rctx
->samplers
[PIPE_SHADER_TESS_CTRL
].views
,
2295 EG_FETCH_CONSTANTS_OFFSET_HS
+ R600_MAX_CONST_BUFFERS
, 0);
2298 static void evergreen_emit_tes_sampler_views(struct r600_context
*rctx
, struct r600_atom
*atom
)
2300 evergreen_emit_sampler_views(rctx
, &rctx
->samplers
[PIPE_SHADER_TESS_EVAL
].views
,
2301 EG_FETCH_CONSTANTS_OFFSET_VS
+ R600_MAX_CONST_BUFFERS
, 0);
2304 static void evergreen_emit_ps_sampler_views(struct r600_context
*rctx
, struct r600_atom
*atom
)
2306 evergreen_emit_sampler_views(rctx
, &rctx
->samplers
[PIPE_SHADER_FRAGMENT
].views
,
2307 EG_FETCH_CONSTANTS_OFFSET_PS
+ R600_MAX_CONST_BUFFERS
, 0);
2310 static void evergreen_emit_cs_sampler_views(struct r600_context
*rctx
, struct r600_atom
*atom
)
2312 evergreen_emit_sampler_views(rctx
, &rctx
->samplers
[PIPE_SHADER_COMPUTE
].views
,
2313 EG_FETCH_CONSTANTS_OFFSET_CS
+ 2, RADEON_CP_PACKET3_COMPUTE_MODE
);
2316 static void evergreen_emit_sampler_states(struct r600_context
*rctx
,
2317 struct r600_textures_info
*texinfo
,
2318 unsigned resource_id_base
,
2319 unsigned border_index_reg
,
2322 struct radeon_winsys_cs
*cs
= rctx
->b
.gfx
.cs
;
2323 uint32_t dirty_mask
= texinfo
->states
.dirty_mask
;
2325 while (dirty_mask
) {
2326 struct r600_pipe_sampler_state
*rstate
;
2327 unsigned i
= u_bit_scan(&dirty_mask
);
2329 rstate
= texinfo
->states
.states
[i
];
2332 radeon_emit(cs
, PKT3(PKT3_SET_SAMPLER
, 3, 0) | pkt_flags
);
2333 radeon_emit(cs
, (resource_id_base
+ i
) * 3);
2334 radeon_emit_array(cs
, rstate
->tex_sampler_words
, 3);
2336 if (rstate
->border_color_use
) {
2337 radeon_set_config_reg_seq(cs
, border_index_reg
, 5);
2339 radeon_emit_array(cs
, rstate
->border_color
.ui
, 4);
2342 texinfo
->states
.dirty_mask
= 0;
2345 static void evergreen_emit_vs_sampler_states(struct r600_context
*rctx
, struct r600_atom
*atom
)
2347 if (rctx
->vs_shader
->current
->shader
.vs_as_ls
) {
2348 evergreen_emit_sampler_states(rctx
, &rctx
->samplers
[PIPE_SHADER_VERTEX
], 72,
2349 R_00A450_TD_LS_SAMPLER0_BORDER_COLOR_INDEX
, 0);
2351 evergreen_emit_sampler_states(rctx
, &rctx
->samplers
[PIPE_SHADER_VERTEX
], 18,
2352 R_00A414_TD_VS_SAMPLER0_BORDER_INDEX
, 0);
2356 static void evergreen_emit_gs_sampler_states(struct r600_context
*rctx
, struct r600_atom
*atom
)
2358 evergreen_emit_sampler_states(rctx
, &rctx
->samplers
[PIPE_SHADER_GEOMETRY
], 36,
2359 R_00A428_TD_GS_SAMPLER0_BORDER_INDEX
, 0);
2362 static void evergreen_emit_tcs_sampler_states(struct r600_context
*rctx
, struct r600_atom
*atom
)
2364 evergreen_emit_sampler_states(rctx
, &rctx
->samplers
[PIPE_SHADER_TESS_CTRL
], 54,
2365 R_00A43C_TD_HS_SAMPLER0_BORDER_COLOR_INDEX
, 0);
2368 static void evergreen_emit_tes_sampler_states(struct r600_context
*rctx
, struct r600_atom
*atom
)
2370 evergreen_emit_sampler_states(rctx
, &rctx
->samplers
[PIPE_SHADER_TESS_EVAL
], 18,
2371 R_00A414_TD_VS_SAMPLER0_BORDER_INDEX
, 0);
2374 static void evergreen_emit_ps_sampler_states(struct r600_context
*rctx
, struct r600_atom
*atom
)
2376 evergreen_emit_sampler_states(rctx
, &rctx
->samplers
[PIPE_SHADER_FRAGMENT
], 0,
2377 R_00A400_TD_PS_SAMPLER0_BORDER_INDEX
, 0);
2380 static void evergreen_emit_cs_sampler_states(struct r600_context
*rctx
, struct r600_atom
*atom
)
2382 evergreen_emit_sampler_states(rctx
, &rctx
->samplers
[PIPE_SHADER_COMPUTE
], 90,
2383 R_00A464_TD_CS_SAMPLER0_BORDER_INDEX
,
2384 RADEON_CP_PACKET3_COMPUTE_MODE
);
2387 static void evergreen_emit_sample_mask(struct r600_context
*rctx
, struct r600_atom
*a
)
2389 struct r600_sample_mask
*s
= (struct r600_sample_mask
*)a
;
2390 uint8_t mask
= s
->sample_mask
;
2392 radeon_set_context_reg(rctx
->b
.gfx
.cs
, R_028C3C_PA_SC_AA_MASK
,
2393 mask
| (mask
<< 8) | (mask
<< 16) | (mask
<< 24));
2396 static void cayman_emit_sample_mask(struct r600_context
*rctx
, struct r600_atom
*a
)
2398 struct r600_sample_mask
*s
= (struct r600_sample_mask
*)a
;
2399 struct radeon_winsys_cs
*cs
= rctx
->b
.gfx
.cs
;
2400 uint16_t mask
= s
->sample_mask
;
2402 radeon_set_context_reg_seq(cs
, CM_R_028C38_PA_SC_AA_MASK_X0Y0_X1Y0
, 2);
2403 radeon_emit(cs
, mask
| (mask
<< 16)); /* X0Y0_X1Y0 */
2404 radeon_emit(cs
, mask
| (mask
<< 16)); /* X0Y1_X1Y1 */
2407 static void evergreen_emit_vertex_fetch_shader(struct r600_context
*rctx
, struct r600_atom
*a
)
2409 struct radeon_winsys_cs
*cs
= rctx
->b
.gfx
.cs
;
2410 struct r600_cso_state
*state
= (struct r600_cso_state
*)a
;
2411 struct r600_fetch_shader
*shader
= (struct r600_fetch_shader
*)state
->cso
;
2416 radeon_set_context_reg(cs
, R_0288A4_SQ_PGM_START_FS
,
2417 (shader
->buffer
->gpu_address
+ shader
->offset
) >> 8);
2418 radeon_emit(cs
, PKT3(PKT3_NOP
, 0, 0));
2419 radeon_emit(cs
, radeon_add_to_buffer_list(&rctx
->b
, &rctx
->b
.gfx
, shader
->buffer
,
2421 RADEON_PRIO_SHADER_BINARY
));
2424 static void evergreen_emit_shader_stages(struct r600_context
*rctx
, struct r600_atom
*a
)
2426 struct radeon_winsys_cs
*cs
= rctx
->b
.gfx
.cs
;
2427 struct r600_shader_stages_state
*state
= (struct r600_shader_stages_state
*)a
;
2429 uint32_t v
= 0, v2
= 0, primid
= 0, tf_param
= 0;
2431 if (rctx
->vs_shader
->current
->shader
.vs_as_gs_a
) {
2432 v2
= S_028A40_MODE(V_028A40_GS_SCENARIO_A
);
2436 if (state
->geom_enable
) {
2439 if (rctx
->gs_shader
->gs_max_out_vertices
<= 128)
2440 cut_val
= V_028A40_GS_CUT_128
;
2441 else if (rctx
->gs_shader
->gs_max_out_vertices
<= 256)
2442 cut_val
= V_028A40_GS_CUT_256
;
2443 else if (rctx
->gs_shader
->gs_max_out_vertices
<= 512)
2444 cut_val
= V_028A40_GS_CUT_512
;
2446 cut_val
= V_028A40_GS_CUT_1024
;
2448 v
= S_028B54_GS_EN(1) |
2449 S_028B54_VS_EN(V_028B54_VS_STAGE_COPY_SHADER
);
2450 if (!rctx
->tes_shader
)
2451 v
|= S_028B54_ES_EN(V_028B54_ES_STAGE_REAL
);
2453 v2
= S_028A40_MODE(V_028A40_GS_SCENARIO_G
) |
2454 S_028A40_CUT_MODE(cut_val
);
2456 if (rctx
->gs_shader
->current
->shader
.gs_prim_id_input
)
2460 if (rctx
->tes_shader
) {
2461 uint32_t type
, partitioning
, topology
;
2462 struct tgsi_shader_info
*info
= &rctx
->tes_shader
->current
->selector
->info
;
2463 unsigned tes_prim_mode
= info
->properties
[TGSI_PROPERTY_TES_PRIM_MODE
];
2464 unsigned tes_spacing
= info
->properties
[TGSI_PROPERTY_TES_SPACING
];
2465 bool tes_vertex_order_cw
= info
->properties
[TGSI_PROPERTY_TES_VERTEX_ORDER_CW
];
2466 bool tes_point_mode
= info
->properties
[TGSI_PROPERTY_TES_POINT_MODE
];
2467 switch (tes_prim_mode
) {
2468 case PIPE_PRIM_LINES
:
2469 type
= V_028B6C_TESS_ISOLINE
;
2471 case PIPE_PRIM_TRIANGLES
:
2472 type
= V_028B6C_TESS_TRIANGLE
;
2474 case PIPE_PRIM_QUADS
:
2475 type
= V_028B6C_TESS_QUAD
;
2482 switch (tes_spacing
) {
2483 case PIPE_TESS_SPACING_FRACTIONAL_ODD
:
2484 partitioning
= V_028B6C_PART_FRAC_ODD
;
2486 case PIPE_TESS_SPACING_FRACTIONAL_EVEN
:
2487 partitioning
= V_028B6C_PART_FRAC_EVEN
;
2489 case PIPE_TESS_SPACING_EQUAL
:
2490 partitioning
= V_028B6C_PART_INTEGER
;
2498 topology
= V_028B6C_OUTPUT_POINT
;
2499 else if (tes_prim_mode
== PIPE_PRIM_LINES
)
2500 topology
= V_028B6C_OUTPUT_LINE
;
2501 else if (tes_vertex_order_cw
)
2502 /* XXX follow radeonsi and invert */
2503 topology
= V_028B6C_OUTPUT_TRIANGLE_CCW
;
2505 topology
= V_028B6C_OUTPUT_TRIANGLE_CW
;
2507 tf_param
= S_028B6C_TYPE(type
) |
2508 S_028B6C_PARTITIONING(partitioning
) |
2509 S_028B6C_TOPOLOGY(topology
);
2512 if (rctx
->tes_shader
) {
2513 v
|= S_028B54_LS_EN(V_028B54_LS_STAGE_ON
) |
2515 if (!state
->geom_enable
)
2516 v
|= S_028B54_VS_EN(V_028B54_VS_STAGE_DS
);
2518 v
|= S_028B54_ES_EN(V_028B54_ES_STAGE_DS
);
2521 radeon_set_context_reg(cs
, R_028AB8_VGT_VTX_CNT_EN
, v
? 1 : 0 );
2522 radeon_set_context_reg(cs
, R_028B54_VGT_SHADER_STAGES_EN
, v
);
2523 radeon_set_context_reg(cs
, R_028A40_VGT_GS_MODE
, v2
);
2524 radeon_set_context_reg(cs
, R_028A84_VGT_PRIMITIVEID_EN
, primid
);
2525 radeon_set_context_reg(cs
, R_028B6C_VGT_TF_PARAM
, tf_param
);
2528 static void evergreen_emit_gs_rings(struct r600_context
*rctx
, struct r600_atom
*a
)
2530 struct radeon_winsys_cs
*cs
= rctx
->b
.gfx
.cs
;
2531 struct r600_gs_rings_state
*state
= (struct r600_gs_rings_state
*)a
;
2532 struct r600_resource
*rbuffer
;
2534 radeon_set_config_reg(cs
, R_008040_WAIT_UNTIL
, S_008040_WAIT_3D_IDLE(1));
2535 radeon_emit(cs
, PKT3(PKT3_EVENT_WRITE
, 0, 0));
2536 radeon_emit(cs
, EVENT_TYPE(EVENT_TYPE_VGT_FLUSH
));
2538 if (state
->enable
) {
2539 rbuffer
=(struct r600_resource
*)state
->esgs_ring
.buffer
;
2540 radeon_set_config_reg(cs
, R_008C40_SQ_ESGS_RING_BASE
,
2541 rbuffer
->gpu_address
>> 8);
2542 radeon_emit(cs
, PKT3(PKT3_NOP
, 0, 0));
2543 radeon_emit(cs
, radeon_add_to_buffer_list(&rctx
->b
, &rctx
->b
.gfx
, rbuffer
,
2544 RADEON_USAGE_READWRITE
,
2545 RADEON_PRIO_SHADER_RINGS
));
2546 radeon_set_config_reg(cs
, R_008C44_SQ_ESGS_RING_SIZE
,
2547 state
->esgs_ring
.buffer_size
>> 8);
2549 rbuffer
=(struct r600_resource
*)state
->gsvs_ring
.buffer
;
2550 radeon_set_config_reg(cs
, R_008C48_SQ_GSVS_RING_BASE
,
2551 rbuffer
->gpu_address
>> 8);
2552 radeon_emit(cs
, PKT3(PKT3_NOP
, 0, 0));
2553 radeon_emit(cs
, radeon_add_to_buffer_list(&rctx
->b
, &rctx
->b
.gfx
, rbuffer
,
2554 RADEON_USAGE_READWRITE
,
2555 RADEON_PRIO_SHADER_RINGS
));
2556 radeon_set_config_reg(cs
, R_008C4C_SQ_GSVS_RING_SIZE
,
2557 state
->gsvs_ring
.buffer_size
>> 8);
2559 radeon_set_config_reg(cs
, R_008C44_SQ_ESGS_RING_SIZE
, 0);
2560 radeon_set_config_reg(cs
, R_008C4C_SQ_GSVS_RING_SIZE
, 0);
2563 radeon_set_config_reg(cs
, R_008040_WAIT_UNTIL
, S_008040_WAIT_3D_IDLE(1));
2564 radeon_emit(cs
, PKT3(PKT3_EVENT_WRITE
, 0, 0));
2565 radeon_emit(cs
, EVENT_TYPE(EVENT_TYPE_VGT_FLUSH
));
2568 void cayman_init_common_regs(struct r600_command_buffer
*cb
,
2569 enum chip_class ctx_chip_class
,
2570 enum radeon_family ctx_family
,
2573 r600_store_config_reg_seq(cb
, R_008C00_SQ_CONFIG
, 2);
2574 r600_store_value(cb
, S_008C00_EXPORT_SRC_C(1)); /* R_008C00_SQ_CONFIG */
2575 /* always set the temp clauses */
2576 r600_store_value(cb
, S_008C04_NUM_CLAUSE_TEMP_GPRS(4)); /* R_008C04_SQ_GPR_RESOURCE_MGMT_1 */
2578 r600_store_config_reg_seq(cb
, R_008C10_SQ_GLOBAL_GPR_RESOURCE_MGMT_1
, 2);
2579 r600_store_value(cb
, 0); /* R_008C10_SQ_GLOBAL_GPR_RESOURCE_MGMT_1 */
2580 r600_store_value(cb
, 0); /* R_008C14_SQ_GLOBAL_GPR_RESOURCE_MGMT_2 */
2582 r600_store_config_reg(cb
, R_008D8C_SQ_DYN_GPR_CNTL_PS_FLUSH_REQ
, (1 << 8));
2584 r600_store_context_reg_seq(cb
, R_028350_SX_MISC
, 2);
2585 r600_store_value(cb
, 0);
2586 r600_store_value(cb
, S_028354_SURFACE_SYNC_MASK(0xf));
2588 r600_store_context_reg(cb
, R_028800_DB_DEPTH_CONTROL
, 0);
2591 static void cayman_init_atom_start_cs(struct r600_context
*rctx
)
2593 struct r600_command_buffer
*cb
= &rctx
->start_cs_cmd
;
2596 r600_init_command_buffer(cb
, 338);
2598 /* This must be first. */
2599 r600_store_value(cb
, PKT3(PKT3_CONTEXT_CONTROL
, 1, 0));
2600 r600_store_value(cb
, 0x80000000);
2601 r600_store_value(cb
, 0x80000000);
2603 /* We're setting config registers here. */
2604 r600_store_value(cb
, PKT3(PKT3_EVENT_WRITE
, 0, 0));
2605 r600_store_value(cb
, EVENT_TYPE(EVENT_TYPE_PS_PARTIAL_FLUSH
) | EVENT_INDEX(4));
2607 /* This enables pipeline stat & streamout queries.
2608 * They are only disabled by blits.
2610 r600_store_value(cb
, PKT3(PKT3_EVENT_WRITE
, 0, 0));
2611 r600_store_value(cb
, EVENT_TYPE(EVENT_TYPE_PIPELINESTAT_START
) | EVENT_INDEX(0));
2613 cayman_init_common_regs(cb
, rctx
->b
.chip_class
,
2614 rctx
->b
.family
, rctx
->screen
->b
.info
.drm_minor
);
2616 r600_store_config_reg(cb
, R_009100_SPI_CONFIG_CNTL
, 0);
2617 r600_store_config_reg(cb
, R_00913C_SPI_CONFIG_CNTL_1
, S_00913C_VTX_DONE_DELAY(4));
2619 /* remove LS/HS from one SIMD for hw workaround */
2620 r600_store_config_reg_seq(cb
, R_008E20_SQ_STATIC_THREAD_MGMT1
, 3);
2621 r600_store_value(cb
, 0xffffffff);
2622 r600_store_value(cb
, 0xffffffff);
2623 r600_store_value(cb
, 0xfffffffe);
2625 r600_store_context_reg_seq(cb
, R_028900_SQ_ESGS_RING_ITEMSIZE
, 6);
2626 r600_store_value(cb
, 0); /* R_028900_SQ_ESGS_RING_ITEMSIZE */
2627 r600_store_value(cb
, 0); /* R_028904_SQ_GSVS_RING_ITEMSIZE */
2628 r600_store_value(cb
, 0); /* R_028908_SQ_ESTMP_RING_ITEMSIZE */
2629 r600_store_value(cb
, 0); /* R_02890C_SQ_GSTMP_RING_ITEMSIZE */
2630 r600_store_value(cb
, 0); /* R_028910_SQ_VSTMP_RING_ITEMSIZE */
2631 r600_store_value(cb
, 0); /* R_028914_SQ_PSTMP_RING_ITEMSIZE */
2633 r600_store_context_reg_seq(cb
, R_02891C_SQ_GS_VERT_ITEMSIZE
, 4);
2634 r600_store_value(cb
, 0); /* R_02891C_SQ_GS_VERT_ITEMSIZE */
2635 r600_store_value(cb
, 0); /* R_028920_SQ_GS_VERT_ITEMSIZE_1 */
2636 r600_store_value(cb
, 0); /* R_028924_SQ_GS_VERT_ITEMSIZE_2 */
2637 r600_store_value(cb
, 0); /* R_028928_SQ_GS_VERT_ITEMSIZE_3 */
2639 r600_store_context_reg_seq(cb
, R_028A10_VGT_OUTPUT_PATH_CNTL
, 13);
2640 r600_store_value(cb
, 0); /* R_028A10_VGT_OUTPUT_PATH_CNTL */
2641 r600_store_value(cb
, 0); /* R_028A14_VGT_HOS_CNTL */
2642 r600_store_value(cb
, fui(64)); /* R_028A18_VGT_HOS_MAX_TESS_LEVEL */
2643 r600_store_value(cb
, fui(0)); /* R_028A1C_VGT_HOS_MIN_TESS_LEVEL */
2644 r600_store_value(cb
, 16); /* R_028A20_VGT_HOS_REUSE_DEPTH */
2645 r600_store_value(cb
, 0); /* R_028A24_VGT_GROUP_PRIM_TYPE */
2646 r600_store_value(cb
, 0); /* R_028A28_VGT_GROUP_FIRST_DECR */
2647 r600_store_value(cb
, 0); /* R_028A2C_VGT_GROUP_DECR */
2648 r600_store_value(cb
, 0); /* R_028A30_VGT_GROUP_VECT_0_CNTL */
2649 r600_store_value(cb
, 0); /* R_028A34_VGT_GROUP_VECT_1_CNTL */
2650 r600_store_value(cb
, 0); /* R_028A38_VGT_GROUP_VECT_0_FMT_CNTL */
2651 r600_store_value(cb
, 0); /* R_028A3C_VGT_GROUP_VECT_1_FMT_CNTL */
2652 r600_store_value(cb
, 0); /* R_028A40_VGT_GS_MODE */
2654 r600_store_context_reg(cb
, R_028B98_VGT_STRMOUT_BUFFER_CONFIG
, 0);
2656 r600_store_config_reg(cb
, R_008A14_PA_CL_ENHANCE
, (3 << 1) | 1);
2658 r600_store_context_reg_seq(cb
, CM_R_028BD4_PA_SC_CENTROID_PRIORITY_0
, 2);
2659 r600_store_value(cb
, 0x76543210); /* CM_R_028BD4_PA_SC_CENTROID_PRIORITY_0 */
2660 r600_store_value(cb
, 0xfedcba98); /* CM_R_028BD8_PA_SC_CENTROID_PRIORITY_1 */
2662 r600_store_context_reg_seq(cb
, R_0288E8_SQ_LDS_ALLOC
, 2);
2663 r600_store_value(cb
, 0); /* R_0288E8_SQ_LDS_ALLOC */
2664 r600_store_value(cb
, 0); /* R_0288EC_SQ_LDS_ALLOC_PS */
2666 r600_store_context_reg(cb
, R_0288F0_SQ_VTX_SEMANTIC_CLEAR
, ~0);
2668 r600_store_context_reg_seq(cb
, R_028400_VGT_MAX_VTX_INDX
, 2);
2669 r600_store_value(cb
, ~0); /* R_028400_VGT_MAX_VTX_INDX */
2670 r600_store_value(cb
, 0); /* R_028404_VGT_MIN_VTX_INDX */
2672 r600_store_ctl_const(cb
, R_03CFF0_SQ_VTX_BASE_VTX_LOC
, 0);
2674 r600_store_context_reg(cb
, R_028028_DB_STENCIL_CLEAR
, 0);
2676 r600_store_context_reg(cb
, R_0286DC_SPI_FOG_CNTL
, 0);
2678 r600_store_context_reg_seq(cb
, R_028AC0_DB_SRESULTS_COMPARE_STATE0
, 3);
2679 r600_store_value(cb
, 0); /* R_028AC0_DB_SRESULTS_COMPARE_STATE0 */
2680 r600_store_value(cb
, 0); /* R_028AC4_DB_SRESULTS_COMPARE_STATE1 */
2681 r600_store_value(cb
, 0); /* R_028AC8_DB_PRELOAD_CONTROL */
2683 r600_store_context_reg(cb
, R_028200_PA_SC_WINDOW_OFFSET
, 0);
2684 r600_store_context_reg(cb
, R_02820C_PA_SC_CLIPRECT_RULE
, 0xFFFF);
2686 r600_store_context_reg(cb
, R_028230_PA_SC_EDGERULE
, 0xAAAAAAAA);
2687 r600_store_context_reg(cb
, R_028820_PA_CL_NANINF_CNTL
, 0);
2689 r600_store_context_reg_seq(cb
, R_028240_PA_SC_GENERIC_SCISSOR_TL
, 2);
2690 r600_store_value(cb
, 0); /* R_028240_PA_SC_GENERIC_SCISSOR_TL */
2691 r600_store_value(cb
, S_028244_BR_X(16384) | S_028244_BR_Y(16384)); /* R_028244_PA_SC_GENERIC_SCISSOR_BR */
2693 r600_store_context_reg_seq(cb
, R_028030_PA_SC_SCREEN_SCISSOR_TL
, 2);
2694 r600_store_value(cb
, 0); /* R_028030_PA_SC_SCREEN_SCISSOR_TL */
2695 r600_store_value(cb
, S_028034_BR_X(16384) | S_028034_BR_Y(16384)); /* R_028034_PA_SC_SCREEN_SCISSOR_BR */
2697 r600_store_context_reg(cb
, R_028848_SQ_PGM_RESOURCES_2_PS
, S_028848_SINGLE_ROUND(V_SQ_ROUND_NEAREST_EVEN
));
2698 r600_store_context_reg(cb
, R_028864_SQ_PGM_RESOURCES_2_VS
, S_028864_SINGLE_ROUND(V_SQ_ROUND_NEAREST_EVEN
));
2699 r600_store_context_reg(cb
, R_02887C_SQ_PGM_RESOURCES_2_GS
, S_028848_SINGLE_ROUND(V_SQ_ROUND_NEAREST_EVEN
));
2700 r600_store_context_reg(cb
, R_028894_SQ_PGM_RESOURCES_2_ES
, S_028848_SINGLE_ROUND(V_SQ_ROUND_NEAREST_EVEN
));
2701 r600_store_context_reg(cb
, R_0288C0_SQ_PGM_RESOURCES_2_HS
, S_028848_SINGLE_ROUND(V_SQ_ROUND_NEAREST_EVEN
));
2702 r600_store_context_reg(cb
, R_0288D8_SQ_PGM_RESOURCES_2_LS
, S_028848_SINGLE_ROUND(V_SQ_ROUND_NEAREST_EVEN
));
2704 r600_store_context_reg(cb
, R_0288A8_SQ_PGM_RESOURCES_FS
, 0);
2706 /* to avoid GPU doing any preloading of constant from random address */
2707 r600_store_context_reg_seq(cb
, R_028140_ALU_CONST_BUFFER_SIZE_PS_0
, 16);
2708 for (i
= 0; i
< 16; i
++)
2709 r600_store_value(cb
, 0);
2711 r600_store_context_reg_seq(cb
, R_028180_ALU_CONST_BUFFER_SIZE_VS_0
, 16);
2712 for (i
= 0; i
< 16; i
++)
2713 r600_store_value(cb
, 0);
2715 r600_store_context_reg_seq(cb
, R_0281C0_ALU_CONST_BUFFER_SIZE_GS_0
, 16);
2716 for (i
= 0; i
< 16; i
++)
2717 r600_store_value(cb
, 0);
2719 r600_store_context_reg_seq(cb
, R_028FC0_ALU_CONST_BUFFER_SIZE_LS_0
, 16);
2720 for (i
= 0; i
< 16; i
++)
2721 r600_store_value(cb
, 0);
2723 r600_store_context_reg_seq(cb
, R_028F80_ALU_CONST_BUFFER_SIZE_HS_0
, 16);
2724 for (i
= 0; i
< 16; i
++)
2725 r600_store_value(cb
, 0);
2727 if (rctx
->screen
->b
.has_streamout
) {
2728 r600_store_context_reg(cb
, R_028B28_VGT_STRMOUT_DRAW_OPAQUE_OFFSET
, 0);
2731 r600_store_context_reg(cb
, R_028010_DB_RENDER_OVERRIDE2
, 0);
2732 r600_store_context_reg(cb
, R_028234_PA_SU_HARDWARE_SCREEN_OFFSET
, 0);
2733 r600_store_context_reg(cb
, R_0286C8_SPI_THREAD_GROUPING
, 0);
2734 r600_store_context_reg_seq(cb
, R_0286E4_SPI_PS_IN_CONTROL_2
, 2);
2735 r600_store_value(cb
, 0); /* R_0286E4_SPI_PS_IN_CONTROL_2 */
2736 r600_store_value(cb
, 0); /* R_0286E8_SPI_COMPUTE_INPUT_CNTL */
2738 r600_store_context_reg_seq(cb
, R_028B54_VGT_SHADER_STAGES_EN
, 2);
2739 r600_store_value(cb
, 0); /* R028B54_VGT_SHADER_STAGES_EN */
2740 r600_store_value(cb
, 0); /* R028B58_VGT_LS_HS_CONFIG */
2741 r600_store_context_reg(cb
, R_028B6C_VGT_TF_PARAM
, 0);
2742 eg_store_loop_const(cb
, R_03A200_SQ_LOOP_CONST_0
, 0x01000FFF);
2743 eg_store_loop_const(cb
, R_03A200_SQ_LOOP_CONST_0
+ (32 * 4), 0x01000FFF);
2744 eg_store_loop_const(cb
, R_03A200_SQ_LOOP_CONST_0
+ (64 * 4), 0x01000FFF);
2745 eg_store_loop_const(cb
, R_03A200_SQ_LOOP_CONST_0
+ (96 * 4), 0x01000FFF);
2746 eg_store_loop_const(cb
, R_03A200_SQ_LOOP_CONST_0
+ (128 * 4), 0x01000FFF);
2749 void evergreen_init_common_regs(struct r600_context
*rctx
, struct r600_command_buffer
*cb
,
2750 enum chip_class ctx_chip_class
,
2751 enum radeon_family ctx_family
,
2773 rctx
->default_gprs
[R600_HW_STAGE_PS
] = 93;
2774 rctx
->default_gprs
[R600_HW_STAGE_VS
] = 46;
2775 rctx
->r6xx_num_clause_temp_gprs
= 4;
2776 rctx
->default_gprs
[R600_HW_STAGE_GS
] = 31;
2777 rctx
->default_gprs
[R600_HW_STAGE_ES
] = 31;
2778 rctx
->default_gprs
[EG_HW_STAGE_HS
] = 23;
2779 rctx
->default_gprs
[EG_HW_STAGE_LS
] = 23;
2782 switch (ctx_family
) {
2790 tmp
|= S_008C00_VC_ENABLE(1);
2793 tmp
|= S_008C00_EXPORT_SRC_C(1);
2794 tmp
|= S_008C00_CS_PRIO(cs_prio
);
2795 tmp
|= S_008C00_LS_PRIO(ls_prio
);
2796 tmp
|= S_008C00_HS_PRIO(hs_prio
);
2797 tmp
|= S_008C00_PS_PRIO(ps_prio
);
2798 tmp
|= S_008C00_VS_PRIO(vs_prio
);
2799 tmp
|= S_008C00_GS_PRIO(gs_prio
);
2800 tmp
|= S_008C00_ES_PRIO(es_prio
);
2802 r600_store_config_reg_seq(cb
, R_008C00_SQ_CONFIG
, 1);
2803 r600_store_value(cb
, tmp
); /* R_008C00_SQ_CONFIG */
2805 r600_store_config_reg_seq(cb
, R_008C10_SQ_GLOBAL_GPR_RESOURCE_MGMT_1
, 2);
2806 r600_store_value(cb
, 0); /* R_008C10_SQ_GLOBAL_GPR_RESOURCE_MGMT_1 */
2807 r600_store_value(cb
, 0); /* R_008C14_SQ_GLOBAL_GPR_RESOURCE_MGMT_2 */
2809 /* The cs checker requires this register to be set. */
2810 r600_store_context_reg(cb
, R_028800_DB_DEPTH_CONTROL
, 0);
2812 r600_store_context_reg_seq(cb
, R_028350_SX_MISC
, 2);
2813 r600_store_value(cb
, 0);
2814 r600_store_value(cb
, S_028354_SURFACE_SYNC_MASK(0xf));
2819 void evergreen_init_atom_start_cs(struct r600_context
*rctx
)
2821 struct r600_command_buffer
*cb
= &rctx
->start_cs_cmd
;
2829 int num_ps_stack_entries
;
2830 int num_vs_stack_entries
;
2831 int num_gs_stack_entries
;
2832 int num_es_stack_entries
;
2833 int num_hs_stack_entries
;
2834 int num_ls_stack_entries
;
2835 enum radeon_family family
;
2838 if (rctx
->b
.chip_class
== CAYMAN
) {
2839 cayman_init_atom_start_cs(rctx
);
2843 r600_init_command_buffer(cb
, 338);
2845 /* This must be first. */
2846 r600_store_value(cb
, PKT3(PKT3_CONTEXT_CONTROL
, 1, 0));
2847 r600_store_value(cb
, 0x80000000);
2848 r600_store_value(cb
, 0x80000000);
2850 /* We're setting config registers here. */
2851 r600_store_value(cb
, PKT3(PKT3_EVENT_WRITE
, 0, 0));
2852 r600_store_value(cb
, EVENT_TYPE(EVENT_TYPE_PS_PARTIAL_FLUSH
) | EVENT_INDEX(4));
2854 /* This enables pipeline stat & streamout queries.
2855 * They are only disabled by blits.
2857 r600_store_value(cb
, PKT3(PKT3_EVENT_WRITE
, 0, 0));
2858 r600_store_value(cb
, EVENT_TYPE(EVENT_TYPE_PIPELINESTAT_START
) | EVENT_INDEX(0));
2860 evergreen_init_common_regs(rctx
, cb
, rctx
->b
.chip_class
,
2861 rctx
->b
.family
, rctx
->screen
->b
.info
.drm_minor
);
2863 family
= rctx
->b
.family
;
2867 num_ps_threads
= 96;
2868 num_vs_threads
= 16;
2869 num_gs_threads
= 16;
2870 num_es_threads
= 16;
2871 num_hs_threads
= 16;
2872 num_ls_threads
= 16;
2873 num_ps_stack_entries
= 42;
2874 num_vs_stack_entries
= 42;
2875 num_gs_stack_entries
= 42;
2876 num_es_stack_entries
= 42;
2877 num_hs_stack_entries
= 42;
2878 num_ls_stack_entries
= 42;
2881 num_ps_threads
= 128;
2882 num_vs_threads
= 20;
2883 num_gs_threads
= 20;
2884 num_es_threads
= 20;
2885 num_hs_threads
= 20;
2886 num_ls_threads
= 20;
2887 num_ps_stack_entries
= 42;
2888 num_vs_stack_entries
= 42;
2889 num_gs_stack_entries
= 42;
2890 num_es_stack_entries
= 42;
2891 num_hs_stack_entries
= 42;
2892 num_ls_stack_entries
= 42;
2895 num_ps_threads
= 128;
2896 num_vs_threads
= 20;
2897 num_gs_threads
= 20;
2898 num_es_threads
= 20;
2899 num_hs_threads
= 20;
2900 num_ls_threads
= 20;
2901 num_ps_stack_entries
= 85;
2902 num_vs_stack_entries
= 85;
2903 num_gs_stack_entries
= 85;
2904 num_es_stack_entries
= 85;
2905 num_hs_stack_entries
= 85;
2906 num_ls_stack_entries
= 85;
2910 num_ps_threads
= 128;
2911 num_vs_threads
= 20;
2912 num_gs_threads
= 20;
2913 num_es_threads
= 20;
2914 num_hs_threads
= 20;
2915 num_ls_threads
= 20;
2916 num_ps_stack_entries
= 85;
2917 num_vs_stack_entries
= 85;
2918 num_gs_stack_entries
= 85;
2919 num_es_stack_entries
= 85;
2920 num_hs_stack_entries
= 85;
2921 num_ls_stack_entries
= 85;
2924 num_ps_threads
= 96;
2925 num_vs_threads
= 16;
2926 num_gs_threads
= 16;
2927 num_es_threads
= 16;
2928 num_hs_threads
= 16;
2929 num_ls_threads
= 16;
2930 num_ps_stack_entries
= 42;
2931 num_vs_stack_entries
= 42;
2932 num_gs_stack_entries
= 42;
2933 num_es_stack_entries
= 42;
2934 num_hs_stack_entries
= 42;
2935 num_ls_stack_entries
= 42;
2938 num_ps_threads
= 96;
2939 num_vs_threads
= 25;
2940 num_gs_threads
= 25;
2941 num_es_threads
= 25;
2942 num_hs_threads
= 16;
2943 num_ls_threads
= 16;
2944 num_ps_stack_entries
= 42;
2945 num_vs_stack_entries
= 42;
2946 num_gs_stack_entries
= 42;
2947 num_es_stack_entries
= 42;
2948 num_hs_stack_entries
= 42;
2949 num_ls_stack_entries
= 42;
2952 num_ps_threads
= 96;
2953 num_vs_threads
= 25;
2954 num_gs_threads
= 25;
2955 num_es_threads
= 25;
2956 num_hs_threads
= 16;
2957 num_ls_threads
= 16;
2958 num_ps_stack_entries
= 85;
2959 num_vs_stack_entries
= 85;
2960 num_gs_stack_entries
= 85;
2961 num_es_stack_entries
= 85;
2962 num_hs_stack_entries
= 85;
2963 num_ls_stack_entries
= 85;
2966 num_ps_threads
= 128;
2967 num_vs_threads
= 20;
2968 num_gs_threads
= 20;
2969 num_es_threads
= 20;
2970 num_hs_threads
= 20;
2971 num_ls_threads
= 20;
2972 num_ps_stack_entries
= 85;
2973 num_vs_stack_entries
= 85;
2974 num_gs_stack_entries
= 85;
2975 num_es_stack_entries
= 85;
2976 num_hs_stack_entries
= 85;
2977 num_ls_stack_entries
= 85;
2980 num_ps_threads
= 128;
2981 num_vs_threads
= 20;
2982 num_gs_threads
= 20;
2983 num_es_threads
= 20;
2984 num_hs_threads
= 20;
2985 num_ls_threads
= 20;
2986 num_ps_stack_entries
= 42;
2987 num_vs_stack_entries
= 42;
2988 num_gs_stack_entries
= 42;
2989 num_es_stack_entries
= 42;
2990 num_hs_stack_entries
= 42;
2991 num_ls_stack_entries
= 42;
2994 num_ps_threads
= 96;
2995 num_vs_threads
= 10;
2996 num_gs_threads
= 10;
2997 num_es_threads
= 10;
2998 num_hs_threads
= 10;
2999 num_ls_threads
= 10;
3000 num_ps_stack_entries
= 42;
3001 num_vs_stack_entries
= 42;
3002 num_gs_stack_entries
= 42;
3003 num_es_stack_entries
= 42;
3004 num_hs_stack_entries
= 42;
3005 num_ls_stack_entries
= 42;
3009 tmp
= S_008C18_NUM_PS_THREADS(num_ps_threads
);
3010 tmp
|= S_008C18_NUM_VS_THREADS(num_vs_threads
);
3011 tmp
|= S_008C18_NUM_GS_THREADS(num_gs_threads
);
3012 tmp
|= S_008C18_NUM_ES_THREADS(num_es_threads
);
3014 r600_store_config_reg_seq(cb
, R_008C18_SQ_THREAD_RESOURCE_MGMT_1
, 5);
3015 r600_store_value(cb
, tmp
); /* R_008C18_SQ_THREAD_RESOURCE_MGMT_1 */
3017 tmp
= S_008C1C_NUM_HS_THREADS(num_hs_threads
);
3018 tmp
|= S_008C1C_NUM_LS_THREADS(num_ls_threads
);
3019 r600_store_value(cb
, tmp
); /* R_008C1C_SQ_THREAD_RESOURCE_MGMT_2 */
3021 tmp
= S_008C20_NUM_PS_STACK_ENTRIES(num_ps_stack_entries
);
3022 tmp
|= S_008C20_NUM_VS_STACK_ENTRIES(num_vs_stack_entries
);
3023 r600_store_value(cb
, tmp
); /* R_008C20_SQ_STACK_RESOURCE_MGMT_1 */
3025 tmp
= S_008C24_NUM_GS_STACK_ENTRIES(num_gs_stack_entries
);
3026 tmp
|= S_008C24_NUM_ES_STACK_ENTRIES(num_es_stack_entries
);
3027 r600_store_value(cb
, tmp
); /* R_008C24_SQ_STACK_RESOURCE_MGMT_2 */
3029 tmp
= S_008C28_NUM_HS_STACK_ENTRIES(num_hs_stack_entries
);
3030 tmp
|= S_008C28_NUM_LS_STACK_ENTRIES(num_ls_stack_entries
);
3031 r600_store_value(cb
, tmp
); /* R_008C28_SQ_STACK_RESOURCE_MGMT_3 */
3033 r600_store_config_reg(cb
, R_008E2C_SQ_LDS_RESOURCE_MGMT
,
3034 S_008E2C_NUM_PS_LDS(0x1000) | S_008E2C_NUM_LS_LDS(0x1000));
3036 /* remove LS/HS from one SIMD for hw workaround */
3037 r600_store_config_reg_seq(cb
, R_008E20_SQ_STATIC_THREAD_MGMT1
, 3);
3038 r600_store_value(cb
, 0xffffffff);
3039 r600_store_value(cb
, 0xffffffff);
3040 r600_store_value(cb
, 0xfffffffe);
3042 r600_store_config_reg(cb
, R_009100_SPI_CONFIG_CNTL
, 0);
3043 r600_store_config_reg(cb
, R_00913C_SPI_CONFIG_CNTL_1
, S_00913C_VTX_DONE_DELAY(4));
3045 r600_store_context_reg_seq(cb
, R_028900_SQ_ESGS_RING_ITEMSIZE
, 6);
3046 r600_store_value(cb
, 0); /* R_028900_SQ_ESGS_RING_ITEMSIZE */
3047 r600_store_value(cb
, 0); /* R_028904_SQ_GSVS_RING_ITEMSIZE */
3048 r600_store_value(cb
, 0); /* R_028908_SQ_ESTMP_RING_ITEMSIZE */
3049 r600_store_value(cb
, 0); /* R_02890C_SQ_GSTMP_RING_ITEMSIZE */
3050 r600_store_value(cb
, 0); /* R_028910_SQ_VSTMP_RING_ITEMSIZE */
3051 r600_store_value(cb
, 0); /* R_028914_SQ_PSTMP_RING_ITEMSIZE */
3053 r600_store_context_reg_seq(cb
, R_02891C_SQ_GS_VERT_ITEMSIZE
, 4);
3054 r600_store_value(cb
, 0); /* R_02891C_SQ_GS_VERT_ITEMSIZE */
3055 r600_store_value(cb
, 0); /* R_028920_SQ_GS_VERT_ITEMSIZE_1 */
3056 r600_store_value(cb
, 0); /* R_028924_SQ_GS_VERT_ITEMSIZE_2 */
3057 r600_store_value(cb
, 0); /* R_028928_SQ_GS_VERT_ITEMSIZE_3 */
3059 r600_store_context_reg_seq(cb
, R_028A10_VGT_OUTPUT_PATH_CNTL
, 13);
3060 r600_store_value(cb
, 0); /* R_028A10_VGT_OUTPUT_PATH_CNTL */
3061 r600_store_value(cb
, 0); /* R_028A14_VGT_HOS_CNTL */
3062 r600_store_value(cb
, fui(64)); /* R_028A18_VGT_HOS_MAX_TESS_LEVEL */
3063 r600_store_value(cb
, fui(1.0)); /* R_028A1C_VGT_HOS_MIN_TESS_LEVEL */
3064 r600_store_value(cb
, 16); /* R_028A20_VGT_HOS_REUSE_DEPTH */
3065 r600_store_value(cb
, 0); /* R_028A24_VGT_GROUP_PRIM_TYPE */
3066 r600_store_value(cb
, 0); /* R_028A28_VGT_GROUP_FIRST_DECR */
3067 r600_store_value(cb
, 0); /* R_028A2C_VGT_GROUP_DECR */
3068 r600_store_value(cb
, 0); /* R_028A30_VGT_GROUP_VECT_0_CNTL */
3069 r600_store_value(cb
, 0); /* R_028A34_VGT_GROUP_VECT_1_CNTL */
3070 r600_store_value(cb
, 0); /* R_028A38_VGT_GROUP_VECT_0_FMT_CNTL */
3071 r600_store_value(cb
, 0); /* R_028A3C_VGT_GROUP_VECT_1_FMT_CNTL */
3072 r600_store_value(cb
, 0); /* R_028A40_VGT_GS_MODE */
3074 r600_store_config_reg(cb
, R_008A14_PA_CL_ENHANCE
, (3 << 1) | 1);
3076 r600_store_context_reg(cb
, R_0288F0_SQ_VTX_SEMANTIC_CLEAR
, ~0);
3078 r600_store_context_reg_seq(cb
, R_028400_VGT_MAX_VTX_INDX
, 2);
3079 r600_store_value(cb
, ~0); /* R_028400_VGT_MAX_VTX_INDX */
3080 r600_store_value(cb
, 0); /* R_028404_VGT_MIN_VTX_INDX */
3082 r600_store_ctl_const(cb
, R_03CFF0_SQ_VTX_BASE_VTX_LOC
, 0);
3084 r600_store_context_reg(cb
, R_028028_DB_STENCIL_CLEAR
, 0);
3086 r600_store_context_reg(cb
, R_028200_PA_SC_WINDOW_OFFSET
, 0);
3087 r600_store_context_reg(cb
, R_02820C_PA_SC_CLIPRECT_RULE
, 0xFFFF);
3088 r600_store_context_reg(cb
, R_028230_PA_SC_EDGERULE
, 0xAAAAAAAA);
3090 r600_store_context_reg(cb
, R_0286DC_SPI_FOG_CNTL
, 0);
3091 r600_store_context_reg(cb
, R_028820_PA_CL_NANINF_CNTL
, 0);
3093 r600_store_context_reg_seq(cb
, R_028AC0_DB_SRESULTS_COMPARE_STATE0
, 3);
3094 r600_store_value(cb
, 0); /* R_028AC0_DB_SRESULTS_COMPARE_STATE0 */
3095 r600_store_value(cb
, 0); /* R_028AC4_DB_SRESULTS_COMPARE_STATE1 */
3096 r600_store_value(cb
, 0); /* R_028AC8_DB_PRELOAD_CONTROL */
3098 r600_store_context_reg_seq(cb
, R_028240_PA_SC_GENERIC_SCISSOR_TL
, 2);
3099 r600_store_value(cb
, 0); /* R_028240_PA_SC_GENERIC_SCISSOR_TL */
3100 r600_store_value(cb
, S_028244_BR_X(16384) | S_028244_BR_Y(16384)); /* R_028244_PA_SC_GENERIC_SCISSOR_BR */
3102 r600_store_context_reg_seq(cb
, R_028030_PA_SC_SCREEN_SCISSOR_TL
, 2);
3103 r600_store_value(cb
, 0); /* R_028030_PA_SC_SCREEN_SCISSOR_TL */
3104 r600_store_value(cb
, S_028034_BR_X(16384) | S_028034_BR_Y(16384)); /* R_028034_PA_SC_SCREEN_SCISSOR_BR */
3106 r600_store_context_reg(cb
, R_028848_SQ_PGM_RESOURCES_2_PS
, S_028848_SINGLE_ROUND(V_SQ_ROUND_NEAREST_EVEN
));
3107 r600_store_context_reg(cb
, R_028864_SQ_PGM_RESOURCES_2_VS
, S_028864_SINGLE_ROUND(V_SQ_ROUND_NEAREST_EVEN
));
3108 r600_store_context_reg(cb
, R_02887C_SQ_PGM_RESOURCES_2_GS
, S_028848_SINGLE_ROUND(V_SQ_ROUND_NEAREST_EVEN
));
3109 r600_store_context_reg(cb
, R_028894_SQ_PGM_RESOURCES_2_ES
, S_028848_SINGLE_ROUND(V_SQ_ROUND_NEAREST_EVEN
));
3110 r600_store_context_reg(cb
, R_0288A8_SQ_PGM_RESOURCES_FS
, 0);
3111 r600_store_context_reg(cb
, R_0288C0_SQ_PGM_RESOURCES_2_HS
, S_028848_SINGLE_ROUND(V_SQ_ROUND_NEAREST_EVEN
));
3112 r600_store_context_reg(cb
, R_0288D8_SQ_PGM_RESOURCES_2_LS
, S_028848_SINGLE_ROUND(V_SQ_ROUND_NEAREST_EVEN
));
3114 /* to avoid GPU doing any preloading of constant from random address */
3115 r600_store_context_reg_seq(cb
, R_028140_ALU_CONST_BUFFER_SIZE_PS_0
, 16);
3116 for (i
= 0; i
< 16; i
++)
3117 r600_store_value(cb
, 0);
3119 r600_store_context_reg_seq(cb
, R_028180_ALU_CONST_BUFFER_SIZE_VS_0
, 16);
3120 for (i
= 0; i
< 16; i
++)
3121 r600_store_value(cb
, 0);
3123 r600_store_context_reg_seq(cb
, R_0281C0_ALU_CONST_BUFFER_SIZE_GS_0
, 16);
3124 for (i
= 0; i
< 16; i
++)
3125 r600_store_value(cb
, 0);
3127 r600_store_context_reg_seq(cb
, R_028FC0_ALU_CONST_BUFFER_SIZE_LS_0
, 16);
3128 for (i
= 0; i
< 16; i
++)
3129 r600_store_value(cb
, 0);
3131 r600_store_context_reg_seq(cb
, R_028F80_ALU_CONST_BUFFER_SIZE_HS_0
, 16);
3132 for (i
= 0; i
< 16; i
++)
3133 r600_store_value(cb
, 0);
3135 r600_store_context_reg(cb
, R_028B98_VGT_STRMOUT_BUFFER_CONFIG
, 0);
3137 if (rctx
->screen
->b
.has_streamout
) {
3138 r600_store_context_reg(cb
, R_028B28_VGT_STRMOUT_DRAW_OPAQUE_OFFSET
, 0);
3141 r600_store_context_reg(cb
, R_028010_DB_RENDER_OVERRIDE2
, 0);
3142 r600_store_context_reg(cb
, R_028234_PA_SU_HARDWARE_SCREEN_OFFSET
, 0);
3143 r600_store_context_reg(cb
, R_0286C8_SPI_THREAD_GROUPING
, 0);
3144 r600_store_context_reg_seq(cb
, R_0286E4_SPI_PS_IN_CONTROL_2
, 2);
3145 r600_store_value(cb
, 0); /* R_0286E4_SPI_PS_IN_CONTROL_2 */
3146 r600_store_value(cb
, 0); /* R_0286E8_SPI_COMPUTE_INPUT_CNTL */
3148 r600_store_context_reg_seq(cb
, R_0288E8_SQ_LDS_ALLOC
, 2);
3149 r600_store_value(cb
, 0); /* R_0288E8_SQ_LDS_ALLOC */
3150 r600_store_value(cb
, 0); /* R_0288EC_SQ_LDS_ALLOC_PS */
3152 if (rctx
->b
.family
== CHIP_CAICOS
) {
3153 r600_store_context_reg_seq(cb
, R_028B54_VGT_SHADER_STAGES_EN
, 2);
3154 r600_store_value(cb
, 0); /* R028B54_VGT_SHADER_STAGES_EN */
3155 r600_store_value(cb
, 0); /* R028B58_VGT_LS_HS_CONFIG */
3156 r600_store_context_reg(cb
, R_028B6C_VGT_TF_PARAM
, 0);
3158 r600_store_context_reg_seq(cb
, R_028B54_VGT_SHADER_STAGES_EN
, 7);
3159 r600_store_value(cb
, 0); /* R028B54_VGT_SHADER_STAGES_EN */
3160 r600_store_value(cb
, 0); /* R028B58_VGT_LS_HS_CONFIG */
3161 r600_store_value(cb
, 0); /* R028B5C_VGT_LS_SIZE */
3162 r600_store_value(cb
, 0); /* R028B60_VGT_HS_SIZE */
3163 r600_store_value(cb
, 0); /* R028B64_VGT_LS_HS_ALLOC */
3164 r600_store_value(cb
, 0); /* R028B68_VGT_HS_PATCH_CONST */
3165 r600_store_value(cb
, 0); /* R028B68_VGT_TF_PARAM */
3168 eg_store_loop_const(cb
, R_03A200_SQ_LOOP_CONST_0
, 0x01000FFF);
3169 eg_store_loop_const(cb
, R_03A200_SQ_LOOP_CONST_0
+ (32 * 4), 0x01000FFF);
3170 eg_store_loop_const(cb
, R_03A200_SQ_LOOP_CONST_0
+ (64 * 4), 0x01000FFF);
3171 eg_store_loop_const(cb
, R_03A200_SQ_LOOP_CONST_0
+ (96 * 4), 0x01000FFF);
3172 eg_store_loop_const(cb
, R_03A200_SQ_LOOP_CONST_0
+ (128 * 4), 0x01000FFF);
3175 void evergreen_update_ps_state(struct pipe_context
*ctx
, struct r600_pipe_shader
*shader
)
3177 struct r600_context
*rctx
= (struct r600_context
*)ctx
;
3178 struct r600_command_buffer
*cb
= &shader
->command_buffer
;
3179 struct r600_shader
*rshader
= &shader
->shader
;
3180 unsigned i
, exports_ps
, num_cout
, spi_ps_in_control_0
, spi_input_z
, spi_ps_in_control_1
, db_shader_control
= 0;
3181 int pos_index
= -1, face_index
= -1, fixed_pt_position_index
= -1;
3183 boolean have_perspective
= FALSE
, have_linear
= FALSE
;
3184 static const unsigned spi_baryc_enable_bit
[6] = {
3185 S_0286E0_PERSP_SAMPLE_ENA(1),
3186 S_0286E0_PERSP_CENTER_ENA(1),
3187 S_0286E0_PERSP_CENTROID_ENA(1),
3188 S_0286E0_LINEAR_SAMPLE_ENA(1),
3189 S_0286E0_LINEAR_CENTER_ENA(1),
3190 S_0286E0_LINEAR_CENTROID_ENA(1)
3192 unsigned spi_baryc_cntl
= 0, sid
, tmp
, num
= 0;
3193 unsigned z_export
= 0, stencil_export
= 0, mask_export
= 0;
3194 unsigned sprite_coord_enable
= rctx
->rasterizer
? rctx
->rasterizer
->sprite_coord_enable
: 0;
3195 uint32_t spi_ps_input_cntl
[32];
3198 r600_init_command_buffer(cb
, 64);
3203 for (i
= 0; i
< rshader
->ninput
; i
++) {
3204 /* evergreen NUM_INTERP only contains values interpolated into the LDS,
3205 POSITION goes via GPRs from the SC so isn't counted */
3206 if (rshader
->input
[i
].name
== TGSI_SEMANTIC_POSITION
)
3208 else if (rshader
->input
[i
].name
== TGSI_SEMANTIC_FACE
) {
3209 if (face_index
== -1)
3212 else if (rshader
->input
[i
].name
== TGSI_SEMANTIC_SAMPLEMASK
) {
3213 if (face_index
== -1)
3214 face_index
= i
; /* lives in same register, same enable bit */
3216 else if (rshader
->input
[i
].name
== TGSI_SEMANTIC_SAMPLEID
) {
3217 fixed_pt_position_index
= i
;
3221 int k
= eg_get_interpolator_index(
3222 rshader
->input
[i
].interpolate
,
3223 rshader
->input
[i
].interpolate_location
);
3225 spi_baryc_cntl
|= spi_baryc_enable_bit
[k
];
3226 have_perspective
|= k
< 3;
3227 have_linear
|= !(k
< 3);
3231 sid
= rshader
->input
[i
].spi_sid
;
3234 tmp
= S_028644_SEMANTIC(sid
);
3236 /* D3D 9 behaviour. GL is undefined */
3237 if (rshader
->input
[i
].name
== TGSI_SEMANTIC_COLOR
&& rshader
->input
[i
].sid
== 0)
3238 tmp
|= S_028644_DEFAULT_VAL(3);
3240 if (rshader
->input
[i
].name
== TGSI_SEMANTIC_POSITION
||
3241 rshader
->input
[i
].interpolate
== TGSI_INTERPOLATE_CONSTANT
||
3242 (rshader
->input
[i
].interpolate
== TGSI_INTERPOLATE_COLOR
&&
3243 rctx
->rasterizer
&& rctx
->rasterizer
->flatshade
)) {
3244 tmp
|= S_028644_FLAT_SHADE(1);
3247 if (rshader
->input
[i
].name
== TGSI_SEMANTIC_GENERIC
&&
3248 (sprite_coord_enable
& (1 << rshader
->input
[i
].sid
))) {
3249 tmp
|= S_028644_PT_SPRITE_TEX(1);
3252 spi_ps_input_cntl
[num
++] = tmp
;
3256 r600_store_context_reg_seq(cb
, R_028644_SPI_PS_INPUT_CNTL_0
, num
);
3257 r600_store_array(cb
, num
, spi_ps_input_cntl
);
3259 for (i
= 0; i
< rshader
->noutput
; i
++) {
3260 if (rshader
->output
[i
].name
== TGSI_SEMANTIC_POSITION
)
3262 if (rshader
->output
[i
].name
== TGSI_SEMANTIC_STENCIL
)
3264 if (rshader
->output
[i
].name
== TGSI_SEMANTIC_SAMPLEMASK
&&
3265 rctx
->framebuffer
.nr_samples
> 1 && rctx
->ps_iter_samples
> 0)
3268 if (rshader
->uses_kill
)
3269 db_shader_control
|= S_02880C_KILL_ENABLE(1);
3271 db_shader_control
|= S_02880C_Z_EXPORT_ENABLE(z_export
);
3272 db_shader_control
|= S_02880C_STENCIL_EXPORT_ENABLE(stencil_export
);
3273 db_shader_control
|= S_02880C_MASK_EXPORT_ENABLE(mask_export
);
3275 if (shader
->selector
->info
.properties
[TGSI_PROPERTY_FS_EARLY_DEPTH_STENCIL
]) {
3276 db_shader_control
|= S_02880C_DEPTH_BEFORE_SHADER(1) |
3277 S_02880C_EXEC_ON_NOOP(shader
->selector
->info
.writes_memory
);
3278 } else if (shader
->selector
->info
.writes_memory
) {
3279 db_shader_control
|= S_02880C_EXEC_ON_HIER_FAIL(1);
3282 switch (rshader
->ps_conservative_z
) {
3283 default: /* fall through */
3284 case TGSI_FS_DEPTH_LAYOUT_ANY
:
3285 db_shader_control
|= S_02880C_CONSERVATIVE_Z_EXPORT(V_02880C_EXPORT_ANY_Z
);
3287 case TGSI_FS_DEPTH_LAYOUT_GREATER
:
3288 db_shader_control
|= S_02880C_CONSERVATIVE_Z_EXPORT(V_02880C_EXPORT_GREATER_THAN_Z
);
3290 case TGSI_FS_DEPTH_LAYOUT_LESS
:
3291 db_shader_control
|= S_02880C_CONSERVATIVE_Z_EXPORT(V_02880C_EXPORT_LESS_THAN_Z
);
3296 for (i
= 0; i
< rshader
->noutput
; i
++) {
3297 if (rshader
->output
[i
].name
== TGSI_SEMANTIC_POSITION
||
3298 rshader
->output
[i
].name
== TGSI_SEMANTIC_STENCIL
||
3299 rshader
->output
[i
].name
== TGSI_SEMANTIC_SAMPLEMASK
)
3303 num_cout
= rshader
->nr_ps_color_exports
;
3305 exports_ps
|= S_02884C_EXPORT_COLORS(num_cout
);
3307 /* always at least export 1 component per pixel */
3310 shader
->nr_ps_color_outputs
= num_cout
;
3313 have_perspective
= TRUE
;
3315 if (!spi_baryc_cntl
)
3316 spi_baryc_cntl
|= spi_baryc_enable_bit
[0];
3318 if (!have_perspective
&& !have_linear
)
3319 have_perspective
= TRUE
;
3321 spi_ps_in_control_0
= S_0286CC_NUM_INTERP(ninterp
) |
3322 S_0286CC_PERSP_GRADIENT_ENA(have_perspective
) |
3323 S_0286CC_LINEAR_GRADIENT_ENA(have_linear
);
3325 if (pos_index
!= -1) {
3326 spi_ps_in_control_0
|= S_0286CC_POSITION_ENA(1) |
3327 S_0286CC_POSITION_CENTROID(rshader
->input
[pos_index
].interpolate_location
== TGSI_INTERPOLATE_LOC_CENTROID
) |
3328 S_0286CC_POSITION_ADDR(rshader
->input
[pos_index
].gpr
);
3329 spi_input_z
|= S_0286D8_PROVIDE_Z_TO_SPI(1);
3332 spi_ps_in_control_1
= 0;
3333 if (face_index
!= -1) {
3334 spi_ps_in_control_1
|= S_0286D0_FRONT_FACE_ENA(1) |
3335 S_0286D0_FRONT_FACE_ADDR(rshader
->input
[face_index
].gpr
);
3337 if (fixed_pt_position_index
!= -1) {
3338 spi_ps_in_control_1
|= S_0286D0_FIXED_PT_POSITION_ENA(1) |
3339 S_0286D0_FIXED_PT_POSITION_ADDR(rshader
->input
[fixed_pt_position_index
].gpr
);
3342 r600_store_context_reg_seq(cb
, R_0286CC_SPI_PS_IN_CONTROL_0
, 2);
3343 r600_store_value(cb
, spi_ps_in_control_0
); /* R_0286CC_SPI_PS_IN_CONTROL_0 */
3344 r600_store_value(cb
, spi_ps_in_control_1
); /* R_0286D0_SPI_PS_IN_CONTROL_1 */
3346 r600_store_context_reg(cb
, R_0286E0_SPI_BARYC_CNTL
, spi_baryc_cntl
);
3347 r600_store_context_reg(cb
, R_0286D8_SPI_INPUT_Z
, spi_input_z
);
3348 r600_store_context_reg(cb
, R_02884C_SQ_PGM_EXPORTS_PS
, exports_ps
);
3350 r600_store_context_reg_seq(cb
, R_028840_SQ_PGM_START_PS
, 2);
3351 r600_store_value(cb
, shader
->bo
->gpu_address
>> 8);
3352 r600_store_value(cb
, /* R_028844_SQ_PGM_RESOURCES_PS */
3353 S_028844_NUM_GPRS(rshader
->bc
.ngpr
) |
3354 S_028844_PRIME_CACHE_ON_DRAW(1) |
3355 S_028844_DX10_CLAMP(1) |
3356 S_028844_STACK_SIZE(rshader
->bc
.nstack
));
3357 /* After that, the NOP relocation packet must be emitted (shader->bo, RADEON_USAGE_READ). */
3359 shader
->db_shader_control
= db_shader_control
;
3360 shader
->ps_depth_export
= z_export
| stencil_export
| mask_export
;
3362 shader
->sprite_coord_enable
= sprite_coord_enable
;
3363 if (rctx
->rasterizer
)
3364 shader
->flatshade
= rctx
->rasterizer
->flatshade
;
3367 void evergreen_update_es_state(struct pipe_context
*ctx
, struct r600_pipe_shader
*shader
)
3369 struct r600_command_buffer
*cb
= &shader
->command_buffer
;
3370 struct r600_shader
*rshader
= &shader
->shader
;
3372 r600_init_command_buffer(cb
, 32);
3374 r600_store_context_reg(cb
, R_028890_SQ_PGM_RESOURCES_ES
,
3375 S_028890_NUM_GPRS(rshader
->bc
.ngpr
) |
3376 S_028890_DX10_CLAMP(1) |
3377 S_028890_STACK_SIZE(rshader
->bc
.nstack
));
3378 r600_store_context_reg(cb
, R_02888C_SQ_PGM_START_ES
,
3379 shader
->bo
->gpu_address
>> 8);
3380 /* After that, the NOP relocation packet must be emitted (shader->bo, RADEON_USAGE_READ). */
3383 void evergreen_update_gs_state(struct pipe_context
*ctx
, struct r600_pipe_shader
*shader
)
3385 struct r600_context
*rctx
= (struct r600_context
*)ctx
;
3386 struct r600_command_buffer
*cb
= &shader
->command_buffer
;
3387 struct r600_shader
*rshader
= &shader
->shader
;
3388 struct r600_shader
*cp_shader
= &shader
->gs_copy_shader
->shader
;
3389 unsigned gsvs_itemsizes
[4] = {
3390 (cp_shader
->ring_item_sizes
[0] * shader
->selector
->gs_max_out_vertices
) >> 2,
3391 (cp_shader
->ring_item_sizes
[1] * shader
->selector
->gs_max_out_vertices
) >> 2,
3392 (cp_shader
->ring_item_sizes
[2] * shader
->selector
->gs_max_out_vertices
) >> 2,
3393 (cp_shader
->ring_item_sizes
[3] * shader
->selector
->gs_max_out_vertices
) >> 2
3396 r600_init_command_buffer(cb
, 64);
3398 /* VGT_GS_MODE is written by evergreen_emit_shader_stages */
3401 r600_store_context_reg(cb
, R_028B38_VGT_GS_MAX_VERT_OUT
,
3402 S_028B38_MAX_VERT_OUT(shader
->selector
->gs_max_out_vertices
));
3403 r600_store_context_reg(cb
, R_028A6C_VGT_GS_OUT_PRIM_TYPE
,
3404 r600_conv_prim_to_gs_out(shader
->selector
->gs_output_prim
));
3406 if (rctx
->screen
->b
.info
.drm_minor
>= 35) {
3407 r600_store_context_reg(cb
, R_028B90_VGT_GS_INSTANCE_CNT
,
3408 S_028B90_CNT(MIN2(shader
->selector
->gs_num_invocations
, 127)) |
3409 S_028B90_ENABLE(shader
->selector
->gs_num_invocations
> 0));
3411 r600_store_context_reg_seq(cb
, R_02891C_SQ_GS_VERT_ITEMSIZE
, 4);
3412 r600_store_value(cb
, cp_shader
->ring_item_sizes
[0] >> 2);
3413 r600_store_value(cb
, cp_shader
->ring_item_sizes
[1] >> 2);
3414 r600_store_value(cb
, cp_shader
->ring_item_sizes
[2] >> 2);
3415 r600_store_value(cb
, cp_shader
->ring_item_sizes
[3] >> 2);
3417 r600_store_context_reg(cb
, R_028900_SQ_ESGS_RING_ITEMSIZE
,
3418 (rshader
->ring_item_sizes
[0]) >> 2);
3420 r600_store_context_reg(cb
, R_028904_SQ_GSVS_RING_ITEMSIZE
,
3426 r600_store_context_reg_seq(cb
, R_02892C_SQ_GSVS_RING_OFFSET_1
, 3);
3427 r600_store_value(cb
, gsvs_itemsizes
[0]);
3428 r600_store_value(cb
, gsvs_itemsizes
[0] + gsvs_itemsizes
[1]);
3429 r600_store_value(cb
, gsvs_itemsizes
[0] + gsvs_itemsizes
[1] + gsvs_itemsizes
[2]);
3431 /* FIXME calculate these values somehow ??? */
3432 r600_store_context_reg_seq(cb
, R_028A54_GS_PER_ES
, 3);
3433 r600_store_value(cb
, 0x80); /* GS_PER_ES */
3434 r600_store_value(cb
, 0x100); /* ES_PER_GS */
3435 r600_store_value(cb
, 0x2); /* GS_PER_VS */
3437 r600_store_context_reg(cb
, R_028878_SQ_PGM_RESOURCES_GS
,
3438 S_028878_NUM_GPRS(rshader
->bc
.ngpr
) |
3439 S_028878_DX10_CLAMP(1) |
3440 S_028878_STACK_SIZE(rshader
->bc
.nstack
));
3441 r600_store_context_reg(cb
, R_028874_SQ_PGM_START_GS
,
3442 shader
->bo
->gpu_address
>> 8);
3443 /* After that, the NOP relocation packet must be emitted (shader->bo, RADEON_USAGE_READ). */
3447 void evergreen_update_vs_state(struct pipe_context
*ctx
, struct r600_pipe_shader
*shader
)
3449 struct r600_command_buffer
*cb
= &shader
->command_buffer
;
3450 struct r600_shader
*rshader
= &shader
->shader
;
3451 unsigned spi_vs_out_id
[10] = {};
3452 unsigned i
, tmp
, nparams
= 0;
3454 for (i
= 0; i
< rshader
->noutput
; i
++) {
3455 if (rshader
->output
[i
].spi_sid
) {
3456 tmp
= rshader
->output
[i
].spi_sid
<< ((nparams
& 3) * 8);
3457 spi_vs_out_id
[nparams
/ 4] |= tmp
;
3462 r600_init_command_buffer(cb
, 32);
3464 r600_store_context_reg_seq(cb
, R_02861C_SPI_VS_OUT_ID_0
, 10);
3465 for (i
= 0; i
< 10; i
++) {
3466 r600_store_value(cb
, spi_vs_out_id
[i
]);
3469 /* Certain attributes (position, psize, etc.) don't count as params.
3470 * VS is required to export at least one param and r600_shader_from_tgsi()
3471 * takes care of adding a dummy export.
3476 r600_store_context_reg(cb
, R_0286C4_SPI_VS_OUT_CONFIG
,
3477 S_0286C4_VS_EXPORT_COUNT(nparams
- 1));
3478 r600_store_context_reg(cb
, R_028860_SQ_PGM_RESOURCES_VS
,
3479 S_028860_NUM_GPRS(rshader
->bc
.ngpr
) |
3480 S_028860_DX10_CLAMP(1) |
3481 S_028860_STACK_SIZE(rshader
->bc
.nstack
));
3482 if (rshader
->vs_position_window_space
) {
3483 r600_store_context_reg(cb
, R_028818_PA_CL_VTE_CNTL
,
3484 S_028818_VTX_XY_FMT(1) | S_028818_VTX_Z_FMT(1));
3486 r600_store_context_reg(cb
, R_028818_PA_CL_VTE_CNTL
,
3487 S_028818_VTX_W0_FMT(1) |
3488 S_028818_VPORT_X_SCALE_ENA(1) | S_028818_VPORT_X_OFFSET_ENA(1) |
3489 S_028818_VPORT_Y_SCALE_ENA(1) | S_028818_VPORT_Y_OFFSET_ENA(1) |
3490 S_028818_VPORT_Z_SCALE_ENA(1) | S_028818_VPORT_Z_OFFSET_ENA(1));
3493 r600_store_context_reg(cb
, R_02885C_SQ_PGM_START_VS
,
3494 shader
->bo
->gpu_address
>> 8);
3495 /* After that, the NOP relocation packet must be emitted (shader->bo, RADEON_USAGE_READ). */
3497 shader
->pa_cl_vs_out_cntl
=
3498 S_02881C_VS_OUT_CCDIST0_VEC_ENA((rshader
->clip_dist_write
& 0x0F) != 0) |
3499 S_02881C_VS_OUT_CCDIST1_VEC_ENA((rshader
->clip_dist_write
& 0xF0) != 0) |
3500 S_02881C_VS_OUT_MISC_VEC_ENA(rshader
->vs_out_misc_write
) |
3501 S_02881C_USE_VTX_POINT_SIZE(rshader
->vs_out_point_size
) |
3502 S_02881C_USE_VTX_EDGE_FLAG(rshader
->vs_out_edgeflag
) |
3503 S_02881C_USE_VTX_VIEWPORT_INDX(rshader
->vs_out_viewport
) |
3504 S_02881C_USE_VTX_RENDER_TARGET_INDX(rshader
->vs_out_layer
);
3507 void evergreen_update_hs_state(struct pipe_context
*ctx
, struct r600_pipe_shader
*shader
)
3509 struct r600_command_buffer
*cb
= &shader
->command_buffer
;
3510 struct r600_shader
*rshader
= &shader
->shader
;
3512 r600_init_command_buffer(cb
, 32);
3513 r600_store_context_reg(cb
, R_0288BC_SQ_PGM_RESOURCES_HS
,
3514 S_0288BC_NUM_GPRS(rshader
->bc
.ngpr
) |
3515 S_0288BC_DX10_CLAMP(1) |
3516 S_0288BC_STACK_SIZE(rshader
->bc
.nstack
));
3517 r600_store_context_reg(cb
, R_0288B8_SQ_PGM_START_HS
,
3518 shader
->bo
->gpu_address
>> 8);
3521 void evergreen_update_ls_state(struct pipe_context
*ctx
, struct r600_pipe_shader
*shader
)
3523 struct r600_command_buffer
*cb
= &shader
->command_buffer
;
3524 struct r600_shader
*rshader
= &shader
->shader
;
3526 r600_init_command_buffer(cb
, 32);
3527 r600_store_context_reg(cb
, R_0288D4_SQ_PGM_RESOURCES_LS
,
3528 S_0288D4_NUM_GPRS(rshader
->bc
.ngpr
) |
3529 S_0288D4_DX10_CLAMP(1) |
3530 S_0288D4_STACK_SIZE(rshader
->bc
.nstack
));
3531 r600_store_context_reg(cb
, R_0288D0_SQ_PGM_START_LS
,
3532 shader
->bo
->gpu_address
>> 8);
3534 void *evergreen_create_resolve_blend(struct r600_context
*rctx
)
3536 struct pipe_blend_state blend
;
3538 memset(&blend
, 0, sizeof(blend
));
3539 blend
.independent_blend_enable
= true;
3540 blend
.rt
[0].colormask
= 0xf;
3541 return evergreen_create_blend_state_mode(&rctx
->b
.b
, &blend
, V_028808_CB_RESOLVE
);
3544 void *evergreen_create_decompress_blend(struct r600_context
*rctx
)
3546 struct pipe_blend_state blend
;
3547 unsigned mode
= rctx
->screen
->has_compressed_msaa_texturing
?
3548 V_028808_CB_FMASK_DECOMPRESS
: V_028808_CB_DECOMPRESS
;
3550 memset(&blend
, 0, sizeof(blend
));
3551 blend
.independent_blend_enable
= true;
3552 blend
.rt
[0].colormask
= 0xf;
3553 return evergreen_create_blend_state_mode(&rctx
->b
.b
, &blend
, mode
);
3556 void *evergreen_create_fastclear_blend(struct r600_context
*rctx
)
3558 struct pipe_blend_state blend
;
3559 unsigned mode
= V_028808_CB_ELIMINATE_FAST_CLEAR
;
3561 memset(&blend
, 0, sizeof(blend
));
3562 blend
.independent_blend_enable
= true;
3563 blend
.rt
[0].colormask
= 0xf;
3564 return evergreen_create_blend_state_mode(&rctx
->b
.b
, &blend
, mode
);
3567 void *evergreen_create_db_flush_dsa(struct r600_context
*rctx
)
3569 struct pipe_depth_stencil_alpha_state dsa
= {{0}};
3571 return rctx
->b
.b
.create_depth_stencil_alpha_state(&rctx
->b
.b
, &dsa
);
3574 void evergreen_update_db_shader_control(struct r600_context
* rctx
)
3577 unsigned db_shader_control
;
3579 if (!rctx
->ps_shader
) {
3583 dual_export
= rctx
->framebuffer
.export_16bpc
&&
3584 !rctx
->ps_shader
->current
->ps_depth_export
;
3586 db_shader_control
= rctx
->ps_shader
->current
->db_shader_control
|
3587 S_02880C_DUAL_EXPORT_ENABLE(dual_export
) |
3588 S_02880C_DB_SOURCE_FORMAT(dual_export
? V_02880C_EXPORT_DB_TWO
:
3589 V_02880C_EXPORT_DB_FULL
) |
3590 S_02880C_ALPHA_TO_MASK_DISABLE(rctx
->framebuffer
.cb0_is_integer
);
3592 /* When alpha test is enabled we can't trust the hw to make the proper
3593 * decision on the order in which ztest should be run related to fragment
3596 * If alpha test is enabled perform early z rejection (RE_Z) but don't early
3597 * write to the zbuffer. Write to zbuffer is delayed after fragment shader
3598 * execution and thus after alpha test so if discarded by the alpha test
3599 * the z value is not written.
3600 * If ReZ is enabled, and the zfunc/zenable/zwrite values change you can
3601 * get a hang unless you flush the DB in between. For now just use
3604 if (rctx
->alphatest_state
.sx_alpha_test_control
|| rctx
->ps_shader
->info
.writes_memory
) {
3605 db_shader_control
|= S_02880C_Z_ORDER(V_02880C_LATE_Z
);
3607 db_shader_control
|= S_02880C_Z_ORDER(V_02880C_EARLY_Z_THEN_LATE_Z
);
3610 if (db_shader_control
!= rctx
->db_misc_state
.db_shader_control
) {
3611 rctx
->db_misc_state
.db_shader_control
= db_shader_control
;
3612 r600_mark_atom_dirty(rctx
, &rctx
->db_misc_state
.atom
);
3616 static void evergreen_dma_copy_tile(struct r600_context
*rctx
,
3617 struct pipe_resource
*dst
,
3622 struct pipe_resource
*src
,
3627 unsigned copy_height
,
3631 struct radeon_winsys_cs
*cs
= rctx
->b
.dma
.cs
;
3632 struct r600_texture
*rsrc
= (struct r600_texture
*)src
;
3633 struct r600_texture
*rdst
= (struct r600_texture
*)dst
;
3634 unsigned array_mode
, lbpp
, pitch_tile_max
, slice_tile_max
, size
;
3635 unsigned ncopy
, height
, cheight
, detile
, i
, x
, y
, z
, src_mode
, dst_mode
;
3636 unsigned sub_cmd
, bank_h
, bank_w
, mt_aspect
, nbanks
, tile_split
, non_disp_tiling
= 0;
3637 uint64_t base
, addr
;
3639 dst_mode
= rdst
->surface
.u
.legacy
.level
[dst_level
].mode
;
3640 src_mode
= rsrc
->surface
.u
.legacy
.level
[src_level
].mode
;
3641 assert(dst_mode
!= src_mode
);
3643 /* non_disp_tiling bit needs to be set for depth, stencil, and fmask surfaces */
3644 if (util_format_has_depth(util_format_description(src
->format
)))
3645 non_disp_tiling
= 1;
3648 sub_cmd
= EG_DMA_COPY_TILED
;
3649 lbpp
= util_logbase2(bpp
);
3650 pitch_tile_max
= ((pitch
/ bpp
) / 8) - 1;
3651 nbanks
= eg_num_banks(rctx
->screen
->b
.info
.r600_num_banks
);
3653 if (dst_mode
== RADEON_SURF_MODE_LINEAR_ALIGNED
) {
3655 array_mode
= evergreen_array_mode(src_mode
);
3656 slice_tile_max
= (rsrc
->surface
.u
.legacy
.level
[src_level
].nblk_x
* rsrc
->surface
.u
.legacy
.level
[src_level
].nblk_y
) / (8*8);
3657 slice_tile_max
= slice_tile_max
? slice_tile_max
- 1 : 0;
3658 /* linear height must be the same as the slice tile max height, it's ok even
3659 * if the linear destination/source have smaller heigh as the size of the
3660 * dma packet will be using the copy_height which is always smaller or equal
3661 * to the linear height
3663 height
= u_minify(rsrc
->resource
.b
.b
.height0
, src_level
);
3668 base
= rsrc
->surface
.u
.legacy
.level
[src_level
].offset
;
3669 addr
= rdst
->surface
.u
.legacy
.level
[dst_level
].offset
;
3670 addr
+= rdst
->surface
.u
.legacy
.level
[dst_level
].slice_size
* dst_z
;
3671 addr
+= dst_y
* pitch
+ dst_x
* bpp
;
3672 bank_h
= eg_bank_wh(rsrc
->surface
.u
.legacy
.bankh
);
3673 bank_w
= eg_bank_wh(rsrc
->surface
.u
.legacy
.bankw
);
3674 mt_aspect
= eg_macro_tile_aspect(rsrc
->surface
.u
.legacy
.mtilea
);
3675 tile_split
= eg_tile_split(rsrc
->surface
.u
.legacy
.tile_split
);
3676 base
+= rsrc
->resource
.gpu_address
;
3677 addr
+= rdst
->resource
.gpu_address
;
3680 array_mode
= evergreen_array_mode(dst_mode
);
3681 slice_tile_max
= (rdst
->surface
.u
.legacy
.level
[dst_level
].nblk_x
* rdst
->surface
.u
.legacy
.level
[dst_level
].nblk_y
) / (8*8);
3682 slice_tile_max
= slice_tile_max
? slice_tile_max
- 1 : 0;
3683 /* linear height must be the same as the slice tile max height, it's ok even
3684 * if the linear destination/source have smaller heigh as the size of the
3685 * dma packet will be using the copy_height which is always smaller or equal
3686 * to the linear height
3688 height
= u_minify(rdst
->resource
.b
.b
.height0
, dst_level
);
3693 base
= rdst
->surface
.u
.legacy
.level
[dst_level
].offset
;
3694 addr
= rsrc
->surface
.u
.legacy
.level
[src_level
].offset
;
3695 addr
+= rsrc
->surface
.u
.legacy
.level
[src_level
].slice_size
* src_z
;
3696 addr
+= src_y
* pitch
+ src_x
* bpp
;
3697 bank_h
= eg_bank_wh(rdst
->surface
.u
.legacy
.bankh
);
3698 bank_w
= eg_bank_wh(rdst
->surface
.u
.legacy
.bankw
);
3699 mt_aspect
= eg_macro_tile_aspect(rdst
->surface
.u
.legacy
.mtilea
);
3700 tile_split
= eg_tile_split(rdst
->surface
.u
.legacy
.tile_split
);
3701 base
+= rdst
->resource
.gpu_address
;
3702 addr
+= rsrc
->resource
.gpu_address
;
3705 size
= (copy_height
* pitch
) / 4;
3706 ncopy
= (size
/ EG_DMA_COPY_MAX_SIZE
) + !!(size
% EG_DMA_COPY_MAX_SIZE
);
3707 r600_need_dma_space(&rctx
->b
, ncopy
* 9, &rdst
->resource
, &rsrc
->resource
);
3709 for (i
= 0; i
< ncopy
; i
++) {
3710 cheight
= copy_height
;
3711 if (((cheight
* pitch
) / 4) > EG_DMA_COPY_MAX_SIZE
) {
3712 cheight
= (EG_DMA_COPY_MAX_SIZE
* 4) / pitch
;
3714 size
= (cheight
* pitch
) / 4;
3715 /* emit reloc before writing cs so that cs is always in consistent state */
3716 radeon_add_to_buffer_list(&rctx
->b
, &rctx
->b
.dma
, &rsrc
->resource
,
3717 RADEON_USAGE_READ
, RADEON_PRIO_SDMA_TEXTURE
);
3718 radeon_add_to_buffer_list(&rctx
->b
, &rctx
->b
.dma
, &rdst
->resource
,
3719 RADEON_USAGE_WRITE
, RADEON_PRIO_SDMA_TEXTURE
);
3720 radeon_emit(cs
, DMA_PACKET(DMA_PACKET_COPY
, sub_cmd
, size
));
3721 radeon_emit(cs
, base
>> 8);
3722 radeon_emit(cs
, (detile
<< 31) | (array_mode
<< 27) |
3723 (lbpp
<< 24) | (bank_h
<< 21) |
3724 (bank_w
<< 18) | (mt_aspect
<< 16));
3725 radeon_emit(cs
, (pitch_tile_max
<< 0) | ((height
- 1) << 16));
3726 radeon_emit(cs
, (slice_tile_max
<< 0));
3727 radeon_emit(cs
, (x
<< 0) | (z
<< 18));
3728 radeon_emit(cs
, (y
<< 0) | (tile_split
<< 21) | (nbanks
<< 25) | (non_disp_tiling
<< 28));
3729 radeon_emit(cs
, addr
& 0xfffffffc);
3730 radeon_emit(cs
, (addr
>> 32UL) & 0xff);
3731 copy_height
-= cheight
;
3732 addr
+= cheight
* pitch
;
3737 static void evergreen_dma_copy(struct pipe_context
*ctx
,
3738 struct pipe_resource
*dst
,
3740 unsigned dstx
, unsigned dsty
, unsigned dstz
,
3741 struct pipe_resource
*src
,
3743 const struct pipe_box
*src_box
)
3745 struct r600_context
*rctx
= (struct r600_context
*)ctx
;
3746 struct r600_texture
*rsrc
= (struct r600_texture
*)src
;
3747 struct r600_texture
*rdst
= (struct r600_texture
*)dst
;
3748 unsigned dst_pitch
, src_pitch
, bpp
, dst_mode
, src_mode
, copy_height
;
3749 unsigned src_w
, dst_w
;
3750 unsigned src_x
, src_y
;
3751 unsigned dst_x
= dstx
, dst_y
= dsty
, dst_z
= dstz
;
3753 if (rctx
->b
.dma
.cs
== NULL
) {
3757 if (dst
->target
== PIPE_BUFFER
&& src
->target
== PIPE_BUFFER
) {
3758 evergreen_dma_copy_buffer(rctx
, dst
, src
, dst_x
, src_box
->x
, src_box
->width
);
3762 if (src_box
->depth
> 1 ||
3763 !r600_prepare_for_dma_blit(&rctx
->b
, rdst
, dst_level
, dstx
, dsty
,
3764 dstz
, rsrc
, src_level
, src_box
))
3767 src_x
= util_format_get_nblocksx(src
->format
, src_box
->x
);
3768 dst_x
= util_format_get_nblocksx(src
->format
, dst_x
);
3769 src_y
= util_format_get_nblocksy(src
->format
, src_box
->y
);
3770 dst_y
= util_format_get_nblocksy(src
->format
, dst_y
);
3772 bpp
= rdst
->surface
.bpe
;
3773 dst_pitch
= rdst
->surface
.u
.legacy
.level
[dst_level
].nblk_x
* rdst
->surface
.bpe
;
3774 src_pitch
= rsrc
->surface
.u
.legacy
.level
[src_level
].nblk_x
* rsrc
->surface
.bpe
;
3775 src_w
= u_minify(rsrc
->resource
.b
.b
.width0
, src_level
);
3776 dst_w
= u_minify(rdst
->resource
.b
.b
.width0
, dst_level
);
3777 copy_height
= src_box
->height
/ rsrc
->surface
.blk_h
;
3779 dst_mode
= rdst
->surface
.u
.legacy
.level
[dst_level
].mode
;
3780 src_mode
= rsrc
->surface
.u
.legacy
.level
[src_level
].mode
;
3782 if (src_pitch
!= dst_pitch
|| src_box
->x
|| dst_x
|| src_w
!= dst_w
) {
3783 /* FIXME evergreen can do partial blit */
3786 /* the x test here are currently useless (because we don't support partial blit)
3787 * but keep them around so we don't forget about those
3789 if (src_pitch
% 8 || src_box
->x
% 8 || dst_x
% 8 || src_box
->y
% 8 || dst_y
% 8) {
3793 /* 128 bpp surfaces require non_disp_tiling for both
3794 * tiled and linear buffers on cayman. However, async
3795 * DMA only supports it on the tiled side. As such
3796 * the tile order is backwards after a L2T/T2L packet.
3798 if ((rctx
->b
.chip_class
== CAYMAN
) &&
3799 (src_mode
!= dst_mode
) &&
3800 (util_format_get_blocksize(src
->format
) >= 16)) {
3804 if (src_mode
== dst_mode
) {
3805 uint64_t dst_offset
, src_offset
;
3806 /* simple dma blit would do NOTE code here assume :
3809 * dst_pitch == src_pitch
3811 src_offset
= rsrc
->surface
.u
.legacy
.level
[src_level
].offset
;
3812 src_offset
+= rsrc
->surface
.u
.legacy
.level
[src_level
].slice_size
* src_box
->z
;
3813 src_offset
+= src_y
* src_pitch
+ src_x
* bpp
;
3814 dst_offset
= rdst
->surface
.u
.legacy
.level
[dst_level
].offset
;
3815 dst_offset
+= rdst
->surface
.u
.legacy
.level
[dst_level
].slice_size
* dst_z
;
3816 dst_offset
+= dst_y
* dst_pitch
+ dst_x
* bpp
;
3817 evergreen_dma_copy_buffer(rctx
, dst
, src
, dst_offset
, src_offset
,
3818 src_box
->height
* src_pitch
);
3820 evergreen_dma_copy_tile(rctx
, dst
, dst_level
, dst_x
, dst_y
, dst_z
,
3821 src
, src_level
, src_x
, src_y
, src_box
->z
,
3822 copy_height
, dst_pitch
, bpp
);
3827 r600_resource_copy_region(ctx
, dst
, dst_level
, dstx
, dsty
, dstz
,
3828 src
, src_level
, src_box
);
3831 static void evergreen_set_tess_state(struct pipe_context
*ctx
,
3832 const float default_outer_level
[4],
3833 const float default_inner_level
[2])
3835 struct r600_context
*rctx
= (struct r600_context
*)ctx
;
3837 memcpy(rctx
->tess_state
, default_outer_level
, sizeof(float) * 4);
3838 memcpy(rctx
->tess_state
+4, default_inner_level
, sizeof(float) * 2);
3839 rctx
->tess_state_dirty
= true;
3842 static void evergreen_set_hw_atomic_buffers(struct pipe_context
*ctx
,
3843 unsigned start_slot
,
3845 const struct pipe_shader_buffer
*buffers
)
3847 struct r600_context
*rctx
= (struct r600_context
*)ctx
;
3848 struct r600_atomic_buffer_state
*astate
;
3851 astate
= &rctx
->atomic_buffer_state
;
3853 /* we'd probably like to expand this to 8 later so put the logic in */
3854 for (i
= start_slot
, idx
= 0; i
< start_slot
+ count
; i
++, idx
++) {
3855 const struct pipe_shader_buffer
*buf
;
3856 struct pipe_shader_buffer
*abuf
;
3858 abuf
= &astate
->buffer
[i
];
3860 if (!buffers
|| !buffers
[idx
].buffer
) {
3861 pipe_resource_reference(&abuf
->buffer
, NULL
);
3862 astate
->enabled_mask
&= ~(1 << i
);
3865 buf
= &buffers
[idx
];
3867 pipe_resource_reference(&abuf
->buffer
, buf
->buffer
);
3868 abuf
->buffer_offset
= buf
->buffer_offset
;
3869 abuf
->buffer_size
= buf
->buffer_size
;
3870 astate
->enabled_mask
|= (1 << i
);
3874 static void evergreen_set_shader_images(struct pipe_context
*ctx
,
3875 enum pipe_shader_type shader
, unsigned start_slot
,
3877 const struct pipe_image_view
*images
)
3879 struct r600_context
*rctx
= (struct r600_context
*)ctx
;
3880 struct r600_screen
*rscreen
= (struct r600_screen
*)ctx
->screen
;
3882 struct r600_image_view
*rview
;
3883 struct pipe_resource
*image
;
3884 struct r600_resource
*resource
;
3885 struct r600_tex_color_info color
;
3886 struct eg_buf_res_params buf_params
;
3887 struct eg_tex_res_params tex_params
;
3889 bool skip_reloc
= false;
3890 struct r600_image_state
*istate
= NULL
;
3892 if (shader
!= PIPE_SHADER_FRAGMENT
&& count
== 0)
3895 istate
= &rctx
->fragment_images
;
3897 assert (shader
== PIPE_SHADER_FRAGMENT
);
3898 old_mask
= istate
->enabled_mask
;
3899 for (i
= start_slot
, idx
= 0; i
< start_slot
+ count
; i
++, idx
++) {
3901 const struct pipe_image_view
*iview
;
3902 rview
= &istate
->views
[i
];
3904 if (!images
|| !images
[idx
].resource
) {
3905 pipe_resource_reference((struct pipe_resource
**)&rview
->base
.resource
, NULL
);
3906 istate
->enabled_mask
&= ~(1 << i
);
3910 iview
= &images
[idx
];
3911 image
= iview
->resource
;
3912 resource
= (struct r600_resource
*)image
;
3914 r600_context_add_resource_size(ctx
, image
);
3916 rview
->base
= *iview
;
3917 rview
->base
.resource
= NULL
;
3918 pipe_resource_reference((struct pipe_resource
**)&rview
->base
.resource
, image
);
3920 if (!resource
->immed_buffer
) {
3921 int immed_size
= (rscreen
->b
.info
.max_se
* 256 * 64) * util_format_get_blocksize(iview
->format
);
3923 eg_resource_alloc_immed(&rscreen
->b
, resource
, immed_size
);
3926 bool is_buffer
= image
->target
== PIPE_BUFFER
;
3927 struct r600_texture
*rtex
= (struct r600_texture
*)image
;
3928 if (!is_buffer
& rtex
->db_compatible
)
3929 istate
->compressed_depthtex_mask
|= 1 << i
;
3931 istate
->compressed_depthtex_mask
&= ~(1 << i
);
3933 if (!is_buffer
&& rtex
->cmask
.size
)
3934 istate
->compressed_colortex_mask
|= 1 << i
;
3936 istate
->compressed_colortex_mask
&= ~(1 << i
);
3939 evergreen_set_color_surface_common(rctx
, rtex
,
3941 iview
->u
.tex
.first_layer
,
3942 iview
->u
.tex
.last_layer
,
3945 color
.dim
= S_028C78_WIDTH_MAX(u_minify(image
->width0
, iview
->u
.tex
.level
) - 1) |
3946 S_028C78_HEIGHT_MAX(u_minify(image
->height0
, iview
->u
.tex
.level
) - 1);
3950 evergreen_set_color_surface_buffer(rctx
, resource
,
3952 iview
->u
.buf
.offset
,
3957 switch (image
->target
) {
3959 res_type
= V_028C70_BUFFER
;
3961 case PIPE_TEXTURE_1D
:
3962 res_type
= V_028C70_TEXTURE1D
;
3964 case PIPE_TEXTURE_1D_ARRAY
:
3965 res_type
= V_028C70_TEXTURE1DARRAY
;
3967 case PIPE_TEXTURE_2D
:
3968 case PIPE_TEXTURE_RECT
:
3969 res_type
= V_028C70_TEXTURE2D
;
3971 case PIPE_TEXTURE_3D
:
3972 res_type
= V_028C70_TEXTURE3D
;
3974 case PIPE_TEXTURE_2D_ARRAY
:
3975 case PIPE_TEXTURE_CUBE
:
3976 case PIPE_TEXTURE_CUBE_ARRAY
:
3977 res_type
= V_028C70_TEXTURE2DARRAY
;
3985 rview
->cb_color_base
= color
.offset
;
3986 rview
->cb_color_dim
= color
.dim
;
3987 rview
->cb_color_info
= color
.info
|
3989 S_028C70_RESOURCE_TYPE(res_type
);
3990 rview
->cb_color_pitch
= color
.pitch
;
3991 rview
->cb_color_slice
= color
.slice
;
3992 rview
->cb_color_view
= color
.view
;
3993 rview
->cb_color_attrib
= color
.attrib
;
3994 rview
->cb_color_fmask
= color
.fmask
;
3995 rview
->cb_color_fmask_slice
= color
.fmask_slice
;
3997 memset(&buf_params
, 0, sizeof(buf_params
));
3998 buf_params
.pipe_format
= iview
->format
;
3999 buf_params
.size
= resource
->immed_buffer
->b
.b
.width0
;
4000 buf_params
.swizzle
[0] = PIPE_SWIZZLE_X
;
4001 buf_params
.swizzle
[1] = PIPE_SWIZZLE_Y
;
4002 buf_params
.swizzle
[2] = PIPE_SWIZZLE_Z
;
4003 buf_params
.swizzle
[3] = PIPE_SWIZZLE_W
;
4004 buf_params
.uncached
= 1;
4005 evergreen_fill_buffer_resource_words(rctx
, &resource
->immed_buffer
->b
.b
,
4006 &buf_params
, &skip_reloc
,
4007 rview
->immed_resource_words
);
4010 if (image
->target
!= PIPE_BUFFER
) {
4011 memset(&tex_params
, 0, sizeof(tex_params
));
4012 tex_params
.pipe_format
= iview
->format
;
4013 tex_params
.force_level
= 0;
4014 tex_params
.width0
= image
->width0
;
4015 tex_params
.height0
= image
->height0
;
4016 tex_params
.first_level
= iview
->u
.tex
.level
;
4017 tex_params
.last_level
= iview
->u
.tex
.level
;
4018 tex_params
.first_layer
= iview
->u
.tex
.first_layer
;
4019 tex_params
.last_layer
= iview
->u
.tex
.last_layer
;
4020 tex_params
.target
= image
->target
;
4021 tex_params
.swizzle
[0] = PIPE_SWIZZLE_X
;
4022 tex_params
.swizzle
[1] = PIPE_SWIZZLE_Y
;
4023 tex_params
.swizzle
[2] = PIPE_SWIZZLE_Z
;
4024 tex_params
.swizzle
[3] = PIPE_SWIZZLE_W
;
4025 evergreen_fill_tex_resource_words(rctx
, &resource
->b
.b
, &tex_params
,
4026 &rview
->skip_mip_address_reloc
,
4027 rview
->resource_words
);
4030 memset(&buf_params
, 0, sizeof(buf_params
));
4031 buf_params
.pipe_format
= iview
->format
;
4032 buf_params
.size
= iview
->u
.buf
.size
;
4033 buf_params
.offset
= iview
->u
.buf
.offset
;
4034 buf_params
.swizzle
[0] = PIPE_SWIZZLE_X
;
4035 buf_params
.swizzle
[1] = PIPE_SWIZZLE_Y
;
4036 buf_params
.swizzle
[2] = PIPE_SWIZZLE_Z
;
4037 buf_params
.swizzle
[3] = PIPE_SWIZZLE_W
;
4038 evergreen_fill_buffer_resource_words(rctx
, &resource
->b
.b
,
4040 &rview
->skip_mip_address_reloc
,
4041 rview
->resource_words
);
4043 istate
->enabled_mask
|= (1 << i
);
4046 istate
->atom
.num_dw
= util_bitcount(istate
->enabled_mask
) * 46;
4047 istate
->dirty_buffer_constants
= TRUE
;
4048 rctx
->b
.flags
|= R600_CONTEXT_WAIT_3D_IDLE
| R600_CONTEXT_FLUSH_AND_INV
;
4049 rctx
->b
.flags
|= R600_CONTEXT_FLUSH_AND_INV_CB
|
4050 R600_CONTEXT_FLUSH_AND_INV_CB_META
;
4052 if (old_mask
!= istate
->enabled_mask
)
4053 r600_mark_atom_dirty(rctx
, &rctx
->framebuffer
.atom
);
4055 if (rctx
->cb_misc_state
.nr_image_rats
!= util_bitcount(istate
->enabled_mask
)) {
4056 rctx
->cb_misc_state
.nr_image_rats
= util_bitcount(istate
->enabled_mask
);
4057 r600_mark_atom_dirty(rctx
, &rctx
->cb_misc_state
.atom
);
4060 r600_mark_atom_dirty(rctx
, &istate
->atom
);
4063 void evergreen_init_state_functions(struct r600_context
*rctx
)
4068 * To avoid GPU lockup registers must be emitted in a specific order
4069 * (no kidding ...). The order below is important and have been
4070 * partially inferred from analyzing fglrx command stream.
4072 * Don't reorder atom without carefully checking the effect (GPU lockup
4073 * or piglit regression).
4076 if (rctx
->b
.chip_class
== EVERGREEN
) {
4077 r600_init_atom(rctx
, &rctx
->config_state
.atom
, id
++, evergreen_emit_config_state
, 11);
4078 rctx
->config_state
.dyn_gpr_enabled
= true;
4080 r600_init_atom(rctx
, &rctx
->framebuffer
.atom
, id
++, evergreen_emit_framebuffer_state
, 0);
4081 r600_init_atom(rctx
, &rctx
->fragment_images
.atom
, id
++, evergreen_emit_fragment_image_state
, 0);
4083 r600_init_atom(rctx
, &rctx
->constbuf_state
[PIPE_SHADER_VERTEX
].atom
, id
++, evergreen_emit_vs_constant_buffers
, 0);
4084 r600_init_atom(rctx
, &rctx
->constbuf_state
[PIPE_SHADER_GEOMETRY
].atom
, id
++, evergreen_emit_gs_constant_buffers
, 0);
4085 r600_init_atom(rctx
, &rctx
->constbuf_state
[PIPE_SHADER_FRAGMENT
].atom
, id
++, evergreen_emit_ps_constant_buffers
, 0);
4086 r600_init_atom(rctx
, &rctx
->constbuf_state
[PIPE_SHADER_TESS_CTRL
].atom
, id
++, evergreen_emit_tcs_constant_buffers
, 0);
4087 r600_init_atom(rctx
, &rctx
->constbuf_state
[PIPE_SHADER_TESS_EVAL
].atom
, id
++, evergreen_emit_tes_constant_buffers
, 0);
4088 r600_init_atom(rctx
, &rctx
->constbuf_state
[PIPE_SHADER_COMPUTE
].atom
, id
++, evergreen_emit_cs_constant_buffers
, 0);
4089 /* shader program */
4090 r600_init_atom(rctx
, &rctx
->cs_shader_state
.atom
, id
++, evergreen_emit_cs_shader
, 0);
4092 r600_init_atom(rctx
, &rctx
->samplers
[PIPE_SHADER_VERTEX
].states
.atom
, id
++, evergreen_emit_vs_sampler_states
, 0);
4093 r600_init_atom(rctx
, &rctx
->samplers
[PIPE_SHADER_GEOMETRY
].states
.atom
, id
++, evergreen_emit_gs_sampler_states
, 0);
4094 r600_init_atom(rctx
, &rctx
->samplers
[PIPE_SHADER_TESS_CTRL
].states
.atom
, id
++, evergreen_emit_tcs_sampler_states
, 0);
4095 r600_init_atom(rctx
, &rctx
->samplers
[PIPE_SHADER_TESS_EVAL
].states
.atom
, id
++, evergreen_emit_tes_sampler_states
, 0);
4096 r600_init_atom(rctx
, &rctx
->samplers
[PIPE_SHADER_FRAGMENT
].states
.atom
, id
++, evergreen_emit_ps_sampler_states
, 0);
4097 r600_init_atom(rctx
, &rctx
->samplers
[PIPE_SHADER_COMPUTE
].states
.atom
, id
++, evergreen_emit_cs_sampler_states
, 0);
4099 r600_init_atom(rctx
, &rctx
->vertex_buffer_state
.atom
, id
++, evergreen_fs_emit_vertex_buffers
, 0);
4100 r600_init_atom(rctx
, &rctx
->cs_vertex_buffer_state
.atom
, id
++, evergreen_cs_emit_vertex_buffers
, 0);
4101 r600_init_atom(rctx
, &rctx
->samplers
[PIPE_SHADER_VERTEX
].views
.atom
, id
++, evergreen_emit_vs_sampler_views
, 0);
4102 r600_init_atom(rctx
, &rctx
->samplers
[PIPE_SHADER_GEOMETRY
].views
.atom
, id
++, evergreen_emit_gs_sampler_views
, 0);
4103 r600_init_atom(rctx
, &rctx
->samplers
[PIPE_SHADER_TESS_CTRL
].views
.atom
, id
++, evergreen_emit_tcs_sampler_views
, 0);
4104 r600_init_atom(rctx
, &rctx
->samplers
[PIPE_SHADER_TESS_EVAL
].views
.atom
, id
++, evergreen_emit_tes_sampler_views
, 0);
4105 r600_init_atom(rctx
, &rctx
->samplers
[PIPE_SHADER_FRAGMENT
].views
.atom
, id
++, evergreen_emit_ps_sampler_views
, 0);
4106 r600_init_atom(rctx
, &rctx
->samplers
[PIPE_SHADER_COMPUTE
].views
.atom
, id
++, evergreen_emit_cs_sampler_views
, 0);
4108 r600_init_atom(rctx
, &rctx
->vgt_state
.atom
, id
++, r600_emit_vgt_state
, 10);
4110 if (rctx
->b
.chip_class
== EVERGREEN
) {
4111 r600_init_atom(rctx
, &rctx
->sample_mask
.atom
, id
++, evergreen_emit_sample_mask
, 3);
4113 r600_init_atom(rctx
, &rctx
->sample_mask
.atom
, id
++, cayman_emit_sample_mask
, 4);
4115 rctx
->sample_mask
.sample_mask
= ~0;
4117 r600_init_atom(rctx
, &rctx
->alphatest_state
.atom
, id
++, r600_emit_alphatest_state
, 6);
4118 r600_init_atom(rctx
, &rctx
->blend_color
.atom
, id
++, r600_emit_blend_color
, 6);
4119 r600_init_atom(rctx
, &rctx
->blend_state
.atom
, id
++, r600_emit_cso_state
, 0);
4120 r600_init_atom(rctx
, &rctx
->cb_misc_state
.atom
, id
++, evergreen_emit_cb_misc_state
, 4);
4121 r600_init_atom(rctx
, &rctx
->clip_misc_state
.atom
, id
++, r600_emit_clip_misc_state
, 9);
4122 r600_init_atom(rctx
, &rctx
->clip_state
.atom
, id
++, evergreen_emit_clip_state
, 26);
4123 r600_init_atom(rctx
, &rctx
->db_misc_state
.atom
, id
++, evergreen_emit_db_misc_state
, 10);
4124 r600_init_atom(rctx
, &rctx
->db_state
.atom
, id
++, evergreen_emit_db_state
, 14);
4125 r600_init_atom(rctx
, &rctx
->dsa_state
.atom
, id
++, r600_emit_cso_state
, 0);
4126 r600_init_atom(rctx
, &rctx
->poly_offset_state
.atom
, id
++, evergreen_emit_polygon_offset
, 9);
4127 r600_init_atom(rctx
, &rctx
->rasterizer_state
.atom
, id
++, r600_emit_cso_state
, 0);
4128 r600_add_atom(rctx
, &rctx
->b
.scissors
.atom
, id
++);
4129 r600_add_atom(rctx
, &rctx
->b
.viewports
.atom
, id
++);
4130 r600_init_atom(rctx
, &rctx
->stencil_ref
.atom
, id
++, r600_emit_stencil_ref
, 4);
4131 r600_init_atom(rctx
, &rctx
->vertex_fetch_shader
.atom
, id
++, evergreen_emit_vertex_fetch_shader
, 5);
4132 r600_add_atom(rctx
, &rctx
->b
.render_cond_atom
, id
++);
4133 r600_add_atom(rctx
, &rctx
->b
.streamout
.begin_atom
, id
++);
4134 r600_add_atom(rctx
, &rctx
->b
.streamout
.enable_atom
, id
++);
4135 for (i
= 0; i
< EG_NUM_HW_STAGES
; i
++)
4136 r600_init_atom(rctx
, &rctx
->hw_shader_stages
[i
].atom
, id
++, r600_emit_shader
, 0);
4137 r600_init_atom(rctx
, &rctx
->shader_stages
.atom
, id
++, evergreen_emit_shader_stages
, 15);
4138 r600_init_atom(rctx
, &rctx
->gs_rings
.atom
, id
++, evergreen_emit_gs_rings
, 26);
4140 rctx
->b
.b
.create_blend_state
= evergreen_create_blend_state
;
4141 rctx
->b
.b
.create_depth_stencil_alpha_state
= evergreen_create_dsa_state
;
4142 rctx
->b
.b
.create_rasterizer_state
= evergreen_create_rs_state
;
4143 rctx
->b
.b
.create_sampler_state
= evergreen_create_sampler_state
;
4144 rctx
->b
.b
.create_sampler_view
= evergreen_create_sampler_view
;
4145 rctx
->b
.b
.set_framebuffer_state
= evergreen_set_framebuffer_state
;
4146 rctx
->b
.b
.set_polygon_stipple
= evergreen_set_polygon_stipple
;
4147 rctx
->b
.b
.set_min_samples
= evergreen_set_min_samples
;
4148 rctx
->b
.b
.set_tess_state
= evergreen_set_tess_state
;
4149 rctx
->b
.b
.set_hw_atomic_buffers
= evergreen_set_hw_atomic_buffers
;
4150 rctx
->b
.b
.set_shader_images
= evergreen_set_shader_images
;
4151 if (rctx
->b
.chip_class
== EVERGREEN
)
4152 rctx
->b
.b
.get_sample_position
= evergreen_get_sample_position
;
4154 rctx
->b
.b
.get_sample_position
= cayman_get_sample_position
;
4155 rctx
->b
.dma_copy
= evergreen_dma_copy
;
4157 evergreen_init_compute_state_functions(rctx
);
4161 * This calculates the LDS size for tessellation shaders (VS, TCS, TES).
4163 * The information about LDS and other non-compile-time parameters is then
4164 * written to the const buffer.
4166 * const buffer contains -
4167 * uint32_t input_patch_size
4168 * uint32_t input_vertex_size
4169 * uint32_t num_tcs_input_cp
4170 * uint32_t num_tcs_output_cp;
4171 * uint32_t output_patch_size
4172 * uint32_t output_vertex_size
4173 * uint32_t output_patch0_offset
4174 * uint32_t perpatch_output_offset
4175 * and the same constbuf is bound to LS/HS/VS(ES).
4177 void evergreen_setup_tess_constants(struct r600_context
*rctx
, const struct pipe_draw_info
*info
, unsigned *num_patches
)
4179 struct pipe_constant_buffer constbuf
= {0};
4180 struct r600_pipe_shader_selector
*tcs
= rctx
->tcs_shader
? rctx
->tcs_shader
: rctx
->tes_shader
;
4181 struct r600_pipe_shader_selector
*ls
= rctx
->vs_shader
;
4182 unsigned num_tcs_input_cp
= info
->vertices_per_patch
;
4183 unsigned num_tcs_outputs
;
4184 unsigned num_tcs_output_cp
;
4185 unsigned num_tcs_patch_outputs
;
4186 unsigned num_tcs_inputs
;
4187 unsigned input_vertex_size
, output_vertex_size
;
4188 unsigned input_patch_size
, pervertex_output_patch_size
, output_patch_size
;
4189 unsigned output_patch0_offset
, perpatch_output_offset
, lds_size
;
4190 uint32_t values
[16];
4192 unsigned num_pipes
= rctx
->screen
->b
.info
.r600_max_quad_pipes
;
4193 unsigned wave_divisor
= (16 * num_pipes
);
4197 if (!rctx
->tes_shader
) {
4198 rctx
->lds_alloc
= 0;
4199 rctx
->b
.b
.set_constant_buffer(&rctx
->b
.b
, PIPE_SHADER_VERTEX
,
4200 R600_LDS_INFO_CONST_BUFFER
, NULL
);
4201 rctx
->b
.b
.set_constant_buffer(&rctx
->b
.b
, PIPE_SHADER_TESS_CTRL
,
4202 R600_LDS_INFO_CONST_BUFFER
, NULL
);
4203 rctx
->b
.b
.set_constant_buffer(&rctx
->b
.b
, PIPE_SHADER_TESS_EVAL
,
4204 R600_LDS_INFO_CONST_BUFFER
, NULL
);
4208 if (rctx
->lds_alloc
!= 0 &&
4209 rctx
->last_ls
== ls
&&
4210 !rctx
->tess_state_dirty
&&
4211 rctx
->last_num_tcs_input_cp
== num_tcs_input_cp
&&
4212 rctx
->last_tcs
== tcs
)
4215 num_tcs_inputs
= util_last_bit64(ls
->lds_outputs_written_mask
);
4217 if (rctx
->tcs_shader
) {
4218 num_tcs_outputs
= util_last_bit64(tcs
->lds_outputs_written_mask
);
4219 num_tcs_output_cp
= tcs
->info
.properties
[TGSI_PROPERTY_TCS_VERTICES_OUT
];
4220 num_tcs_patch_outputs
= util_last_bit64(tcs
->lds_patch_outputs_written_mask
);
4222 num_tcs_outputs
= num_tcs_inputs
;
4223 num_tcs_output_cp
= num_tcs_input_cp
;
4224 num_tcs_patch_outputs
= 2; /* TESSINNER + TESSOUTER */
4228 input_vertex_size
= num_tcs_inputs
* 16;
4229 output_vertex_size
= num_tcs_outputs
* 16;
4231 input_patch_size
= num_tcs_input_cp
* input_vertex_size
;
4233 pervertex_output_patch_size
= num_tcs_output_cp
* output_vertex_size
;
4234 output_patch_size
= pervertex_output_patch_size
+ num_tcs_patch_outputs
* 16;
4236 output_patch0_offset
= rctx
->tcs_shader
? input_patch_size
* *num_patches
: 0;
4237 perpatch_output_offset
= output_patch0_offset
+ pervertex_output_patch_size
;
4239 lds_size
= output_patch0_offset
+ output_patch_size
* *num_patches
;
4241 values
[0] = input_patch_size
;
4242 values
[1] = input_vertex_size
;
4243 values
[2] = num_tcs_input_cp
;
4244 values
[3] = num_tcs_output_cp
;
4246 values
[4] = output_patch_size
;
4247 values
[5] = output_vertex_size
;
4248 values
[6] = output_patch0_offset
;
4249 values
[7] = perpatch_output_offset
;
4251 /* docs say HS_NUM_WAVES - CEIL((LS_HS_CONFIG.NUM_PATCHES *
4252 LS_HS_CONFIG.HS_NUM_OUTPUT_CP) / (NUM_GOOD_PIPES * 16)) */
4253 num_waves
= ceilf((float)(*num_patches
* num_tcs_output_cp
) / (float)wave_divisor
);
4255 rctx
->lds_alloc
= (lds_size
| (num_waves
<< 14));
4257 memcpy(&values
[8], rctx
->tess_state
, 6 * sizeof(float));
4261 rctx
->tess_state_dirty
= false;
4263 rctx
->last_tcs
= tcs
;
4264 rctx
->last_num_tcs_input_cp
= num_tcs_input_cp
;
4266 constbuf
.user_buffer
= values
;
4267 constbuf
.buffer_size
= 16 * 4;
4269 rctx
->b
.b
.set_constant_buffer(&rctx
->b
.b
, PIPE_SHADER_VERTEX
,
4270 R600_LDS_INFO_CONST_BUFFER
, &constbuf
);
4271 rctx
->b
.b
.set_constant_buffer(&rctx
->b
.b
, PIPE_SHADER_TESS_CTRL
,
4272 R600_LDS_INFO_CONST_BUFFER
, &constbuf
);
4273 rctx
->b
.b
.set_constant_buffer(&rctx
->b
.b
, PIPE_SHADER_TESS_EVAL
,
4274 R600_LDS_INFO_CONST_BUFFER
, &constbuf
);
4275 pipe_resource_reference(&constbuf
.buffer
, NULL
);
4278 uint32_t evergreen_get_ls_hs_config(struct r600_context
*rctx
,
4279 const struct pipe_draw_info
*info
,
4280 unsigned num_patches
)
4282 unsigned num_output_cp
;
4284 if (!rctx
->tes_shader
)
4287 num_output_cp
= rctx
->tcs_shader
?
4288 rctx
->tcs_shader
->info
.properties
[TGSI_PROPERTY_TCS_VERTICES_OUT
] :
4289 info
->vertices_per_patch
;
4291 return S_028B58_NUM_PATCHES(num_patches
) |
4292 S_028B58_HS_NUM_INPUT_CP(info
->vertices_per_patch
) |
4293 S_028B58_HS_NUM_OUTPUT_CP(num_output_cp
);
4296 void evergreen_set_ls_hs_config(struct r600_context
*rctx
,
4297 struct radeon_winsys_cs
*cs
,
4298 uint32_t ls_hs_config
)
4300 radeon_set_context_reg(cs
, R_028B58_VGT_LS_HS_CONFIG
, ls_hs_config
);
4303 void evergreen_set_lds_alloc(struct r600_context
*rctx
,
4304 struct radeon_winsys_cs
*cs
,
4307 radeon_set_context_reg(cs
, R_0288E8_SQ_LDS_ALLOC
, lds_alloc
);
4310 /* on evergreen if you are running tessellation you need to disable dynamic
4311 GPRs to workaround a hardware bug.*/
4312 bool evergreen_adjust_gprs(struct r600_context
*rctx
)
4314 unsigned num_gprs
[EG_NUM_HW_STAGES
];
4315 unsigned def_gprs
[EG_NUM_HW_STAGES
];
4316 unsigned cur_gprs
[EG_NUM_HW_STAGES
];
4317 unsigned new_gprs
[EG_NUM_HW_STAGES
];
4318 unsigned def_num_clause_temp_gprs
= rctx
->r6xx_num_clause_temp_gprs
;
4321 unsigned total_gprs
;
4323 bool rework
= false, set_default
= false, set_dirty
= false;
4325 for (i
= 0; i
< EG_NUM_HW_STAGES
; i
++) {
4326 def_gprs
[i
] = rctx
->default_gprs
[i
];
4327 max_gprs
+= def_gprs
[i
];
4329 max_gprs
+= def_num_clause_temp_gprs
* 2;
4331 /* if we have no TESS and dyn gpr is enabled then do nothing. */
4332 if (!rctx
->hw_shader_stages
[EG_HW_STAGE_HS
].shader
) {
4333 if (rctx
->config_state
.dyn_gpr_enabled
)
4336 /* transition back to dyn gpr enabled state */
4337 rctx
->config_state
.dyn_gpr_enabled
= true;
4338 r600_mark_atom_dirty(rctx
, &rctx
->config_state
.atom
);
4339 rctx
->b
.flags
|= R600_CONTEXT_WAIT_3D_IDLE
;
4344 /* gather required shader gprs */
4345 for (i
= 0; i
< EG_NUM_HW_STAGES
; i
++) {
4346 if (rctx
->hw_shader_stages
[i
].shader
)
4347 num_gprs
[i
] = rctx
->hw_shader_stages
[i
].shader
->shader
.bc
.ngpr
;
4352 cur_gprs
[R600_HW_STAGE_PS
] = G_008C04_NUM_PS_GPRS(rctx
->config_state
.sq_gpr_resource_mgmt_1
);
4353 cur_gprs
[R600_HW_STAGE_VS
] = G_008C04_NUM_VS_GPRS(rctx
->config_state
.sq_gpr_resource_mgmt_1
);
4354 cur_gprs
[R600_HW_STAGE_GS
] = G_008C08_NUM_GS_GPRS(rctx
->config_state
.sq_gpr_resource_mgmt_2
);
4355 cur_gprs
[R600_HW_STAGE_ES
] = G_008C08_NUM_ES_GPRS(rctx
->config_state
.sq_gpr_resource_mgmt_2
);
4356 cur_gprs
[EG_HW_STAGE_LS
] = G_008C0C_NUM_LS_GPRS(rctx
->config_state
.sq_gpr_resource_mgmt_3
);
4357 cur_gprs
[EG_HW_STAGE_HS
] = G_008C0C_NUM_HS_GPRS(rctx
->config_state
.sq_gpr_resource_mgmt_3
);
4360 for (i
= 0; i
< EG_NUM_HW_STAGES
; i
++) {
4361 new_gprs
[i
] = num_gprs
[i
];
4362 total_gprs
+= num_gprs
[i
];
4365 if (total_gprs
> (max_gprs
- (2 * def_num_clause_temp_gprs
)))
4368 for (i
= 0; i
< EG_NUM_HW_STAGES
; i
++) {
4369 if (new_gprs
[i
] > cur_gprs
[i
]) {
4375 if (rctx
->config_state
.dyn_gpr_enabled
) {
4377 rctx
->config_state
.dyn_gpr_enabled
= false;
4382 for (i
= 0; i
< EG_NUM_HW_STAGES
; i
++) {
4383 if (new_gprs
[i
] > def_gprs
[i
])
4384 set_default
= false;
4388 for (i
= 0; i
< EG_NUM_HW_STAGES
; i
++) {
4389 new_gprs
[i
] = def_gprs
[i
];
4392 unsigned ps_value
= max_gprs
;
4394 ps_value
-= (def_num_clause_temp_gprs
* 2);
4395 for (i
= R600_HW_STAGE_VS
; i
< EG_NUM_HW_STAGES
; i
++)
4396 ps_value
-= new_gprs
[i
];
4398 new_gprs
[R600_HW_STAGE_PS
] = ps_value
;
4401 tmp
[0] = S_008C04_NUM_PS_GPRS(new_gprs
[R600_HW_STAGE_PS
]) |
4402 S_008C04_NUM_VS_GPRS(new_gprs
[R600_HW_STAGE_VS
]) |
4403 S_008C04_NUM_CLAUSE_TEMP_GPRS(def_num_clause_temp_gprs
);
4405 tmp
[1] = S_008C08_NUM_ES_GPRS(new_gprs
[R600_HW_STAGE_ES
]) |
4406 S_008C08_NUM_GS_GPRS(new_gprs
[R600_HW_STAGE_GS
]);
4408 tmp
[2] = S_008C0C_NUM_HS_GPRS(new_gprs
[EG_HW_STAGE_HS
]) |
4409 S_008C0C_NUM_LS_GPRS(new_gprs
[EG_HW_STAGE_LS
]);
4411 if (rctx
->config_state
.sq_gpr_resource_mgmt_1
!= tmp
[0] ||
4412 rctx
->config_state
.sq_gpr_resource_mgmt_2
!= tmp
[1] ||
4413 rctx
->config_state
.sq_gpr_resource_mgmt_3
!= tmp
[2]) {
4414 rctx
->config_state
.sq_gpr_resource_mgmt_1
= tmp
[0];
4415 rctx
->config_state
.sq_gpr_resource_mgmt_2
= tmp
[1];
4416 rctx
->config_state
.sq_gpr_resource_mgmt_3
= tmp
[2];
4423 r600_mark_atom_dirty(rctx
, &rctx
->config_state
.atom
);
4424 rctx
->b
.flags
|= R600_CONTEXT_WAIT_3D_IDLE
;
4429 #define AC_ENCODE_TRACE_POINT(id) (0xcafe0000 | ((id) & 0xffff))
4431 void eg_trace_emit(struct r600_context
*rctx
)
4433 struct radeon_winsys_cs
*cs
= rctx
->b
.gfx
.cs
;
4436 if (rctx
->b
.chip_class
< EVERGREEN
)
4439 /* This must be done after r600_need_cs_space. */
4440 reloc
= radeon_add_to_buffer_list(&rctx
->b
, &rctx
->b
.gfx
,
4441 (struct r600_resource
*)rctx
->trace_buf
, RADEON_USAGE_WRITE
,
4442 RADEON_PRIO_CP_DMA
);
4445 radeon_add_to_buffer_list(&rctx
->b
, &rctx
->b
.gfx
, rctx
->trace_buf
,
4446 RADEON_USAGE_READWRITE
, RADEON_PRIO_TRACE
);
4447 radeon_emit(cs
, PKT3(PKT3_MEM_WRITE
, 3, 0));
4448 radeon_emit(cs
, rctx
->trace_buf
->gpu_address
);
4449 radeon_emit(cs
, rctx
->trace_buf
->gpu_address
>> 32 | MEM_WRITE_32_BITS
| MEM_WRITE_CONFIRM
);
4450 radeon_emit(cs
, rctx
->trace_id
);
4452 radeon_emit(cs
, PKT3(PKT3_NOP
, 0, 0));
4453 radeon_emit(cs
, reloc
);
4454 radeon_emit(cs
, PKT3(PKT3_NOP
, 0, 0));
4455 radeon_emit(cs
, AC_ENCODE_TRACE_POINT(rctx
->trace_id
));
4458 bool evergreen_emit_atomic_buffer_setup(struct r600_context
*rctx
,
4459 struct r600_shader_atomic
*combined_atomics
,
4460 uint8_t *atomic_used_mask_p
)
4462 struct radeon_winsys_cs
*cs
= rctx
->b
.gfx
.cs
;
4463 struct r600_atomic_buffer_state
*astate
= &rctx
->atomic_buffer_state
;
4464 unsigned pkt_flags
= 0;
4465 uint8_t atomic_used_mask
= 0;
4468 for (i
= 0; i
< EG_NUM_HW_STAGES
; i
++) {
4469 uint8_t num_atomic_stage
;
4470 struct r600_pipe_shader
*pshader
;
4472 pshader
= rctx
->hw_shader_stages
[i
].shader
;
4476 num_atomic_stage
= pshader
->shader
.nhwatomic_ranges
;
4477 if (!num_atomic_stage
)
4480 for (j
= 0; j
< num_atomic_stage
; j
++) {
4481 struct r600_shader_atomic
*atomic
= &pshader
->shader
.atomics
[j
];
4482 int natomics
= atomic
->end
- atomic
->start
+ 1;
4484 for (k
= 0; k
< natomics
; k
++) {
4485 /* seen this in a previous stage */
4486 if (atomic_used_mask
& (1u << (atomic
->hw_idx
+ k
)))
4489 combined_atomics
[atomic
->hw_idx
+ k
].hw_idx
= atomic
->hw_idx
+ k
;
4490 combined_atomics
[atomic
->hw_idx
+ k
].buffer_id
= atomic
->buffer_id
;
4491 combined_atomics
[atomic
->hw_idx
+ k
].start
= atomic
->start
+ k
;
4492 combined_atomics
[atomic
->hw_idx
+ k
].end
= combined_atomics
[atomic
->hw_idx
+ k
].start
+ 1;
4493 atomic_used_mask
|= (1u << (atomic
->hw_idx
+ k
));
4498 uint32_t mask
= atomic_used_mask
;
4500 unsigned atomic_index
= u_bit_scan(&mask
);
4501 struct r600_shader_atomic
*atomic
= &combined_atomics
[atomic_index
];
4502 struct r600_resource
*resource
= r600_resource(astate
->buffer
[atomic
->buffer_id
].buffer
);
4504 unsigned reloc
= radeon_add_to_buffer_list(&rctx
->b
, &rctx
->b
.gfx
,
4507 RADEON_PRIO_SHADER_RW_BUFFER
);
4508 uint64_t dst_offset
= resource
->gpu_address
+ (atomic
->start
* 4);
4509 uint32_t base_reg_0
= R_02872C_GDS_APPEND_COUNT_0
;
4511 uint32_t reg_val
= (base_reg_0
+ atomic
->hw_idx
* 4 - EVERGREEN_CONTEXT_REG_OFFSET
) >> 2;
4513 radeon_emit(cs
, PKT3(PKT3_SET_APPEND_CNT
, 2, 0) | pkt_flags
);
4514 radeon_emit(cs
, (reg_val
<< 16) | 0x3);
4515 radeon_emit(cs
, dst_offset
& 0xfffffffc);
4516 radeon_emit(cs
, (dst_offset
>> 32) & 0xff);
4517 radeon_emit(cs
, PKT3(PKT3_NOP
, 0, 0));
4518 radeon_emit(cs
, reloc
);
4520 *atomic_used_mask_p
= atomic_used_mask
;
4524 void evergreen_emit_atomic_buffer_save(struct r600_context
*rctx
,
4525 struct r600_shader_atomic
*combined_atomics
,
4526 uint8_t *atomic_used_mask_p
)
4528 struct radeon_winsys_cs
*cs
= rctx
->b
.gfx
.cs
;
4529 struct r600_atomic_buffer_state
*astate
= &rctx
->atomic_buffer_state
;
4530 uint32_t pkt_flags
= 0;
4531 uint32_t event
= EVENT_TYPE_PS_DONE
;
4532 uint32_t mask
= astate
->enabled_mask
;
4533 uint64_t dst_offset
;
4536 mask
= *atomic_used_mask_p
;
4541 unsigned atomic_index
= u_bit_scan(&mask
);
4542 struct r600_shader_atomic
*atomic
= &combined_atomics
[atomic_index
];
4543 struct r600_resource
*resource
= r600_resource(astate
->buffer
[atomic
->buffer_id
].buffer
);
4546 uint32_t base_reg_0
= R_02872C_GDS_APPEND_COUNT_0
;
4547 reloc
= radeon_add_to_buffer_list(&rctx
->b
, &rctx
->b
.gfx
,
4550 RADEON_PRIO_SHADER_RW_BUFFER
);
4551 dst_offset
= resource
->gpu_address
+ (atomic
->start
* 4);
4552 uint32_t reg_val
= (base_reg_0
+ atomic
->hw_idx
* 4) >> 2;
4554 radeon_emit(cs
, PKT3(PKT3_EVENT_WRITE_EOS
, 3, 0) | pkt_flags
);
4555 radeon_emit(cs
, EVENT_TYPE(event
) | EVENT_INDEX(6));
4556 radeon_emit(cs
, (dst_offset
) & 0xffffffff);
4557 radeon_emit(cs
, (0 << 29) | ((dst_offset
>> 32) & 0xff));
4558 radeon_emit(cs
, reg_val
);
4559 radeon_emit(cs
, PKT3(PKT3_NOP
, 0, 0));
4560 radeon_emit(cs
, reloc
);
4562 ++rctx
->append_fence_id
;
4563 reloc
= radeon_add_to_buffer_list(&rctx
->b
, &rctx
->b
.gfx
,
4564 r600_resource(rctx
->append_fence
),
4565 RADEON_USAGE_READWRITE
,
4566 RADEON_PRIO_SHADER_RW_BUFFER
);
4567 dst_offset
= r600_resource(rctx
->append_fence
)->gpu_address
;
4568 radeon_emit(cs
, PKT3(PKT3_EVENT_WRITE_EOS
, 3, 0) | pkt_flags
);
4569 radeon_emit(cs
, EVENT_TYPE(event
) | EVENT_INDEX(6));
4570 radeon_emit(cs
, dst_offset
& 0xffffffff);
4571 radeon_emit(cs
, (2 << 29) | ((dst_offset
>> 32) & 0xff));
4572 radeon_emit(cs
, rctx
->append_fence_id
);
4573 radeon_emit(cs
, PKT3(PKT3_NOP
, 0, 0));
4574 radeon_emit(cs
, reloc
);
4576 radeon_emit(cs
, PKT3(PKT3_WAIT_REG_MEM
, 5, 0) | pkt_flags
);
4577 radeon_emit(cs
, WAIT_REG_MEM_GEQUAL
| WAIT_REG_MEM_MEMORY
| (1 << 8));
4578 radeon_emit(cs
, dst_offset
& 0xffffffff);
4579 radeon_emit(cs
, ((dst_offset
>> 32) & 0xff));
4580 radeon_emit(cs
, rctx
->append_fence_id
);
4581 radeon_emit(cs
, 0xffffffff);
4582 radeon_emit(cs
, 0xa);
4583 radeon_emit(cs
, PKT3(PKT3_NOP
, 0, 0));
4584 radeon_emit(cs
, reloc
);