src/gallium/drivers/r600/evergreen_state.c

   1 /*
   2  * Copyright 2010 Jerome Glisse <glisse@freedesktop.org>
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * on the rights to use, copy, modify, merge, publish, distribute, sub
   8  * license, and/or sell copies of the Software, and to permit persons to whom
   9  * the Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice (including the next
  12  * paragraph) shall be included in all copies or substantial portions of the
  13  * Software.
  14  *
  15  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  16  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  17  * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
  18  * THE AUTHOR(S) AND/OR THEIR SUPPLIERS BE LIABLE FOR ANY CLAIM,
  19  * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
  20  * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
  21  * USE OR OTHER DEALINGS IN THE SOFTWARE.
  22  */
  23
  24 /* TODO:
  25  *      - fix mask for depth control & cull for query
  26  */
  27 #include <stdio.h>
  28 #include <errno.h>
  29 #include <pipe/p_defines.h>
  30 #include <pipe/p_state.h>
  31 #include <pipe/p_context.h>
  32 #include <tgsi/tgsi_scan.h>
  33 #include <tgsi/tgsi_parse.h>
  34 #include <tgsi/tgsi_util.h>
  35 #include <util/u_blitter.h>
  36 #include <util/u_double_list.h>
  37 #include <util/u_transfer.h>
  38 #include <util/u_surface.h>
  39 #include <util/u_pack_color.h>
  40 #include <util/u_memory.h>
  41 #include <util/u_inlines.h>
  42 #include <util/u_framebuffer.h>
  43 #include <pipebuffer/pb_buffer.h>
  44 #include "r600.h"
  45 #include "evergreend.h"
  46 #include "r600_resource.h"
  47 #include "r600_shader.h"
  48 #include "r600_pipe.h"
  49 #include "eg_state_inlines.h"
  50
  51 static void evergreen_set_blend_color(struct pipe_context *ctx,
  52                                         const struct pipe_blend_color *state)
  53 {
  54         struct r600_pipe_context *rctx = (struct r600_pipe_context *)ctx;
  55         struct r600_pipe_state *rstate = CALLOC_STRUCT(r600_pipe_state);
  56
  57         if (rstate == NULL)
  58                 return;
  59
  60         rstate->id = R600_PIPE_STATE_BLEND_COLOR;
  61         r600_pipe_state_add_reg(rstate, R_028414_CB_BLEND_RED, fui(state->color[0]), 0xFFFFFFFF, NULL);
  62         r600_pipe_state_add_reg(rstate, R_028418_CB_BLEND_GREEN, fui(state->color[1]), 0xFFFFFFFF, NULL);
  63         r600_pipe_state_add_reg(rstate, R_02841C_CB_BLEND_BLUE, fui(state->color[2]), 0xFFFFFFFF, NULL);
  64         r600_pipe_state_add_reg(rstate, R_028420_CB_BLEND_ALPHA, fui(state->color[3]), 0xFFFFFFFF, NULL);
  65
  66         free(rctx->states[R600_PIPE_STATE_BLEND_COLOR]);
  67         rctx->states[R600_PIPE_STATE_BLEND_COLOR] = rstate;
  68         r600_context_pipe_state_set(&rctx->ctx, rstate);
  69 }
  70
  71 static void *evergreen_create_blend_state(struct pipe_context *ctx,
  72                                         const struct pipe_blend_state *state)
  73 {
  74         struct r600_pipe_blend *blend = CALLOC_STRUCT(r600_pipe_blend);
  75         struct r600_pipe_state *rstate;
  76         u32 color_control, target_mask;
  77         /* FIXME there is more then 8 framebuffer */
  78         unsigned blend_cntl[8];
  79
  80         if (blend == NULL) {
  81                 return NULL;
  82         }
  83         rstate = &blend->rstate;
  84
  85         rstate->id = R600_PIPE_STATE_BLEND;
  86
  87         target_mask = 0;
  88         color_control = S_028808_MODE(1);
  89         if (state->logicop_enable) {
  90                 color_control |= (state->logicop_func << 16) | (state->logicop_func << 20);
  91         } else {
  92                 color_control |= (0xcc << 16);
  93         }
  94         /* we pretend 8 buffer are used, CB_SHADER_MASK will disable unused one */
  95         if (state->independent_blend_enable) {
  96                 for (int i = 0; i < 8; i++) {
  97                         target_mask |= (state->rt[i].colormask << (4 * i));
  98                 }
  99         } else {
 100                 for (int i = 0; i < 8; i++) {
 101                         target_mask |= (state->rt[0].colormask << (4 * i));
 102                 }
 103         }
 104         blend->cb_target_mask = target_mask;
 105         r600_pipe_state_add_reg(rstate, R_028808_CB_COLOR_CONTROL,
 106                                 color_control, 0xFFFFFFFD, NULL);
 107         r600_pipe_state_add_reg(rstate, R_028C3C_PA_SC_AA_MASK, 0xFFFFFFFF, 0xFFFFFFFF, NULL);
 108
 109         for (int i = 0; i < 8; i++) {
 110                 unsigned eqRGB = state->rt[i].rgb_func;
 111                 unsigned srcRGB = state->rt[i].rgb_src_factor;
 112                 unsigned dstRGB = state->rt[i].rgb_dst_factor;
 113                 unsigned eqA = state->rt[i].alpha_func;
 114                 unsigned srcA = state->rt[i].alpha_src_factor;
 115                 unsigned dstA = state->rt[i].alpha_dst_factor;
 116
 117                 blend_cntl[i] = 0;
 118                 if (!state->rt[i].blend_enable)
 119                         continue;
 120
 121                 blend_cntl[i] |= S_028780_BLEND_CONTROL_ENABLE(1);
 122                 blend_cntl[i] |= S_028780_COLOR_COMB_FCN(r600_translate_blend_function(eqRGB));
 123                 blend_cntl[i] |= S_028780_COLOR_SRCBLEND(r600_translate_blend_factor(srcRGB));
 124                 blend_cntl[i] |= S_028780_COLOR_DESTBLEND(r600_translate_blend_factor(dstRGB));
 125
 126                 if (srcA != srcRGB || dstA != dstRGB || eqA != eqRGB) {
 127                         blend_cntl[i] |= S_028780_SEPARATE_ALPHA_BLEND(1);
 128                         blend_cntl[i] |= S_028780_ALPHA_COMB_FCN(r600_translate_blend_function(eqA));
 129                         blend_cntl[i] |= S_028780_ALPHA_SRCBLEND(r600_translate_blend_factor(srcA));
 130                         blend_cntl[i] |= S_028780_ALPHA_DESTBLEND(r600_translate_blend_factor(dstA));
 131                 }
 132         }
 133         for (int i = 0; i < 8; i++) {
 134                 r600_pipe_state_add_reg(rstate, R_028780_CB_BLEND0_CONTROL + i * 4, blend_cntl[i], 0xFFFFFFFF, NULL);
 135         }
 136
 137         return rstate;
 138 }
 139
 140 static void *evergreen_create_dsa_state(struct pipe_context *ctx,
 141                                    const struct pipe_depth_stencil_alpha_state *state)
 142 {
 143         struct r600_pipe_state *rstate = CALLOC_STRUCT(r600_pipe_state);
 144         unsigned db_depth_control, alpha_test_control, alpha_ref, db_shader_control;
 145         unsigned stencil_ref_mask, stencil_ref_mask_bf, db_render_override, db_render_control;
 146
 147         if (rstate == NULL) {
 148                 return NULL;
 149         }
 150
 151         rstate->id = R600_PIPE_STATE_DSA;
 152         /* depth TODO some of those db_shader_control field depend on shader adjust mask & add it to shader */
 153         /* db_shader_control is 0xFFFFFFBE as Z_EXPORT_ENABLE (bit 0) will be
 154          * set by fragment shader if it export Z and KILL_ENABLE (bit 6) will
 155          * be set if shader use texkill instruction
 156          */
 157         db_shader_control = S_02880C_Z_ORDER(V_02880C_EARLY_Z_THEN_LATE_Z);
 158         stencil_ref_mask = 0;
 159         stencil_ref_mask_bf = 0;
 160         db_depth_control = S_028800_Z_ENABLE(state->depth.enabled) |
 161                 S_028800_Z_WRITE_ENABLE(state->depth.writemask) |
 162                 S_028800_ZFUNC(state->depth.func);
 163
 164         /* stencil */
 165         if (state->stencil[0].enabled) {
 166                 db_depth_control |= S_028800_STENCIL_ENABLE(1);
 167                 db_depth_control |= S_028800_STENCILFUNC(r600_translate_ds_func(state->stencil[0].func));
 168                 db_depth_control |= S_028800_STENCILFAIL(r600_translate_stencil_op(state->stencil[0].fail_op));
 169                 db_depth_control |= S_028800_STENCILZPASS(r600_translate_stencil_op(state->stencil[0].zpass_op));
 170                 db_depth_control |= S_028800_STENCILZFAIL(r600_translate_stencil_op(state->stencil[0].zfail_op));
 171
 172
 173                 stencil_ref_mask = S_028430_STENCILMASK(state->stencil[0].valuemask) |
 174                         S_028430_STENCILWRITEMASK(state->stencil[0].writemask);
 175                 if (state->stencil[1].enabled) {
 176                         db_depth_control |= S_028800_BACKFACE_ENABLE(1);
 177                         db_depth_control |= S_028800_STENCILFUNC_BF(r600_translate_ds_func(state->stencil[1].func));
 178                         db_depth_control |= S_028800_STENCILFAIL_BF(r600_translate_stencil_op(state->stencil[1].fail_op));
 179                         db_depth_control |= S_028800_STENCILZPASS_BF(r600_translate_stencil_op(state->stencil[1].zpass_op));
 180                         db_depth_control |= S_028800_STENCILZFAIL_BF(r600_translate_stencil_op(state->stencil[1].zfail_op));
 181                         stencil_ref_mask_bf = S_028434_STENCILMASK_BF(state->stencil[1].valuemask) |
 182                                 S_028434_STENCILWRITEMASK_BF(state->stencil[1].writemask);
 183                 }
 184         }
 185
 186         /* alpha */
 187         alpha_test_control = 0;
 188         alpha_ref = 0;
 189         if (state->alpha.enabled) {
 190                 alpha_test_control = S_028410_ALPHA_FUNC(state->alpha.func);
 191                 alpha_test_control |= S_028410_ALPHA_TEST_ENABLE(1);
 192                 alpha_ref = fui(state->alpha.ref_value);
 193         }
 194
 195         /* misc */
 196         db_render_control = 0;
 197         db_render_override = S_02800C_FORCE_HIZ_ENABLE(V_02800C_FORCE_DISABLE) |
 198                 S_02800C_FORCE_HIS_ENABLE0(V_02800C_FORCE_DISABLE) |
 199                 S_02800C_FORCE_HIS_ENABLE1(V_02800C_FORCE_DISABLE);
 200         /* TODO db_render_override depends on query */
 201         r600_pipe_state_add_reg(rstate, R_028028_DB_STENCIL_CLEAR, 0x00000000, 0xFFFFFFFF, NULL);
 202         r600_pipe_state_add_reg(rstate, R_02802C_DB_DEPTH_CLEAR, 0x3F800000, 0xFFFFFFFF, NULL);
 203         r600_pipe_state_add_reg(rstate, R_028410_SX_ALPHA_TEST_CONTROL, alpha_test_control, 0xFFFFFFFF, NULL);
 204         r600_pipe_state_add_reg(rstate,
 205                                 R_028430_DB_STENCILREFMASK, stencil_ref_mask,
 206                                 0xFFFFFFFF & C_028430_STENCILREF, NULL);
 207         r600_pipe_state_add_reg(rstate,
 208                                 R_028434_DB_STENCILREFMASK_BF, stencil_ref_mask_bf,
 209                                 0xFFFFFFFF & C_028434_STENCILREF_BF, NULL);
 210         r600_pipe_state_add_reg(rstate, R_028438_SX_ALPHA_REF, alpha_ref, 0xFFFFFFFF, NULL);
 211         r600_pipe_state_add_reg(rstate, R_0286DC_SPI_FOG_CNTL, 0x00000000, 0xFFFFFFFF, NULL);
 212         r600_pipe_state_add_reg(rstate, R_028800_DB_DEPTH_CONTROL, db_depth_control, 0xFFFFFFFF, NULL);
 213         r600_pipe_state_add_reg(rstate, R_02880C_DB_SHADER_CONTROL, db_shader_control, 0xFFFFFFBE, NULL);
 214         r600_pipe_state_add_reg(rstate, R_028000_DB_RENDER_CONTROL, db_render_control, 0xFFFFFFFF, NULL);
 215         r600_pipe_state_add_reg(rstate, R_02800C_DB_RENDER_OVERRIDE, db_render_override, 0xFFFFFFFF, NULL);
 216         r600_pipe_state_add_reg(rstate, R_028AC0_DB_SRESULTS_COMPARE_STATE0, 0x0, 0xFFFFFFFF, NULL);
 217         r600_pipe_state_add_reg(rstate, R_028AC4_DB_SRESULTS_COMPARE_STATE1, 0x0, 0xFFFFFFFF, NULL);
 218         r600_pipe_state_add_reg(rstate, R_028AC8_DB_PRELOAD_CONTROL, 0x0, 0xFFFFFFFF, NULL);
 219         r600_pipe_state_add_reg(rstate, R_028B70_DB_ALPHA_TO_MASK, 0x0000AA00, 0xFFFFFFFF, NULL);
 220
 221         return rstate;
 222 }
 223
 224 static void *evergreen_create_rs_state(struct pipe_context *ctx,
 225                                         const struct pipe_rasterizer_state *state)
 226 {
 227         struct r600_pipe_rasterizer *rs = CALLOC_STRUCT(r600_pipe_rasterizer);
 228         struct r600_pipe_state *rstate;
 229         unsigned tmp;
 230         unsigned prov_vtx = 1, polygon_dual_mode;
 231         unsigned clip_rule;
 232
 233         if (rs == NULL) {
 234                 return NULL;
 235         }
 236
 237         rstate = &rs->rstate;
 238         rs->flatshade = state->flatshade;
 239         rs->sprite_coord_enable = state->sprite_coord_enable;
 240
 241         clip_rule = state->scissor ? 0xAAAA : 0xFFFF;
 242
 243         /* offset */
 244         rs->offset_units = state->offset_units;
 245         rs->offset_scale = state->offset_scale * 12.0f;
 246
 247         rstate->id = R600_PIPE_STATE_RASTERIZER;
 248         if (state->flatshade_first)
 249                 prov_vtx = 0;
 250         tmp = S_0286D4_FLAT_SHADE_ENA(1);
 251         if (state->sprite_coord_enable) {
 252                 tmp |= S_0286D4_PNT_SPRITE_ENA(1) |
 253                         S_0286D4_PNT_SPRITE_OVRD_X(2) |
 254                         S_0286D4_PNT_SPRITE_OVRD_Y(3) |
 255                         S_0286D4_PNT_SPRITE_OVRD_Z(0) |
 256                         S_0286D4_PNT_SPRITE_OVRD_W(1);
 257                 if (state->sprite_coord_mode != PIPE_SPRITE_COORD_UPPER_LEFT) {
 258                         tmp |= S_0286D4_PNT_SPRITE_TOP_1(1);
 259                 }
 260         }
 261         r600_pipe_state_add_reg(rstate, R_0286D4_SPI_INTERP_CONTROL_0, tmp, 0xFFFFFFFF, NULL);
 262
 263         polygon_dual_mode = (state->fill_front != PIPE_POLYGON_MODE_FILL ||
 264                                 state->fill_back != PIPE_POLYGON_MODE_FILL);
 265         r600_pipe_state_add_reg(rstate, R_028814_PA_SU_SC_MODE_CNTL,
 266                 S_028814_PROVOKING_VTX_LAST(prov_vtx) |
 267                 S_028814_CULL_FRONT((state->cull_face & PIPE_FACE_FRONT) ? 1 : 0) |
 268                 S_028814_CULL_BACK((state->cull_face & PIPE_FACE_BACK) ? 1 : 0) |
 269                 S_028814_FACE(!state->front_ccw) |
 270                 S_028814_POLY_OFFSET_FRONT_ENABLE(state->offset_tri) |
 271                 S_028814_POLY_OFFSET_BACK_ENABLE(state->offset_tri) |
 272                 S_028814_POLY_OFFSET_PARA_ENABLE(state->offset_tri) |
 273                 S_028814_POLY_MODE(polygon_dual_mode) |
 274                 S_028814_POLYMODE_FRONT_PTYPE(r600_translate_fill(state->fill_front)) |
 275                 S_028814_POLYMODE_BACK_PTYPE(r600_translate_fill(state->fill_back)), 0xFFFFFFFF, NULL);
 276         r600_pipe_state_add_reg(rstate, R_02881C_PA_CL_VS_OUT_CNTL,
 277                         S_02881C_USE_VTX_POINT_SIZE(state->point_size_per_vertex) |
 278                         S_02881C_VS_OUT_MISC_VEC_ENA(state->point_size_per_vertex), 0xFFFFFFFF, NULL);
 279         r600_pipe_state_add_reg(rstate, R_028820_PA_CL_NANINF_CNTL, 0x00000000, 0xFFFFFFFF, NULL);
 280         /* point size 12.4 fixed point */
 281         tmp = (unsigned)(state->point_size * 8.0);
 282         r600_pipe_state_add_reg(rstate, R_028A00_PA_SU_POINT_SIZE, S_028A00_HEIGHT(tmp) | S_028A00_WIDTH(tmp), 0xFFFFFFFF, NULL);
 283         r600_pipe_state_add_reg(rstate, R_028A04_PA_SU_POINT_MINMAX, 0x80000000, 0xFFFFFFFF, NULL);
 284
 285         tmp = (unsigned)state->line_width * 8;
 286         r600_pipe_state_add_reg(rstate, R_028A08_PA_SU_LINE_CNTL, S_028A08_WIDTH(tmp), 0xFFFFFFFF, NULL);
 287
 288         r600_pipe_state_add_reg(rstate, R_028C00_PA_SC_LINE_CNTL, 0x00000400, 0xFFFFFFFF, NULL);
 289         r600_pipe_state_add_reg(rstate, R_028C0C_PA_CL_GB_VERT_CLIP_ADJ, 0x3F800000, 0xFFFFFFFF, NULL);
 290         r600_pipe_state_add_reg(rstate, R_028C10_PA_CL_GB_VERT_DISC_ADJ, 0x3F800000, 0xFFFFFFFF, NULL);
 291         r600_pipe_state_add_reg(rstate, R_028C14_PA_CL_GB_HORZ_CLIP_ADJ, 0x3F800000, 0xFFFFFFFF, NULL);
 292         r600_pipe_state_add_reg(rstate, R_028C18_PA_CL_GB_HORZ_DISC_ADJ, 0x3F800000, 0xFFFFFFFF, NULL);
 293         r600_pipe_state_add_reg(rstate, R_028B7C_PA_SU_POLY_OFFSET_CLAMP, 0x0, 0xFFFFFFFF, NULL);
 294
 295         r600_pipe_state_add_reg(rstate, R_028C08_PA_SU_VTX_CNTL,
 296                                 S_028C08_PIX_CENTER_HALF(state->gl_rasterization_rules),
 297                                 0xFFFFFFFF, NULL);
 298
 299         r600_pipe_state_add_reg(rstate, R_02820C_PA_SC_CLIPRECT_RULE, clip_rule, 0xFFFFFFFF, NULL);
 300         return rstate;
 301 }
 302
 303 static void *evergreen_create_sampler_state(struct pipe_context *ctx,
 304                                         const struct pipe_sampler_state *state)
 305 {
 306         struct r600_pipe_state *rstate = CALLOC_STRUCT(r600_pipe_state);
 307         union util_color uc;
 308
 309         if (rstate == NULL) {
 310                 return NULL;
 311         }
 312
 313         rstate->id = R600_PIPE_STATE_SAMPLER;
 314         util_pack_color(state->border_color, PIPE_FORMAT_B8G8R8A8_UNORM, &uc);
 315         r600_pipe_state_add_reg(rstate, R_03C000_SQ_TEX_SAMPLER_WORD0_0,
 316                         S_03C000_CLAMP_X(r600_tex_wrap(state->wrap_s)) |
 317                         S_03C000_CLAMP_Y(r600_tex_wrap(state->wrap_t)) |
 318                         S_03C000_CLAMP_Z(r600_tex_wrap(state->wrap_r)) |
 319                         S_03C000_XY_MAG_FILTER(r600_tex_filter(state->mag_img_filter)) |
 320                         S_03C000_XY_MIN_FILTER(r600_tex_filter(state->min_img_filter)) |
 321                         S_03C000_MIP_FILTER(r600_tex_mipfilter(state->min_mip_filter)) |
 322                         S_03C000_DEPTH_COMPARE_FUNCTION(r600_tex_compare(state->compare_func)) |
 323                         S_03C000_BORDER_COLOR_TYPE(uc.ui ? V_03C000_SQ_TEX_BORDER_COLOR_REGISTER : 0), 0xFFFFFFFF, NULL);
 324         /* FIXME LOD it depends on texture base level ... */
 325         r600_pipe_state_add_reg(rstate, R_03C004_SQ_TEX_SAMPLER_WORD1_0,
 326                         S_03C004_MIN_LOD(S_FIXED(CLAMP(state->min_lod, 0, 15), 8)) |
 327                         S_03C004_MAX_LOD(S_FIXED(CLAMP(state->max_lod, 0, 15), 8)),
 328                         0xFFFFFFFF, NULL);
 329         r600_pipe_state_add_reg(rstate, R_03C008_SQ_TEX_SAMPLER_WORD2_0,
 330                                 S_03C008_LOD_BIAS(S_FIXED(CLAMP(state->lod_bias, -16, 16), 8)) |
 331                                 S_03C008_TYPE(1),
 332                                 0xFFFFFFFF, NULL);
 333
 334         if (uc.ui) {
 335                 r600_pipe_state_add_reg(rstate, R_00A404_TD_PS_SAMPLER0_BORDER_RED, fui(state->border_color[0]), 0xFFFFFFFF, NULL);
 336                 r600_pipe_state_add_reg(rstate, R_00A408_TD_PS_SAMPLER0_BORDER_GREEN, fui(state->border_color[1]), 0xFFFFFFFF, NULL);
 337                 r600_pipe_state_add_reg(rstate, R_00A40C_TD_PS_SAMPLER0_BORDER_BLUE, fui(state->border_color[2]), 0xFFFFFFFF, NULL);
 338                 r600_pipe_state_add_reg(rstate, R_00A410_TD_PS_SAMPLER0_BORDER_ALPHA, fui(state->border_color[3]), 0xFFFFFFFF, NULL);
 339         }
 340         return rstate;
 341 }
 342
 343 static struct pipe_sampler_view *evergreen_create_sampler_view(struct pipe_context *ctx,
 344                                                         struct pipe_resource *texture,
 345                                                         const struct pipe_sampler_view *state)
 346 {
 347         struct r600_pipe_sampler_view *resource = CALLOC_STRUCT(r600_pipe_sampler_view);
 348         struct r600_pipe_state *rstate;
 349         const struct util_format_description *desc;
 350         struct r600_resource_texture *tmp;
 351         struct r600_resource *rbuffer;
 352         unsigned format;
 353         uint32_t word4 = 0, yuv_format = 0, pitch = 0;
 354         unsigned char swizzle[4];
 355         struct r600_bo *bo[2];
 356
 357         if (resource == NULL)
 358                 return NULL;
 359         rstate = &resource->state;
 360
 361         /* initialize base object */
 362         resource->base = *state;
 363         resource->base.texture = NULL;
 364         pipe_reference(NULL, &texture->reference);
 365         resource->base.texture = texture;
 366         resource->base.reference.count = 1;
 367         resource->base.context = ctx;
 368
 369         swizzle[0] = state->swizzle_r;
 370         swizzle[1] = state->swizzle_g;
 371         swizzle[2] = state->swizzle_b;
 372         swizzle[3] = state->swizzle_a;
 373         format = r600_translate_texformat(state->format,
 374                                           swizzle,
 375                                           &word4, &yuv_format);
 376         if (format == ~0) {
 377                 format = 0;
 378         }
 379         desc = util_format_description(state->format);
 380         if (desc == NULL) {
 381                 R600_ERR("unknow format %d\n", state->format);
 382         }
 383         tmp = (struct r600_resource_texture *)texture;
 384         if (tmp->depth) {
 385                 r600_texture_depth_flush(ctx, texture);
 386                 tmp = tmp->flushed_depth_texture;
 387         }
 388         rbuffer = &tmp->resource;
 389         bo[0] = rbuffer->bo;
 390         bo[1] = rbuffer->bo;
 391
 392         pitch = align(tmp->pitch_in_pixels[0], 8);
 393
 394         /* FIXME properly handle first level != 0 */
 395         r600_pipe_state_add_reg(rstate, R_030000_RESOURCE0_WORD0,
 396                                 S_030000_DIM(r600_tex_dim(texture->target)) |
 397                                 S_030000_PITCH((pitch / 8) - 1) |
 398                                 S_030000_TEX_WIDTH(texture->width0 - 1), 0xFFFFFFFF, NULL);
 399         r600_pipe_state_add_reg(rstate, R_030004_RESOURCE0_WORD1,
 400                                 S_030004_TEX_HEIGHT(texture->height0 - 1) |
 401                                 S_030004_TEX_DEPTH(texture->depth0 - 1),
 402                                 0xFFFFFFFF, NULL);
 403         r600_pipe_state_add_reg(rstate, R_030008_RESOURCE0_WORD2,
 404                                 (tmp->offset[0] + r600_bo_offset(bo[0])) >> 8, 0xFFFFFFFF, bo[0]);
 405         r600_pipe_state_add_reg(rstate, R_03000C_RESOURCE0_WORD3,
 406                                 (tmp->offset[1] + r600_bo_offset(bo[1])) >> 8, 0xFFFFFFFF, bo[1]);
 407         r600_pipe_state_add_reg(rstate, R_030010_RESOURCE0_WORD4,
 408                                 word4 | S_030010_NUM_FORMAT_ALL(V_030010_SQ_NUM_FORMAT_NORM) |
 409                                 S_030010_SRF_MODE_ALL(V_030010_SRF_MODE_NO_ZERO) |
 410                                 S_030010_BASE_LEVEL(state->u.tex.first_level), 0xFFFFFFFF, NULL);
 411         r600_pipe_state_add_reg(rstate, R_030014_RESOURCE0_WORD5,
 412                                 S_030014_LAST_LEVEL(state->u.tex.last_level) |
 413                                 S_030014_BASE_ARRAY(0) |
 414                                 S_030014_LAST_ARRAY(0), 0xffffffff, NULL);
 415         r600_pipe_state_add_reg(rstate, R_030018_RESOURCE0_WORD6, 0x0, 0xFFFFFFFF, NULL);
 416         r600_pipe_state_add_reg(rstate, R_03001C_RESOURCE0_WORD7,
 417                                 S_03001C_DATA_FORMAT(format) |
 418                                 S_03001C_TYPE(V_03001C_SQ_TEX_VTX_VALID_TEXTURE), 0xFFFFFFFF, NULL);
 419
 420         return &resource->base;
 421 }
 422
 423 static void evergreen_set_vs_sampler_view(struct pipe_context *ctx, unsigned count,
 424                                         struct pipe_sampler_view **views)
 425 {
 426         struct r600_pipe_context *rctx = (struct r600_pipe_context *)ctx;
 427         struct r600_pipe_sampler_view **resource = (struct r600_pipe_sampler_view **)views;
 428
 429         for (int i = 0; i < count; i++) {
 430                 if (resource[i]) {
 431                         evergreen_context_pipe_state_set_vs_resource(&rctx->ctx, &resource[i]->state, i);
 432                 }
 433         }
 434 }
 435
 436 static void evergreen_set_ps_sampler_view(struct pipe_context *ctx, unsigned count,
 437                                         struct pipe_sampler_view **views)
 438 {
 439         struct r600_pipe_context *rctx = (struct r600_pipe_context *)ctx;
 440         struct r600_pipe_sampler_view **resource = (struct r600_pipe_sampler_view **)views;
 441         int i;
 442
 443         for (i = 0; i < count; i++) {
 444                 if (&rctx->ps_samplers.views[i]->base != views[i]) {
 445                         if (resource[i])
 446                                 evergreen_context_pipe_state_set_ps_resource(&rctx->ctx, &resource[i]->state, i);
 447                         else
 448                                 evergreen_context_pipe_state_set_ps_resource(&rctx->ctx, NULL, i);
 449
 450                         pipe_sampler_view_reference(
 451                                 (struct pipe_sampler_view **)&rctx->ps_samplers.views[i],
 452                                 views[i]);
 453                 }
 454         }
 455         for (i = count; i < NUM_TEX_UNITS; i++) {
 456                 if (rctx->ps_samplers.views[i]) {
 457                         evergreen_context_pipe_state_set_ps_resource(&rctx->ctx, NULL, i);
 458                         pipe_sampler_view_reference((struct pipe_sampler_view **)&rctx->ps_samplers.views[i], NULL);
 459                 }
 460         }
 461         rctx->ps_samplers.n_views = count;
 462 }
 463
 464 static void evergreen_bind_ps_sampler(struct pipe_context *ctx, unsigned count, void **states)
 465 {
 466         struct r600_pipe_context *rctx = (struct r600_pipe_context *)ctx;
 467         struct r600_pipe_state **rstates = (struct r600_pipe_state **)states;
 468
 469
 470         memcpy(rctx->ps_samplers.samplers, states, sizeof(void*) * count);
 471         rctx->ps_samplers.n_samplers = count;
 472
 473         for (int i = 0; i < count; i++) {
 474                 evergreen_context_pipe_state_set_ps_sampler(&rctx->ctx, rstates[i], i);
 475         }
 476 }
 477
 478 static void evergreen_bind_vs_sampler(struct pipe_context *ctx, unsigned count, void **states)
 479 {
 480         struct r600_pipe_context *rctx = (struct r600_pipe_context *)ctx;
 481         struct r600_pipe_state **rstates = (struct r600_pipe_state **)states;
 482
 483         for (int i = 0; i < count; i++) {
 484                 evergreen_context_pipe_state_set_vs_sampler(&rctx->ctx, rstates[i], i);
 485         }
 486 }
 487
 488 static void evergreen_set_clip_state(struct pipe_context *ctx,
 489                                 const struct pipe_clip_state *state)
 490 {
 491         struct r600_pipe_context *rctx = (struct r600_pipe_context *)ctx;
 492         struct r600_pipe_state *rstate = CALLOC_STRUCT(r600_pipe_state);
 493
 494         if (rstate == NULL)
 495                 return;
 496
 497         rctx->clip = *state;
 498         rstate->id = R600_PIPE_STATE_CLIP;
 499         for (int i = 0; i < state->nr; i++) {
 500                 r600_pipe_state_add_reg(rstate,
 501                                         R_0285BC_PA_CL_UCP0_X + i * 16,
 502                                         fui(state->ucp[i][0]), 0xFFFFFFFF, NULL);
 503                 r600_pipe_state_add_reg(rstate,
 504                                         R_0285C0_PA_CL_UCP0_Y + i * 16,
 505                                         fui(state->ucp[i][1]) , 0xFFFFFFFF, NULL);
 506                 r600_pipe_state_add_reg(rstate,
 507                                         R_0285C4_PA_CL_UCP0_Z + i * 16,
 508                                         fui(state->ucp[i][2]), 0xFFFFFFFF, NULL);
 509                 r600_pipe_state_add_reg(rstate,
 510                                         R_0285C8_PA_CL_UCP0_W + i * 16,
 511                                         fui(state->ucp[i][3]), 0xFFFFFFFF, NULL);
 512         }
 513         r600_pipe_state_add_reg(rstate, R_028810_PA_CL_CLIP_CNTL,
 514                         S_028810_PS_UCP_MODE(3) | ((1 << state->nr) - 1) |
 515                         S_028810_ZCLIP_NEAR_DISABLE(state->depth_clamp) |
 516                         S_028810_ZCLIP_FAR_DISABLE(state->depth_clamp), 0xFFFFFFFF, NULL);
 517
 518         free(rctx->states[R600_PIPE_STATE_CLIP]);
 519         rctx->states[R600_PIPE_STATE_CLIP] = rstate;
 520         r600_context_pipe_state_set(&rctx->ctx, rstate);
 521 }
 522
 523 static void evergreen_set_polygon_stipple(struct pipe_context *ctx,
 524                                          const struct pipe_poly_stipple *state)
 525 {
 526 }
 527
 528 static void evergreen_set_sample_mask(struct pipe_context *pipe, unsigned sample_mask)
 529 {
 530 }
 531
 532 static void evergreen_set_scissor_state(struct pipe_context *ctx,
 533                                         const struct pipe_scissor_state *state)
 534 {
 535         struct r600_pipe_context *rctx = (struct r600_pipe_context *)ctx;
 536         struct r600_pipe_state *rstate = CALLOC_STRUCT(r600_pipe_state);
 537         u32 tl, br;
 538
 539         if (rstate == NULL)
 540                 return;
 541
 542         rstate->id = R600_PIPE_STATE_SCISSOR;
 543         tl = S_028240_TL_X(state->minx) | S_028240_TL_Y(state->miny);
 544         br = S_028244_BR_X(state->maxx) | S_028244_BR_Y(state->maxy);
 545         r600_pipe_state_add_reg(rstate,
 546                                 R_028210_PA_SC_CLIPRECT_0_TL, tl,
 547                                 0xFFFFFFFF, NULL);
 548         r600_pipe_state_add_reg(rstate,
 549                                 R_028214_PA_SC_CLIPRECT_0_BR, br,
 550                                 0xFFFFFFFF, NULL);
 551         r600_pipe_state_add_reg(rstate,
 552                                 R_028218_PA_SC_CLIPRECT_1_TL, tl,
 553                                 0xFFFFFFFF, NULL);
 554         r600_pipe_state_add_reg(rstate,
 555                                 R_02821C_PA_SC_CLIPRECT_1_BR, br,
 556                                 0xFFFFFFFF, NULL);
 557         r600_pipe_state_add_reg(rstate,
 558                                 R_028220_PA_SC_CLIPRECT_2_TL, tl,
 559                                 0xFFFFFFFF, NULL);
 560         r600_pipe_state_add_reg(rstate,
 561                                 R_028224_PA_SC_CLIPRECT_2_BR, br,
 562                                 0xFFFFFFFF, NULL);
 563         r600_pipe_state_add_reg(rstate,
 564                                 R_028228_PA_SC_CLIPRECT_3_TL, tl,
 565                                 0xFFFFFFFF, NULL);
 566         r600_pipe_state_add_reg(rstate,
 567                                 R_02822C_PA_SC_CLIPRECT_3_BR, br,
 568                                 0xFFFFFFFF, NULL);
 569
 570         free(rctx->states[R600_PIPE_STATE_SCISSOR]);
 571         rctx->states[R600_PIPE_STATE_SCISSOR] = rstate;
 572         r600_context_pipe_state_set(&rctx->ctx, rstate);
 573 }
 574
 575 static void evergreen_set_stencil_ref(struct pipe_context *ctx,
 576                                 const struct pipe_stencil_ref *state)
 577 {
 578         struct r600_pipe_context *rctx = (struct r600_pipe_context *)ctx;
 579         struct r600_pipe_state *rstate = CALLOC_STRUCT(r600_pipe_state);
 580         u32 tmp;
 581
 582         if (rstate == NULL)
 583                 return;
 584
 585         rctx->stencil_ref = *state;
 586         rstate->id = R600_PIPE_STATE_STENCIL_REF;
 587         tmp = S_028430_STENCILREF(state->ref_value[0]);
 588         r600_pipe_state_add_reg(rstate,
 589                                 R_028430_DB_STENCILREFMASK, tmp,
 590                                 ~C_028430_STENCILREF, NULL);
 591         tmp = S_028434_STENCILREF_BF(state->ref_value[1]);
 592         r600_pipe_state_add_reg(rstate,
 593                                 R_028434_DB_STENCILREFMASK_BF, tmp,
 594                                 ~C_028434_STENCILREF_BF, NULL);
 595
 596         free(rctx->states[R600_PIPE_STATE_STENCIL_REF]);
 597         rctx->states[R600_PIPE_STATE_STENCIL_REF] = rstate;
 598         r600_context_pipe_state_set(&rctx->ctx, rstate);
 599 }
 600
 601 static void evergreen_set_viewport_state(struct pipe_context *ctx,
 602                                         const struct pipe_viewport_state *state)
 603 {
 604         struct r600_pipe_context *rctx = (struct r600_pipe_context *)ctx;
 605         struct r600_pipe_state *rstate = CALLOC_STRUCT(r600_pipe_state);
 606
 607         if (rstate == NULL)
 608                 return;
 609
 610         rctx->viewport = *state;
 611         rstate->id = R600_PIPE_STATE_VIEWPORT;
 612         r600_pipe_state_add_reg(rstate, R_0282D0_PA_SC_VPORT_ZMIN_0, 0x00000000, 0xFFFFFFFF, NULL);
 613         r600_pipe_state_add_reg(rstate, R_0282D4_PA_SC_VPORT_ZMAX_0, 0x3F800000, 0xFFFFFFFF, NULL);
 614         r600_pipe_state_add_reg(rstate, R_02843C_PA_CL_VPORT_XSCALE_0, fui(state->scale[0]), 0xFFFFFFFF, NULL);
 615         r600_pipe_state_add_reg(rstate, R_028444_PA_CL_VPORT_YSCALE_0, fui(state->scale[1]), 0xFFFFFFFF, NULL);
 616         r600_pipe_state_add_reg(rstate, R_02844C_PA_CL_VPORT_ZSCALE_0, fui(state->scale[2]), 0xFFFFFFFF, NULL);
 617         r600_pipe_state_add_reg(rstate, R_028440_PA_CL_VPORT_XOFFSET_0, fui(state->translate[0]), 0xFFFFFFFF, NULL);
 618         r600_pipe_state_add_reg(rstate, R_028448_PA_CL_VPORT_YOFFSET_0, fui(state->translate[1]), 0xFFFFFFFF, NULL);
 619         r600_pipe_state_add_reg(rstate, R_028450_PA_CL_VPORT_ZOFFSET_0, fui(state->translate[2]), 0xFFFFFFFF, NULL);
 620         r600_pipe_state_add_reg(rstate, R_028818_PA_CL_VTE_CNTL, 0x0000043F, 0xFFFFFFFF, NULL);
 621
 622         free(rctx->states[R600_PIPE_STATE_VIEWPORT]);
 623         rctx->states[R600_PIPE_STATE_VIEWPORT] = rstate;
 624         r600_context_pipe_state_set(&rctx->ctx, rstate);
 625 }
 626
 627 static void evergreen_cb(struct r600_pipe_context *rctx, struct r600_pipe_state *rstate,
 628                         const struct pipe_framebuffer_state *state, int cb)
 629 {
 630         struct r600_resource_texture *rtex;
 631         struct r600_resource *rbuffer;
 632         struct r600_surface *surf;
 633         unsigned level = state->cbufs[cb]->u.tex.level;
 634         unsigned pitch, slice;
 635         unsigned color_info;
 636         unsigned format, swap, ntype;
 637         unsigned offset;
 638         const struct util_format_description *desc;
 639         struct r600_bo *bo[3];
 640
 641         surf = (struct r600_surface *)state->cbufs[cb];
 642         rtex = (struct r600_resource_texture*)state->cbufs[cb]->texture;
 643         rbuffer = &rtex->resource;
 644         bo[0] = rbuffer->bo;
 645         bo[1] = rbuffer->bo;
 646         bo[2] = rbuffer->bo;
 647
 648         /* XXX quite sure for dx10+ hw don't need any offset hacks */
 649         offset = r600_texture_get_offset((struct r600_resource_texture *)state->cbufs[cb]->texture,
 650                                          level, state->cbufs[cb]->u.tex.first_layer);
 651         pitch = rtex->pitch_in_pixels[level] / 8 - 1;
 652         slice = rtex->pitch_in_pixels[level] * surf->aligned_height / 64 - 1;
 653         ntype = 0;
 654         desc = util_format_description(rtex->resource.base.b.format);
 655         if (desc->colorspace == UTIL_FORMAT_COLORSPACE_SRGB)
 656                 ntype = V_028C70_NUMBER_SRGB;
 657
 658         format = r600_translate_colorformat(rtex->resource.base.b.format);
 659         swap = r600_translate_colorswap(rtex->resource.base.b.format);
 660         color_info = S_028C70_FORMAT(format) |
 661                 S_028C70_COMP_SWAP(swap) |
 662                 S_028C70_BLEND_CLAMP(1) |
 663                 S_028C70_NUMBER_TYPE(ntype);
 664         if (desc->colorspace != UTIL_FORMAT_COLORSPACE_ZS)
 665                 color_info |= S_028C70_SOURCE_FORMAT(1);
 666
 667         /* FIXME handle enabling of CB beyond BASE8 which has different offset */
 668         r600_pipe_state_add_reg(rstate,
 669                                 R_028C60_CB_COLOR0_BASE + cb * 0x3C,
 670                                 (offset +  r600_bo_offset(bo[0])) >> 8, 0xFFFFFFFF, bo[0]);
 671         r600_pipe_state_add_reg(rstate,
 672                                 R_028C78_CB_COLOR0_DIM + cb * 0x3C,
 673                                 0x0, 0xFFFFFFFF, NULL);
 674         r600_pipe_state_add_reg(rstate,
 675                                 R_028C70_CB_COLOR0_INFO + cb * 0x3C,
 676                                 color_info, 0xFFFFFFFF, bo[0]);
 677         r600_pipe_state_add_reg(rstate,
 678                                 R_028C64_CB_COLOR0_PITCH + cb * 0x3C,
 679                                 S_028C64_PITCH_TILE_MAX(pitch),
 680                                 0xFFFFFFFF, NULL);
 681         r600_pipe_state_add_reg(rstate,
 682                                 R_028C68_CB_COLOR0_SLICE + cb * 0x3C,
 683                                 S_028C68_SLICE_TILE_MAX(slice),
 684                                 0xFFFFFFFF, NULL);
 685         r600_pipe_state_add_reg(rstate,
 686                                 R_028C6C_CB_COLOR0_VIEW + cb * 0x3C,
 687                                 0x00000000, 0xFFFFFFFF, NULL);
 688         r600_pipe_state_add_reg(rstate,
 689                                 R_028C74_CB_COLOR0_ATTRIB + cb * 0x3C,
 690                                 S_028C74_NON_DISP_TILING_ORDER(1),
 691                                 0xFFFFFFFF, bo[0]);
 692 }
 693
 694 static void evergreen_db(struct r600_pipe_context *rctx, struct r600_pipe_state *rstate,
 695                         const struct pipe_framebuffer_state *state)
 696 {
 697         struct r600_resource_texture *rtex;
 698         struct r600_resource *rbuffer;
 699         struct r600_surface *surf;
 700         unsigned level;
 701         unsigned pitch, slice, format, stencil_format;
 702         unsigned offset;
 703
 704         if (state->zsbuf == NULL)
 705                 return;
 706
 707         level = state->zsbuf->u.tex.level;
 708
 709         surf = (struct r600_surface *)state->zsbuf;
 710         rtex = (struct r600_resource_texture*)state->zsbuf->texture;
 711         rtex->tiled = 1;
 712         rtex->array_mode[level] = 2;
 713         rtex->tile_type = 1;
 714         rtex->depth = 1;
 715         rbuffer = &rtex->resource;
 716
 717         /* XXX quite sure for dx10+ hw don't need any offset hacks */
 718         offset = r600_texture_get_offset((struct r600_resource_texture *)state->zsbuf->texture,
 719                                          level, state->zsbuf->u.tex.first_layer);
 720         pitch = rtex->pitch_in_pixels[level] / 8 - 1;
 721         slice = rtex->pitch_in_pixels[level] * surf->aligned_height / 64 - 1;
 722         format = r600_translate_dbformat(state->zsbuf->texture->format);
 723         stencil_format = r600_translate_stencilformat(state->zsbuf->texture->format);
 724
 725         r600_pipe_state_add_reg(rstate, R_028048_DB_Z_READ_BASE,
 726                                 (offset + r600_bo_offset(rbuffer->bo)) >> 8, 0xFFFFFFFF, rbuffer->bo);
 727         r600_pipe_state_add_reg(rstate, R_028050_DB_Z_WRITE_BASE,
 728                                 (offset  + r600_bo_offset(rbuffer->bo)) >> 8, 0xFFFFFFFF, rbuffer->bo);
 729
 730         if (stencil_format) {
 731                 uint32_t stencil_offset;
 732
 733                 stencil_offset = ((surf->aligned_height * rtex->pitch_in_bytes[level]) + 255) & ~255;
 734                 r600_pipe_state_add_reg(rstate, R_02804C_DB_STENCIL_READ_BASE,
 735                                         (offset + stencil_offset + r600_bo_offset(rbuffer->bo)) >> 8, 0xFFFFFFFF, rbuffer->bo);
 736                 r600_pipe_state_add_reg(rstate, R_028054_DB_STENCIL_WRITE_BASE,
 737                                         (offset + stencil_offset + r600_bo_offset(rbuffer->bo)) >> 8, 0xFFFFFFFF, rbuffer->bo);
 738         }
 739
 740         r600_pipe_state_add_reg(rstate, R_028008_DB_DEPTH_VIEW, 0x00000000, 0xFFFFFFFF, NULL);
 741         r600_pipe_state_add_reg(rstate, R_028044_DB_STENCIL_INFO,
 742                                 S_028044_FORMAT(stencil_format), 0xFFFFFFFF, rbuffer->bo);
 743
 744         r600_pipe_state_add_reg(rstate, R_028040_DB_Z_INFO,
 745                                 S_028040_ARRAY_MODE(rtex->array_mode[level]) | S_028040_FORMAT(format),
 746                                 0xFFFFFFFF, rbuffer->bo);
 747         r600_pipe_state_add_reg(rstate, R_028058_DB_DEPTH_SIZE,
 748                                 S_028058_PITCH_TILE_MAX(pitch),
 749                                 0xFFFFFFFF, NULL);
 750         r600_pipe_state_add_reg(rstate, R_02805C_DB_DEPTH_SLICE,
 751                                 S_02805C_SLICE_TILE_MAX(slice),
 752                                 0xFFFFFFFF, NULL);
 753 }
 754
 755 static void evergreen_set_framebuffer_state(struct pipe_context *ctx,
 756                                         const struct pipe_framebuffer_state *state)
 757 {
 758         struct r600_pipe_context *rctx = (struct r600_pipe_context *)ctx;
 759         struct r600_pipe_state *rstate = CALLOC_STRUCT(r600_pipe_state);
 760         u32 shader_mask, tl, br, target_mask;
 761
 762         if (rstate == NULL)
 763                 return;
 764
 765         /* unreference old buffer and reference new one */
 766         rstate->id = R600_PIPE_STATE_FRAMEBUFFER;
 767
 768         util_copy_framebuffer_state(&rctx->framebuffer, state);
 769
 770         /* build states */
 771         for (int i = 0; i < state->nr_cbufs; i++) {
 772                 evergreen_cb(rctx, rstate, state, i);
 773         }
 774         if (state->zsbuf) {
 775                 evergreen_db(rctx, rstate, state);
 776         }
 777
 778         target_mask = 0x00000000;
 779         target_mask = 0xFFFFFFFF;
 780         shader_mask = 0;
 781         for (int i = 0; i < state->nr_cbufs; i++) {
 782                 target_mask ^= 0xf << (i * 4);
 783                 shader_mask |= 0xf << (i * 4);
 784         }
 785         tl = S_028240_TL_X(0) | S_028240_TL_Y(0);
 786         br = S_028244_BR_X(state->width) | S_028244_BR_Y(state->height);
 787
 788         r600_pipe_state_add_reg(rstate,
 789                                 R_028240_PA_SC_GENERIC_SCISSOR_TL, tl,
 790                                 0xFFFFFFFF, NULL);
 791         r600_pipe_state_add_reg(rstate,
 792                                 R_028244_PA_SC_GENERIC_SCISSOR_BR, br,
 793                                 0xFFFFFFFF, NULL);
 794         r600_pipe_state_add_reg(rstate,
 795                                 R_028250_PA_SC_VPORT_SCISSOR_0_TL, tl,
 796                                 0xFFFFFFFF, NULL);
 797         r600_pipe_state_add_reg(rstate,
 798                                 R_028254_PA_SC_VPORT_SCISSOR_0_BR, br,
 799                                 0xFFFFFFFF, NULL);
 800         r600_pipe_state_add_reg(rstate,
 801                                 R_028030_PA_SC_SCREEN_SCISSOR_TL, tl,
 802                                 0xFFFFFFFF, NULL);
 803         r600_pipe_state_add_reg(rstate,
 804                                 R_028034_PA_SC_SCREEN_SCISSOR_BR, br,
 805                                 0xFFFFFFFF, NULL);
 806         r600_pipe_state_add_reg(rstate,
 807                                 R_028204_PA_SC_WINDOW_SCISSOR_TL, tl,
 808                                 0xFFFFFFFF, NULL);
 809         r600_pipe_state_add_reg(rstate,
 810                                 R_028208_PA_SC_WINDOW_SCISSOR_BR, br,
 811                                 0xFFFFFFFF, NULL);
 812         r600_pipe_state_add_reg(rstate,
 813                                 R_028200_PA_SC_WINDOW_OFFSET, 0x00000000,
 814                                 0xFFFFFFFF, NULL);
 815         r600_pipe_state_add_reg(rstate,
 816                                 R_028230_PA_SC_EDGERULE, 0xAAAAAAAA,
 817                                 0xFFFFFFFF, NULL);
 818
 819         r600_pipe_state_add_reg(rstate, R_028238_CB_TARGET_MASK,
 820                                 0x00000000, target_mask, NULL);
 821         r600_pipe_state_add_reg(rstate, R_02823C_CB_SHADER_MASK,
 822                                 shader_mask, 0xFFFFFFFF, NULL);
 823         r600_pipe_state_add_reg(rstate, R_028C04_PA_SC_AA_CONFIG,
 824                                 0x00000000, 0xFFFFFFFF, NULL);
 825         r600_pipe_state_add_reg(rstate, R_028C1C_PA_SC_AA_SAMPLE_LOCS_MCTX,
 826                                 0x00000000, 0xFFFFFFFF, NULL);
 827
 828         free(rctx->states[R600_PIPE_STATE_FRAMEBUFFER]);
 829         rctx->states[R600_PIPE_STATE_FRAMEBUFFER] = rstate;
 830         r600_context_pipe_state_set(&rctx->ctx, rstate);
 831
 832         if (state->zsbuf) {
 833                 evergreen_polygon_offset_update(rctx);
 834         }
 835 }
 836
 837 void evergreen_init_state_functions(struct r600_pipe_context *rctx)
 838 {
 839         rctx->context.create_blend_state = evergreen_create_blend_state;
 840         rctx->context.create_depth_stencil_alpha_state = evergreen_create_dsa_state;
 841         rctx->context.create_fs_state = r600_create_shader_state;
 842         rctx->context.create_rasterizer_state = evergreen_create_rs_state;
 843         rctx->context.create_sampler_state = evergreen_create_sampler_state;
 844         rctx->context.create_sampler_view = evergreen_create_sampler_view;
 845         rctx->context.create_vertex_elements_state = r600_create_vertex_elements;
 846         rctx->context.create_vs_state = r600_create_shader_state;
 847         rctx->context.bind_blend_state = r600_bind_blend_state;
 848         rctx->context.bind_depth_stencil_alpha_state = r600_bind_state;
 849         rctx->context.bind_fragment_sampler_states = evergreen_bind_ps_sampler;
 850         rctx->context.bind_fs_state = r600_bind_ps_shader;
 851         rctx->context.bind_rasterizer_state = r600_bind_rs_state;
 852         rctx->context.bind_vertex_elements_state = r600_bind_vertex_elements;
 853         rctx->context.bind_vertex_sampler_states = evergreen_bind_vs_sampler;
 854         rctx->context.bind_vs_state = r600_bind_vs_shader;
 855         rctx->context.delete_blend_state = r600_delete_state;
 856         rctx->context.delete_depth_stencil_alpha_state = r600_delete_state;
 857         rctx->context.delete_fs_state = r600_delete_ps_shader;
 858         rctx->context.delete_rasterizer_state = r600_delete_rs_state;
 859         rctx->context.delete_sampler_state = r600_delete_state;
 860         rctx->context.delete_vertex_elements_state = r600_delete_vertex_element;
 861         rctx->context.delete_vs_state = r600_delete_vs_shader;
 862         rctx->context.set_blend_color = evergreen_set_blend_color;
 863         rctx->context.set_clip_state = evergreen_set_clip_state;
 864         rctx->context.set_constant_buffer = r600_set_constant_buffer;
 865         rctx->context.set_fragment_sampler_views = evergreen_set_ps_sampler_view;
 866         rctx->context.set_framebuffer_state = evergreen_set_framebuffer_state;
 867         rctx->context.set_polygon_stipple = evergreen_set_polygon_stipple;
 868         rctx->context.set_sample_mask = evergreen_set_sample_mask;
 869         rctx->context.set_scissor_state = evergreen_set_scissor_state;
 870         rctx->context.set_stencil_ref = evergreen_set_stencil_ref;
 871         rctx->context.set_vertex_buffers = r600_set_vertex_buffers;
 872         rctx->context.set_index_buffer = r600_set_index_buffer;
 873         rctx->context.set_vertex_sampler_views = evergreen_set_vs_sampler_view;
 874         rctx->context.set_viewport_state = evergreen_set_viewport_state;
 875         rctx->context.sampler_view_destroy = r600_sampler_view_destroy;
 876 }
 877
 878 void evergreen_init_config(struct r600_pipe_context *rctx)
 879 {
 880         struct r600_pipe_state *rstate = &rctx->config;
 881         int ps_prio;
 882         int vs_prio;
 883         int gs_prio;
 884         int es_prio;
 885         int hs_prio, cs_prio, ls_prio;
 886         int num_ps_gprs;
 887         int num_vs_gprs;
 888         int num_gs_gprs;
 889         int num_es_gprs;
 890         int num_hs_gprs;
 891         int num_ls_gprs;
 892         int num_temp_gprs;
 893         int num_ps_threads;
 894         int num_vs_threads;
 895         int num_gs_threads;
 896         int num_es_threads;
 897         int num_hs_threads;
 898         int num_ls_threads;
 899         int num_ps_stack_entries;
 900         int num_vs_stack_entries;
 901         int num_gs_stack_entries;
 902         int num_es_stack_entries;
 903         int num_hs_stack_entries;
 904         int num_ls_stack_entries;
 905         enum radeon_family family;
 906         unsigned tmp;
 907
 908         family = r600_get_family(rctx->radeon);
 909         ps_prio = 0;
 910         vs_prio = 1;
 911         gs_prio = 2;
 912         es_prio = 3;
 913         hs_prio = 0;
 914         ls_prio = 0;
 915         cs_prio = 0;
 916
 917         switch (family) {
 918         case CHIP_CEDAR:
 919         default:
 920                 num_ps_gprs = 93;
 921                 num_vs_gprs = 46;
 922                 num_temp_gprs = 4;
 923                 num_gs_gprs = 31;
 924                 num_es_gprs = 31;
 925                 num_hs_gprs = 23;
 926                 num_ls_gprs = 23;
 927                 num_ps_threads = 96;
 928                 num_vs_threads = 16;
 929                 num_gs_threads = 16;
 930                 num_es_threads = 16;
 931                 num_hs_threads = 16;
 932                 num_ls_threads = 16;
 933                 num_ps_stack_entries = 42;
 934                 num_vs_stack_entries = 42;
 935                 num_gs_stack_entries = 42;
 936                 num_es_stack_entries = 42;
 937                 num_hs_stack_entries = 42;
 938                 num_ls_stack_entries = 42;
 939                 break;
 940         case CHIP_REDWOOD:
 941                 num_ps_gprs = 93;
 942                 num_vs_gprs = 46;
 943                 num_temp_gprs = 4;
 944                 num_gs_gprs = 31;
 945                 num_es_gprs = 31;
 946                 num_hs_gprs = 23;
 947                 num_ls_gprs = 23;
 948                 num_ps_threads = 128;
 949                 num_vs_threads = 20;
 950                 num_gs_threads = 20;
 951                 num_es_threads = 20;
 952                 num_hs_threads = 20;
 953                 num_ls_threads = 20;
 954                 num_ps_stack_entries = 42;
 955                 num_vs_stack_entries = 42;
 956                 num_gs_stack_entries = 42;
 957                 num_es_stack_entries = 42;
 958                 num_hs_stack_entries = 42;
 959                 num_ls_stack_entries = 42;
 960                 break;
 961         case CHIP_JUNIPER:
 962                 num_ps_gprs = 93;
 963                 num_vs_gprs = 46;
 964                 num_temp_gprs = 4;
 965                 num_gs_gprs = 31;
 966                 num_es_gprs = 31;
 967                 num_hs_gprs = 23;
 968                 num_ls_gprs = 23;
 969                 num_ps_threads = 128;
 970                 num_vs_threads = 20;
 971                 num_gs_threads = 20;
 972                 num_es_threads = 20;
 973                 num_hs_threads = 20;
 974                 num_ls_threads = 20;
 975                 num_ps_stack_entries = 85;
 976                 num_vs_stack_entries = 85;
 977                 num_gs_stack_entries = 85;
 978                 num_es_stack_entries = 85;
 979                 num_hs_stack_entries = 85;
 980                 num_ls_stack_entries = 85;
 981                 break;
 982         case CHIP_CYPRESS:
 983         case CHIP_HEMLOCK:
 984                 num_ps_gprs = 93;
 985                 num_vs_gprs = 46;
 986                 num_temp_gprs = 4;
 987                 num_gs_gprs = 31;
 988                 num_es_gprs = 31;
 989                 num_hs_gprs = 23;
 990                 num_ls_gprs = 23;
 991                 num_ps_threads = 128;
 992                 num_vs_threads = 20;
 993                 num_gs_threads = 20;
 994                 num_es_threads = 20;
 995                 num_hs_threads = 20;
 996                 num_ls_threads = 20;
 997                 num_ps_stack_entries = 85;
 998                 num_vs_stack_entries = 85;
 999                 num_gs_stack_entries = 85;
1000                 num_es_stack_entries = 85;
1001                 num_hs_stack_entries = 85;
1002                 num_ls_stack_entries = 85;
1003                 break;
1004         case CHIP_PALM:
1005                 num_ps_gprs = 93;
1006                 num_vs_gprs = 46;
1007                 num_temp_gprs = 4;
1008                 num_gs_gprs = 31;
1009                 num_es_gprs = 31;
1010                 num_hs_gprs = 23;
1011                 num_ls_gprs = 23;
1012                 num_ps_threads = 96;
1013                 num_vs_threads = 16;
1014                 num_gs_threads = 16;
1015                 num_es_threads = 16;
1016                 num_hs_threads = 16;
1017                 num_ls_threads = 16;
1018                 num_ps_stack_entries = 42;
1019                 num_vs_stack_entries = 42;
1020                 num_gs_stack_entries = 42;
1021                 num_es_stack_entries = 42;
1022                 num_hs_stack_entries = 42;
1023                 num_ls_stack_entries = 42;
1024                 break;
1025         case CHIP_BARTS:
1026                 num_ps_gprs = 93;
1027                 num_vs_gprs = 46;
1028                 num_temp_gprs = 4;
1029                 num_gs_gprs = 31;
1030                 num_es_gprs = 31;
1031                 num_hs_gprs = 23;
1032                 num_ls_gprs = 23;
1033                 num_ps_threads = 128;
1034                 num_vs_threads = 20;
1035                 num_gs_threads = 20;
1036                 num_es_threads = 20;
1037                 num_hs_threads = 20;
1038                 num_ls_threads = 20;
1039                 num_ps_stack_entries = 85;
1040                 num_vs_stack_entries = 85;
1041                 num_gs_stack_entries = 85;
1042                 num_es_stack_entries = 85;
1043                 num_hs_stack_entries = 85;
1044                 num_ls_stack_entries = 85;
1045                 break;
1046         case CHIP_TURKS:
1047                 num_ps_gprs = 93;
1048                 num_vs_gprs = 46;
1049                 num_temp_gprs = 4;
1050                 num_gs_gprs = 31;
1051                 num_es_gprs = 31;
1052                 num_hs_gprs = 23;
1053                 num_ls_gprs = 23;
1054                 num_ps_threads = 128;
1055                 num_vs_threads = 20;
1056                 num_gs_threads = 20;
1057                 num_es_threads = 20;
1058                 num_hs_threads = 20;
1059                 num_ls_threads = 20;
1060                 num_ps_stack_entries = 42;
1061                 num_vs_stack_entries = 42;
1062                 num_gs_stack_entries = 42;
1063                 num_es_stack_entries = 42;
1064                 num_hs_stack_entries = 42;
1065                 num_ls_stack_entries = 42;
1066                 break;
1067         case CHIP_CAICOS:
1068                 num_ps_gprs = 93;
1069                 num_vs_gprs = 46;
1070                 num_temp_gprs = 4;
1071                 num_gs_gprs = 31;
1072                 num_es_gprs = 31;
1073                 num_hs_gprs = 23;
1074                 num_ls_gprs = 23;
1075                 num_ps_threads = 128;
1076                 num_vs_threads = 10;
1077                 num_gs_threads = 10;
1078                 num_es_threads = 10;
1079                 num_hs_threads = 10;
1080                 num_ls_threads = 10;
1081                 num_ps_stack_entries = 42;
1082                 num_vs_stack_entries = 42;
1083                 num_gs_stack_entries = 42;
1084                 num_es_stack_entries = 42;
1085                 num_hs_stack_entries = 42;
1086                 num_ls_stack_entries = 42;
1087                 break;
1088         }
1089
1090         tmp = 0x00000000;
1091         switch (family) {
1092         case CHIP_CEDAR:
1093         case CHIP_PALM:
1094         case CHIP_CAICOS:
1095                 break;
1096         default:
1097                 tmp |= S_008C00_VC_ENABLE(1);
1098                 break;
1099         }
1100         tmp |= S_008C00_EXPORT_SRC_C(1);
1101         tmp |= S_008C00_CS_PRIO(cs_prio);
1102         tmp |= S_008C00_LS_PRIO(ls_prio);
1103         tmp |= S_008C00_HS_PRIO(hs_prio);
1104         tmp |= S_008C00_PS_PRIO(ps_prio);
1105         tmp |= S_008C00_VS_PRIO(vs_prio);
1106         tmp |= S_008C00_GS_PRIO(gs_prio);
1107         tmp |= S_008C00_ES_PRIO(es_prio);
1108         r600_pipe_state_add_reg(rstate, R_008C00_SQ_CONFIG, tmp, 0xFFFFFFFF, NULL);
1109
1110         tmp = 0;
1111         tmp |= S_008C04_NUM_PS_GPRS(num_ps_gprs);
1112         tmp |= S_008C04_NUM_VS_GPRS(num_vs_gprs);
1113         tmp |= S_008C04_NUM_CLAUSE_TEMP_GPRS(num_temp_gprs);
1114         r600_pipe_state_add_reg(rstate, R_008C04_SQ_GPR_RESOURCE_MGMT_1, tmp, 0xFFFFFFFF, NULL);
1115
1116         tmp = 0;
1117         tmp |= S_008C08_NUM_GS_GPRS(num_gs_gprs);
1118         tmp |= S_008C08_NUM_ES_GPRS(num_es_gprs);
1119         r600_pipe_state_add_reg(rstate, R_008C08_SQ_GPR_RESOURCE_MGMT_2, tmp, 0xFFFFFFFF, NULL);
1120
1121         tmp = 0;
1122         tmp |= S_008C0C_NUM_HS_GPRS(num_hs_gprs);
1123         tmp |= S_008C0C_NUM_LS_GPRS(num_ls_gprs);
1124         r600_pipe_state_add_reg(rstate, R_008C0C_SQ_GPR_RESOURCE_MGMT_3, tmp, 0xFFFFFFFF, NULL);
1125
1126         tmp = 0;
1127         tmp |= S_008C18_NUM_PS_THREADS(num_ps_threads);
1128         tmp |= S_008C18_NUM_VS_THREADS(num_vs_threads);
1129         tmp |= S_008C18_NUM_GS_THREADS(num_gs_threads);
1130         tmp |= S_008C18_NUM_ES_THREADS(num_es_threads);
1131         r600_pipe_state_add_reg(rstate, R_008C18_SQ_THREAD_RESOURCE_MGMT_1, tmp, 0xFFFFFFFF, NULL);
1132
1133         tmp = 0;
1134         tmp |= S_008C1C_NUM_HS_THREADS(num_hs_threads);
1135         tmp |= S_008C1C_NUM_LS_THREADS(num_ls_threads);
1136         r600_pipe_state_add_reg(rstate, R_008C1C_SQ_THREAD_RESOURCE_MGMT_2, tmp, 0xFFFFFFFF, NULL);
1137
1138         tmp = 0;
1139         tmp |= S_008C20_NUM_PS_STACK_ENTRIES(num_ps_stack_entries);
1140         tmp |= S_008C20_NUM_VS_STACK_ENTRIES(num_vs_stack_entries);
1141         r600_pipe_state_add_reg(rstate, R_008C20_SQ_STACK_RESOURCE_MGMT_1, tmp, 0xFFFFFFFF, NULL);
1142
1143         tmp = 0;
1144         tmp |= S_008C24_NUM_GS_STACK_ENTRIES(num_gs_stack_entries);
1145         tmp |= S_008C24_NUM_ES_STACK_ENTRIES(num_es_stack_entries);
1146         r600_pipe_state_add_reg(rstate, R_008C24_SQ_STACK_RESOURCE_MGMT_2, tmp, 0xFFFFFFFF, NULL);
1147
1148         tmp = 0;
1149         tmp |= S_008C28_NUM_HS_STACK_ENTRIES(num_hs_stack_entries);
1150         tmp |= S_008C28_NUM_LS_STACK_ENTRIES(num_ls_stack_entries);
1151         r600_pipe_state_add_reg(rstate, R_008C28_SQ_STACK_RESOURCE_MGMT_3, tmp, 0xFFFFFFFF, NULL);
1152
1153         r600_pipe_state_add_reg(rstate, R_009100_SPI_CONFIG_CNTL, 0x0, 0xFFFFFFFF, NULL);
1154         r600_pipe_state_add_reg(rstate, R_00913C_SPI_CONFIG_CNTL_1, S_00913C_VTX_DONE_DELAY(4), 0xFFFFFFFF, NULL);
1155
1156 //      r600_pipe_state_add_reg(rstate, R_028350_SX_MISC, 0x0, 0xFFFFFFFF, NULL);
1157
1158 //      r600_pipe_state_add_reg(rstate, R_008D8C_SQ_DYN_GPR_CNTL_PS_FLUSH_REQ, 0x0, 0xFFFFFFFF, NULL);
1159         r600_pipe_state_add_reg(rstate, R_028A48_PA_SC_MODE_CNTL_0, 0x0, 0xFFFFFFFF, NULL);
1160         r600_pipe_state_add_reg(rstate, R_028A4C_PA_SC_MODE_CNTL_1, 0x0, 0xFFFFFFFF, NULL);
1161
1162         r600_pipe_state_add_reg(rstate, R_028900_SQ_ESGS_RING_ITEMSIZE, 0x0, 0xFFFFFFFF, NULL);
1163         r600_pipe_state_add_reg(rstate, R_028904_SQ_GSVS_RING_ITEMSIZE, 0x0, 0xFFFFFFFF, NULL);
1164         r600_pipe_state_add_reg(rstate, R_028908_SQ_ESTMP_RING_ITEMSIZE, 0x0, 0xFFFFFFFF, NULL);
1165         r600_pipe_state_add_reg(rstate, R_02890C_SQ_GSTMP_RING_ITEMSIZE, 0x0, 0xFFFFFFFF, NULL);
1166         r600_pipe_state_add_reg(rstate, R_028910_SQ_VSTMP_RING_ITEMSIZE, 0x0, 0xFFFFFFFF, NULL);
1167         r600_pipe_state_add_reg(rstate, R_028914_SQ_PSTMP_RING_ITEMSIZE, 0x0, 0xFFFFFFFF, NULL);
1168
1169         r600_pipe_state_add_reg(rstate, R_02891C_SQ_GS_VERT_ITEMSIZE, 0x0, 0xFFFFFFFF, NULL);
1170         r600_pipe_state_add_reg(rstate, R_028920_SQ_GS_VERT_ITEMSIZE_1, 0x0, 0xFFFFFFFF, NULL);
1171         r600_pipe_state_add_reg(rstate, R_028924_SQ_GS_VERT_ITEMSIZE_2, 0x0, 0xFFFFFFFF, NULL);
1172         r600_pipe_state_add_reg(rstate, R_028928_SQ_GS_VERT_ITEMSIZE_3, 0x0, 0xFFFFFFFF, NULL);
1173
1174         r600_pipe_state_add_reg(rstate, R_028A10_VGT_OUTPUT_PATH_CNTL, 0x0, 0xFFFFFFFF, NULL);
1175         r600_pipe_state_add_reg(rstate, R_028A14_VGT_HOS_CNTL, 0x0, 0xFFFFFFFF, NULL);
1176         r600_pipe_state_add_reg(rstate, R_028A18_VGT_HOS_MAX_TESS_LEVEL, 0x0, 0xFFFFFFFF, NULL);
1177         r600_pipe_state_add_reg(rstate, R_028A1C_VGT_HOS_MIN_TESS_LEVEL, 0x0, 0xFFFFFFFF, NULL);
1178         r600_pipe_state_add_reg(rstate, R_028A20_VGT_HOS_REUSE_DEPTH, 0x0, 0xFFFFFFFF, NULL);
1179         r600_pipe_state_add_reg(rstate, R_028A24_VGT_GROUP_PRIM_TYPE, 0x0, 0xFFFFFFFF, NULL);
1180         r600_pipe_state_add_reg(rstate, R_028A28_VGT_GROUP_FIRST_DECR, 0x0, 0xFFFFFFFF, NULL);
1181         r600_pipe_state_add_reg(rstate, R_028A2C_VGT_GROUP_DECR, 0x0, 0xFFFFFFFF, NULL);
1182         r600_pipe_state_add_reg(rstate, R_028A30_VGT_GROUP_VECT_0_CNTL, 0x0, 0xFFFFFFFF, NULL);
1183         r600_pipe_state_add_reg(rstate, R_028A34_VGT_GROUP_VECT_1_CNTL, 0x0, 0xFFFFFFFF, NULL);
1184         r600_pipe_state_add_reg(rstate, R_028A38_VGT_GROUP_VECT_0_FMT_CNTL, 0x0, 0xFFFFFFFF, NULL);
1185         r600_pipe_state_add_reg(rstate, R_028A3C_VGT_GROUP_VECT_1_FMT_CNTL, 0x0, 0xFFFFFFFF, NULL);
1186         r600_pipe_state_add_reg(rstate, R_028A40_VGT_GS_MODE, 0x0, 0xFFFFFFFF, NULL);
1187         r600_pipe_state_add_reg(rstate, R_028B94_VGT_STRMOUT_CONFIG, 0x0, 0xFFFFFFFF, NULL);
1188         r600_pipe_state_add_reg(rstate, R_028B98_VGT_STRMOUT_BUFFER_CONFIG, 0x0, 0xFFFFFFFF, NULL);
1189         r600_pipe_state_add_reg(rstate, R_028AB4_VGT_REUSE_OFF, 0x00000000, 0xFFFFFFFF, NULL);
1190         r600_pipe_state_add_reg(rstate, R_028AB8_VGT_VTX_CNT_EN, 0x0, 0xFFFFFFFF, NULL);
1191         r600_pipe_state_add_reg(rstate, R_008A14_PA_CL_ENHANCE, (3 << 1) | 1, 0xFFFFFFFF, NULL);
1192
1193         r600_pipe_state_add_reg(rstate, R_028380_SQ_VTX_SEMANTIC_0, 0x0, 0xFFFFFFFF, NULL);
1194         r600_pipe_state_add_reg(rstate, R_028384_SQ_VTX_SEMANTIC_1, 0x0, 0xFFFFFFFF, NULL);
1195         r600_pipe_state_add_reg(rstate, R_028388_SQ_VTX_SEMANTIC_2, 0x0, 0xFFFFFFFF, NULL);
1196         r600_pipe_state_add_reg(rstate, R_02838C_SQ_VTX_SEMANTIC_3, 0x0, 0xFFFFFFFF, NULL);
1197         r600_pipe_state_add_reg(rstate, R_028390_SQ_VTX_SEMANTIC_4, 0x0, 0xFFFFFFFF, NULL);
1198         r600_pipe_state_add_reg(rstate, R_028394_SQ_VTX_SEMANTIC_5, 0x0, 0xFFFFFFFF, NULL);
1199         r600_pipe_state_add_reg(rstate, R_028398_SQ_VTX_SEMANTIC_6, 0x0, 0xFFFFFFFF, NULL);
1200         r600_pipe_state_add_reg(rstate, R_02839C_SQ_VTX_SEMANTIC_7, 0x0, 0xFFFFFFFF, NULL);
1201         r600_pipe_state_add_reg(rstate, R_0283A0_SQ_VTX_SEMANTIC_8, 0x0, 0xFFFFFFFF, NULL);
1202         r600_pipe_state_add_reg(rstate, R_0283A4_SQ_VTX_SEMANTIC_9, 0x0, 0xFFFFFFFF, NULL);
1203         r600_pipe_state_add_reg(rstate, R_0283A8_SQ_VTX_SEMANTIC_10, 0x0, 0xFFFFFFFF, NULL);
1204         r600_pipe_state_add_reg(rstate, R_0283AC_SQ_VTX_SEMANTIC_11, 0x0, 0xFFFFFFFF, NULL);
1205         r600_pipe_state_add_reg(rstate, R_0283B0_SQ_VTX_SEMANTIC_12, 0x0, 0xFFFFFFFF, NULL);
1206         r600_pipe_state_add_reg(rstate, R_0283B4_SQ_VTX_SEMANTIC_13, 0x0, 0xFFFFFFFF, NULL);
1207         r600_pipe_state_add_reg(rstate, R_0283B8_SQ_VTX_SEMANTIC_14, 0x0, 0xFFFFFFFF, NULL);
1208         r600_pipe_state_add_reg(rstate, R_0283BC_SQ_VTX_SEMANTIC_15, 0x0, 0xFFFFFFFF, NULL);
1209         r600_pipe_state_add_reg(rstate, R_0283C0_SQ_VTX_SEMANTIC_16, 0x0, 0xFFFFFFFF, NULL);
1210         r600_pipe_state_add_reg(rstate, R_0283C4_SQ_VTX_SEMANTIC_17, 0x0, 0xFFFFFFFF, NULL);
1211         r600_pipe_state_add_reg(rstate, R_0283C8_SQ_VTX_SEMANTIC_18, 0x0, 0xFFFFFFFF, NULL);
1212         r600_pipe_state_add_reg(rstate, R_0283CC_SQ_VTX_SEMANTIC_19, 0x0, 0xFFFFFFFF, NULL);
1213         r600_pipe_state_add_reg(rstate, R_0283D0_SQ_VTX_SEMANTIC_20, 0x0, 0xFFFFFFFF, NULL);
1214         r600_pipe_state_add_reg(rstate, R_0283D4_SQ_VTX_SEMANTIC_21, 0x0, 0xFFFFFFFF, NULL);
1215         r600_pipe_state_add_reg(rstate, R_0283D8_SQ_VTX_SEMANTIC_22, 0x0, 0xFFFFFFFF, NULL);
1216         r600_pipe_state_add_reg(rstate, R_0283DC_SQ_VTX_SEMANTIC_23, 0x0, 0xFFFFFFFF, NULL);
1217         r600_pipe_state_add_reg(rstate, R_0283E0_SQ_VTX_SEMANTIC_24, 0x0, 0xFFFFFFFF, NULL);
1218         r600_pipe_state_add_reg(rstate, R_0283E4_SQ_VTX_SEMANTIC_25, 0x0, 0xFFFFFFFF, NULL);
1219         r600_pipe_state_add_reg(rstate, R_0283E8_SQ_VTX_SEMANTIC_26, 0x0, 0xFFFFFFFF, NULL);
1220         r600_pipe_state_add_reg(rstate, R_0283EC_SQ_VTX_SEMANTIC_27, 0x0, 0xFFFFFFFF, NULL);
1221         r600_pipe_state_add_reg(rstate, R_0283F0_SQ_VTX_SEMANTIC_28, 0x0, 0xFFFFFFFF, NULL);
1222         r600_pipe_state_add_reg(rstate, R_0283F4_SQ_VTX_SEMANTIC_29, 0x0, 0xFFFFFFFF, NULL);
1223         r600_pipe_state_add_reg(rstate, R_0283F8_SQ_VTX_SEMANTIC_30, 0x0, 0xFFFFFFFF, NULL);
1224         r600_pipe_state_add_reg(rstate, R_0283FC_SQ_VTX_SEMANTIC_31, 0x0, 0xFFFFFFFF, NULL);
1225
1226         r600_pipe_state_add_reg(rstate, R_028810_PA_CL_CLIP_CNTL, 0x0, 0xFFFFFFFF, NULL);
1227
1228         r600_context_pipe_state_set(&rctx->ctx, rstate);
1229 }
1230
1231 void evergreen_polygon_offset_update(struct r600_pipe_context *rctx)
1232 {
1233         struct r600_pipe_state state;
1234
1235         state.id = R600_PIPE_STATE_POLYGON_OFFSET;
1236         state.nregs = 0;
1237         if (rctx->rasterizer && rctx->framebuffer.zsbuf) {
1238                 float offset_units = rctx->rasterizer->offset_units;
1239                 unsigned offset_db_fmt_cntl = 0, depth;
1240
1241                 switch (rctx->framebuffer.zsbuf->texture->format) {
1242                 case PIPE_FORMAT_Z24X8_UNORM:
1243                 case PIPE_FORMAT_Z24_UNORM_S8_USCALED:
1244                         depth = -24;
1245                         offset_units *= 2.0f;
1246                         break;
1247                 case PIPE_FORMAT_Z32_FLOAT:
1248                         depth = -23;
1249                         offset_units *= 1.0f;
1250                         offset_db_fmt_cntl |= S_028B78_POLY_OFFSET_DB_IS_FLOAT_FMT(1);
1251                         break;
1252                 case PIPE_FORMAT_Z16_UNORM:
1253                         depth = -16;
1254                         offset_units *= 4.0f;
1255                         break;
1256                 default:
1257                         return;
1258                 }
1259                 /* FIXME some of those reg can be computed with cso */
1260                 offset_db_fmt_cntl |= S_028B78_POLY_OFFSET_NEG_NUM_DB_BITS(depth);
1261                 r600_pipe_state_add_reg(&state,
1262                                 R_028B80_PA_SU_POLY_OFFSET_FRONT_SCALE,
1263                                 fui(rctx->rasterizer->offset_scale), 0xFFFFFFFF, NULL);
1264                 r600_pipe_state_add_reg(&state,
1265                                 R_028B84_PA_SU_POLY_OFFSET_FRONT_OFFSET,
1266                                 fui(offset_units), 0xFFFFFFFF, NULL);
1267                 r600_pipe_state_add_reg(&state,
1268                                 R_028B88_PA_SU_POLY_OFFSET_BACK_SCALE,
1269                                 fui(rctx->rasterizer->offset_scale), 0xFFFFFFFF, NULL);
1270                 r600_pipe_state_add_reg(&state,
1271                                 R_028B8C_PA_SU_POLY_OFFSET_BACK_OFFSET,
1272                                 fui(offset_units), 0xFFFFFFFF, NULL);
1273                 r600_pipe_state_add_reg(&state,
1274                                 R_028B78_PA_SU_POLY_OFFSET_DB_FMT_CNTL,
1275                                 offset_db_fmt_cntl, 0xFFFFFFFF, NULL);
1276                 r600_context_pipe_state_set(&rctx->ctx, &state);
1277         }
1278 }
1279
1280 void evergreen_pipe_shader_ps(struct pipe_context *ctx, struct r600_pipe_shader *shader)
1281 {
1282         struct r600_pipe_state *rstate = &shader->rstate;
1283         struct r600_shader *rshader = &shader->shader;
1284         unsigned i, exports_ps, num_cout, spi_ps_in_control_0, spi_input_z, spi_ps_in_control_1;
1285         int pos_index = -1, face_index = -1;
1286         int ninterp = 0;
1287         boolean have_linear = FALSE, have_centroid = FALSE, have_perspective = FALSE;
1288         unsigned spi_baryc_cntl;
1289
1290         rstate->nregs = 0;
1291
1292         for (i = 0; i < rshader->ninput; i++) {
1293                 /* evergreen NUM_INTERP only contains values interpolated into the LDS,
1294                    POSITION goes via GPRs from the SC so isn't counted */
1295                 if (rshader->input[i].name == TGSI_SEMANTIC_POSITION)
1296                         pos_index = i;
1297                 else if (rshader->input[i].name == TGSI_SEMANTIC_FACE)
1298                         face_index = i;
1299                 else {
1300                         if (rshader->input[i].interpolate == TGSI_INTERPOLATE_LINEAR ||
1301                             rshader->input[i].interpolate == TGSI_INTERPOLATE_PERSPECTIVE)
1302                                 ninterp++;
1303                         if (rshader->input[i].interpolate == TGSI_INTERPOLATE_LINEAR)
1304                                 have_linear = TRUE;
1305                         if (rshader->input[i].interpolate == TGSI_INTERPOLATE_PERSPECTIVE)
1306                                 have_perspective = TRUE;
1307                         if (rshader->input[i].centroid)
1308                                 have_centroid = TRUE;
1309                 }
1310         }
1311         for (i = 0; i < rshader->noutput; i++) {
1312                 if (rshader->output[i].name == TGSI_SEMANTIC_POSITION)
1313                         r600_pipe_state_add_reg(rstate,
1314                                                 R_02880C_DB_SHADER_CONTROL,
1315                                                 S_02880C_Z_EXPORT_ENABLE(1),
1316                                                 S_02880C_Z_EXPORT_ENABLE(1), NULL);
1317                 if (rshader->output[i].name == TGSI_SEMANTIC_STENCIL)
1318                         r600_pipe_state_add_reg(rstate,
1319                                                 R_02880C_DB_SHADER_CONTROL,
1320                                                 S_02880C_STENCIL_EXPORT_ENABLE(1),
1321                                                 S_02880C_STENCIL_EXPORT_ENABLE(1), NULL);
1322         }
1323
1324         exports_ps = 0;
1325         num_cout = 0;
1326         for (i = 0; i < rshader->noutput; i++) {
1327                 if (rshader->output[i].name == TGSI_SEMANTIC_POSITION ||
1328                     rshader->output[i].name == TGSI_SEMANTIC_STENCIL)
1329                         exports_ps |= 1;
1330                 else if (rshader->output[i].name == TGSI_SEMANTIC_COLOR) {
1331                         num_cout++;
1332                 }
1333         }
1334         exports_ps |= S_02884C_EXPORT_COLORS(num_cout);
1335         if (!exports_ps) {
1336                 /* always at least export 1 component per pixel */
1337                 exports_ps = 2;
1338         }
1339
1340         if (ninterp == 0) {
1341                 ninterp = 1;
1342                 have_perspective = TRUE;
1343         }
1344
1345         spi_ps_in_control_0 = S_0286CC_NUM_INTERP(ninterp) |
1346                               S_0286CC_PERSP_GRADIENT_ENA(have_perspective) |
1347                               S_0286CC_LINEAR_GRADIENT_ENA(have_linear);
1348         spi_input_z = 0;
1349         if (pos_index != -1) {
1350                 spi_ps_in_control_0 |=  S_0286CC_POSITION_ENA(1) |
1351                         S_0286CC_POSITION_CENTROID(rshader->input[pos_index].centroid) |
1352                         S_0286CC_POSITION_ADDR(rshader->input[pos_index].gpr);
1353                 spi_input_z |= 1;
1354         }
1355
1356         spi_ps_in_control_1 = 0;
1357         if (face_index != -1) {
1358                 spi_ps_in_control_1 |= S_0286D0_FRONT_FACE_ENA(1) |
1359                         S_0286D0_FRONT_FACE_ADDR(rshader->input[face_index].gpr);
1360         }
1361
1362         spi_baryc_cntl = 0;
1363         if (have_perspective)
1364                 spi_baryc_cntl |= S_0286E0_PERSP_CENTER_ENA(1) |
1365                                   S_0286E0_PERSP_CENTROID_ENA(have_centroid);
1366         if (have_linear)
1367                 spi_baryc_cntl |= S_0286E0_LINEAR_CENTER_ENA(1) |
1368                                   S_0286E0_LINEAR_CENTROID_ENA(have_centroid);
1369
1370         r600_pipe_state_add_reg(rstate, R_0286CC_SPI_PS_IN_CONTROL_0,
1371                                 spi_ps_in_control_0, 0xFFFFFFFF, NULL);
1372         r600_pipe_state_add_reg(rstate, R_0286D0_SPI_PS_IN_CONTROL_1,
1373                                 spi_ps_in_control_1, 0xFFFFFFFF, NULL);
1374         r600_pipe_state_add_reg(rstate, R_0286E4_SPI_PS_IN_CONTROL_2,
1375                                 0, 0xFFFFFFFF, NULL);
1376         r600_pipe_state_add_reg(rstate, R_0286D8_SPI_INPUT_Z, spi_input_z, 0xFFFFFFFF, NULL);
1377         r600_pipe_state_add_reg(rstate,
1378                                 R_0286E0_SPI_BARYC_CNTL,
1379                                 spi_baryc_cntl,
1380                                 0xFFFFFFFF, NULL);
1381
1382         r600_pipe_state_add_reg(rstate,
1383                                 R_028840_SQ_PGM_START_PS,
1384                                 (r600_bo_offset(shader->bo)) >> 8, 0xFFFFFFFF, shader->bo);
1385         r600_pipe_state_add_reg(rstate,
1386                                 R_028844_SQ_PGM_RESOURCES_PS,
1387                                 S_028844_NUM_GPRS(rshader->bc.ngpr) |
1388                                 S_028844_PRIME_CACHE_ON_DRAW(1) |
1389                                 S_028844_STACK_SIZE(rshader->bc.nstack),
1390                                 0xFFFFFFFF, NULL);
1391         r600_pipe_state_add_reg(rstate,
1392                                 R_028848_SQ_PGM_RESOURCES_2_PS,
1393                                 0x0, 0xFFFFFFFF, NULL);
1394         r600_pipe_state_add_reg(rstate,
1395                                 R_02884C_SQ_PGM_EXPORTS_PS,
1396                                 exports_ps, 0xFFFFFFFF, NULL);
1397
1398         if (rshader->uses_kill) {
1399                 /* only set some bits here, the other bits are set in the dsa state */
1400                 r600_pipe_state_add_reg(rstate,
1401                                         R_02880C_DB_SHADER_CONTROL,
1402                                         S_02880C_KILL_ENABLE(1),
1403                                         S_02880C_KILL_ENABLE(1), NULL);
1404         }
1405
1406         r600_pipe_state_add_reg(rstate,
1407                                 R_03A200_SQ_LOOP_CONST_0, 0x01000FFF,
1408                                 0xFFFFFFFF, NULL);
1409 }
1410
1411 void evergreen_pipe_shader_vs(struct pipe_context *ctx, struct r600_pipe_shader *shader)
1412 {
1413         struct r600_pipe_state *rstate = &shader->rstate;
1414         struct r600_shader *rshader = &shader->shader;
1415         unsigned spi_vs_out_id[10];
1416         unsigned i, tmp;
1417
1418         /* clear previous register */
1419         rstate->nregs = 0;
1420
1421         /* so far never got proper semantic id from tgsi */
1422         for (i = 0; i < 10; i++) {
1423                 spi_vs_out_id[i] = 0;
1424         }
1425         for (i = 0; i < 32; i++) {
1426                 tmp = i << ((i & 3) * 8);
1427                 spi_vs_out_id[i / 4] |= tmp;
1428         }
1429         for (i = 0; i < 10; i++) {
1430                 r600_pipe_state_add_reg(rstate,
1431                                         R_02861C_SPI_VS_OUT_ID_0 + i * 4,
1432                                         spi_vs_out_id[i], 0xFFFFFFFF, NULL);
1433         }
1434
1435         r600_pipe_state_add_reg(rstate,
1436                         R_0286C4_SPI_VS_OUT_CONFIG,
1437                         S_0286C4_VS_EXPORT_COUNT(rshader->noutput - 2),
1438                         0xFFFFFFFF, NULL);
1439         r600_pipe_state_add_reg(rstate,
1440                         R_028860_SQ_PGM_RESOURCES_VS,
1441                         S_028860_NUM_GPRS(rshader->bc.ngpr) |
1442                         S_028860_STACK_SIZE(rshader->bc.nstack),
1443                         0xFFFFFFFF, NULL);
1444         r600_pipe_state_add_reg(rstate,
1445                                 R_028864_SQ_PGM_RESOURCES_2_VS,
1446                                 0x0, 0xFFFFFFFF, NULL);
1447         r600_pipe_state_add_reg(rstate,
1448                         R_02885C_SQ_PGM_START_VS,
1449                         (r600_bo_offset(shader->bo)) >> 8, 0xFFFFFFFF, shader->bo);
1450
1451         r600_pipe_state_add_reg(rstate,
1452                                 R_03A200_SQ_LOOP_CONST_0 + (32 * 4), 0x01000FFF,
1453                                 0xFFFFFFFF, NULL);
1454 }
1455
1456 void *evergreen_create_db_flush_dsa(struct r600_pipe_context *rctx)
1457 {
1458         struct pipe_depth_stencil_alpha_state dsa;
1459         struct r600_pipe_state *rstate;
1460
1461         memset(&dsa, 0, sizeof(dsa));
1462
1463         rstate = rctx->context.create_depth_stencil_alpha_state(&rctx->context, &dsa);
1464         r600_pipe_state_add_reg(rstate,
1465                                 R_02880C_DB_SHADER_CONTROL,
1466                                 0x0,
1467                                 S_02880C_DUAL_EXPORT_ENABLE(1), NULL);
1468         r600_pipe_state_add_reg(rstate,
1469                                 R_028000_DB_RENDER_CONTROL,
1470                                 S_028000_DEPTH_COPY_ENABLE(1) |
1471                                 S_028000_STENCIL_COPY_ENABLE(1) |
1472                                 S_028000_COPY_CENTROID(1),
1473                                 S_028000_DEPTH_COPY_ENABLE(1) |
1474                                 S_028000_STENCIL_COPY_ENABLE(1) |
1475                                 S_028000_COPY_CENTROID(1), NULL);
1476         return rstate;
1477 }
1478
1479 void evergreen_pipe_add_vertex_attrib(struct r600_pipe_context *rctx,
1480                                       struct r600_pipe_state *rstate,
1481                                       unsigned index,
1482                                       struct r600_resource *rbuffer,
1483                                       unsigned offset, unsigned stride)
1484 {
1485         r600_pipe_state_add_reg(rstate, R_030000_RESOURCE0_WORD0,
1486                                 offset, 0xFFFFFFFF, rbuffer->bo);
1487         r600_pipe_state_add_reg(rstate, R_030004_RESOURCE0_WORD1,
1488                                 rbuffer->bo_size - offset - 1, 0xFFFFFFFF, NULL);
1489         r600_pipe_state_add_reg(rstate, R_030008_RESOURCE0_WORD2,
1490                                 S_030008_STRIDE(stride),
1491                                 0xFFFFFFFF, NULL);
1492         r600_pipe_state_add_reg(rstate, R_03000C_RESOURCE0_WORD3,
1493                                 S_03000C_DST_SEL_X(V_03000C_SQ_SEL_X) |
1494                                 S_03000C_DST_SEL_Y(V_03000C_SQ_SEL_Y) |
1495                                 S_03000C_DST_SEL_Z(V_03000C_SQ_SEL_Z) |
1496                                 S_03000C_DST_SEL_W(V_03000C_SQ_SEL_W),
1497                                 0xFFFFFFFF, NULL);
1498         r600_pipe_state_add_reg(rstate, R_030010_RESOURCE0_WORD4,
1499                                 0x00000000, 0xFFFFFFFF, NULL);
1500         r600_pipe_state_add_reg(rstate, R_030014_RESOURCE0_WORD5,
1501                                 0x00000000, 0xFFFFFFFF, NULL);
1502         r600_pipe_state_add_reg(rstate, R_030018_RESOURCE0_WORD6,
1503                                 0x00000000, 0xFFFFFFFF, NULL);
1504         r600_pipe_state_add_reg(rstate, R_03001C_RESOURCE0_WORD7,
1505                                 0xC0000000, 0xFFFFFFFF, NULL);
1506         evergreen_context_pipe_state_set_fs_resource(&rctx->ctx, rstate, index);
1507 }